Commit | Line | Data |
---|---|---|
d129bceb | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver |
d129bceb | 3 | * |
b69c9058 | 4 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
d129bceb PO |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
643f720c PO |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or (at | |
9 | * your option) any later version. | |
84c46a53 PO |
10 | * |
11 | * Thanks to the following companies for their support: | |
12 | * | |
13 | * - JMicron (hardware and technical support) | |
d129bceb PO |
14 | */ |
15 | ||
d129bceb PO |
16 | #include <linux/delay.h> |
17 | #include <linux/highmem.h> | |
b8c86fc5 | 18 | #include <linux/io.h> |
d129bceb | 19 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
11763609 | 21 | #include <linux/scatterlist.h> |
9bea3c85 | 22 | #include <linux/regulator/consumer.h> |
d129bceb | 23 | |
2f730fec PO |
24 | #include <linux/leds.h> |
25 | ||
22113efd | 26 | #include <linux/mmc/mmc.h> |
d129bceb | 27 | #include <linux/mmc/host.h> |
d129bceb | 28 | |
d129bceb PO |
29 | #include "sdhci.h" |
30 | ||
31 | #define DRIVER_NAME "sdhci" | |
d129bceb | 32 | |
d129bceb | 33 | #define DBG(f, x...) \ |
c6563178 | 34 | pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) |
d129bceb | 35 | |
f9134319 PO |
36 | #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ |
37 | defined(CONFIG_MMC_SDHCI_MODULE)) | |
38 | #define SDHCI_USE_LEDS_CLASS | |
39 | #endif | |
40 | ||
df673b22 | 41 | static unsigned int debug_quirks = 0; |
67435274 | 42 | |
d129bceb PO |
43 | static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *); |
44 | static void sdhci_finish_data(struct sdhci_host *); | |
45 | ||
46 | static void sdhci_send_command(struct sdhci_host *, struct mmc_command *); | |
47 | static void sdhci_finish_command(struct sdhci_host *); | |
48 | ||
49 | static void sdhci_dumpregs(struct sdhci_host *host) | |
50 | { | |
412ab659 PR |
51 | printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", |
52 | mmc_hostname(host->mmc)); | |
d129bceb PO |
53 | |
54 | printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", | |
4e4141a5 AV |
55 | sdhci_readl(host, SDHCI_DMA_ADDRESS), |
56 | sdhci_readw(host, SDHCI_HOST_VERSION)); | |
d129bceb | 57 | printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", |
4e4141a5 AV |
58 | sdhci_readw(host, SDHCI_BLOCK_SIZE), |
59 | sdhci_readw(host, SDHCI_BLOCK_COUNT)); | |
d129bceb | 60 | printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", |
4e4141a5 AV |
61 | sdhci_readl(host, SDHCI_ARGUMENT), |
62 | sdhci_readw(host, SDHCI_TRANSFER_MODE)); | |
d129bceb | 63 | printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", |
4e4141a5 AV |
64 | sdhci_readl(host, SDHCI_PRESENT_STATE), |
65 | sdhci_readb(host, SDHCI_HOST_CONTROL)); | |
d129bceb | 66 | printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", |
4e4141a5 AV |
67 | sdhci_readb(host, SDHCI_POWER_CONTROL), |
68 | sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); | |
d129bceb | 69 | printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", |
4e4141a5 AV |
70 | sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), |
71 | sdhci_readw(host, SDHCI_CLOCK_CONTROL)); | |
d129bceb | 72 | printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", |
4e4141a5 AV |
73 | sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), |
74 | sdhci_readl(host, SDHCI_INT_STATUS)); | |
d129bceb | 75 | printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", |
4e4141a5 AV |
76 | sdhci_readl(host, SDHCI_INT_ENABLE), |
77 | sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); | |
d129bceb | 78 | printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", |
4e4141a5 AV |
79 | sdhci_readw(host, SDHCI_ACMD12_ERR), |
80 | sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); | |
e8120ad1 | 81 | printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", |
4e4141a5 | 82 | sdhci_readl(host, SDHCI_CAPABILITIES), |
e8120ad1 PR |
83 | sdhci_readl(host, SDHCI_CAPABILITIES_1)); |
84 | printk(KERN_DEBUG DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", | |
85 | sdhci_readw(host, SDHCI_COMMAND), | |
4e4141a5 | 86 | sdhci_readl(host, SDHCI_MAX_CURRENT)); |
d129bceb | 87 | |
be3f4ae0 BD |
88 | if (host->flags & SDHCI_USE_ADMA) |
89 | printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", | |
90 | readl(host->ioaddr + SDHCI_ADMA_ERROR), | |
91 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); | |
92 | ||
d129bceb PO |
93 | printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n"); |
94 | } | |
95 | ||
96 | /*****************************************************************************\ | |
97 | * * | |
98 | * Low level functions * | |
99 | * * | |
100 | \*****************************************************************************/ | |
101 | ||
7260cf5e AV |
102 | static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) |
103 | { | |
104 | u32 ier; | |
105 | ||
106 | ier = sdhci_readl(host, SDHCI_INT_ENABLE); | |
107 | ier &= ~clear; | |
108 | ier |= set; | |
109 | sdhci_writel(host, ier, SDHCI_INT_ENABLE); | |
110 | sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); | |
111 | } | |
112 | ||
113 | static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs) | |
114 | { | |
115 | sdhci_clear_set_irqs(host, 0, irqs); | |
116 | } | |
117 | ||
118 | static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs) | |
119 | { | |
120 | sdhci_clear_set_irqs(host, irqs, 0); | |
121 | } | |
122 | ||
123 | static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) | |
124 | { | |
125 | u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; | |
126 | ||
68d1fb7e AV |
127 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) |
128 | return; | |
129 | ||
7260cf5e AV |
130 | if (enable) |
131 | sdhci_unmask_irqs(host, irqs); | |
132 | else | |
133 | sdhci_mask_irqs(host, irqs); | |
134 | } | |
135 | ||
136 | static void sdhci_enable_card_detection(struct sdhci_host *host) | |
137 | { | |
138 | sdhci_set_card_detection(host, true); | |
139 | } | |
140 | ||
141 | static void sdhci_disable_card_detection(struct sdhci_host *host) | |
142 | { | |
143 | sdhci_set_card_detection(host, false); | |
144 | } | |
145 | ||
d129bceb PO |
146 | static void sdhci_reset(struct sdhci_host *host, u8 mask) |
147 | { | |
e16514d8 | 148 | unsigned long timeout; |
063a9dbb | 149 | u32 uninitialized_var(ier); |
e16514d8 | 150 | |
b8c86fc5 | 151 | if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { |
4e4141a5 | 152 | if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & |
8a4da143 PO |
153 | SDHCI_CARD_PRESENT)) |
154 | return; | |
155 | } | |
156 | ||
063a9dbb AV |
157 | if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) |
158 | ier = sdhci_readl(host, SDHCI_INT_ENABLE); | |
159 | ||
4e4141a5 | 160 | sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); |
d129bceb | 161 | |
e16514d8 | 162 | if (mask & SDHCI_RESET_ALL) |
d129bceb PO |
163 | host->clock = 0; |
164 | ||
e16514d8 PO |
165 | /* Wait max 100 ms */ |
166 | timeout = 100; | |
167 | ||
168 | /* hw clears the bit when it's done */ | |
4e4141a5 | 169 | while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { |
e16514d8 | 170 | if (timeout == 0) { |
acf1da45 | 171 | printk(KERN_ERR "%s: Reset 0x%x never completed.\n", |
e16514d8 PO |
172 | mmc_hostname(host->mmc), (int)mask); |
173 | sdhci_dumpregs(host); | |
174 | return; | |
175 | } | |
176 | timeout--; | |
177 | mdelay(1); | |
d129bceb | 178 | } |
063a9dbb AV |
179 | |
180 | if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) | |
181 | sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier); | |
d129bceb PO |
182 | } |
183 | ||
2f4cbb3d NP |
184 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); |
185 | ||
186 | static void sdhci_init(struct sdhci_host *host, int soft) | |
d129bceb | 187 | { |
2f4cbb3d NP |
188 | if (soft) |
189 | sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); | |
190 | else | |
191 | sdhci_reset(host, SDHCI_RESET_ALL); | |
d129bceb | 192 | |
7260cf5e AV |
193 | sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, |
194 | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | | |
3192a28f PO |
195 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | |
196 | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | | |
6aa943ab | 197 | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE); |
2f4cbb3d NP |
198 | |
199 | if (soft) { | |
200 | /* force clock reconfiguration */ | |
201 | host->clock = 0; | |
202 | sdhci_set_ios(host->mmc, &host->mmc->ios); | |
203 | } | |
7260cf5e | 204 | } |
d129bceb | 205 | |
7260cf5e AV |
206 | static void sdhci_reinit(struct sdhci_host *host) |
207 | { | |
2f4cbb3d | 208 | sdhci_init(host, 0); |
7260cf5e | 209 | sdhci_enable_card_detection(host); |
d129bceb PO |
210 | } |
211 | ||
212 | static void sdhci_activate_led(struct sdhci_host *host) | |
213 | { | |
214 | u8 ctrl; | |
215 | ||
4e4141a5 | 216 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 217 | ctrl |= SDHCI_CTRL_LED; |
4e4141a5 | 218 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
219 | } |
220 | ||
221 | static void sdhci_deactivate_led(struct sdhci_host *host) | |
222 | { | |
223 | u8 ctrl; | |
224 | ||
4e4141a5 | 225 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 226 | ctrl &= ~SDHCI_CTRL_LED; |
4e4141a5 | 227 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
228 | } |
229 | ||
f9134319 | 230 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
231 | static void sdhci_led_control(struct led_classdev *led, |
232 | enum led_brightness brightness) | |
233 | { | |
234 | struct sdhci_host *host = container_of(led, struct sdhci_host, led); | |
235 | unsigned long flags; | |
236 | ||
237 | spin_lock_irqsave(&host->lock, flags); | |
238 | ||
239 | if (brightness == LED_OFF) | |
240 | sdhci_deactivate_led(host); | |
241 | else | |
242 | sdhci_activate_led(host); | |
243 | ||
244 | spin_unlock_irqrestore(&host->lock, flags); | |
245 | } | |
246 | #endif | |
247 | ||
d129bceb PO |
248 | /*****************************************************************************\ |
249 | * * | |
250 | * Core functions * | |
251 | * * | |
252 | \*****************************************************************************/ | |
253 | ||
a406f5a3 | 254 | static void sdhci_read_block_pio(struct sdhci_host *host) |
d129bceb | 255 | { |
7659150c PO |
256 | unsigned long flags; |
257 | size_t blksize, len, chunk; | |
7244b85b | 258 | u32 uninitialized_var(scratch); |
7659150c | 259 | u8 *buf; |
d129bceb | 260 | |
a406f5a3 | 261 | DBG("PIO reading\n"); |
d129bceb | 262 | |
a406f5a3 | 263 | blksize = host->data->blksz; |
7659150c | 264 | chunk = 0; |
d129bceb | 265 | |
7659150c | 266 | local_irq_save(flags); |
d129bceb | 267 | |
a406f5a3 | 268 | while (blksize) { |
7659150c PO |
269 | if (!sg_miter_next(&host->sg_miter)) |
270 | BUG(); | |
d129bceb | 271 | |
7659150c | 272 | len = min(host->sg_miter.length, blksize); |
d129bceb | 273 | |
7659150c PO |
274 | blksize -= len; |
275 | host->sg_miter.consumed = len; | |
14d836e7 | 276 | |
7659150c | 277 | buf = host->sg_miter.addr; |
d129bceb | 278 | |
7659150c PO |
279 | while (len) { |
280 | if (chunk == 0) { | |
4e4141a5 | 281 | scratch = sdhci_readl(host, SDHCI_BUFFER); |
7659150c | 282 | chunk = 4; |
a406f5a3 | 283 | } |
7659150c PO |
284 | |
285 | *buf = scratch & 0xFF; | |
286 | ||
287 | buf++; | |
288 | scratch >>= 8; | |
289 | chunk--; | |
290 | len--; | |
d129bceb | 291 | } |
a406f5a3 | 292 | } |
7659150c PO |
293 | |
294 | sg_miter_stop(&host->sg_miter); | |
295 | ||
296 | local_irq_restore(flags); | |
a406f5a3 | 297 | } |
d129bceb | 298 | |
a406f5a3 PO |
299 | static void sdhci_write_block_pio(struct sdhci_host *host) |
300 | { | |
7659150c PO |
301 | unsigned long flags; |
302 | size_t blksize, len, chunk; | |
303 | u32 scratch; | |
304 | u8 *buf; | |
d129bceb | 305 | |
a406f5a3 PO |
306 | DBG("PIO writing\n"); |
307 | ||
308 | blksize = host->data->blksz; | |
7659150c PO |
309 | chunk = 0; |
310 | scratch = 0; | |
d129bceb | 311 | |
7659150c | 312 | local_irq_save(flags); |
d129bceb | 313 | |
a406f5a3 | 314 | while (blksize) { |
7659150c PO |
315 | if (!sg_miter_next(&host->sg_miter)) |
316 | BUG(); | |
a406f5a3 | 317 | |
7659150c PO |
318 | len = min(host->sg_miter.length, blksize); |
319 | ||
320 | blksize -= len; | |
321 | host->sg_miter.consumed = len; | |
322 | ||
323 | buf = host->sg_miter.addr; | |
d129bceb | 324 | |
7659150c PO |
325 | while (len) { |
326 | scratch |= (u32)*buf << (chunk * 8); | |
327 | ||
328 | buf++; | |
329 | chunk++; | |
330 | len--; | |
331 | ||
332 | if ((chunk == 4) || ((len == 0) && (blksize == 0))) { | |
4e4141a5 | 333 | sdhci_writel(host, scratch, SDHCI_BUFFER); |
7659150c PO |
334 | chunk = 0; |
335 | scratch = 0; | |
d129bceb | 336 | } |
d129bceb PO |
337 | } |
338 | } | |
7659150c PO |
339 | |
340 | sg_miter_stop(&host->sg_miter); | |
341 | ||
342 | local_irq_restore(flags); | |
a406f5a3 PO |
343 | } |
344 | ||
345 | static void sdhci_transfer_pio(struct sdhci_host *host) | |
346 | { | |
347 | u32 mask; | |
348 | ||
349 | BUG_ON(!host->data); | |
350 | ||
7659150c | 351 | if (host->blocks == 0) |
a406f5a3 PO |
352 | return; |
353 | ||
354 | if (host->data->flags & MMC_DATA_READ) | |
355 | mask = SDHCI_DATA_AVAILABLE; | |
356 | else | |
357 | mask = SDHCI_SPACE_AVAILABLE; | |
358 | ||
4a3cba32 PO |
359 | /* |
360 | * Some controllers (JMicron JMB38x) mess up the buffer bits | |
361 | * for transfers < 4 bytes. As long as it is just one block, | |
362 | * we can ignore the bits. | |
363 | */ | |
364 | if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && | |
365 | (host->data->blocks == 1)) | |
366 | mask = ~0; | |
367 | ||
4e4141a5 | 368 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
3e3bf207 AV |
369 | if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) |
370 | udelay(100); | |
371 | ||
a406f5a3 PO |
372 | if (host->data->flags & MMC_DATA_READ) |
373 | sdhci_read_block_pio(host); | |
374 | else | |
375 | sdhci_write_block_pio(host); | |
d129bceb | 376 | |
7659150c PO |
377 | host->blocks--; |
378 | if (host->blocks == 0) | |
a406f5a3 | 379 | break; |
a406f5a3 | 380 | } |
d129bceb | 381 | |
a406f5a3 | 382 | DBG("PIO transfer complete.\n"); |
d129bceb PO |
383 | } |
384 | ||
2134a922 PO |
385 | static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) |
386 | { | |
387 | local_irq_save(*flags); | |
388 | return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; | |
389 | } | |
390 | ||
391 | static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) | |
392 | { | |
393 | kunmap_atomic(buffer, KM_BIO_SRC_IRQ); | |
394 | local_irq_restore(*flags); | |
395 | } | |
396 | ||
118cd17d BD |
397 | static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd) |
398 | { | |
9e506f35 BD |
399 | __le32 *dataddr = (__le32 __force *)(desc + 4); |
400 | __le16 *cmdlen = (__le16 __force *)desc; | |
118cd17d | 401 | |
9e506f35 BD |
402 | /* SDHCI specification says ADMA descriptors should be 4 byte |
403 | * aligned, so using 16 or 32bit operations should be safe. */ | |
118cd17d | 404 | |
9e506f35 BD |
405 | cmdlen[0] = cpu_to_le16(cmd); |
406 | cmdlen[1] = cpu_to_le16(len); | |
407 | ||
408 | dataddr[0] = cpu_to_le32(addr); | |
118cd17d BD |
409 | } |
410 | ||
8f1934ce | 411 | static int sdhci_adma_table_pre(struct sdhci_host *host, |
2134a922 PO |
412 | struct mmc_data *data) |
413 | { | |
414 | int direction; | |
415 | ||
416 | u8 *desc; | |
417 | u8 *align; | |
418 | dma_addr_t addr; | |
419 | dma_addr_t align_addr; | |
420 | int len, offset; | |
421 | ||
422 | struct scatterlist *sg; | |
423 | int i; | |
424 | char *buffer; | |
425 | unsigned long flags; | |
426 | ||
427 | /* | |
428 | * The spec does not specify endianness of descriptor table. | |
429 | * We currently guess that it is LE. | |
430 | */ | |
431 | ||
432 | if (data->flags & MMC_DATA_READ) | |
433 | direction = DMA_FROM_DEVICE; | |
434 | else | |
435 | direction = DMA_TO_DEVICE; | |
436 | ||
437 | /* | |
438 | * The ADMA descriptor table is mapped further down as we | |
439 | * need to fill it with data first. | |
440 | */ | |
441 | ||
442 | host->align_addr = dma_map_single(mmc_dev(host->mmc), | |
443 | host->align_buffer, 128 * 4, direction); | |
8d8bb39b | 444 | if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) |
8f1934ce | 445 | goto fail; |
2134a922 PO |
446 | BUG_ON(host->align_addr & 0x3); |
447 | ||
448 | host->sg_count = dma_map_sg(mmc_dev(host->mmc), | |
449 | data->sg, data->sg_len, direction); | |
8f1934ce PO |
450 | if (host->sg_count == 0) |
451 | goto unmap_align; | |
2134a922 PO |
452 | |
453 | desc = host->adma_desc; | |
454 | align = host->align_buffer; | |
455 | ||
456 | align_addr = host->align_addr; | |
457 | ||
458 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
459 | addr = sg_dma_address(sg); | |
460 | len = sg_dma_len(sg); | |
461 | ||
462 | /* | |
463 | * The SDHCI specification states that ADMA | |
464 | * addresses must be 32-bit aligned. If they | |
465 | * aren't, then we use a bounce buffer for | |
466 | * the (up to three) bytes that screw up the | |
467 | * alignment. | |
468 | */ | |
469 | offset = (4 - (addr & 0x3)) & 0x3; | |
470 | if (offset) { | |
471 | if (data->flags & MMC_DATA_WRITE) { | |
472 | buffer = sdhci_kmap_atomic(sg, &flags); | |
6cefd05f | 473 | WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); |
2134a922 PO |
474 | memcpy(align, buffer, offset); |
475 | sdhci_kunmap_atomic(buffer, &flags); | |
476 | } | |
477 | ||
118cd17d BD |
478 | /* tran, valid */ |
479 | sdhci_set_adma_desc(desc, align_addr, offset, 0x21); | |
2134a922 PO |
480 | |
481 | BUG_ON(offset > 65536); | |
482 | ||
2134a922 PO |
483 | align += 4; |
484 | align_addr += 4; | |
485 | ||
486 | desc += 8; | |
487 | ||
488 | addr += offset; | |
489 | len -= offset; | |
490 | } | |
491 | ||
2134a922 PO |
492 | BUG_ON(len > 65536); |
493 | ||
118cd17d BD |
494 | /* tran, valid */ |
495 | sdhci_set_adma_desc(desc, addr, len, 0x21); | |
2134a922 PO |
496 | desc += 8; |
497 | ||
498 | /* | |
499 | * If this triggers then we have a calculation bug | |
500 | * somewhere. :/ | |
501 | */ | |
502 | WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4); | |
503 | } | |
504 | ||
70764a90 TA |
505 | if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { |
506 | /* | |
507 | * Mark the last descriptor as the terminating descriptor | |
508 | */ | |
509 | if (desc != host->adma_desc) { | |
510 | desc -= 8; | |
511 | desc[0] |= 0x2; /* end */ | |
512 | } | |
513 | } else { | |
514 | /* | |
515 | * Add a terminating entry. | |
516 | */ | |
2134a922 | 517 | |
70764a90 TA |
518 | /* nop, end, valid */ |
519 | sdhci_set_adma_desc(desc, 0, 0, 0x3); | |
520 | } | |
2134a922 PO |
521 | |
522 | /* | |
523 | * Resync align buffer as we might have changed it. | |
524 | */ | |
525 | if (data->flags & MMC_DATA_WRITE) { | |
526 | dma_sync_single_for_device(mmc_dev(host->mmc), | |
527 | host->align_addr, 128 * 4, direction); | |
528 | } | |
529 | ||
530 | host->adma_addr = dma_map_single(mmc_dev(host->mmc), | |
531 | host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE); | |
980167b7 | 532 | if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr)) |
8f1934ce | 533 | goto unmap_entries; |
2134a922 | 534 | BUG_ON(host->adma_addr & 0x3); |
8f1934ce PO |
535 | |
536 | return 0; | |
537 | ||
538 | unmap_entries: | |
539 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
540 | data->sg_len, direction); | |
541 | unmap_align: | |
542 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, | |
543 | 128 * 4, direction); | |
544 | fail: | |
545 | return -EINVAL; | |
2134a922 PO |
546 | } |
547 | ||
548 | static void sdhci_adma_table_post(struct sdhci_host *host, | |
549 | struct mmc_data *data) | |
550 | { | |
551 | int direction; | |
552 | ||
553 | struct scatterlist *sg; | |
554 | int i, size; | |
555 | u8 *align; | |
556 | char *buffer; | |
557 | unsigned long flags; | |
558 | ||
559 | if (data->flags & MMC_DATA_READ) | |
560 | direction = DMA_FROM_DEVICE; | |
561 | else | |
562 | direction = DMA_TO_DEVICE; | |
563 | ||
564 | dma_unmap_single(mmc_dev(host->mmc), host->adma_addr, | |
565 | (128 * 2 + 1) * 4, DMA_TO_DEVICE); | |
566 | ||
567 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, | |
568 | 128 * 4, direction); | |
569 | ||
570 | if (data->flags & MMC_DATA_READ) { | |
571 | dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, | |
572 | data->sg_len, direction); | |
573 | ||
574 | align = host->align_buffer; | |
575 | ||
576 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
577 | if (sg_dma_address(sg) & 0x3) { | |
578 | size = 4 - (sg_dma_address(sg) & 0x3); | |
579 | ||
580 | buffer = sdhci_kmap_atomic(sg, &flags); | |
6cefd05f | 581 | WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); |
2134a922 PO |
582 | memcpy(buffer, align, size); |
583 | sdhci_kunmap_atomic(buffer, &flags); | |
584 | ||
585 | align += 4; | |
586 | } | |
587 | } | |
588 | } | |
589 | ||
590 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
591 | data->sg_len, direction); | |
592 | } | |
593 | ||
ee53ab5d | 594 | static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data) |
d129bceb | 595 | { |
1c8cde92 PO |
596 | u8 count; |
597 | unsigned target_timeout, current_timeout; | |
d129bceb | 598 | |
ee53ab5d PO |
599 | /* |
600 | * If the host controller provides us with an incorrect timeout | |
601 | * value, just skip the check and use 0xE. The hardware may take | |
602 | * longer to time out, but that's much better than having a too-short | |
603 | * timeout value. | |
604 | */ | |
11a2f1b7 | 605 | if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) |
ee53ab5d | 606 | return 0xE; |
e538fbe8 | 607 | |
1c8cde92 PO |
608 | /* timeout in us */ |
609 | target_timeout = data->timeout_ns / 1000 + | |
610 | data->timeout_clks / host->clock; | |
d129bceb | 611 | |
81b39802 AV |
612 | if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) |
613 | host->timeout_clk = host->clock / 1000; | |
614 | ||
1c8cde92 PO |
615 | /* |
616 | * Figure out needed cycles. | |
617 | * We do this in steps in order to fit inside a 32 bit int. | |
618 | * The first step is the minimum timeout, which will have a | |
619 | * minimum resolution of 6 bits: | |
620 | * (1) 2^13*1000 > 2^22, | |
621 | * (2) host->timeout_clk < 2^16 | |
622 | * => | |
623 | * (1) / (2) > 2^6 | |
624 | */ | |
625 | count = 0; | |
626 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; | |
627 | while (current_timeout < target_timeout) { | |
628 | count++; | |
629 | current_timeout <<= 1; | |
630 | if (count >= 0xF) | |
631 | break; | |
632 | } | |
633 | ||
634 | if (count >= 0xF) { | |
635 | printk(KERN_WARNING "%s: Too large timeout requested!\n", | |
636 | mmc_hostname(host->mmc)); | |
637 | count = 0xE; | |
638 | } | |
639 | ||
ee53ab5d PO |
640 | return count; |
641 | } | |
642 | ||
6aa943ab AV |
643 | static void sdhci_set_transfer_irqs(struct sdhci_host *host) |
644 | { | |
645 | u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; | |
646 | u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; | |
647 | ||
648 | if (host->flags & SDHCI_REQ_USE_DMA) | |
649 | sdhci_clear_set_irqs(host, pio_irqs, dma_irqs); | |
650 | else | |
651 | sdhci_clear_set_irqs(host, dma_irqs, pio_irqs); | |
652 | } | |
653 | ||
ee53ab5d PO |
654 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) |
655 | { | |
656 | u8 count; | |
2134a922 | 657 | u8 ctrl; |
8f1934ce | 658 | int ret; |
ee53ab5d PO |
659 | |
660 | WARN_ON(host->data); | |
661 | ||
662 | if (data == NULL) | |
663 | return; | |
664 | ||
665 | /* Sanity checks */ | |
666 | BUG_ON(data->blksz * data->blocks > 524288); | |
667 | BUG_ON(data->blksz > host->mmc->max_blk_size); | |
668 | BUG_ON(data->blocks > 65535); | |
669 | ||
670 | host->data = data; | |
671 | host->data_early = 0; | |
672 | ||
673 | count = sdhci_calc_timeout(host, data); | |
4e4141a5 | 674 | sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); |
d129bceb | 675 | |
a13abc7b | 676 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) |
c9fddbc4 PO |
677 | host->flags |= SDHCI_REQ_USE_DMA; |
678 | ||
2134a922 PO |
679 | /* |
680 | * FIXME: This doesn't account for merging when mapping the | |
681 | * scatterlist. | |
682 | */ | |
683 | if (host->flags & SDHCI_REQ_USE_DMA) { | |
684 | int broken, i; | |
685 | struct scatterlist *sg; | |
686 | ||
687 | broken = 0; | |
688 | if (host->flags & SDHCI_USE_ADMA) { | |
689 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) | |
690 | broken = 1; | |
691 | } else { | |
692 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) | |
693 | broken = 1; | |
694 | } | |
695 | ||
696 | if (unlikely(broken)) { | |
697 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
698 | if (sg->length & 0x3) { | |
699 | DBG("Reverting to PIO because of " | |
700 | "transfer size (%d)\n", | |
701 | sg->length); | |
702 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
703 | break; | |
704 | } | |
705 | } | |
706 | } | |
c9fddbc4 PO |
707 | } |
708 | ||
709 | /* | |
710 | * The assumption here being that alignment is the same after | |
711 | * translation to device address space. | |
712 | */ | |
2134a922 PO |
713 | if (host->flags & SDHCI_REQ_USE_DMA) { |
714 | int broken, i; | |
715 | struct scatterlist *sg; | |
716 | ||
717 | broken = 0; | |
718 | if (host->flags & SDHCI_USE_ADMA) { | |
719 | /* | |
720 | * As we use 3 byte chunks to work around | |
721 | * alignment problems, we need to check this | |
722 | * quirk. | |
723 | */ | |
724 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) | |
725 | broken = 1; | |
726 | } else { | |
727 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) | |
728 | broken = 1; | |
729 | } | |
730 | ||
731 | if (unlikely(broken)) { | |
732 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
733 | if (sg->offset & 0x3) { | |
734 | DBG("Reverting to PIO because of " | |
735 | "bad alignment\n"); | |
736 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
737 | break; | |
738 | } | |
739 | } | |
740 | } | |
741 | } | |
742 | ||
8f1934ce PO |
743 | if (host->flags & SDHCI_REQ_USE_DMA) { |
744 | if (host->flags & SDHCI_USE_ADMA) { | |
745 | ret = sdhci_adma_table_pre(host, data); | |
746 | if (ret) { | |
747 | /* | |
748 | * This only happens when someone fed | |
749 | * us an invalid request. | |
750 | */ | |
751 | WARN_ON(1); | |
ebd6d357 | 752 | host->flags &= ~SDHCI_REQ_USE_DMA; |
8f1934ce | 753 | } else { |
4e4141a5 AV |
754 | sdhci_writel(host, host->adma_addr, |
755 | SDHCI_ADMA_ADDRESS); | |
8f1934ce PO |
756 | } |
757 | } else { | |
c8b3e02e | 758 | int sg_cnt; |
8f1934ce | 759 | |
c8b3e02e | 760 | sg_cnt = dma_map_sg(mmc_dev(host->mmc), |
8f1934ce PO |
761 | data->sg, data->sg_len, |
762 | (data->flags & MMC_DATA_READ) ? | |
763 | DMA_FROM_DEVICE : | |
764 | DMA_TO_DEVICE); | |
c8b3e02e | 765 | if (sg_cnt == 0) { |
8f1934ce PO |
766 | /* |
767 | * This only happens when someone fed | |
768 | * us an invalid request. | |
769 | */ | |
770 | WARN_ON(1); | |
ebd6d357 | 771 | host->flags &= ~SDHCI_REQ_USE_DMA; |
8f1934ce | 772 | } else { |
719a61b4 | 773 | WARN_ON(sg_cnt != 1); |
4e4141a5 AV |
774 | sdhci_writel(host, sg_dma_address(data->sg), |
775 | SDHCI_DMA_ADDRESS); | |
8f1934ce PO |
776 | } |
777 | } | |
778 | } | |
779 | ||
2134a922 PO |
780 | /* |
781 | * Always adjust the DMA selection as some controllers | |
782 | * (e.g. JMicron) can't do PIO properly when the selection | |
783 | * is ADMA. | |
784 | */ | |
785 | if (host->version >= SDHCI_SPEC_200) { | |
4e4141a5 | 786 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
2134a922 PO |
787 | ctrl &= ~SDHCI_CTRL_DMA_MASK; |
788 | if ((host->flags & SDHCI_REQ_USE_DMA) && | |
789 | (host->flags & SDHCI_USE_ADMA)) | |
790 | ctrl |= SDHCI_CTRL_ADMA32; | |
791 | else | |
792 | ctrl |= SDHCI_CTRL_SDMA; | |
4e4141a5 | 793 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
c9fddbc4 PO |
794 | } |
795 | ||
8f1934ce | 796 | if (!(host->flags & SDHCI_REQ_USE_DMA)) { |
da60a91d SAS |
797 | int flags; |
798 | ||
799 | flags = SG_MITER_ATOMIC; | |
800 | if (host->data->flags & MMC_DATA_READ) | |
801 | flags |= SG_MITER_TO_SG; | |
802 | else | |
803 | flags |= SG_MITER_FROM_SG; | |
804 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
7659150c | 805 | host->blocks = data->blocks; |
d129bceb | 806 | } |
c7fa9963 | 807 | |
6aa943ab AV |
808 | sdhci_set_transfer_irqs(host); |
809 | ||
bab76961 | 810 | /* We do not handle DMA boundaries, so set it to max (512 KiB) */ |
4e4141a5 AV |
811 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE); |
812 | sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); | |
c7fa9963 PO |
813 | } |
814 | ||
815 | static void sdhci_set_transfer_mode(struct sdhci_host *host, | |
816 | struct mmc_data *data) | |
817 | { | |
818 | u16 mode; | |
819 | ||
c7fa9963 PO |
820 | if (data == NULL) |
821 | return; | |
822 | ||
e538fbe8 PO |
823 | WARN_ON(!host->data); |
824 | ||
c7fa9963 | 825 | mode = SDHCI_TRNS_BLK_CNT_EN; |
c4512f79 JH |
826 | if (data->blocks > 1) { |
827 | if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) | |
828 | mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12; | |
829 | else | |
830 | mode |= SDHCI_TRNS_MULTI; | |
831 | } | |
c7fa9963 PO |
832 | if (data->flags & MMC_DATA_READ) |
833 | mode |= SDHCI_TRNS_READ; | |
c9fddbc4 | 834 | if (host->flags & SDHCI_REQ_USE_DMA) |
c7fa9963 PO |
835 | mode |= SDHCI_TRNS_DMA; |
836 | ||
4e4141a5 | 837 | sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); |
d129bceb PO |
838 | } |
839 | ||
840 | static void sdhci_finish_data(struct sdhci_host *host) | |
841 | { | |
842 | struct mmc_data *data; | |
d129bceb PO |
843 | |
844 | BUG_ON(!host->data); | |
845 | ||
846 | data = host->data; | |
847 | host->data = NULL; | |
848 | ||
c9fddbc4 | 849 | if (host->flags & SDHCI_REQ_USE_DMA) { |
2134a922 PO |
850 | if (host->flags & SDHCI_USE_ADMA) |
851 | sdhci_adma_table_post(host, data); | |
852 | else { | |
853 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
854 | data->sg_len, (data->flags & MMC_DATA_READ) ? | |
855 | DMA_FROM_DEVICE : DMA_TO_DEVICE); | |
856 | } | |
d129bceb PO |
857 | } |
858 | ||
859 | /* | |
c9b74c5b PO |
860 | * The specification states that the block count register must |
861 | * be updated, but it does not specify at what point in the | |
862 | * data flow. That makes the register entirely useless to read | |
863 | * back so we have to assume that nothing made it to the card | |
864 | * in the event of an error. | |
d129bceb | 865 | */ |
c9b74c5b PO |
866 | if (data->error) |
867 | data->bytes_xfered = 0; | |
d129bceb | 868 | else |
c9b74c5b | 869 | data->bytes_xfered = data->blksz * data->blocks; |
d129bceb | 870 | |
d129bceb PO |
871 | if (data->stop) { |
872 | /* | |
873 | * The controller needs a reset of internal state machines | |
874 | * upon error conditions. | |
875 | */ | |
17b0429d | 876 | if (data->error) { |
d129bceb PO |
877 | sdhci_reset(host, SDHCI_RESET_CMD); |
878 | sdhci_reset(host, SDHCI_RESET_DATA); | |
879 | } | |
880 | ||
881 | sdhci_send_command(host, data->stop); | |
882 | } else | |
883 | tasklet_schedule(&host->finish_tasklet); | |
884 | } | |
885 | ||
886 | static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) | |
887 | { | |
888 | int flags; | |
fd2208d7 | 889 | u32 mask; |
7cb2c76f | 890 | unsigned long timeout; |
d129bceb PO |
891 | |
892 | WARN_ON(host->cmd); | |
893 | ||
d129bceb | 894 | /* Wait max 10 ms */ |
7cb2c76f | 895 | timeout = 10; |
fd2208d7 PO |
896 | |
897 | mask = SDHCI_CMD_INHIBIT; | |
898 | if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) | |
899 | mask |= SDHCI_DATA_INHIBIT; | |
900 | ||
901 | /* We shouldn't wait for data inihibit for stop commands, even | |
902 | though they might use busy signaling */ | |
903 | if (host->mrq->data && (cmd == host->mrq->data->stop)) | |
904 | mask &= ~SDHCI_DATA_INHIBIT; | |
905 | ||
4e4141a5 | 906 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
7cb2c76f | 907 | if (timeout == 0) { |
d129bceb | 908 | printk(KERN_ERR "%s: Controller never released " |
acf1da45 | 909 | "inhibit bit(s).\n", mmc_hostname(host->mmc)); |
d129bceb | 910 | sdhci_dumpregs(host); |
17b0429d | 911 | cmd->error = -EIO; |
d129bceb PO |
912 | tasklet_schedule(&host->finish_tasklet); |
913 | return; | |
914 | } | |
7cb2c76f PO |
915 | timeout--; |
916 | mdelay(1); | |
917 | } | |
d129bceb PO |
918 | |
919 | mod_timer(&host->timer, jiffies + 10 * HZ); | |
920 | ||
921 | host->cmd = cmd; | |
922 | ||
923 | sdhci_prepare_data(host, cmd->data); | |
924 | ||
4e4141a5 | 925 | sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); |
d129bceb | 926 | |
c7fa9963 PO |
927 | sdhci_set_transfer_mode(host, cmd->data); |
928 | ||
d129bceb | 929 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
acf1da45 | 930 | printk(KERN_ERR "%s: Unsupported response type!\n", |
d129bceb | 931 | mmc_hostname(host->mmc)); |
17b0429d | 932 | cmd->error = -EINVAL; |
d129bceb PO |
933 | tasklet_schedule(&host->finish_tasklet); |
934 | return; | |
935 | } | |
936 | ||
937 | if (!(cmd->flags & MMC_RSP_PRESENT)) | |
938 | flags = SDHCI_CMD_RESP_NONE; | |
939 | else if (cmd->flags & MMC_RSP_136) | |
940 | flags = SDHCI_CMD_RESP_LONG; | |
941 | else if (cmd->flags & MMC_RSP_BUSY) | |
942 | flags = SDHCI_CMD_RESP_SHORT_BUSY; | |
943 | else | |
944 | flags = SDHCI_CMD_RESP_SHORT; | |
945 | ||
946 | if (cmd->flags & MMC_RSP_CRC) | |
947 | flags |= SDHCI_CMD_CRC; | |
948 | if (cmd->flags & MMC_RSP_OPCODE) | |
949 | flags |= SDHCI_CMD_INDEX; | |
950 | if (cmd->data) | |
951 | flags |= SDHCI_CMD_DATA; | |
952 | ||
4e4141a5 | 953 | sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); |
d129bceb PO |
954 | } |
955 | ||
956 | static void sdhci_finish_command(struct sdhci_host *host) | |
957 | { | |
958 | int i; | |
959 | ||
960 | BUG_ON(host->cmd == NULL); | |
961 | ||
962 | if (host->cmd->flags & MMC_RSP_PRESENT) { | |
963 | if (host->cmd->flags & MMC_RSP_136) { | |
964 | /* CRC is stripped so we need to do some shifting. */ | |
965 | for (i = 0;i < 4;i++) { | |
4e4141a5 | 966 | host->cmd->resp[i] = sdhci_readl(host, |
d129bceb PO |
967 | SDHCI_RESPONSE + (3-i)*4) << 8; |
968 | if (i != 3) | |
969 | host->cmd->resp[i] |= | |
4e4141a5 | 970 | sdhci_readb(host, |
d129bceb PO |
971 | SDHCI_RESPONSE + (3-i)*4-1); |
972 | } | |
973 | } else { | |
4e4141a5 | 974 | host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); |
d129bceb PO |
975 | } |
976 | } | |
977 | ||
17b0429d | 978 | host->cmd->error = 0; |
d129bceb | 979 | |
e538fbe8 PO |
980 | if (host->data && host->data_early) |
981 | sdhci_finish_data(host); | |
982 | ||
983 | if (!host->cmd->data) | |
d129bceb PO |
984 | tasklet_schedule(&host->finish_tasklet); |
985 | ||
986 | host->cmd = NULL; | |
987 | } | |
988 | ||
989 | static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) | |
990 | { | |
991 | int div; | |
992 | u16 clk; | |
7cb2c76f | 993 | unsigned long timeout; |
d129bceb PO |
994 | |
995 | if (clock == host->clock) | |
996 | return; | |
997 | ||
8114634c AV |
998 | if (host->ops->set_clock) { |
999 | host->ops->set_clock(host, clock); | |
1000 | if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) | |
1001 | return; | |
1002 | } | |
1003 | ||
4e4141a5 | 1004 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
d129bceb PO |
1005 | |
1006 | if (clock == 0) | |
1007 | goto out; | |
1008 | ||
85105c53 ZG |
1009 | if (host->version >= SDHCI_SPEC_300) { |
1010 | /* Version 3.00 divisors must be a multiple of 2. */ | |
1011 | if (host->max_clk <= clock) | |
1012 | div = 1; | |
1013 | else { | |
0397526d | 1014 | for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) { |
85105c53 ZG |
1015 | if ((host->max_clk / div) <= clock) |
1016 | break; | |
1017 | } | |
1018 | } | |
1019 | } else { | |
1020 | /* Version 2.00 divisors must be a power of 2. */ | |
0397526d | 1021 | for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { |
85105c53 ZG |
1022 | if ((host->max_clk / div) <= clock) |
1023 | break; | |
1024 | } | |
d129bceb PO |
1025 | } |
1026 | div >>= 1; | |
1027 | ||
85105c53 ZG |
1028 | clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; |
1029 | clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) | |
1030 | << SDHCI_DIVIDER_HI_SHIFT; | |
d129bceb | 1031 | clk |= SDHCI_CLOCK_INT_EN; |
4e4141a5 | 1032 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb | 1033 | |
27f6cb16 CB |
1034 | /* Wait max 20 ms */ |
1035 | timeout = 20; | |
4e4141a5 | 1036 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) |
7cb2c76f PO |
1037 | & SDHCI_CLOCK_INT_STABLE)) { |
1038 | if (timeout == 0) { | |
acf1da45 PO |
1039 | printk(KERN_ERR "%s: Internal clock never " |
1040 | "stabilised.\n", mmc_hostname(host->mmc)); | |
d129bceb PO |
1041 | sdhci_dumpregs(host); |
1042 | return; | |
1043 | } | |
7cb2c76f PO |
1044 | timeout--; |
1045 | mdelay(1); | |
1046 | } | |
d129bceb PO |
1047 | |
1048 | clk |= SDHCI_CLOCK_CARD_EN; | |
4e4141a5 | 1049 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb PO |
1050 | |
1051 | out: | |
1052 | host->clock = clock; | |
1053 | } | |
1054 | ||
146ad66e PO |
1055 | static void sdhci_set_power(struct sdhci_host *host, unsigned short power) |
1056 | { | |
8364248a | 1057 | u8 pwr = 0; |
146ad66e | 1058 | |
8364248a | 1059 | if (power != (unsigned short)-1) { |
ae628903 PO |
1060 | switch (1 << power) { |
1061 | case MMC_VDD_165_195: | |
1062 | pwr = SDHCI_POWER_180; | |
1063 | break; | |
1064 | case MMC_VDD_29_30: | |
1065 | case MMC_VDD_30_31: | |
1066 | pwr = SDHCI_POWER_300; | |
1067 | break; | |
1068 | case MMC_VDD_32_33: | |
1069 | case MMC_VDD_33_34: | |
1070 | pwr = SDHCI_POWER_330; | |
1071 | break; | |
1072 | default: | |
1073 | BUG(); | |
1074 | } | |
1075 | } | |
1076 | ||
1077 | if (host->pwr == pwr) | |
146ad66e PO |
1078 | return; |
1079 | ||
ae628903 PO |
1080 | host->pwr = pwr; |
1081 | ||
1082 | if (pwr == 0) { | |
4e4141a5 | 1083 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
ae628903 | 1084 | return; |
9e9dc5f2 DS |
1085 | } |
1086 | ||
1087 | /* | |
1088 | * Spec says that we should clear the power reg before setting | |
1089 | * a new value. Some controllers don't seem to like this though. | |
1090 | */ | |
b8c86fc5 | 1091 | if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) |
4e4141a5 | 1092 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
146ad66e | 1093 | |
e08c1694 | 1094 | /* |
c71f6512 | 1095 | * At least the Marvell CaFe chip gets confused if we set the voltage |
e08c1694 AS |
1096 | * and set turn on power at the same time, so set the voltage first. |
1097 | */ | |
11a2f1b7 | 1098 | if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) |
ae628903 | 1099 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
e08c1694 | 1100 | |
ae628903 | 1101 | pwr |= SDHCI_POWER_ON; |
146ad66e | 1102 | |
ae628903 | 1103 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
557b0697 HW |
1104 | |
1105 | /* | |
1106 | * Some controllers need an extra 10ms delay of 10ms before they | |
1107 | * can apply clock after applying power | |
1108 | */ | |
11a2f1b7 | 1109 | if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) |
557b0697 | 1110 | mdelay(10); |
146ad66e PO |
1111 | } |
1112 | ||
d129bceb PO |
1113 | /*****************************************************************************\ |
1114 | * * | |
1115 | * MMC callbacks * | |
1116 | * * | |
1117 | \*****************************************************************************/ | |
1118 | ||
1119 | static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1120 | { | |
1121 | struct sdhci_host *host; | |
68d1fb7e | 1122 | bool present; |
d129bceb PO |
1123 | unsigned long flags; |
1124 | ||
1125 | host = mmc_priv(mmc); | |
1126 | ||
1127 | spin_lock_irqsave(&host->lock, flags); | |
1128 | ||
1129 | WARN_ON(host->mrq != NULL); | |
1130 | ||
f9134319 | 1131 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 1132 | sdhci_activate_led(host); |
2f730fec | 1133 | #endif |
c4512f79 JH |
1134 | if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) { |
1135 | if (mrq->stop) { | |
1136 | mrq->data->stop = NULL; | |
1137 | mrq->stop = NULL; | |
1138 | } | |
1139 | } | |
d129bceb PO |
1140 | |
1141 | host->mrq = mrq; | |
1142 | ||
68d1fb7e AV |
1143 | /* If polling, assume that the card is always present. */ |
1144 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) | |
1145 | present = true; | |
1146 | else | |
1147 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
1148 | SDHCI_CARD_PRESENT; | |
1149 | ||
1150 | if (!present || host->flags & SDHCI_DEVICE_DEAD) { | |
17b0429d | 1151 | host->mrq->cmd->error = -ENOMEDIUM; |
d129bceb PO |
1152 | tasklet_schedule(&host->finish_tasklet); |
1153 | } else | |
1154 | sdhci_send_command(host, mrq->cmd); | |
1155 | ||
5f25a66f | 1156 | mmiowb(); |
d129bceb PO |
1157 | spin_unlock_irqrestore(&host->lock, flags); |
1158 | } | |
1159 | ||
1160 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1161 | { | |
1162 | struct sdhci_host *host; | |
1163 | unsigned long flags; | |
1164 | u8 ctrl; | |
1165 | ||
1166 | host = mmc_priv(mmc); | |
1167 | ||
1168 | spin_lock_irqsave(&host->lock, flags); | |
1169 | ||
1e72859e PO |
1170 | if (host->flags & SDHCI_DEVICE_DEAD) |
1171 | goto out; | |
1172 | ||
d129bceb PO |
1173 | /* |
1174 | * Reset the chip on each power off. | |
1175 | * Should clear out any weird states. | |
1176 | */ | |
1177 | if (ios->power_mode == MMC_POWER_OFF) { | |
4e4141a5 | 1178 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
7260cf5e | 1179 | sdhci_reinit(host); |
d129bceb PO |
1180 | } |
1181 | ||
1182 | sdhci_set_clock(host, ios->clock); | |
1183 | ||
1184 | if (ios->power_mode == MMC_POWER_OFF) | |
146ad66e | 1185 | sdhci_set_power(host, -1); |
d129bceb | 1186 | else |
146ad66e | 1187 | sdhci_set_power(host, ios->vdd); |
d129bceb | 1188 | |
643a81ff PR |
1189 | if (host->ops->platform_send_init_74_clocks) |
1190 | host->ops->platform_send_init_74_clocks(host, ios->power_mode); | |
1191 | ||
15ec4461 PR |
1192 | /* |
1193 | * If your platform has 8-bit width support but is not a v3 controller, | |
1194 | * or if it requires special setup code, you should implement that in | |
1195 | * platform_8bit_width(). | |
1196 | */ | |
1197 | if (host->ops->platform_8bit_width) | |
1198 | host->ops->platform_8bit_width(host, ios->bus_width); | |
1199 | else { | |
1200 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
1201 | if (ios->bus_width == MMC_BUS_WIDTH_8) { | |
1202 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
1203 | if (host->version >= SDHCI_SPEC_300) | |
1204 | ctrl |= SDHCI_CTRL_8BITBUS; | |
1205 | } else { | |
1206 | if (host->version >= SDHCI_SPEC_300) | |
1207 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
1208 | if (ios->bus_width == MMC_BUS_WIDTH_4) | |
1209 | ctrl |= SDHCI_CTRL_4BITBUS; | |
1210 | else | |
1211 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
1212 | } | |
1213 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
1214 | } | |
ae6d6c92 | 1215 | |
15ec4461 | 1216 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
cd9277c0 | 1217 | |
3ab9c8da PR |
1218 | if ((ios->timing == MMC_TIMING_SD_HS || |
1219 | ios->timing == MMC_TIMING_MMC_HS) | |
1220 | && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) | |
cd9277c0 PO |
1221 | ctrl |= SDHCI_CTRL_HISPD; |
1222 | else | |
1223 | ctrl &= ~SDHCI_CTRL_HISPD; | |
1224 | ||
4e4141a5 | 1225 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb | 1226 | |
b8352260 LD |
1227 | /* |
1228 | * Some (ENE) controllers go apeshit on some ios operation, | |
1229 | * signalling timeout and CRC errors even on CMD0. Resetting | |
1230 | * it on each ios seems to solve the problem. | |
1231 | */ | |
b8c86fc5 | 1232 | if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) |
b8352260 LD |
1233 | sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); |
1234 | ||
1e72859e | 1235 | out: |
5f25a66f | 1236 | mmiowb(); |
d129bceb PO |
1237 | spin_unlock_irqrestore(&host->lock, flags); |
1238 | } | |
1239 | ||
1240 | static int sdhci_get_ro(struct mmc_host *mmc) | |
1241 | { | |
1242 | struct sdhci_host *host; | |
1243 | unsigned long flags; | |
2dfb579c | 1244 | int is_readonly; |
d129bceb PO |
1245 | |
1246 | host = mmc_priv(mmc); | |
1247 | ||
1248 | spin_lock_irqsave(&host->lock, flags); | |
1249 | ||
1e72859e | 1250 | if (host->flags & SDHCI_DEVICE_DEAD) |
2dfb579c WS |
1251 | is_readonly = 0; |
1252 | else if (host->ops->get_ro) | |
1253 | is_readonly = host->ops->get_ro(host); | |
1e72859e | 1254 | else |
2dfb579c WS |
1255 | is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) |
1256 | & SDHCI_WRITE_PROTECT); | |
d129bceb PO |
1257 | |
1258 | spin_unlock_irqrestore(&host->lock, flags); | |
1259 | ||
2dfb579c WS |
1260 | /* This quirk needs to be replaced by a callback-function later */ |
1261 | return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? | |
1262 | !is_readonly : is_readonly; | |
d129bceb PO |
1263 | } |
1264 | ||
f75979b7 PO |
1265 | static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
1266 | { | |
1267 | struct sdhci_host *host; | |
1268 | unsigned long flags; | |
f75979b7 PO |
1269 | |
1270 | host = mmc_priv(mmc); | |
1271 | ||
1272 | spin_lock_irqsave(&host->lock, flags); | |
1273 | ||
1e72859e PO |
1274 | if (host->flags & SDHCI_DEVICE_DEAD) |
1275 | goto out; | |
1276 | ||
f75979b7 | 1277 | if (enable) |
7260cf5e AV |
1278 | sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT); |
1279 | else | |
1280 | sdhci_mask_irqs(host, SDHCI_INT_CARD_INT); | |
1e72859e | 1281 | out: |
f75979b7 PO |
1282 | mmiowb(); |
1283 | ||
1284 | spin_unlock_irqrestore(&host->lock, flags); | |
1285 | } | |
1286 | ||
ab7aefd0 | 1287 | static const struct mmc_host_ops sdhci_ops = { |
d129bceb PO |
1288 | .request = sdhci_request, |
1289 | .set_ios = sdhci_set_ios, | |
1290 | .get_ro = sdhci_get_ro, | |
f75979b7 | 1291 | .enable_sdio_irq = sdhci_enable_sdio_irq, |
d129bceb PO |
1292 | }; |
1293 | ||
1294 | /*****************************************************************************\ | |
1295 | * * | |
1296 | * Tasklets * | |
1297 | * * | |
1298 | \*****************************************************************************/ | |
1299 | ||
1300 | static void sdhci_tasklet_card(unsigned long param) | |
1301 | { | |
1302 | struct sdhci_host *host; | |
1303 | unsigned long flags; | |
1304 | ||
1305 | host = (struct sdhci_host*)param; | |
1306 | ||
1307 | spin_lock_irqsave(&host->lock, flags); | |
1308 | ||
4e4141a5 | 1309 | if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { |
d129bceb PO |
1310 | if (host->mrq) { |
1311 | printk(KERN_ERR "%s: Card removed during transfer!\n", | |
1312 | mmc_hostname(host->mmc)); | |
1313 | printk(KERN_ERR "%s: Resetting controller.\n", | |
1314 | mmc_hostname(host->mmc)); | |
1315 | ||
1316 | sdhci_reset(host, SDHCI_RESET_CMD); | |
1317 | sdhci_reset(host, SDHCI_RESET_DATA); | |
1318 | ||
17b0429d | 1319 | host->mrq->cmd->error = -ENOMEDIUM; |
d129bceb PO |
1320 | tasklet_schedule(&host->finish_tasklet); |
1321 | } | |
1322 | } | |
1323 | ||
1324 | spin_unlock_irqrestore(&host->lock, flags); | |
1325 | ||
04cf585d | 1326 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); |
d129bceb PO |
1327 | } |
1328 | ||
1329 | static void sdhci_tasklet_finish(unsigned long param) | |
1330 | { | |
1331 | struct sdhci_host *host; | |
1332 | unsigned long flags; | |
1333 | struct mmc_request *mrq; | |
1334 | ||
1335 | host = (struct sdhci_host*)param; | |
1336 | ||
1337 | spin_lock_irqsave(&host->lock, flags); | |
1338 | ||
1339 | del_timer(&host->timer); | |
1340 | ||
1341 | mrq = host->mrq; | |
1342 | ||
d129bceb PO |
1343 | /* |
1344 | * The controller needs a reset of internal state machines | |
1345 | * upon error conditions. | |
1346 | */ | |
1e72859e | 1347 | if (!(host->flags & SDHCI_DEVICE_DEAD) && |
b7b4d342 | 1348 | ((mrq->cmd && mrq->cmd->error) || |
1e72859e PO |
1349 | (mrq->data && (mrq->data->error || |
1350 | (mrq->data->stop && mrq->data->stop->error))) || | |
1351 | (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { | |
645289dc PO |
1352 | |
1353 | /* Some controllers need this kick or reset won't work here */ | |
b8c86fc5 | 1354 | if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) { |
645289dc PO |
1355 | unsigned int clock; |
1356 | ||
1357 | /* This is to force an update */ | |
1358 | clock = host->clock; | |
1359 | host->clock = 0; | |
1360 | sdhci_set_clock(host, clock); | |
1361 | } | |
1362 | ||
1363 | /* Spec says we should do both at the same time, but Ricoh | |
1364 | controllers do not like that. */ | |
d129bceb PO |
1365 | sdhci_reset(host, SDHCI_RESET_CMD); |
1366 | sdhci_reset(host, SDHCI_RESET_DATA); | |
1367 | } | |
1368 | ||
1369 | host->mrq = NULL; | |
1370 | host->cmd = NULL; | |
1371 | host->data = NULL; | |
1372 | ||
f9134319 | 1373 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 1374 | sdhci_deactivate_led(host); |
2f730fec | 1375 | #endif |
d129bceb | 1376 | |
5f25a66f | 1377 | mmiowb(); |
d129bceb PO |
1378 | spin_unlock_irqrestore(&host->lock, flags); |
1379 | ||
1380 | mmc_request_done(host->mmc, mrq); | |
1381 | } | |
1382 | ||
1383 | static void sdhci_timeout_timer(unsigned long data) | |
1384 | { | |
1385 | struct sdhci_host *host; | |
1386 | unsigned long flags; | |
1387 | ||
1388 | host = (struct sdhci_host*)data; | |
1389 | ||
1390 | spin_lock_irqsave(&host->lock, flags); | |
1391 | ||
1392 | if (host->mrq) { | |
acf1da45 PO |
1393 | printk(KERN_ERR "%s: Timeout waiting for hardware " |
1394 | "interrupt.\n", mmc_hostname(host->mmc)); | |
d129bceb PO |
1395 | sdhci_dumpregs(host); |
1396 | ||
1397 | if (host->data) { | |
17b0429d | 1398 | host->data->error = -ETIMEDOUT; |
d129bceb PO |
1399 | sdhci_finish_data(host); |
1400 | } else { | |
1401 | if (host->cmd) | |
17b0429d | 1402 | host->cmd->error = -ETIMEDOUT; |
d129bceb | 1403 | else |
17b0429d | 1404 | host->mrq->cmd->error = -ETIMEDOUT; |
d129bceb PO |
1405 | |
1406 | tasklet_schedule(&host->finish_tasklet); | |
1407 | } | |
1408 | } | |
1409 | ||
5f25a66f | 1410 | mmiowb(); |
d129bceb PO |
1411 | spin_unlock_irqrestore(&host->lock, flags); |
1412 | } | |
1413 | ||
1414 | /*****************************************************************************\ | |
1415 | * * | |
1416 | * Interrupt handling * | |
1417 | * * | |
1418 | \*****************************************************************************/ | |
1419 | ||
1420 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) | |
1421 | { | |
1422 | BUG_ON(intmask == 0); | |
1423 | ||
1424 | if (!host->cmd) { | |
b67ac3f3 PO |
1425 | printk(KERN_ERR "%s: Got command interrupt 0x%08x even " |
1426 | "though no command operation was in progress.\n", | |
1427 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
1428 | sdhci_dumpregs(host); |
1429 | return; | |
1430 | } | |
1431 | ||
43b58b36 | 1432 | if (intmask & SDHCI_INT_TIMEOUT) |
17b0429d PO |
1433 | host->cmd->error = -ETIMEDOUT; |
1434 | else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | | |
1435 | SDHCI_INT_INDEX)) | |
1436 | host->cmd->error = -EILSEQ; | |
43b58b36 | 1437 | |
e809517f | 1438 | if (host->cmd->error) { |
d129bceb | 1439 | tasklet_schedule(&host->finish_tasklet); |
e809517f PO |
1440 | return; |
1441 | } | |
1442 | ||
1443 | /* | |
1444 | * The host can send and interrupt when the busy state has | |
1445 | * ended, allowing us to wait without wasting CPU cycles. | |
1446 | * Unfortunately this is overloaded on the "data complete" | |
1447 | * interrupt, so we need to take some care when handling | |
1448 | * it. | |
1449 | * | |
1450 | * Note: The 1.0 specification is a bit ambiguous about this | |
1451 | * feature so there might be some problems with older | |
1452 | * controllers. | |
1453 | */ | |
1454 | if (host->cmd->flags & MMC_RSP_BUSY) { | |
1455 | if (host->cmd->data) | |
1456 | DBG("Cannot wait for busy signal when also " | |
1457 | "doing a data transfer"); | |
f945405c | 1458 | else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)) |
e809517f | 1459 | return; |
f945405c BD |
1460 | |
1461 | /* The controller does not support the end-of-busy IRQ, | |
1462 | * fall through and take the SDHCI_INT_RESPONSE */ | |
e809517f PO |
1463 | } |
1464 | ||
1465 | if (intmask & SDHCI_INT_RESPONSE) | |
43b58b36 | 1466 | sdhci_finish_command(host); |
d129bceb PO |
1467 | } |
1468 | ||
0957c333 | 1469 | #ifdef CONFIG_MMC_DEBUG |
6882a8c0 BD |
1470 | static void sdhci_show_adma_error(struct sdhci_host *host) |
1471 | { | |
1472 | const char *name = mmc_hostname(host->mmc); | |
1473 | u8 *desc = host->adma_desc; | |
1474 | __le32 *dma; | |
1475 | __le16 *len; | |
1476 | u8 attr; | |
1477 | ||
1478 | sdhci_dumpregs(host); | |
1479 | ||
1480 | while (true) { | |
1481 | dma = (__le32 *)(desc + 4); | |
1482 | len = (__le16 *)(desc + 2); | |
1483 | attr = *desc; | |
1484 | ||
1485 | DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", | |
1486 | name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr); | |
1487 | ||
1488 | desc += 8; | |
1489 | ||
1490 | if (attr & 2) | |
1491 | break; | |
1492 | } | |
1493 | } | |
1494 | #else | |
1495 | static void sdhci_show_adma_error(struct sdhci_host *host) { } | |
1496 | #endif | |
1497 | ||
d129bceb PO |
1498 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) |
1499 | { | |
1500 | BUG_ON(intmask == 0); | |
1501 | ||
1502 | if (!host->data) { | |
1503 | /* | |
e809517f PO |
1504 | * The "data complete" interrupt is also used to |
1505 | * indicate that a busy state has ended. See comment | |
1506 | * above in sdhci_cmd_irq(). | |
d129bceb | 1507 | */ |
e809517f PO |
1508 | if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { |
1509 | if (intmask & SDHCI_INT_DATA_END) { | |
1510 | sdhci_finish_command(host); | |
1511 | return; | |
1512 | } | |
1513 | } | |
d129bceb | 1514 | |
b67ac3f3 PO |
1515 | printk(KERN_ERR "%s: Got data interrupt 0x%08x even " |
1516 | "though no data operation was in progress.\n", | |
1517 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
1518 | sdhci_dumpregs(host); |
1519 | ||
1520 | return; | |
1521 | } | |
1522 | ||
1523 | if (intmask & SDHCI_INT_DATA_TIMEOUT) | |
17b0429d | 1524 | host->data->error = -ETIMEDOUT; |
22113efd AL |
1525 | else if (intmask & SDHCI_INT_DATA_END_BIT) |
1526 | host->data->error = -EILSEQ; | |
1527 | else if ((intmask & SDHCI_INT_DATA_CRC) && | |
1528 | SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) | |
1529 | != MMC_BUS_TEST_R) | |
17b0429d | 1530 | host->data->error = -EILSEQ; |
6882a8c0 BD |
1531 | else if (intmask & SDHCI_INT_ADMA_ERROR) { |
1532 | printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc)); | |
1533 | sdhci_show_adma_error(host); | |
2134a922 | 1534 | host->data->error = -EIO; |
6882a8c0 | 1535 | } |
d129bceb | 1536 | |
17b0429d | 1537 | if (host->data->error) |
d129bceb PO |
1538 | sdhci_finish_data(host); |
1539 | else { | |
a406f5a3 | 1540 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
d129bceb PO |
1541 | sdhci_transfer_pio(host); |
1542 | ||
6ba736a1 PO |
1543 | /* |
1544 | * We currently don't do anything fancy with DMA | |
1545 | * boundaries, but as we can't disable the feature | |
1546 | * we need to at least restart the transfer. | |
1547 | */ | |
1548 | if (intmask & SDHCI_INT_DMA_END) | |
4e4141a5 AV |
1549 | sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS), |
1550 | SDHCI_DMA_ADDRESS); | |
6ba736a1 | 1551 | |
e538fbe8 PO |
1552 | if (intmask & SDHCI_INT_DATA_END) { |
1553 | if (host->cmd) { | |
1554 | /* | |
1555 | * Data managed to finish before the | |
1556 | * command completed. Make sure we do | |
1557 | * things in the proper order. | |
1558 | */ | |
1559 | host->data_early = 1; | |
1560 | } else { | |
1561 | sdhci_finish_data(host); | |
1562 | } | |
1563 | } | |
d129bceb PO |
1564 | } |
1565 | } | |
1566 | ||
7d12e780 | 1567 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
d129bceb PO |
1568 | { |
1569 | irqreturn_t result; | |
1570 | struct sdhci_host* host = dev_id; | |
1571 | u32 intmask; | |
f75979b7 | 1572 | int cardint = 0; |
d129bceb PO |
1573 | |
1574 | spin_lock(&host->lock); | |
1575 | ||
4e4141a5 | 1576 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
d129bceb | 1577 | |
62df67a5 | 1578 | if (!intmask || intmask == 0xffffffff) { |
d129bceb PO |
1579 | result = IRQ_NONE; |
1580 | goto out; | |
1581 | } | |
1582 | ||
b69c9058 PO |
1583 | DBG("*** %s got interrupt: 0x%08x\n", |
1584 | mmc_hostname(host->mmc), intmask); | |
d129bceb | 1585 | |
3192a28f | 1586 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
4e4141a5 AV |
1587 | sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | |
1588 | SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); | |
d129bceb | 1589 | tasklet_schedule(&host->card_tasklet); |
3192a28f | 1590 | } |
d129bceb | 1591 | |
3192a28f | 1592 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); |
d129bceb | 1593 | |
3192a28f | 1594 | if (intmask & SDHCI_INT_CMD_MASK) { |
4e4141a5 AV |
1595 | sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, |
1596 | SDHCI_INT_STATUS); | |
3192a28f | 1597 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); |
d129bceb PO |
1598 | } |
1599 | ||
1600 | if (intmask & SDHCI_INT_DATA_MASK) { | |
4e4141a5 AV |
1601 | sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK, |
1602 | SDHCI_INT_STATUS); | |
3192a28f | 1603 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); |
d129bceb PO |
1604 | } |
1605 | ||
1606 | intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); | |
1607 | ||
964f9ce2 PO |
1608 | intmask &= ~SDHCI_INT_ERROR; |
1609 | ||
d129bceb | 1610 | if (intmask & SDHCI_INT_BUS_POWER) { |
3192a28f | 1611 | printk(KERN_ERR "%s: Card is consuming too much power!\n", |
d129bceb | 1612 | mmc_hostname(host->mmc)); |
4e4141a5 | 1613 | sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS); |
d129bceb PO |
1614 | } |
1615 | ||
9d26a5d3 | 1616 | intmask &= ~SDHCI_INT_BUS_POWER; |
3192a28f | 1617 | |
f75979b7 PO |
1618 | if (intmask & SDHCI_INT_CARD_INT) |
1619 | cardint = 1; | |
1620 | ||
1621 | intmask &= ~SDHCI_INT_CARD_INT; | |
1622 | ||
3192a28f | 1623 | if (intmask) { |
acf1da45 | 1624 | printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n", |
3192a28f | 1625 | mmc_hostname(host->mmc), intmask); |
d129bceb PO |
1626 | sdhci_dumpregs(host); |
1627 | ||
4e4141a5 | 1628 | sdhci_writel(host, intmask, SDHCI_INT_STATUS); |
3192a28f | 1629 | } |
d129bceb PO |
1630 | |
1631 | result = IRQ_HANDLED; | |
1632 | ||
5f25a66f | 1633 | mmiowb(); |
d129bceb PO |
1634 | out: |
1635 | spin_unlock(&host->lock); | |
1636 | ||
f75979b7 PO |
1637 | /* |
1638 | * We have to delay this as it calls back into the driver. | |
1639 | */ | |
1640 | if (cardint) | |
1641 | mmc_signal_sdio_irq(host->mmc); | |
1642 | ||
d129bceb PO |
1643 | return result; |
1644 | } | |
1645 | ||
1646 | /*****************************************************************************\ | |
1647 | * * | |
1648 | * Suspend/resume * | |
1649 | * * | |
1650 | \*****************************************************************************/ | |
1651 | ||
1652 | #ifdef CONFIG_PM | |
1653 | ||
b8c86fc5 | 1654 | int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state) |
d129bceb | 1655 | { |
b8c86fc5 | 1656 | int ret; |
a715dfc7 | 1657 | |
7260cf5e AV |
1658 | sdhci_disable_card_detection(host); |
1659 | ||
1a13f8fa | 1660 | ret = mmc_suspend_host(host->mmc); |
b8c86fc5 PO |
1661 | if (ret) |
1662 | return ret; | |
a715dfc7 | 1663 | |
b8c86fc5 | 1664 | free_irq(host->irq, host); |
d129bceb | 1665 | |
9bea3c85 MS |
1666 | if (host->vmmc) |
1667 | ret = regulator_disable(host->vmmc); | |
1668 | ||
1669 | return ret; | |
d129bceb PO |
1670 | } |
1671 | ||
b8c86fc5 | 1672 | EXPORT_SYMBOL_GPL(sdhci_suspend_host); |
d129bceb | 1673 | |
b8c86fc5 PO |
1674 | int sdhci_resume_host(struct sdhci_host *host) |
1675 | { | |
1676 | int ret; | |
d129bceb | 1677 | |
9bea3c85 MS |
1678 | if (host->vmmc) { |
1679 | int ret = regulator_enable(host->vmmc); | |
1680 | if (ret) | |
1681 | return ret; | |
1682 | } | |
1683 | ||
1684 | ||
a13abc7b | 1685 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
b8c86fc5 PO |
1686 | if (host->ops->enable_dma) |
1687 | host->ops->enable_dma(host); | |
1688 | } | |
d129bceb | 1689 | |
b8c86fc5 PO |
1690 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, |
1691 | mmc_hostname(host->mmc), host); | |
df1c4b7b PO |
1692 | if (ret) |
1693 | return ret; | |
d129bceb | 1694 | |
2f4cbb3d | 1695 | sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); |
b8c86fc5 PO |
1696 | mmiowb(); |
1697 | ||
1698 | ret = mmc_resume_host(host->mmc); | |
7260cf5e AV |
1699 | sdhci_enable_card_detection(host); |
1700 | ||
2f4cbb3d | 1701 | return ret; |
d129bceb PO |
1702 | } |
1703 | ||
b8c86fc5 | 1704 | EXPORT_SYMBOL_GPL(sdhci_resume_host); |
d129bceb | 1705 | |
5f619704 DD |
1706 | void sdhci_enable_irq_wakeups(struct sdhci_host *host) |
1707 | { | |
1708 | u8 val; | |
1709 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); | |
1710 | val |= SDHCI_WAKE_ON_INT; | |
1711 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); | |
1712 | } | |
1713 | ||
1714 | EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); | |
1715 | ||
d129bceb PO |
1716 | #endif /* CONFIG_PM */ |
1717 | ||
1718 | /*****************************************************************************\ | |
1719 | * * | |
b8c86fc5 | 1720 | * Device allocation/registration * |
d129bceb PO |
1721 | * * |
1722 | \*****************************************************************************/ | |
1723 | ||
b8c86fc5 PO |
1724 | struct sdhci_host *sdhci_alloc_host(struct device *dev, |
1725 | size_t priv_size) | |
d129bceb | 1726 | { |
d129bceb PO |
1727 | struct mmc_host *mmc; |
1728 | struct sdhci_host *host; | |
1729 | ||
b8c86fc5 | 1730 | WARN_ON(dev == NULL); |
d129bceb | 1731 | |
b8c86fc5 | 1732 | mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); |
d129bceb | 1733 | if (!mmc) |
b8c86fc5 | 1734 | return ERR_PTR(-ENOMEM); |
d129bceb PO |
1735 | |
1736 | host = mmc_priv(mmc); | |
1737 | host->mmc = mmc; | |
1738 | ||
b8c86fc5 PO |
1739 | return host; |
1740 | } | |
8a4da143 | 1741 | |
b8c86fc5 | 1742 | EXPORT_SYMBOL_GPL(sdhci_alloc_host); |
d129bceb | 1743 | |
b8c86fc5 PO |
1744 | int sdhci_add_host(struct sdhci_host *host) |
1745 | { | |
1746 | struct mmc_host *mmc; | |
8f230f45 | 1747 | unsigned int caps, ocr_avail; |
b8c86fc5 | 1748 | int ret; |
d129bceb | 1749 | |
b8c86fc5 PO |
1750 | WARN_ON(host == NULL); |
1751 | if (host == NULL) | |
1752 | return -EINVAL; | |
d129bceb | 1753 | |
b8c86fc5 | 1754 | mmc = host->mmc; |
d129bceb | 1755 | |
b8c86fc5 PO |
1756 | if (debug_quirks) |
1757 | host->quirks = debug_quirks; | |
d129bceb | 1758 | |
d96649ed PO |
1759 | sdhci_reset(host, SDHCI_RESET_ALL); |
1760 | ||
4e4141a5 | 1761 | host->version = sdhci_readw(host, SDHCI_HOST_VERSION); |
2134a922 PO |
1762 | host->version = (host->version & SDHCI_SPEC_VER_MASK) |
1763 | >> SDHCI_SPEC_VER_SHIFT; | |
85105c53 | 1764 | if (host->version > SDHCI_SPEC_300) { |
4a965505 | 1765 | printk(KERN_ERR "%s: Unknown controller version (%d). " |
b69c9058 | 1766 | "You may experience problems.\n", mmc_hostname(mmc), |
2134a922 | 1767 | host->version); |
4a965505 PO |
1768 | } |
1769 | ||
ccc92c23 ML |
1770 | caps = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : |
1771 | sdhci_readl(host, SDHCI_CAPABILITIES); | |
d129bceb | 1772 | |
b8c86fc5 | 1773 | if (host->quirks & SDHCI_QUIRK_FORCE_DMA) |
a13abc7b RR |
1774 | host->flags |= SDHCI_USE_SDMA; |
1775 | else if (!(caps & SDHCI_CAN_DO_SDMA)) | |
1776 | DBG("Controller doesn't have SDMA capability\n"); | |
67435274 | 1777 | else |
a13abc7b | 1778 | host->flags |= SDHCI_USE_SDMA; |
d129bceb | 1779 | |
b8c86fc5 | 1780 | if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && |
a13abc7b | 1781 | (host->flags & SDHCI_USE_SDMA)) { |
cee687ce | 1782 | DBG("Disabling DMA as it is marked broken\n"); |
a13abc7b | 1783 | host->flags &= ~SDHCI_USE_SDMA; |
7c168e3d FT |
1784 | } |
1785 | ||
a13abc7b RR |
1786 | if ((host->version >= SDHCI_SPEC_200) && (caps & SDHCI_CAN_DO_ADMA2)) |
1787 | host->flags |= SDHCI_USE_ADMA; | |
2134a922 PO |
1788 | |
1789 | if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && | |
1790 | (host->flags & SDHCI_USE_ADMA)) { | |
1791 | DBG("Disabling ADMA as it is marked broken\n"); | |
1792 | host->flags &= ~SDHCI_USE_ADMA; | |
1793 | } | |
1794 | ||
a13abc7b | 1795 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
b8c86fc5 PO |
1796 | if (host->ops->enable_dma) { |
1797 | if (host->ops->enable_dma(host)) { | |
1798 | printk(KERN_WARNING "%s: No suitable DMA " | |
1799 | "available. Falling back to PIO.\n", | |
1800 | mmc_hostname(mmc)); | |
a13abc7b RR |
1801 | host->flags &= |
1802 | ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); | |
b8c86fc5 | 1803 | } |
d129bceb PO |
1804 | } |
1805 | } | |
1806 | ||
2134a922 PO |
1807 | if (host->flags & SDHCI_USE_ADMA) { |
1808 | /* | |
1809 | * We need to allocate descriptors for all sg entries | |
1810 | * (128) and potentially one alignment transfer for | |
1811 | * each of those entries. | |
1812 | */ | |
1813 | host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL); | |
1814 | host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); | |
1815 | if (!host->adma_desc || !host->align_buffer) { | |
1816 | kfree(host->adma_desc); | |
1817 | kfree(host->align_buffer); | |
1818 | printk(KERN_WARNING "%s: Unable to allocate ADMA " | |
1819 | "buffers. Falling back to standard DMA.\n", | |
1820 | mmc_hostname(mmc)); | |
1821 | host->flags &= ~SDHCI_USE_ADMA; | |
1822 | } | |
1823 | } | |
1824 | ||
7659150c PO |
1825 | /* |
1826 | * If we use DMA, then it's up to the caller to set the DMA | |
1827 | * mask, but PIO does not need the hw shim so we set a new | |
1828 | * mask here in that case. | |
1829 | */ | |
a13abc7b | 1830 | if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { |
7659150c PO |
1831 | host->dma_mask = DMA_BIT_MASK(64); |
1832 | mmc_dev(host->mmc)->dma_mask = &host->dma_mask; | |
1833 | } | |
d129bceb | 1834 | |
c4687d5f ZG |
1835 | if (host->version >= SDHCI_SPEC_300) |
1836 | host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) | |
1837 | >> SDHCI_CLOCK_BASE_SHIFT; | |
1838 | else | |
1839 | host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) | |
1840 | >> SDHCI_CLOCK_BASE_SHIFT; | |
1841 | ||
4240ff0a | 1842 | host->max_clk *= 1000000; |
f27f47ef AV |
1843 | if (host->max_clk == 0 || host->quirks & |
1844 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { | |
4240ff0a BD |
1845 | if (!host->ops->get_max_clock) { |
1846 | printk(KERN_ERR | |
1847 | "%s: Hardware doesn't specify base clock " | |
1848 | "frequency.\n", mmc_hostname(mmc)); | |
1849 | return -ENODEV; | |
1850 | } | |
1851 | host->max_clk = host->ops->get_max_clock(host); | |
8ef1a143 | 1852 | } |
d129bceb | 1853 | |
1c8cde92 PO |
1854 | host->timeout_clk = |
1855 | (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; | |
1856 | if (host->timeout_clk == 0) { | |
81b39802 AV |
1857 | if (host->ops->get_timeout_clock) { |
1858 | host->timeout_clk = host->ops->get_timeout_clock(host); | |
1859 | } else if (!(host->quirks & | |
1860 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { | |
4240ff0a BD |
1861 | printk(KERN_ERR |
1862 | "%s: Hardware doesn't specify timeout clock " | |
1863 | "frequency.\n", mmc_hostname(mmc)); | |
1864 | return -ENODEV; | |
1865 | } | |
1c8cde92 PO |
1866 | } |
1867 | if (caps & SDHCI_TIMEOUT_CLK_UNIT) | |
1868 | host->timeout_clk *= 1000; | |
d129bceb PO |
1869 | |
1870 | /* | |
1871 | * Set host parameters. | |
1872 | */ | |
1873 | mmc->ops = &sdhci_ops; | |
ce5f036b | 1874 | if (host->ops->get_min_clock) |
a9e58f25 | 1875 | mmc->f_min = host->ops->get_min_clock(host); |
0397526d ZG |
1876 | else if (host->version >= SDHCI_SPEC_300) |
1877 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; | |
a9e58f25 | 1878 | else |
0397526d | 1879 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; |
15ec4461 | 1880 | |
d129bceb | 1881 | mmc->f_max = host->max_clk; |
c1f5977c | 1882 | mmc->caps |= MMC_CAP_SDIO_IRQ; |
5fe23c7f | 1883 | |
15ec4461 PR |
1884 | /* |
1885 | * A controller may support 8-bit width, but the board itself | |
1886 | * might not have the pins brought out. Boards that support | |
1887 | * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in | |
1888 | * their platform code before calling sdhci_add_host(), and we | |
1889 | * won't assume 8-bit width for hosts without that CAP. | |
1890 | */ | |
5fe23c7f | 1891 | if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) |
15ec4461 | 1892 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
d129bceb | 1893 | |
86a6a874 | 1894 | if (caps & SDHCI_CAN_DO_HISPD) |
a29e7e18 | 1895 | mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; |
cd9277c0 | 1896 | |
176d1ed4 JC |
1897 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && |
1898 | mmc_card_is_removable(mmc)) | |
68d1fb7e AV |
1899 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
1900 | ||
8f230f45 | 1901 | ocr_avail = 0; |
146ad66e | 1902 | if (caps & SDHCI_CAN_VDD_330) |
8f230f45 | 1903 | ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; |
c70840e8 | 1904 | if (caps & SDHCI_CAN_VDD_300) |
8f230f45 | 1905 | ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; |
c70840e8 | 1906 | if (caps & SDHCI_CAN_VDD_180) |
8f230f45 TI |
1907 | ocr_avail |= MMC_VDD_165_195; |
1908 | ||
1909 | mmc->ocr_avail = ocr_avail; | |
1910 | mmc->ocr_avail_sdio = ocr_avail; | |
1911 | if (host->ocr_avail_sdio) | |
1912 | mmc->ocr_avail_sdio &= host->ocr_avail_sdio; | |
1913 | mmc->ocr_avail_sd = ocr_avail; | |
1914 | if (host->ocr_avail_sd) | |
1915 | mmc->ocr_avail_sd &= host->ocr_avail_sd; | |
1916 | else /* normal SD controllers don't support 1.8V */ | |
1917 | mmc->ocr_avail_sd &= ~MMC_VDD_165_195; | |
1918 | mmc->ocr_avail_mmc = ocr_avail; | |
1919 | if (host->ocr_avail_mmc) | |
1920 | mmc->ocr_avail_mmc &= host->ocr_avail_mmc; | |
146ad66e PO |
1921 | |
1922 | if (mmc->ocr_avail == 0) { | |
1923 | printk(KERN_ERR "%s: Hardware doesn't report any " | |
b69c9058 | 1924 | "support voltages.\n", mmc_hostname(mmc)); |
b8c86fc5 | 1925 | return -ENODEV; |
146ad66e PO |
1926 | } |
1927 | ||
d129bceb PO |
1928 | spin_lock_init(&host->lock); |
1929 | ||
1930 | /* | |
2134a922 PO |
1931 | * Maximum number of segments. Depends on if the hardware |
1932 | * can do scatter/gather or not. | |
d129bceb | 1933 | */ |
2134a922 | 1934 | if (host->flags & SDHCI_USE_ADMA) |
a36274e0 | 1935 | mmc->max_segs = 128; |
a13abc7b | 1936 | else if (host->flags & SDHCI_USE_SDMA) |
a36274e0 | 1937 | mmc->max_segs = 1; |
2134a922 | 1938 | else /* PIO */ |
a36274e0 | 1939 | mmc->max_segs = 128; |
d129bceb PO |
1940 | |
1941 | /* | |
bab76961 | 1942 | * Maximum number of sectors in one transfer. Limited by DMA boundary |
55db890a | 1943 | * size (512KiB). |
d129bceb | 1944 | */ |
55db890a | 1945 | mmc->max_req_size = 524288; |
d129bceb PO |
1946 | |
1947 | /* | |
1948 | * Maximum segment size. Could be one segment with the maximum number | |
2134a922 PO |
1949 | * of bytes. When doing hardware scatter/gather, each entry cannot |
1950 | * be larger than 64 KiB though. | |
d129bceb | 1951 | */ |
30652aa3 OJ |
1952 | if (host->flags & SDHCI_USE_ADMA) { |
1953 | if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) | |
1954 | mmc->max_seg_size = 65535; | |
1955 | else | |
1956 | mmc->max_seg_size = 65536; | |
1957 | } else { | |
2134a922 | 1958 | mmc->max_seg_size = mmc->max_req_size; |
30652aa3 | 1959 | } |
d129bceb | 1960 | |
fe4a3c7a PO |
1961 | /* |
1962 | * Maximum block size. This varies from controller to controller and | |
1963 | * is specified in the capabilities register. | |
1964 | */ | |
0633f654 AV |
1965 | if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { |
1966 | mmc->max_blk_size = 2; | |
1967 | } else { | |
1968 | mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> | |
1969 | SDHCI_MAX_BLOCK_SHIFT; | |
1970 | if (mmc->max_blk_size >= 3) { | |
1971 | printk(KERN_WARNING "%s: Invalid maximum block size, " | |
1972 | "assuming 512 bytes\n", mmc_hostname(mmc)); | |
1973 | mmc->max_blk_size = 0; | |
1974 | } | |
1975 | } | |
1976 | ||
1977 | mmc->max_blk_size = 512 << mmc->max_blk_size; | |
fe4a3c7a | 1978 | |
55db890a PO |
1979 | /* |
1980 | * Maximum block count. | |
1981 | */ | |
1388eefd | 1982 | mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; |
55db890a | 1983 | |
d129bceb PO |
1984 | /* |
1985 | * Init tasklets. | |
1986 | */ | |
1987 | tasklet_init(&host->card_tasklet, | |
1988 | sdhci_tasklet_card, (unsigned long)host); | |
1989 | tasklet_init(&host->finish_tasklet, | |
1990 | sdhci_tasklet_finish, (unsigned long)host); | |
1991 | ||
e4cad1b5 | 1992 | setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); |
d129bceb | 1993 | |
dace1453 | 1994 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, |
b69c9058 | 1995 | mmc_hostname(mmc), host); |
d129bceb | 1996 | if (ret) |
8ef1a143 | 1997 | goto untasklet; |
d129bceb | 1998 | |
9bea3c85 MS |
1999 | host->vmmc = regulator_get(mmc_dev(mmc), "vmmc"); |
2000 | if (IS_ERR(host->vmmc)) { | |
2001 | printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc)); | |
2002 | host->vmmc = NULL; | |
2003 | } else { | |
2004 | regulator_enable(host->vmmc); | |
2005 | } | |
2006 | ||
2f4cbb3d | 2007 | sdhci_init(host, 0); |
d129bceb PO |
2008 | |
2009 | #ifdef CONFIG_MMC_DEBUG | |
2010 | sdhci_dumpregs(host); | |
2011 | #endif | |
2012 | ||
f9134319 | 2013 | #ifdef SDHCI_USE_LEDS_CLASS |
5dbace0c HS |
2014 | snprintf(host->led_name, sizeof(host->led_name), |
2015 | "%s::", mmc_hostname(mmc)); | |
2016 | host->led.name = host->led_name; | |
2f730fec PO |
2017 | host->led.brightness = LED_OFF; |
2018 | host->led.default_trigger = mmc_hostname(mmc); | |
2019 | host->led.brightness_set = sdhci_led_control; | |
2020 | ||
b8c86fc5 | 2021 | ret = led_classdev_register(mmc_dev(mmc), &host->led); |
2f730fec PO |
2022 | if (ret) |
2023 | goto reset; | |
2024 | #endif | |
2025 | ||
5f25a66f PO |
2026 | mmiowb(); |
2027 | ||
d129bceb PO |
2028 | mmc_add_host(mmc); |
2029 | ||
a13abc7b | 2030 | printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n", |
d1b26863 | 2031 | mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), |
a13abc7b RR |
2032 | (host->flags & SDHCI_USE_ADMA) ? "ADMA" : |
2033 | (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); | |
d129bceb | 2034 | |
7260cf5e AV |
2035 | sdhci_enable_card_detection(host); |
2036 | ||
d129bceb PO |
2037 | return 0; |
2038 | ||
f9134319 | 2039 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
2040 | reset: |
2041 | sdhci_reset(host, SDHCI_RESET_ALL); | |
2042 | free_irq(host->irq, host); | |
2043 | #endif | |
8ef1a143 | 2044 | untasklet: |
d129bceb PO |
2045 | tasklet_kill(&host->card_tasklet); |
2046 | tasklet_kill(&host->finish_tasklet); | |
d129bceb PO |
2047 | |
2048 | return ret; | |
2049 | } | |
2050 | ||
b8c86fc5 | 2051 | EXPORT_SYMBOL_GPL(sdhci_add_host); |
d129bceb | 2052 | |
1e72859e | 2053 | void sdhci_remove_host(struct sdhci_host *host, int dead) |
b8c86fc5 | 2054 | { |
1e72859e PO |
2055 | unsigned long flags; |
2056 | ||
2057 | if (dead) { | |
2058 | spin_lock_irqsave(&host->lock, flags); | |
2059 | ||
2060 | host->flags |= SDHCI_DEVICE_DEAD; | |
2061 | ||
2062 | if (host->mrq) { | |
2063 | printk(KERN_ERR "%s: Controller removed during " | |
2064 | " transfer!\n", mmc_hostname(host->mmc)); | |
2065 | ||
2066 | host->mrq->cmd->error = -ENOMEDIUM; | |
2067 | tasklet_schedule(&host->finish_tasklet); | |
2068 | } | |
2069 | ||
2070 | spin_unlock_irqrestore(&host->lock, flags); | |
2071 | } | |
2072 | ||
7260cf5e AV |
2073 | sdhci_disable_card_detection(host); |
2074 | ||
b8c86fc5 | 2075 | mmc_remove_host(host->mmc); |
d129bceb | 2076 | |
f9134319 | 2077 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
2078 | led_classdev_unregister(&host->led); |
2079 | #endif | |
2080 | ||
1e72859e PO |
2081 | if (!dead) |
2082 | sdhci_reset(host, SDHCI_RESET_ALL); | |
d129bceb PO |
2083 | |
2084 | free_irq(host->irq, host); | |
2085 | ||
2086 | del_timer_sync(&host->timer); | |
2087 | ||
2088 | tasklet_kill(&host->card_tasklet); | |
2089 | tasklet_kill(&host->finish_tasklet); | |
2134a922 | 2090 | |
9bea3c85 MS |
2091 | if (host->vmmc) { |
2092 | regulator_disable(host->vmmc); | |
2093 | regulator_put(host->vmmc); | |
2094 | } | |
2095 | ||
2134a922 PO |
2096 | kfree(host->adma_desc); |
2097 | kfree(host->align_buffer); | |
2098 | ||
2099 | host->adma_desc = NULL; | |
2100 | host->align_buffer = NULL; | |
d129bceb PO |
2101 | } |
2102 | ||
b8c86fc5 | 2103 | EXPORT_SYMBOL_GPL(sdhci_remove_host); |
d129bceb | 2104 | |
b8c86fc5 | 2105 | void sdhci_free_host(struct sdhci_host *host) |
d129bceb | 2106 | { |
b8c86fc5 | 2107 | mmc_free_host(host->mmc); |
d129bceb PO |
2108 | } |
2109 | ||
b8c86fc5 | 2110 | EXPORT_SYMBOL_GPL(sdhci_free_host); |
d129bceb PO |
2111 | |
2112 | /*****************************************************************************\ | |
2113 | * * | |
2114 | * Driver init/exit * | |
2115 | * * | |
2116 | \*****************************************************************************/ | |
2117 | ||
2118 | static int __init sdhci_drv_init(void) | |
2119 | { | |
2120 | printk(KERN_INFO DRIVER_NAME | |
52fbf9c9 | 2121 | ": Secure Digital Host Controller Interface driver\n"); |
d129bceb PO |
2122 | printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); |
2123 | ||
b8c86fc5 | 2124 | return 0; |
d129bceb PO |
2125 | } |
2126 | ||
2127 | static void __exit sdhci_drv_exit(void) | |
2128 | { | |
d129bceb PO |
2129 | } |
2130 | ||
2131 | module_init(sdhci_drv_init); | |
2132 | module_exit(sdhci_drv_exit); | |
2133 | ||
df673b22 | 2134 | module_param(debug_quirks, uint, 0444); |
67435274 | 2135 | |
32710e8f | 2136 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
b8c86fc5 | 2137 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); |
d129bceb | 2138 | MODULE_LICENSE("GPL"); |
67435274 | 2139 | |
df673b22 | 2140 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |