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d129bceb | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver |
d129bceb | 3 | * |
b69c9058 | 4 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
d129bceb PO |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
643f720c PO |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or (at | |
9 | * your option) any later version. | |
d129bceb PO |
10 | */ |
11 | ||
0c7ad106 | 12 | #include <linux/scatterlist.h> |
4e4141a5 AV |
13 | #include <linux/compiler.h> |
14 | #include <linux/types.h> | |
15 | #include <linux/io.h> | |
0c7ad106 | 16 | |
d129bceb PO |
17 | /* |
18 | * Controller registers | |
19 | */ | |
20 | ||
21 | #define SDHCI_DMA_ADDRESS 0x00 | |
22 | ||
23 | #define SDHCI_BLOCK_SIZE 0x04 | |
bab76961 | 24 | #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) |
d129bceb PO |
25 | |
26 | #define SDHCI_BLOCK_COUNT 0x06 | |
27 | ||
28 | #define SDHCI_ARGUMENT 0x08 | |
29 | ||
30 | #define SDHCI_TRANSFER_MODE 0x0C | |
31 | #define SDHCI_TRNS_DMA 0x01 | |
32 | #define SDHCI_TRNS_BLK_CNT_EN 0x02 | |
33 | #define SDHCI_TRNS_ACMD12 0x04 | |
34 | #define SDHCI_TRNS_READ 0x10 | |
35 | #define SDHCI_TRNS_MULTI 0x20 | |
36 | ||
37 | #define SDHCI_COMMAND 0x0E | |
38 | #define SDHCI_CMD_RESP_MASK 0x03 | |
39 | #define SDHCI_CMD_CRC 0x08 | |
40 | #define SDHCI_CMD_INDEX 0x10 | |
41 | #define SDHCI_CMD_DATA 0x20 | |
42 | ||
43 | #define SDHCI_CMD_RESP_NONE 0x00 | |
44 | #define SDHCI_CMD_RESP_LONG 0x01 | |
45 | #define SDHCI_CMD_RESP_SHORT 0x02 | |
46 | #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 | |
47 | ||
48 | #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) | |
49 | ||
50 | #define SDHCI_RESPONSE 0x10 | |
51 | ||
52 | #define SDHCI_BUFFER 0x20 | |
53 | ||
54 | #define SDHCI_PRESENT_STATE 0x24 | |
55 | #define SDHCI_CMD_INHIBIT 0x00000001 | |
56 | #define SDHCI_DATA_INHIBIT 0x00000002 | |
57 | #define SDHCI_DOING_WRITE 0x00000100 | |
58 | #define SDHCI_DOING_READ 0x00000200 | |
59 | #define SDHCI_SPACE_AVAILABLE 0x00000400 | |
60 | #define SDHCI_DATA_AVAILABLE 0x00000800 | |
61 | #define SDHCI_CARD_PRESENT 0x00010000 | |
62 | #define SDHCI_WRITE_PROTECT 0x00080000 | |
63 | ||
64 | #define SDHCI_HOST_CONTROL 0x28 | |
65 | #define SDHCI_CTRL_LED 0x01 | |
66 | #define SDHCI_CTRL_4BITBUS 0x02 | |
077df884 | 67 | #define SDHCI_CTRL_HISPD 0x04 |
2134a922 PO |
68 | #define SDHCI_CTRL_DMA_MASK 0x18 |
69 | #define SDHCI_CTRL_SDMA 0x00 | |
70 | #define SDHCI_CTRL_ADMA1 0x08 | |
71 | #define SDHCI_CTRL_ADMA32 0x10 | |
72 | #define SDHCI_CTRL_ADMA64 0x18 | |
d129bceb PO |
73 | |
74 | #define SDHCI_POWER_CONTROL 0x29 | |
146ad66e PO |
75 | #define SDHCI_POWER_ON 0x01 |
76 | #define SDHCI_POWER_180 0x0A | |
77 | #define SDHCI_POWER_300 0x0C | |
78 | #define SDHCI_POWER_330 0x0E | |
d129bceb PO |
79 | |
80 | #define SDHCI_BLOCK_GAP_CONTROL 0x2A | |
81 | ||
2df3b71b | 82 | #define SDHCI_WAKE_UP_CONTROL 0x2B |
d129bceb PO |
83 | |
84 | #define SDHCI_CLOCK_CONTROL 0x2C | |
85 | #define SDHCI_DIVIDER_SHIFT 8 | |
86 | #define SDHCI_CLOCK_CARD_EN 0x0004 | |
87 | #define SDHCI_CLOCK_INT_STABLE 0x0002 | |
88 | #define SDHCI_CLOCK_INT_EN 0x0001 | |
89 | ||
90 | #define SDHCI_TIMEOUT_CONTROL 0x2E | |
91 | ||
92 | #define SDHCI_SOFTWARE_RESET 0x2F | |
93 | #define SDHCI_RESET_ALL 0x01 | |
94 | #define SDHCI_RESET_CMD 0x02 | |
95 | #define SDHCI_RESET_DATA 0x04 | |
96 | ||
97 | #define SDHCI_INT_STATUS 0x30 | |
98 | #define SDHCI_INT_ENABLE 0x34 | |
99 | #define SDHCI_SIGNAL_ENABLE 0x38 | |
100 | #define SDHCI_INT_RESPONSE 0x00000001 | |
101 | #define SDHCI_INT_DATA_END 0x00000002 | |
102 | #define SDHCI_INT_DMA_END 0x00000008 | |
a406f5a3 PO |
103 | #define SDHCI_INT_SPACE_AVAIL 0x00000010 |
104 | #define SDHCI_INT_DATA_AVAIL 0x00000020 | |
d129bceb PO |
105 | #define SDHCI_INT_CARD_INSERT 0x00000040 |
106 | #define SDHCI_INT_CARD_REMOVE 0x00000080 | |
107 | #define SDHCI_INT_CARD_INT 0x00000100 | |
964f9ce2 | 108 | #define SDHCI_INT_ERROR 0x00008000 |
d129bceb PO |
109 | #define SDHCI_INT_TIMEOUT 0x00010000 |
110 | #define SDHCI_INT_CRC 0x00020000 | |
111 | #define SDHCI_INT_END_BIT 0x00040000 | |
112 | #define SDHCI_INT_INDEX 0x00080000 | |
113 | #define SDHCI_INT_DATA_TIMEOUT 0x00100000 | |
114 | #define SDHCI_INT_DATA_CRC 0x00200000 | |
115 | #define SDHCI_INT_DATA_END_BIT 0x00400000 | |
116 | #define SDHCI_INT_BUS_POWER 0x00800000 | |
117 | #define SDHCI_INT_ACMD12ERR 0x01000000 | |
2134a922 | 118 | #define SDHCI_INT_ADMA_ERROR 0x02000000 |
d129bceb PO |
119 | |
120 | #define SDHCI_INT_NORMAL_MASK 0x00007FFF | |
121 | #define SDHCI_INT_ERROR_MASK 0xFFFF8000 | |
122 | ||
123 | #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ | |
124 | SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) | |
125 | #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ | |
a406f5a3 | 126 | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ |
d129bceb PO |
127 | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ |
128 | SDHCI_INT_DATA_END_BIT) | |
7260cf5e | 129 | #define SDHCI_INT_ALL_MASK ((unsigned int)-1) |
d129bceb PO |
130 | |
131 | #define SDHCI_ACMD12_ERR 0x3C | |
132 | ||
133 | /* 3E-3F reserved */ | |
134 | ||
135 | #define SDHCI_CAPABILITIES 0x40 | |
1c8cde92 PO |
136 | #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F |
137 | #define SDHCI_TIMEOUT_CLK_SHIFT 0 | |
138 | #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 | |
d129bceb PO |
139 | #define SDHCI_CLOCK_BASE_MASK 0x00003F00 |
140 | #define SDHCI_CLOCK_BASE_SHIFT 8 | |
1d676e02 PO |
141 | #define SDHCI_MAX_BLOCK_MASK 0x00030000 |
142 | #define SDHCI_MAX_BLOCK_SHIFT 16 | |
2134a922 PO |
143 | #define SDHCI_CAN_DO_ADMA2 0x00080000 |
144 | #define SDHCI_CAN_DO_ADMA1 0x00100000 | |
077df884 | 145 | #define SDHCI_CAN_DO_HISPD 0x00200000 |
146ad66e PO |
146 | #define SDHCI_CAN_DO_DMA 0x00400000 |
147 | #define SDHCI_CAN_VDD_330 0x01000000 | |
148 | #define SDHCI_CAN_VDD_300 0x02000000 | |
149 | #define SDHCI_CAN_VDD_180 0x04000000 | |
2134a922 | 150 | #define SDHCI_CAN_64BIT 0x10000000 |
d129bceb PO |
151 | |
152 | /* 44-47 reserved for more caps */ | |
153 | ||
154 | #define SDHCI_MAX_CURRENT 0x48 | |
155 | ||
156 | /* 4C-4F reserved for more max current */ | |
157 | ||
2134a922 PO |
158 | #define SDHCI_SET_ACMD12_ERROR 0x50 |
159 | #define SDHCI_SET_INT_ERROR 0x52 | |
160 | ||
161 | #define SDHCI_ADMA_ERROR 0x54 | |
162 | ||
163 | /* 55-57 reserved */ | |
164 | ||
165 | #define SDHCI_ADMA_ADDRESS 0x58 | |
166 | ||
167 | /* 60-FB reserved */ | |
d129bceb PO |
168 | |
169 | #define SDHCI_SLOT_INT_STATUS 0xFC | |
170 | ||
171 | #define SDHCI_HOST_VERSION 0xFE | |
4a965505 PO |
172 | #define SDHCI_VENDOR_VER_MASK 0xFF00 |
173 | #define SDHCI_VENDOR_VER_SHIFT 8 | |
174 | #define SDHCI_SPEC_VER_MASK 0x00FF | |
175 | #define SDHCI_SPEC_VER_SHIFT 0 | |
2134a922 PO |
176 | #define SDHCI_SPEC_100 0 |
177 | #define SDHCI_SPEC_200 1 | |
d129bceb | 178 | |
b8c86fc5 | 179 | struct sdhci_ops; |
d129bceb PO |
180 | |
181 | struct sdhci_host { | |
b8c86fc5 PO |
182 | /* Data set by hardware interface driver */ |
183 | const char *hw_name; /* Hardware bus name */ | |
184 | ||
185 | unsigned int quirks; /* Deviations from spec. */ | |
186 | ||
187 | /* Controller doesn't honor resets unless we touch the clock register */ | |
188 | #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) | |
189 | /* Controller has bad caps bits, but really supports DMA */ | |
190 | #define SDHCI_QUIRK_FORCE_DMA (1<<1) | |
191 | /* Controller doesn't like to be reset when there is no card inserted. */ | |
192 | #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) | |
193 | /* Controller doesn't like clearing the power reg before a change */ | |
194 | #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) | |
195 | /* Controller has flaky internal state so reset it on each ios change */ | |
196 | #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) | |
197 | /* Controller has an unusable DMA engine */ | |
198 | #define SDHCI_QUIRK_BROKEN_DMA (1<<5) | |
2134a922 PO |
199 | /* Controller has an unusable ADMA engine */ |
200 | #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) | |
b8c86fc5 | 201 | /* Controller can only DMA from 32-bit aligned addresses */ |
2134a922 | 202 | #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) |
b8c86fc5 | 203 | /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ |
2134a922 PO |
204 | #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) |
205 | /* Controller can only ADMA chunks that are a multiple of 32 bits */ | |
206 | #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) | |
b8c86fc5 | 207 | /* Controller needs to be reset after each request to stay stable */ |
2134a922 | 208 | #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) |
b8c86fc5 | 209 | /* Controller needs voltage and power writes to happen separately */ |
2134a922 | 210 | #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) |
ee53ab5d | 211 | /* Controller provides an incorrect timeout value for transfers */ |
2134a922 | 212 | #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) |
4a3cba32 PO |
213 | /* Controller has an issue with buffer bits for small transfers */ |
214 | #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) | |
f945405c BD |
215 | /* Controller does not provide transfer-complete interrupt when not busy */ |
216 | #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) | |
68d1fb7e AV |
217 | /* Controller has unreliable card detection */ |
218 | #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) | |
c5075a10 AV |
219 | /* Controller reports inverted write-protect state */ |
220 | #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) | |
b8c86fc5 PO |
221 | |
222 | int irq; /* Device IRQ */ | |
223 | void __iomem * ioaddr; /* Mapped address */ | |
224 | ||
225 | const struct sdhci_ops *ops; /* Low level hw interface */ | |
226 | ||
227 | /* Internal data */ | |
d129bceb | 228 | struct mmc_host *mmc; /* MMC structure */ |
7659150c | 229 | u64 dma_mask; /* custom DMA mask */ |
d129bceb | 230 | |
35ff8554 | 231 | #if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) |
2f730fec | 232 | struct led_classdev led; /* LED control */ |
5dbace0c | 233 | char led_name[32]; |
2f730fec PO |
234 | #endif |
235 | ||
d129bceb PO |
236 | spinlock_t lock; /* Mutex */ |
237 | ||
238 | int flags; /* Host attributes */ | |
c9fddbc4 | 239 | #define SDHCI_USE_DMA (1<<0) /* Host is DMA capable */ |
2134a922 PO |
240 | #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ |
241 | #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ | |
242 | #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ | |
243 | ||
244 | unsigned int version; /* SDHCI spec. version */ | |
d129bceb PO |
245 | |
246 | unsigned int max_clk; /* Max possible freq (MHz) */ | |
1c8cde92 | 247 | unsigned int timeout_clk; /* Timeout freq (KHz) */ |
d129bceb PO |
248 | |
249 | unsigned int clock; /* Current clock (MHz) */ | |
146ad66e | 250 | unsigned short power; /* Current voltage */ |
d129bceb PO |
251 | |
252 | struct mmc_request *mrq; /* Current request */ | |
253 | struct mmc_command *cmd; /* Current command */ | |
254 | struct mmc_data *data; /* Current data request */ | |
55654be9 | 255 | unsigned int data_early:1; /* Data finished before cmd */ |
d129bceb | 256 | |
7659150c PO |
257 | struct sg_mapping_iter sg_miter; /* SG state for PIO */ |
258 | unsigned int blocks; /* remaining PIO blocks */ | |
d129bceb | 259 | |
2134a922 PO |
260 | int sg_count; /* Mapped sg entries */ |
261 | ||
262 | u8 *adma_desc; /* ADMA descriptor table */ | |
263 | u8 *align_buffer; /* Bounce buffer */ | |
264 | ||
265 | dma_addr_t adma_addr; /* Mapped ADMA descr. table */ | |
266 | dma_addr_t align_addr; /* Mapped bounce buffer */ | |
267 | ||
d129bceb PO |
268 | struct tasklet_struct card_tasklet; /* Tasklet structures */ |
269 | struct tasklet_struct finish_tasklet; | |
270 | ||
271 | struct timer_list timer; /* Timer for timeouts */ | |
d129bceb | 272 | |
b8c86fc5 PO |
273 | unsigned long private[0] ____cacheline_aligned; |
274 | }; | |
d129bceb | 275 | |
df673b22 | 276 | |
b8c86fc5 | 277 | struct sdhci_ops { |
4e4141a5 AV |
278 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
279 | u32 (*readl)(struct sdhci_host *host, int reg); | |
280 | u16 (*readw)(struct sdhci_host *host, int reg); | |
281 | u8 (*readb)(struct sdhci_host *host, int reg); | |
282 | void (*writel)(struct sdhci_host *host, u32 val, int reg); | |
283 | void (*writew)(struct sdhci_host *host, u16 val, int reg); | |
284 | void (*writeb)(struct sdhci_host *host, u8 val, int reg); | |
285 | #endif | |
286 | ||
b8c86fc5 | 287 | int (*enable_dma)(struct sdhci_host *host); |
4240ff0a BD |
288 | unsigned int (*get_max_clock)(struct sdhci_host *host); |
289 | unsigned int (*get_timeout_clock)(struct sdhci_host *host); | |
d129bceb | 290 | }; |
b8c86fc5 | 291 | |
4e4141a5 AV |
292 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
293 | ||
294 | static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) | |
295 | { | |
296 | if (unlikely(host->ops->writel)) | |
297 | host->ops->writel(host, val, reg); | |
298 | else | |
299 | writel(val, host->ioaddr + reg); | |
300 | } | |
301 | ||
302 | static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) | |
303 | { | |
304 | if (unlikely(host->ops->writew)) | |
305 | host->ops->writew(host, val, reg); | |
306 | else | |
307 | writew(val, host->ioaddr + reg); | |
308 | } | |
309 | ||
310 | static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) | |
311 | { | |
312 | if (unlikely(host->ops->writeb)) | |
313 | host->ops->writeb(host, val, reg); | |
314 | else | |
315 | writeb(val, host->ioaddr + reg); | |
316 | } | |
317 | ||
318 | static inline u32 sdhci_readl(struct sdhci_host *host, int reg) | |
319 | { | |
320 | if (unlikely(host->ops->readl)) | |
321 | return host->ops->readl(host, reg); | |
322 | else | |
323 | return readl(host->ioaddr + reg); | |
324 | } | |
325 | ||
326 | static inline u16 sdhci_readw(struct sdhci_host *host, int reg) | |
327 | { | |
328 | if (unlikely(host->ops->readw)) | |
329 | return host->ops->readw(host, reg); | |
330 | else | |
331 | return readw(host->ioaddr + reg); | |
332 | } | |
333 | ||
334 | static inline u8 sdhci_readb(struct sdhci_host *host, int reg) | |
335 | { | |
336 | if (unlikely(host->ops->readb)) | |
337 | return host->ops->readb(host, reg); | |
338 | else | |
339 | return readb(host->ioaddr + reg); | |
340 | } | |
341 | ||
342 | #else | |
343 | ||
344 | static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) | |
345 | { | |
346 | writel(val, host->ioaddr + reg); | |
347 | } | |
348 | ||
349 | static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) | |
350 | { | |
351 | writew(val, host->ioaddr + reg); | |
352 | } | |
353 | ||
354 | static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) | |
355 | { | |
356 | writeb(val, host->ioaddr + reg); | |
357 | } | |
358 | ||
359 | static inline u32 sdhci_readl(struct sdhci_host *host, int reg) | |
360 | { | |
361 | return readl(host->ioaddr + reg); | |
362 | } | |
363 | ||
364 | static inline u16 sdhci_readw(struct sdhci_host *host, int reg) | |
365 | { | |
366 | return readw(host->ioaddr + reg); | |
367 | } | |
368 | ||
369 | static inline u8 sdhci_readb(struct sdhci_host *host, int reg) | |
370 | { | |
371 | return readb(host->ioaddr + reg); | |
372 | } | |
373 | ||
374 | #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ | |
b8c86fc5 PO |
375 | |
376 | extern struct sdhci_host *sdhci_alloc_host(struct device *dev, | |
377 | size_t priv_size); | |
378 | extern void sdhci_free_host(struct sdhci_host *host); | |
379 | ||
380 | static inline void *sdhci_priv(struct sdhci_host *host) | |
381 | { | |
382 | return (void *)host->private; | |
383 | } | |
384 | ||
385 | extern int sdhci_add_host(struct sdhci_host *host); | |
1e72859e | 386 | extern void sdhci_remove_host(struct sdhci_host *host, int dead); |
b8c86fc5 PO |
387 | |
388 | #ifdef CONFIG_PM | |
389 | extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state); | |
390 | extern int sdhci_resume_host(struct sdhci_host *host); | |
391 | #endif |