Commit | Line | Data |
---|---|---|
fdc50a94 YG |
1 | /* |
2 | * MMCIF eMMC driver. | |
3 | * | |
4 | * Copyright (C) 2010 Renesas Solutions Corp. | |
5 | * Yusuke Goda <yusuke.goda.sx@renesas.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License. | |
10 | * | |
11 | * | |
12 | * TODO | |
13 | * 1. DMA | |
14 | * 2. Power management | |
15 | * 3. Handle MMC errors better | |
16 | * | |
17 | */ | |
18 | ||
f985da17 GL |
19 | /* |
20 | * The MMCIF driver is now processing MMC requests asynchronously, according | |
21 | * to the Linux MMC API requirement. | |
22 | * | |
23 | * The MMCIF driver processes MMC requests in up to 3 stages: command, optional | |
24 | * data, and optional stop. To achieve asynchronous processing each of these | |
25 | * stages is split into two halves: a top and a bottom half. The top half | |
26 | * initialises the hardware, installs a timeout handler to handle completion | |
27 | * timeouts, and returns. In case of the command stage this immediately returns | |
28 | * control to the caller, leaving all further processing to run asynchronously. | |
29 | * All further request processing is performed by the bottom halves. | |
30 | * | |
31 | * The bottom half further consists of a "hard" IRQ handler, an IRQ handler | |
32 | * thread, a DMA completion callback, if DMA is used, a timeout work, and | |
33 | * request- and stage-specific handler methods. | |
34 | * | |
35 | * Each bottom half run begins with either a hardware interrupt, a DMA callback | |
36 | * invocation, or a timeout work run. In case of an error or a successful | |
37 | * processing completion, the MMC core is informed and the request processing is | |
38 | * finished. In case processing has to continue, i.e., if data has to be read | |
39 | * from or written to the card, or if a stop command has to be sent, the next | |
40 | * top half is called, which performs the necessary hardware handling and | |
41 | * reschedules the timeout work. This returns the driver state machine into the | |
42 | * bottom half waiting state. | |
43 | */ | |
44 | ||
86df1745 | 45 | #include <linux/bitops.h> |
aa0787a9 GL |
46 | #include <linux/clk.h> |
47 | #include <linux/completion.h> | |
e47bf32a | 48 | #include <linux/delay.h> |
fdc50a94 | 49 | #include <linux/dma-mapping.h> |
a782d688 | 50 | #include <linux/dmaengine.h> |
fdc50a94 YG |
51 | #include <linux/mmc/card.h> |
52 | #include <linux/mmc/core.h> | |
e47bf32a | 53 | #include <linux/mmc/host.h> |
fdc50a94 YG |
54 | #include <linux/mmc/mmc.h> |
55 | #include <linux/mmc/sdio.h> | |
fdc50a94 | 56 | #include <linux/mmc/sh_mmcif.h> |
e480606a | 57 | #include <linux/mmc/slot-gpio.h> |
bf68a812 | 58 | #include <linux/mod_devicetable.h> |
8047310e | 59 | #include <linux/mutex.h> |
89d49a70 | 60 | #include <linux/of_device.h> |
a782d688 | 61 | #include <linux/pagemap.h> |
e47bf32a | 62 | #include <linux/platform_device.h> |
efe6a8ad | 63 | #include <linux/pm_qos.h> |
faca6648 | 64 | #include <linux/pm_runtime.h> |
d00cadac | 65 | #include <linux/sh_dma.h> |
3b0beafc | 66 | #include <linux/spinlock.h> |
88b47679 | 67 | #include <linux/module.h> |
fdc50a94 YG |
68 | |
69 | #define DRIVER_NAME "sh_mmcif" | |
70 | #define DRIVER_VERSION "2010-04-28" | |
71 | ||
fdc50a94 YG |
72 | /* CE_CMD_SET */ |
73 | #define CMD_MASK 0x3f000000 | |
74 | #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) | |
75 | #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ | |
76 | #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ | |
77 | #define CMD_SET_RBSY (1 << 21) /* R1b */ | |
78 | #define CMD_SET_CCSEN (1 << 20) | |
79 | #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ | |
80 | #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ | |
81 | #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ | |
82 | #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ | |
83 | #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ | |
84 | #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ | |
85 | #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ | |
86 | #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ | |
87 | #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ | |
88 | #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ | |
89 | #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ | |
90 | #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ | |
91 | #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ | |
92 | #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ | |
93 | #define CMD_SET_CCSH (1 << 5) | |
555061f9 | 94 | #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */ |
fdc50a94 YG |
95 | #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ |
96 | #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ | |
97 | #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ | |
98 | ||
99 | /* CE_CMD_CTRL */ | |
100 | #define CMD_CTRL_BREAK (1 << 0) | |
101 | ||
102 | /* CE_BLOCK_SET */ | |
103 | #define BLOCK_SIZE_MASK 0x0000ffff | |
104 | ||
fdc50a94 YG |
105 | /* CE_INT */ |
106 | #define INT_CCSDE (1 << 29) | |
107 | #define INT_CMD12DRE (1 << 26) | |
108 | #define INT_CMD12RBE (1 << 25) | |
109 | #define INT_CMD12CRE (1 << 24) | |
110 | #define INT_DTRANE (1 << 23) | |
111 | #define INT_BUFRE (1 << 22) | |
112 | #define INT_BUFWEN (1 << 21) | |
113 | #define INT_BUFREN (1 << 20) | |
114 | #define INT_CCSRCV (1 << 19) | |
115 | #define INT_RBSYE (1 << 17) | |
116 | #define INT_CRSPE (1 << 16) | |
117 | #define INT_CMDVIO (1 << 15) | |
118 | #define INT_BUFVIO (1 << 14) | |
119 | #define INT_WDATERR (1 << 11) | |
120 | #define INT_RDATERR (1 << 10) | |
121 | #define INT_RIDXERR (1 << 9) | |
122 | #define INT_RSPERR (1 << 8) | |
123 | #define INT_CCSTO (1 << 5) | |
124 | #define INT_CRCSTO (1 << 4) | |
125 | #define INT_WDATTO (1 << 3) | |
126 | #define INT_RDATTO (1 << 2) | |
127 | #define INT_RBSYTO (1 << 1) | |
128 | #define INT_RSPTO (1 << 0) | |
129 | #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ | |
130 | INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ | |
131 | INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ | |
132 | INT_RDATTO | INT_RBSYTO | INT_RSPTO) | |
133 | ||
8af50750 GL |
134 | #define INT_ALL (INT_RBSYE | INT_CRSPE | INT_BUFREN | \ |
135 | INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \ | |
136 | INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE) | |
137 | ||
967bcb77 GL |
138 | #define INT_CCS (INT_CCSTO | INT_CCSRCV | INT_CCSDE) |
139 | ||
fdc50a94 YG |
140 | /* CE_INT_MASK */ |
141 | #define MASK_ALL 0x00000000 | |
142 | #define MASK_MCCSDE (1 << 29) | |
143 | #define MASK_MCMD12DRE (1 << 26) | |
144 | #define MASK_MCMD12RBE (1 << 25) | |
145 | #define MASK_MCMD12CRE (1 << 24) | |
146 | #define MASK_MDTRANE (1 << 23) | |
147 | #define MASK_MBUFRE (1 << 22) | |
148 | #define MASK_MBUFWEN (1 << 21) | |
149 | #define MASK_MBUFREN (1 << 20) | |
150 | #define MASK_MCCSRCV (1 << 19) | |
151 | #define MASK_MRBSYE (1 << 17) | |
152 | #define MASK_MCRSPE (1 << 16) | |
153 | #define MASK_MCMDVIO (1 << 15) | |
154 | #define MASK_MBUFVIO (1 << 14) | |
155 | #define MASK_MWDATERR (1 << 11) | |
156 | #define MASK_MRDATERR (1 << 10) | |
157 | #define MASK_MRIDXERR (1 << 9) | |
158 | #define MASK_MRSPERR (1 << 8) | |
159 | #define MASK_MCCSTO (1 << 5) | |
160 | #define MASK_MCRCSTO (1 << 4) | |
161 | #define MASK_MWDATTO (1 << 3) | |
162 | #define MASK_MRDATTO (1 << 2) | |
163 | #define MASK_MRBSYTO (1 << 1) | |
164 | #define MASK_MRSPTO (1 << 0) | |
165 | ||
ee4b8887 GL |
166 | #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ |
167 | MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ | |
967bcb77 | 168 | MASK_MCRCSTO | MASK_MWDATTO | \ |
ee4b8887 GL |
169 | MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) |
170 | ||
8af50750 GL |
171 | #define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \ |
172 | MASK_MBUFREN | MASK_MBUFWEN | \ | |
173 | MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE | \ | |
174 | MASK_MCMD12RBE | MASK_MCMD12CRE) | |
175 | ||
fdc50a94 YG |
176 | /* CE_HOST_STS1 */ |
177 | #define STS1_CMDSEQ (1 << 31) | |
178 | ||
179 | /* CE_HOST_STS2 */ | |
180 | #define STS2_CRCSTE (1 << 31) | |
181 | #define STS2_CRC16E (1 << 30) | |
182 | #define STS2_AC12CRCE (1 << 29) | |
183 | #define STS2_RSPCRC7E (1 << 28) | |
184 | #define STS2_CRCSTEBE (1 << 27) | |
185 | #define STS2_RDATEBE (1 << 26) | |
186 | #define STS2_AC12REBE (1 << 25) | |
187 | #define STS2_RSPEBE (1 << 24) | |
188 | #define STS2_AC12IDXE (1 << 23) | |
189 | #define STS2_RSPIDXE (1 << 22) | |
190 | #define STS2_CCSTO (1 << 15) | |
191 | #define STS2_RDATTO (1 << 14) | |
192 | #define STS2_DATBSYTO (1 << 13) | |
193 | #define STS2_CRCSTTO (1 << 12) | |
194 | #define STS2_AC12BSYTO (1 << 11) | |
195 | #define STS2_RSPBSYTO (1 << 10) | |
196 | #define STS2_AC12RSPTO (1 << 9) | |
197 | #define STS2_RSPTO (1 << 8) | |
198 | #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ | |
199 | STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) | |
200 | #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ | |
201 | STS2_DATBSYTO | STS2_CRCSTTO | \ | |
202 | STS2_AC12BSYTO | STS2_RSPBSYTO | \ | |
203 | STS2_AC12RSPTO | STS2_RSPTO) | |
204 | ||
fdc50a94 YG |
205 | #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ |
206 | #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ | |
207 | #define CLKDEV_INIT 400000 /* 400 KHz */ | |
208 | ||
1b1a694d | 209 | enum sh_mmcif_state { |
3b0beafc GL |
210 | STATE_IDLE, |
211 | STATE_REQUEST, | |
212 | STATE_IOS, | |
8047310e | 213 | STATE_TIMEOUT, |
3b0beafc GL |
214 | }; |
215 | ||
1b1a694d | 216 | enum sh_mmcif_wait_for { |
f985da17 GL |
217 | MMCIF_WAIT_FOR_REQUEST, |
218 | MMCIF_WAIT_FOR_CMD, | |
219 | MMCIF_WAIT_FOR_MREAD, | |
220 | MMCIF_WAIT_FOR_MWRITE, | |
221 | MMCIF_WAIT_FOR_READ, | |
222 | MMCIF_WAIT_FOR_WRITE, | |
223 | MMCIF_WAIT_FOR_READ_END, | |
224 | MMCIF_WAIT_FOR_WRITE_END, | |
225 | MMCIF_WAIT_FOR_STOP, | |
226 | }; | |
227 | ||
89d49a70 KM |
228 | /* |
229 | * difference for each SoC | |
230 | */ | |
fdc50a94 YG |
231 | struct sh_mmcif_host { |
232 | struct mmc_host *mmc; | |
f985da17 | 233 | struct mmc_request *mrq; |
fdc50a94 | 234 | struct platform_device *pd; |
6aed678b | 235 | struct clk *clk; |
fdc50a94 | 236 | int bus_width; |
555061f9 | 237 | unsigned char timing; |
aa0787a9 | 238 | bool sd_error; |
f985da17 | 239 | bool dying; |
fdc50a94 YG |
240 | long timeout; |
241 | void __iomem *addr; | |
f985da17 | 242 | u32 *pio_ptr; |
ee4b8887 | 243 | spinlock_t lock; /* protect sh_mmcif_host::state */ |
1b1a694d KM |
244 | enum sh_mmcif_state state; |
245 | enum sh_mmcif_wait_for wait_for; | |
f985da17 GL |
246 | struct delayed_work timeout_work; |
247 | size_t blocksize; | |
248 | int sg_idx; | |
249 | int sg_blkidx; | |
faca6648 | 250 | bool power; |
967bcb77 | 251 | bool ccs_enable; /* Command Completion Signal support */ |
6d6fd367 | 252 | bool clk_ctrl2_enable; |
8047310e | 253 | struct mutex thread_lock; |
89d49a70 | 254 | u32 clkdiv_map; /* see CE_CLK_CTRL::CLKDIV */ |
fdc50a94 | 255 | |
a782d688 GL |
256 | /* DMA support */ |
257 | struct dma_chan *chan_rx; | |
258 | struct dma_chan *chan_tx; | |
259 | struct completion dma_complete; | |
f38f94c6 | 260 | bool dma_active; |
a782d688 | 261 | }; |
fdc50a94 | 262 | |
1b1a694d | 263 | static const struct of_device_id sh_mmcif_of_match[] = { |
70830b41 KM |
264 | { .compatible = "renesas,sh-mmcif" }, |
265 | { } | |
266 | }; | |
1b1a694d | 267 | MODULE_DEVICE_TABLE(of, sh_mmcif_of_match); |
70830b41 | 268 | |
585c3a5a KM |
269 | #define sh_mmcif_host_to_dev(host) (&host->pd->dev) |
270 | ||
fdc50a94 YG |
271 | static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, |
272 | unsigned int reg, u32 val) | |
273 | { | |
487d9fc5 | 274 | writel(val | readl(host->addr + reg), host->addr + reg); |
fdc50a94 YG |
275 | } |
276 | ||
277 | static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, | |
278 | unsigned int reg, u32 val) | |
279 | { | |
487d9fc5 | 280 | writel(~val & readl(host->addr + reg), host->addr + reg); |
fdc50a94 YG |
281 | } |
282 | ||
1b1a694d | 283 | static void sh_mmcif_dma_complete(void *arg) |
a782d688 GL |
284 | { |
285 | struct sh_mmcif_host *host = arg; | |
8047310e | 286 | struct mmc_request *mrq = host->mrq; |
585c3a5a | 287 | struct device *dev = sh_mmcif_host_to_dev(host); |
69983404 | 288 | |
585c3a5a | 289 | dev_dbg(dev, "Command completed\n"); |
a782d688 | 290 | |
8047310e | 291 | if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n", |
585c3a5a | 292 | dev_name(dev))) |
a782d688 GL |
293 | return; |
294 | ||
a782d688 GL |
295 | complete(&host->dma_complete); |
296 | } | |
297 | ||
298 | static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) | |
299 | { | |
69983404 GL |
300 | struct mmc_data *data = host->mrq->data; |
301 | struct scatterlist *sg = data->sg; | |
a782d688 GL |
302 | struct dma_async_tx_descriptor *desc = NULL; |
303 | struct dma_chan *chan = host->chan_rx; | |
585c3a5a | 304 | struct device *dev = sh_mmcif_host_to_dev(host); |
a782d688 GL |
305 | dma_cookie_t cookie = -EINVAL; |
306 | int ret; | |
307 | ||
69983404 | 308 | ret = dma_map_sg(chan->device->dev, sg, data->sg_len, |
1ed828db | 309 | DMA_FROM_DEVICE); |
a782d688 | 310 | if (ret > 0) { |
f38f94c6 | 311 | host->dma_active = true; |
16052827 | 312 | desc = dmaengine_prep_slave_sg(chan, sg, ret, |
05f5799c | 313 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
a782d688 GL |
314 | } |
315 | ||
316 | if (desc) { | |
1b1a694d | 317 | desc->callback = sh_mmcif_dma_complete; |
a782d688 | 318 | desc->callback_param = host; |
a5ece7d2 LW |
319 | cookie = dmaengine_submit(desc); |
320 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); | |
321 | dma_async_issue_pending(chan); | |
a782d688 | 322 | } |
585c3a5a | 323 | dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n", |
69983404 | 324 | __func__, data->sg_len, ret, cookie); |
a782d688 GL |
325 | |
326 | if (!desc) { | |
327 | /* DMA failed, fall back to PIO */ | |
328 | if (ret >= 0) | |
329 | ret = -EIO; | |
330 | host->chan_rx = NULL; | |
f38f94c6 | 331 | host->dma_active = false; |
a782d688 GL |
332 | dma_release_channel(chan); |
333 | /* Free the Tx channel too */ | |
334 | chan = host->chan_tx; | |
335 | if (chan) { | |
336 | host->chan_tx = NULL; | |
337 | dma_release_channel(chan); | |
338 | } | |
585c3a5a | 339 | dev_warn(dev, |
a782d688 GL |
340 | "DMA failed: %d, falling back to PIO\n", ret); |
341 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
342 | } | |
343 | ||
585c3a5a | 344 | dev_dbg(dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, |
69983404 | 345 | desc, cookie, data->sg_len); |
a782d688 GL |
346 | } |
347 | ||
348 | static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) | |
349 | { | |
69983404 GL |
350 | struct mmc_data *data = host->mrq->data; |
351 | struct scatterlist *sg = data->sg; | |
a782d688 GL |
352 | struct dma_async_tx_descriptor *desc = NULL; |
353 | struct dma_chan *chan = host->chan_tx; | |
585c3a5a | 354 | struct device *dev = sh_mmcif_host_to_dev(host); |
a782d688 GL |
355 | dma_cookie_t cookie = -EINVAL; |
356 | int ret; | |
357 | ||
69983404 | 358 | ret = dma_map_sg(chan->device->dev, sg, data->sg_len, |
1ed828db | 359 | DMA_TO_DEVICE); |
a782d688 | 360 | if (ret > 0) { |
f38f94c6 | 361 | host->dma_active = true; |
16052827 | 362 | desc = dmaengine_prep_slave_sg(chan, sg, ret, |
05f5799c | 363 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
a782d688 GL |
364 | } |
365 | ||
366 | if (desc) { | |
1b1a694d | 367 | desc->callback = sh_mmcif_dma_complete; |
a782d688 | 368 | desc->callback_param = host; |
a5ece7d2 LW |
369 | cookie = dmaengine_submit(desc); |
370 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); | |
371 | dma_async_issue_pending(chan); | |
a782d688 | 372 | } |
585c3a5a | 373 | dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n", |
69983404 | 374 | __func__, data->sg_len, ret, cookie); |
a782d688 GL |
375 | |
376 | if (!desc) { | |
377 | /* DMA failed, fall back to PIO */ | |
378 | if (ret >= 0) | |
379 | ret = -EIO; | |
380 | host->chan_tx = NULL; | |
f38f94c6 | 381 | host->dma_active = false; |
a782d688 GL |
382 | dma_release_channel(chan); |
383 | /* Free the Rx channel too */ | |
384 | chan = host->chan_rx; | |
385 | if (chan) { | |
386 | host->chan_rx = NULL; | |
387 | dma_release_channel(chan); | |
388 | } | |
585c3a5a | 389 | dev_warn(dev, |
a782d688 GL |
390 | "DMA failed: %d, falling back to PIO\n", ret); |
391 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
392 | } | |
393 | ||
585c3a5a | 394 | dev_dbg(dev, "%s(): desc %p, cookie %d\n", __func__, |
a782d688 GL |
395 | desc, cookie); |
396 | } | |
397 | ||
e5a233cb | 398 | static struct dma_chan * |
27cbd7e8 | 399 | sh_mmcif_request_dma_pdata(struct sh_mmcif_host *host, uintptr_t slave_id) |
a782d688 | 400 | { |
0e79f9ae | 401 | dma_cap_mask_t mask; |
a782d688 | 402 | |
e5a233cb LP |
403 | dma_cap_zero(mask); |
404 | dma_cap_set(DMA_SLAVE, mask); | |
27cbd7e8 AB |
405 | if (slave_id <= 0) |
406 | return NULL; | |
e5a233cb | 407 | |
27cbd7e8 AB |
408 | return dma_request_channel(mask, shdma_chan_filter, (void *)slave_id); |
409 | } | |
e5a233cb | 410 | |
27cbd7e8 AB |
411 | static int sh_mmcif_dma_slave_config(struct sh_mmcif_host *host, |
412 | struct dma_chan *chan, | |
413 | enum dma_transfer_direction direction) | |
414 | { | |
415 | struct resource *res; | |
416 | struct dma_slave_config cfg = { 0, }; | |
e5a233cb LP |
417 | |
418 | res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); | |
e5a233cb | 419 | cfg.direction = direction; |
d25006e7 | 420 | |
e36152aa | 421 | if (direction == DMA_DEV_TO_MEM) { |
d25006e7 | 422 | cfg.src_addr = res->start + MMCIF_CE_DATA; |
e36152aa LP |
423 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
424 | } else { | |
d25006e7 | 425 | cfg.dst_addr = res->start + MMCIF_CE_DATA; |
e36152aa LP |
426 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
427 | } | |
d25006e7 | 428 | |
27cbd7e8 | 429 | return dmaengine_slave_config(chan, &cfg); |
e5a233cb LP |
430 | } |
431 | ||
27cbd7e8 | 432 | static void sh_mmcif_request_dma(struct sh_mmcif_host *host) |
e5a233cb | 433 | { |
585c3a5a | 434 | struct device *dev = sh_mmcif_host_to_dev(host); |
f38f94c6 | 435 | host->dma_active = false; |
a782d688 | 436 | |
27cbd7e8 AB |
437 | /* We can only either use DMA for both Tx and Rx or not use it at all */ |
438 | if (IS_ENABLED(CONFIG_SUPERH) && dev->platform_data) { | |
439 | struct sh_mmcif_plat_data *pdata = dev->platform_data; | |
440 | ||
441 | host->chan_tx = sh_mmcif_request_dma_pdata(host, | |
442 | pdata->slave_id_tx); | |
443 | host->chan_rx = sh_mmcif_request_dma_pdata(host, | |
444 | pdata->slave_id_rx); | |
445 | } else { | |
446 | host->chan_tx = dma_request_slave_channel(dev, "tx"); | |
a32ef81c | 447 | host->chan_rx = dma_request_slave_channel(dev, "rx"); |
acd6d772 | 448 | } |
27cbd7e8 AB |
449 | dev_dbg(dev, "%s: got channel TX %p RX %p\n", __func__, host->chan_tx, |
450 | host->chan_rx); | |
a782d688 | 451 | |
27cbd7e8 AB |
452 | if (!host->chan_tx || !host->chan_rx || |
453 | sh_mmcif_dma_slave_config(host, host->chan_tx, DMA_MEM_TO_DEV) || | |
454 | sh_mmcif_dma_slave_config(host, host->chan_rx, DMA_DEV_TO_MEM)) | |
455 | goto error; | |
a782d688 | 456 | |
27cbd7e8 AB |
457 | return; |
458 | ||
459 | error: | |
460 | if (host->chan_tx) | |
e5a233cb | 461 | dma_release_channel(host->chan_tx); |
27cbd7e8 AB |
462 | if (host->chan_rx) |
463 | dma_release_channel(host->chan_rx); | |
464 | host->chan_tx = host->chan_rx = NULL; | |
a782d688 GL |
465 | } |
466 | ||
467 | static void sh_mmcif_release_dma(struct sh_mmcif_host *host) | |
468 | { | |
469 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
470 | /* Descriptors are freed automatically */ | |
471 | if (host->chan_tx) { | |
472 | struct dma_chan *chan = host->chan_tx; | |
473 | host->chan_tx = NULL; | |
474 | dma_release_channel(chan); | |
475 | } | |
476 | if (host->chan_rx) { | |
477 | struct dma_chan *chan = host->chan_rx; | |
478 | host->chan_rx = NULL; | |
479 | dma_release_channel(chan); | |
480 | } | |
481 | ||
f38f94c6 | 482 | host->dma_active = false; |
a782d688 | 483 | } |
fdc50a94 YG |
484 | |
485 | static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) | |
486 | { | |
585c3a5a KM |
487 | struct device *dev = sh_mmcif_host_to_dev(host); |
488 | struct sh_mmcif_plat_data *p = dev->platform_data; | |
bf68a812 | 489 | bool sup_pclk = p ? p->sup_pclk : false; |
6aed678b | 490 | unsigned int current_clk = clk_get_rate(host->clk); |
89d49a70 | 491 | unsigned int clkdiv; |
fdc50a94 YG |
492 | |
493 | sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); | |
494 | sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); | |
495 | ||
496 | if (!clk) | |
497 | return; | |
fdc50a94 | 498 | |
89d49a70 KM |
499 | if (host->clkdiv_map) { |
500 | unsigned int freq, best_freq, myclk, div, diff_min, diff; | |
501 | int i; | |
502 | ||
503 | clkdiv = 0; | |
504 | diff_min = ~0; | |
505 | best_freq = 0; | |
506 | for (i = 31; i >= 0; i--) { | |
507 | if (!((1 << i) & host->clkdiv_map)) | |
508 | continue; | |
509 | ||
510 | /* | |
511 | * clk = parent_freq / div | |
512 | * -> parent_freq = clk x div | |
513 | */ | |
514 | ||
515 | div = 1 << (i + 1); | |
516 | freq = clk_round_rate(host->clk, clk * div); | |
517 | myclk = freq / div; | |
518 | diff = (myclk > clk) ? myclk - clk : clk - myclk; | |
519 | ||
520 | if (diff <= diff_min) { | |
521 | best_freq = freq; | |
522 | clkdiv = i; | |
523 | diff_min = diff; | |
524 | } | |
525 | } | |
526 | ||
527 | dev_dbg(dev, "clk %u/%u (%u, 0x%x)\n", | |
528 | (best_freq / (1 << (clkdiv + 1))), clk, | |
529 | best_freq, clkdiv); | |
530 | ||
531 | clk_set_rate(host->clk, best_freq); | |
532 | clkdiv = clkdiv << 16; | |
533 | } else if (sup_pclk && clk == current_clk) { | |
534 | clkdiv = CLK_SUP_PCLK; | |
535 | } else { | |
536 | clkdiv = (fls(DIV_ROUND_UP(current_clk, clk) - 1) - 1) << 16; | |
537 | } | |
538 | ||
539 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & clkdiv); | |
fdc50a94 YG |
540 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); |
541 | } | |
542 | ||
543 | static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) | |
544 | { | |
545 | u32 tmp; | |
546 | ||
487d9fc5 | 547 | tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); |
fdc50a94 | 548 | |
487d9fc5 MD |
549 | sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); |
550 | sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); | |
967bcb77 GL |
551 | if (host->ccs_enable) |
552 | tmp |= SCCSTO_29; | |
6d6fd367 GL |
553 | if (host->clk_ctrl2_enable) |
554 | sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000); | |
fdc50a94 | 555 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | |
967bcb77 | 556 | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29); |
fdc50a94 YG |
557 | /* byte swap on */ |
558 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); | |
559 | } | |
560 | ||
561 | static int sh_mmcif_error_manage(struct sh_mmcif_host *host) | |
562 | { | |
585c3a5a | 563 | struct device *dev = sh_mmcif_host_to_dev(host); |
fdc50a94 | 564 | u32 state1, state2; |
ee4b8887 | 565 | int ret, timeout; |
fdc50a94 | 566 | |
aa0787a9 | 567 | host->sd_error = false; |
fdc50a94 | 568 | |
487d9fc5 MD |
569 | state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); |
570 | state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); | |
585c3a5a KM |
571 | dev_dbg(dev, "ERR HOST_STS1 = %08x\n", state1); |
572 | dev_dbg(dev, "ERR HOST_STS2 = %08x\n", state2); | |
fdc50a94 YG |
573 | |
574 | if (state1 & STS1_CMDSEQ) { | |
575 | sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); | |
576 | sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); | |
52e00b84 | 577 | for (timeout = 10000; timeout; timeout--) { |
487d9fc5 | 578 | if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) |
ee4b8887 | 579 | & STS1_CMDSEQ)) |
fdc50a94 YG |
580 | break; |
581 | mdelay(1); | |
582 | } | |
ee4b8887 | 583 | if (!timeout) { |
585c3a5a | 584 | dev_err(dev, |
ee4b8887 GL |
585 | "Forced end of command sequence timeout err\n"); |
586 | return -EIO; | |
587 | } | |
fdc50a94 | 588 | sh_mmcif_sync_reset(host); |
585c3a5a | 589 | dev_dbg(dev, "Forced end of command sequence\n"); |
fdc50a94 YG |
590 | return -EIO; |
591 | } | |
592 | ||
593 | if (state2 & STS2_CRC_ERR) { | |
585c3a5a | 594 | dev_err(dev, " CRC error: state %u, wait %u\n", |
e475b270 | 595 | host->state, host->wait_for); |
fdc50a94 YG |
596 | ret = -EIO; |
597 | } else if (state2 & STS2_TIMEOUT_ERR) { | |
585c3a5a | 598 | dev_err(dev, " Timeout: state %u, wait %u\n", |
e475b270 | 599 | host->state, host->wait_for); |
fdc50a94 YG |
600 | ret = -ETIMEDOUT; |
601 | } else { | |
585c3a5a | 602 | dev_dbg(dev, " End/Index error: state %u, wait %u\n", |
e475b270 | 603 | host->state, host->wait_for); |
fdc50a94 YG |
604 | ret = -EIO; |
605 | } | |
606 | return ret; | |
607 | } | |
608 | ||
f985da17 | 609 | static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) |
fdc50a94 | 610 | { |
f985da17 GL |
611 | struct mmc_data *data = host->mrq->data; |
612 | ||
613 | host->sg_blkidx += host->blocksize; | |
614 | ||
615 | /* data->sg->length must be a multiple of host->blocksize? */ | |
616 | BUG_ON(host->sg_blkidx > data->sg->length); | |
617 | ||
618 | if (host->sg_blkidx == data->sg->length) { | |
619 | host->sg_blkidx = 0; | |
620 | if (++host->sg_idx < data->sg_len) | |
621 | host->pio_ptr = sg_virt(++data->sg); | |
622 | } else { | |
623 | host->pio_ptr = p; | |
624 | } | |
625 | ||
99eb9d8d | 626 | return host->sg_idx != data->sg_len; |
f985da17 GL |
627 | } |
628 | ||
629 | static void sh_mmcif_single_read(struct sh_mmcif_host *host, | |
630 | struct mmc_request *mrq) | |
631 | { | |
632 | host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & | |
633 | BLOCK_SIZE_MASK) + 3; | |
634 | ||
635 | host->wait_for = MMCIF_WAIT_FOR_READ; | |
fdc50a94 | 636 | |
fdc50a94 YG |
637 | /* buf read enable */ |
638 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); | |
f985da17 GL |
639 | } |
640 | ||
641 | static bool sh_mmcif_read_block(struct sh_mmcif_host *host) | |
642 | { | |
585c3a5a | 643 | struct device *dev = sh_mmcif_host_to_dev(host); |
f985da17 GL |
644 | struct mmc_data *data = host->mrq->data; |
645 | u32 *p = sg_virt(data->sg); | |
646 | int i; | |
647 | ||
648 | if (host->sd_error) { | |
649 | data->error = sh_mmcif_error_manage(host); | |
585c3a5a | 650 | dev_dbg(dev, "%s(): %d\n", __func__, data->error); |
f985da17 GL |
651 | return false; |
652 | } | |
653 | ||
654 | for (i = 0; i < host->blocksize / 4; i++) | |
487d9fc5 | 655 | *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); |
fdc50a94 YG |
656 | |
657 | /* buffer read end */ | |
658 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); | |
f985da17 | 659 | host->wait_for = MMCIF_WAIT_FOR_READ_END; |
fdc50a94 | 660 | |
f985da17 | 661 | return true; |
fdc50a94 YG |
662 | } |
663 | ||
f985da17 GL |
664 | static void sh_mmcif_multi_read(struct sh_mmcif_host *host, |
665 | struct mmc_request *mrq) | |
fdc50a94 YG |
666 | { |
667 | struct mmc_data *data = mrq->data; | |
f985da17 GL |
668 | |
669 | if (!data->sg_len || !data->sg->length) | |
670 | return; | |
671 | ||
672 | host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & | |
673 | BLOCK_SIZE_MASK; | |
674 | ||
675 | host->wait_for = MMCIF_WAIT_FOR_MREAD; | |
676 | host->sg_idx = 0; | |
677 | host->sg_blkidx = 0; | |
678 | host->pio_ptr = sg_virt(data->sg); | |
5df460b1 | 679 | |
f985da17 GL |
680 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); |
681 | } | |
682 | ||
683 | static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) | |
684 | { | |
585c3a5a | 685 | struct device *dev = sh_mmcif_host_to_dev(host); |
f985da17 GL |
686 | struct mmc_data *data = host->mrq->data; |
687 | u32 *p = host->pio_ptr; | |
688 | int i; | |
689 | ||
690 | if (host->sd_error) { | |
691 | data->error = sh_mmcif_error_manage(host); | |
585c3a5a | 692 | dev_dbg(dev, "%s(): %d\n", __func__, data->error); |
f985da17 | 693 | return false; |
fdc50a94 | 694 | } |
f985da17 GL |
695 | |
696 | BUG_ON(!data->sg->length); | |
697 | ||
698 | for (i = 0; i < host->blocksize / 4; i++) | |
699 | *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); | |
700 | ||
701 | if (!sh_mmcif_next_block(host, p)) | |
702 | return false; | |
703 | ||
f985da17 GL |
704 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); |
705 | ||
706 | return true; | |
fdc50a94 YG |
707 | } |
708 | ||
f985da17 | 709 | static void sh_mmcif_single_write(struct sh_mmcif_host *host, |
fdc50a94 YG |
710 | struct mmc_request *mrq) |
711 | { | |
f985da17 GL |
712 | host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & |
713 | BLOCK_SIZE_MASK) + 3; | |
fdc50a94 | 714 | |
f985da17 | 715 | host->wait_for = MMCIF_WAIT_FOR_WRITE; |
fdc50a94 YG |
716 | |
717 | /* buf write enable */ | |
f985da17 GL |
718 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); |
719 | } | |
720 | ||
721 | static bool sh_mmcif_write_block(struct sh_mmcif_host *host) | |
722 | { | |
585c3a5a | 723 | struct device *dev = sh_mmcif_host_to_dev(host); |
f985da17 GL |
724 | struct mmc_data *data = host->mrq->data; |
725 | u32 *p = sg_virt(data->sg); | |
726 | int i; | |
727 | ||
728 | if (host->sd_error) { | |
729 | data->error = sh_mmcif_error_manage(host); | |
585c3a5a | 730 | dev_dbg(dev, "%s(): %d\n", __func__, data->error); |
f985da17 GL |
731 | return false; |
732 | } | |
733 | ||
734 | for (i = 0; i < host->blocksize / 4; i++) | |
487d9fc5 | 735 | sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); |
fdc50a94 YG |
736 | |
737 | /* buffer write end */ | |
738 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); | |
f985da17 | 739 | host->wait_for = MMCIF_WAIT_FOR_WRITE_END; |
fdc50a94 | 740 | |
f985da17 | 741 | return true; |
fdc50a94 YG |
742 | } |
743 | ||
f985da17 GL |
744 | static void sh_mmcif_multi_write(struct sh_mmcif_host *host, |
745 | struct mmc_request *mrq) | |
fdc50a94 YG |
746 | { |
747 | struct mmc_data *data = mrq->data; | |
fdc50a94 | 748 | |
f985da17 GL |
749 | if (!data->sg_len || !data->sg->length) |
750 | return; | |
fdc50a94 | 751 | |
f985da17 GL |
752 | host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & |
753 | BLOCK_SIZE_MASK; | |
fdc50a94 | 754 | |
f985da17 GL |
755 | host->wait_for = MMCIF_WAIT_FOR_MWRITE; |
756 | host->sg_idx = 0; | |
757 | host->sg_blkidx = 0; | |
758 | host->pio_ptr = sg_virt(data->sg); | |
5df460b1 | 759 | |
f985da17 GL |
760 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); |
761 | } | |
fdc50a94 | 762 | |
f985da17 GL |
763 | static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) |
764 | { | |
585c3a5a | 765 | struct device *dev = sh_mmcif_host_to_dev(host); |
f985da17 GL |
766 | struct mmc_data *data = host->mrq->data; |
767 | u32 *p = host->pio_ptr; | |
768 | int i; | |
769 | ||
770 | if (host->sd_error) { | |
771 | data->error = sh_mmcif_error_manage(host); | |
585c3a5a | 772 | dev_dbg(dev, "%s(): %d\n", __func__, data->error); |
f985da17 | 773 | return false; |
fdc50a94 | 774 | } |
f985da17 GL |
775 | |
776 | BUG_ON(!data->sg->length); | |
777 | ||
778 | for (i = 0; i < host->blocksize / 4; i++) | |
779 | sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); | |
780 | ||
781 | if (!sh_mmcif_next_block(host, p)) | |
782 | return false; | |
783 | ||
f985da17 GL |
784 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); |
785 | ||
786 | return true; | |
fdc50a94 YG |
787 | } |
788 | ||
789 | static void sh_mmcif_get_response(struct sh_mmcif_host *host, | |
790 | struct mmc_command *cmd) | |
791 | { | |
792 | if (cmd->flags & MMC_RSP_136) { | |
487d9fc5 MD |
793 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); |
794 | cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); | |
795 | cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); | |
796 | cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); | |
fdc50a94 | 797 | } else |
487d9fc5 | 798 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); |
fdc50a94 YG |
799 | } |
800 | ||
801 | static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, | |
802 | struct mmc_command *cmd) | |
803 | { | |
487d9fc5 | 804 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); |
fdc50a94 YG |
805 | } |
806 | ||
807 | static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, | |
69983404 | 808 | struct mmc_request *mrq) |
fdc50a94 | 809 | { |
585c3a5a | 810 | struct device *dev = sh_mmcif_host_to_dev(host); |
69983404 GL |
811 | struct mmc_data *data = mrq->data; |
812 | struct mmc_command *cmd = mrq->cmd; | |
813 | u32 opc = cmd->opcode; | |
fdc50a94 YG |
814 | u32 tmp = 0; |
815 | ||
816 | /* Response Type check */ | |
817 | switch (mmc_resp_type(cmd)) { | |
818 | case MMC_RSP_NONE: | |
819 | tmp |= CMD_SET_RTYP_NO; | |
820 | break; | |
821 | case MMC_RSP_R1: | |
fdc50a94 YG |
822 | case MMC_RSP_R3: |
823 | tmp |= CMD_SET_RTYP_6B; | |
824 | break; | |
5b1c29bc UH |
825 | case MMC_RSP_R1B: |
826 | tmp |= CMD_SET_RBSY | CMD_SET_RTYP_6B; | |
827 | break; | |
fdc50a94 YG |
828 | case MMC_RSP_R2: |
829 | tmp |= CMD_SET_RTYP_17B; | |
830 | break; | |
831 | default: | |
585c3a5a | 832 | dev_err(dev, "Unsupported response type.\n"); |
fdc50a94 YG |
833 | break; |
834 | } | |
5b1c29bc | 835 | |
fdc50a94 | 836 | /* WDAT / DATW */ |
69983404 | 837 | if (data) { |
fdc50a94 YG |
838 | tmp |= CMD_SET_WDAT; |
839 | switch (host->bus_width) { | |
840 | case MMC_BUS_WIDTH_1: | |
841 | tmp |= CMD_SET_DATW_1; | |
842 | break; | |
843 | case MMC_BUS_WIDTH_4: | |
844 | tmp |= CMD_SET_DATW_4; | |
845 | break; | |
846 | case MMC_BUS_WIDTH_8: | |
847 | tmp |= CMD_SET_DATW_8; | |
848 | break; | |
849 | default: | |
585c3a5a | 850 | dev_err(dev, "Unsupported bus width.\n"); |
fdc50a94 YG |
851 | break; |
852 | } | |
555061f9 | 853 | switch (host->timing) { |
4039ff47 | 854 | case MMC_TIMING_MMC_DDR52: |
555061f9 TK |
855 | /* |
856 | * MMC core will only set this timing, if the host | |
4039ff47 SJ |
857 | * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR |
858 | * capability. MMCIF implementations with this | |
859 | * capability, e.g. sh73a0, will have to set it | |
860 | * in their platform data. | |
555061f9 TK |
861 | */ |
862 | tmp |= CMD_SET_DARS; | |
863 | break; | |
864 | } | |
fdc50a94 YG |
865 | } |
866 | /* DWEN */ | |
867 | if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) | |
868 | tmp |= CMD_SET_DWEN; | |
869 | /* CMLTE/CMD12EN */ | |
870 | if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { | |
871 | tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; | |
872 | sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, | |
69983404 | 873 | data->blocks << 16); |
fdc50a94 YG |
874 | } |
875 | /* RIDXC[1:0] check bits */ | |
876 | if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || | |
877 | opc == MMC_SEND_CSD || opc == MMC_SEND_CID) | |
878 | tmp |= CMD_SET_RIDXC_BITS; | |
879 | /* RCRC7C[1:0] check bits */ | |
880 | if (opc == MMC_SEND_OP_COND) | |
881 | tmp |= CMD_SET_CRC7C_BITS; | |
882 | /* RCRC7C[1:0] internal CRC7 */ | |
883 | if (opc == MMC_ALL_SEND_CID || | |
884 | opc == MMC_SEND_CSD || opc == MMC_SEND_CID) | |
885 | tmp |= CMD_SET_CRC7C_INTERNAL; | |
886 | ||
69983404 | 887 | return (opc << 24) | tmp; |
fdc50a94 YG |
888 | } |
889 | ||
e47bf32a | 890 | static int sh_mmcif_data_trans(struct sh_mmcif_host *host, |
f985da17 | 891 | struct mmc_request *mrq, u32 opc) |
fdc50a94 | 892 | { |
585c3a5a KM |
893 | struct device *dev = sh_mmcif_host_to_dev(host); |
894 | ||
fdc50a94 YG |
895 | switch (opc) { |
896 | case MMC_READ_MULTIPLE_BLOCK: | |
f985da17 GL |
897 | sh_mmcif_multi_read(host, mrq); |
898 | return 0; | |
fdc50a94 | 899 | case MMC_WRITE_MULTIPLE_BLOCK: |
f985da17 GL |
900 | sh_mmcif_multi_write(host, mrq); |
901 | return 0; | |
fdc50a94 | 902 | case MMC_WRITE_BLOCK: |
f985da17 GL |
903 | sh_mmcif_single_write(host, mrq); |
904 | return 0; | |
fdc50a94 YG |
905 | case MMC_READ_SINGLE_BLOCK: |
906 | case MMC_SEND_EXT_CSD: | |
f985da17 GL |
907 | sh_mmcif_single_read(host, mrq); |
908 | return 0; | |
fdc50a94 | 909 | default: |
585c3a5a | 910 | dev_err(dev, "Unsupported CMD%d\n", opc); |
ee4b8887 | 911 | return -EINVAL; |
fdc50a94 | 912 | } |
fdc50a94 YG |
913 | } |
914 | ||
915 | static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, | |
ee4b8887 | 916 | struct mmc_request *mrq) |
fdc50a94 | 917 | { |
ee4b8887 | 918 | struct mmc_command *cmd = mrq->cmd; |
f985da17 | 919 | u32 opc = cmd->opcode; |
5b1c29bc | 920 | u32 mask = 0; |
dbb42d96 | 921 | unsigned long flags; |
fdc50a94 | 922 | |
5b1c29bc | 923 | if (cmd->flags & MMC_RSP_BUSY) |
ee4b8887 | 924 | mask = MASK_START_CMD | MASK_MRBSYE; |
5b1c29bc | 925 | else |
ee4b8887 | 926 | mask = MASK_START_CMD | MASK_MCRSPE; |
fdc50a94 | 927 | |
967bcb77 GL |
928 | if (host->ccs_enable) |
929 | mask |= MASK_MCCSTO; | |
930 | ||
69983404 | 931 | if (mrq->data) { |
487d9fc5 MD |
932 | sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); |
933 | sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, | |
934 | mrq->data->blksz); | |
fdc50a94 | 935 | } |
69983404 | 936 | opc = sh_mmcif_set_cmd(host, mrq); |
fdc50a94 | 937 | |
967bcb77 GL |
938 | if (host->ccs_enable) |
939 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); | |
940 | else | |
941 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS); | |
487d9fc5 | 942 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); |
fdc50a94 | 943 | /* set arg */ |
487d9fc5 | 944 | sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); |
fdc50a94 | 945 | /* set cmd */ |
dbb42d96 | 946 | spin_lock_irqsave(&host->lock, flags); |
487d9fc5 | 947 | sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); |
fdc50a94 | 948 | |
f985da17 GL |
949 | host->wait_for = MMCIF_WAIT_FOR_CMD; |
950 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
dbb42d96 | 951 | spin_unlock_irqrestore(&host->lock, flags); |
fdc50a94 YG |
952 | } |
953 | ||
954 | static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, | |
ee4b8887 | 955 | struct mmc_request *mrq) |
fdc50a94 | 956 | { |
585c3a5a KM |
957 | struct device *dev = sh_mmcif_host_to_dev(host); |
958 | ||
69983404 GL |
959 | switch (mrq->cmd->opcode) { |
960 | case MMC_READ_MULTIPLE_BLOCK: | |
fdc50a94 | 961 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); |
69983404 GL |
962 | break; |
963 | case MMC_WRITE_MULTIPLE_BLOCK: | |
fdc50a94 | 964 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); |
69983404 GL |
965 | break; |
966 | default: | |
585c3a5a | 967 | dev_err(dev, "unsupported stop cmd\n"); |
69983404 | 968 | mrq->stop->error = sh_mmcif_error_manage(host); |
fdc50a94 YG |
969 | return; |
970 | } | |
971 | ||
f985da17 | 972 | host->wait_for = MMCIF_WAIT_FOR_STOP; |
fdc50a94 YG |
973 | } |
974 | ||
975 | static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
976 | { | |
977 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
585c3a5a | 978 | struct device *dev = sh_mmcif_host_to_dev(host); |
3b0beafc GL |
979 | unsigned long flags; |
980 | ||
981 | spin_lock_irqsave(&host->lock, flags); | |
982 | if (host->state != STATE_IDLE) { | |
585c3a5a KM |
983 | dev_dbg(dev, "%s() rejected, state %u\n", |
984 | __func__, host->state); | |
3b0beafc GL |
985 | spin_unlock_irqrestore(&host->lock, flags); |
986 | mrq->cmd->error = -EAGAIN; | |
987 | mmc_request_done(mmc, mrq); | |
988 | return; | |
989 | } | |
990 | ||
991 | host->state = STATE_REQUEST; | |
992 | spin_unlock_irqrestore(&host->lock, flags); | |
fdc50a94 | 993 | |
f985da17 | 994 | host->mrq = mrq; |
fdc50a94 | 995 | |
f985da17 | 996 | sh_mmcif_start_cmd(host, mrq); |
fdc50a94 YG |
997 | } |
998 | ||
9bb09a30 | 999 | static void sh_mmcif_clk_setup(struct sh_mmcif_host *host) |
a6609267 | 1000 | { |
89d49a70 KM |
1001 | struct device *dev = sh_mmcif_host_to_dev(host); |
1002 | ||
1003 | if (host->mmc->f_max) { | |
1004 | unsigned int f_max, f_min = 0, f_min_old; | |
1005 | ||
1006 | f_max = host->mmc->f_max; | |
1007 | for (f_min_old = f_max; f_min_old > 2;) { | |
1008 | f_min = clk_round_rate(host->clk, f_min_old / 2); | |
1009 | if (f_min == f_min_old) | |
1010 | break; | |
1011 | f_min_old = f_min; | |
1012 | } | |
1013 | ||
1014 | /* | |
1015 | * This driver assumes this SoC is R-Car Gen2 or later | |
1016 | */ | |
1017 | host->clkdiv_map = 0x3ff; | |
1018 | ||
1019 | host->mmc->f_max = f_max / (1 << ffs(host->clkdiv_map)); | |
1020 | host->mmc->f_min = f_min / (1 << fls(host->clkdiv_map)); | |
1021 | } else { | |
1022 | unsigned int clk = clk_get_rate(host->clk); | |
1023 | ||
1024 | host->mmc->f_max = clk / 2; | |
1025 | host->mmc->f_min = clk / 512; | |
1026 | } | |
a6609267 | 1027 | |
89d49a70 KM |
1028 | dev_dbg(dev, "clk max/min = %d/%d\n", |
1029 | host->mmc->f_max, host->mmc->f_min); | |
a6609267 GL |
1030 | } |
1031 | ||
fdc50a94 YG |
1032 | static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
1033 | { | |
1034 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
585c3a5a | 1035 | struct device *dev = sh_mmcif_host_to_dev(host); |
3b0beafc GL |
1036 | unsigned long flags; |
1037 | ||
1038 | spin_lock_irqsave(&host->lock, flags); | |
1039 | if (host->state != STATE_IDLE) { | |
585c3a5a KM |
1040 | dev_dbg(dev, "%s() rejected, state %u\n", |
1041 | __func__, host->state); | |
3b0beafc GL |
1042 | spin_unlock_irqrestore(&host->lock, flags); |
1043 | return; | |
1044 | } | |
1045 | ||
1046 | host->state = STATE_IOS; | |
1047 | spin_unlock_irqrestore(&host->lock, flags); | |
fdc50a94 | 1048 | |
4caf653a UH |
1049 | switch (ios->power_mode) { |
1050 | case MMC_POWER_UP: | |
33a31cea UH |
1051 | if (!IS_ERR(mmc->supply.vmmc)) |
1052 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); | |
4caf653a UH |
1053 | if (!host->power) { |
1054 | clk_prepare_enable(host->clk); | |
1055 | pm_runtime_get_sync(dev); | |
1056 | sh_mmcif_sync_reset(host); | |
27cbd7e8 | 1057 | sh_mmcif_request_dma(host); |
4caf653a | 1058 | host->power = true; |
faca6648 | 1059 | } |
4caf653a UH |
1060 | break; |
1061 | case MMC_POWER_OFF: | |
33a31cea UH |
1062 | if (!IS_ERR(mmc->supply.vmmc)) |
1063 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); | |
c9b0cef2 | 1064 | if (host->power) { |
4caf653a UH |
1065 | sh_mmcif_clock_control(host, 0); |
1066 | sh_mmcif_release_dma(host); | |
1067 | pm_runtime_put(dev); | |
6aed678b | 1068 | clk_disable_unprepare(host->clk); |
c9b0cef2 | 1069 | host->power = false; |
c9b0cef2 | 1070 | } |
4caf653a UH |
1071 | break; |
1072 | case MMC_POWER_ON: | |
fdc50a94 | 1073 | sh_mmcif_clock_control(host, ios->clock); |
4caf653a | 1074 | break; |
c9b0cef2 | 1075 | } |
fdc50a94 | 1076 | |
555061f9 | 1077 | host->timing = ios->timing; |
fdc50a94 | 1078 | host->bus_width = ios->bus_width; |
3b0beafc | 1079 | host->state = STATE_IDLE; |
fdc50a94 YG |
1080 | } |
1081 | ||
777271d0 AH |
1082 | static int sh_mmcif_get_cd(struct mmc_host *mmc) |
1083 | { | |
1084 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
585c3a5a KM |
1085 | struct device *dev = sh_mmcif_host_to_dev(host); |
1086 | struct sh_mmcif_plat_data *p = dev->platform_data; | |
e480606a GL |
1087 | int ret = mmc_gpio_get_cd(mmc); |
1088 | ||
1089 | if (ret >= 0) | |
1090 | return ret; | |
777271d0 | 1091 | |
bf68a812 | 1092 | if (!p || !p->get_cd) |
777271d0 AH |
1093 | return -ENOSYS; |
1094 | else | |
1095 | return p->get_cd(host->pd); | |
1096 | } | |
1097 | ||
fdc50a94 YG |
1098 | static struct mmc_host_ops sh_mmcif_ops = { |
1099 | .request = sh_mmcif_request, | |
1100 | .set_ios = sh_mmcif_set_ios, | |
777271d0 | 1101 | .get_cd = sh_mmcif_get_cd, |
fdc50a94 YG |
1102 | }; |
1103 | ||
f985da17 GL |
1104 | static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) |
1105 | { | |
1106 | struct mmc_command *cmd = host->mrq->cmd; | |
69983404 | 1107 | struct mmc_data *data = host->mrq->data; |
585c3a5a | 1108 | struct device *dev = sh_mmcif_host_to_dev(host); |
f985da17 GL |
1109 | long time; |
1110 | ||
1111 | if (host->sd_error) { | |
1112 | switch (cmd->opcode) { | |
1113 | case MMC_ALL_SEND_CID: | |
1114 | case MMC_SELECT_CARD: | |
1115 | case MMC_APP_CMD: | |
1116 | cmd->error = -ETIMEDOUT; | |
f985da17 GL |
1117 | break; |
1118 | default: | |
1119 | cmd->error = sh_mmcif_error_manage(host); | |
f985da17 GL |
1120 | break; |
1121 | } | |
585c3a5a | 1122 | dev_dbg(dev, "CMD%d error %d\n", |
e475b270 | 1123 | cmd->opcode, cmd->error); |
aba9d646 | 1124 | host->sd_error = false; |
f985da17 GL |
1125 | return false; |
1126 | } | |
1127 | if (!(cmd->flags & MMC_RSP_PRESENT)) { | |
1128 | cmd->error = 0; | |
1129 | return false; | |
1130 | } | |
1131 | ||
1132 | sh_mmcif_get_response(host, cmd); | |
1133 | ||
69983404 | 1134 | if (!data) |
f985da17 GL |
1135 | return false; |
1136 | ||
90f1cb43 GL |
1137 | /* |
1138 | * Completion can be signalled from DMA callback and error, so, have to | |
1139 | * reset here, before setting .dma_active | |
1140 | */ | |
1141 | init_completion(&host->dma_complete); | |
1142 | ||
69983404 | 1143 | if (data->flags & MMC_DATA_READ) { |
f985da17 GL |
1144 | if (host->chan_rx) |
1145 | sh_mmcif_start_dma_rx(host); | |
1146 | } else { | |
1147 | if (host->chan_tx) | |
1148 | sh_mmcif_start_dma_tx(host); | |
1149 | } | |
1150 | ||
1151 | if (!host->dma_active) { | |
69983404 | 1152 | data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); |
99eb9d8d | 1153 | return !data->error; |
f985da17 GL |
1154 | } |
1155 | ||
1156 | /* Running in the IRQ thread, can sleep */ | |
1157 | time = wait_for_completion_interruptible_timeout(&host->dma_complete, | |
1158 | host->timeout); | |
eae30983 TK |
1159 | |
1160 | if (data->flags & MMC_DATA_READ) | |
1161 | dma_unmap_sg(host->chan_rx->device->dev, | |
1162 | data->sg, data->sg_len, | |
1163 | DMA_FROM_DEVICE); | |
1164 | else | |
1165 | dma_unmap_sg(host->chan_tx->device->dev, | |
1166 | data->sg, data->sg_len, | |
1167 | DMA_TO_DEVICE); | |
1168 | ||
f985da17 GL |
1169 | if (host->sd_error) { |
1170 | dev_err(host->mmc->parent, | |
1171 | "Error IRQ while waiting for DMA completion!\n"); | |
1172 | /* Woken up by an error IRQ: abort DMA */ | |
69983404 | 1173 | data->error = sh_mmcif_error_manage(host); |
f985da17 | 1174 | } else if (!time) { |
e475b270 | 1175 | dev_err(host->mmc->parent, "DMA timeout!\n"); |
69983404 | 1176 | data->error = -ETIMEDOUT; |
f985da17 | 1177 | } else if (time < 0) { |
e475b270 TK |
1178 | dev_err(host->mmc->parent, |
1179 | "wait_for_completion_...() error %ld!\n", time); | |
69983404 | 1180 | data->error = time; |
f985da17 GL |
1181 | } |
1182 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, | |
1183 | BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
1184 | host->dma_active = false; | |
1185 | ||
eae30983 | 1186 | if (data->error) { |
69983404 | 1187 | data->bytes_xfered = 0; |
eae30983 TK |
1188 | /* Abort DMA */ |
1189 | if (data->flags & MMC_DATA_READ) | |
1190 | dmaengine_terminate_all(host->chan_rx); | |
1191 | else | |
1192 | dmaengine_terminate_all(host->chan_tx); | |
1193 | } | |
f985da17 GL |
1194 | |
1195 | return false; | |
1196 | } | |
1197 | ||
1198 | static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) | |
1199 | { | |
1200 | struct sh_mmcif_host *host = dev_id; | |
8047310e | 1201 | struct mmc_request *mrq; |
585c3a5a | 1202 | struct device *dev = sh_mmcif_host_to_dev(host); |
5df460b1 | 1203 | bool wait = false; |
dbb42d96 KT |
1204 | unsigned long flags; |
1205 | int wait_work; | |
1206 | ||
1207 | spin_lock_irqsave(&host->lock, flags); | |
1208 | wait_work = host->wait_for; | |
1209 | spin_unlock_irqrestore(&host->lock, flags); | |
f985da17 GL |
1210 | |
1211 | cancel_delayed_work_sync(&host->timeout_work); | |
1212 | ||
8047310e GL |
1213 | mutex_lock(&host->thread_lock); |
1214 | ||
1215 | mrq = host->mrq; | |
1216 | if (!mrq) { | |
585c3a5a | 1217 | dev_dbg(dev, "IRQ thread state %u, wait %u: NULL mrq!\n", |
8047310e GL |
1218 | host->state, host->wait_for); |
1219 | mutex_unlock(&host->thread_lock); | |
1220 | return IRQ_HANDLED; | |
1221 | } | |
1222 | ||
f985da17 GL |
1223 | /* |
1224 | * All handlers return true, if processing continues, and false, if the | |
1225 | * request has to be completed - successfully or not | |
1226 | */ | |
dbb42d96 | 1227 | switch (wait_work) { |
f985da17 GL |
1228 | case MMCIF_WAIT_FOR_REQUEST: |
1229 | /* We're too late, the timeout has already kicked in */ | |
8047310e | 1230 | mutex_unlock(&host->thread_lock); |
f985da17 GL |
1231 | return IRQ_HANDLED; |
1232 | case MMCIF_WAIT_FOR_CMD: | |
5df460b1 GL |
1233 | /* Wait for data? */ |
1234 | wait = sh_mmcif_end_cmd(host); | |
f985da17 GL |
1235 | break; |
1236 | case MMCIF_WAIT_FOR_MREAD: | |
5df460b1 GL |
1237 | /* Wait for more data? */ |
1238 | wait = sh_mmcif_mread_block(host); | |
f985da17 GL |
1239 | break; |
1240 | case MMCIF_WAIT_FOR_READ: | |
5df460b1 GL |
1241 | /* Wait for data end? */ |
1242 | wait = sh_mmcif_read_block(host); | |
f985da17 GL |
1243 | break; |
1244 | case MMCIF_WAIT_FOR_MWRITE: | |
5df460b1 GL |
1245 | /* Wait data to write? */ |
1246 | wait = sh_mmcif_mwrite_block(host); | |
f985da17 GL |
1247 | break; |
1248 | case MMCIF_WAIT_FOR_WRITE: | |
5df460b1 GL |
1249 | /* Wait for data end? */ |
1250 | wait = sh_mmcif_write_block(host); | |
f985da17 GL |
1251 | break; |
1252 | case MMCIF_WAIT_FOR_STOP: | |
1253 | if (host->sd_error) { | |
1254 | mrq->stop->error = sh_mmcif_error_manage(host); | |
585c3a5a | 1255 | dev_dbg(dev, "%s(): %d\n", __func__, mrq->stop->error); |
f985da17 GL |
1256 | break; |
1257 | } | |
1258 | sh_mmcif_get_cmd12response(host, mrq->stop); | |
1259 | mrq->stop->error = 0; | |
1260 | break; | |
1261 | case MMCIF_WAIT_FOR_READ_END: | |
1262 | case MMCIF_WAIT_FOR_WRITE_END: | |
e475b270 | 1263 | if (host->sd_error) { |
91ab252a | 1264 | mrq->data->error = sh_mmcif_error_manage(host); |
585c3a5a | 1265 | dev_dbg(dev, "%s(): %d\n", __func__, mrq->data->error); |
e475b270 | 1266 | } |
f985da17 GL |
1267 | break; |
1268 | default: | |
1269 | BUG(); | |
1270 | } | |
1271 | ||
5df460b1 GL |
1272 | if (wait) { |
1273 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
1274 | /* Wait for more data */ | |
8047310e | 1275 | mutex_unlock(&host->thread_lock); |
5df460b1 GL |
1276 | return IRQ_HANDLED; |
1277 | } | |
1278 | ||
f985da17 | 1279 | if (host->wait_for != MMCIF_WAIT_FOR_STOP) { |
91ab252a | 1280 | struct mmc_data *data = mrq->data; |
69983404 GL |
1281 | if (!mrq->cmd->error && data && !data->error) |
1282 | data->bytes_xfered = | |
1283 | data->blocks * data->blksz; | |
f985da17 | 1284 | |
69983404 | 1285 | if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { |
f985da17 | 1286 | sh_mmcif_stop_cmd(host, mrq); |
5df460b1 GL |
1287 | if (!mrq->stop->error) { |
1288 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
8047310e | 1289 | mutex_unlock(&host->thread_lock); |
f985da17 | 1290 | return IRQ_HANDLED; |
5df460b1 | 1291 | } |
f985da17 GL |
1292 | } |
1293 | } | |
1294 | ||
1295 | host->wait_for = MMCIF_WAIT_FOR_REQUEST; | |
1296 | host->state = STATE_IDLE; | |
69983404 | 1297 | host->mrq = NULL; |
f985da17 GL |
1298 | mmc_request_done(host->mmc, mrq); |
1299 | ||
8047310e GL |
1300 | mutex_unlock(&host->thread_lock); |
1301 | ||
f985da17 GL |
1302 | return IRQ_HANDLED; |
1303 | } | |
1304 | ||
fdc50a94 YG |
1305 | static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) |
1306 | { | |
1307 | struct sh_mmcif_host *host = dev_id; | |
585c3a5a | 1308 | struct device *dev = sh_mmcif_host_to_dev(host); |
967bcb77 | 1309 | u32 state, mask; |
fdc50a94 | 1310 | |
487d9fc5 | 1311 | state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); |
967bcb77 GL |
1312 | mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK); |
1313 | if (host->ccs_enable) | |
1314 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask)); | |
1315 | else | |
1316 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask)); | |
8af50750 | 1317 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); |
fdc50a94 | 1318 | |
8af50750 | 1319 | if (state & ~MASK_CLEAN) |
585c3a5a | 1320 | dev_dbg(dev, "IRQ state = 0x%08x incompletely cleared\n", |
8af50750 GL |
1321 | state); |
1322 | ||
1323 | if (state & INT_ERR_STS || state & ~INT_ALL) { | |
aa0787a9 | 1324 | host->sd_error = true; |
585c3a5a | 1325 | dev_dbg(dev, "int err state = 0x%08x\n", state); |
fdc50a94 | 1326 | } |
f985da17 | 1327 | if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { |
8af50750 | 1328 | if (!host->mrq) |
585c3a5a | 1329 | dev_dbg(dev, "NULL IRQ state = 0x%08x\n", state); |
f985da17 GL |
1330 | if (!host->dma_active) |
1331 | return IRQ_WAKE_THREAD; | |
1332 | else if (host->sd_error) | |
1b1a694d | 1333 | sh_mmcif_dma_complete(host); |
f985da17 | 1334 | } else { |
585c3a5a | 1335 | dev_dbg(dev, "Unexpected IRQ 0x%x\n", state); |
f985da17 | 1336 | } |
fdc50a94 YG |
1337 | |
1338 | return IRQ_HANDLED; | |
1339 | } | |
1340 | ||
1b1a694d | 1341 | static void sh_mmcif_timeout_work(struct work_struct *work) |
f985da17 | 1342 | { |
1046a811 | 1343 | struct delayed_work *d = to_delayed_work(work); |
f985da17 GL |
1344 | struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); |
1345 | struct mmc_request *mrq = host->mrq; | |
585c3a5a | 1346 | struct device *dev = sh_mmcif_host_to_dev(host); |
8047310e | 1347 | unsigned long flags; |
f985da17 GL |
1348 | |
1349 | if (host->dying) | |
1350 | /* Don't run after mmc_remove_host() */ | |
1351 | return; | |
1352 | ||
8047310e GL |
1353 | spin_lock_irqsave(&host->lock, flags); |
1354 | if (host->state == STATE_IDLE) { | |
1355 | spin_unlock_irqrestore(&host->lock, flags); | |
1356 | return; | |
1357 | } | |
1358 | ||
585c3a5a | 1359 | dev_err(dev, "Timeout waiting for %u on CMD%u\n", |
4cbd5224 KT |
1360 | host->wait_for, mrq->cmd->opcode); |
1361 | ||
8047310e GL |
1362 | host->state = STATE_TIMEOUT; |
1363 | spin_unlock_irqrestore(&host->lock, flags); | |
1364 | ||
f985da17 GL |
1365 | /* |
1366 | * Handle races with cancel_delayed_work(), unless | |
1367 | * cancel_delayed_work_sync() is used | |
1368 | */ | |
1369 | switch (host->wait_for) { | |
1370 | case MMCIF_WAIT_FOR_CMD: | |
1371 | mrq->cmd->error = sh_mmcif_error_manage(host); | |
1372 | break; | |
1373 | case MMCIF_WAIT_FOR_STOP: | |
1374 | mrq->stop->error = sh_mmcif_error_manage(host); | |
1375 | break; | |
1376 | case MMCIF_WAIT_FOR_MREAD: | |
1377 | case MMCIF_WAIT_FOR_MWRITE: | |
1378 | case MMCIF_WAIT_FOR_READ: | |
1379 | case MMCIF_WAIT_FOR_WRITE: | |
1380 | case MMCIF_WAIT_FOR_READ_END: | |
1381 | case MMCIF_WAIT_FOR_WRITE_END: | |
69983404 | 1382 | mrq->data->error = sh_mmcif_error_manage(host); |
f985da17 GL |
1383 | break; |
1384 | default: | |
1385 | BUG(); | |
1386 | } | |
1387 | ||
1388 | host->state = STATE_IDLE; | |
1389 | host->wait_for = MMCIF_WAIT_FOR_REQUEST; | |
f985da17 GL |
1390 | host->mrq = NULL; |
1391 | mmc_request_done(host->mmc, mrq); | |
1392 | } | |
1393 | ||
7d17baa0 GL |
1394 | static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) |
1395 | { | |
585c3a5a KM |
1396 | struct device *dev = sh_mmcif_host_to_dev(host); |
1397 | struct sh_mmcif_plat_data *pd = dev->platform_data; | |
7d17baa0 GL |
1398 | struct mmc_host *mmc = host->mmc; |
1399 | ||
1400 | mmc_regulator_get_supply(mmc); | |
1401 | ||
bf68a812 GL |
1402 | if (!pd) |
1403 | return; | |
1404 | ||
7d17baa0 GL |
1405 | if (!mmc->ocr_avail) |
1406 | mmc->ocr_avail = pd->ocr; | |
1407 | else if (pd->ocr) | |
1408 | dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); | |
1409 | } | |
1410 | ||
c3be1efd | 1411 | static int sh_mmcif_probe(struct platform_device *pdev) |
fdc50a94 YG |
1412 | { |
1413 | int ret = 0, irq[2]; | |
1414 | struct mmc_host *mmc; | |
e47bf32a | 1415 | struct sh_mmcif_host *host; |
60985c39 KM |
1416 | struct device *dev = &pdev->dev; |
1417 | struct sh_mmcif_plat_data *pd = dev->platform_data; | |
fdc50a94 YG |
1418 | struct resource *res; |
1419 | void __iomem *reg; | |
2cd5b3e0 | 1420 | const char *name; |
fdc50a94 YG |
1421 | |
1422 | irq[0] = platform_get_irq(pdev, 0); | |
1423 | irq[1] = platform_get_irq(pdev, 1); | |
2cd5b3e0 | 1424 | if (irq[0] < 0) { |
60985c39 | 1425 | dev_err(dev, "Get irq error\n"); |
fdc50a94 YG |
1426 | return -ENXIO; |
1427 | } | |
18f55fcc | 1428 | |
fdc50a94 | 1429 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
60985c39 | 1430 | reg = devm_ioremap_resource(dev, res); |
18f55fcc BD |
1431 | if (IS_ERR(reg)) |
1432 | return PTR_ERR(reg); | |
e1aae2eb | 1433 | |
60985c39 | 1434 | mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), dev); |
18f55fcc BD |
1435 | if (!mmc) |
1436 | return -ENOMEM; | |
2c9054dc SB |
1437 | |
1438 | ret = mmc_of_parse(mmc); | |
1439 | if (ret < 0) | |
46991005 | 1440 | goto err_host; |
2c9054dc | 1441 | |
fdc50a94 YG |
1442 | host = mmc_priv(mmc); |
1443 | host->mmc = mmc; | |
1444 | host->addr = reg; | |
bad4371d | 1445 | host->timeout = msecs_to_jiffies(10000); |
967bcb77 | 1446 | host->ccs_enable = !pd || !pd->ccs_unsupported; |
6d6fd367 | 1447 | host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present; |
fdc50a94 | 1448 | |
fdc50a94 YG |
1449 | host->pd = pdev; |
1450 | ||
3b0beafc | 1451 | spin_lock_init(&host->lock); |
fdc50a94 YG |
1452 | |
1453 | mmc->ops = &sh_mmcif_ops; | |
7d17baa0 GL |
1454 | sh_mmcif_init_ocr(host); |
1455 | ||
eca889f6 | 1456 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY; |
dab3a28b | 1457 | mmc->caps2 |= MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; |
549646a9 | 1458 | mmc->max_busy_timeout = 10000; |
dab3a28b | 1459 | |
bf68a812 | 1460 | if (pd && pd->caps) |
fdc50a94 | 1461 | mmc->caps |= pd->caps; |
a782d688 | 1462 | mmc->max_segs = 32; |
fdc50a94 | 1463 | mmc->max_blk_size = 512; |
09cbfeaf | 1464 | mmc->max_req_size = PAGE_SIZE * mmc->max_segs; |
a782d688 | 1465 | mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; |
fdc50a94 YG |
1466 | mmc->max_seg_size = mmc->max_req_size; |
1467 | ||
fdc50a94 | 1468 | platform_set_drvdata(pdev, host); |
a782d688 | 1469 | |
6aed678b KM |
1470 | host->clk = devm_clk_get(dev, NULL); |
1471 | if (IS_ERR(host->clk)) { | |
1472 | ret = PTR_ERR(host->clk); | |
60985c39 | 1473 | dev_err(dev, "cannot get clock: %d\n", ret); |
88ac2a2c | 1474 | goto err_host; |
b289174f | 1475 | } |
9bb09a30 KM |
1476 | |
1477 | ret = clk_prepare_enable(host->clk); | |
a6609267 | 1478 | if (ret < 0) |
88ac2a2c | 1479 | goto err_host; |
b289174f | 1480 | |
9bb09a30 KM |
1481 | sh_mmcif_clk_setup(host); |
1482 | ||
88ac2a2c UH |
1483 | pm_runtime_enable(dev); |
1484 | host->power = false; | |
1485 | ||
1486 | ret = pm_runtime_get_sync(dev); | |
faca6648 | 1487 | if (ret < 0) |
46991005 | 1488 | goto err_clk; |
a782d688 | 1489 | |
1b1a694d | 1490 | INIT_DELAYED_WORK(&host->timeout_work, sh_mmcif_timeout_work); |
fdc50a94 | 1491 | |
b289174f | 1492 | sh_mmcif_sync_reset(host); |
3b0beafc GL |
1493 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
1494 | ||
60985c39 KM |
1495 | name = irq[1] < 0 ? dev_name(dev) : "sh_mmc:error"; |
1496 | ret = devm_request_threaded_irq(dev, irq[0], sh_mmcif_intr, | |
6f4789e6 | 1497 | sh_mmcif_irqt, 0, name, host); |
fdc50a94 | 1498 | if (ret) { |
60985c39 | 1499 | dev_err(dev, "request_irq error (%s)\n", name); |
11a80852 | 1500 | goto err_clk; |
fdc50a94 | 1501 | } |
2cd5b3e0 | 1502 | if (irq[1] >= 0) { |
60985c39 | 1503 | ret = devm_request_threaded_irq(dev, irq[1], |
6f4789e6 BD |
1504 | sh_mmcif_intr, sh_mmcif_irqt, |
1505 | 0, "sh_mmc:int", host); | |
2cd5b3e0 | 1506 | if (ret) { |
60985c39 | 1507 | dev_err(dev, "request_irq error (sh_mmc:int)\n"); |
11a80852 | 1508 | goto err_clk; |
2cd5b3e0 | 1509 | } |
fdc50a94 YG |
1510 | } |
1511 | ||
e480606a | 1512 | if (pd && pd->use_cd_gpio) { |
214fc309 | 1513 | ret = mmc_gpio_request_cd(mmc, pd->cd_gpio, 0); |
e480606a | 1514 | if (ret < 0) |
7f67f3a2 | 1515 | goto err_clk; |
e480606a GL |
1516 | } |
1517 | ||
8047310e GL |
1518 | mutex_init(&host->thread_lock); |
1519 | ||
5ba85d95 GL |
1520 | ret = mmc_add_host(mmc); |
1521 | if (ret < 0) | |
7f67f3a2 | 1522 | goto err_clk; |
fdc50a94 | 1523 | |
60985c39 | 1524 | dev_pm_qos_expose_latency_limit(dev, 100); |
efe6a8ad | 1525 | |
60985c39 | 1526 | dev_info(dev, "Chip version 0x%04x, clock rate %luMHz\n", |
ce7eb688 | 1527 | sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff, |
6aed678b | 1528 | clk_get_rate(host->clk) / 1000000UL); |
ce7eb688 | 1529 | |
88ac2a2c | 1530 | pm_runtime_put(dev); |
6aed678b | 1531 | clk_disable_unprepare(host->clk); |
fdc50a94 YG |
1532 | return ret; |
1533 | ||
46991005 | 1534 | err_clk: |
6aed678b | 1535 | clk_disable_unprepare(host->clk); |
88ac2a2c | 1536 | pm_runtime_put_sync(dev); |
60985c39 | 1537 | pm_runtime_disable(dev); |
46991005 | 1538 | err_host: |
fdc50a94 | 1539 | mmc_free_host(mmc); |
fdc50a94 YG |
1540 | return ret; |
1541 | } | |
1542 | ||
6e0ee714 | 1543 | static int sh_mmcif_remove(struct platform_device *pdev) |
fdc50a94 YG |
1544 | { |
1545 | struct sh_mmcif_host *host = platform_get_drvdata(pdev); | |
fdc50a94 | 1546 | |
f985da17 | 1547 | host->dying = true; |
6aed678b | 1548 | clk_prepare_enable(host->clk); |
faca6648 | 1549 | pm_runtime_get_sync(&pdev->dev); |
fdc50a94 | 1550 | |
efe6a8ad RW |
1551 | dev_pm_qos_hide_latency_limit(&pdev->dev); |
1552 | ||
faca6648 | 1553 | mmc_remove_host(host->mmc); |
3b0beafc GL |
1554 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
1555 | ||
f985da17 GL |
1556 | /* |
1557 | * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the | |
1558 | * mmc_remove_host() call above. But swapping order doesn't help either | |
1559 | * (a query on the linux-mmc mailing list didn't bring any replies). | |
1560 | */ | |
1561 | cancel_delayed_work_sync(&host->timeout_work); | |
1562 | ||
6aed678b | 1563 | clk_disable_unprepare(host->clk); |
fdc50a94 | 1564 | mmc_free_host(host->mmc); |
faca6648 GL |
1565 | pm_runtime_put_sync(&pdev->dev); |
1566 | pm_runtime_disable(&pdev->dev); | |
fdc50a94 YG |
1567 | |
1568 | return 0; | |
1569 | } | |
1570 | ||
51129f31 | 1571 | #ifdef CONFIG_PM_SLEEP |
faca6648 GL |
1572 | static int sh_mmcif_suspend(struct device *dev) |
1573 | { | |
b289174f | 1574 | struct sh_mmcif_host *host = dev_get_drvdata(dev); |
faca6648 | 1575 | |
5afc30fc | 1576 | pm_runtime_get_sync(dev); |
cb3ca1ae | 1577 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
5afc30fc | 1578 | pm_runtime_put(dev); |
faca6648 | 1579 | |
cb3ca1ae | 1580 | return 0; |
faca6648 GL |
1581 | } |
1582 | ||
1583 | static int sh_mmcif_resume(struct device *dev) | |
1584 | { | |
cb3ca1ae | 1585 | return 0; |
faca6648 | 1586 | } |
51129f31 | 1587 | #endif |
faca6648 GL |
1588 | |
1589 | static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { | |
51129f31 | 1590 | SET_SYSTEM_SLEEP_PM_OPS(sh_mmcif_suspend, sh_mmcif_resume) |
faca6648 GL |
1591 | }; |
1592 | ||
fdc50a94 YG |
1593 | static struct platform_driver sh_mmcif_driver = { |
1594 | .probe = sh_mmcif_probe, | |
1595 | .remove = sh_mmcif_remove, | |
1596 | .driver = { | |
1597 | .name = DRIVER_NAME, | |
faca6648 | 1598 | .pm = &sh_mmcif_dev_pm_ops, |
1b1a694d | 1599 | .of_match_table = sh_mmcif_of_match, |
fdc50a94 YG |
1600 | }, |
1601 | }; | |
1602 | ||
d1f81a64 | 1603 | module_platform_driver(sh_mmcif_driver); |
fdc50a94 YG |
1604 | |
1605 | MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); | |
1606 | MODULE_LICENSE("GPL"); | |
aa0787a9 | 1607 | MODULE_ALIAS("platform:" DRIVER_NAME); |
fdc50a94 | 1608 | MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); |