Commit | Line | Data |
---|---|---|
fdc50a94 YG |
1 | /* |
2 | * MMCIF eMMC driver. | |
3 | * | |
4 | * Copyright (C) 2010 Renesas Solutions Corp. | |
5 | * Yusuke Goda <yusuke.goda.sx@renesas.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License. | |
10 | * | |
11 | * | |
12 | * TODO | |
13 | * 1. DMA | |
14 | * 2. Power management | |
15 | * 3. Handle MMC errors better | |
16 | * | |
17 | */ | |
18 | ||
f985da17 GL |
19 | /* |
20 | * The MMCIF driver is now processing MMC requests asynchronously, according | |
21 | * to the Linux MMC API requirement. | |
22 | * | |
23 | * The MMCIF driver processes MMC requests in up to 3 stages: command, optional | |
24 | * data, and optional stop. To achieve asynchronous processing each of these | |
25 | * stages is split into two halves: a top and a bottom half. The top half | |
26 | * initialises the hardware, installs a timeout handler to handle completion | |
27 | * timeouts, and returns. In case of the command stage this immediately returns | |
28 | * control to the caller, leaving all further processing to run asynchronously. | |
29 | * All further request processing is performed by the bottom halves. | |
30 | * | |
31 | * The bottom half further consists of a "hard" IRQ handler, an IRQ handler | |
32 | * thread, a DMA completion callback, if DMA is used, a timeout work, and | |
33 | * request- and stage-specific handler methods. | |
34 | * | |
35 | * Each bottom half run begins with either a hardware interrupt, a DMA callback | |
36 | * invocation, or a timeout work run. In case of an error or a successful | |
37 | * processing completion, the MMC core is informed and the request processing is | |
38 | * finished. In case processing has to continue, i.e., if data has to be read | |
39 | * from or written to the card, or if a stop command has to be sent, the next | |
40 | * top half is called, which performs the necessary hardware handling and | |
41 | * reschedules the timeout work. This returns the driver state machine into the | |
42 | * bottom half waiting state. | |
43 | */ | |
44 | ||
86df1745 | 45 | #include <linux/bitops.h> |
aa0787a9 GL |
46 | #include <linux/clk.h> |
47 | #include <linux/completion.h> | |
e47bf32a | 48 | #include <linux/delay.h> |
fdc50a94 | 49 | #include <linux/dma-mapping.h> |
a782d688 | 50 | #include <linux/dmaengine.h> |
fdc50a94 YG |
51 | #include <linux/mmc/card.h> |
52 | #include <linux/mmc/core.h> | |
e47bf32a | 53 | #include <linux/mmc/host.h> |
fdc50a94 YG |
54 | #include <linux/mmc/mmc.h> |
55 | #include <linux/mmc/sdio.h> | |
fdc50a94 | 56 | #include <linux/mmc/sh_mmcif.h> |
e480606a | 57 | #include <linux/mmc/slot-gpio.h> |
bf68a812 | 58 | #include <linux/mod_devicetable.h> |
8047310e | 59 | #include <linux/mutex.h> |
89d49a70 | 60 | #include <linux/of_device.h> |
a782d688 | 61 | #include <linux/pagemap.h> |
e47bf32a | 62 | #include <linux/platform_device.h> |
efe6a8ad | 63 | #include <linux/pm_qos.h> |
faca6648 | 64 | #include <linux/pm_runtime.h> |
d00cadac | 65 | #include <linux/sh_dma.h> |
3b0beafc | 66 | #include <linux/spinlock.h> |
88b47679 | 67 | #include <linux/module.h> |
fdc50a94 YG |
68 | |
69 | #define DRIVER_NAME "sh_mmcif" | |
70 | #define DRIVER_VERSION "2010-04-28" | |
71 | ||
fdc50a94 YG |
72 | /* CE_CMD_SET */ |
73 | #define CMD_MASK 0x3f000000 | |
74 | #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) | |
75 | #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ | |
76 | #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ | |
77 | #define CMD_SET_RBSY (1 << 21) /* R1b */ | |
78 | #define CMD_SET_CCSEN (1 << 20) | |
79 | #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ | |
80 | #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ | |
81 | #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ | |
82 | #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ | |
83 | #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ | |
84 | #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ | |
85 | #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ | |
86 | #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ | |
87 | #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ | |
88 | #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ | |
89 | #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ | |
90 | #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ | |
91 | #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ | |
92 | #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ | |
93 | #define CMD_SET_CCSH (1 << 5) | |
555061f9 | 94 | #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */ |
fdc50a94 YG |
95 | #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ |
96 | #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ | |
97 | #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ | |
98 | ||
99 | /* CE_CMD_CTRL */ | |
100 | #define CMD_CTRL_BREAK (1 << 0) | |
101 | ||
102 | /* CE_BLOCK_SET */ | |
103 | #define BLOCK_SIZE_MASK 0x0000ffff | |
104 | ||
fdc50a94 YG |
105 | /* CE_INT */ |
106 | #define INT_CCSDE (1 << 29) | |
107 | #define INT_CMD12DRE (1 << 26) | |
108 | #define INT_CMD12RBE (1 << 25) | |
109 | #define INT_CMD12CRE (1 << 24) | |
110 | #define INT_DTRANE (1 << 23) | |
111 | #define INT_BUFRE (1 << 22) | |
112 | #define INT_BUFWEN (1 << 21) | |
113 | #define INT_BUFREN (1 << 20) | |
114 | #define INT_CCSRCV (1 << 19) | |
115 | #define INT_RBSYE (1 << 17) | |
116 | #define INT_CRSPE (1 << 16) | |
117 | #define INT_CMDVIO (1 << 15) | |
118 | #define INT_BUFVIO (1 << 14) | |
119 | #define INT_WDATERR (1 << 11) | |
120 | #define INT_RDATERR (1 << 10) | |
121 | #define INT_RIDXERR (1 << 9) | |
122 | #define INT_RSPERR (1 << 8) | |
123 | #define INT_CCSTO (1 << 5) | |
124 | #define INT_CRCSTO (1 << 4) | |
125 | #define INT_WDATTO (1 << 3) | |
126 | #define INT_RDATTO (1 << 2) | |
127 | #define INT_RBSYTO (1 << 1) | |
128 | #define INT_RSPTO (1 << 0) | |
129 | #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ | |
130 | INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ | |
131 | INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ | |
132 | INT_RDATTO | INT_RBSYTO | INT_RSPTO) | |
133 | ||
8af50750 GL |
134 | #define INT_ALL (INT_RBSYE | INT_CRSPE | INT_BUFREN | \ |
135 | INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \ | |
136 | INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE) | |
137 | ||
967bcb77 GL |
138 | #define INT_CCS (INT_CCSTO | INT_CCSRCV | INT_CCSDE) |
139 | ||
fdc50a94 YG |
140 | /* CE_INT_MASK */ |
141 | #define MASK_ALL 0x00000000 | |
142 | #define MASK_MCCSDE (1 << 29) | |
143 | #define MASK_MCMD12DRE (1 << 26) | |
144 | #define MASK_MCMD12RBE (1 << 25) | |
145 | #define MASK_MCMD12CRE (1 << 24) | |
146 | #define MASK_MDTRANE (1 << 23) | |
147 | #define MASK_MBUFRE (1 << 22) | |
148 | #define MASK_MBUFWEN (1 << 21) | |
149 | #define MASK_MBUFREN (1 << 20) | |
150 | #define MASK_MCCSRCV (1 << 19) | |
151 | #define MASK_MRBSYE (1 << 17) | |
152 | #define MASK_MCRSPE (1 << 16) | |
153 | #define MASK_MCMDVIO (1 << 15) | |
154 | #define MASK_MBUFVIO (1 << 14) | |
155 | #define MASK_MWDATERR (1 << 11) | |
156 | #define MASK_MRDATERR (1 << 10) | |
157 | #define MASK_MRIDXERR (1 << 9) | |
158 | #define MASK_MRSPERR (1 << 8) | |
159 | #define MASK_MCCSTO (1 << 5) | |
160 | #define MASK_MCRCSTO (1 << 4) | |
161 | #define MASK_MWDATTO (1 << 3) | |
162 | #define MASK_MRDATTO (1 << 2) | |
163 | #define MASK_MRBSYTO (1 << 1) | |
164 | #define MASK_MRSPTO (1 << 0) | |
165 | ||
ee4b8887 GL |
166 | #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ |
167 | MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ | |
967bcb77 | 168 | MASK_MCRCSTO | MASK_MWDATTO | \ |
ee4b8887 GL |
169 | MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) |
170 | ||
8af50750 GL |
171 | #define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \ |
172 | MASK_MBUFREN | MASK_MBUFWEN | \ | |
173 | MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE | \ | |
174 | MASK_MCMD12RBE | MASK_MCMD12CRE) | |
175 | ||
fdc50a94 YG |
176 | /* CE_HOST_STS1 */ |
177 | #define STS1_CMDSEQ (1 << 31) | |
178 | ||
179 | /* CE_HOST_STS2 */ | |
180 | #define STS2_CRCSTE (1 << 31) | |
181 | #define STS2_CRC16E (1 << 30) | |
182 | #define STS2_AC12CRCE (1 << 29) | |
183 | #define STS2_RSPCRC7E (1 << 28) | |
184 | #define STS2_CRCSTEBE (1 << 27) | |
185 | #define STS2_RDATEBE (1 << 26) | |
186 | #define STS2_AC12REBE (1 << 25) | |
187 | #define STS2_RSPEBE (1 << 24) | |
188 | #define STS2_AC12IDXE (1 << 23) | |
189 | #define STS2_RSPIDXE (1 << 22) | |
190 | #define STS2_CCSTO (1 << 15) | |
191 | #define STS2_RDATTO (1 << 14) | |
192 | #define STS2_DATBSYTO (1 << 13) | |
193 | #define STS2_CRCSTTO (1 << 12) | |
194 | #define STS2_AC12BSYTO (1 << 11) | |
195 | #define STS2_RSPBSYTO (1 << 10) | |
196 | #define STS2_AC12RSPTO (1 << 9) | |
197 | #define STS2_RSPTO (1 << 8) | |
198 | #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ | |
199 | STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) | |
200 | #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ | |
201 | STS2_DATBSYTO | STS2_CRCSTTO | \ | |
202 | STS2_AC12BSYTO | STS2_RSPBSYTO | \ | |
203 | STS2_AC12RSPTO | STS2_RSPTO) | |
204 | ||
fdc50a94 YG |
205 | #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ |
206 | #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ | |
207 | #define CLKDEV_INIT 400000 /* 400 KHz */ | |
208 | ||
1b1a694d | 209 | enum sh_mmcif_state { |
3b0beafc GL |
210 | STATE_IDLE, |
211 | STATE_REQUEST, | |
212 | STATE_IOS, | |
8047310e | 213 | STATE_TIMEOUT, |
3b0beafc GL |
214 | }; |
215 | ||
1b1a694d | 216 | enum sh_mmcif_wait_for { |
f985da17 GL |
217 | MMCIF_WAIT_FOR_REQUEST, |
218 | MMCIF_WAIT_FOR_CMD, | |
219 | MMCIF_WAIT_FOR_MREAD, | |
220 | MMCIF_WAIT_FOR_MWRITE, | |
221 | MMCIF_WAIT_FOR_READ, | |
222 | MMCIF_WAIT_FOR_WRITE, | |
223 | MMCIF_WAIT_FOR_READ_END, | |
224 | MMCIF_WAIT_FOR_WRITE_END, | |
225 | MMCIF_WAIT_FOR_STOP, | |
226 | }; | |
227 | ||
89d49a70 KM |
228 | /* |
229 | * difference for each SoC | |
230 | */ | |
fdc50a94 YG |
231 | struct sh_mmcif_host { |
232 | struct mmc_host *mmc; | |
f985da17 | 233 | struct mmc_request *mrq; |
fdc50a94 | 234 | struct platform_device *pd; |
6aed678b | 235 | struct clk *clk; |
fdc50a94 | 236 | int bus_width; |
555061f9 | 237 | unsigned char timing; |
aa0787a9 | 238 | bool sd_error; |
f985da17 | 239 | bool dying; |
fdc50a94 YG |
240 | long timeout; |
241 | void __iomem *addr; | |
f985da17 | 242 | u32 *pio_ptr; |
ee4b8887 | 243 | spinlock_t lock; /* protect sh_mmcif_host::state */ |
1b1a694d KM |
244 | enum sh_mmcif_state state; |
245 | enum sh_mmcif_wait_for wait_for; | |
f985da17 GL |
246 | struct delayed_work timeout_work; |
247 | size_t blocksize; | |
248 | int sg_idx; | |
249 | int sg_blkidx; | |
faca6648 | 250 | bool power; |
c9b0cef2 | 251 | bool card_present; |
967bcb77 | 252 | bool ccs_enable; /* Command Completion Signal support */ |
6d6fd367 | 253 | bool clk_ctrl2_enable; |
8047310e | 254 | struct mutex thread_lock; |
89d49a70 | 255 | u32 clkdiv_map; /* see CE_CLK_CTRL::CLKDIV */ |
fdc50a94 | 256 | |
a782d688 GL |
257 | /* DMA support */ |
258 | struct dma_chan *chan_rx; | |
259 | struct dma_chan *chan_tx; | |
260 | struct completion dma_complete; | |
f38f94c6 | 261 | bool dma_active; |
a782d688 | 262 | }; |
fdc50a94 | 263 | |
1b1a694d | 264 | static const struct of_device_id sh_mmcif_of_match[] = { |
70830b41 KM |
265 | { .compatible = "renesas,sh-mmcif" }, |
266 | { } | |
267 | }; | |
1b1a694d | 268 | MODULE_DEVICE_TABLE(of, sh_mmcif_of_match); |
70830b41 | 269 | |
585c3a5a KM |
270 | #define sh_mmcif_host_to_dev(host) (&host->pd->dev) |
271 | ||
fdc50a94 YG |
272 | static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, |
273 | unsigned int reg, u32 val) | |
274 | { | |
487d9fc5 | 275 | writel(val | readl(host->addr + reg), host->addr + reg); |
fdc50a94 YG |
276 | } |
277 | ||
278 | static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, | |
279 | unsigned int reg, u32 val) | |
280 | { | |
487d9fc5 | 281 | writel(~val & readl(host->addr + reg), host->addr + reg); |
fdc50a94 YG |
282 | } |
283 | ||
1b1a694d | 284 | static void sh_mmcif_dma_complete(void *arg) |
a782d688 GL |
285 | { |
286 | struct sh_mmcif_host *host = arg; | |
8047310e | 287 | struct mmc_request *mrq = host->mrq; |
585c3a5a | 288 | struct device *dev = sh_mmcif_host_to_dev(host); |
69983404 | 289 | |
585c3a5a | 290 | dev_dbg(dev, "Command completed\n"); |
a782d688 | 291 | |
8047310e | 292 | if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n", |
585c3a5a | 293 | dev_name(dev))) |
a782d688 GL |
294 | return; |
295 | ||
a782d688 GL |
296 | complete(&host->dma_complete); |
297 | } | |
298 | ||
299 | static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) | |
300 | { | |
69983404 GL |
301 | struct mmc_data *data = host->mrq->data; |
302 | struct scatterlist *sg = data->sg; | |
a782d688 GL |
303 | struct dma_async_tx_descriptor *desc = NULL; |
304 | struct dma_chan *chan = host->chan_rx; | |
585c3a5a | 305 | struct device *dev = sh_mmcif_host_to_dev(host); |
a782d688 GL |
306 | dma_cookie_t cookie = -EINVAL; |
307 | int ret; | |
308 | ||
69983404 | 309 | ret = dma_map_sg(chan->device->dev, sg, data->sg_len, |
1ed828db | 310 | DMA_FROM_DEVICE); |
a782d688 | 311 | if (ret > 0) { |
f38f94c6 | 312 | host->dma_active = true; |
16052827 | 313 | desc = dmaengine_prep_slave_sg(chan, sg, ret, |
05f5799c | 314 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
a782d688 GL |
315 | } |
316 | ||
317 | if (desc) { | |
1b1a694d | 318 | desc->callback = sh_mmcif_dma_complete; |
a782d688 | 319 | desc->callback_param = host; |
a5ece7d2 LW |
320 | cookie = dmaengine_submit(desc); |
321 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); | |
322 | dma_async_issue_pending(chan); | |
a782d688 | 323 | } |
585c3a5a | 324 | dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n", |
69983404 | 325 | __func__, data->sg_len, ret, cookie); |
a782d688 GL |
326 | |
327 | if (!desc) { | |
328 | /* DMA failed, fall back to PIO */ | |
329 | if (ret >= 0) | |
330 | ret = -EIO; | |
331 | host->chan_rx = NULL; | |
f38f94c6 | 332 | host->dma_active = false; |
a782d688 GL |
333 | dma_release_channel(chan); |
334 | /* Free the Tx channel too */ | |
335 | chan = host->chan_tx; | |
336 | if (chan) { | |
337 | host->chan_tx = NULL; | |
338 | dma_release_channel(chan); | |
339 | } | |
585c3a5a | 340 | dev_warn(dev, |
a782d688 GL |
341 | "DMA failed: %d, falling back to PIO\n", ret); |
342 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
343 | } | |
344 | ||
585c3a5a | 345 | dev_dbg(dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, |
69983404 | 346 | desc, cookie, data->sg_len); |
a782d688 GL |
347 | } |
348 | ||
349 | static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) | |
350 | { | |
69983404 GL |
351 | struct mmc_data *data = host->mrq->data; |
352 | struct scatterlist *sg = data->sg; | |
a782d688 GL |
353 | struct dma_async_tx_descriptor *desc = NULL; |
354 | struct dma_chan *chan = host->chan_tx; | |
585c3a5a | 355 | struct device *dev = sh_mmcif_host_to_dev(host); |
a782d688 GL |
356 | dma_cookie_t cookie = -EINVAL; |
357 | int ret; | |
358 | ||
69983404 | 359 | ret = dma_map_sg(chan->device->dev, sg, data->sg_len, |
1ed828db | 360 | DMA_TO_DEVICE); |
a782d688 | 361 | if (ret > 0) { |
f38f94c6 | 362 | host->dma_active = true; |
16052827 | 363 | desc = dmaengine_prep_slave_sg(chan, sg, ret, |
05f5799c | 364 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
a782d688 GL |
365 | } |
366 | ||
367 | if (desc) { | |
1b1a694d | 368 | desc->callback = sh_mmcif_dma_complete; |
a782d688 | 369 | desc->callback_param = host; |
a5ece7d2 LW |
370 | cookie = dmaengine_submit(desc); |
371 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); | |
372 | dma_async_issue_pending(chan); | |
a782d688 | 373 | } |
585c3a5a | 374 | dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n", |
69983404 | 375 | __func__, data->sg_len, ret, cookie); |
a782d688 GL |
376 | |
377 | if (!desc) { | |
378 | /* DMA failed, fall back to PIO */ | |
379 | if (ret >= 0) | |
380 | ret = -EIO; | |
381 | host->chan_tx = NULL; | |
f38f94c6 | 382 | host->dma_active = false; |
a782d688 GL |
383 | dma_release_channel(chan); |
384 | /* Free the Rx channel too */ | |
385 | chan = host->chan_rx; | |
386 | if (chan) { | |
387 | host->chan_rx = NULL; | |
388 | dma_release_channel(chan); | |
389 | } | |
585c3a5a | 390 | dev_warn(dev, |
a782d688 GL |
391 | "DMA failed: %d, falling back to PIO\n", ret); |
392 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
393 | } | |
394 | ||
585c3a5a | 395 | dev_dbg(dev, "%s(): desc %p, cookie %d\n", __func__, |
a782d688 GL |
396 | desc, cookie); |
397 | } | |
398 | ||
e5a233cb LP |
399 | static struct dma_chan * |
400 | sh_mmcif_request_dma_one(struct sh_mmcif_host *host, | |
401 | struct sh_mmcif_plat_data *pdata, | |
402 | enum dma_transfer_direction direction) | |
a782d688 | 403 | { |
d25006e7 | 404 | struct dma_slave_config cfg = { 0, }; |
e5a233cb | 405 | struct dma_chan *chan; |
5f48dd06 | 406 | void *slave_data = NULL; |
e5a233cb | 407 | struct resource *res; |
585c3a5a | 408 | struct device *dev = sh_mmcif_host_to_dev(host); |
0e79f9ae GL |
409 | dma_cap_mask_t mask; |
410 | int ret; | |
a782d688 | 411 | |
e5a233cb LP |
412 | dma_cap_zero(mask); |
413 | dma_cap_set(DMA_SLAVE, mask); | |
414 | ||
415 | if (pdata) | |
5f48dd06 KM |
416 | slave_data = direction == DMA_MEM_TO_DEV ? |
417 | (void *)pdata->slave_id_tx : | |
418 | (void *)pdata->slave_id_rx; | |
e5a233cb LP |
419 | |
420 | chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, | |
585c3a5a | 421 | slave_data, dev, |
e5a233cb LP |
422 | direction == DMA_MEM_TO_DEV ? "tx" : "rx"); |
423 | ||
585c3a5a | 424 | dev_dbg(dev, "%s: %s: got channel %p\n", __func__, |
e5a233cb LP |
425 | direction == DMA_MEM_TO_DEV ? "TX" : "RX", chan); |
426 | ||
427 | if (!chan) | |
428 | return NULL; | |
429 | ||
430 | res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); | |
431 | ||
e5a233cb | 432 | cfg.direction = direction; |
d25006e7 | 433 | |
e36152aa | 434 | if (direction == DMA_DEV_TO_MEM) { |
d25006e7 | 435 | cfg.src_addr = res->start + MMCIF_CE_DATA; |
e36152aa LP |
436 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
437 | } else { | |
d25006e7 | 438 | cfg.dst_addr = res->start + MMCIF_CE_DATA; |
e36152aa LP |
439 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
440 | } | |
d25006e7 | 441 | |
e5a233cb LP |
442 | ret = dmaengine_slave_config(chan, &cfg); |
443 | if (ret < 0) { | |
444 | dma_release_channel(chan); | |
445 | return NULL; | |
446 | } | |
447 | ||
448 | return chan; | |
449 | } | |
450 | ||
451 | static void sh_mmcif_request_dma(struct sh_mmcif_host *host, | |
452 | struct sh_mmcif_plat_data *pdata) | |
453 | { | |
585c3a5a | 454 | struct device *dev = sh_mmcif_host_to_dev(host); |
f38f94c6 | 455 | host->dma_active = false; |
a782d688 | 456 | |
acd6d772 GL |
457 | if (pdata) { |
458 | if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0) | |
459 | return; | |
585c3a5a | 460 | } else if (!dev->of_node) { |
0e79f9ae | 461 | return; |
acd6d772 | 462 | } |
a782d688 | 463 | |
0e79f9ae | 464 | /* We can only either use DMA for both Tx and Rx or not use it at all */ |
e5a233cb | 465 | host->chan_tx = sh_mmcif_request_dma_one(host, pdata, DMA_MEM_TO_DEV); |
0e79f9ae GL |
466 | if (!host->chan_tx) |
467 | return; | |
a782d688 | 468 | |
e5a233cb LP |
469 | host->chan_rx = sh_mmcif_request_dma_one(host, pdata, DMA_DEV_TO_MEM); |
470 | if (!host->chan_rx) { | |
471 | dma_release_channel(host->chan_tx); | |
472 | host->chan_tx = NULL; | |
473 | } | |
a782d688 GL |
474 | } |
475 | ||
476 | static void sh_mmcif_release_dma(struct sh_mmcif_host *host) | |
477 | { | |
478 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
479 | /* Descriptors are freed automatically */ | |
480 | if (host->chan_tx) { | |
481 | struct dma_chan *chan = host->chan_tx; | |
482 | host->chan_tx = NULL; | |
483 | dma_release_channel(chan); | |
484 | } | |
485 | if (host->chan_rx) { | |
486 | struct dma_chan *chan = host->chan_rx; | |
487 | host->chan_rx = NULL; | |
488 | dma_release_channel(chan); | |
489 | } | |
490 | ||
f38f94c6 | 491 | host->dma_active = false; |
a782d688 | 492 | } |
fdc50a94 YG |
493 | |
494 | static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) | |
495 | { | |
585c3a5a KM |
496 | struct device *dev = sh_mmcif_host_to_dev(host); |
497 | struct sh_mmcif_plat_data *p = dev->platform_data; | |
bf68a812 | 498 | bool sup_pclk = p ? p->sup_pclk : false; |
6aed678b | 499 | unsigned int current_clk = clk_get_rate(host->clk); |
89d49a70 | 500 | unsigned int clkdiv; |
fdc50a94 YG |
501 | |
502 | sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); | |
503 | sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); | |
504 | ||
505 | if (!clk) | |
506 | return; | |
fdc50a94 | 507 | |
89d49a70 KM |
508 | if (host->clkdiv_map) { |
509 | unsigned int freq, best_freq, myclk, div, diff_min, diff; | |
510 | int i; | |
511 | ||
512 | clkdiv = 0; | |
513 | diff_min = ~0; | |
514 | best_freq = 0; | |
515 | for (i = 31; i >= 0; i--) { | |
516 | if (!((1 << i) & host->clkdiv_map)) | |
517 | continue; | |
518 | ||
519 | /* | |
520 | * clk = parent_freq / div | |
521 | * -> parent_freq = clk x div | |
522 | */ | |
523 | ||
524 | div = 1 << (i + 1); | |
525 | freq = clk_round_rate(host->clk, clk * div); | |
526 | myclk = freq / div; | |
527 | diff = (myclk > clk) ? myclk - clk : clk - myclk; | |
528 | ||
529 | if (diff <= diff_min) { | |
530 | best_freq = freq; | |
531 | clkdiv = i; | |
532 | diff_min = diff; | |
533 | } | |
534 | } | |
535 | ||
536 | dev_dbg(dev, "clk %u/%u (%u, 0x%x)\n", | |
537 | (best_freq / (1 << (clkdiv + 1))), clk, | |
538 | best_freq, clkdiv); | |
539 | ||
540 | clk_set_rate(host->clk, best_freq); | |
541 | clkdiv = clkdiv << 16; | |
542 | } else if (sup_pclk && clk == current_clk) { | |
543 | clkdiv = CLK_SUP_PCLK; | |
544 | } else { | |
545 | clkdiv = (fls(DIV_ROUND_UP(current_clk, clk) - 1) - 1) << 16; | |
546 | } | |
547 | ||
548 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & clkdiv); | |
fdc50a94 YG |
549 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); |
550 | } | |
551 | ||
552 | static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) | |
553 | { | |
554 | u32 tmp; | |
555 | ||
487d9fc5 | 556 | tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); |
fdc50a94 | 557 | |
487d9fc5 MD |
558 | sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); |
559 | sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); | |
967bcb77 GL |
560 | if (host->ccs_enable) |
561 | tmp |= SCCSTO_29; | |
6d6fd367 GL |
562 | if (host->clk_ctrl2_enable) |
563 | sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000); | |
fdc50a94 | 564 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | |
967bcb77 | 565 | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29); |
fdc50a94 YG |
566 | /* byte swap on */ |
567 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); | |
568 | } | |
569 | ||
570 | static int sh_mmcif_error_manage(struct sh_mmcif_host *host) | |
571 | { | |
585c3a5a | 572 | struct device *dev = sh_mmcif_host_to_dev(host); |
fdc50a94 | 573 | u32 state1, state2; |
ee4b8887 | 574 | int ret, timeout; |
fdc50a94 | 575 | |
aa0787a9 | 576 | host->sd_error = false; |
fdc50a94 | 577 | |
487d9fc5 MD |
578 | state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); |
579 | state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); | |
585c3a5a KM |
580 | dev_dbg(dev, "ERR HOST_STS1 = %08x\n", state1); |
581 | dev_dbg(dev, "ERR HOST_STS2 = %08x\n", state2); | |
fdc50a94 YG |
582 | |
583 | if (state1 & STS1_CMDSEQ) { | |
584 | sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); | |
585 | sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); | |
ee4b8887 | 586 | for (timeout = 10000000; timeout; timeout--) { |
487d9fc5 | 587 | if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) |
ee4b8887 | 588 | & STS1_CMDSEQ)) |
fdc50a94 YG |
589 | break; |
590 | mdelay(1); | |
591 | } | |
ee4b8887 | 592 | if (!timeout) { |
585c3a5a | 593 | dev_err(dev, |
ee4b8887 GL |
594 | "Forced end of command sequence timeout err\n"); |
595 | return -EIO; | |
596 | } | |
fdc50a94 | 597 | sh_mmcif_sync_reset(host); |
585c3a5a | 598 | dev_dbg(dev, "Forced end of command sequence\n"); |
fdc50a94 YG |
599 | return -EIO; |
600 | } | |
601 | ||
602 | if (state2 & STS2_CRC_ERR) { | |
585c3a5a | 603 | dev_err(dev, " CRC error: state %u, wait %u\n", |
e475b270 | 604 | host->state, host->wait_for); |
fdc50a94 YG |
605 | ret = -EIO; |
606 | } else if (state2 & STS2_TIMEOUT_ERR) { | |
585c3a5a | 607 | dev_err(dev, " Timeout: state %u, wait %u\n", |
e475b270 | 608 | host->state, host->wait_for); |
fdc50a94 YG |
609 | ret = -ETIMEDOUT; |
610 | } else { | |
585c3a5a | 611 | dev_dbg(dev, " End/Index error: state %u, wait %u\n", |
e475b270 | 612 | host->state, host->wait_for); |
fdc50a94 YG |
613 | ret = -EIO; |
614 | } | |
615 | return ret; | |
616 | } | |
617 | ||
f985da17 | 618 | static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) |
fdc50a94 | 619 | { |
f985da17 GL |
620 | struct mmc_data *data = host->mrq->data; |
621 | ||
622 | host->sg_blkidx += host->blocksize; | |
623 | ||
624 | /* data->sg->length must be a multiple of host->blocksize? */ | |
625 | BUG_ON(host->sg_blkidx > data->sg->length); | |
626 | ||
627 | if (host->sg_blkidx == data->sg->length) { | |
628 | host->sg_blkidx = 0; | |
629 | if (++host->sg_idx < data->sg_len) | |
630 | host->pio_ptr = sg_virt(++data->sg); | |
631 | } else { | |
632 | host->pio_ptr = p; | |
633 | } | |
634 | ||
99eb9d8d | 635 | return host->sg_idx != data->sg_len; |
f985da17 GL |
636 | } |
637 | ||
638 | static void sh_mmcif_single_read(struct sh_mmcif_host *host, | |
639 | struct mmc_request *mrq) | |
640 | { | |
641 | host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & | |
642 | BLOCK_SIZE_MASK) + 3; | |
643 | ||
644 | host->wait_for = MMCIF_WAIT_FOR_READ; | |
fdc50a94 | 645 | |
fdc50a94 YG |
646 | /* buf read enable */ |
647 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); | |
f985da17 GL |
648 | } |
649 | ||
650 | static bool sh_mmcif_read_block(struct sh_mmcif_host *host) | |
651 | { | |
585c3a5a | 652 | struct device *dev = sh_mmcif_host_to_dev(host); |
f985da17 GL |
653 | struct mmc_data *data = host->mrq->data; |
654 | u32 *p = sg_virt(data->sg); | |
655 | int i; | |
656 | ||
657 | if (host->sd_error) { | |
658 | data->error = sh_mmcif_error_manage(host); | |
585c3a5a | 659 | dev_dbg(dev, "%s(): %d\n", __func__, data->error); |
f985da17 GL |
660 | return false; |
661 | } | |
662 | ||
663 | for (i = 0; i < host->blocksize / 4; i++) | |
487d9fc5 | 664 | *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); |
fdc50a94 YG |
665 | |
666 | /* buffer read end */ | |
667 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); | |
f985da17 | 668 | host->wait_for = MMCIF_WAIT_FOR_READ_END; |
fdc50a94 | 669 | |
f985da17 | 670 | return true; |
fdc50a94 YG |
671 | } |
672 | ||
f985da17 GL |
673 | static void sh_mmcif_multi_read(struct sh_mmcif_host *host, |
674 | struct mmc_request *mrq) | |
fdc50a94 YG |
675 | { |
676 | struct mmc_data *data = mrq->data; | |
f985da17 GL |
677 | |
678 | if (!data->sg_len || !data->sg->length) | |
679 | return; | |
680 | ||
681 | host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & | |
682 | BLOCK_SIZE_MASK; | |
683 | ||
684 | host->wait_for = MMCIF_WAIT_FOR_MREAD; | |
685 | host->sg_idx = 0; | |
686 | host->sg_blkidx = 0; | |
687 | host->pio_ptr = sg_virt(data->sg); | |
5df460b1 | 688 | |
f985da17 GL |
689 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); |
690 | } | |
691 | ||
692 | static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) | |
693 | { | |
585c3a5a | 694 | struct device *dev = sh_mmcif_host_to_dev(host); |
f985da17 GL |
695 | struct mmc_data *data = host->mrq->data; |
696 | u32 *p = host->pio_ptr; | |
697 | int i; | |
698 | ||
699 | if (host->sd_error) { | |
700 | data->error = sh_mmcif_error_manage(host); | |
585c3a5a | 701 | dev_dbg(dev, "%s(): %d\n", __func__, data->error); |
f985da17 | 702 | return false; |
fdc50a94 | 703 | } |
f985da17 GL |
704 | |
705 | BUG_ON(!data->sg->length); | |
706 | ||
707 | for (i = 0; i < host->blocksize / 4; i++) | |
708 | *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); | |
709 | ||
710 | if (!sh_mmcif_next_block(host, p)) | |
711 | return false; | |
712 | ||
f985da17 GL |
713 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); |
714 | ||
715 | return true; | |
fdc50a94 YG |
716 | } |
717 | ||
f985da17 | 718 | static void sh_mmcif_single_write(struct sh_mmcif_host *host, |
fdc50a94 YG |
719 | struct mmc_request *mrq) |
720 | { | |
f985da17 GL |
721 | host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & |
722 | BLOCK_SIZE_MASK) + 3; | |
fdc50a94 | 723 | |
f985da17 | 724 | host->wait_for = MMCIF_WAIT_FOR_WRITE; |
fdc50a94 YG |
725 | |
726 | /* buf write enable */ | |
f985da17 GL |
727 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); |
728 | } | |
729 | ||
730 | static bool sh_mmcif_write_block(struct sh_mmcif_host *host) | |
731 | { | |
585c3a5a | 732 | struct device *dev = sh_mmcif_host_to_dev(host); |
f985da17 GL |
733 | struct mmc_data *data = host->mrq->data; |
734 | u32 *p = sg_virt(data->sg); | |
735 | int i; | |
736 | ||
737 | if (host->sd_error) { | |
738 | data->error = sh_mmcif_error_manage(host); | |
585c3a5a | 739 | dev_dbg(dev, "%s(): %d\n", __func__, data->error); |
f985da17 GL |
740 | return false; |
741 | } | |
742 | ||
743 | for (i = 0; i < host->blocksize / 4; i++) | |
487d9fc5 | 744 | sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); |
fdc50a94 YG |
745 | |
746 | /* buffer write end */ | |
747 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); | |
f985da17 | 748 | host->wait_for = MMCIF_WAIT_FOR_WRITE_END; |
fdc50a94 | 749 | |
f985da17 | 750 | return true; |
fdc50a94 YG |
751 | } |
752 | ||
f985da17 GL |
753 | static void sh_mmcif_multi_write(struct sh_mmcif_host *host, |
754 | struct mmc_request *mrq) | |
fdc50a94 YG |
755 | { |
756 | struct mmc_data *data = mrq->data; | |
fdc50a94 | 757 | |
f985da17 GL |
758 | if (!data->sg_len || !data->sg->length) |
759 | return; | |
fdc50a94 | 760 | |
f985da17 GL |
761 | host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & |
762 | BLOCK_SIZE_MASK; | |
fdc50a94 | 763 | |
f985da17 GL |
764 | host->wait_for = MMCIF_WAIT_FOR_MWRITE; |
765 | host->sg_idx = 0; | |
766 | host->sg_blkidx = 0; | |
767 | host->pio_ptr = sg_virt(data->sg); | |
5df460b1 | 768 | |
f985da17 GL |
769 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); |
770 | } | |
fdc50a94 | 771 | |
f985da17 GL |
772 | static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) |
773 | { | |
585c3a5a | 774 | struct device *dev = sh_mmcif_host_to_dev(host); |
f985da17 GL |
775 | struct mmc_data *data = host->mrq->data; |
776 | u32 *p = host->pio_ptr; | |
777 | int i; | |
778 | ||
779 | if (host->sd_error) { | |
780 | data->error = sh_mmcif_error_manage(host); | |
585c3a5a | 781 | dev_dbg(dev, "%s(): %d\n", __func__, data->error); |
f985da17 | 782 | return false; |
fdc50a94 | 783 | } |
f985da17 GL |
784 | |
785 | BUG_ON(!data->sg->length); | |
786 | ||
787 | for (i = 0; i < host->blocksize / 4; i++) | |
788 | sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); | |
789 | ||
790 | if (!sh_mmcif_next_block(host, p)) | |
791 | return false; | |
792 | ||
f985da17 GL |
793 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); |
794 | ||
795 | return true; | |
fdc50a94 YG |
796 | } |
797 | ||
798 | static void sh_mmcif_get_response(struct sh_mmcif_host *host, | |
799 | struct mmc_command *cmd) | |
800 | { | |
801 | if (cmd->flags & MMC_RSP_136) { | |
487d9fc5 MD |
802 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); |
803 | cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); | |
804 | cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); | |
805 | cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); | |
fdc50a94 | 806 | } else |
487d9fc5 | 807 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); |
fdc50a94 YG |
808 | } |
809 | ||
810 | static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, | |
811 | struct mmc_command *cmd) | |
812 | { | |
487d9fc5 | 813 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); |
fdc50a94 YG |
814 | } |
815 | ||
816 | static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, | |
69983404 | 817 | struct mmc_request *mrq) |
fdc50a94 | 818 | { |
585c3a5a | 819 | struct device *dev = sh_mmcif_host_to_dev(host); |
69983404 GL |
820 | struct mmc_data *data = mrq->data; |
821 | struct mmc_command *cmd = mrq->cmd; | |
822 | u32 opc = cmd->opcode; | |
fdc50a94 YG |
823 | u32 tmp = 0; |
824 | ||
825 | /* Response Type check */ | |
826 | switch (mmc_resp_type(cmd)) { | |
827 | case MMC_RSP_NONE: | |
828 | tmp |= CMD_SET_RTYP_NO; | |
829 | break; | |
830 | case MMC_RSP_R1: | |
831 | case MMC_RSP_R1B: | |
832 | case MMC_RSP_R3: | |
833 | tmp |= CMD_SET_RTYP_6B; | |
834 | break; | |
835 | case MMC_RSP_R2: | |
836 | tmp |= CMD_SET_RTYP_17B; | |
837 | break; | |
838 | default: | |
585c3a5a | 839 | dev_err(dev, "Unsupported response type.\n"); |
fdc50a94 YG |
840 | break; |
841 | } | |
842 | switch (opc) { | |
843 | /* RBSY */ | |
a812ba0f | 844 | case MMC_SLEEP_AWAKE: |
fdc50a94 YG |
845 | case MMC_SWITCH: |
846 | case MMC_STOP_TRANSMISSION: | |
847 | case MMC_SET_WRITE_PROT: | |
848 | case MMC_CLR_WRITE_PROT: | |
849 | case MMC_ERASE: | |
fdc50a94 YG |
850 | tmp |= CMD_SET_RBSY; |
851 | break; | |
852 | } | |
853 | /* WDAT / DATW */ | |
69983404 | 854 | if (data) { |
fdc50a94 YG |
855 | tmp |= CMD_SET_WDAT; |
856 | switch (host->bus_width) { | |
857 | case MMC_BUS_WIDTH_1: | |
858 | tmp |= CMD_SET_DATW_1; | |
859 | break; | |
860 | case MMC_BUS_WIDTH_4: | |
861 | tmp |= CMD_SET_DATW_4; | |
862 | break; | |
863 | case MMC_BUS_WIDTH_8: | |
864 | tmp |= CMD_SET_DATW_8; | |
865 | break; | |
866 | default: | |
585c3a5a | 867 | dev_err(dev, "Unsupported bus width.\n"); |
fdc50a94 YG |
868 | break; |
869 | } | |
555061f9 | 870 | switch (host->timing) { |
4039ff47 | 871 | case MMC_TIMING_MMC_DDR52: |
555061f9 TK |
872 | /* |
873 | * MMC core will only set this timing, if the host | |
4039ff47 SJ |
874 | * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR |
875 | * capability. MMCIF implementations with this | |
876 | * capability, e.g. sh73a0, will have to set it | |
877 | * in their platform data. | |
555061f9 TK |
878 | */ |
879 | tmp |= CMD_SET_DARS; | |
880 | break; | |
881 | } | |
fdc50a94 YG |
882 | } |
883 | /* DWEN */ | |
884 | if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) | |
885 | tmp |= CMD_SET_DWEN; | |
886 | /* CMLTE/CMD12EN */ | |
887 | if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { | |
888 | tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; | |
889 | sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, | |
69983404 | 890 | data->blocks << 16); |
fdc50a94 YG |
891 | } |
892 | /* RIDXC[1:0] check bits */ | |
893 | if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || | |
894 | opc == MMC_SEND_CSD || opc == MMC_SEND_CID) | |
895 | tmp |= CMD_SET_RIDXC_BITS; | |
896 | /* RCRC7C[1:0] check bits */ | |
897 | if (opc == MMC_SEND_OP_COND) | |
898 | tmp |= CMD_SET_CRC7C_BITS; | |
899 | /* RCRC7C[1:0] internal CRC7 */ | |
900 | if (opc == MMC_ALL_SEND_CID || | |
901 | opc == MMC_SEND_CSD || opc == MMC_SEND_CID) | |
902 | tmp |= CMD_SET_CRC7C_INTERNAL; | |
903 | ||
69983404 | 904 | return (opc << 24) | tmp; |
fdc50a94 YG |
905 | } |
906 | ||
e47bf32a | 907 | static int sh_mmcif_data_trans(struct sh_mmcif_host *host, |
f985da17 | 908 | struct mmc_request *mrq, u32 opc) |
fdc50a94 | 909 | { |
585c3a5a KM |
910 | struct device *dev = sh_mmcif_host_to_dev(host); |
911 | ||
fdc50a94 YG |
912 | switch (opc) { |
913 | case MMC_READ_MULTIPLE_BLOCK: | |
f985da17 GL |
914 | sh_mmcif_multi_read(host, mrq); |
915 | return 0; | |
fdc50a94 | 916 | case MMC_WRITE_MULTIPLE_BLOCK: |
f985da17 GL |
917 | sh_mmcif_multi_write(host, mrq); |
918 | return 0; | |
fdc50a94 | 919 | case MMC_WRITE_BLOCK: |
f985da17 GL |
920 | sh_mmcif_single_write(host, mrq); |
921 | return 0; | |
fdc50a94 YG |
922 | case MMC_READ_SINGLE_BLOCK: |
923 | case MMC_SEND_EXT_CSD: | |
f985da17 GL |
924 | sh_mmcif_single_read(host, mrq); |
925 | return 0; | |
fdc50a94 | 926 | default: |
585c3a5a | 927 | dev_err(dev, "Unsupported CMD%d\n", opc); |
ee4b8887 | 928 | return -EINVAL; |
fdc50a94 | 929 | } |
fdc50a94 YG |
930 | } |
931 | ||
932 | static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, | |
ee4b8887 | 933 | struct mmc_request *mrq) |
fdc50a94 | 934 | { |
ee4b8887 | 935 | struct mmc_command *cmd = mrq->cmd; |
f985da17 GL |
936 | u32 opc = cmd->opcode; |
937 | u32 mask; | |
dbb42d96 | 938 | unsigned long flags; |
fdc50a94 | 939 | |
fdc50a94 | 940 | switch (opc) { |
ee4b8887 | 941 | /* response busy check */ |
a812ba0f | 942 | case MMC_SLEEP_AWAKE: |
fdc50a94 YG |
943 | case MMC_SWITCH: |
944 | case MMC_STOP_TRANSMISSION: | |
945 | case MMC_SET_WRITE_PROT: | |
946 | case MMC_CLR_WRITE_PROT: | |
947 | case MMC_ERASE: | |
ee4b8887 | 948 | mask = MASK_START_CMD | MASK_MRBSYE; |
fdc50a94 YG |
949 | break; |
950 | default: | |
ee4b8887 | 951 | mask = MASK_START_CMD | MASK_MCRSPE; |
fdc50a94 YG |
952 | break; |
953 | } | |
fdc50a94 | 954 | |
967bcb77 GL |
955 | if (host->ccs_enable) |
956 | mask |= MASK_MCCSTO; | |
957 | ||
69983404 | 958 | if (mrq->data) { |
487d9fc5 MD |
959 | sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); |
960 | sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, | |
961 | mrq->data->blksz); | |
fdc50a94 | 962 | } |
69983404 | 963 | opc = sh_mmcif_set_cmd(host, mrq); |
fdc50a94 | 964 | |
967bcb77 GL |
965 | if (host->ccs_enable) |
966 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); | |
967 | else | |
968 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS); | |
487d9fc5 | 969 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); |
fdc50a94 | 970 | /* set arg */ |
487d9fc5 | 971 | sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); |
fdc50a94 | 972 | /* set cmd */ |
dbb42d96 | 973 | spin_lock_irqsave(&host->lock, flags); |
487d9fc5 | 974 | sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); |
fdc50a94 | 975 | |
f985da17 GL |
976 | host->wait_for = MMCIF_WAIT_FOR_CMD; |
977 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
dbb42d96 | 978 | spin_unlock_irqrestore(&host->lock, flags); |
fdc50a94 YG |
979 | } |
980 | ||
981 | static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, | |
ee4b8887 | 982 | struct mmc_request *mrq) |
fdc50a94 | 983 | { |
585c3a5a KM |
984 | struct device *dev = sh_mmcif_host_to_dev(host); |
985 | ||
69983404 GL |
986 | switch (mrq->cmd->opcode) { |
987 | case MMC_READ_MULTIPLE_BLOCK: | |
fdc50a94 | 988 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); |
69983404 GL |
989 | break; |
990 | case MMC_WRITE_MULTIPLE_BLOCK: | |
fdc50a94 | 991 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); |
69983404 GL |
992 | break; |
993 | default: | |
585c3a5a | 994 | dev_err(dev, "unsupported stop cmd\n"); |
69983404 | 995 | mrq->stop->error = sh_mmcif_error_manage(host); |
fdc50a94 YG |
996 | return; |
997 | } | |
998 | ||
f985da17 | 999 | host->wait_for = MMCIF_WAIT_FOR_STOP; |
fdc50a94 YG |
1000 | } |
1001 | ||
1002 | static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1003 | { | |
1004 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
585c3a5a | 1005 | struct device *dev = sh_mmcif_host_to_dev(host); |
3b0beafc GL |
1006 | unsigned long flags; |
1007 | ||
1008 | spin_lock_irqsave(&host->lock, flags); | |
1009 | if (host->state != STATE_IDLE) { | |
585c3a5a KM |
1010 | dev_dbg(dev, "%s() rejected, state %u\n", |
1011 | __func__, host->state); | |
3b0beafc GL |
1012 | spin_unlock_irqrestore(&host->lock, flags); |
1013 | mrq->cmd->error = -EAGAIN; | |
1014 | mmc_request_done(mmc, mrq); | |
1015 | return; | |
1016 | } | |
1017 | ||
1018 | host->state = STATE_REQUEST; | |
1019 | spin_unlock_irqrestore(&host->lock, flags); | |
fdc50a94 YG |
1020 | |
1021 | switch (mrq->cmd->opcode) { | |
1022 | /* MMCIF does not support SD/SDIO command */ | |
7541ca98 LP |
1023 | case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */ |
1024 | case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ | |
1025 | if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR) | |
1026 | break; | |
fdc50a94 | 1027 | case MMC_APP_CMD: |
92ff0c5b | 1028 | case SD_IO_RW_DIRECT: |
3b0beafc | 1029 | host->state = STATE_IDLE; |
fdc50a94 YG |
1030 | mrq->cmd->error = -ETIMEDOUT; |
1031 | mmc_request_done(mmc, mrq); | |
1032 | return; | |
fdc50a94 YG |
1033 | default: |
1034 | break; | |
1035 | } | |
f985da17 GL |
1036 | |
1037 | host->mrq = mrq; | |
fdc50a94 | 1038 | |
f985da17 | 1039 | sh_mmcif_start_cmd(host, mrq); |
fdc50a94 YG |
1040 | } |
1041 | ||
9bb09a30 | 1042 | static void sh_mmcif_clk_setup(struct sh_mmcif_host *host) |
a6609267 | 1043 | { |
89d49a70 KM |
1044 | struct device *dev = sh_mmcif_host_to_dev(host); |
1045 | ||
1046 | if (host->mmc->f_max) { | |
1047 | unsigned int f_max, f_min = 0, f_min_old; | |
1048 | ||
1049 | f_max = host->mmc->f_max; | |
1050 | for (f_min_old = f_max; f_min_old > 2;) { | |
1051 | f_min = clk_round_rate(host->clk, f_min_old / 2); | |
1052 | if (f_min == f_min_old) | |
1053 | break; | |
1054 | f_min_old = f_min; | |
1055 | } | |
1056 | ||
1057 | /* | |
1058 | * This driver assumes this SoC is R-Car Gen2 or later | |
1059 | */ | |
1060 | host->clkdiv_map = 0x3ff; | |
1061 | ||
1062 | host->mmc->f_max = f_max / (1 << ffs(host->clkdiv_map)); | |
1063 | host->mmc->f_min = f_min / (1 << fls(host->clkdiv_map)); | |
1064 | } else { | |
1065 | unsigned int clk = clk_get_rate(host->clk); | |
1066 | ||
1067 | host->mmc->f_max = clk / 2; | |
1068 | host->mmc->f_min = clk / 512; | |
1069 | } | |
a6609267 | 1070 | |
89d49a70 KM |
1071 | dev_dbg(dev, "clk max/min = %d/%d\n", |
1072 | host->mmc->f_max, host->mmc->f_min); | |
a6609267 GL |
1073 | } |
1074 | ||
7d17baa0 GL |
1075 | static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios) |
1076 | { | |
7d17baa0 GL |
1077 | struct mmc_host *mmc = host->mmc; |
1078 | ||
7d17baa0 GL |
1079 | if (!IS_ERR(mmc->supply.vmmc)) |
1080 | /* Errors ignored... */ | |
1081 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, | |
1082 | ios->power_mode ? ios->vdd : 0); | |
1083 | } | |
1084 | ||
fdc50a94 YG |
1085 | static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
1086 | { | |
1087 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
585c3a5a | 1088 | struct device *dev = sh_mmcif_host_to_dev(host); |
3b0beafc GL |
1089 | unsigned long flags; |
1090 | ||
1091 | spin_lock_irqsave(&host->lock, flags); | |
1092 | if (host->state != STATE_IDLE) { | |
585c3a5a KM |
1093 | dev_dbg(dev, "%s() rejected, state %u\n", |
1094 | __func__, host->state); | |
3b0beafc GL |
1095 | spin_unlock_irqrestore(&host->lock, flags); |
1096 | return; | |
1097 | } | |
1098 | ||
1099 | host->state = STATE_IOS; | |
1100 | spin_unlock_irqrestore(&host->lock, flags); | |
fdc50a94 | 1101 | |
f5e0cec4 | 1102 | if (ios->power_mode == MMC_POWER_UP) { |
c9b0cef2 | 1103 | if (!host->card_present) { |
faca6648 | 1104 | /* See if we also get DMA */ |
585c3a5a | 1105 | sh_mmcif_request_dma(host, dev->platform_data); |
c9b0cef2 | 1106 | host->card_present = true; |
faca6648 | 1107 | } |
7d17baa0 | 1108 | sh_mmcif_set_power(host, ios); |
f5e0cec4 | 1109 | } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) { |
fdc50a94 YG |
1110 | /* clock stop */ |
1111 | sh_mmcif_clock_control(host, 0); | |
faca6648 | 1112 | if (ios->power_mode == MMC_POWER_OFF) { |
c9b0cef2 | 1113 | if (host->card_present) { |
faca6648 | 1114 | sh_mmcif_release_dma(host); |
c9b0cef2 | 1115 | host->card_present = false; |
faca6648 | 1116 | } |
c9b0cef2 GL |
1117 | } |
1118 | if (host->power) { | |
585c3a5a | 1119 | pm_runtime_put_sync(dev); |
6aed678b | 1120 | clk_disable_unprepare(host->clk); |
c9b0cef2 | 1121 | host->power = false; |
7d17baa0 GL |
1122 | if (ios->power_mode == MMC_POWER_OFF) |
1123 | sh_mmcif_set_power(host, ios); | |
faca6648 | 1124 | } |
3b0beafc | 1125 | host->state = STATE_IDLE; |
fdc50a94 | 1126 | return; |
fdc50a94 YG |
1127 | } |
1128 | ||
c9b0cef2 GL |
1129 | if (ios->clock) { |
1130 | if (!host->power) { | |
9bb09a30 KM |
1131 | clk_prepare_enable(host->clk); |
1132 | ||
585c3a5a | 1133 | pm_runtime_get_sync(dev); |
c9b0cef2 GL |
1134 | host->power = true; |
1135 | sh_mmcif_sync_reset(host); | |
1136 | } | |
fdc50a94 | 1137 | sh_mmcif_clock_control(host, ios->clock); |
c9b0cef2 | 1138 | } |
fdc50a94 | 1139 | |
555061f9 | 1140 | host->timing = ios->timing; |
fdc50a94 | 1141 | host->bus_width = ios->bus_width; |
3b0beafc | 1142 | host->state = STATE_IDLE; |
fdc50a94 YG |
1143 | } |
1144 | ||
777271d0 AH |
1145 | static int sh_mmcif_get_cd(struct mmc_host *mmc) |
1146 | { | |
1147 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
585c3a5a KM |
1148 | struct device *dev = sh_mmcif_host_to_dev(host); |
1149 | struct sh_mmcif_plat_data *p = dev->platform_data; | |
e480606a GL |
1150 | int ret = mmc_gpio_get_cd(mmc); |
1151 | ||
1152 | if (ret >= 0) | |
1153 | return ret; | |
777271d0 | 1154 | |
bf68a812 | 1155 | if (!p || !p->get_cd) |
777271d0 AH |
1156 | return -ENOSYS; |
1157 | else | |
1158 | return p->get_cd(host->pd); | |
1159 | } | |
1160 | ||
fdc50a94 YG |
1161 | static struct mmc_host_ops sh_mmcif_ops = { |
1162 | .request = sh_mmcif_request, | |
1163 | .set_ios = sh_mmcif_set_ios, | |
777271d0 | 1164 | .get_cd = sh_mmcif_get_cd, |
fdc50a94 YG |
1165 | }; |
1166 | ||
f985da17 GL |
1167 | static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) |
1168 | { | |
1169 | struct mmc_command *cmd = host->mrq->cmd; | |
69983404 | 1170 | struct mmc_data *data = host->mrq->data; |
585c3a5a | 1171 | struct device *dev = sh_mmcif_host_to_dev(host); |
f985da17 GL |
1172 | long time; |
1173 | ||
1174 | if (host->sd_error) { | |
1175 | switch (cmd->opcode) { | |
1176 | case MMC_ALL_SEND_CID: | |
1177 | case MMC_SELECT_CARD: | |
1178 | case MMC_APP_CMD: | |
1179 | cmd->error = -ETIMEDOUT; | |
f985da17 GL |
1180 | break; |
1181 | default: | |
1182 | cmd->error = sh_mmcif_error_manage(host); | |
f985da17 GL |
1183 | break; |
1184 | } | |
585c3a5a | 1185 | dev_dbg(dev, "CMD%d error %d\n", |
e475b270 | 1186 | cmd->opcode, cmd->error); |
aba9d646 | 1187 | host->sd_error = false; |
f985da17 GL |
1188 | return false; |
1189 | } | |
1190 | if (!(cmd->flags & MMC_RSP_PRESENT)) { | |
1191 | cmd->error = 0; | |
1192 | return false; | |
1193 | } | |
1194 | ||
1195 | sh_mmcif_get_response(host, cmd); | |
1196 | ||
69983404 | 1197 | if (!data) |
f985da17 GL |
1198 | return false; |
1199 | ||
90f1cb43 GL |
1200 | /* |
1201 | * Completion can be signalled from DMA callback and error, so, have to | |
1202 | * reset here, before setting .dma_active | |
1203 | */ | |
1204 | init_completion(&host->dma_complete); | |
1205 | ||
69983404 | 1206 | if (data->flags & MMC_DATA_READ) { |
f985da17 GL |
1207 | if (host->chan_rx) |
1208 | sh_mmcif_start_dma_rx(host); | |
1209 | } else { | |
1210 | if (host->chan_tx) | |
1211 | sh_mmcif_start_dma_tx(host); | |
1212 | } | |
1213 | ||
1214 | if (!host->dma_active) { | |
69983404 | 1215 | data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); |
99eb9d8d | 1216 | return !data->error; |
f985da17 GL |
1217 | } |
1218 | ||
1219 | /* Running in the IRQ thread, can sleep */ | |
1220 | time = wait_for_completion_interruptible_timeout(&host->dma_complete, | |
1221 | host->timeout); | |
eae30983 TK |
1222 | |
1223 | if (data->flags & MMC_DATA_READ) | |
1224 | dma_unmap_sg(host->chan_rx->device->dev, | |
1225 | data->sg, data->sg_len, | |
1226 | DMA_FROM_DEVICE); | |
1227 | else | |
1228 | dma_unmap_sg(host->chan_tx->device->dev, | |
1229 | data->sg, data->sg_len, | |
1230 | DMA_TO_DEVICE); | |
1231 | ||
f985da17 GL |
1232 | if (host->sd_error) { |
1233 | dev_err(host->mmc->parent, | |
1234 | "Error IRQ while waiting for DMA completion!\n"); | |
1235 | /* Woken up by an error IRQ: abort DMA */ | |
69983404 | 1236 | data->error = sh_mmcif_error_manage(host); |
f985da17 | 1237 | } else if (!time) { |
e475b270 | 1238 | dev_err(host->mmc->parent, "DMA timeout!\n"); |
69983404 | 1239 | data->error = -ETIMEDOUT; |
f985da17 | 1240 | } else if (time < 0) { |
e475b270 TK |
1241 | dev_err(host->mmc->parent, |
1242 | "wait_for_completion_...() error %ld!\n", time); | |
69983404 | 1243 | data->error = time; |
f985da17 GL |
1244 | } |
1245 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, | |
1246 | BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
1247 | host->dma_active = false; | |
1248 | ||
eae30983 | 1249 | if (data->error) { |
69983404 | 1250 | data->bytes_xfered = 0; |
eae30983 TK |
1251 | /* Abort DMA */ |
1252 | if (data->flags & MMC_DATA_READ) | |
1253 | dmaengine_terminate_all(host->chan_rx); | |
1254 | else | |
1255 | dmaengine_terminate_all(host->chan_tx); | |
1256 | } | |
f985da17 GL |
1257 | |
1258 | return false; | |
1259 | } | |
1260 | ||
1261 | static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) | |
1262 | { | |
1263 | struct sh_mmcif_host *host = dev_id; | |
8047310e | 1264 | struct mmc_request *mrq; |
585c3a5a | 1265 | struct device *dev = sh_mmcif_host_to_dev(host); |
5df460b1 | 1266 | bool wait = false; |
dbb42d96 KT |
1267 | unsigned long flags; |
1268 | int wait_work; | |
1269 | ||
1270 | spin_lock_irqsave(&host->lock, flags); | |
1271 | wait_work = host->wait_for; | |
1272 | spin_unlock_irqrestore(&host->lock, flags); | |
f985da17 GL |
1273 | |
1274 | cancel_delayed_work_sync(&host->timeout_work); | |
1275 | ||
8047310e GL |
1276 | mutex_lock(&host->thread_lock); |
1277 | ||
1278 | mrq = host->mrq; | |
1279 | if (!mrq) { | |
585c3a5a | 1280 | dev_dbg(dev, "IRQ thread state %u, wait %u: NULL mrq!\n", |
8047310e GL |
1281 | host->state, host->wait_for); |
1282 | mutex_unlock(&host->thread_lock); | |
1283 | return IRQ_HANDLED; | |
1284 | } | |
1285 | ||
f985da17 GL |
1286 | /* |
1287 | * All handlers return true, if processing continues, and false, if the | |
1288 | * request has to be completed - successfully or not | |
1289 | */ | |
dbb42d96 | 1290 | switch (wait_work) { |
f985da17 GL |
1291 | case MMCIF_WAIT_FOR_REQUEST: |
1292 | /* We're too late, the timeout has already kicked in */ | |
8047310e | 1293 | mutex_unlock(&host->thread_lock); |
f985da17 GL |
1294 | return IRQ_HANDLED; |
1295 | case MMCIF_WAIT_FOR_CMD: | |
5df460b1 GL |
1296 | /* Wait for data? */ |
1297 | wait = sh_mmcif_end_cmd(host); | |
f985da17 GL |
1298 | break; |
1299 | case MMCIF_WAIT_FOR_MREAD: | |
5df460b1 GL |
1300 | /* Wait for more data? */ |
1301 | wait = sh_mmcif_mread_block(host); | |
f985da17 GL |
1302 | break; |
1303 | case MMCIF_WAIT_FOR_READ: | |
5df460b1 GL |
1304 | /* Wait for data end? */ |
1305 | wait = sh_mmcif_read_block(host); | |
f985da17 GL |
1306 | break; |
1307 | case MMCIF_WAIT_FOR_MWRITE: | |
5df460b1 GL |
1308 | /* Wait data to write? */ |
1309 | wait = sh_mmcif_mwrite_block(host); | |
f985da17 GL |
1310 | break; |
1311 | case MMCIF_WAIT_FOR_WRITE: | |
5df460b1 GL |
1312 | /* Wait for data end? */ |
1313 | wait = sh_mmcif_write_block(host); | |
f985da17 GL |
1314 | break; |
1315 | case MMCIF_WAIT_FOR_STOP: | |
1316 | if (host->sd_error) { | |
1317 | mrq->stop->error = sh_mmcif_error_manage(host); | |
585c3a5a | 1318 | dev_dbg(dev, "%s(): %d\n", __func__, mrq->stop->error); |
f985da17 GL |
1319 | break; |
1320 | } | |
1321 | sh_mmcif_get_cmd12response(host, mrq->stop); | |
1322 | mrq->stop->error = 0; | |
1323 | break; | |
1324 | case MMCIF_WAIT_FOR_READ_END: | |
1325 | case MMCIF_WAIT_FOR_WRITE_END: | |
e475b270 | 1326 | if (host->sd_error) { |
91ab252a | 1327 | mrq->data->error = sh_mmcif_error_manage(host); |
585c3a5a | 1328 | dev_dbg(dev, "%s(): %d\n", __func__, mrq->data->error); |
e475b270 | 1329 | } |
f985da17 GL |
1330 | break; |
1331 | default: | |
1332 | BUG(); | |
1333 | } | |
1334 | ||
5df460b1 GL |
1335 | if (wait) { |
1336 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
1337 | /* Wait for more data */ | |
8047310e | 1338 | mutex_unlock(&host->thread_lock); |
5df460b1 GL |
1339 | return IRQ_HANDLED; |
1340 | } | |
1341 | ||
f985da17 | 1342 | if (host->wait_for != MMCIF_WAIT_FOR_STOP) { |
91ab252a | 1343 | struct mmc_data *data = mrq->data; |
69983404 GL |
1344 | if (!mrq->cmd->error && data && !data->error) |
1345 | data->bytes_xfered = | |
1346 | data->blocks * data->blksz; | |
f985da17 | 1347 | |
69983404 | 1348 | if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { |
f985da17 | 1349 | sh_mmcif_stop_cmd(host, mrq); |
5df460b1 GL |
1350 | if (!mrq->stop->error) { |
1351 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
8047310e | 1352 | mutex_unlock(&host->thread_lock); |
f985da17 | 1353 | return IRQ_HANDLED; |
5df460b1 | 1354 | } |
f985da17 GL |
1355 | } |
1356 | } | |
1357 | ||
1358 | host->wait_for = MMCIF_WAIT_FOR_REQUEST; | |
1359 | host->state = STATE_IDLE; | |
69983404 | 1360 | host->mrq = NULL; |
f985da17 GL |
1361 | mmc_request_done(host->mmc, mrq); |
1362 | ||
8047310e GL |
1363 | mutex_unlock(&host->thread_lock); |
1364 | ||
f985da17 GL |
1365 | return IRQ_HANDLED; |
1366 | } | |
1367 | ||
fdc50a94 YG |
1368 | static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) |
1369 | { | |
1370 | struct sh_mmcif_host *host = dev_id; | |
585c3a5a | 1371 | struct device *dev = sh_mmcif_host_to_dev(host); |
967bcb77 | 1372 | u32 state, mask; |
fdc50a94 | 1373 | |
487d9fc5 | 1374 | state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); |
967bcb77 GL |
1375 | mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK); |
1376 | if (host->ccs_enable) | |
1377 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask)); | |
1378 | else | |
1379 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask)); | |
8af50750 | 1380 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); |
fdc50a94 | 1381 | |
8af50750 | 1382 | if (state & ~MASK_CLEAN) |
585c3a5a | 1383 | dev_dbg(dev, "IRQ state = 0x%08x incompletely cleared\n", |
8af50750 GL |
1384 | state); |
1385 | ||
1386 | if (state & INT_ERR_STS || state & ~INT_ALL) { | |
aa0787a9 | 1387 | host->sd_error = true; |
585c3a5a | 1388 | dev_dbg(dev, "int err state = 0x%08x\n", state); |
fdc50a94 | 1389 | } |
f985da17 | 1390 | if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { |
8af50750 | 1391 | if (!host->mrq) |
585c3a5a | 1392 | dev_dbg(dev, "NULL IRQ state = 0x%08x\n", state); |
f985da17 GL |
1393 | if (!host->dma_active) |
1394 | return IRQ_WAKE_THREAD; | |
1395 | else if (host->sd_error) | |
1b1a694d | 1396 | sh_mmcif_dma_complete(host); |
f985da17 | 1397 | } else { |
585c3a5a | 1398 | dev_dbg(dev, "Unexpected IRQ 0x%x\n", state); |
f985da17 | 1399 | } |
fdc50a94 YG |
1400 | |
1401 | return IRQ_HANDLED; | |
1402 | } | |
1403 | ||
1b1a694d | 1404 | static void sh_mmcif_timeout_work(struct work_struct *work) |
f985da17 GL |
1405 | { |
1406 | struct delayed_work *d = container_of(work, struct delayed_work, work); | |
1407 | struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); | |
1408 | struct mmc_request *mrq = host->mrq; | |
585c3a5a | 1409 | struct device *dev = sh_mmcif_host_to_dev(host); |
8047310e | 1410 | unsigned long flags; |
f985da17 GL |
1411 | |
1412 | if (host->dying) | |
1413 | /* Don't run after mmc_remove_host() */ | |
1414 | return; | |
1415 | ||
8047310e GL |
1416 | spin_lock_irqsave(&host->lock, flags); |
1417 | if (host->state == STATE_IDLE) { | |
1418 | spin_unlock_irqrestore(&host->lock, flags); | |
1419 | return; | |
1420 | } | |
1421 | ||
585c3a5a | 1422 | dev_err(dev, "Timeout waiting for %u on CMD%u\n", |
4cbd5224 KT |
1423 | host->wait_for, mrq->cmd->opcode); |
1424 | ||
8047310e GL |
1425 | host->state = STATE_TIMEOUT; |
1426 | spin_unlock_irqrestore(&host->lock, flags); | |
1427 | ||
f985da17 GL |
1428 | /* |
1429 | * Handle races with cancel_delayed_work(), unless | |
1430 | * cancel_delayed_work_sync() is used | |
1431 | */ | |
1432 | switch (host->wait_for) { | |
1433 | case MMCIF_WAIT_FOR_CMD: | |
1434 | mrq->cmd->error = sh_mmcif_error_manage(host); | |
1435 | break; | |
1436 | case MMCIF_WAIT_FOR_STOP: | |
1437 | mrq->stop->error = sh_mmcif_error_manage(host); | |
1438 | break; | |
1439 | case MMCIF_WAIT_FOR_MREAD: | |
1440 | case MMCIF_WAIT_FOR_MWRITE: | |
1441 | case MMCIF_WAIT_FOR_READ: | |
1442 | case MMCIF_WAIT_FOR_WRITE: | |
1443 | case MMCIF_WAIT_FOR_READ_END: | |
1444 | case MMCIF_WAIT_FOR_WRITE_END: | |
69983404 | 1445 | mrq->data->error = sh_mmcif_error_manage(host); |
f985da17 GL |
1446 | break; |
1447 | default: | |
1448 | BUG(); | |
1449 | } | |
1450 | ||
1451 | host->state = STATE_IDLE; | |
1452 | host->wait_for = MMCIF_WAIT_FOR_REQUEST; | |
f985da17 GL |
1453 | host->mrq = NULL; |
1454 | mmc_request_done(host->mmc, mrq); | |
1455 | } | |
1456 | ||
7d17baa0 GL |
1457 | static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) |
1458 | { | |
585c3a5a KM |
1459 | struct device *dev = sh_mmcif_host_to_dev(host); |
1460 | struct sh_mmcif_plat_data *pd = dev->platform_data; | |
7d17baa0 GL |
1461 | struct mmc_host *mmc = host->mmc; |
1462 | ||
1463 | mmc_regulator_get_supply(mmc); | |
1464 | ||
bf68a812 GL |
1465 | if (!pd) |
1466 | return; | |
1467 | ||
7d17baa0 GL |
1468 | if (!mmc->ocr_avail) |
1469 | mmc->ocr_avail = pd->ocr; | |
1470 | else if (pd->ocr) | |
1471 | dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); | |
1472 | } | |
1473 | ||
c3be1efd | 1474 | static int sh_mmcif_probe(struct platform_device *pdev) |
fdc50a94 YG |
1475 | { |
1476 | int ret = 0, irq[2]; | |
1477 | struct mmc_host *mmc; | |
e47bf32a | 1478 | struct sh_mmcif_host *host; |
60985c39 KM |
1479 | struct device *dev = &pdev->dev; |
1480 | struct sh_mmcif_plat_data *pd = dev->platform_data; | |
fdc50a94 YG |
1481 | struct resource *res; |
1482 | void __iomem *reg; | |
2cd5b3e0 | 1483 | const char *name; |
fdc50a94 YG |
1484 | |
1485 | irq[0] = platform_get_irq(pdev, 0); | |
1486 | irq[1] = platform_get_irq(pdev, 1); | |
2cd5b3e0 | 1487 | if (irq[0] < 0) { |
60985c39 | 1488 | dev_err(dev, "Get irq error\n"); |
fdc50a94 YG |
1489 | return -ENXIO; |
1490 | } | |
18f55fcc | 1491 | |
fdc50a94 | 1492 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
60985c39 | 1493 | reg = devm_ioremap_resource(dev, res); |
18f55fcc BD |
1494 | if (IS_ERR(reg)) |
1495 | return PTR_ERR(reg); | |
e1aae2eb | 1496 | |
60985c39 | 1497 | mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), dev); |
18f55fcc BD |
1498 | if (!mmc) |
1499 | return -ENOMEM; | |
2c9054dc SB |
1500 | |
1501 | ret = mmc_of_parse(mmc); | |
1502 | if (ret < 0) | |
46991005 | 1503 | goto err_host; |
2c9054dc | 1504 | |
fdc50a94 YG |
1505 | host = mmc_priv(mmc); |
1506 | host->mmc = mmc; | |
1507 | host->addr = reg; | |
bad4371d | 1508 | host->timeout = msecs_to_jiffies(10000); |
967bcb77 | 1509 | host->ccs_enable = !pd || !pd->ccs_unsupported; |
6d6fd367 | 1510 | host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present; |
fdc50a94 | 1511 | |
fdc50a94 YG |
1512 | host->pd = pdev; |
1513 | ||
3b0beafc | 1514 | spin_lock_init(&host->lock); |
fdc50a94 YG |
1515 | |
1516 | mmc->ops = &sh_mmcif_ops; | |
7d17baa0 GL |
1517 | sh_mmcif_init_ocr(host); |
1518 | ||
eca889f6 | 1519 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY; |
bf68a812 | 1520 | if (pd && pd->caps) |
fdc50a94 | 1521 | mmc->caps |= pd->caps; |
a782d688 | 1522 | mmc->max_segs = 32; |
fdc50a94 | 1523 | mmc->max_blk_size = 512; |
a782d688 GL |
1524 | mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs; |
1525 | mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; | |
fdc50a94 YG |
1526 | mmc->max_seg_size = mmc->max_req_size; |
1527 | ||
fdc50a94 | 1528 | platform_set_drvdata(pdev, host); |
a782d688 | 1529 | |
60985c39 | 1530 | pm_runtime_enable(dev); |
faca6648 GL |
1531 | host->power = false; |
1532 | ||
6aed678b KM |
1533 | host->clk = devm_clk_get(dev, NULL); |
1534 | if (IS_ERR(host->clk)) { | |
1535 | ret = PTR_ERR(host->clk); | |
60985c39 | 1536 | dev_err(dev, "cannot get clock: %d\n", ret); |
46991005 | 1537 | goto err_pm; |
b289174f | 1538 | } |
9bb09a30 KM |
1539 | |
1540 | ret = clk_prepare_enable(host->clk); | |
a6609267 | 1541 | if (ret < 0) |
46991005 | 1542 | goto err_pm; |
b289174f | 1543 | |
9bb09a30 KM |
1544 | sh_mmcif_clk_setup(host); |
1545 | ||
60985c39 | 1546 | ret = pm_runtime_resume(dev); |
faca6648 | 1547 | if (ret < 0) |
46991005 | 1548 | goto err_clk; |
a782d688 | 1549 | |
1b1a694d | 1550 | INIT_DELAYED_WORK(&host->timeout_work, sh_mmcif_timeout_work); |
fdc50a94 | 1551 | |
b289174f | 1552 | sh_mmcif_sync_reset(host); |
3b0beafc GL |
1553 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
1554 | ||
60985c39 KM |
1555 | name = irq[1] < 0 ? dev_name(dev) : "sh_mmc:error"; |
1556 | ret = devm_request_threaded_irq(dev, irq[0], sh_mmcif_intr, | |
6f4789e6 | 1557 | sh_mmcif_irqt, 0, name, host); |
fdc50a94 | 1558 | if (ret) { |
60985c39 | 1559 | dev_err(dev, "request_irq error (%s)\n", name); |
11a80852 | 1560 | goto err_clk; |
fdc50a94 | 1561 | } |
2cd5b3e0 | 1562 | if (irq[1] >= 0) { |
60985c39 | 1563 | ret = devm_request_threaded_irq(dev, irq[1], |
6f4789e6 BD |
1564 | sh_mmcif_intr, sh_mmcif_irqt, |
1565 | 0, "sh_mmc:int", host); | |
2cd5b3e0 | 1566 | if (ret) { |
60985c39 | 1567 | dev_err(dev, "request_irq error (sh_mmc:int)\n"); |
11a80852 | 1568 | goto err_clk; |
2cd5b3e0 | 1569 | } |
fdc50a94 YG |
1570 | } |
1571 | ||
e480606a | 1572 | if (pd && pd->use_cd_gpio) { |
214fc309 | 1573 | ret = mmc_gpio_request_cd(mmc, pd->cd_gpio, 0); |
e480606a | 1574 | if (ret < 0) |
7f67f3a2 | 1575 | goto err_clk; |
e480606a GL |
1576 | } |
1577 | ||
8047310e GL |
1578 | mutex_init(&host->thread_lock); |
1579 | ||
5ba85d95 GL |
1580 | ret = mmc_add_host(mmc); |
1581 | if (ret < 0) | |
7f67f3a2 | 1582 | goto err_clk; |
fdc50a94 | 1583 | |
60985c39 | 1584 | dev_pm_qos_expose_latency_limit(dev, 100); |
efe6a8ad | 1585 | |
60985c39 | 1586 | dev_info(dev, "Chip version 0x%04x, clock rate %luMHz\n", |
ce7eb688 | 1587 | sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff, |
6aed678b | 1588 | clk_get_rate(host->clk) / 1000000UL); |
ce7eb688 | 1589 | |
6aed678b | 1590 | clk_disable_unprepare(host->clk); |
fdc50a94 YG |
1591 | return ret; |
1592 | ||
46991005 | 1593 | err_clk: |
6aed678b | 1594 | clk_disable_unprepare(host->clk); |
46991005 | 1595 | err_pm: |
60985c39 | 1596 | pm_runtime_disable(dev); |
46991005 | 1597 | err_host: |
fdc50a94 | 1598 | mmc_free_host(mmc); |
fdc50a94 YG |
1599 | return ret; |
1600 | } | |
1601 | ||
6e0ee714 | 1602 | static int sh_mmcif_remove(struct platform_device *pdev) |
fdc50a94 YG |
1603 | { |
1604 | struct sh_mmcif_host *host = platform_get_drvdata(pdev); | |
fdc50a94 | 1605 | |
f985da17 | 1606 | host->dying = true; |
6aed678b | 1607 | clk_prepare_enable(host->clk); |
faca6648 | 1608 | pm_runtime_get_sync(&pdev->dev); |
fdc50a94 | 1609 | |
efe6a8ad RW |
1610 | dev_pm_qos_hide_latency_limit(&pdev->dev); |
1611 | ||
faca6648 | 1612 | mmc_remove_host(host->mmc); |
3b0beafc GL |
1613 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
1614 | ||
f985da17 GL |
1615 | /* |
1616 | * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the | |
1617 | * mmc_remove_host() call above. But swapping order doesn't help either | |
1618 | * (a query on the linux-mmc mailing list didn't bring any replies). | |
1619 | */ | |
1620 | cancel_delayed_work_sync(&host->timeout_work); | |
1621 | ||
6aed678b | 1622 | clk_disable_unprepare(host->clk); |
fdc50a94 | 1623 | mmc_free_host(host->mmc); |
faca6648 GL |
1624 | pm_runtime_put_sync(&pdev->dev); |
1625 | pm_runtime_disable(&pdev->dev); | |
fdc50a94 YG |
1626 | |
1627 | return 0; | |
1628 | } | |
1629 | ||
51129f31 | 1630 | #ifdef CONFIG_PM_SLEEP |
faca6648 GL |
1631 | static int sh_mmcif_suspend(struct device *dev) |
1632 | { | |
b289174f | 1633 | struct sh_mmcif_host *host = dev_get_drvdata(dev); |
faca6648 | 1634 | |
5afc30fc | 1635 | pm_runtime_get_sync(dev); |
cb3ca1ae | 1636 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
5afc30fc | 1637 | pm_runtime_put(dev); |
faca6648 | 1638 | |
cb3ca1ae | 1639 | return 0; |
faca6648 GL |
1640 | } |
1641 | ||
1642 | static int sh_mmcif_resume(struct device *dev) | |
1643 | { | |
cb3ca1ae | 1644 | return 0; |
faca6648 | 1645 | } |
51129f31 | 1646 | #endif |
faca6648 GL |
1647 | |
1648 | static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { | |
51129f31 | 1649 | SET_SYSTEM_SLEEP_PM_OPS(sh_mmcif_suspend, sh_mmcif_resume) |
faca6648 GL |
1650 | }; |
1651 | ||
fdc50a94 YG |
1652 | static struct platform_driver sh_mmcif_driver = { |
1653 | .probe = sh_mmcif_probe, | |
1654 | .remove = sh_mmcif_remove, | |
1655 | .driver = { | |
1656 | .name = DRIVER_NAME, | |
faca6648 | 1657 | .pm = &sh_mmcif_dev_pm_ops, |
1b1a694d | 1658 | .of_match_table = sh_mmcif_of_match, |
fdc50a94 YG |
1659 | }, |
1660 | }; | |
1661 | ||
d1f81a64 | 1662 | module_platform_driver(sh_mmcif_driver); |
fdc50a94 YG |
1663 | |
1664 | MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); | |
1665 | MODULE_LICENSE("GPL"); | |
aa0787a9 | 1666 | MODULE_ALIAS("platform:" DRIVER_NAME); |
fdc50a94 | 1667 | MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); |