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mmc_block: check card state after write
[deliverable/linux.git] / drivers / mmc / host / tifm_sd.c
CommitLineData
4020f2d7
AD		 1/*
2 * tifm_sd.c - TI FlashMedia driver
3 *
4 * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
91f8d011
AD		 10 * Special thanks to Brad Campbell for extensive testing of this driver.
11 *
4020f2d7
AD		 12 */
13
14
15#include <linux/tifm.h>
4020f2d7
AD		 16#include <linux/mmc/host.h>
17#include <linux/highmem.h>
13cdf48e 18#include <linux/scatterlist.h>
019a5f56 19#include <linux/log2.h>
2099c99e 20#include <asm/io.h>
4020f2d7
AD		 21
22#define DRIVER_NAME "tifm_sd"
4552f0cb 23#define DRIVER_VERSION "0.8"
4020f2d7
AD		 24
25static int no_dma = 0;
26static int fixed_timeout = 0;
27module_param(no_dma, bool, 0644);
28module_param(fixed_timeout, bool, 0644);
29
30/* Constants here are mostly from OMAP5912 datasheet */
31#define TIFM_MMCSD_RESET 0x0002
32#define TIFM_MMCSD_CLKMASK 0x03ff
33#define TIFM_MMCSD_POWER 0x0800
34#define TIFM_MMCSD_4BBUS 0x8000
35#define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
36#define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
37#define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
38#define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
39#define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
40#define TIFM_MMCSD_READ 0x8000
41
12c83452 42#define TIFM_MMCSD_ERRMASK 0x01e0 /* set bits: CCRC, CTO, DCRC, DTO */
4020f2d7 43#define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
91f8d011 44#define TIFM_MMCSD_CD 0x0002 /* card detect */
4020f2d7
AD		 45#define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
46#define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
47#define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
48#define TIFM_MMCSD_DTO 0x0020 /* data time-out */
49#define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
50#define TIFM_MMCSD_CTO 0x0080 /* command time-out */
51#define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
52#define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
53#define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
91f8d011
AD		 54#define TIFM_MMCSD_OCRB 0x1000 /* OCR busy */
55#define TIFM_MMCSD_CIRQ 0x2000 /* card irq (cmd40/sdio) */
4020f2d7
AD		 56#define TIFM_MMCSD_CERR 0x4000 /* card status error */
57
0007d483
AD		 58#define TIFM_MMCSD_ODTO 0x0040 /* open drain / extended timeout */
59#define TIFM_MMCSD_CARD_RO 0x0200 /* card is read-only */
60
4020f2d7
AD		 61#define TIFM_MMCSD_FIFO_SIZE 0x0020
62
63#define TIFM_MMCSD_RSP_R0 0x0000
64#define TIFM_MMCSD_RSP_R1 0x0100
65#define TIFM_MMCSD_RSP_R2 0x0200
66#define TIFM_MMCSD_RSP_R3 0x0300
67#define TIFM_MMCSD_RSP_R4 0x0400
68#define TIFM_MMCSD_RSP_R5 0x0500
69#define TIFM_MMCSD_RSP_R6 0x0600
70
71#define TIFM_MMCSD_RSP_BUSY 0x0800
72
73#define TIFM_MMCSD_CMD_BC 0x0000
74#define TIFM_MMCSD_CMD_BCR 0x1000
75#define TIFM_MMCSD_CMD_AC 0x2000
76#define TIFM_MMCSD_CMD_ADTC 0x3000
77
13cdf48e
AD		 78#define TIFM_MMCSD_MAX_BLOCK_SIZE 0x0800UL
79
4020f2d7 80enum {
72dc9d96
AD		 81 CMD_READY = 0x0001,
82 FIFO_READY = 0x0002,
83 BRS_READY = 0x0004,
84 SCMD_ACTIVE = 0x0008,
85 SCMD_READY = 0x0010,
86 CARD_BUSY = 0x0020,
87 DATA_CARRY = 0x0040
0007d483 88};
4020f2d7
AD		 89
90struct tifm_sd {
91f8d011 91 struct tifm_dev *dev;
4020f2d7 92
91f8d011
AD		 93 unsigned short eject:1,
94 open_drain:1,
95 no_dma:1;
96 unsigned short cmd_flags;
72dc9d96 97
91f8d011
AD		 98 unsigned int clk_freq;
99 unsigned int clk_div;
100 unsigned long timeout_jiffies;
4020f2d7 101
8e02f858 102 struct tasklet_struct finish_tasklet;
0803dd0c 103 struct timer_list timer;
4020f2d7 104 struct mmc_request *req;
4020f2d7 105
13cdf48e
AD		 106 int sg_len;
107 int sg_pos;
108 unsigned int block_pos;
109 struct scatterlist bounce_buf;
110 unsigned char bounce_buf_data[TIFM_MMCSD_MAX_BLOCK_SIZE];
4020f2d7
AD		 111};
112
13cdf48e
AD		 113/* for some reason, host won't respond correctly to readw/writew */
114static void tifm_sd_read_fifo(struct tifm_sd *host, struct page *pg,
115 unsigned int off, unsigned int cnt)
255ef22e 116{
13cdf48e
AD		 117 struct tifm_dev *sock = host->dev;
118 unsigned char *buf;
119 unsigned int pos = 0, val;
120
121 buf = kmap_atomic(pg, KM_BIO_DST_IRQ) + off;
122 if (host->cmd_flags & DATA_CARRY) {
123 buf[pos++] = host->bounce_buf_data[0];
124 host->cmd_flags &= ~DATA_CARRY;
125 }
126
127 while (pos < cnt) {
128 val = readl(sock->addr + SOCK_MMCSD_DATA);
129 buf[pos++] = val & 0xff;
130 if (pos == cnt) {
131 host->bounce_buf_data[0] = (val >> 8) & 0xff;
132 host->cmd_flags |= DATA_CARRY;
133 break;
134 }
135 buf[pos++] = (val >> 8) & 0xff;
136 }
137 kunmap_atomic(buf - off, KM_BIO_DST_IRQ);
255ef22e
AD		 138}
139
13cdf48e
AD		 140static void tifm_sd_write_fifo(struct tifm_sd *host, struct page *pg,
141 unsigned int off, unsigned int cnt)
4020f2d7 142{
13cdf48e
AD		 143 struct tifm_dev *sock = host->dev;
144 unsigned char *buf;
145 unsigned int pos = 0, val;
146
147 buf = kmap_atomic(pg, KM_BIO_SRC_IRQ) + off;
148 if (host->cmd_flags & DATA_CARRY) {
149 val = host->bounce_buf_data[0] | ((buf[pos++] << 8) & 0xff00);
150 writel(val, sock->addr + SOCK_MMCSD_DATA);
151 host->cmd_flags &= ~DATA_CARRY;
152 }
153
154 while (pos < cnt) {
155 val = buf[pos++];
156 if (pos == cnt) {
157 host->bounce_buf_data[0] = val & 0xff;
158 host->cmd_flags |= DATA_CARRY;
159 break;
4020f2d7 160 }
13cdf48e
AD		 161 val |= (buf[pos++] << 8) & 0xff00;
162 writel(val, sock->addr + SOCK_MMCSD_DATA);
163 }
164 kunmap_atomic(buf - off, KM_BIO_SRC_IRQ);
165}
166
167static void tifm_sd_transfer_data(struct tifm_sd *host)
168{
169 struct mmc_data *r_data = host->req->cmd->data;
170 struct scatterlist *sg = r_data->sg;
171 unsigned int off, cnt, t_size = TIFM_MMCSD_FIFO_SIZE * 2;
172 unsigned int p_off, p_cnt;
173 struct page *pg;
174
175 if (host->sg_pos == host->sg_len)
176 return;
177 while (t_size) {
178 cnt = sg[host->sg_pos].length - host->block_pos;
179 if (!cnt) {
180 host->block_pos = 0;
181 host->sg_pos++;
182 if (host->sg_pos == host->sg_len) {
183 if ((r_data->flags & MMC_DATA_WRITE)
184 && DATA_CARRY)
185 writel(host->bounce_buf_data[0],
186 host->dev->addr
187 + SOCK_MMCSD_DATA);
188
189 return;
4020f2d7 190 }
13cdf48e 191 cnt = sg[host->sg_pos].length;
4020f2d7 192 }
13cdf48e
AD		 193 off = sg[host->sg_pos].offset + host->block_pos;
194
45711f1a 195 pg = nth_page(sg_page(&sg[host->sg_pos]), off >> PAGE_SHIFT);
13cdf48e
AD		 196 p_off = offset_in_page(off);
197 p_cnt = PAGE_SIZE - p_off;
198 p_cnt = min(p_cnt, cnt);
199 p_cnt = min(p_cnt, t_size);
200
201 if (r_data->flags & MMC_DATA_READ)
202 tifm_sd_read_fifo(host, pg, p_off, p_cnt);
203 else if (r_data->flags & MMC_DATA_WRITE)
204 tifm_sd_write_fifo(host, pg, p_off, p_cnt);
205
206 t_size -= p_cnt;
207 host->block_pos += p_cnt;
4020f2d7 208 }
13cdf48e
AD		 209}
210
211static void tifm_sd_copy_page(struct page *dst, unsigned int dst_off,
212 struct page *src, unsigned int src_off,
213 unsigned int count)
214{
215 unsigned char *src_buf = kmap_atomic(src, KM_BIO_SRC_IRQ) + src_off;
216 unsigned char *dst_buf = kmap_atomic(dst, KM_BIO_DST_IRQ) + dst_off;
217
218 memcpy(dst_buf, src_buf, count);
219
220 kunmap_atomic(dst_buf - dst_off, KM_BIO_DST_IRQ);
221 kunmap_atomic(src_buf - src_off, KM_BIO_SRC_IRQ);
222}
223
224static void tifm_sd_bounce_block(struct tifm_sd *host, struct mmc_data *r_data)
225{
226 struct scatterlist *sg = r_data->sg;
227 unsigned int t_size = r_data->blksz;
228 unsigned int off, cnt;
229 unsigned int p_off, p_cnt;
230 struct page *pg;
231
232 dev_dbg(&host->dev->dev, "bouncing block\n");
233 while (t_size) {
234 cnt = sg[host->sg_pos].length - host->block_pos;
235 if (!cnt) {
236 host->block_pos = 0;
237 host->sg_pos++;
238 if (host->sg_pos == host->sg_len)
239 return;
240 cnt = sg[host->sg_pos].length;
241 }
242 off = sg[host->sg_pos].offset + host->block_pos;
243
45711f1a 244 pg = nth_page(sg_page(&sg[host->sg_pos]), off >> PAGE_SHIFT);
13cdf48e
AD		 245 p_off = offset_in_page(off);
246 p_cnt = PAGE_SIZE - p_off;
247 p_cnt = min(p_cnt, cnt);
248 p_cnt = min(p_cnt, t_size);
249
250 if (r_data->flags & MMC_DATA_WRITE)
45711f1a 251 tifm_sd_copy_page(sg_page(&host->bounce_buf),
13cdf48e
AD		 252 r_data->blksz - t_size,
253 pg, p_off, p_cnt);
254 else if (r_data->flags & MMC_DATA_READ)
45711f1a 255 tifm_sd_copy_page(pg, p_off, sg_page(&host->bounce_buf),
13cdf48e
AD		 256 r_data->blksz - t_size, p_cnt);
257
258 t_size -= p_cnt;
259 host->block_pos += p_cnt;
260 }
261}
262
d97956f8 263static int tifm_sd_set_dma_data(struct tifm_sd *host, struct mmc_data *r_data)
13cdf48e
AD		 264{
265 struct tifm_dev *sock = host->dev;
266 unsigned int t_size = TIFM_DMA_TSIZE * r_data->blksz;
267 unsigned int dma_len, dma_blk_cnt, dma_off;
268 struct scatterlist *sg = NULL;
269 unsigned long flags;
270
271 if (host->sg_pos == host->sg_len)
272 return 1;
273
274 if (host->cmd_flags & DATA_CARRY) {
275 host->cmd_flags &= ~DATA_CARRY;
276 local_irq_save(flags);
277 tifm_sd_bounce_block(host, r_data);
278 local_irq_restore(flags);
279 if (host->sg_pos == host->sg_len)
280 return 1;
281 }
282
283 dma_len = sg_dma_len(&r_data->sg[host->sg_pos]) - host->block_pos;
284 if (!dma_len) {
285 host->block_pos = 0;
286 host->sg_pos++;
287 if (host->sg_pos == host->sg_len)
288 return 1;
289 dma_len = sg_dma_len(&r_data->sg[host->sg_pos]);
290 }
291
292 if (dma_len < t_size) {
293 dma_blk_cnt = dma_len / r_data->blksz;
294 dma_off = host->block_pos;
295 host->block_pos += dma_blk_cnt * r_data->blksz;
296 } else {
297 dma_blk_cnt = TIFM_DMA_TSIZE;
298 dma_off = host->block_pos;
299 host->block_pos += t_size;
300 }
301
302 if (dma_blk_cnt)
303 sg = &r_data->sg[host->sg_pos];
304 else if (dma_len) {
305 if (r_data->flags & MMC_DATA_WRITE) {
306 local_irq_save(flags);
307 tifm_sd_bounce_block(host, r_data);
308 local_irq_restore(flags);
309 } else
310 host->cmd_flags |= DATA_CARRY;
311
312 sg = &host->bounce_buf;
313 dma_off = 0;
314 dma_blk_cnt = 1;
315 } else
316 return 1;
317
318 dev_dbg(&sock->dev, "setting dma for %d blocks\n", dma_blk_cnt);
319 writel(sg_dma_address(sg) + dma_off, sock->addr + SOCK_DMA_ADDRESS);
320 if (r_data->flags & MMC_DATA_WRITE)
321 writel((dma_blk_cnt << 8) | TIFM_DMA_TX | TIFM_DMA_EN,
322 sock->addr + SOCK_DMA_CONTROL);
323 else
324 writel((dma_blk_cnt << 8) | TIFM_DMA_EN,
325 sock->addr + SOCK_DMA_CONTROL);
326
4020f2d7
AD		 327 return 0;
328}
329
330static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
331{
332 unsigned int rc = 0;
333
334 switch (mmc_resp_type(cmd)) {
335 case MMC_RSP_NONE:
336 rc |= TIFM_MMCSD_RSP_R0;
337 break;
338 case MMC_RSP_R1B:
339 rc |= TIFM_MMCSD_RSP_BUSY; // deliberate fall-through
340 case MMC_RSP_R1:
341 rc |= TIFM_MMCSD_RSP_R1;
342 break;
343 case MMC_RSP_R2:
344 rc |= TIFM_MMCSD_RSP_R2;
345 break;
346 case MMC_RSP_R3:
347 rc |= TIFM_MMCSD_RSP_R3;
348 break;
4020f2d7
AD		 349 default:
350 BUG();
351 }
352
353 switch (mmc_cmd_type(cmd)) {
354 case MMC_CMD_BC:
355 rc |= TIFM_MMCSD_CMD_BC;
356 break;
357 case MMC_CMD_BCR:
358 rc |= TIFM_MMCSD_CMD_BCR;
359 break;
360 case MMC_CMD_AC:
361 rc |= TIFM_MMCSD_CMD_AC;
362 break;
363 case MMC_CMD_ADTC:
364 rc |= TIFM_MMCSD_CMD_ADTC;
365 break;
366 default:
367 BUG();
368 }
369 return rc;
370}
371
372static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
373{
374 struct tifm_dev *sock = host->dev;
0007d483
AD		 375 unsigned int cmd_mask = tifm_sd_op_flags(cmd);
376
377 if (host->open_drain)
378 cmd_mask |= TIFM_MMCSD_ODTO;
4020f2d7
AD		 379
380 if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
381 cmd_mask |= TIFM_MMCSD_READ;
382
383 dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
2e8ce5e7 384 cmd->opcode, cmd->arg, cmd_mask);
4020f2d7
AD		 385
386 writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
387 writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
388 writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
389}
390
391static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
392{
393 cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
394 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
395 cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
396 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
397 cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
398 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
399 cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
400 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
401}
402
72dc9d96 403static void tifm_sd_check_status(struct tifm_sd *host)
4020f2d7 404{
72dc9d96 405 struct tifm_dev *sock = host->dev;
4020f2d7
AD		 406 struct mmc_command *cmd = host->req->cmd;
407
17b0429d 408 if (cmd->error)
72dc9d96
AD		 409 goto finish_request;
410
411 if (!(host->cmd_flags & CMD_READY))
4020f2d7 412 return;
72dc9d96
AD		 413
414 if (cmd->data) {
17b0429d 415 if (cmd->data->error) {
72dc9d96
AD		 416 if ((host->cmd_flags & SCMD_ACTIVE)
417 && !(host->cmd_flags & SCMD_READY))
418 return;
419
420 goto finish_request;
4020f2d7 421 }
72dc9d96
AD		 422
423 if (!(host->cmd_flags & BRS_READY))
424 return;
425
426 if (!(host->no_dma || (host->cmd_flags & FIFO_READY)))
427 return;
428
429 if (cmd->data->flags & MMC_DATA_WRITE) {
430 if (host->req->stop) {
431 if (!(host->cmd_flags & SCMD_ACTIVE)) {
432 host->cmd_flags |= SCMD_ACTIVE;
433 writel(TIFM_MMCSD_EOFB
434 | readl(sock->addr
435 + SOCK_MMCSD_INT_ENABLE),
436 sock->addr
437 + SOCK_MMCSD_INT_ENABLE);
1289335a 438 tifm_sd_exec(host, host->req->stop);
72dc9d96 439 return;
1289335a 440 } else {
72dc9d96
AD		 441 if (!(host->cmd_flags & SCMD_READY)
442 || (host->cmd_flags & CARD_BUSY))
443 return;
444 writel((~TIFM_MMCSD_EOFB)
445 & readl(sock->addr
446 + SOCK_MMCSD_INT_ENABLE),
447 sock->addr
448 + SOCK_MMCSD_INT_ENABLE);
1289335a
AD		 449 }
450 } else {
72dc9d96
AD		 451 if (host->cmd_flags & CARD_BUSY)
452 return;
453 writel((~TIFM_MMCSD_EOFB)
454 & readl(sock->addr
455 + SOCK_MMCSD_INT_ENABLE),
456 sock->addr + SOCK_MMCSD_INT_ENABLE);
1289335a 457 }
72dc9d96 458 } else {
1289335a 459 if (host->req->stop) {
72dc9d96
AD		 460 if (!(host->cmd_flags & SCMD_ACTIVE)) {
461 host->cmd_flags |= SCMD_ACTIVE;
462 tifm_sd_exec(host, host->req->stop);
463 return;
464 } else {
465 if (!(host->cmd_flags & SCMD_READY))
466 return;
467 }
1289335a 468 }
4020f2d7 469 }
4020f2d7 470 }
72dc9d96
AD		 471finish_request:
472 tasklet_schedule(&host->finish_tasklet);
4020f2d7
AD		 473}
474
475/* Called from interrupt handler */
4552f0cb 476static void tifm_sd_data_event(struct tifm_dev *sock)
4020f2d7
AD		 477{
478 struct tifm_sd *host;
4552f0cb 479 unsigned int fifo_status = 0;
72dc9d96 480 struct mmc_data *r_data = NULL;
4020f2d7
AD		 481
482 spin_lock(&sock->lock);
483 host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
4552f0cb 484 fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
72dc9d96
AD		 485 dev_dbg(&sock->dev, "data event: fifo_status %x, flags %x\n",
486 fifo_status, host->cmd_flags);
4552f0cb 487
72dc9d96
AD		 488 if (host->req) {
489 r_data = host->req->cmd->data;
4552f0cb 490
72dc9d96 491 if (r_data && (fifo_status & TIFM_FIFO_READY)) {
13cdf48e
AD		 492 if (tifm_sd_set_dma_data(host, r_data)) {
493 host->cmd_flags |= FIFO_READY;
494 tifm_sd_check_status(host);
495 }
72dc9d96
AD		 496 }
497 }
4552f0cb 498
72dc9d96 499 writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
4552f0cb 500 spin_unlock(&sock->lock);
4552f0cb
AD		 501}
502
503/* Called from interrupt handler */
504static void tifm_sd_card_event(struct tifm_dev *sock)
505{
506 struct tifm_sd *host;
507 unsigned int host_status = 0;
17b0429d 508 int cmd_error = 0;
72dc9d96
AD		 509 struct mmc_command *cmd = NULL;
510 unsigned long flags;
4552f0cb
AD		 511
512 spin_lock(&sock->lock);
513 host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
72dc9d96
AD		 514 host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
515 dev_dbg(&sock->dev, "host event: host_status %x, flags %x\n",
516 host_status, host->cmd_flags);
4020f2d7 517
72dc9d96
AD		 518 if (host->req) {
519 cmd = host->req->cmd;
4020f2d7
AD		 520
521 if (host_status & TIFM_MMCSD_ERRMASK) {
72dc9d96
AD		 522 writel(host_status & TIFM_MMCSD_ERRMASK,
523 sock->addr + SOCK_MMCSD_STATUS);
524 if (host_status & TIFM_MMCSD_CTO)
17b0429d 525 cmd_error = -ETIMEDOUT;
72dc9d96 526 else if (host_status & TIFM_MMCSD_CCRC)
17b0429d 527 cmd_error = -EILSEQ;
72dc9d96
AD		 528
529 if (cmd->data) {
530 if (host_status & TIFM_MMCSD_DTO)
17b0429d 531 cmd->data->error = -ETIMEDOUT;
72dc9d96 532 else if (host_status & TIFM_MMCSD_DCRC)
17b0429d 533 cmd->data->error = -EILSEQ;
72dc9d96 534 }
4020f2d7
AD		 535
536 writel(TIFM_FIFO_INT_SETALL,
537 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
538 writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
539
540 if (host->req->stop) {
72dc9d96
AD		 541 if (host->cmd_flags & SCMD_ACTIVE) {
542 host->req->stop->error = cmd_error;
543 host->cmd_flags |= SCMD_READY;
544 } else {
545 cmd->error = cmd_error;
546 host->cmd_flags |= SCMD_ACTIVE;
4020f2d7 547 tifm_sd_exec(host, host->req->stop);
4020f2d7 548 goto done;
4020f2d7 549 }
72dc9d96
AD		 550 } else
551 cmd->error = cmd_error;
552 } else {
553 if (host_status & (TIFM_MMCSD_EOC | TIFM_MMCSD_CERR)) {
554 if (!(host->cmd_flags & CMD_READY)) {
555 host->cmd_flags |= CMD_READY;
556 tifm_sd_fetch_resp(cmd, sock);
557 } else if (host->cmd_flags & SCMD_ACTIVE) {
558 host->cmd_flags |= SCMD_READY;
559 tifm_sd_fetch_resp(host->req->stop,
560 sock);
561 }
4020f2d7 562 }
72dc9d96
AD		 563 if (host_status & TIFM_MMCSD_BRS)
564 host->cmd_flags |= BRS_READY;
4020f2d7
AD		 565 }
566
72dc9d96
AD		 567 if (host->no_dma && cmd->data) {
568 if (host_status & TIFM_MMCSD_AE)
569 writel(host_status & TIFM_MMCSD_AE,
570 sock->addr + SOCK_MMCSD_STATUS);
571
572 if (host_status & (TIFM_MMCSD_AE | TIFM_MMCSD_AF
573 | TIFM_MMCSD_BRS)) {
574 local_irq_save(flags);
13cdf48e 575 tifm_sd_transfer_data(host);
72dc9d96
AD		 576 local_irq_restore(flags);
577 host_status &= ~TIFM_MMCSD_AE;
578 }
4020f2d7 579 }
4020f2d7 580
72dc9d96
AD		 581 if (host_status & TIFM_MMCSD_EOFB)
582 host->cmd_flags &= ~CARD_BUSY;
583 else if (host_status & TIFM_MMCSD_CB)
584 host->cmd_flags |= CARD_BUSY;
585
586 tifm_sd_check_status(host);
587 }
4020f2d7 588done:
72dc9d96 589 writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
4020f2d7 590 spin_unlock(&sock->lock);
4020f2d7
AD		 591}
592
4020f2d7 593static void tifm_sd_set_data_timeout(struct tifm_sd *host,
2e8ce5e7 594 struct mmc_data *data)
4020f2d7
AD		 595{
596 struct tifm_dev *sock = host->dev;
597 unsigned int data_timeout = data->timeout_clks;
598
599 if (fixed_timeout)
600 return;
601
602 data_timeout += data->timeout_ns /
83d420ba 603 ((1000000000UL / host->clk_freq) * host->clk_div);
4020f2d7
AD		 604
605 if (data_timeout < 0xffff) {
4020f2d7 606 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
83d420ba
AD		 607 writel((~TIFM_MMCSD_DPE)
608 & readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
609 sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
4020f2d7 610 } else {
4020f2d7 611 data_timeout = (data_timeout >> 10) + 1;
2e8ce5e7 612 if (data_timeout > 0xffff)
4020f2d7
AD		 613 data_timeout = 0; /* set to unlimited */
614 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
83d420ba
AD		 615 writel(TIFM_MMCSD_DPE
616 | readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
617 sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
4020f2d7
AD		 618 }
619}
620
621static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
622{
623 struct tifm_sd *host = mmc_priv(mmc);
624 struct tifm_dev *sock = host->dev;
625 unsigned long flags;
4020f2d7
AD		 626 struct mmc_data *r_data = mrq->cmd->data;
627
628 spin_lock_irqsave(&sock->lock, flags);
0007d483 629 if (host->eject) {
255d01af 630 mrq->cmd->error = -ENOMEDIUM;
4020f2d7
AD		 631 goto err_out;
632 }
633
634 if (host->req) {
91f8d011
AD		 635 printk(KERN_ERR "%s : unfinished request detected\n",
636 sock->dev.bus_id);
255d01af
PO		 637 mrq->cmd->error = -ETIMEDOUT;
638 goto err_out;
639 }
640
019a5f56 641 if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
255d01af
PO		 642 printk(KERN_ERR "%s: Unsupported block size (%d bytes)\n",
643 sock->dev.bus_id, mrq->data->blksz);
644 mrq->cmd->error = -EINVAL;
4020f2d7
AD		 645 goto err_out;
646 }
647
13cdf48e
AD		 648 host->cmd_flags = 0;
649 host->block_pos = 0;
650 host->sg_pos = 0;
651
4020f2d7
AD		 652 if (r_data) {
653 tifm_sd_set_data_timeout(host, r_data);
654
13cdf48e
AD		 655 if ((r_data->flags & MMC_DATA_WRITE) && !mrq->stop)
656 writel(TIFM_MMCSD_EOFB
657 | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
658 sock->addr + SOCK_MMCSD_INT_ENABLE);
dfef26d9 659
13cdf48e 660 if (host->no_dma) {
dfef26d9
AD		 661 writel(TIFM_MMCSD_BUFINT
662 | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
663 sock->addr + SOCK_MMCSD_INT_ENABLE);
664 writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8)
665 | (TIFM_MMCSD_FIFO_SIZE - 1),
666 sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
667
13cdf48e 668 host->sg_len = r_data->sg_len;
dfef26d9 669 } else {
13cdf48e
AD		 670 sg_init_one(&host->bounce_buf, host->bounce_buf_data,
671 r_data->blksz);
672
673 if(1 != tifm_map_sg(sock, &host->bounce_buf, 1,
674 r_data->flags & MMC_DATA_WRITE
675 ? PCI_DMA_TODEVICE
676 : PCI_DMA_FROMDEVICE)) {
677 printk(KERN_ERR "%s : scatterlist map failed\n",
678 sock->dev.bus_id);
679 spin_unlock_irqrestore(&sock->lock, flags);
680 goto err_out;
681 }
682 host->sg_len = tifm_map_sg(sock, r_data->sg,
683 r_data->sg_len,
684 r_data->flags
685 & MMC_DATA_WRITE
686 ? PCI_DMA_TODEVICE
687 : PCI_DMA_FROMDEVICE);
688 if (host->sg_len < 1) {
689 printk(KERN_ERR "%s : scatterlist map failed\n",
690 sock->dev.bus_id);
691 tifm_unmap_sg(sock, &host->bounce_buf, 1,
692 r_data->flags & MMC_DATA_WRITE
693 ? PCI_DMA_TODEVICE
694 : PCI_DMA_FROMDEVICE);
dfef26d9
AD		 695 spin_unlock_irqrestore(&sock->lock, flags);
696 goto err_out;
697 }
4020f2d7 698
13cdf48e
AD		 699 writel(TIFM_FIFO_INT_SETALL,
700 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
701 writel(ilog2(r_data->blksz) - 2,
702 sock->addr + SOCK_FIFO_PAGE_SIZE);
703 writel(TIFM_FIFO_ENABLE,
704 sock->addr + SOCK_FIFO_CONTROL);
705 writel(TIFM_FIFO_INTMASK,
706 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
707
708 if (r_data->flags & MMC_DATA_WRITE)
709 writel(TIFM_MMCSD_TXDE,
710 sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
711 else
712 writel(TIFM_MMCSD_RXDE,
713 sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
714
715 tifm_sd_set_dma_data(host, r_data);
dfef26d9 716 }
13cdf48e
AD		 717
718 writel(r_data->blocks - 1,
719 sock->addr + SOCK_MMCSD_NUM_BLOCKS);
720 writel(r_data->blksz - 1,
721 sock->addr + SOCK_MMCSD_BLOCK_LEN);
4020f2d7
AD		 722 }
723
724 host->req = mrq;
0803dd0c 725 mod_timer(&host->timer, jiffies + host->timeout_jiffies);
4020f2d7 726 writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
2e8ce5e7 727 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 728 tifm_sd_exec(host, mrq->cmd);
729 spin_unlock_irqrestore(&sock->lock, flags);
730 return;
731
732err_out:
255d01af 733 spin_unlock_irqrestore(&sock->lock, flags);
4020f2d7
AD		 734 mmc_request_done(mmc, mrq);
735}
736
8e02f858 737static void tifm_sd_end_cmd(unsigned long data)
4020f2d7 738{
8e02f858 739 struct tifm_sd *host = (struct tifm_sd*)data;
4020f2d7
AD		 740 struct tifm_dev *sock = host->dev;
741 struct mmc_host *mmc = tifm_get_drvdata(sock);
742 struct mmc_request *mrq;
e069d79d 743 struct mmc_data *r_data = NULL;
4020f2d7
AD		 744 unsigned long flags;
745
746 spin_lock_irqsave(&sock->lock, flags);
747
0803dd0c 748 del_timer(&host->timer);
4020f2d7 749 mrq = host->req;
e069d79d 750 host->req = NULL;
4020f2d7
AD		 751
752 if (!mrq) {
91f8d011
AD		 753 printk(KERN_ERR " %s : no request to complete?\n",
754 sock->dev.bus_id);
4020f2d7
AD		 755 spin_unlock_irqrestore(&sock->lock, flags);
756 return;
757 }
758
759 r_data = mrq->cmd->data;
760 if (r_data) {
dfef26d9 761 if (host->no_dma) {
13cdf48e
AD		 762 writel((~TIFM_MMCSD_BUFINT)
763 & readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
764 sock->addr + SOCK_MMCSD_INT_ENABLE);
4020f2d7 765 } else {
13cdf48e
AD		 766 tifm_unmap_sg(sock, &host->bounce_buf, 1,
767 (r_data->flags & MMC_DATA_WRITE)
768 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
dfef26d9
AD		 769 tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
770 (r_data->flags & MMC_DATA_WRITE)
771 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
4020f2d7 772 }
13cdf48e
AD		 773
774 r_data->bytes_xfered = r_data->blocks
775 - readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
776 r_data->bytes_xfered *= r_data->blksz;
777 r_data->bytes_xfered += r_data->blksz
778 - readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
4020f2d7
AD		 779 }
780
781 writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
2e8ce5e7 782 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 783
784 spin_unlock_irqrestore(&sock->lock, flags);
4020f2d7
AD		 785 mmc_request_done(mmc, mrq);
786}
787
0803dd0c 788static void tifm_sd_abort(unsigned long data)
4020f2d7 789{
8e02f858
AD		 790 struct tifm_sd *host = (struct tifm_sd*)data;
791
91f8d011
AD		 792 printk(KERN_ERR
793 "%s : card failed to respond for a long period of time "
794 "(%x, %x)\n",
795 host->dev->dev.bus_id, host->req->cmd->opcode, host->cmd_flags);
8e02f858 796
8e02f858 797 tifm_eject(host->dev);
4020f2d7
AD		 798}
799
800static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
801{
802 struct tifm_sd *host = mmc_priv(mmc);
803 struct tifm_dev *sock = host->dev;
804 unsigned int clk_div1, clk_div2;
805 unsigned long flags;
806
807 spin_lock_irqsave(&sock->lock, flags);
808
91f8d011
AD		 809 dev_dbg(&sock->dev, "ios: clock = %u, vdd = %x, bus_mode = %x, "
810 "chip_select = %x, power_mode = %x, bus_width = %x\n",
811 ios->clock, ios->vdd, ios->bus_mode, ios->chip_select,
812 ios->power_mode, ios->bus_width);
813
4020f2d7
AD		 814 if (ios->bus_width == MMC_BUS_WIDTH_4) {
815 writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
816 sock->addr + SOCK_MMCSD_CONFIG);
817 } else {
2e8ce5e7
AD		 818 writel((~TIFM_MMCSD_4BBUS)
819 & readl(sock->addr + SOCK_MMCSD_CONFIG),
820 sock->addr + SOCK_MMCSD_CONFIG);
4020f2d7
AD		 821 }
822
823 if (ios->clock) {
824 clk_div1 = 20000000 / ios->clock;
825 if (!clk_div1)
826 clk_div1 = 1;
827
828 clk_div2 = 24000000 / ios->clock;
829 if (!clk_div2)
830 clk_div2 = 1;
831
832 if ((20000000 / clk_div1) > ios->clock)
833 clk_div1++;
834 if ((24000000 / clk_div2) > ios->clock)
835 clk_div2++;
836 if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
837 host->clk_freq = 20000000;
838 host->clk_div = clk_div1;
2e8ce5e7
AD		 839 writel((~TIFM_CTRL_FAST_CLK)
840 & readl(sock->addr + SOCK_CONTROL),
841 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 842 } else {
843 host->clk_freq = 24000000;
844 host->clk_div = clk_div2;
2e8ce5e7
AD		 845 writel(TIFM_CTRL_FAST_CLK
846 | readl(sock->addr + SOCK_CONTROL),
847 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 848 }
849 } else {
850 host->clk_div = 0;
851 }
852 host->clk_div &= TIFM_MMCSD_CLKMASK;
2e8ce5e7
AD		 853 writel(host->clk_div
854 | ((~TIFM_MMCSD_CLKMASK)
855 & readl(sock->addr + SOCK_MMCSD_CONFIG)),
856 sock->addr + SOCK_MMCSD_CONFIG);
4020f2d7 857
0007d483 858 host->open_drain = (ios->bus_mode == MMC_BUSMODE_OPENDRAIN);
4020f2d7
AD		 859
860 /* chip_select : maybe later */
861 //vdd
862 //power is set before probe / after remove
4020f2d7
AD		 863
864 spin_unlock_irqrestore(&sock->lock, flags);
865}
866
867static int tifm_sd_ro(struct mmc_host *mmc)
868{
0007d483 869 int rc = 0;
4020f2d7
AD		 870 struct tifm_sd *host = mmc_priv(mmc);
871 struct tifm_dev *sock = host->dev;
872 unsigned long flags;
873
874 spin_lock_irqsave(&sock->lock, flags);
0007d483
AD		 875 if (TIFM_MMCSD_CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE))
876 rc = 1;
4020f2d7
AD		 877 spin_unlock_irqrestore(&sock->lock, flags);
878 return rc;
879}
880
dfef26d9 881static const struct mmc_host_ops tifm_sd_ops = {
4020f2d7
AD		 882 .request = tifm_sd_request,
883 .set_ios = tifm_sd_ios,
884 .get_ro = tifm_sd_ro
885};
886
8e02f858 887static int tifm_sd_initialize_host(struct tifm_sd *host)
4020f2d7 888{
8e02f858
AD		 889 int rc;
890 unsigned int host_status = 0;
4020f2d7 891 struct tifm_dev *sock = host->dev;
4020f2d7 892
8e02f858
AD		 893 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
894 mmiowb();
895 host->clk_div = 61;
896 host->clk_freq = 20000000;
897 writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
898 writel(host->clk_div | TIFM_MMCSD_POWER,
899 sock->addr + SOCK_MMCSD_CONFIG);
900
901 /* wait up to 0.51 sec for reset */
5897d657 902 for (rc = 32; rc <= 256; rc <<= 1) {
8e02f858
AD		 903 if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
904 rc = 0;
905 break;
906 }
907 msleep(rc);
908 }
909
910 if (rc) {
5897d657
AD		 911 printk(KERN_ERR "%s : controller failed to reset\n",
912 sock->dev.bus_id);
8e02f858
AD		 913 return -ENODEV;
914 }
915
916 writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
917 writel(host->clk_div | TIFM_MMCSD_POWER,
918 sock->addr + SOCK_MMCSD_CONFIG);
919 writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
920
921 // command timeout fixed to 64 clocks for now
922 writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO);
923 writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
924
5897d657 925 for (rc = 16; rc <= 64; rc <<= 1) {
8e02f858
AD		 926 host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
927 writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
928 if (!(host_status & TIFM_MMCSD_ERRMASK)
929 && (host_status & TIFM_MMCSD_EOC)) {
930 rc = 0;
931 break;
932 }
933 msleep(rc);
934 }
935
936 if (rc) {
5897d657
AD		 937 printk(KERN_ERR
938 "%s : card not ready - probe failed on initialization\n",
939 sock->dev.bus_id);
8e02f858
AD		 940 return -ENODEV;
941 }
942
5897d657
AD		 943 writel(TIFM_MMCSD_CERR | TIFM_MMCSD_BRS | TIFM_MMCSD_EOC
944 | TIFM_MMCSD_ERRMASK,
8e02f858
AD		 945 sock->addr + SOCK_MMCSD_INT_ENABLE);
946 mmiowb();
947
948 return 0;
4020f2d7
AD		 949}
950
951static int tifm_sd_probe(struct tifm_dev *sock)
952{
953 struct mmc_host *mmc;
954 struct tifm_sd *host;
955 int rc = -EIO;
956
2e8ce5e7
AD		 957 if (!(TIFM_SOCK_STATE_OCCUPIED
958 & readl(sock->addr + SOCK_PRESENT_STATE))) {
91f8d011
AD		 959 printk(KERN_WARNING "%s : card gone, unexpectedly\n",
960 sock->dev.bus_id);
4020f2d7
AD		 961 return rc;
962 }
963
964 mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
965 if (!mmc)
966 return -ENOMEM;
967
968 host = mmc_priv(mmc);
0007d483 969 host->no_dma = no_dma;
4020f2d7 970 tifm_set_drvdata(sock, mmc);
8e02f858 971 host->dev = sock;
4020f2d7
AD		 972 host->timeout_jiffies = msecs_to_jiffies(1000);
973
dfef26d9 974 tasklet_init(&host->finish_tasklet, tifm_sd_end_cmd,
8e02f858
AD		 975 (unsigned long)host);
976 setup_timer(&host->timer, tifm_sd_abort, (unsigned long)host);
977
4020f2d7
AD		 978 mmc->ops = &tifm_sd_ops;
979 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
8e02f858 980 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE;
4020f2d7
AD		 981 mmc->f_min = 20000000 / 60;
982 mmc->f_max = 24000000;
13cdf48e
AD		 983
984 mmc->max_blk_count = 2048;
985 mmc->max_hw_segs = mmc->max_blk_count;
986 mmc->max_blk_size = min(TIFM_MMCSD_MAX_BLOCK_SIZE, PAGE_SIZE);
987 mmc->max_seg_size = mmc->max_blk_count * mmc->max_blk_size;
988 mmc->max_req_size = mmc->max_seg_size;
989 mmc->max_phys_segs = mmc->max_hw_segs;
990
4552f0cb
AD		 991 sock->card_event = tifm_sd_card_event;
992 sock->data_event = tifm_sd_data_event;
8e02f858 993 rc = tifm_sd_initialize_host(host);
4020f2d7 994
8e02f858
AD		 995 if (!rc)
996 rc = mmc_add_host(mmc);
91f8d011
AD		 997 if (!rc)
998 return 0;
4020f2d7 999
8e02f858 1000 mmc_free_host(mmc);
4020f2d7
AD		 1001 return rc;
1002}
1003
1004static void tifm_sd_remove(struct tifm_dev *sock)
1005{
1006 struct mmc_host *mmc = tifm_get_drvdata(sock);
1007 struct tifm_sd *host = mmc_priv(mmc);
b039d4a1 1008 unsigned long flags;
4020f2d7 1009
592d372a 1010 spin_lock_irqsave(&sock->lock, flags);
0007d483 1011 host->eject = 1;
b039d4a1
AD		 1012 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
1013 mmiowb();
592d372a
AD		 1014 spin_unlock_irqrestore(&sock->lock, flags);
1015
1016 tasklet_kill(&host->finish_tasklet);
1017
b039d4a1 1018 spin_lock_irqsave(&sock->lock, flags);
b039d4a1
AD		 1019 if (host->req) {
1020 writel(TIFM_FIFO_INT_SETALL,
1021 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
1022 writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
17b0429d 1023 host->req->cmd->error = -ENOMEDIUM;
592d372a 1024 if (host->req->stop)
17b0429d 1025 host->req->stop->error = -ENOMEDIUM;
b039d4a1
AD		 1026 tasklet_schedule(&host->finish_tasklet);
1027 }
1028 spin_unlock_irqrestore(&sock->lock, flags);
8e02f858 1029 mmc_remove_host(mmc);
592d372a 1030 dev_dbg(&sock->dev, "after remove\n");
4020f2d7 1031
4020f2d7
AD		 1032 mmc_free_host(mmc);
1033}
1034
dba4acca
AD		 1035#ifdef CONFIG_PM
1036
1037static int tifm_sd_suspend(struct tifm_dev *sock, pm_message_t state)
1038{
055b8224 1039 return mmc_suspend_host(tifm_get_drvdata(sock), state);
dba4acca
AD		 1040}
1041
1042static int tifm_sd_resume(struct tifm_dev *sock)
1043{
1044 struct mmc_host *mmc = tifm_get_drvdata(sock);
1045 struct tifm_sd *host = mmc_priv(mmc);
5897d657 1046 int rc;
dba4acca 1047
5897d657
AD		 1048 rc = tifm_sd_initialize_host(host);
1049 dev_dbg(&sock->dev, "resume initialize %d\n", rc);
1050
1051 if (rc)
1052 host->eject = 1;
1053 else
1054 rc = mmc_resume_host(mmc);
1055
1056 return rc;
dba4acca
AD		 1057}
1058
1059#else
1060
1061#define tifm_sd_suspend NULL
1062#define tifm_sd_resume NULL
1063
1064#endif /* CONFIG_PM */
1065
e23f2b8a
AD		 1066static struct tifm_device_id tifm_sd_id_tbl[] = {
1067 { TIFM_TYPE_SD }, { }
4020f2d7
AD		 1068};
1069
1070static struct tifm_driver tifm_sd_driver = {
1071 .driver = {
1072 .name = DRIVER_NAME,
1073 .owner = THIS_MODULE
1074 },
1075 .id_table = tifm_sd_id_tbl,
1076 .probe = tifm_sd_probe,
dba4acca
AD		 1077 .remove = tifm_sd_remove,
1078 .suspend = tifm_sd_suspend,
1079 .resume = tifm_sd_resume
4020f2d7
AD		 1080};
1081
1082static int __init tifm_sd_init(void)
1083{
1084 return tifm_register_driver(&tifm_sd_driver);
1085}
1086
1087static void __exit tifm_sd_exit(void)
1088{
1089 tifm_unregister_driver(&tifm_sd_driver);
1090}
1091
1092MODULE_AUTHOR("Alex Dubov");
1093MODULE_DESCRIPTION("TI FlashMedia SD driver");
1094MODULE_LICENSE("GPL");
1095MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
1096MODULE_VERSION(DRIVER_VERSION);
1097
1098module_init(tifm_sd_init);
1099module_exit(tifm_sd_exit);
Linux kernel - Deliverables
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