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Merge branch 'mailbox-for-linus' of git://git.linaro.org/landing-teams/working/fujits...
[deliverable/linux.git] / drivers / mmc / host / tmio_mmc_pio.c
CommitLineData
b6147490
GL		 1/*
2 * linux/drivers/mmc/host/tmio_mmc_pio.c
3 *
4 * Copyright (C) 2011 Guennadi Liakhovetski
5 * Copyright (C) 2007 Ian Molton
6 * Copyright (C) 2004 Ian Molton
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Driver for the MMC / SD / SDIO IP found in:
13 *
14 * TC6393XB, TC6391XB, TC6387XB, T7L66XB, ASIC3, SH-Mobile SoCs
15 *
16 * This driver draws mainly on scattered spec sheets, Reverse engineering
17 * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit
18 * support). (Further 4 bit support from a later datasheet).
19 *
20 * TODO:
21 * Investigate using a workqueue for PIO transfers
22 * Eliminate FIXMEs
23 * SDIO support
24 * Better Power management
25 * Handle MMC errors better
26 * double buffer support
27 *
28 */
29
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <linux/highmem.h>
33#include <linux/interrupt.h>
34#include <linux/io.h>
35#include <linux/irq.h>
36#include <linux/mfd/tmio.h>
37#include <linux/mmc/host.h>
0f506a96 38#include <linux/mmc/mmc.h>
fd0ea65d 39#include <linux/mmc/slot-gpio.h>
cba179ae 40#include <linux/mmc/tmio.h>
b6147490
GL		 41#include <linux/module.h>
42#include <linux/pagemap.h>
43#include <linux/platform_device.h>
c419e611 44#include <linux/pm_qos.h>
e6ee7182 45#include <linux/pm_runtime.h>
619b08d4 46#include <linux/regulator/consumer.h>
b8d11962 47#include <linux/mmc/sdio.h>
b6147490 48#include <linux/scatterlist.h>
b6147490 49#include <linux/spinlock.h>
e3de2be7 50#include <linux/workqueue.h>
b6147490
GL		 51
52#include "tmio_mmc.h"
53
b6147490
GL		 54void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
55{
54680fe7
SH		 56 host->sdcard_irq_mask &= ~(i & TMIO_MASK_IRQ);
57 sd_ctrl_write32(host, CTL_IRQ_MASK, host->sdcard_irq_mask);
b6147490
GL		 58}
59
60void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
61{
54680fe7
SH		 62 host->sdcard_irq_mask |= (i & TMIO_MASK_IRQ);
63 sd_ctrl_write32(host, CTL_IRQ_MASK, host->sdcard_irq_mask);
b6147490
GL		 64}
65
66static void tmio_mmc_ack_mmc_irqs(struct tmio_mmc_host *host, u32 i)
67{
68 sd_ctrl_write32(host, CTL_STATUS, ~i);
69}
70
71static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data)
72{
73 host->sg_len = data->sg_len;
74 host->sg_ptr = data->sg;
75 host->sg_orig = data->sg;
76 host->sg_off = 0;
77}
78
79static int tmio_mmc_next_sg(struct tmio_mmc_host *host)
80{
81 host->sg_ptr = sg_next(host->sg_ptr);
82 host->sg_off = 0;
83 return --host->sg_len;
84}
85
86#ifdef CONFIG_MMC_DEBUG
87
88#define STATUS_TO_TEXT(a, status, i) \
89 do { \
90 if (status & TMIO_STAT_##a) { \
91 if (i++) \
92 printk(" | "); \
93 printk(#a); \
94 } \
95 } while (0)
96
97static void pr_debug_status(u32 status)
98{
99 int i = 0;
a3c76eb9 100 pr_debug("status: %08x = ", status);
b6147490
GL		 101 STATUS_TO_TEXT(CARD_REMOVE, status, i);
102 STATUS_TO_TEXT(CARD_INSERT, status, i);
103 STATUS_TO_TEXT(SIGSTATE, status, i);
104 STATUS_TO_TEXT(WRPROTECT, status, i);
105 STATUS_TO_TEXT(CARD_REMOVE_A, status, i);
106 STATUS_TO_TEXT(CARD_INSERT_A, status, i);
107 STATUS_TO_TEXT(SIGSTATE_A, status, i);
108 STATUS_TO_TEXT(CMD_IDX_ERR, status, i);
109 STATUS_TO_TEXT(STOPBIT_ERR, status, i);
110 STATUS_TO_TEXT(ILL_FUNC, status, i);
111 STATUS_TO_TEXT(CMD_BUSY, status, i);
112 STATUS_TO_TEXT(CMDRESPEND, status, i);
113 STATUS_TO_TEXT(DATAEND, status, i);
114 STATUS_TO_TEXT(CRCFAIL, status, i);
115 STATUS_TO_TEXT(DATATIMEOUT, status, i);
116 STATUS_TO_TEXT(CMDTIMEOUT, status, i);
117 STATUS_TO_TEXT(RXOVERFLOW, status, i);
118 STATUS_TO_TEXT(TXUNDERRUN, status, i);
119 STATUS_TO_TEXT(RXRDY, status, i);
120 STATUS_TO_TEXT(TXRQ, status, i);
121 STATUS_TO_TEXT(ILL_ACCESS, status, i);
122 printk("\n");
123}
124
125#else
126#define pr_debug_status(s) do { } while (0)
127#endif
128
129static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
130{
131 struct tmio_mmc_host *host = mmc_priv(mmc);
132
7501c431
UH		 133 if (enable && !host->sdio_irq_enabled) {
134 /* Keep device active while SDIO irq is enabled */
135 pm_runtime_get_sync(mmc_dev(mmc));
136 host->sdio_irq_enabled = true;
137
54680fe7
SH		 138 host->sdio_irq_mask = TMIO_SDIO_MASK_ALL &
139 ~TMIO_SDIO_STAT_IOIRQ;
b6147490 140 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001);
54680fe7 141 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
7501c431 142 } else if (!enable && host->sdio_irq_enabled) {
54680fe7
SH		 143 host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;
144 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
b6147490 145 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000);
7501c431
UH		 146
147 host->sdio_irq_enabled = false;
0369483e
UH		 148 pm_runtime_mark_last_busy(mmc_dev(mmc));
149 pm_runtime_put_autosuspend(mmc_dev(mmc));
b6147490
GL		 150 }
151}
152
ae12d250
UH		 153static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
154 unsigned int new_clock)
b6147490
GL		 155{
156 u32 clk = 0, clock;
157
158 if (new_clock) {
159 for (clock = host->mmc->f_min, clk = 0x80000080;
160 new_clock >= (clock<<1); clk >>= 1)
161 clock <<= 1;
da29fe2b
SU		 162
163 /* 1/1 clock is option */
164 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) &&
165 ((clk >> 22) & 0x1))
166 clk |= 0xff;
b6147490
GL		 167 }
168
169 if (host->set_clk_div)
170 host->set_clk_div(host->pdev, (clk>>22) & 1);
171
172 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & 0x1ff);
619b08d4 173 msleep(10);
b6147490
GL		 174}
175
176static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
177{
69d1fe18 178 /* implicit BUG_ON(!res) */
5d60e500 179 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
69d1fe18
GL		 180 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
181 msleep(10);
182 }
d9b03421 183
b6147490
GL		 184 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~0x0100 &
185 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
186 msleep(10);
187}
188
189static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
190{
b6147490
GL		 191 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 |
192 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
193 msleep(10);
d9b03421 194
69d1fe18 195 /* implicit BUG_ON(!res) */
5d60e500 196 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
69d1fe18
GL		 197 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
198 msleep(10);
199 }
b6147490
GL		 200}
201
202static void tmio_mmc_reset(struct tmio_mmc_host *host)
203{
204 /* FIXME - should we set stop clock reg here */
205 sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
69d1fe18 206 /* implicit BUG_ON(!res) */
5d60e500 207 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG)
69d1fe18 208 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
b6147490
GL		 209 msleep(10);
210 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
5d60e500 211 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG)
69d1fe18 212 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
b6147490
GL		 213 msleep(10);
214}
215
216static void tmio_mmc_reset_work(struct work_struct *work)
217{
218 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
219 delayed_reset_work.work);
220 struct mmc_request *mrq;
221 unsigned long flags;
222
223 spin_lock_irqsave(&host->lock, flags);
224 mrq = host->mrq;
225
df3ef2d3
GL		 226 /*
227 * is request already finished? Since we use a non-blocking
228 * cancel_delayed_work(), it can happen, that a .set_ios() call preempts
229 * us, so, have to check for IS_ERR(host->mrq)
230 */
231 if (IS_ERR_OR_NULL(mrq)
b6147490
GL		 232 || time_is_after_jiffies(host->last_req_ts +
233 msecs_to_jiffies(2000))) {
234 spin_unlock_irqrestore(&host->lock, flags);
235 return;
236 }
237
238 dev_warn(&host->pdev->dev,
239 "timeout waiting for hardware interrupt (CMD%u)\n",
240 mrq->cmd->opcode);
241
242 if (host->data)
243 host->data->error = -ETIMEDOUT;
244 else if (host->cmd)
245 host->cmd->error = -ETIMEDOUT;
246 else
247 mrq->cmd->error = -ETIMEDOUT;
248
249 host->cmd = NULL;
250 host->data = NULL;
b6147490
GL		 251 host->force_pio = false;
252
253 spin_unlock_irqrestore(&host->lock, flags);
254
255 tmio_mmc_reset(host);
256
df3ef2d3
GL		 257 /* Ready for new calls */
258 host->mrq = NULL;
259
e3de2be7 260 tmio_mmc_abort_dma(host);
b6147490 261 mmc_request_done(host->mmc, mrq);
0369483e
UH		 262
263 pm_runtime_mark_last_busy(mmc_dev(host->mmc));
264 pm_runtime_put_autosuspend(mmc_dev(host->mmc));
b6147490
GL		 265}
266
df3ef2d3 267/* called with host->lock held, interrupts disabled */
b6147490
GL		 268static void tmio_mmc_finish_request(struct tmio_mmc_host *host)
269{
b9269fdd
GL		 270 struct mmc_request *mrq;
271 unsigned long flags;
b6147490 272
b9269fdd
GL		 273 spin_lock_irqsave(&host->lock, flags);
274
275 mrq = host->mrq;
276 if (IS_ERR_OR_NULL(mrq)) {
277 spin_unlock_irqrestore(&host->lock, flags);
b6147490 278 return;
b9269fdd 279 }
b6147490 280
b6147490
GL		 281 host->cmd = NULL;
282 host->data = NULL;
283 host->force_pio = false;
284
285 cancel_delayed_work(&host->delayed_reset_work);
286
df3ef2d3 287 host->mrq = NULL;
b9269fdd 288 spin_unlock_irqrestore(&host->lock, flags);
df3ef2d3 289
e3de2be7
GL		 290 if (mrq->cmd->error || (mrq->data && mrq->data->error))
291 tmio_mmc_abort_dma(host);
292
b6147490 293 mmc_request_done(host->mmc, mrq);
0369483e
UH		 294
295 pm_runtime_mark_last_busy(mmc_dev(host->mmc));
296 pm_runtime_put_autosuspend(mmc_dev(host->mmc));
b6147490
GL		 297}
298
b9269fdd
GL		 299static void tmio_mmc_done_work(struct work_struct *work)
300{
301 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
302 done);
303 tmio_mmc_finish_request(host);
304}
305
b6147490
GL		 306/* These are the bitmasks the tmio chip requires to implement the MMC response
307 * types. Note that R1 and R6 are the same in this scheme. */
308#define APP_CMD 0x0040
309#define RESP_NONE 0x0300
310#define RESP_R1 0x0400
311#define RESP_R1B 0x0500
312#define RESP_R2 0x0600
313#define RESP_R3 0x0700
314#define DATA_PRESENT 0x0800
315#define TRANSFER_READ 0x1000
316#define TRANSFER_MULTI 0x2000
317#define SECURITY_CMD 0x4000
b8d11962 318#define NO_CMD12_ISSUE 0x4000 /* TMIO_MMC_HAVE_CMD12_CTRL */
b6147490
GL		 319
320static int tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd)
321{
322 struct mmc_data *data = host->data;
323 int c = cmd->opcode;
e23cd53c 324 u32 irq_mask = TMIO_MASK_CMD;
b6147490 325
0f506a96
GL		 326 /* CMD12 is handled by hardware */
327 if (cmd->opcode == MMC_STOP_TRANSMISSION && !cmd->arg) {
b6147490
GL		 328 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x001);
329 return 0;
330 }
331
332 switch (mmc_resp_type(cmd)) {
333 case MMC_RSP_NONE: c |= RESP_NONE; break;
334 case MMC_RSP_R1: c |= RESP_R1; break;
335 case MMC_RSP_R1B: c |= RESP_R1B; break;
336 case MMC_RSP_R2: c |= RESP_R2; break;
337 case MMC_RSP_R3: c |= RESP_R3; break;
338 default:
339 pr_debug("Unknown response type %d\n", mmc_resp_type(cmd));
340 return -EINVAL;
341 }
342
343 host->cmd = cmd;
344
345/* FIXME - this seems to be ok commented out but the spec suggest this bit
346 * should be set when issuing app commands.
347 * if(cmd->flags & MMC_FLAG_ACMD)
348 * c |= APP_CMD;
349 */
350 if (data) {
351 c |= DATA_PRESENT;
352 if (data->blocks > 1) {
353 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x100);
354 c |= TRANSFER_MULTI;
b8d11962
SU		 355
356 /*
357 * Disable auto CMD12 at IO_RW_EXTENDED when
358 * multiple block transfer
359 */
360 if ((host->pdata->flags & TMIO_MMC_HAVE_CMD12_CTRL) &&
361 (cmd->opcode == SD_IO_RW_EXTENDED))
362 c |= NO_CMD12_ISSUE;
b6147490
GL		 363 }
364 if (data->flags & MMC_DATA_READ)
365 c |= TRANSFER_READ;
366 }
367
e23cd53c
GL		 368 if (!host->native_hotplug)
369 irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
370 tmio_mmc_enable_mmc_irqs(host, irq_mask);
b6147490
GL		 371
372 /* Fire off the command */
373 sd_ctrl_write32(host, CTL_ARG_REG, cmd->arg);
374 sd_ctrl_write16(host, CTL_SD_CMD, c);
375
376 return 0;
377}
378
b9bd7ff8
KM		 379static void tmio_mmc_transfer_data(struct tmio_mmc_host *host,
380 unsigned short *buf,
381 unsigned int count)
382{
383 int is_read = host->data->flags & MMC_DATA_READ;
384 u8 *buf8;
385
386 /*
387 * Transfer the data
388 */
389 if (is_read)
390 sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
391 else
392 sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
393
394 /* if count was even number */
395 if (!(count & 0x1))
396 return;
397
398 /* if count was odd number */
399 buf8 = (u8 *)(buf + (count >> 1));
400
401 /*
402 * FIXME
403 *
404 * driver and this function are assuming that
405 * it is used as little endian
406 */
407 if (is_read)
408 *buf8 = sd_ctrl_read16(host, CTL_SD_DATA_PORT) & 0xff;
409 else
410 sd_ctrl_write16(host, CTL_SD_DATA_PORT, *buf8);
411}
412
b6147490
GL		 413/*
414 * This chip always returns (at least?) as much data as you ask for.
415 * I'm unsure what happens if you ask for less than a block. This should be
25985edc 416 * looked into to ensure that a funny length read doesn't hose the controller.
b6147490
GL		 417 */
418static void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
419{
420 struct mmc_data *data = host->data;
421 void *sg_virt;
422 unsigned short *buf;
423 unsigned int count;
424 unsigned long flags;
425
426 if ((host->chan_tx || host->chan_rx) && !host->force_pio) {
427 pr_err("PIO IRQ in DMA mode!\n");
428 return;
429 } else if (!data) {
430 pr_debug("Spurious PIO IRQ\n");
431 return;
432 }
433
434 sg_virt = tmio_mmc_kmap_atomic(host->sg_ptr, &flags);
435 buf = (unsigned short *)(sg_virt + host->sg_off);
436
437 count = host->sg_ptr->length - host->sg_off;
438 if (count > data->blksz)
439 count = data->blksz;
440
441 pr_debug("count: %08x offset: %08x flags %08x\n",
442 count, host->sg_off, data->flags);
443
444 /* Transfer the data */
b9bd7ff8 445 tmio_mmc_transfer_data(host, buf, count);
b6147490
GL		 446
447 host->sg_off += count;
448
449 tmio_mmc_kunmap_atomic(host->sg_ptr, &flags, sg_virt);
450
451 if (host->sg_off == host->sg_ptr->length)
452 tmio_mmc_next_sg(host);
453
454 return;
455}
456
457static void tmio_mmc_check_bounce_buffer(struct tmio_mmc_host *host)
458{
459 if (host->sg_ptr == &host->bounce_sg) {
460 unsigned long flags;
461 void *sg_vaddr = tmio_mmc_kmap_atomic(host->sg_orig, &flags);
462 memcpy(sg_vaddr, host->bounce_buf, host->bounce_sg.length);
463 tmio_mmc_kunmap_atomic(host->sg_orig, &flags, sg_vaddr);
464 }
465}
466
467/* needs to be called with host->lock held */
468void tmio_mmc_do_data_irq(struct tmio_mmc_host *host)
469{
470 struct mmc_data *data = host->data;
471 struct mmc_command *stop;
472
473 host->data = NULL;
474
475 if (!data) {
476 dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
477 return;
478 }
479 stop = data->stop;
480
481 /* FIXME - return correct transfer count on errors */
482 if (!data->error)
483 data->bytes_xfered = data->blocks * data->blksz;
484 else
485 data->bytes_xfered = 0;
486
487 pr_debug("Completed data request\n");
488
489 /*
490 * FIXME: other drivers allow an optional stop command of any given type
491 * which we dont do, as the chip can auto generate them.
492 * Perhaps we can be smarter about when to use auto CMD12 and
493 * only issue the auto request when we know this is the desired
494 * stop command, allowing fallback to the stop command the
495 * upper layers expect. For now, we do what works.
496 */
497
498 if (data->flags & MMC_DATA_READ) {
499 if (host->chan_rx && !host->force_pio)
500 tmio_mmc_check_bounce_buffer(host);
501 dev_dbg(&host->pdev->dev, "Complete Rx request %p\n",
502 host->mrq);
503 } else {
504 dev_dbg(&host->pdev->dev, "Complete Tx request %p\n",
505 host->mrq);
506 }
507
508 if (stop) {
0f506a96 509 if (stop->opcode == MMC_STOP_TRANSMISSION && !stop->arg)
b6147490
GL		 510 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x000);
511 else
512 BUG();
513 }
514
b9269fdd 515 schedule_work(&host->done);
b6147490
GL		 516}
517
518static void tmio_mmc_data_irq(struct tmio_mmc_host *host)
519{
520 struct mmc_data *data;
521 spin_lock(&host->lock);
522 data = host->data;
523
524 if (!data)
525 goto out;
526
527 if (host->chan_tx && (data->flags & MMC_DATA_WRITE) && !host->force_pio) {
81e888da
SU		 528 u32 status = sd_ctrl_read32(host, CTL_STATUS);
529 bool done = false;
530
b6147490
GL		 531 /*
532 * Has all data been written out yet? Testing on SuperH showed,
533 * that in most cases the first interrupt comes already with the
534 * BUSY status bit clear, but on some operations, like mount or
535 * in the beginning of a write / sync / umount, there is one
536 * DATAEND interrupt with the BUSY bit set, in this cases
537 * waiting for one more interrupt fixes the problem.
538 */
81e888da
SU		 539 if (host->pdata->flags & TMIO_MMC_HAS_IDLE_WAIT) {
540 if (status & TMIO_STAT_ILL_FUNC)
541 done = true;
542 } else {
543 if (!(status & TMIO_STAT_CMD_BUSY))
544 done = true;
545 }
546
547 if (done) {
b6147490
GL		 548 tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
549 tasklet_schedule(&host->dma_complete);
550 }
551 } else if (host->chan_rx && (data->flags & MMC_DATA_READ) && !host->force_pio) {
552 tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
553 tasklet_schedule(&host->dma_complete);
554 } else {
555 tmio_mmc_do_data_irq(host);
556 tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_READOP | TMIO_MASK_WRITEOP);
557 }
558out:
559 spin_unlock(&host->lock);
560}
561
562static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
563 unsigned int stat)
564{
565 struct mmc_command *cmd = host->cmd;
566 int i, addr;
567
568 spin_lock(&host->lock);
569
570 if (!host->cmd) {
571 pr_debug("Spurious CMD irq\n");
572 goto out;
573 }
574
575 host->cmd = NULL;
576
577 /* This controller is sicker than the PXA one. Not only do we need to
578 * drop the top 8 bits of the first response word, we also need to
579 * modify the order of the response for short response command types.
580 */
581
582 for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4)
583 cmd->resp[i] = sd_ctrl_read32(host, addr);
584
585 if (cmd->flags & MMC_RSP_136) {
586 cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24);
587 cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24);
588 cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24);
589 cmd->resp[3] <<= 8;
590 } else if (cmd->flags & MMC_RSP_R3) {
591 cmd->resp[0] = cmd->resp[3];
592 }
593
594 if (stat & TMIO_STAT_CMDTIMEOUT)
595 cmd->error = -ETIMEDOUT;
596 else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC)
597 cmd->error = -EILSEQ;
598
599 /* If there is data to handle we enable data IRQs here, and
600 * we will ultimatley finish the request in the data_end handler.
601 * If theres no data or we encountered an error, finish now.
602 */
603 if (host->data && !cmd->error) {
604 if (host->data->flags & MMC_DATA_READ) {
605 if (host->force_pio || !host->chan_rx)
606 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_READOP);
607 else
608 tasklet_schedule(&host->dma_issue);
609 } else {
610 if (host->force_pio || !host->chan_tx)
611 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_WRITEOP);
612 else
613 tasklet_schedule(&host->dma_issue);
614 }
615 } else {
b9269fdd 616 schedule_work(&host->done);
b6147490
GL		 617 }
618
619out:
620 spin_unlock(&host->lock);
621}
622
7729c7a2
SH		 623static void tmio_mmc_card_irq_status(struct tmio_mmc_host *host,
624 int *ireg, int *status)
b6147490 625{
7729c7a2
SH		 626 *status = sd_ctrl_read32(host, CTL_STATUS);
627 *ireg = *status & TMIO_MASK_IRQ & ~host->sdcard_irq_mask;
b6147490 628
7729c7a2
SH		 629 pr_debug_status(*status);
630 pr_debug_status(*ireg);
f83bfa75
SU		 631
632 /* Clear the status except the interrupt status */
633 sd_ctrl_write32(host, CTL_STATUS, TMIO_MASK_IRQ);
7729c7a2 634}
b6147490 635
7729c7a2
SH		 636static bool __tmio_mmc_card_detect_irq(struct tmio_mmc_host *host,
637 int ireg, int status)
638{
639 struct mmc_host *mmc = host->mmc;
b6147490 640
e312eb1e
PP		 641 /* Card insert / remove attempts */
642 if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) {
643 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT |
644 TMIO_STAT_CARD_REMOVE);
71d111cd
GL		 645 if ((((ireg & TMIO_STAT_CARD_REMOVE) && mmc->card) ||
646 ((ireg & TMIO_STAT_CARD_INSERT) && !mmc->card)) &&
647 !work_pending(&mmc->detect.work))
b9269fdd 648 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
7729c7a2 649 return true;
b6147490
GL		 650 }
651
7729c7a2
SH		 652 return false;
653}
654
655irqreturn_t tmio_mmc_card_detect_irq(int irq, void *devid)
656{
657 unsigned int ireg, status;
658 struct tmio_mmc_host *host = devid;
b6147490 659
7729c7a2
SH		 660 tmio_mmc_card_irq_status(host, &ireg, &status);
661 __tmio_mmc_card_detect_irq(host, ireg, status);
662
663 return IRQ_HANDLED;
664}
665EXPORT_SYMBOL(tmio_mmc_card_detect_irq);
666
667static bool __tmio_mmc_sdcard_irq(struct tmio_mmc_host *host,
668 int ireg, int status)
669{
e312eb1e
PP		 670 /* Command completion */
671 if (ireg & (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT)) {
672 tmio_mmc_ack_mmc_irqs(host,
673 TMIO_STAT_CMDRESPEND |
674 TMIO_STAT_CMDTIMEOUT);
675 tmio_mmc_cmd_irq(host, status);
7729c7a2 676 return true;
e312eb1e 677 }
b6147490 678
e312eb1e
PP		 679 /* Data transfer */
680 if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) {
681 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ);
682 tmio_mmc_pio_irq(host);
7729c7a2 683 return true;
e312eb1e 684 }
b6147490 685
e312eb1e
PP		 686 /* Data transfer completion */
687 if (ireg & TMIO_STAT_DATAEND) {
688 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_DATAEND);
689 tmio_mmc_data_irq(host);
7729c7a2 690 return true;
b6147490 691 }
e312eb1e 692
7729c7a2
SH		 693 return false;
694}
695
696irqreturn_t tmio_mmc_sdcard_irq(int irq, void *devid)
697{
698 unsigned int ireg, status;
699 struct tmio_mmc_host *host = devid;
700
701 tmio_mmc_card_irq_status(host, &ireg, &status);
702 __tmio_mmc_sdcard_irq(host, ireg, status);
703
704 return IRQ_HANDLED;
705}
706EXPORT_SYMBOL(tmio_mmc_sdcard_irq);
707
708irqreturn_t tmio_mmc_sdio_irq(int irq, void *devid)
709{
710 struct tmio_mmc_host *host = devid;
711 struct mmc_host *mmc = host->mmc;
712 struct tmio_mmc_data *pdata = host->pdata;
713 unsigned int ireg, status;
6b98757e 714 unsigned int sdio_status;
7729c7a2
SH		 715
716 if (!(pdata->flags & TMIO_MMC_SDIO_IRQ))
717 return IRQ_HANDLED;
718
719 status = sd_ctrl_read16(host, CTL_SDIO_STATUS);
720 ireg = status & TMIO_SDIO_MASK_ALL & ~host->sdcard_irq_mask;
721
6b98757e
SU		 722 sdio_status = status & ~TMIO_SDIO_MASK_ALL;
723 if (pdata->flags & TMIO_MMC_SDIO_STATUS_QUIRK)
724 sdio_status |= 6;
725
726 sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status);
7729c7a2
SH		 727
728 if (mmc->caps & MMC_CAP_SDIO_IRQ && ireg & TMIO_SDIO_STAT_IOIRQ)
729 mmc_signal_sdio_irq(mmc);
730
731 return IRQ_HANDLED;
732}
733EXPORT_SYMBOL(tmio_mmc_sdio_irq);
734
735irqreturn_t tmio_mmc_irq(int irq, void *devid)
736{
737 struct tmio_mmc_host *host = devid;
738 unsigned int ireg, status;
739
740 pr_debug("MMC IRQ begin\n");
741
742 tmio_mmc_card_irq_status(host, &ireg, &status);
743 if (__tmio_mmc_card_detect_irq(host, ireg, status))
744 return IRQ_HANDLED;
745 if (__tmio_mmc_sdcard_irq(host, ireg, status))
746 return IRQ_HANDLED;
747
748 tmio_mmc_sdio_irq(irq, devid);
b6147490 749
b6147490
GL		 750 return IRQ_HANDLED;
751}
8e7bfdb3 752EXPORT_SYMBOL(tmio_mmc_irq);
b6147490
GL		 753
754static int tmio_mmc_start_data(struct tmio_mmc_host *host,
755 struct mmc_data *data)
756{
757 struct tmio_mmc_data *pdata = host->pdata;
758
759 pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n",
760 data->blksz, data->blocks);
761
762 /* Some hardware cannot perform 2 byte requests in 4 bit mode */
763 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
764 int blksz_2bytes = pdata->flags & TMIO_MMC_BLKSZ_2BYTES;
765
766 if (data->blksz < 2 || (data->blksz < 4 && !blksz_2bytes)) {
767 pr_err("%s: %d byte block unsupported in 4 bit mode\n",
768 mmc_hostname(host->mmc), data->blksz);
769 return -EINVAL;
770 }
771 }
772
773 tmio_mmc_init_sg(host, data);
774 host->data = data;
775
776 /* Set transfer length / blocksize */
777 sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz);
778 sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks);
779
780 tmio_mmc_start_dma(host, data);
781
782 return 0;
783}
784
785/* Process requests from the MMC layer */
786static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
787{
788 struct tmio_mmc_host *host = mmc_priv(mmc);
df3ef2d3 789 unsigned long flags;
b6147490
GL		 790 int ret;
791
df3ef2d3
GL		 792 spin_lock_irqsave(&host->lock, flags);
793
794 if (host->mrq) {
b6147490 795 pr_debug("request not null\n");
df3ef2d3
GL		 796 if (IS_ERR(host->mrq)) {
797 spin_unlock_irqrestore(&host->lock, flags);
798 mrq->cmd->error = -EAGAIN;
799 mmc_request_done(mmc, mrq);
800 return;
801 }
802 }
b6147490
GL		 803
804 host->last_req_ts = jiffies;
805 wmb();
806 host->mrq = mrq;
807
df3ef2d3
GL		 808 spin_unlock_irqrestore(&host->lock, flags);
809
0369483e
UH		 810 pm_runtime_get_sync(mmc_dev(mmc));
811
b6147490
GL		 812 if (mrq->data) {
813 ret = tmio_mmc_start_data(host, mrq->data);
814 if (ret)
815 goto fail;
816 }
817
818 ret = tmio_mmc_start_command(host, mrq->cmd);
819 if (!ret) {
820 schedule_delayed_work(&host->delayed_reset_work,
821 msecs_to_jiffies(2000));
822 return;
823 }
824
825fail:
b6147490 826 host->force_pio = false;
df3ef2d3 827 host->mrq = NULL;
b6147490
GL		 828 mrq->cmd->error = ret;
829 mmc_request_done(mmc, mrq);
0369483e
UH		 830
831 pm_runtime_mark_last_busy(mmc_dev(mmc));
832 pm_runtime_put_autosuspend(mmc_dev(mmc));
b6147490
GL		 833}
834
ae12d250 835static int tmio_mmc_clk_update(struct tmio_mmc_host *host)
8c102a96 836{
ae12d250 837 struct mmc_host *mmc = host->mmc;
8c102a96
GL		 838 struct tmio_mmc_data *pdata = host->pdata;
839 int ret;
840
841 if (!pdata->clk_enable)
842 return -ENOTSUPP;
843
844 ret = pdata->clk_enable(host->pdev, &mmc->f_max);
845 if (!ret)
846 mmc->f_min = mmc->f_max / 512;
847
848 return ret;
849}
850
619b08d4 851static void tmio_mmc_power_on(struct tmio_mmc_host *host, unsigned short vdd)
b958a67c
GL		 852{
853 struct mmc_host *mmc = host->mmc;
619b08d4
GL		 854 int ret = 0;
855
856 /* .set_ios() is returning void, so, no chance to report an error */
b958a67c 857
9d731e75
CB		 858 if (host->set_pwr)
859 host->set_pwr(host->pdev, 1);
860
619b08d4
GL		 861 if (!IS_ERR(mmc->supply.vmmc)) {
862 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
863 /*
864 * Attention: empiric value. With a b43 WiFi SDIO card this
865 * delay proved necessary for reliable card-insertion probing.
866 * 100us were not enough. Is this the same 140us delay, as in
867 * tmio_mmc_set_ios()?
868 */
869 udelay(200);
870 }
871 /*
872 * It seems, VccQ should be switched on after Vcc, this is also what the
873 * omap_hsmmc.c driver does.
874 */
875 if (!IS_ERR(mmc->supply.vqmmc) && !ret) {
6d1d6b47 876 ret = regulator_enable(mmc->supply.vqmmc);
619b08d4
GL		 877 udelay(200);
878 }
6d1d6b47
GL		 879
880 if (ret < 0)
881 dev_dbg(&host->pdev->dev, "Regulators failed to power up: %d\n",
882 ret);
619b08d4
GL		 883}
884
885static void tmio_mmc_power_off(struct tmio_mmc_host *host)
886{
887 struct mmc_host *mmc = host->mmc;
888
889 if (!IS_ERR(mmc->supply.vqmmc))
890 regulator_disable(mmc->supply.vqmmc);
891
b958a67c 892 if (!IS_ERR(mmc->supply.vmmc))
619b08d4 893 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
9d731e75
CB		 894
895 if (host->set_pwr)
896 host->set_pwr(host->pdev, 0);
b958a67c
GL		 897}
898
9ae4ed7d
UH		 899static void tmio_mmc_set_bus_width(struct tmio_mmc_host *host,
900 unsigned char bus_width)
901{
902 switch (bus_width) {
903 case MMC_BUS_WIDTH_1:
904 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x80e0);
905 break;
906 case MMC_BUS_WIDTH_4:
907 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x00e0);
908 break;
909 }
910}
911
b6147490
GL		 912/* Set MMC clock / power.
913 * Note: This controller uses a simple divider scheme therefore it cannot
914 * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
915 * MMC wont run that fast, it has to be clocked at 12MHz which is the next
916 * slowest setting.
917 */
918static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
919{
920 struct tmio_mmc_host *host = mmc_priv(mmc);
4932bd64 921 struct device *dev = &host->pdev->dev;
df3ef2d3
GL		 922 unsigned long flags;
923
0369483e
UH		 924 pm_runtime_get_sync(mmc_dev(mmc));
925
b9269fdd
GL		 926 mutex_lock(&host->ios_lock);
927
df3ef2d3
GL		 928 spin_lock_irqsave(&host->lock, flags);
929 if (host->mrq) {
930 if (IS_ERR(host->mrq)) {
4932bd64 931 dev_dbg(dev,
df3ef2d3
GL		 932 "%s.%d: concurrent .set_ios(), clk %u, mode %u\n",
933 current->comm, task_pid_nr(current),
934 ios->clock, ios->power_mode);
935 host->mrq = ERR_PTR(-EINTR);
936 } else {
4932bd64 937 dev_dbg(dev,
df3ef2d3
GL		 938 "%s.%d: CMD%u active since %lu, now %lu!\n",
939 current->comm, task_pid_nr(current),
940 host->mrq->cmd->opcode, host->last_req_ts, jiffies);
941 }
942 spin_unlock_irqrestore(&host->lock, flags);
b9269fdd
GL		 943
944 mutex_unlock(&host->ios_lock);
df3ef2d3
GL		 945 return;
946 }
947
948 host->mrq = ERR_PTR(-EBUSY);
949
950 spin_unlock_irqrestore(&host->lock, flags);
b6147490 951
3b292bb0
UH		 952 switch (ios->power_mode) {
953 case MMC_POWER_OFF:
954 tmio_mmc_power_off(host);
955 tmio_mmc_clk_stop(host);
956 break;
957 case MMC_POWER_UP:
71d111cd 958 tmio_mmc_set_clock(host, ios->clock);
3b292bb0 959 tmio_mmc_power_on(host, ios->vdd);
5fd01579 960 tmio_mmc_clk_start(host);
9ae4ed7d 961 tmio_mmc_set_bus_width(host, ios->bus_width);
3b292bb0
UH		 962 break;
963 case MMC_POWER_ON:
964 tmio_mmc_set_clock(host, ios->clock);
965 tmio_mmc_clk_start(host);
966 tmio_mmc_set_bus_width(host, ios->bus_width);
967 break;
968 }
b6147490
GL		 969
970 /* Let things settle. delay taken from winCE driver */
971 udelay(140);
df3ef2d3
GL		 972 if (PTR_ERR(host->mrq) == -EINTR)
973 dev_dbg(&host->pdev->dev,
974 "%s.%d: IOS interrupted: clk %u, mode %u",
975 current->comm, task_pid_nr(current),
976 ios->clock, ios->power_mode);
977 host->mrq = NULL;
b9269fdd 978
ae12d250
UH		 979 host->clk_cache = ios->clock;
980
b9269fdd 981 mutex_unlock(&host->ios_lock);
0369483e
UH		 982
983 pm_runtime_mark_last_busy(mmc_dev(mmc));
984 pm_runtime_put_autosuspend(mmc_dev(mmc));
b6147490
GL		 985}
986
987static int tmio_mmc_get_ro(struct mmc_host *mmc)
988{
989 struct tmio_mmc_host *host = mmc_priv(mmc);
990 struct tmio_mmc_data *pdata = host->pdata;
3071cafb
GL		 991 int ret = mmc_gpio_get_ro(mmc);
992 if (ret >= 0)
993 return ret;
b6147490 994
0369483e
UH		 995 pm_runtime_get_sync(mmc_dev(mmc));
996 ret = !((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) ||
997 (sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT));
998 pm_runtime_mark_last_busy(mmc_dev(mmc));
999 pm_runtime_put_autosuspend(mmc_dev(mmc));
1000
1001 return ret;
b6147490
GL		 1002}
1003
bbf0208d
KM		 1004static int tmio_multi_io_quirk(struct mmc_card *card,
1005 unsigned int direction, int blk_size)
1006{
1007 struct tmio_mmc_host *host = mmc_priv(card->host);
1008 struct tmio_mmc_data *pdata = host->pdata;
1009
1010 if (pdata->multi_io_quirk)
1011 return pdata->multi_io_quirk(card, direction, blk_size);
1012
1013 return blk_size;
1014}
1015
b6147490
GL		 1016static const struct mmc_host_ops tmio_mmc_ops = {
1017 .request = tmio_mmc_request,
1018 .set_ios = tmio_mmc_set_ios,
1019 .get_ro = tmio_mmc_get_ro,
2b63b341 1020 .get_cd = mmc_gpio_get_cd,
b6147490 1021 .enable_sdio_irq = tmio_mmc_enable_sdio_irq,
bbf0208d 1022 .multi_io_quirk = tmio_multi_io_quirk,
b6147490
GL		 1023};
1024
05fae4a7 1025static int tmio_mmc_init_ocr(struct tmio_mmc_host *host)
b958a67c
GL		 1026{
1027 struct tmio_mmc_data *pdata = host->pdata;
1028 struct mmc_host *mmc = host->mmc;
1029
1030 mmc_regulator_get_supply(mmc);
1031
05fae4a7 1032 /* use ocr_mask if no regulator */
b958a67c 1033 if (!mmc->ocr_avail)
05fae4a7
KM		 1034 mmc->ocr_avail = pdata->ocr_mask;
1035
1036 /*
1037 * try again.
1038 * There is possibility that regulator has not been probed
1039 */
1040 if (!mmc->ocr_avail)
1041 return -EPROBE_DEFER;
1042
1043 return 0;
b958a67c
GL		 1044}
1045
5a00a971
GL		 1046static void tmio_mmc_of_parse(struct platform_device *pdev,
1047 struct tmio_mmc_data *pdata)
1048{
1049 const struct device_node *np = pdev->dev.of_node;
1050 if (!np)
1051 return;
1052
1053 if (of_get_property(np, "toshiba,mmc-wrprotect-disable", NULL))
1054 pdata->flags |= TMIO_MMC_WRPROTECT_DISABLE;
1055}
1056
c3be1efd 1057int tmio_mmc_host_probe(struct tmio_mmc_host **host,
b6147490
GL		 1058 struct platform_device *pdev,
1059 struct tmio_mmc_data *pdata)
1060{
1061 struct tmio_mmc_host *_host;
1062 struct mmc_host *mmc;
1063 struct resource *res_ctl;
1064 int ret;
1065 u32 irq_mask = TMIO_MASK_CMD;
1066
5a00a971
GL		 1067 tmio_mmc_of_parse(pdev, pdata);
1068
7b952137
GL		 1069 if (!(pdata->flags & TMIO_MMC_HAS_IDLE_WAIT))
1070 pdata->write16_hook = NULL;
1071
b6147490
GL		 1072 res_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1073 if (!res_ctl)
1074 return -EINVAL;
1075
1076 mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &pdev->dev);
1077 if (!mmc)
1078 return -ENOMEM;
1079
274a752b
SB		 1080 ret = mmc_of_parse(mmc);
1081 if (ret < 0)
1082 goto host_free;
5a00a971 1083
7311bef0 1084 pdata->dev = &pdev->dev;
b6147490
GL		 1085 _host = mmc_priv(mmc);
1086 _host->pdata = pdata;
1087 _host->mmc = mmc;
1088 _host->pdev = pdev;
1089 platform_set_drvdata(pdev, mmc);
1090
9d731e75 1091 _host->set_pwr = pdata->set_pwr;
b6147490
GL		 1092 _host->set_clk_div = pdata->set_clk_div;
1093
05fae4a7
KM		 1094 ret = tmio_mmc_init_ocr(_host);
1095 if (ret < 0)
1096 goto host_free;
1097
b6147490
GL		 1098 _host->ctl = ioremap(res_ctl->start, resource_size(res_ctl));
1099 if (!_host->ctl) {
1100 ret = -ENOMEM;
1101 goto host_free;
1102 }
1103
1104 mmc->ops = &tmio_mmc_ops;
5a00a971 1105 mmc->caps |= MMC_CAP_4_BIT_DATA | pdata->capabilities;
dd006b30 1106 mmc->caps2 |= pdata->capabilities2;
b6147490
GL		 1107 mmc->max_segs = 32;
1108 mmc->max_blk_size = 512;
1109 mmc->max_blk_count = (PAGE_CACHE_SIZE / mmc->max_blk_size) *
1110 mmc->max_segs;
1111 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1112 mmc->max_seg_size = mmc->max_req_size;
b6147490 1113
c8be24c2 1114 _host->native_hotplug = !(pdata->flags & TMIO_MMC_USE_GPIO_CD ||
2b1ac5c2 1115 mmc->caps & MMC_CAP_NEEDS_POLL ||
5a00a971
GL		 1116 mmc->caps & MMC_CAP_NONREMOVABLE ||
1117 mmc->slot.cd_irq >= 0);
2b1ac5c2 1118
ae12d250 1119 if (tmio_mmc_clk_update(_host) < 0) {
8c102a96
GL		 1120 mmc->f_max = pdata->hclk;
1121 mmc->f_min = mmc->f_max / 512;
1122 }
1123
bb98d9d1
SS		 1124 /*
1125 * Check the sanity of mmc->f_min to prevent tmio_mmc_set_clock() from
1126 * looping forever...
1127 */
1128 if (mmc->f_min == 0) {
1129 ret = -EINVAL;
1130 goto host_free;
1131 }
1132
cbb18b30 1133 /*
0369483e
UH		 1134 * While using internal tmio hardware logic for card detection, we need
1135 * to ensure it stays powered for it to work.
cbb18b30 1136 */
2b1ac5c2 1137 if (_host->native_hotplug)
cbb18b30
BH		 1138 pm_runtime_get_noresume(&pdev->dev);
1139
b6147490
GL		 1140 tmio_mmc_clk_stop(_host);
1141 tmio_mmc_reset(_host);
1142
54680fe7 1143 _host->sdcard_irq_mask = sd_ctrl_read32(_host, CTL_IRQ_MASK);
b6147490 1144 tmio_mmc_disable_mmc_irqs(_host, TMIO_MASK_ALL);
e0337cc8
GL		 1145
1146 /* Unmask the IRQs we want to know about */
1147 if (!_host->chan_rx)
1148 irq_mask |= TMIO_MASK_READOP;
1149 if (!_host->chan_tx)
1150 irq_mask |= TMIO_MASK_WRITEOP;
1151 if (!_host->native_hotplug)
1152 irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
1153
1154 _host->sdcard_irq_mask &= ~irq_mask;
1155
7501c431
UH		 1156 _host->sdio_irq_enabled = false;
1157 if (pdata->flags & TMIO_MMC_SDIO_IRQ) {
1158 _host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;
1159 sd_ctrl_write16(_host, CTL_SDIO_IRQ_MASK, _host->sdio_irq_mask);
1160 sd_ctrl_write16(_host, CTL_TRANSACTION_CTL, 0x0000);
1161 }
b6147490 1162
b6147490 1163 spin_lock_init(&_host->lock);
b9269fdd 1164 mutex_init(&_host->ios_lock);
b6147490
GL		 1165
1166 /* Init delayed work for request timeouts */
1167 INIT_DELAYED_WORK(&_host->delayed_reset_work, tmio_mmc_reset_work);
b9269fdd 1168 INIT_WORK(&_host->done, tmio_mmc_done_work);
b6147490
GL		 1169
1170 /* See if we also get DMA */
1171 tmio_mmc_request_dma(_host, pdata);
1172
0369483e
UH		 1173 pm_runtime_set_active(&pdev->dev);
1174 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1175 pm_runtime_use_autosuspend(&pdev->dev);
1176 pm_runtime_enable(&pdev->dev);
1177
8c102a96 1178 ret = mmc_add_host(mmc);
8c102a96
GL		 1179 if (ret < 0) {
1180 tmio_mmc_host_remove(_host);
1181 return ret;
1182 }
b6147490 1183
c419e611
RW		 1184 dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
1185
c8be24c2 1186 if (pdata->flags & TMIO_MMC_USE_GPIO_CD) {
214fc309 1187 ret = mmc_gpio_request_cd(mmc, pdata->cd_gpio, 0);
c8be24c2
GL		 1188 if (ret < 0) {
1189 tmio_mmc_host_remove(_host);
1190 return ret;
1191 }
d4d11449 1192 mmc_gpiod_request_cd_irq(mmc);
c8be24c2
GL		 1193 }
1194
b6147490
GL		 1195 *host = _host;
1196
1197 return 0;
1198
b6147490
GL		 1199host_free:
1200 mmc_free_host(mmc);
1201
1202 return ret;
1203}
1204EXPORT_SYMBOL(tmio_mmc_host_probe);
1205
1206void tmio_mmc_host_remove(struct tmio_mmc_host *host)
1207{
e6ee7182 1208 struct platform_device *pdev = host->pdev;
c8be24c2
GL		 1209 struct mmc_host *mmc = host->mmc;
1210
2b1ac5c2 1211 if (!host->native_hotplug)
7311bef0
GL		 1212 pm_runtime_get_sync(&pdev->dev);
1213
c419e611
RW		 1214 dev_pm_qos_hide_latency_limit(&pdev->dev);
1215
c8be24c2 1216 mmc_remove_host(mmc);
b9269fdd 1217 cancel_work_sync(&host->done);
b6147490
GL		 1218 cancel_delayed_work_sync(&host->delayed_reset_work);
1219 tmio_mmc_release_dma(host);
e6ee7182 1220
e6ee7182
GL		 1221 pm_runtime_put_sync(&pdev->dev);
1222 pm_runtime_disable(&pdev->dev);
7311bef0
GL		 1223
1224 iounmap(host->ctl);
c8be24c2 1225 mmc_free_host(mmc);
b6147490
GL		 1226}
1227EXPORT_SYMBOL(tmio_mmc_host_remove);
1228
9ade7dbf 1229#ifdef CONFIG_PM
7311bef0
GL		 1230int tmio_mmc_host_runtime_suspend(struct device *dev)
1231{
ae12d250
UH		 1232 struct mmc_host *mmc = dev_get_drvdata(dev);
1233 struct tmio_mmc_host *host = mmc_priv(mmc);
1234
20e955c3
UH		 1235 tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL);
1236
ae12d250
UH		 1237 if (host->clk_cache)
1238 tmio_mmc_clk_stop(host);
1239
1240 if (host->pdata->clk_disable)
1241 host->pdata->clk_disable(host->pdev);
1242
7311bef0
GL		 1243 return 0;
1244}
1245EXPORT_SYMBOL(tmio_mmc_host_runtime_suspend);
1246
1247int tmio_mmc_host_runtime_resume(struct device *dev)
1248{
1249 struct mmc_host *mmc = dev_get_drvdata(dev);
1250 struct tmio_mmc_host *host = mmc_priv(mmc);
7311bef0 1251
ae12d250
UH		 1252 tmio_mmc_reset(host);
1253 tmio_mmc_clk_update(host);
1254
1255 if (host->clk_cache) {
1256 tmio_mmc_set_clock(host, host->clk_cache);
1257 tmio_mmc_clk_start(host);
1258 }
1259
162f43e3 1260 tmio_mmc_enable_dma(host, true);
7311bef0 1261
7311bef0
GL		 1262 return 0;
1263}
1264EXPORT_SYMBOL(tmio_mmc_host_runtime_resume);
710dec95 1265#endif
7311bef0 1266
b6147490 1267MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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