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tifm_sd: fix resume handler
[deliverable/linux.git] / drivers / mmc / tifm_sd.c
CommitLineData
4020f2d7
AD		 1/*
2 * tifm_sd.c - TI FlashMedia driver
3 *
4 * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12
13#include <linux/tifm.h>
14#include <linux/mmc/protocol.h>
15#include <linux/mmc/host.h>
16#include <linux/highmem.h>
2099c99e 17#include <asm/io.h>
4020f2d7
AD		 18
19#define DRIVER_NAME "tifm_sd"
4552f0cb 20#define DRIVER_VERSION "0.8"
4020f2d7
AD		 21
22static int no_dma = 0;
23static int fixed_timeout = 0;
24module_param(no_dma, bool, 0644);
25module_param(fixed_timeout, bool, 0644);
26
27/* Constants here are mostly from OMAP5912 datasheet */
28#define TIFM_MMCSD_RESET 0x0002
29#define TIFM_MMCSD_CLKMASK 0x03ff
30#define TIFM_MMCSD_POWER 0x0800
31#define TIFM_MMCSD_4BBUS 0x8000
32#define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
33#define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
34#define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
35#define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
36#define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
37#define TIFM_MMCSD_READ 0x8000
38
12c83452 39#define TIFM_MMCSD_ERRMASK 0x01e0 /* set bits: CCRC, CTO, DCRC, DTO */
4020f2d7
AD		 40#define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
41#define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
42#define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
43#define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
44#define TIFM_MMCSD_DTO 0x0020 /* data time-out */
45#define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
46#define TIFM_MMCSD_CTO 0x0080 /* command time-out */
47#define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
48#define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
49#define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
50#define TIFM_MMCSD_CERR 0x4000 /* card status error */
51
0007d483
AD		 52#define TIFM_MMCSD_ODTO 0x0040 /* open drain / extended timeout */
53#define TIFM_MMCSD_CARD_RO 0x0200 /* card is read-only */
54
4020f2d7
AD		 55#define TIFM_MMCSD_FIFO_SIZE 0x0020
56
57#define TIFM_MMCSD_RSP_R0 0x0000
58#define TIFM_MMCSD_RSP_R1 0x0100
59#define TIFM_MMCSD_RSP_R2 0x0200
60#define TIFM_MMCSD_RSP_R3 0x0300
61#define TIFM_MMCSD_RSP_R4 0x0400
62#define TIFM_MMCSD_RSP_R5 0x0500
63#define TIFM_MMCSD_RSP_R6 0x0600
64
65#define TIFM_MMCSD_RSP_BUSY 0x0800
66
67#define TIFM_MMCSD_CMD_BC 0x0000
68#define TIFM_MMCSD_CMD_BCR 0x1000
69#define TIFM_MMCSD_CMD_AC 0x2000
70#define TIFM_MMCSD_CMD_ADTC 0x3000
71
4020f2d7 72enum {
72dc9d96
AD		 73 CMD_READY = 0x0001,
74 FIFO_READY = 0x0002,
75 BRS_READY = 0x0004,
76 SCMD_ACTIVE = 0x0008,
77 SCMD_READY = 0x0010,
78 CARD_BUSY = 0x0020,
79 DATA_CARRY = 0x0040
0007d483 80};
4020f2d7
AD		 81
82struct tifm_sd {
83 struct tifm_dev *dev;
84
0007d483
AD		 85 unsigned short eject:1,
86 open_drain:1,
87 no_dma:1;
88 unsigned short cmd_flags;
72dc9d96 89
4020f2d7
AD		 90 unsigned int clk_freq;
91 unsigned int clk_div;
0803dd0c 92 unsigned long timeout_jiffies;
4020f2d7 93
8e02f858 94 struct tasklet_struct finish_tasklet;
0803dd0c 95 struct timer_list timer;
4020f2d7 96 struct mmc_request *req;
4020f2d7
AD		 97
98 size_t written_blocks;
4020f2d7
AD		 99 size_t buffer_size;
100 size_t buffer_pos;
101
102};
103
f9d429a2 104static char* tifm_sd_data_buffer(struct mmc_data *data)
255ef22e 105{
f9d429a2 106 return page_address(data->sg->page) + data->sg->offset;
255ef22e
AD		 107}
108
4020f2d7 109static int tifm_sd_transfer_data(struct tifm_dev *sock, struct tifm_sd *host,
2e8ce5e7 110 unsigned int host_status)
4020f2d7
AD		 111{
112 struct mmc_command *cmd = host->req->cmd;
113 unsigned int t_val = 0, cnt = 0;
255ef22e 114 char *buffer;
4020f2d7
AD		 115
116 if (host_status & TIFM_MMCSD_BRS) {
117 /* in non-dma rx mode BRS fires when fifo is still not empty */
0007d483 118 if (host->no_dma && (cmd->data->flags & MMC_DATA_READ)) {
f9d429a2 119 buffer = tifm_sd_data_buffer(host->req->data);
4020f2d7
AD		 120 while (host->buffer_size > host->buffer_pos) {
121 t_val = readl(sock->addr + SOCK_MMCSD_DATA);
255ef22e
AD		 122 buffer[host->buffer_pos++] = t_val & 0xff;
123 buffer[host->buffer_pos++] =
4020f2d7
AD		 124 (t_val >> 8) & 0xff;
125 }
126 }
127 return 1;
0007d483 128 } else if (host->no_dma) {
f9d429a2 129 buffer = tifm_sd_data_buffer(host->req->data);
4020f2d7
AD		 130 if ((cmd->data->flags & MMC_DATA_READ) &&
131 (host_status & TIFM_MMCSD_AF)) {
132 for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
133 t_val = readl(sock->addr + SOCK_MMCSD_DATA);
134 if (host->buffer_size > host->buffer_pos) {
255ef22e 135 buffer[host->buffer_pos++] =
4020f2d7 136 t_val & 0xff;
255ef22e 137 buffer[host->buffer_pos++] =
4020f2d7
AD		 138 (t_val >> 8) & 0xff;
139 }
140 }
141 } else if ((cmd->data->flags & MMC_DATA_WRITE)
142 && (host_status & TIFM_MMCSD_AE)) {
143 for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
144 if (host->buffer_size > host->buffer_pos) {
255ef22e
AD		 145 t_val = buffer[host->buffer_pos++]
146 & 0x00ff;
147 t_val |= ((buffer[host->buffer_pos++])
148 << 8) & 0xff00;
4020f2d7 149 writel(t_val,
2e8ce5e7 150 sock->addr + SOCK_MMCSD_DATA);
4020f2d7
AD		 151 }
152 }
153 }
154 }
155 return 0;
156}
157
158static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
159{
160 unsigned int rc = 0;
161
162 switch (mmc_resp_type(cmd)) {
163 case MMC_RSP_NONE:
164 rc |= TIFM_MMCSD_RSP_R0;
165 break;
166 case MMC_RSP_R1B:
167 rc |= TIFM_MMCSD_RSP_BUSY; // deliberate fall-through
168 case MMC_RSP_R1:
169 rc |= TIFM_MMCSD_RSP_R1;
170 break;
171 case MMC_RSP_R2:
172 rc |= TIFM_MMCSD_RSP_R2;
173 break;
174 case MMC_RSP_R3:
175 rc |= TIFM_MMCSD_RSP_R3;
176 break;
4020f2d7
AD		 177 default:
178 BUG();
179 }
180
181 switch (mmc_cmd_type(cmd)) {
182 case MMC_CMD_BC:
183 rc |= TIFM_MMCSD_CMD_BC;
184 break;
185 case MMC_CMD_BCR:
186 rc |= TIFM_MMCSD_CMD_BCR;
187 break;
188 case MMC_CMD_AC:
189 rc |= TIFM_MMCSD_CMD_AC;
190 break;
191 case MMC_CMD_ADTC:
192 rc |= TIFM_MMCSD_CMD_ADTC;
193 break;
194 default:
195 BUG();
196 }
197 return rc;
198}
199
200static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
201{
202 struct tifm_dev *sock = host->dev;
0007d483
AD		 203 unsigned int cmd_mask = tifm_sd_op_flags(cmd);
204
205 if (host->open_drain)
206 cmd_mask |= TIFM_MMCSD_ODTO;
4020f2d7
AD		 207
208 if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
209 cmd_mask |= TIFM_MMCSD_READ;
210
211 dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
2e8ce5e7 212 cmd->opcode, cmd->arg, cmd_mask);
4020f2d7
AD		 213
214 writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
215 writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
216 writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
217}
218
219static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
220{
221 cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
222 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
223 cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
224 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
225 cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
226 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
227 cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
228 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
229}
230
72dc9d96 231static void tifm_sd_check_status(struct tifm_sd *host)
4020f2d7 232{
72dc9d96 233 struct tifm_dev *sock = host->dev;
4020f2d7
AD		 234 struct mmc_command *cmd = host->req->cmd;
235
72dc9d96
AD		 236 if (cmd->error != MMC_ERR_NONE)
237 goto finish_request;
238
239 if (!(host->cmd_flags & CMD_READY))
4020f2d7 240 return;
72dc9d96
AD		 241
242 if (cmd->data) {
243 if (cmd->data->error != MMC_ERR_NONE) {
244 if ((host->cmd_flags & SCMD_ACTIVE)
245 && !(host->cmd_flags & SCMD_READY))
246 return;
247
248 goto finish_request;
4020f2d7 249 }
72dc9d96
AD		 250
251 if (!(host->cmd_flags & BRS_READY))
252 return;
253
254 if (!(host->no_dma || (host->cmd_flags & FIFO_READY)))
255 return;
256
257 if (cmd->data->flags & MMC_DATA_WRITE) {
258 if (host->req->stop) {
259 if (!(host->cmd_flags & SCMD_ACTIVE)) {
260 host->cmd_flags |= SCMD_ACTIVE;
261 writel(TIFM_MMCSD_EOFB
262 | readl(sock->addr
263 + SOCK_MMCSD_INT_ENABLE),
264 sock->addr
265 + SOCK_MMCSD_INT_ENABLE);
1289335a 266 tifm_sd_exec(host, host->req->stop);
72dc9d96 267 return;
1289335a 268 } else {
72dc9d96
AD		 269 if (!(host->cmd_flags & SCMD_READY)
270 || (host->cmd_flags & CARD_BUSY))
271 return;
272 writel((~TIFM_MMCSD_EOFB)
273 & readl(sock->addr
274 + SOCK_MMCSD_INT_ENABLE),
275 sock->addr
276 + SOCK_MMCSD_INT_ENABLE);
1289335a
AD		 277 }
278 } else {
72dc9d96
AD		 279 if (host->cmd_flags & CARD_BUSY)
280 return;
281 writel((~TIFM_MMCSD_EOFB)
282 & readl(sock->addr
283 + SOCK_MMCSD_INT_ENABLE),
284 sock->addr + SOCK_MMCSD_INT_ENABLE);
1289335a 285 }
72dc9d96 286 } else {
1289335a 287 if (host->req->stop) {
72dc9d96
AD		 288 if (!(host->cmd_flags & SCMD_ACTIVE)) {
289 host->cmd_flags |= SCMD_ACTIVE;
290 tifm_sd_exec(host, host->req->stop);
291 return;
292 } else {
293 if (!(host->cmd_flags & SCMD_READY))
294 return;
295 }
1289335a 296 }
4020f2d7 297 }
4020f2d7 298 }
72dc9d96
AD		 299finish_request:
300 tasklet_schedule(&host->finish_tasklet);
4020f2d7
AD		 301}
302
303/* Called from interrupt handler */
4552f0cb 304static void tifm_sd_data_event(struct tifm_dev *sock)
4020f2d7
AD		 305{
306 struct tifm_sd *host;
4552f0cb 307 unsigned int fifo_status = 0;
72dc9d96 308 struct mmc_data *r_data = NULL;
4020f2d7
AD		 309
310 spin_lock(&sock->lock);
311 host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
4552f0cb 312 fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
72dc9d96
AD		 313 dev_dbg(&sock->dev, "data event: fifo_status %x, flags %x\n",
314 fifo_status, host->cmd_flags);
4552f0cb 315
72dc9d96
AD		 316 if (host->req) {
317 r_data = host->req->cmd->data;
4552f0cb 318
72dc9d96
AD		 319 if (r_data && (fifo_status & TIFM_FIFO_READY)) {
320 host->cmd_flags |= FIFO_READY;
321 tifm_sd_check_status(host);
322 }
323 }
4552f0cb 324
72dc9d96 325 writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
4552f0cb 326 spin_unlock(&sock->lock);
4552f0cb
AD		 327}
328
329/* Called from interrupt handler */
330static void tifm_sd_card_event(struct tifm_dev *sock)
331{
332 struct tifm_sd *host;
333 unsigned int host_status = 0;
72dc9d96
AD		 334 int cmd_error = MMC_ERR_NONE;
335 struct mmc_command *cmd = NULL;
336 unsigned long flags;
4552f0cb
AD		 337
338 spin_lock(&sock->lock);
339 host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
72dc9d96
AD		 340 host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
341 dev_dbg(&sock->dev, "host event: host_status %x, flags %x\n",
342 host_status, host->cmd_flags);
4020f2d7 343
72dc9d96
AD		 344 if (host->req) {
345 cmd = host->req->cmd;
4020f2d7
AD		 346
347 if (host_status & TIFM_MMCSD_ERRMASK) {
72dc9d96
AD		 348 writel(host_status & TIFM_MMCSD_ERRMASK,
349 sock->addr + SOCK_MMCSD_STATUS);
350 if (host_status & TIFM_MMCSD_CTO)
351 cmd_error = MMC_ERR_TIMEOUT;
352 else if (host_status & TIFM_MMCSD_CCRC)
353 cmd_error = MMC_ERR_BADCRC;
354
355 if (cmd->data) {
356 if (host_status & TIFM_MMCSD_DTO)
357 cmd->data->error = MMC_ERR_TIMEOUT;
358 else if (host_status & TIFM_MMCSD_DCRC)
359 cmd->data->error = MMC_ERR_BADCRC;
360 }
4020f2d7
AD		 361
362 writel(TIFM_FIFO_INT_SETALL,
363 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
364 writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
365
366 if (host->req->stop) {
72dc9d96
AD		 367 if (host->cmd_flags & SCMD_ACTIVE) {
368 host->req->stop->error = cmd_error;
369 host->cmd_flags |= SCMD_READY;
370 } else {
371 cmd->error = cmd_error;
372 host->cmd_flags |= SCMD_ACTIVE;
4020f2d7 373 tifm_sd_exec(host, host->req->stop);
4020f2d7 374 goto done;
4020f2d7 375 }
72dc9d96
AD		 376 } else
377 cmd->error = cmd_error;
378 } else {
379 if (host_status & (TIFM_MMCSD_EOC | TIFM_MMCSD_CERR)) {
380 if (!(host->cmd_flags & CMD_READY)) {
381 host->cmd_flags |= CMD_READY;
382 tifm_sd_fetch_resp(cmd, sock);
383 } else if (host->cmd_flags & SCMD_ACTIVE) {
384 host->cmd_flags |= SCMD_READY;
385 tifm_sd_fetch_resp(host->req->stop,
386 sock);
387 }
4020f2d7 388 }
72dc9d96
AD		 389 if (host_status & TIFM_MMCSD_BRS)
390 host->cmd_flags |= BRS_READY;
4020f2d7
AD		 391 }
392
72dc9d96
AD		 393 if (host->no_dma && cmd->data) {
394 if (host_status & TIFM_MMCSD_AE)
395 writel(host_status & TIFM_MMCSD_AE,
396 sock->addr + SOCK_MMCSD_STATUS);
397
398 if (host_status & (TIFM_MMCSD_AE | TIFM_MMCSD_AF
399 | TIFM_MMCSD_BRS)) {
400 local_irq_save(flags);
401 tifm_sd_transfer_data(sock, host, host_status);
402 local_irq_restore(flags);
403 host_status &= ~TIFM_MMCSD_AE;
404 }
4020f2d7 405 }
4020f2d7 406
72dc9d96
AD		 407 if (host_status & TIFM_MMCSD_EOFB)
408 host->cmd_flags &= ~CARD_BUSY;
409 else if (host_status & TIFM_MMCSD_CB)
410 host->cmd_flags |= CARD_BUSY;
411
412 tifm_sd_check_status(host);
413 }
4020f2d7 414done:
72dc9d96 415 writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
4020f2d7 416 spin_unlock(&sock->lock);
4020f2d7
AD		 417}
418
2e8ce5e7 419static void tifm_sd_prepare_data(struct tifm_sd *host, struct mmc_command *cmd)
4020f2d7 420{
2e8ce5e7 421 struct tifm_dev *sock = host->dev;
4020f2d7
AD		 422 unsigned int dest_cnt;
423
424 /* DMA style IO */
2e8ce5e7
AD		 425 dev_dbg(&sock->dev, "setting dma for %d blocks\n",
426 cmd->data->blocks);
4020f2d7 427 writel(TIFM_FIFO_INT_SETALL,
2e8ce5e7 428 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
f0d1b0b3 429 writel(ilog2(cmd->data->blksz) - 2,
2e8ce5e7 430 sock->addr + SOCK_FIFO_PAGE_SIZE);
4020f2d7
AD		 431 writel(TIFM_FIFO_ENABLE, sock->addr + SOCK_FIFO_CONTROL);
432 writel(TIFM_FIFO_INTMASK, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
433
434 dest_cnt = (cmd->data->blocks) << 8;
435
436 writel(sg_dma_address(cmd->data->sg), sock->addr + SOCK_DMA_ADDRESS);
437
438 writel(cmd->data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
439 writel(cmd->data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
440
441 if (cmd->data->flags & MMC_DATA_WRITE) {
442 writel(TIFM_MMCSD_TXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
443 writel(dest_cnt | TIFM_DMA_TX | TIFM_DMA_EN,
2e8ce5e7 444 sock->addr + SOCK_DMA_CONTROL);
4020f2d7
AD		 445 } else {
446 writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
447 writel(dest_cnt | TIFM_DMA_EN, sock->addr + SOCK_DMA_CONTROL);
448 }
449}
450
451static void tifm_sd_set_data_timeout(struct tifm_sd *host,
2e8ce5e7 452 struct mmc_data *data)
4020f2d7
AD		 453{
454 struct tifm_dev *sock = host->dev;
455 unsigned int data_timeout = data->timeout_clks;
456
457 if (fixed_timeout)
458 return;
459
460 data_timeout += data->timeout_ns /
83d420ba 461 ((1000000000UL / host->clk_freq) * host->clk_div);
4020f2d7
AD		 462
463 if (data_timeout < 0xffff) {
4020f2d7 464 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
83d420ba
AD		 465 writel((~TIFM_MMCSD_DPE)
466 & readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
467 sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
4020f2d7 468 } else {
4020f2d7 469 data_timeout = (data_timeout >> 10) + 1;
2e8ce5e7 470 if (data_timeout > 0xffff)
4020f2d7
AD		 471 data_timeout = 0; /* set to unlimited */
472 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
83d420ba
AD		 473 writel(TIFM_MMCSD_DPE
474 | readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
475 sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
4020f2d7
AD		 476 }
477}
478
479static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
480{
481 struct tifm_sd *host = mmc_priv(mmc);
482 struct tifm_dev *sock = host->dev;
483 unsigned long flags;
484 int sg_count = 0;
485 struct mmc_data *r_data = mrq->cmd->data;
486
487 spin_lock_irqsave(&sock->lock, flags);
0007d483 488 if (host->eject) {
4020f2d7
AD		 489 spin_unlock_irqrestore(&sock->lock, flags);
490 goto err_out;
491 }
492
493 if (host->req) {
494 printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
495 spin_unlock_irqrestore(&sock->lock, flags);
496 goto err_out;
497 }
498
499 if (r_data) {
500 tifm_sd_set_data_timeout(host, r_data);
501
dfef26d9
AD		 502 if (host->no_dma) {
503 host->buffer_size = mrq->cmd->data->blocks
504 * mrq->cmd->data->blksz;
505
506 writel(TIFM_MMCSD_BUFINT
507 | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
508 sock->addr + SOCK_MMCSD_INT_ENABLE);
509 writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8)
510 | (TIFM_MMCSD_FIFO_SIZE - 1),
511 sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
512
513 host->written_blocks = 0;
514 host->cmd_flags &= ~CARD_BUSY;
515 host->buffer_pos = 0;
516 writel(r_data->blocks - 1,
517 sock->addr + SOCK_MMCSD_NUM_BLOCKS);
518 writel(r_data->blksz - 1,
519 sock->addr + SOCK_MMCSD_BLOCK_LEN);
520 } else {
521 sg_count = tifm_map_sg(sock, r_data->sg, r_data->sg_len,
522 mrq->cmd->flags & MMC_DATA_WRITE
523 ? PCI_DMA_TODEVICE
524 : PCI_DMA_FROMDEVICE);
525 if (sg_count != 1) {
526 printk(KERN_ERR DRIVER_NAME
527 ": scatterlist map failed\n");
528 spin_unlock_irqrestore(&sock->lock, flags);
529 goto err_out;
530 }
4020f2d7 531
dfef26d9
AD		 532 host->written_blocks = 0;
533 host->cmd_flags &= ~CARD_BUSY;
534 tifm_sd_prepare_data(host, mrq->cmd);
535 }
4020f2d7
AD		 536 }
537
538 host->req = mrq;
0803dd0c 539 mod_timer(&host->timer, jiffies + host->timeout_jiffies);
72dc9d96 540 host->cmd_flags = 0;
4020f2d7 541 writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
2e8ce5e7 542 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 543 tifm_sd_exec(host, mrq->cmd);
544 spin_unlock_irqrestore(&sock->lock, flags);
545 return;
546
547err_out:
548 if (sg_count > 0)
549 tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
550 (r_data->flags & MMC_DATA_WRITE)
551 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
552
553 mrq->cmd->error = MMC_ERR_TIMEOUT;
554 mmc_request_done(mmc, mrq);
555}
556
8e02f858 557static void tifm_sd_end_cmd(unsigned long data)
4020f2d7 558{
8e02f858 559 struct tifm_sd *host = (struct tifm_sd*)data;
4020f2d7
AD		 560 struct tifm_dev *sock = host->dev;
561 struct mmc_host *mmc = tifm_get_drvdata(sock);
562 struct mmc_request *mrq;
e069d79d 563 struct mmc_data *r_data = NULL;
4020f2d7
AD		 564 unsigned long flags;
565
566 spin_lock_irqsave(&sock->lock, flags);
567
0803dd0c 568 del_timer(&host->timer);
4020f2d7 569 mrq = host->req;
e069d79d 570 host->req = NULL;
4020f2d7
AD		 571
572 if (!mrq) {
573 printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
574 spin_unlock_irqrestore(&sock->lock, flags);
575 return;
576 }
577
578 r_data = mrq->cmd->data;
579 if (r_data) {
dfef26d9
AD		 580 if (host->no_dma) {
581 writel((~TIFM_MMCSD_BUFINT) &
582 readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
583 sock->addr + SOCK_MMCSD_INT_ENABLE);
584
585 if (r_data->flags & MMC_DATA_WRITE) {
586 r_data->bytes_xfered = host->written_blocks
587 * r_data->blksz;
588 } else {
589 r_data->bytes_xfered = r_data->blocks -
590 readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS)
591 - 1;
592 r_data->bytes_xfered *= r_data->blksz;
593 r_data->bytes_xfered += r_data->blksz
594 - readl(sock->addr + SOCK_MMCSD_BLOCK_LEN)
595 + 1;
596 }
597 host->buffer_pos = 0;
598 host->buffer_size = 0;
4020f2d7 599 } else {
dfef26d9
AD		 600 if (r_data->flags & MMC_DATA_WRITE) {
601 r_data->bytes_xfered = host->written_blocks
602 * r_data->blksz;
603 } else {
604 r_data->bytes_xfered = r_data->blocks -
605 readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
606 r_data->bytes_xfered *= r_data->blksz;
607 r_data->bytes_xfered += r_data->blksz -
608 readl(sock->addr + SOCK_MMCSD_BLOCK_LEN)
609 + 1;
610 }
611 tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
612 (r_data->flags & MMC_DATA_WRITE)
613 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
4020f2d7 614 }
4020f2d7
AD		 615 }
616
617 writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
2e8ce5e7 618 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 619
620 spin_unlock_irqrestore(&sock->lock, flags);
4020f2d7
AD		 621 mmc_request_done(mmc, mrq);
622}
623
0803dd0c 624static void tifm_sd_abort(unsigned long data)
4020f2d7 625{
8e02f858
AD		 626 struct tifm_sd *host = (struct tifm_sd*)data;
627
4020f2d7 628 printk(KERN_ERR DRIVER_NAME
b039d4a1 629 ": card failed to respond for a long period of time\n");
8e02f858 630
8e02f858 631 tifm_eject(host->dev);
4020f2d7
AD		 632}
633
634static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
635{
636 struct tifm_sd *host = mmc_priv(mmc);
637 struct tifm_dev *sock = host->dev;
638 unsigned int clk_div1, clk_div2;
639 unsigned long flags;
640
641 spin_lock_irqsave(&sock->lock, flags);
642
643 dev_dbg(&sock->dev, "Setting bus width %d, power %d\n", ios->bus_width,
644 ios->power_mode);
645 if (ios->bus_width == MMC_BUS_WIDTH_4) {
646 writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
647 sock->addr + SOCK_MMCSD_CONFIG);
648 } else {
2e8ce5e7
AD		 649 writel((~TIFM_MMCSD_4BBUS)
650 & readl(sock->addr + SOCK_MMCSD_CONFIG),
651 sock->addr + SOCK_MMCSD_CONFIG);
4020f2d7
AD		 652 }
653
654 if (ios->clock) {
655 clk_div1 = 20000000 / ios->clock;
656 if (!clk_div1)
657 clk_div1 = 1;
658
659 clk_div2 = 24000000 / ios->clock;
660 if (!clk_div2)
661 clk_div2 = 1;
662
663 if ((20000000 / clk_div1) > ios->clock)
664 clk_div1++;
665 if ((24000000 / clk_div2) > ios->clock)
666 clk_div2++;
667 if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
668 host->clk_freq = 20000000;
669 host->clk_div = clk_div1;
2e8ce5e7
AD		 670 writel((~TIFM_CTRL_FAST_CLK)
671 & readl(sock->addr + SOCK_CONTROL),
672 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 673 } else {
674 host->clk_freq = 24000000;
675 host->clk_div = clk_div2;
2e8ce5e7
AD		 676 writel(TIFM_CTRL_FAST_CLK
677 | readl(sock->addr + SOCK_CONTROL),
678 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 679 }
680 } else {
681 host->clk_div = 0;
682 }
683 host->clk_div &= TIFM_MMCSD_CLKMASK;
2e8ce5e7
AD		 684 writel(host->clk_div
685 | ((~TIFM_MMCSD_CLKMASK)
686 & readl(sock->addr + SOCK_MMCSD_CONFIG)),
687 sock->addr + SOCK_MMCSD_CONFIG);
4020f2d7 688
0007d483 689 host->open_drain = (ios->bus_mode == MMC_BUSMODE_OPENDRAIN);
4020f2d7
AD		 690
691 /* chip_select : maybe later */
692 //vdd
693 //power is set before probe / after remove
4020f2d7
AD		 694
695 spin_unlock_irqrestore(&sock->lock, flags);
696}
697
698static int tifm_sd_ro(struct mmc_host *mmc)
699{
0007d483 700 int rc = 0;
4020f2d7
AD		 701 struct tifm_sd *host = mmc_priv(mmc);
702 struct tifm_dev *sock = host->dev;
703 unsigned long flags;
704
705 spin_lock_irqsave(&sock->lock, flags);
0007d483
AD		 706 if (TIFM_MMCSD_CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE))
707 rc = 1;
4020f2d7
AD		 708 spin_unlock_irqrestore(&sock->lock, flags);
709 return rc;
710}
711
dfef26d9 712static const struct mmc_host_ops tifm_sd_ops = {
4020f2d7
AD		 713 .request = tifm_sd_request,
714 .set_ios = tifm_sd_ios,
715 .get_ro = tifm_sd_ro
716};
717
8e02f858 718static int tifm_sd_initialize_host(struct tifm_sd *host)
4020f2d7 719{
8e02f858
AD		 720 int rc;
721 unsigned int host_status = 0;
4020f2d7 722 struct tifm_dev *sock = host->dev;
4020f2d7 723
8e02f858
AD		 724 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
725 mmiowb();
726 host->clk_div = 61;
727 host->clk_freq = 20000000;
728 writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
729 writel(host->clk_div | TIFM_MMCSD_POWER,
730 sock->addr + SOCK_MMCSD_CONFIG);
731
732 /* wait up to 0.51 sec for reset */
5897d657 733 for (rc = 32; rc <= 256; rc <<= 1) {
8e02f858
AD		 734 if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
735 rc = 0;
736 break;
737 }
738 msleep(rc);
739 }
740
741 if (rc) {
5897d657
AD		 742 printk(KERN_ERR "%s : controller failed to reset\n",
743 sock->dev.bus_id);
8e02f858
AD		 744 return -ENODEV;
745 }
746
747 writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
748 writel(host->clk_div | TIFM_MMCSD_POWER,
749 sock->addr + SOCK_MMCSD_CONFIG);
750 writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
751
752 // command timeout fixed to 64 clocks for now
753 writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO);
754 writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
755
5897d657 756 for (rc = 16; rc <= 64; rc <<= 1) {
8e02f858
AD		 757 host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
758 writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
759 if (!(host_status & TIFM_MMCSD_ERRMASK)
760 && (host_status & TIFM_MMCSD_EOC)) {
761 rc = 0;
762 break;
763 }
764 msleep(rc);
765 }
766
767 if (rc) {
5897d657
AD		 768 printk(KERN_ERR
769 "%s : card not ready - probe failed on initialization\n",
770 sock->dev.bus_id);
8e02f858
AD		 771 return -ENODEV;
772 }
773
5897d657
AD		 774 writel(TIFM_MMCSD_CERR | TIFM_MMCSD_BRS | TIFM_MMCSD_EOC
775 | TIFM_MMCSD_ERRMASK,
8e02f858
AD		 776 sock->addr + SOCK_MMCSD_INT_ENABLE);
777 mmiowb();
778
779 return 0;
4020f2d7
AD		 780}
781
782static int tifm_sd_probe(struct tifm_dev *sock)
783{
784 struct mmc_host *mmc;
785 struct tifm_sd *host;
786 int rc = -EIO;
787
2e8ce5e7
AD		 788 if (!(TIFM_SOCK_STATE_OCCUPIED
789 & readl(sock->addr + SOCK_PRESENT_STATE))) {
4020f2d7
AD		 790 printk(KERN_WARNING DRIVER_NAME ": card gone, unexpectedly\n");
791 return rc;
792 }
793
794 mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
795 if (!mmc)
796 return -ENOMEM;
797
798 host = mmc_priv(mmc);
0007d483 799 host->no_dma = no_dma;
4020f2d7 800 tifm_set_drvdata(sock, mmc);
8e02f858 801 host->dev = sock;
4020f2d7
AD		 802 host->timeout_jiffies = msecs_to_jiffies(1000);
803
dfef26d9 804 tasklet_init(&host->finish_tasklet, tifm_sd_end_cmd,
8e02f858
AD		 805 (unsigned long)host);
806 setup_timer(&host->timer, tifm_sd_abort, (unsigned long)host);
807
4020f2d7
AD		 808 mmc->ops = &tifm_sd_ops;
809 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
8e02f858 810 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE;
4020f2d7
AD		 811 mmc->f_min = 20000000 / 60;
812 mmc->f_max = 24000000;
813 mmc->max_hw_segs = 1;
814 mmc->max_phys_segs = 1;
55db890a
PO		 815 // limited by DMA counter - it's safer to stick with
816 // block counter has 11 bits though
817 mmc->max_blk_count = 256;
818 // 2k maximum hw block length
fe4a3c7a 819 mmc->max_blk_size = 2048;
55db890a
PO		 820 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
821 mmc->max_seg_size = mmc->max_req_size;
4552f0cb
AD		 822 sock->card_event = tifm_sd_card_event;
823 sock->data_event = tifm_sd_data_event;
8e02f858 824 rc = tifm_sd_initialize_host(host);
4020f2d7 825
8e02f858
AD		 826 if (!rc)
827 rc = mmc_add_host(mmc);
828 if (rc)
829 goto out_free_mmc;
4020f2d7
AD		 830
831 return 0;
8e02f858
AD		 832out_free_mmc:
833 mmc_free_host(mmc);
4020f2d7
AD		 834 return rc;
835}
836
837static void tifm_sd_remove(struct tifm_dev *sock)
838{
839 struct mmc_host *mmc = tifm_get_drvdata(sock);
840 struct tifm_sd *host = mmc_priv(mmc);
b039d4a1 841 unsigned long flags;
4020f2d7 842
592d372a 843 spin_lock_irqsave(&sock->lock, flags);
0007d483 844 host->eject = 1;
b039d4a1
AD		 845 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
846 mmiowb();
592d372a
AD		 847 spin_unlock_irqrestore(&sock->lock, flags);
848
849 tasklet_kill(&host->finish_tasklet);
850
b039d4a1 851 spin_lock_irqsave(&sock->lock, flags);
b039d4a1
AD		 852 if (host->req) {
853 writel(TIFM_FIFO_INT_SETALL,
854 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
855 writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
592d372a
AD		 856 host->req->cmd->error = MMC_ERR_TIMEOUT;
857 if (host->req->stop)
858 host->req->stop->error = MMC_ERR_TIMEOUT;
b039d4a1
AD		 859 tasklet_schedule(&host->finish_tasklet);
860 }
861 spin_unlock_irqrestore(&sock->lock, flags);
8e02f858 862 mmc_remove_host(mmc);
592d372a 863 dev_dbg(&sock->dev, "after remove\n");
4020f2d7
AD		 864
865 /* The meaning of the bit majority in this constant is unknown. */
866 writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
2e8ce5e7 867 sock->addr + SOCK_CONTROL);
4020f2d7 868
4020f2d7
AD		 869 mmc_free_host(mmc);
870}
871
dba4acca
AD		 872#ifdef CONFIG_PM
873
874static int tifm_sd_suspend(struct tifm_dev *sock, pm_message_t state)
875{
876 struct mmc_host *mmc = tifm_get_drvdata(sock);
877 int rc;
878
879 rc = mmc_suspend_host(mmc, state);
880 /* The meaning of the bit majority in this constant is unknown. */
881 writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
882 sock->addr + SOCK_CONTROL);
883 return rc;
884}
885
886static int tifm_sd_resume(struct tifm_dev *sock)
887{
888 struct mmc_host *mmc = tifm_get_drvdata(sock);
889 struct tifm_sd *host = mmc_priv(mmc);
5897d657 890 int rc;
dba4acca 891
5897d657
AD		 892 rc = tifm_sd_initialize_host(host);
893 dev_dbg(&sock->dev, "resume initialize %d\n", rc);
894
895 if (rc)
896 host->eject = 1;
897 else
898 rc = mmc_resume_host(mmc);
899
900 return rc;
dba4acca
AD		 901}
902
903#else
904
905#define tifm_sd_suspend NULL
906#define tifm_sd_resume NULL
907
908#endif /* CONFIG_PM */
909
e23f2b8a
AD		 910static struct tifm_device_id tifm_sd_id_tbl[] = {
911 { TIFM_TYPE_SD }, { }
4020f2d7
AD		 912};
913
914static struct tifm_driver tifm_sd_driver = {
915 .driver = {
916 .name = DRIVER_NAME,
917 .owner = THIS_MODULE
918 },
919 .id_table = tifm_sd_id_tbl,
920 .probe = tifm_sd_probe,
dba4acca
AD		 921 .remove = tifm_sd_remove,
922 .suspend = tifm_sd_suspend,
923 .resume = tifm_sd_resume
4020f2d7
AD		 924};
925
926static int __init tifm_sd_init(void)
927{
928 return tifm_register_driver(&tifm_sd_driver);
929}
930
931static void __exit tifm_sd_exit(void)
932{
933 tifm_unregister_driver(&tifm_sd_driver);
934}
935
936MODULE_AUTHOR("Alex Dubov");
937MODULE_DESCRIPTION("TI FlashMedia SD driver");
938MODULE_LICENSE("GPL");
939MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
940MODULE_VERSION(DRIVER_VERSION);
941
942module_init(tifm_sd_init);
943module_exit(tifm_sd_exit);
Linux kernel - Deliverables
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