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1d6432fe DB |
1 | /* |
2 | * Atmel AT45xxx DataFlash MTD driver for lightweight SPI framework | |
3 | * | |
4 | * Largely derived from at91_dataflash.c: | |
5 | * Copyright (C) 2003-2005 SAN People (Pty) Ltd | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
1d6432fe DB |
12 | #include <linux/module.h> |
13 | #include <linux/init.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/device.h> | |
ec9ce52e | 17 | #include <linux/mutex.h> |
771999b6 | 18 | #include <linux/err.h> |
5b7f3a50 | 19 | #include <linux/math64.h> |
b94e757c SG |
20 | #include <linux/of.h> |
21 | #include <linux/of_device.h> | |
771999b6 | 22 | |
1d6432fe DB |
23 | #include <linux/spi/spi.h> |
24 | #include <linux/spi/flash.h> | |
25 | ||
26 | #include <linux/mtd/mtd.h> | |
27 | #include <linux/mtd/partitions.h> | |
28 | ||
1d6432fe DB |
29 | /* |
30 | * DataFlash is a kind of SPI flash. Most AT45 chips have two buffers in | |
31 | * each chip, which may be used for double buffered I/O; but this driver | |
32 | * doesn't (yet) use these for any kind of i/o overlap or prefetching. | |
33 | * | |
34 | * Sometimes DataFlash is packaged in MMC-format cards, although the | |
8c64038e | 35 | * MMC stack can't (yet?) distinguish between MMC and DataFlash |
1d6432fe DB |
36 | * protocols during enumeration. |
37 | */ | |
38 | ||
1d6432fe DB |
39 | /* reads can bypass the buffers */ |
40 | #define OP_READ_CONTINUOUS 0xE8 | |
41 | #define OP_READ_PAGE 0xD2 | |
42 | ||
43 | /* group B requests can run even while status reports "busy" */ | |
44 | #define OP_READ_STATUS 0xD7 /* group B */ | |
45 | ||
46 | /* move data between host and buffer */ | |
47 | #define OP_READ_BUFFER1 0xD4 /* group B */ | |
48 | #define OP_READ_BUFFER2 0xD6 /* group B */ | |
49 | #define OP_WRITE_BUFFER1 0x84 /* group B */ | |
50 | #define OP_WRITE_BUFFER2 0x87 /* group B */ | |
51 | ||
52 | /* erasing flash */ | |
53 | #define OP_ERASE_PAGE 0x81 | |
54 | #define OP_ERASE_BLOCK 0x50 | |
55 | ||
56 | /* move data between buffer and flash */ | |
57 | #define OP_TRANSFER_BUF1 0x53 | |
58 | #define OP_TRANSFER_BUF2 0x55 | |
59 | #define OP_MREAD_BUFFER1 0xD4 | |
60 | #define OP_MREAD_BUFFER2 0xD6 | |
61 | #define OP_MWERASE_BUFFER1 0x83 | |
62 | #define OP_MWERASE_BUFFER2 0x86 | |
63 | #define OP_MWRITE_BUFFER1 0x88 /* sector must be pre-erased */ | |
64 | #define OP_MWRITE_BUFFER2 0x89 /* sector must be pre-erased */ | |
65 | ||
66 | /* write to buffer, then write-erase to flash */ | |
67 | #define OP_PROGRAM_VIA_BUF1 0x82 | |
68 | #define OP_PROGRAM_VIA_BUF2 0x85 | |
69 | ||
70 | /* compare buffer to flash */ | |
71 | #define OP_COMPARE_BUF1 0x60 | |
72 | #define OP_COMPARE_BUF2 0x61 | |
73 | ||
74 | /* read flash to buffer, then write-erase to flash */ | |
75 | #define OP_REWRITE_VIA_BUF1 0x58 | |
76 | #define OP_REWRITE_VIA_BUF2 0x59 | |
77 | ||
78 | /* newer chips report JEDEC manufacturer and device IDs; chip | |
79 | * serial number and OTP bits; and per-sector writeprotect. | |
80 | */ | |
81 | #define OP_READ_ID 0x9F | |
82 | #define OP_READ_SECURITY 0x77 | |
34a82443 DB |
83 | #define OP_WRITE_SECURITY_REVC 0x9A |
84 | #define OP_WRITE_SECURITY 0x9B /* revision D */ | |
1d6432fe DB |
85 | |
86 | ||
87 | struct dataflash { | |
271c5c59 | 88 | uint8_t command[4]; |
1d6432fe DB |
89 | char name[24]; |
90 | ||
91 | unsigned partitioned:1; | |
92 | ||
93 | unsigned short page_offset; /* offset in flash address */ | |
94 | unsigned int page_size; /* of bytes per page */ | |
95 | ||
ec9ce52e | 96 | struct mutex lock; |
1d6432fe DB |
97 | struct spi_device *spi; |
98 | ||
99 | struct mtd_info mtd; | |
100 | }; | |
101 | ||
b94e757c SG |
102 | #ifdef CONFIG_OF |
103 | static const struct of_device_id dataflash_dt_ids[] = { | |
104 | { .compatible = "atmel,at45", }, | |
105 | { .compatible = "atmel,dataflash", }, | |
106 | { /* sentinel */ } | |
107 | }; | |
b94e757c SG |
108 | #endif |
109 | ||
1d6432fe DB |
110 | /* ......................................................................... */ |
111 | ||
112 | /* | |
113 | * Return the status of the DataFlash device. | |
114 | */ | |
115 | static inline int dataflash_status(struct spi_device *spi) | |
116 | { | |
117 | /* NOTE: at45db321c over 25 MHz wants to write | |
118 | * a dummy byte after the opcode... | |
119 | */ | |
120 | return spi_w8r8(spi, OP_READ_STATUS); | |
121 | } | |
122 | ||
123 | /* | |
124 | * Poll the DataFlash device until it is READY. | |
125 | * This usually takes 5-20 msec or so; more for sector erase. | |
126 | */ | |
127 | static int dataflash_waitready(struct spi_device *spi) | |
128 | { | |
129 | int status; | |
130 | ||
131 | for (;;) { | |
132 | status = dataflash_status(spi); | |
133 | if (status < 0) { | |
289c0522 | 134 | pr_debug("%s: status %d?\n", |
160bbab3 | 135 | dev_name(&spi->dev), status); |
1d6432fe DB |
136 | status = 0; |
137 | } | |
138 | ||
139 | if (status & (1 << 7)) /* RDY/nBSY */ | |
140 | return status; | |
141 | ||
142 | msleep(3); | |
143 | } | |
144 | } | |
145 | ||
146 | /* ......................................................................... */ | |
147 | ||
148 | /* | |
149 | * Erase pages of flash. | |
150 | */ | |
151 | static int dataflash_erase(struct mtd_info *mtd, struct erase_info *instr) | |
152 | { | |
42845d2a | 153 | struct dataflash *priv = mtd->priv; |
1d6432fe | 154 | struct spi_device *spi = priv->spi; |
8275c642 | 155 | struct spi_transfer x = { .tx_dma = 0, }; |
1d6432fe DB |
156 | struct spi_message msg; |
157 | unsigned blocksize = priv->page_size << 3; | |
271c5c59 | 158 | uint8_t *command; |
5b7f3a50 | 159 | uint32_t rem; |
1d6432fe | 160 | |
289c0522 | 161 | pr_debug("%s: erase addr=0x%llx len 0x%llx\n", |
160bbab3 KS |
162 | dev_name(&spi->dev), (long long)instr->addr, |
163 | (long long)instr->len); | |
1d6432fe | 164 | |
5b7f3a50 AB |
165 | div_u64_rem(instr->len, priv->page_size, &rem); |
166 | if (rem) | |
167 | return -EINVAL; | |
168 | div_u64_rem(instr->addr, priv->page_size, &rem); | |
169 | if (rem) | |
1d6432fe DB |
170 | return -EINVAL; |
171 | ||
8275c642 VW |
172 | spi_message_init(&msg); |
173 | ||
174 | x.tx_buf = command = priv->command; | |
175 | x.len = 4; | |
176 | spi_message_add_tail(&x, &msg); | |
1d6432fe | 177 | |
ec9ce52e | 178 | mutex_lock(&priv->lock); |
1d6432fe DB |
179 | while (instr->len > 0) { |
180 | unsigned int pageaddr; | |
181 | int status; | |
182 | int do_block; | |
183 | ||
184 | /* Calculate flash page address; use block erase (for speed) if | |
185 | * we're at a block boundary and need to erase the whole block. | |
186 | */ | |
dbf8c11f | 187 | pageaddr = div_u64(instr->addr, priv->page_size); |
3cb4f09f | 188 | do_block = (pageaddr & 0x7) == 0 && instr->len >= blocksize; |
1d6432fe DB |
189 | pageaddr = pageaddr << priv->page_offset; |
190 | ||
191 | command[0] = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE; | |
271c5c59 DW |
192 | command[1] = (uint8_t)(pageaddr >> 16); |
193 | command[2] = (uint8_t)(pageaddr >> 8); | |
1d6432fe DB |
194 | command[3] = 0; |
195 | ||
289c0522 | 196 | pr_debug("ERASE %s: (%x) %x %x %x [%i]\n", |
1d6432fe DB |
197 | do_block ? "block" : "page", |
198 | command[0], command[1], command[2], command[3], | |
199 | pageaddr); | |
200 | ||
201 | status = spi_sync(spi, &msg); | |
202 | (void) dataflash_waitready(spi); | |
203 | ||
204 | if (status < 0) { | |
205 | printk(KERN_ERR "%s: erase %x, err %d\n", | |
160bbab3 | 206 | dev_name(&spi->dev), pageaddr, status); |
1d6432fe DB |
207 | /* REVISIT: can retry instr->retries times; or |
208 | * giveup and instr->fail_addr = instr->addr; | |
209 | */ | |
210 | continue; | |
211 | } | |
212 | ||
213 | if (do_block) { | |
214 | instr->addr += blocksize; | |
215 | instr->len -= blocksize; | |
216 | } else { | |
217 | instr->addr += priv->page_size; | |
218 | instr->len -= priv->page_size; | |
219 | } | |
220 | } | |
ec9ce52e | 221 | mutex_unlock(&priv->lock); |
1d6432fe DB |
222 | |
223 | /* Inform MTD subsystem that erase is complete */ | |
224 | instr->state = MTD_ERASE_DONE; | |
225 | mtd_erase_callback(instr); | |
226 | ||
227 | return 0; | |
228 | } | |
229 | ||
230 | /* | |
231 | * Read from the DataFlash device. | |
232 | * from : Start offset in flash device | |
233 | * len : Amount to read | |
234 | * retlen : About of data actually read | |
235 | * buf : Buffer containing the data | |
236 | */ | |
237 | static int dataflash_read(struct mtd_info *mtd, loff_t from, size_t len, | |
238 | size_t *retlen, u_char *buf) | |
239 | { | |
42845d2a | 240 | struct dataflash *priv = mtd->priv; |
1d6432fe DB |
241 | struct spi_transfer x[2] = { { .tx_dma = 0, }, }; |
242 | struct spi_message msg; | |
243 | unsigned int addr; | |
271c5c59 | 244 | uint8_t *command; |
1d6432fe DB |
245 | int status; |
246 | ||
0a32a102 BN |
247 | pr_debug("%s: read 0x%x..0x%x\n", dev_name(&priv->spi->dev), |
248 | (unsigned)from, (unsigned)(from + len)); | |
1d6432fe | 249 | |
1d6432fe DB |
250 | /* Calculate flash page/byte address */ |
251 | addr = (((unsigned)from / priv->page_size) << priv->page_offset) | |
252 | + ((unsigned)from % priv->page_size); | |
253 | ||
254 | command = priv->command; | |
255 | ||
289c0522 | 256 | pr_debug("READ: (%x) %x %x %x\n", |
1d6432fe DB |
257 | command[0], command[1], command[2], command[3]); |
258 | ||
8275c642 VW |
259 | spi_message_init(&msg); |
260 | ||
1d6432fe DB |
261 | x[0].tx_buf = command; |
262 | x[0].len = 8; | |
8275c642 VW |
263 | spi_message_add_tail(&x[0], &msg); |
264 | ||
1d6432fe DB |
265 | x[1].rx_buf = buf; |
266 | x[1].len = len; | |
8275c642 | 267 | spi_message_add_tail(&x[1], &msg); |
1d6432fe | 268 | |
ec9ce52e | 269 | mutex_lock(&priv->lock); |
1d6432fe DB |
270 | |
271 | /* Continuous read, max clock = f(car) which may be less than | |
272 | * the peak rate available. Some chips support commands with | |
273 | * fewer "don't care" bytes. Both buffers stay unchanged. | |
274 | */ | |
275 | command[0] = OP_READ_CONTINUOUS; | |
271c5c59 DW |
276 | command[1] = (uint8_t)(addr >> 16); |
277 | command[2] = (uint8_t)(addr >> 8); | |
278 | command[3] = (uint8_t)(addr >> 0); | |
1d6432fe DB |
279 | /* plus 4 "don't care" bytes */ |
280 | ||
281 | status = spi_sync(priv->spi, &msg); | |
ec9ce52e | 282 | mutex_unlock(&priv->lock); |
1d6432fe DB |
283 | |
284 | if (status >= 0) { | |
285 | *retlen = msg.actual_length - 8; | |
286 | status = 0; | |
287 | } else | |
289c0522 | 288 | pr_debug("%s: read %x..%x --> %d\n", |
160bbab3 | 289 | dev_name(&priv->spi->dev), |
1d6432fe DB |
290 | (unsigned)from, (unsigned)(from + len), |
291 | status); | |
292 | return status; | |
293 | } | |
294 | ||
295 | /* | |
296 | * Write to the DataFlash device. | |
297 | * to : Start offset in flash device | |
298 | * len : Amount to write | |
299 | * retlen : Amount of data actually written | |
300 | * buf : Buffer containing the data | |
301 | */ | |
302 | static int dataflash_write(struct mtd_info *mtd, loff_t to, size_t len, | |
303 | size_t * retlen, const u_char * buf) | |
304 | { | |
42845d2a | 305 | struct dataflash *priv = mtd->priv; |
1d6432fe DB |
306 | struct spi_device *spi = priv->spi; |
307 | struct spi_transfer x[2] = { { .tx_dma = 0, }, }; | |
308 | struct spi_message msg; | |
309 | unsigned int pageaddr, addr, offset, writelen; | |
310 | size_t remaining = len; | |
311 | u_char *writebuf = (u_char *) buf; | |
312 | int status = -EINVAL; | |
271c5c59 | 313 | uint8_t *command; |
1d6432fe | 314 | |
289c0522 | 315 | pr_debug("%s: write 0x%x..0x%x\n", |
160bbab3 | 316 | dev_name(&spi->dev), (unsigned)to, (unsigned)(to + len)); |
1d6432fe | 317 | |
8275c642 VW |
318 | spi_message_init(&msg); |
319 | ||
1d6432fe DB |
320 | x[0].tx_buf = command = priv->command; |
321 | x[0].len = 4; | |
8275c642 | 322 | spi_message_add_tail(&x[0], &msg); |
1d6432fe DB |
323 | |
324 | pageaddr = ((unsigned)to / priv->page_size); | |
325 | offset = ((unsigned)to % priv->page_size); | |
326 | if (offset + len > priv->page_size) | |
327 | writelen = priv->page_size - offset; | |
328 | else | |
329 | writelen = len; | |
330 | ||
ec9ce52e | 331 | mutex_lock(&priv->lock); |
1d6432fe | 332 | while (remaining > 0) { |
289c0522 | 333 | pr_debug("write @ %i:%i len=%i\n", |
1d6432fe DB |
334 | pageaddr, offset, writelen); |
335 | ||
336 | /* REVISIT: | |
337 | * (a) each page in a sector must be rewritten at least | |
338 | * once every 10K sibling erase/program operations. | |
339 | * (b) for pages that are already erased, we could | |
340 | * use WRITE+MWRITE not PROGRAM for ~30% speedup. | |
341 | * (c) WRITE to buffer could be done while waiting for | |
342 | * a previous MWRITE/MWERASE to complete ... | |
343 | * (d) error handling here seems to be mostly missing. | |
344 | * | |
345 | * Two persistent bits per page, plus a per-sector counter, | |
346 | * could support (a) and (b) ... we might consider using | |
347 | * the second half of sector zero, which is just one block, | |
348 | * to track that state. (On AT91, that sector should also | |
349 | * support boot-from-DataFlash.) | |
350 | */ | |
351 | ||
352 | addr = pageaddr << priv->page_offset; | |
353 | ||
354 | /* (1) Maybe transfer partial page to Buffer1 */ | |
355 | if (writelen != priv->page_size) { | |
356 | command[0] = OP_TRANSFER_BUF1; | |
357 | command[1] = (addr & 0x00FF0000) >> 16; | |
358 | command[2] = (addr & 0x0000FF00) >> 8; | |
359 | command[3] = 0; | |
360 | ||
289c0522 | 361 | pr_debug("TRANSFER: (%x) %x %x %x\n", |
1d6432fe DB |
362 | command[0], command[1], command[2], command[3]); |
363 | ||
1d6432fe DB |
364 | status = spi_sync(spi, &msg); |
365 | if (status < 0) | |
0a32a102 | 366 | pr_debug("%s: xfer %u -> %d\n", |
160bbab3 | 367 | dev_name(&spi->dev), addr, status); |
1d6432fe DB |
368 | |
369 | (void) dataflash_waitready(priv->spi); | |
370 | } | |
371 | ||
372 | /* (2) Program full page via Buffer1 */ | |
373 | addr += offset; | |
374 | command[0] = OP_PROGRAM_VIA_BUF1; | |
375 | command[1] = (addr & 0x00FF0000) >> 16; | |
376 | command[2] = (addr & 0x0000FF00) >> 8; | |
377 | command[3] = (addr & 0x000000FF); | |
378 | ||
289c0522 | 379 | pr_debug("PROGRAM: (%x) %x %x %x\n", |
1d6432fe DB |
380 | command[0], command[1], command[2], command[3]); |
381 | ||
382 | x[1].tx_buf = writebuf; | |
383 | x[1].len = writelen; | |
8275c642 | 384 | spi_message_add_tail(x + 1, &msg); |
1d6432fe | 385 | status = spi_sync(spi, &msg); |
8275c642 | 386 | spi_transfer_del(x + 1); |
1d6432fe | 387 | if (status < 0) |
0a32a102 | 388 | pr_debug("%s: pgm %u/%u -> %d\n", |
160bbab3 | 389 | dev_name(&spi->dev), addr, writelen, status); |
1d6432fe DB |
390 | |
391 | (void) dataflash_waitready(priv->spi); | |
392 | ||
8275c642 | 393 | |
05dd1807 | 394 | #ifdef CONFIG_MTD_DATAFLASH_WRITE_VERIFY |
1d6432fe DB |
395 | |
396 | /* (3) Compare to Buffer1 */ | |
397 | addr = pageaddr << priv->page_offset; | |
398 | command[0] = OP_COMPARE_BUF1; | |
399 | command[1] = (addr & 0x00FF0000) >> 16; | |
400 | command[2] = (addr & 0x0000FF00) >> 8; | |
401 | command[3] = 0; | |
402 | ||
289c0522 | 403 | pr_debug("COMPARE: (%x) %x %x %x\n", |
1d6432fe DB |
404 | command[0], command[1], command[2], command[3]); |
405 | ||
1d6432fe DB |
406 | status = spi_sync(spi, &msg); |
407 | if (status < 0) | |
0a32a102 | 408 | pr_debug("%s: compare %u -> %d\n", |
160bbab3 | 409 | dev_name(&spi->dev), addr, status); |
1d6432fe DB |
410 | |
411 | status = dataflash_waitready(priv->spi); | |
412 | ||
413 | /* Check result of the compare operation */ | |
cccb45d4 | 414 | if (status & (1 << 6)) { |
1d6432fe | 415 | printk(KERN_ERR "%s: compare page %u, err %d\n", |
160bbab3 | 416 | dev_name(&spi->dev), pageaddr, status); |
1d6432fe DB |
417 | remaining = 0; |
418 | status = -EIO; | |
419 | break; | |
420 | } else | |
421 | status = 0; | |
422 | ||
05dd1807 | 423 | #endif /* CONFIG_MTD_DATAFLASH_WRITE_VERIFY */ |
1d6432fe DB |
424 | |
425 | remaining = remaining - writelen; | |
426 | pageaddr++; | |
427 | offset = 0; | |
428 | writebuf += writelen; | |
429 | *retlen += writelen; | |
430 | ||
431 | if (remaining > priv->page_size) | |
432 | writelen = priv->page_size; | |
433 | else | |
434 | writelen = remaining; | |
435 | } | |
ec9ce52e | 436 | mutex_unlock(&priv->lock); |
1d6432fe DB |
437 | |
438 | return status; | |
439 | } | |
440 | ||
441 | /* ......................................................................... */ | |
442 | ||
34a82443 DB |
443 | #ifdef CONFIG_MTD_DATAFLASH_OTP |
444 | ||
445 | static int dataflash_get_otp_info(struct mtd_info *mtd, | |
446 | struct otp_info *info, size_t len) | |
447 | { | |
448 | /* Report both blocks as identical: bytes 0..64, locked. | |
449 | * Unless the user block changed from all-ones, we can't | |
450 | * tell whether it's still writable; so we assume it isn't. | |
451 | */ | |
452 | info->start = 0; | |
453 | info->length = 64; | |
454 | info->locked = 1; | |
455 | return sizeof(*info); | |
456 | } | |
457 | ||
458 | static ssize_t otp_read(struct spi_device *spi, unsigned base, | |
459 | uint8_t *buf, loff_t off, size_t len) | |
460 | { | |
461 | struct spi_message m; | |
462 | size_t l; | |
463 | uint8_t *scratch; | |
464 | struct spi_transfer t; | |
465 | int status; | |
466 | ||
467 | if (off > 64) | |
468 | return -EINVAL; | |
469 | ||
470 | if ((off + len) > 64) | |
471 | len = 64 - off; | |
34a82443 DB |
472 | |
473 | spi_message_init(&m); | |
474 | ||
475 | l = 4 + base + off + len; | |
476 | scratch = kzalloc(l, GFP_KERNEL); | |
477 | if (!scratch) | |
478 | return -ENOMEM; | |
479 | ||
480 | /* OUT: OP_READ_SECURITY, 3 don't-care bytes, zeroes | |
481 | * IN: ignore 4 bytes, data bytes 0..N (max 127) | |
482 | */ | |
483 | scratch[0] = OP_READ_SECURITY; | |
484 | ||
485 | memset(&t, 0, sizeof t); | |
486 | t.tx_buf = scratch; | |
487 | t.rx_buf = scratch; | |
488 | t.len = l; | |
489 | spi_message_add_tail(&t, &m); | |
490 | ||
491 | dataflash_waitready(spi); | |
492 | ||
493 | status = spi_sync(spi, &m); | |
494 | if (status >= 0) { | |
495 | memcpy(buf, scratch + 4 + base + off, len); | |
496 | status = len; | |
497 | } | |
498 | ||
499 | kfree(scratch); | |
500 | return status; | |
501 | } | |
502 | ||
503 | static int dataflash_read_fact_otp(struct mtd_info *mtd, | |
504 | loff_t from, size_t len, size_t *retlen, u_char *buf) | |
505 | { | |
42845d2a | 506 | struct dataflash *priv = mtd->priv; |
34a82443 DB |
507 | int status; |
508 | ||
509 | /* 64 bytes, from 0..63 ... start at 64 on-chip */ | |
510 | mutex_lock(&priv->lock); | |
511 | status = otp_read(priv->spi, 64, buf, from, len); | |
512 | mutex_unlock(&priv->lock); | |
513 | ||
514 | if (status < 0) | |
515 | return status; | |
516 | *retlen = status; | |
517 | return 0; | |
518 | } | |
519 | ||
520 | static int dataflash_read_user_otp(struct mtd_info *mtd, | |
521 | loff_t from, size_t len, size_t *retlen, u_char *buf) | |
522 | { | |
42845d2a | 523 | struct dataflash *priv = mtd->priv; |
34a82443 DB |
524 | int status; |
525 | ||
526 | /* 64 bytes, from 0..63 ... start at 0 on-chip */ | |
527 | mutex_lock(&priv->lock); | |
528 | status = otp_read(priv->spi, 0, buf, from, len); | |
529 | mutex_unlock(&priv->lock); | |
530 | ||
531 | if (status < 0) | |
532 | return status; | |
533 | *retlen = status; | |
534 | return 0; | |
535 | } | |
536 | ||
537 | static int dataflash_write_user_otp(struct mtd_info *mtd, | |
538 | loff_t from, size_t len, size_t *retlen, u_char *buf) | |
539 | { | |
540 | struct spi_message m; | |
541 | const size_t l = 4 + 64; | |
542 | uint8_t *scratch; | |
543 | struct spi_transfer t; | |
42845d2a | 544 | struct dataflash *priv = mtd->priv; |
34a82443 DB |
545 | int status; |
546 | ||
547 | if (len > 64) | |
548 | return -EINVAL; | |
549 | ||
550 | /* Strictly speaking, we *could* truncate the write ... but | |
551 | * let's not do that for the only write that's ever possible. | |
552 | */ | |
553 | if ((from + len) > 64) | |
554 | return -EINVAL; | |
555 | ||
556 | /* OUT: OP_WRITE_SECURITY, 3 zeroes, 64 data-or-zero bytes | |
557 | * IN: ignore all | |
558 | */ | |
559 | scratch = kzalloc(l, GFP_KERNEL); | |
560 | if (!scratch) | |
561 | return -ENOMEM; | |
562 | scratch[0] = OP_WRITE_SECURITY; | |
563 | memcpy(scratch + 4 + from, buf, len); | |
564 | ||
565 | spi_message_init(&m); | |
566 | ||
567 | memset(&t, 0, sizeof t); | |
568 | t.tx_buf = scratch; | |
569 | t.len = l; | |
570 | spi_message_add_tail(&t, &m); | |
571 | ||
572 | /* Write the OTP bits, if they've not yet been written. | |
573 | * This modifies SRAM buffer1. | |
574 | */ | |
575 | mutex_lock(&priv->lock); | |
576 | dataflash_waitready(priv->spi); | |
577 | status = spi_sync(priv->spi, &m); | |
578 | mutex_unlock(&priv->lock); | |
579 | ||
580 | kfree(scratch); | |
581 | ||
582 | if (status >= 0) { | |
583 | status = 0; | |
584 | *retlen = len; | |
585 | } | |
586 | return status; | |
587 | } | |
588 | ||
589 | static char *otp_setup(struct mtd_info *device, char revision) | |
590 | { | |
3c3c10bb AB |
591 | device->_get_fact_prot_info = dataflash_get_otp_info; |
592 | device->_read_fact_prot_reg = dataflash_read_fact_otp; | |
593 | device->_get_user_prot_info = dataflash_get_otp_info; | |
594 | device->_read_user_prot_reg = dataflash_read_user_otp; | |
34a82443 DB |
595 | |
596 | /* rev c parts (at45db321c and at45db1281 only!) use a | |
597 | * different write procedure; not (yet?) implemented. | |
598 | */ | |
599 | if (revision > 'c') | |
3c3c10bb | 600 | device->_write_user_prot_reg = dataflash_write_user_otp; |
34a82443 DB |
601 | |
602 | return ", OTP"; | |
603 | } | |
604 | ||
605 | #else | |
606 | ||
cf93ae02 | 607 | static char *otp_setup(struct mtd_info *device, char revision) |
34a82443 DB |
608 | { |
609 | return " (OTP)"; | |
610 | } | |
611 | ||
612 | #endif | |
613 | ||
614 | /* ......................................................................... */ | |
615 | ||
1d6432fe DB |
616 | /* |
617 | * Register DataFlash device with MTD subsystem. | |
618 | */ | |
d8929942 GKH |
619 | static int add_dataflash_otp(struct spi_device *spi, char *name, int nr_pages, |
620 | int pagesize, int pageoffset, char revision) | |
1d6432fe DB |
621 | { |
622 | struct dataflash *priv; | |
623 | struct mtd_info *device; | |
b94e757c | 624 | struct mtd_part_parser_data ppdata; |
0278fd3f | 625 | struct flash_platform_data *pdata = dev_get_platdata(&spi->dev); |
34a82443 | 626 | char *otp_tag = ""; |
d4702669 | 627 | int err = 0; |
1d6432fe | 628 | |
5cbded58 | 629 | priv = kzalloc(sizeof *priv, GFP_KERNEL); |
1d6432fe DB |
630 | if (!priv) |
631 | return -ENOMEM; | |
632 | ||
ec9ce52e | 633 | mutex_init(&priv->lock); |
1d6432fe DB |
634 | priv->spi = spi; |
635 | priv->page_size = pagesize; | |
636 | priv->page_offset = pageoffset; | |
637 | ||
638 | /* name must be usable with cmdlinepart */ | |
639 | sprintf(priv->name, "spi%d.%d-%s", | |
640 | spi->master->bus_num, spi->chip_select, | |
641 | name); | |
642 | ||
643 | device = &priv->mtd; | |
644 | device->name = (pdata && pdata->name) ? pdata->name : priv->name; | |
645 | device->size = nr_pages * pagesize; | |
646 | device->erasesize = pagesize; | |
17ffc7ba | 647 | device->writesize = pagesize; |
1d6432fe DB |
648 | device->owner = THIS_MODULE; |
649 | device->type = MTD_DATAFLASH; | |
6c33cafc | 650 | device->flags = MTD_WRITEABLE; |
3c3c10bb AB |
651 | device->_erase = dataflash_erase; |
652 | device->_read = dataflash_read; | |
653 | device->_write = dataflash_write; | |
1d6432fe DB |
654 | device->priv = priv; |
655 | ||
87f39f04 DB |
656 | device->dev.parent = &spi->dev; |
657 | ||
34a82443 DB |
658 | if (revision >= 'c') |
659 | otp_tag = otp_setup(device, revision); | |
660 | ||
5b7f3a50 AB |
661 | dev_info(&spi->dev, "%s (%lld KBytes) pagesize %d bytes%s\n", |
662 | name, (long long)((device->size + 1023) >> 10), | |
34a82443 | 663 | pagesize, otp_tag); |
5cacbfa9 | 664 | spi_set_drvdata(spi, priv); |
1d6432fe | 665 | |
b94e757c SG |
666 | ppdata.of_node = spi->dev.of_node; |
667 | err = mtd_device_parse_register(device, NULL, &ppdata, | |
3a8fb12a DES |
668 | pdata ? pdata->parts : NULL, |
669 | pdata ? pdata->nr_parts : 0); | |
1d6432fe | 670 | |
d4702669 HS |
671 | if (!err) |
672 | return 0; | |
673 | ||
5cacbfa9 | 674 | spi_set_drvdata(spi, NULL); |
d4702669 HS |
675 | kfree(priv); |
676 | return err; | |
1d6432fe DB |
677 | } |
678 | ||
d8929942 GKH |
679 | static inline int add_dataflash(struct spi_device *spi, char *name, |
680 | int nr_pages, int pagesize, int pageoffset) | |
34a82443 DB |
681 | { |
682 | return add_dataflash_otp(spi, name, nr_pages, pagesize, | |
683 | pageoffset, 0); | |
684 | } | |
685 | ||
e9d42227 MH |
686 | struct flash_info { |
687 | char *name; | |
688 | ||
771999b6 | 689 | /* JEDEC id has a high byte of zero plus three data bytes: |
690 | * the manufacturer id, then a two byte device id. | |
e9d42227 | 691 | */ |
271c5c59 | 692 | uint32_t jedec_id; |
e9d42227 | 693 | |
771999b6 | 694 | /* The size listed here is what works with OP_ERASE_PAGE. */ |
e9d42227 | 695 | unsigned nr_pages; |
271c5c59 DW |
696 | uint16_t pagesize; |
697 | uint16_t pageoffset; | |
e9d42227 | 698 | |
271c5c59 | 699 | uint16_t flags; |
771999b6 | 700 | #define SUP_POW2PS 0x0002 /* supports 2^N byte pages */ |
701 | #define IS_POW2PS 0x0001 /* uses 2^N byte pages */ | |
e9d42227 MH |
702 | }; |
703 | ||
7bf350b7 | 704 | static struct flash_info dataflash_data[] = { |
e9d42227 | 705 | |
771999b6 | 706 | /* |
707 | * NOTE: chips with SUP_POW2PS (rev D and up) need two entries, | |
708 | * one with IS_POW2PS and the other without. The entry with the | |
709 | * non-2^N byte page size can't name exact chip revisions without | |
710 | * losing backwards compatibility for cmdlinepart. | |
711 | * | |
712 | * These newer chips also support 128-byte security registers (with | |
713 | * 64 bytes one-time-programmable) and software write-protection. | |
714 | */ | |
715 | { "AT45DB011B", 0x1f2200, 512, 264, 9, SUP_POW2PS}, | |
e9d42227 MH |
716 | { "at45db011d", 0x1f2200, 512, 256, 8, SUP_POW2PS | IS_POW2PS}, |
717 | ||
771999b6 | 718 | { "AT45DB021B", 0x1f2300, 1024, 264, 9, SUP_POW2PS}, |
e9d42227 MH |
719 | { "at45db021d", 0x1f2300, 1024, 256, 8, SUP_POW2PS | IS_POW2PS}, |
720 | ||
771999b6 | 721 | { "AT45DB041x", 0x1f2400, 2048, 264, 9, SUP_POW2PS}, |
e9d42227 MH |
722 | { "at45db041d", 0x1f2400, 2048, 256, 8, SUP_POW2PS | IS_POW2PS}, |
723 | ||
771999b6 | 724 | { "AT45DB081B", 0x1f2500, 4096, 264, 9, SUP_POW2PS}, |
e9d42227 MH |
725 | { "at45db081d", 0x1f2500, 4096, 256, 8, SUP_POW2PS | IS_POW2PS}, |
726 | ||
771999b6 | 727 | { "AT45DB161x", 0x1f2600, 4096, 528, 10, SUP_POW2PS}, |
e9d42227 MH |
728 | { "at45db161d", 0x1f2600, 4096, 512, 9, SUP_POW2PS | IS_POW2PS}, |
729 | ||
771999b6 | 730 | { "AT45DB321x", 0x1f2700, 8192, 528, 10, 0}, /* rev C */ |
e9d42227 | 731 | |
771999b6 | 732 | { "AT45DB321x", 0x1f2701, 8192, 528, 10, SUP_POW2PS}, |
e9d42227 MH |
733 | { "at45db321d", 0x1f2701, 8192, 512, 9, SUP_POW2PS | IS_POW2PS}, |
734 | ||
771999b6 | 735 | { "AT45DB642x", 0x1f2800, 8192, 1056, 11, SUP_POW2PS}, |
736 | { "at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS}, | |
e9d42227 MH |
737 | }; |
738 | ||
06f25510 | 739 | static struct flash_info *jedec_probe(struct spi_device *spi) |
e9d42227 MH |
740 | { |
741 | int tmp; | |
271c5c59 DW |
742 | uint8_t code = OP_READ_ID; |
743 | uint8_t id[3]; | |
744 | uint32_t jedec; | |
e9d42227 MH |
745 | struct flash_info *info; |
746 | int status; | |
747 | ||
e9d42227 MH |
748 | /* JEDEC also defines an optional "extended device information" |
749 | * string for after vendor-specific data, after the three bytes | |
750 | * we use here. Supporting some chips might require using it. | |
771999b6 | 751 | * |
752 | * If the vendor ID isn't Atmel's (0x1f), assume this call failed. | |
753 | * That's not an error; only rev C and newer chips handle it, and | |
754 | * only Atmel sells these chips. | |
e9d42227 MH |
755 | */ |
756 | tmp = spi_write_then_read(spi, &code, 1, id, 3); | |
757 | if (tmp < 0) { | |
289c0522 | 758 | pr_debug("%s: error %d reading JEDEC ID\n", |
160bbab3 | 759 | dev_name(&spi->dev), tmp); |
771999b6 | 760 | return ERR_PTR(tmp); |
e9d42227 | 761 | } |
771999b6 | 762 | if (id[0] != 0x1f) |
763 | return NULL; | |
764 | ||
e9d42227 MH |
765 | jedec = id[0]; |
766 | jedec = jedec << 8; | |
767 | jedec |= id[1]; | |
768 | jedec = jedec << 8; | |
769 | jedec |= id[2]; | |
770 | ||
771 | for (tmp = 0, info = dataflash_data; | |
772 | tmp < ARRAY_SIZE(dataflash_data); | |
773 | tmp++, info++) { | |
774 | if (info->jedec_id == jedec) { | |
289c0522 | 775 | pr_debug("%s: OTP, sector protect%s\n", |
771999b6 | 776 | dev_name(&spi->dev), |
777 | (info->flags & SUP_POW2PS) | |
778 | ? ", binary pagesize" : "" | |
779 | ); | |
e9d42227 MH |
780 | if (info->flags & SUP_POW2PS) { |
781 | status = dataflash_status(spi); | |
771999b6 | 782 | if (status < 0) { |
289c0522 | 783 | pr_debug("%s: status error %d\n", |
771999b6 | 784 | dev_name(&spi->dev), status); |
785 | return ERR_PTR(status); | |
786 | } | |
787 | if (status & 0x1) { | |
788 | if (info->flags & IS_POW2PS) | |
789 | return info; | |
790 | } else { | |
791 | if (!(info->flags & IS_POW2PS)) | |
792 | return info; | |
793 | } | |
229cc58b WN |
794 | } else |
795 | return info; | |
e9d42227 MH |
796 | } |
797 | } | |
771999b6 | 798 | |
799 | /* | |
800 | * Treat other chips as errors ... we won't know the right page | |
801 | * size (it might be binary) even when we can tell which density | |
802 | * class is involved (legacy chip id scheme). | |
803 | */ | |
804 | dev_warn(&spi->dev, "JEDEC id %06x not handled\n", jedec); | |
805 | return ERR_PTR(-ENODEV); | |
e9d42227 MH |
806 | } |
807 | ||
771999b6 | 808 | /* |
809 | * Detect and initialize DataFlash device, using JEDEC IDs on newer chips | |
810 | * or else the ID code embedded in the status bits: | |
811 | * | |
812 | * Device Density ID code #Pages PageSize Offset | |
813 | * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9 | |
814 | * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1024 264 9 | |
815 | * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9 | |
816 | * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9 | |
817 | * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10 | |
818 | * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10 | |
819 | * AT45DB0642 64Mbit (8M) xx111xxx (0x3c) 8192 1056 11 | |
820 | * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11 | |
821 | */ | |
06f25510 | 822 | static int dataflash_probe(struct spi_device *spi) |
1d6432fe DB |
823 | { |
824 | int status; | |
e9d42227 MH |
825 | struct flash_info *info; |
826 | ||
827 | /* | |
828 | * Try to detect dataflash by JEDEC ID. | |
829 | * If it succeeds we know we have either a C or D part. | |
830 | * D will support power of 2 pagesize option. | |
34a82443 DB |
831 | * Both support the security register, though with different |
832 | * write procedures. | |
e9d42227 | 833 | */ |
e9d42227 | 834 | info = jedec_probe(spi); |
771999b6 | 835 | if (IS_ERR(info)) |
836 | return PTR_ERR(info); | |
e9d42227 | 837 | if (info != NULL) |
34a82443 DB |
838 | return add_dataflash_otp(spi, info->name, info->nr_pages, |
839 | info->pagesize, info->pageoffset, | |
840 | (info->flags & SUP_POW2PS) ? 'd' : 'c'); | |
e9d42227 | 841 | |
771999b6 | 842 | /* |
843 | * Older chips support only legacy commands, identifing | |
844 | * capacity using bits in the status byte. | |
845 | */ | |
1d6432fe DB |
846 | status = dataflash_status(spi); |
847 | if (status <= 0 || status == 0xff) { | |
289c0522 | 848 | pr_debug("%s: status error %d\n", |
160bbab3 | 849 | dev_name(&spi->dev), status); |
de4fa992 | 850 | if (status == 0 || status == 0xff) |
1d6432fe DB |
851 | status = -ENODEV; |
852 | return status; | |
853 | } | |
854 | ||
855 | /* if there's a device there, assume it's dataflash. | |
856 | * board setup should have set spi->max_speed_max to | |
857 | * match f(car) for continuous reads, mode 0 or 3. | |
858 | */ | |
859 | switch (status & 0x3c) { | |
860 | case 0x0c: /* 0 0 1 1 x x */ | |
861 | status = add_dataflash(spi, "AT45DB011B", 512, 264, 9); | |
862 | break; | |
863 | case 0x14: /* 0 1 0 1 x x */ | |
e9d42227 | 864 | status = add_dataflash(spi, "AT45DB021B", 1024, 264, 9); |
1d6432fe DB |
865 | break; |
866 | case 0x1c: /* 0 1 1 1 x x */ | |
771999b6 | 867 | status = add_dataflash(spi, "AT45DB041x", 2048, 264, 9); |
1d6432fe DB |
868 | break; |
869 | case 0x24: /* 1 0 0 1 x x */ | |
870 | status = add_dataflash(spi, "AT45DB081B", 4096, 264, 9); | |
871 | break; | |
872 | case 0x2c: /* 1 0 1 1 x x */ | |
771999b6 | 873 | status = add_dataflash(spi, "AT45DB161x", 4096, 528, 10); |
1d6432fe DB |
874 | break; |
875 | case 0x34: /* 1 1 0 1 x x */ | |
876 | status = add_dataflash(spi, "AT45DB321x", 8192, 528, 10); | |
877 | break; | |
878 | case 0x38: /* 1 1 1 x x x */ | |
879 | case 0x3c: | |
880 | status = add_dataflash(spi, "AT45DB642x", 8192, 1056, 11); | |
881 | break; | |
882 | /* obsolete AT45DB1282 not (yet?) supported */ | |
883 | default: | |
0a32a102 BN |
884 | pr_debug("%s: unsupported device (%x)\n", dev_name(&spi->dev), |
885 | status & 0x3c); | |
1d6432fe DB |
886 | status = -ENODEV; |
887 | } | |
888 | ||
889 | if (status < 0) | |
0a32a102 BN |
890 | pr_debug("%s: add_dataflash --> %d\n", dev_name(&spi->dev), |
891 | status); | |
1d6432fe DB |
892 | |
893 | return status; | |
894 | } | |
895 | ||
810b7e06 | 896 | static int dataflash_remove(struct spi_device *spi) |
1d6432fe | 897 | { |
5cacbfa9 | 898 | struct dataflash *flash = spi_get_drvdata(spi); |
1d6432fe DB |
899 | int status; |
900 | ||
289c0522 | 901 | pr_debug("%s: remove\n", dev_name(&spi->dev)); |
1d6432fe | 902 | |
436c06da | 903 | status = mtd_device_unregister(&flash->mtd); |
d4702669 | 904 | if (status == 0) { |
5cacbfa9 | 905 | spi_set_drvdata(spi, NULL); |
1d6432fe | 906 | kfree(flash); |
d4702669 | 907 | } |
1d6432fe DB |
908 | return status; |
909 | } | |
910 | ||
911 | static struct spi_driver dataflash_driver = { | |
912 | .driver = { | |
913 | .name = "mtd_dataflash", | |
1d6432fe | 914 | .owner = THIS_MODULE, |
19d69b86 | 915 | .of_match_table = of_match_ptr(dataflash_dt_ids), |
1d6432fe DB |
916 | }, |
917 | ||
918 | .probe = dataflash_probe, | |
5153b88c | 919 | .remove = dataflash_remove, |
1d6432fe DB |
920 | |
921 | /* FIXME: investigate suspend and resume... */ | |
922 | }; | |
923 | ||
c9d1b752 | 924 | module_spi_driver(dataflash_driver); |
1d6432fe DB |
925 | |
926 | MODULE_LICENSE("GPL"); | |
927 | MODULE_AUTHOR("Andrew Victor, David Brownell"); | |
928 | MODULE_DESCRIPTION("MTD DataFlash driver"); | |
e0626e38 | 929 | MODULE_ALIAS("spi:mtd_dataflash"); |