Commit | Line | Data |
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3d12c0c7 JM |
1 | /* |
2 | * drivers/mtd/nand/ams-delta.c | |
3 | * | |
4 | * Copyright (C) 2006 Jonathan McDowell <noodles@earth.li> | |
5 | * | |
6 | * Derived from drivers/mtd/toto.c | |
7e95d1f1 | 7 | * Converted to platform driver by Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> |
eaca491f | 8 | * Partially stolen from drivers/mtd/nand/plat_nand.c |
3d12c0c7 JM |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * Overview: | |
15 | * This is a device driver for the NAND flash device found on the | |
16 | * Amstrad E3 (Delta). | |
17 | */ | |
18 | ||
19 | #include <linux/slab.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/mtd/mtd.h> | |
24 | #include <linux/mtd/nand.h> | |
25 | #include <linux/mtd/partitions.h> | |
26 | #include <asm/io.h> | |
a09e64fb | 27 | #include <mach/hardware.h> |
3d12c0c7 | 28 | #include <asm/sizes.h> |
68f06766 | 29 | #include <linux/gpio.h> |
ce491cf8 | 30 | #include <plat/board-ams-delta.h> |
3d12c0c7 JM |
31 | |
32 | /* | |
33 | * MTD structure for E3 (Delta) | |
34 | */ | |
35 | static struct mtd_info *ams_delta_mtd = NULL; | |
36 | ||
3d12c0c7 JM |
37 | /* |
38 | * Define partitions for flash devices | |
39 | */ | |
40 | ||
41 | static struct mtd_partition partition_info[] = { | |
42 | { .name = "Kernel", | |
43 | .offset = 0, | |
44 | .size = 3 * SZ_1M + SZ_512K }, | |
45 | { .name = "u-boot", | |
46 | .offset = 3 * SZ_1M + SZ_512K, | |
47 | .size = SZ_256K }, | |
48 | { .name = "u-boot params", | |
49 | .offset = 3 * SZ_1M + SZ_512K + SZ_256K, | |
50 | .size = SZ_256K }, | |
51 | { .name = "Amstrad LDR", | |
52 | .offset = 4 * SZ_1M, | |
53 | .size = SZ_256K }, | |
54 | { .name = "File system", | |
55 | .offset = 4 * SZ_1M + 1 * SZ_256K, | |
56 | .size = 27 * SZ_1M }, | |
57 | { .name = "PBL reserved", | |
58 | .offset = 32 * SZ_1M - 3 * SZ_256K, | |
59 | .size = 3 * SZ_256K }, | |
60 | }; | |
61 | ||
3d12c0c7 JM |
62 | static void ams_delta_write_byte(struct mtd_info *mtd, u_char byte) |
63 | { | |
64 | struct nand_chip *this = mtd->priv; | |
eaca491f | 65 | void __iomem *io_base = this->priv; |
3d12c0c7 | 66 | |
eaca491f JK |
67 | writew(0, io_base + OMAP_MPUIO_IO_CNTL); |
68 | writew(byte, this->IO_ADDR_W); | |
68f06766 | 69 | gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 0); |
3d12c0c7 | 70 | ndelay(40); |
68f06766 | 71 | gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 1); |
3d12c0c7 JM |
72 | } |
73 | ||
74 | static u_char ams_delta_read_byte(struct mtd_info *mtd) | |
75 | { | |
76 | u_char res; | |
77 | struct nand_chip *this = mtd->priv; | |
eaca491f | 78 | void __iomem *io_base = this->priv; |
3d12c0c7 | 79 | |
68f06766 | 80 | gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NRE, 0); |
3d12c0c7 | 81 | ndelay(40); |
eaca491f JK |
82 | writew(~0, io_base + OMAP_MPUIO_IO_CNTL); |
83 | res = readw(this->IO_ADDR_R); | |
68f06766 | 84 | gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NRE, 1); |
3d12c0c7 JM |
85 | |
86 | return res; | |
87 | } | |
88 | ||
89 | static void ams_delta_write_buf(struct mtd_info *mtd, const u_char *buf, | |
90 | int len) | |
91 | { | |
92 | int i; | |
93 | ||
94 | for (i=0; i<len; i++) | |
95 | ams_delta_write_byte(mtd, buf[i]); | |
96 | } | |
97 | ||
98 | static void ams_delta_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
99 | { | |
100 | int i; | |
101 | ||
102 | for (i=0; i<len; i++) | |
103 | buf[i] = ams_delta_read_byte(mtd); | |
104 | } | |
105 | ||
106 | static int ams_delta_verify_buf(struct mtd_info *mtd, const u_char *buf, | |
107 | int len) | |
108 | { | |
109 | int i; | |
110 | ||
111 | for (i=0; i<len; i++) | |
112 | if (buf[i] != ams_delta_read_byte(mtd)) | |
113 | return -EFAULT; | |
114 | ||
115 | return 0; | |
116 | } | |
117 | ||
7abd3ef9 TG |
118 | /* |
119 | * Command control function | |
120 | * | |
121 | * ctrl: | |
122 | * NAND_NCE: bit 0 -> bit 2 | |
123 | * NAND_CLE: bit 1 -> bit 7 | |
124 | * NAND_ALE: bit 2 -> bit 6 | |
125 | */ | |
126 | static void ams_delta_hwcontrol(struct mtd_info *mtd, int cmd, | |
127 | unsigned int ctrl) | |
128 | { | |
129 | ||
130 | if (ctrl & NAND_CTRL_CHANGE) { | |
68f06766 JK |
131 | gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NCE, |
132 | (ctrl & NAND_NCE) == 0); | |
133 | gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_CLE, | |
134 | (ctrl & NAND_CLE) != 0); | |
135 | gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_ALE, | |
136 | (ctrl & NAND_ALE) != 0); | |
7abd3ef9 TG |
137 | } |
138 | ||
139 | if (cmd != NAND_CMD_NONE) | |
140 | ams_delta_write_byte(mtd, cmd); | |
141 | } | |
142 | ||
3d12c0c7 JM |
143 | static int ams_delta_nand_ready(struct mtd_info *mtd) |
144 | { | |
93a22f8b | 145 | return gpio_get_value(AMS_DELTA_GPIO_PIN_NAND_RB); |
3d12c0c7 JM |
146 | } |
147 | ||
da564a05 | 148 | static const struct gpio _mandatory_gpio[] = { |
68f06766 JK |
149 | { |
150 | .gpio = AMS_DELTA_GPIO_PIN_NAND_NCE, | |
151 | .flags = GPIOF_OUT_INIT_HIGH, | |
152 | .label = "nand_nce", | |
153 | }, | |
154 | { | |
155 | .gpio = AMS_DELTA_GPIO_PIN_NAND_NRE, | |
156 | .flags = GPIOF_OUT_INIT_HIGH, | |
157 | .label = "nand_nre", | |
158 | }, | |
159 | { | |
160 | .gpio = AMS_DELTA_GPIO_PIN_NAND_NWP, | |
161 | .flags = GPIOF_OUT_INIT_HIGH, | |
162 | .label = "nand_nwp", | |
163 | }, | |
164 | { | |
165 | .gpio = AMS_DELTA_GPIO_PIN_NAND_NWE, | |
166 | .flags = GPIOF_OUT_INIT_HIGH, | |
167 | .label = "nand_nwe", | |
168 | }, | |
169 | { | |
170 | .gpio = AMS_DELTA_GPIO_PIN_NAND_ALE, | |
171 | .flags = GPIOF_OUT_INIT_LOW, | |
172 | .label = "nand_ale", | |
173 | }, | |
174 | { | |
175 | .gpio = AMS_DELTA_GPIO_PIN_NAND_CLE, | |
176 | .flags = GPIOF_OUT_INIT_LOW, | |
177 | .label = "nand_cle", | |
178 | }, | |
179 | }; | |
180 | ||
3d12c0c7 JM |
181 | /* |
182 | * Main initialization routine | |
183 | */ | |
7e95d1f1 | 184 | static int __devinit ams_delta_init(struct platform_device *pdev) |
3d12c0c7 JM |
185 | { |
186 | struct nand_chip *this; | |
eaca491f JK |
187 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
188 | void __iomem *io_base; | |
3d12c0c7 JM |
189 | int err = 0; |
190 | ||
eaca491f JK |
191 | if (!res) |
192 | return -ENXIO; | |
193 | ||
3d12c0c7 JM |
194 | /* Allocate memory for MTD device structure and private data */ |
195 | ams_delta_mtd = kmalloc(sizeof(struct mtd_info) + | |
196 | sizeof(struct nand_chip), GFP_KERNEL); | |
197 | if (!ams_delta_mtd) { | |
198 | printk (KERN_WARNING "Unable to allocate E3 NAND MTD device structure.\n"); | |
199 | err = -ENOMEM; | |
200 | goto out; | |
201 | } | |
202 | ||
203 | ams_delta_mtd->owner = THIS_MODULE; | |
204 | ||
205 | /* Get pointer to private data */ | |
206 | this = (struct nand_chip *) (&ams_delta_mtd[1]); | |
207 | ||
208 | /* Initialize structures */ | |
209 | memset(ams_delta_mtd, 0, sizeof(struct mtd_info)); | |
210 | memset(this, 0, sizeof(struct nand_chip)); | |
211 | ||
212 | /* Link the private data with the MTD structure */ | |
213 | ams_delta_mtd->priv = this; | |
214 | ||
eaca491f JK |
215 | if (!request_mem_region(res->start, resource_size(res), |
216 | dev_name(&pdev->dev))) { | |
217 | dev_err(&pdev->dev, "request_mem_region failed\n"); | |
218 | err = -EBUSY; | |
219 | goto out_free; | |
220 | } | |
221 | ||
222 | io_base = ioremap(res->start, resource_size(res)); | |
223 | if (io_base == NULL) { | |
224 | dev_err(&pdev->dev, "ioremap failed\n"); | |
225 | err = -EIO; | |
226 | goto out_release_io; | |
227 | } | |
228 | ||
229 | this->priv = io_base; | |
230 | ||
3d12c0c7 | 231 | /* Set address of NAND IO lines */ |
eaca491f JK |
232 | this->IO_ADDR_R = io_base + OMAP_MPUIO_INPUT_LATCH; |
233 | this->IO_ADDR_W = io_base + OMAP_MPUIO_OUTPUT; | |
3d12c0c7 | 234 | this->read_byte = ams_delta_read_byte; |
3d12c0c7 JM |
235 | this->write_buf = ams_delta_write_buf; |
236 | this->read_buf = ams_delta_read_buf; | |
237 | this->verify_buf = ams_delta_verify_buf; | |
7abd3ef9 | 238 | this->cmd_ctrl = ams_delta_hwcontrol; |
93a22f8b | 239 | if (gpio_request(AMS_DELTA_GPIO_PIN_NAND_RB, "nand_rdy") == 0) { |
3d12c0c7 JM |
240 | this->dev_ready = ams_delta_nand_ready; |
241 | } else { | |
242 | this->dev_ready = NULL; | |
243 | printk(KERN_NOTICE "Couldn't request gpio for Delta NAND ready.\n"); | |
244 | } | |
245 | /* 25 us command delay time */ | |
246 | this->chip_delay = 30; | |
6dfc6d25 | 247 | this->ecc.mode = NAND_ECC_SOFT; |
3d12c0c7 | 248 | |
eaca491f JK |
249 | platform_set_drvdata(pdev, io_base); |
250 | ||
3d12c0c7 | 251 | /* Set chip enabled, but */ |
68f06766 JK |
252 | err = gpio_request_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio)); |
253 | if (err) | |
254 | goto out_gpio; | |
3d12c0c7 | 255 | |
25985edc | 256 | /* Scan to find existence of the device */ |
3d12c0c7 JM |
257 | if (nand_scan(ams_delta_mtd, 1)) { |
258 | err = -ENXIO; | |
259 | goto out_mtd; | |
260 | } | |
261 | ||
262 | /* Register the partitions */ | |
ee0e87b1 JI |
263 | mtd_device_register(ams_delta_mtd, partition_info, |
264 | ARRAY_SIZE(partition_info)); | |
3d12c0c7 JM |
265 | |
266 | goto out; | |
267 | ||
268 | out_mtd: | |
68f06766 JK |
269 | gpio_free_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio)); |
270 | out_gpio: | |
eaca491f | 271 | platform_set_drvdata(pdev, NULL); |
68f06766 | 272 | gpio_free(AMS_DELTA_GPIO_PIN_NAND_RB); |
eaca491f JK |
273 | iounmap(io_base); |
274 | out_release_io: | |
275 | release_mem_region(res->start, resource_size(res)); | |
276 | out_free: | |
3d12c0c7 JM |
277 | kfree(ams_delta_mtd); |
278 | out: | |
279 | return err; | |
280 | } | |
281 | ||
3d12c0c7 JM |
282 | /* |
283 | * Clean up routine | |
284 | */ | |
7e95d1f1 | 285 | static int __devexit ams_delta_cleanup(struct platform_device *pdev) |
3d12c0c7 | 286 | { |
eaca491f JK |
287 | void __iomem *io_base = platform_get_drvdata(pdev); |
288 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
289 | ||
3d12c0c7 JM |
290 | /* Release resources, unregister device */ |
291 | nand_release(ams_delta_mtd); | |
292 | ||
68f06766 JK |
293 | gpio_free_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio)); |
294 | gpio_free(AMS_DELTA_GPIO_PIN_NAND_RB); | |
eaca491f JK |
295 | iounmap(io_base); |
296 | release_mem_region(res->start, resource_size(res)); | |
297 | ||
3d12c0c7 JM |
298 | /* Free the MTD device structure */ |
299 | kfree(ams_delta_mtd); | |
7e95d1f1 JK |
300 | |
301 | return 0; | |
302 | } | |
303 | ||
304 | static struct platform_driver ams_delta_nand_driver = { | |
305 | .probe = ams_delta_init, | |
306 | .remove = __devexit_p(ams_delta_cleanup), | |
307 | .driver = { | |
308 | .name = "ams-delta-nand", | |
309 | .owner = THIS_MODULE, | |
310 | }, | |
311 | }; | |
312 | ||
f99640de | 313 | module_platform_driver(ams_delta_nand_driver); |
3d12c0c7 JM |
314 | |
315 | MODULE_LICENSE("GPL"); | |
316 | MODULE_AUTHOR("Jonathan McDowell <noodles@earth.li>"); | |
317 | MODULE_DESCRIPTION("Glue layer for NAND flash on Amstrad E3 (Delta)"); |