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Merge git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile
[deliverable/linux.git] / drivers / mtd / nand / cafe_nand.c
CommitLineData
c9ac5977 1/*
fbad5696 2 * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
5467fb02 3 *
514fca43 4 * The data sheet for this device can be found at:
631dd1a8 5 * http://wiki.laptop.org/go/Datasheets
514fca43 6 *
5467fb02
DW		 7 * Copyright © 2006 Red Hat, Inc.
8 * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
9 */
10
8dd851de 11#define DEBUG
5467fb02
DW		 12
13#include <linux/device.h>
14#undef DEBUG
15#include <linux/mtd/mtd.h>
16#include <linux/mtd/nand.h>
9c37f332 17#include <linux/mtd/partitions.h>
8c61b7a7 18#include <linux/rslib.h>
5467fb02
DW		 19#include <linux/pci.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
a1274302 22#include <linux/dma-mapping.h>
5a0e3ad6 23#include <linux/slab.h>
a0e5cc58 24#include <linux/module.h>
5467fb02
DW		 25#include <asm/io.h>
26
27#define CAFE_NAND_CTRL1 0x00
28#define CAFE_NAND_CTRL2 0x04
29#define CAFE_NAND_CTRL3 0x08
30#define CAFE_NAND_STATUS 0x0c
31#define CAFE_NAND_IRQ 0x10
32#define CAFE_NAND_IRQ_MASK 0x14
33#define CAFE_NAND_DATA_LEN 0x18
34#define CAFE_NAND_ADDR1 0x1c
35#define CAFE_NAND_ADDR2 0x20
36#define CAFE_NAND_TIMING1 0x24
37#define CAFE_NAND_TIMING2 0x28
38#define CAFE_NAND_TIMING3 0x2c
39#define CAFE_NAND_NONMEM 0x30
04459d7c 40#define CAFE_NAND_ECC_RESULT 0x3C
fbad5696
DW		 41#define CAFE_NAND_DMA_CTRL 0x40
42#define CAFE_NAND_DMA_ADDR0 0x44
43#define CAFE_NAND_DMA_ADDR1 0x48
04459d7c
DW		 44#define CAFE_NAND_ECC_SYN01 0x50
45#define CAFE_NAND_ECC_SYN23 0x54
46#define CAFE_NAND_ECC_SYN45 0x58
47#define CAFE_NAND_ECC_SYN67 0x5c
5467fb02
DW		 48#define CAFE_NAND_READ_DATA 0x1000
49#define CAFE_NAND_WRITE_DATA 0x2000
50
195a253b
DW		 51#define CAFE_GLOBAL_CTRL 0x3004
52#define CAFE_GLOBAL_IRQ 0x3008
53#define CAFE_GLOBAL_IRQ_MASK 0x300c
54#define CAFE_NAND_RESET 0x3034
55
048c37b4
DW		 56/* Missing from the datasheet: bit 19 of CTRL1 sets CE0 vs. CE1 */
57#define CTRL1_CHIPSELECT (1<<19)
58
5467fb02
DW		 59struct cafe_priv {
60 struct nand_chip nand;
61 struct pci_dev *pdev;
62 void __iomem *mmio;
8c61b7a7 63 struct rs_control *rs;
5467fb02
DW		 64 uint32_t ctl1;
65 uint32_t ctl2;
66 int datalen;
67 int nr_data;
68 int data_pos;
69 int page_addr;
70 dma_addr_t dmaaddr;
71 unsigned char *dmabuf;
5467fb02
DW		 72};
73
b478c775 74static int usedma = 1;
5467fb02
DW		 75module_param(usedma, int, 0644);
76
8dd851de
DW		 77static int skipbbt = 0;
78module_param(skipbbt, int, 0644);
79
80static int debug = 0;
81module_param(debug, int, 0644);
82
be8444bd
DW		 83static int regdebug = 0;
84module_param(regdebug, int, 0644);
85
b478c775 86static int checkecc = 1;
470b0a90
DW		 87module_param(checkecc, int, 0644);
88
64a6f950 89static unsigned int numtimings;
527a4f45
DW		 90static int timing[3];
91module_param_array(timing, int, &numtimings, 0644);
b478c775 92
68874414 93static const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
9c37f332 94
04459d7c 95/* Hrm. Why isn't this already conditional on something in the struct device? */
8dd851de
DW		 96#define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
97
195a253b
DW		 98/* Make it easier to switch to PIO if we need to */
99#define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
100#define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
8dd851de 101
5467fb02
DW		 102static int cafe_device_ready(struct mtd_info *mtd)
103{
104 struct cafe_priv *cafe = mtd->priv;
48f8b641 105 int result = !!(cafe_readl(cafe, NAND_STATUS) & 0x40000000);
195a253b 106 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
fbad5696 107
195a253b 108 cafe_writel(cafe, irqs, NAND_IRQ);
fbad5696 109
8dd851de 110 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
195a253b
DW		 111 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
112 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
fbad5696 113
5467fb02
DW		 114 return result;
115}
116
117
118static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
119{
120 struct cafe_priv *cafe = mtd->priv;
121
122 if (usedma)
123 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
124 else
125 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
fbad5696 126
5467fb02
DW		 127 cafe->datalen += len;
128
8dd851de 129 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
5467fb02
DW		 130 len, cafe->datalen);
131}
132
133static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
134{
135 struct cafe_priv *cafe = mtd->priv;
136
137 if (usedma)
138 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
139 else
140 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
141
8dd851de 142 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
5467fb02
DW		 143 len, cafe->datalen);
144 cafe->datalen += len;
145}
146
147static uint8_t cafe_read_byte(struct mtd_info *mtd)
148{
149 struct cafe_priv *cafe = mtd->priv;
150 uint8_t d;
151
152 cafe_read_buf(mtd, &d, 1);
8dd851de 153 cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
5467fb02
DW		 154
155 return d;
156}
157
158static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
159 int column, int page_addr)
160{
161 struct cafe_priv *cafe = mtd->priv;
162 int adrbytes = 0;
163 uint32_t ctl1;
164 uint32_t doneint = 0x80000000;
5467fb02 165
8dd851de 166 cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
5467fb02
DW		 167 command, column, page_addr);
168
169 if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
170 /* Second half of a command we already calculated */
195a253b 171 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
5467fb02 172 ctl1 = cafe->ctl1;
cad40654 173 cafe->ctl2 &= ~(1<<30);
8dd851de 174 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
5467fb02
DW		 175 cafe->ctl1, cafe->nr_data);
176 goto do_command;
177 }
178 /* Reset ECC engine */
195a253b 179 cafe_writel(cafe, 0, NAND_CTRL2);
5467fb02
DW		 180
181 /* Emulate NAND_CMD_READOOB on large-page chips */
182 if (mtd->writesize > 512 &&
183 command == NAND_CMD_READOOB) {
184 column += mtd->writesize;
185 command = NAND_CMD_READ0;
186 }
187
188 /* FIXME: Do we need to send read command before sending data
189 for small-page chips, to position the buffer correctly? */
190
191 if (column != -1) {
195a253b 192 cafe_writel(cafe, column, NAND_ADDR1);
5467fb02
DW		 193 adrbytes = 2;
194 if (page_addr != -1)
195 goto write_adr2;
196 } else if (page_addr != -1) {
195a253b 197 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
5467fb02
DW		 198 page_addr >>= 16;
199 write_adr2:
195a253b 200 cafe_writel(cafe, page_addr, NAND_ADDR2);
5467fb02
DW		 201 adrbytes += 2;
202 if (mtd->size > mtd->writesize << 16)
203 adrbytes++;
204 }
205
206 cafe->data_pos = cafe->datalen = 0;
207
048c37b4
DW		 208 /* Set command valid bit, mask in the chip select bit */
209 ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT);
5467fb02
DW		 210
211 /* Set RD or WR bits as appropriate */
212 if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
213 ctl1 |= (1<<26); /* rd */
214 /* Always 5 bytes, for now */
8dd851de 215 cafe->datalen = 4;
5467fb02
DW		 216 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
217 adrbytes = 1;
218 } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
219 command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
220 ctl1 |= 1<<26; /* rd */
221 /* For now, assume just read to end of page */
222 cafe->datalen = mtd->writesize + mtd->oobsize - column;
223 } else if (command == NAND_CMD_SEQIN)
224 ctl1 |= 1<<25; /* wr */
225
226 /* Set number of address bytes */
227 if (adrbytes)
228 ctl1 |= ((adrbytes-1)|8) << 27;
229
230 if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
c9ac5977 231 /* Ignore the first command of a pair; the hardware
5467fb02
DW		 232 deals with them both at once, later */
233 cafe->ctl1 = ctl1;
8dd851de 234 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
5467fb02
DW		 235 cafe->ctl1, cafe->datalen);
236 return;
237 }
238 /* RNDOUT and READ0 commands need a following byte */
239 if (command == NAND_CMD_RNDOUT)
195a253b 240 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
5467fb02 241 else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
195a253b 242 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
5467fb02
DW		 243
244 do_command:
c9ac5977 245 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
195a253b 246 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
fbad5696 247
5467fb02 248 /* NB: The datasheet lies -- we really should be subtracting 1 here */
195a253b
DW		 249 cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
250 cafe_writel(cafe, 0x90000000, NAND_IRQ);
5467fb02
DW		 251 if (usedma && (ctl1 & (3<<25))) {
252 uint32_t dmactl = 0xc0000000 + cafe->datalen;
253 /* If WR or RD bits set, set up DMA */
254 if (ctl1 & (1<<26)) {
255 /* It's a read */
256 dmactl |= (1<<29);
257 /* ... so it's done when the DMA is done, not just
258 the command. */
259 doneint = 0x10000000;
260 }
195a253b 261 cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
5467fb02 262 }
5467fb02
DW		 263 cafe->datalen = 0;
264
be8444bd
DW		 265 if (unlikely(regdebug)) {
266 int i;
267 printk("About to write command %08x to register 0\n", ctl1);
268 for (i=4; i< 0x5c; i+=4)
269 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
fbad5696 270 }
be8444bd 271
195a253b 272 cafe_writel(cafe, ctl1, NAND_CTRL1);
5467fb02
DW		 273 /* Apply this short delay always to ensure that we do wait tWB in
274 * any case on any machine. */
275 ndelay(100);
276
277 if (1) {
2a7295b2 278 int c;
5467fb02
DW		 279 uint32_t irqs;
280
2a7295b2 281 for (c = 500000; c != 0; c--) {
195a253b 282 irqs = cafe_readl(cafe, NAND_IRQ);
5467fb02
DW		 283 if (irqs & doneint)
284 break;
285 udelay(1);
8dd851de
DW		 286 if (!(c % 100000))
287 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
5467fb02
DW		 288 cpu_relax();
289 }
195a253b 290 cafe_writel(cafe, doneint, NAND_IRQ);
a020727b 291 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
195a253b 292 command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
5467fb02
DW		 293 }
294
cad40654 295 WARN_ON(cafe->ctl2 & (1<<30));
5467fb02
DW		 296
297 switch (command) {
298
299 case NAND_CMD_CACHEDPROG:
300 case NAND_CMD_PAGEPROG:
301 case NAND_CMD_ERASE1:
302 case NAND_CMD_ERASE2:
303 case NAND_CMD_SEQIN:
304 case NAND_CMD_RNDIN:
305 case NAND_CMD_STATUS:
306 case NAND_CMD_DEPLETE1:
307 case NAND_CMD_RNDOUT:
308 case NAND_CMD_STATUS_ERROR:
309 case NAND_CMD_STATUS_ERROR0:
310 case NAND_CMD_STATUS_ERROR1:
311 case NAND_CMD_STATUS_ERROR2:
312 case NAND_CMD_STATUS_ERROR3:
195a253b 313 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
5467fb02
DW		 314 return;
315 }
316 nand_wait_ready(mtd);
195a253b 317 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
5467fb02
DW		 318}
319
320static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
321{
048c37b4
DW		 322 struct cafe_priv *cafe = mtd->priv;
323
324 cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
325
326 /* Mask the appropriate bit into the stored value of ctl1
327 which will be used by cafe_nand_cmdfunc() */
328 if (chipnr)
329 cafe->ctl1 |= CTRL1_CHIPSELECT;
330 else
331 cafe->ctl1 &= ~CTRL1_CHIPSELECT;
5467fb02 332}
fbad5696 333
67cd724f 334static irqreturn_t cafe_nand_interrupt(int irq, void *id)
5467fb02
DW		 335{
336 struct mtd_info *mtd = id;
337 struct cafe_priv *cafe = mtd->priv;
195a253b
DW		 338 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
339 cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
5467fb02
DW		 340 if (!irqs)
341 return IRQ_NONE;
342
195a253b 343 cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
5467fb02
DW		 344 return IRQ_HANDLED;
345}
346
347static void cafe_nand_bug(struct mtd_info *mtd)
348{
349 BUG();
350}
351
352static int cafe_nand_write_oob(struct mtd_info *mtd,
353 struct nand_chip *chip, int page)
354{
355 int status = 0;
356
5467fb02
DW		 357 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
358 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
359 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
360 status = chip->waitfunc(mtd, chip);
361
362 return status & NAND_STATUS_FAIL ? -EIO : 0;
363}
364
365/* Don't use -- use nand_read_oob_std for now */
366static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 367 int page)
5467fb02
DW		 368{
369 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
370 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
5c2ffb11 371 return 0;
5467fb02
DW		 372}
373/**
7854d3f7 374 * cafe_nand_read_page_syndrome - [REPLACEABLE] hardware ecc syndrome based page read
5467fb02
DW		 375 * @mtd: mtd info structure
376 * @chip: nand chip info structure
377 * @buf: buffer to store read data
1fbb938d 378 * @oob_required: caller expects OOB data read to chip->oob_poi
5467fb02 379 *
b9bc815c 380 * The hw generator calculates the error syndrome automatically. Therefore
5467fb02
DW		 381 * we need a special oob layout and handling.
382 */
383static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 384 uint8_t *buf, int oob_required, int page)
5467fb02
DW		 385{
386 struct cafe_priv *cafe = mtd->priv;
3f91e94f 387 unsigned int max_bitflips = 0;
5467fb02 388
fbad5696 389 cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
195a253b
DW		 390 cafe_readl(cafe, NAND_ECC_RESULT),
391 cafe_readl(cafe, NAND_ECC_SYN01));
5467fb02
DW		 392
393 chip->read_buf(mtd, buf, mtd->writesize);
394 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
395
195a253b 396 if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
8c61b7a7
SB		 397 unsigned short syn[8], pat[4];
398 int pos[4];
399 u8 *oob = chip->oob_poi;
400 int i, n;
04459d7c
DW		 401
402 for (i=0; i<8; i+=2) {
195a253b 403 uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
8c61b7a7
SB		 404 syn[i] = cafe->rs->index_of[tmp & 0xfff];
405 syn[i+1] = cafe->rs->index_of[(tmp >> 16) & 0xfff];
406 }
407
408 n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0,
409 pat);
410
411 for (i = 0; i < n; i++) {
412 int p = pos[i];
413
414 /* The 12-bit symbols are mapped to bytes here */
415
416 if (p > 1374) {
417 /* out of range */
418 n = -1374;
419 } else if (p == 0) {
420 /* high four bits do not correspond to data */
421 if (pat[i] > 0xff)
422 n = -2048;
423 else
424 buf[0] ^= pat[i];
425 } else if (p == 1365) {
426 buf[2047] ^= pat[i] >> 4;
427 oob[0] ^= pat[i] << 4;
428 } else if (p > 1365) {
429 if ((p & 1) == 1) {
430 oob[3*p/2 - 2048] ^= pat[i] >> 4;
431 oob[3*p/2 - 2047] ^= pat[i] << 4;
432 } else {
433 oob[3*p/2 - 2049] ^= pat[i] >> 8;
434 oob[3*p/2 - 2048] ^= pat[i];
435 }
436 } else if ((p & 1) == 1) {
437 buf[3*p/2] ^= pat[i] >> 4;
438 buf[3*p/2 + 1] ^= pat[i] << 4;
439 } else {
440 buf[3*p/2 - 1] ^= pat[i] >> 8;
441 buf[3*p/2] ^= pat[i];
442 }
c9ac5977 443 }
04459d7c 444
8c61b7a7 445 if (n < 0) {
be8444bd
DW		 446 dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
447 cafe_readl(cafe, NAND_ADDR2) * 2048);
8c61b7a7 448 for (i = 0; i < 0x5c; i += 4)
be8444bd 449 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
04459d7c
DW		 450 mtd->ecc_stats.failed++;
451 } else {
8c61b7a7
SB		 452 dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n);
453 mtd->ecc_stats.corrected += n;
3f91e94f 454 max_bitflips = max_t(unsigned int, max_bitflips, n);
04459d7c
DW		 455 }
456 }
457
3f91e94f 458 return max_bitflips;
5467fb02
DW		 459}
460
8dd851de
DW		 461static struct nand_ecclayout cafe_oobinfo_2048 = {
462 .eccbytes = 14,
463 .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
464 .oobfree = {{14, 50}}
465};
466
c9ac5977 467/* Ick. The BBT code really ought to be able to work this bit out
fbad5696
DW		 468 for itself from the above, at least for the 2KiB case */
469static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
470static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
471
472static uint8_t cafe_bbt_pattern_512[] = { 0xBB };
473static uint8_t cafe_mirror_pattern_512[] = { 0xBC };
474
8dd851de
DW		 475
476static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
477 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
048c37b4 478 | NAND_BBT_2BIT | NAND_BBT_VERSION,
8dd851de
DW		 479 .offs = 14,
480 .len = 4,
481 .veroffs = 18,
482 .maxblocks = 4,
fbad5696 483 .pattern = cafe_bbt_pattern_2048
8dd851de
DW		 484};
485
486static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
487 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
048c37b4 488 | NAND_BBT_2BIT | NAND_BBT_VERSION,
8dd851de
DW		 489 .offs = 14,
490 .len = 4,
491 .veroffs = 18,
492 .maxblocks = 4,
fbad5696 493 .pattern = cafe_mirror_pattern_2048
8dd851de
DW		 494};
495
496static struct nand_ecclayout cafe_oobinfo_512 = {
497 .eccbytes = 14,
498 .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
499 .oobfree = {{14, 2}}
500};
501
fbad5696
DW		 502static struct nand_bbt_descr cafe_bbt_main_descr_512 = {
503 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
048c37b4 504 | NAND_BBT_2BIT | NAND_BBT_VERSION,
fbad5696
DW		 505 .offs = 14,
506 .len = 1,
507 .veroffs = 15,
508 .maxblocks = 4,
509 .pattern = cafe_bbt_pattern_512
510};
511
512static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
513 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
048c37b4 514 | NAND_BBT_2BIT | NAND_BBT_VERSION,
fbad5696
DW		 515 .offs = 14,
516 .len = 1,
517 .veroffs = 15,
518 .maxblocks = 4,
519 .pattern = cafe_mirror_pattern_512
520};
521
522
fdbad98d 523static int cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
1fbb938d
BN		 524 struct nand_chip *chip,
525 const uint8_t *buf, int oob_required)
5467fb02
DW		 526{
527 struct cafe_priv *cafe = mtd->priv;
528
5467fb02 529 chip->write_buf(mtd, buf, mtd->writesize);
8dd851de 530 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
5467fb02
DW		 531
532 /* Set up ECC autogeneration */
cad40654 533 cafe->ctl2 |= (1<<30);
fdbad98d
JW		 534
535 return 0;
5467fb02
DW		 536}
537
538static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d
BN		 539 const uint8_t *buf, int oob_required, int page,
540 int cached, int raw)
5467fb02
DW		 541{
542 int status;
543
5467fb02
DW		 544 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
545
546 if (unlikely(raw))
fdbad98d 547 status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
5467fb02 548 else
fdbad98d
JW		 549 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
550
551 if (status < 0)
552 return status;
5467fb02
DW		 553
554 /*
555 * Cached progamming disabled for now, Not sure if its worth the
556 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
557 */
558 cached = 0;
559
560 if (!cached || !(chip->options & NAND_CACHEPRG)) {
561
562 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
563 status = chip->waitfunc(mtd, chip);
564 /*
565 * See if operation failed and additional status checks are
566 * available
567 */
568 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
569 status = chip->errstat(mtd, chip, FL_WRITING, status,
570 page);
571
572 if (status & NAND_STATUS_FAIL)
573 return -EIO;
574 } else {
575 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
576 status = chip->waitfunc(mtd, chip);
577 }
578
5467fb02
DW		 579 return 0;
580}
581
8dd851de
DW		 582static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
583{
584 return 0;
585}
5467fb02 586
8c61b7a7
SB		 587/* F_2[X]/(X**6+X+1) */
588static unsigned short __devinit gf64_mul(u8 a, u8 b)
589{
590 u8 c;
591 unsigned int i;
592
593 c = 0;
594 for (i = 0; i < 6; i++) {
595 if (a & 1)
596 c ^= b;
597 a >>= 1;
598 b <<= 1;
599 if ((b & 0x40) != 0)
600 b ^= 0x43;
601 }
602
603 return c;
604}
605
606/* F_64[X]/(X**2+X+A**-1) with A the generator of F_64[X] */
607static u16 __devinit gf4096_mul(u16 a, u16 b)
608{
609 u8 ah, al, bh, bl, ch, cl;
610
611 ah = a >> 6;
612 al = a & 0x3f;
613 bh = b >> 6;
614 bl = b & 0x3f;
615
616 ch = gf64_mul(ah ^ al, bh ^ bl) ^ gf64_mul(al, bl);
617 cl = gf64_mul(gf64_mul(ah, bh), 0x21) ^ gf64_mul(al, bl);
618
619 return (ch << 6) ^ cl;
620}
621
622static int __devinit cafe_mul(int x)
623{
624 if (x == 0)
625 return 1;
626 return gf4096_mul(x, 0xe01);
627}
628
5467fb02
DW		 629static int __devinit cafe_nand_probe(struct pci_dev *pdev,
630 const struct pci_device_id *ent)
631{
632 struct mtd_info *mtd;
633 struct cafe_priv *cafe;
634 uint32_t ctrl;
635 int err = 0;
636
06ed24e5
DW		 637 /* Very old versions shared the same PCI ident for all three
638 functions on the chip. Verify the class too... */
639 if ((pdev->class >> 8) != PCI_CLASS_MEMORY_FLASH)
640 return -ENODEV;
641
5467fb02
DW		 642 err = pci_enable_device(pdev);
643 if (err)
644 return err;
645
646 pci_set_master(pdev);
647
648 mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL);
649 if (!mtd) {
650 dev_warn(&pdev->dev, "failed to alloc mtd_info\n");
651 return -ENOMEM;
652 }
653 cafe = (void *)(&mtd[1]);
654
c451c7c4 655 mtd->dev.parent = &pdev->dev;
5467fb02
DW		 656 mtd->priv = cafe;
657 mtd->owner = THIS_MODULE;
658
659 cafe->pdev = pdev;
660 cafe->mmio = pci_iomap(pdev, 0, 0);
661 if (!cafe->mmio) {
662 dev_warn(&pdev->dev, "failed to iomap\n");
663 err = -ENOMEM;
664 goto out_free_mtd;
665 }
666 cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers),
667 &cafe->dmaaddr, GFP_KERNEL);
668 if (!cafe->dmabuf) {
669 err = -ENOMEM;
670 goto out_ior;
671 }
672 cafe->nand.buffers = (void *)cafe->dmabuf + 2112;
673
8c61b7a7
SB		 674 cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8);
675 if (!cafe->rs) {
676 err = -ENOMEM;
677 goto out_ior;
678 }
679
5467fb02
DW		 680 cafe->nand.cmdfunc = cafe_nand_cmdfunc;
681 cafe->nand.dev_ready = cafe_device_ready;
682 cafe->nand.read_byte = cafe_read_byte;
683 cafe->nand.read_buf = cafe_read_buf;
684 cafe->nand.write_buf = cafe_write_buf;
685 cafe->nand.select_chip = cafe_select_chip;
686
687 cafe->nand.chip_delay = 0;
688
689 /* Enable the following for a flash based bad block table */
bb9ebd4e 690 cafe->nand.bbt_options = NAND_BBT_USE_FLASH;
1826dbcc 691 cafe->nand.options = NAND_OWN_BUFFERS;
8dd851de
DW		 692
693 if (skipbbt) {
694 cafe->nand.options |= NAND_SKIP_BBTSCAN;
695 cafe->nand.block_bad = cafe_nand_block_bad;
696 }
c9ac5977 697
527a4f45
DW		 698 if (numtimings && numtimings != 3) {
699 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
700 }
701
702 if (numtimings == 3) {
527a4f45 703 cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
8e5368a1 704 timing[0], timing[1], timing[2]);
527a4f45 705 } else {
8e5368a1
DW		 706 timing[0] = cafe_readl(cafe, NAND_TIMING1);
707 timing[1] = cafe_readl(cafe, NAND_TIMING2);
708 timing[2] = cafe_readl(cafe, NAND_TIMING3);
527a4f45 709
8e5368a1
DW		 710 if (timing[0] | timing[1] | timing[2]) {
711 cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n",
712 timing[0], timing[1], timing[2]);
527a4f45
DW		 713 } else {
714 dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
8e5368a1 715 timing[0] = timing[1] = timing[2] = 0xffffffff;
527a4f45
DW		 716 }
717 }
718
dcc41bc8 719 /* Start off by resetting the NAND controller completely */
195a253b
DW		 720 cafe_writel(cafe, 1, NAND_RESET);
721 cafe_writel(cafe, 0, NAND_RESET);
dcc41bc8 722
8e5368a1
DW		 723 cafe_writel(cafe, timing[0], NAND_TIMING1);
724 cafe_writel(cafe, timing[1], NAND_TIMING2);
725 cafe_writel(cafe, timing[2], NAND_TIMING3);
b478c775 726
195a253b 727 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
2db6346f
TG		 728 err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED,
729 "CAFE NAND", mtd);
5467fb02
DW		 730 if (err) {
731 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
5467fb02
DW		 732 goto out_free_dma;
733 }
f7c37d7b 734
5467fb02 735 /* Disable master reset, enable NAND clock */
195a253b 736 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
5467fb02
DW		 737 ctrl &= 0xffffeff0;
738 ctrl |= 0x00007000;
195a253b
DW		 739 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
740 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
741 cafe_writel(cafe, 0, NAND_DMA_CTRL);
5467fb02 742
195a253b
DW		 743 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
744 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
5467fb02
DW		 745
746 /* Set up DMA address */
195a253b 747 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
5467fb02 748 if (sizeof(cafe->dmaaddr) > 4)
fbad5696 749 /* Shift in two parts to shut the compiler up */
195a253b 750 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
5467fb02 751 else
195a253b 752 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
fbad5696 753
8dd851de 754 cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
195a253b 755 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
5467fb02
DW		 756
757 /* Enable NAND IRQ in global IRQ mask register */
195a253b 758 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
8dd851de 759 cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
195a253b 760 cafe_readl(cafe, GLOBAL_CTRL), cafe_readl(cafe, GLOBAL_IRQ_MASK));
f7c37d7b
DW		 761
762 /* Scan to find existence of the device */
5e81e88a 763 if (nand_scan_ident(mtd, 2, NULL)) {
5467fb02
DW		 764 err = -ENXIO;
765 goto out_irq;
766 }
767
768 cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
769 if (mtd->writesize == 2048)
770 cafe->ctl2 |= 1<<29; /* 2KiB page size */
771
772 /* Set up ECC according to the type of chip we found */
fbad5696 773 if (mtd->writesize == 2048) {
8dd851de
DW		 774 cafe->nand.ecc.layout = &cafe_oobinfo_2048;
775 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
776 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
fbad5696
DW		 777 } else if (mtd->writesize == 512) {
778 cafe->nand.ecc.layout = &cafe_oobinfo_512;
779 cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
780 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
5467fb02 781 } else {
fbad5696 782 printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n",
5467fb02 783 mtd->writesize);
fbad5696 784 goto out_irq;
5467fb02 785 }
fbad5696
DW		 786 cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
787 cafe->nand.ecc.size = mtd->writesize;
788 cafe->nand.ecc.bytes = 14;
6a918bad 789 cafe->nand.ecc.strength = 4;
fbad5696
DW		 790 cafe->nand.ecc.hwctl = (void *)cafe_nand_bug;
791 cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
792 cafe->nand.ecc.correct = (void *)cafe_nand_bug;
793 cafe->nand.write_page = cafe_nand_write_page;
794 cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
795 cafe->nand.ecc.write_oob = cafe_nand_write_oob;
796 cafe->nand.ecc.read_page = cafe_nand_read_page;
797 cafe->nand.ecc.read_oob = cafe_nand_read_oob;
5467fb02
DW		 798
799 err = nand_scan_tail(mtd);
800 if (err)
801 goto out_irq;
802
5467fb02 803 pci_set_drvdata(pdev, mtd);
9c37f332 804
68874414 805 mtd->name = "cafe_nand";
42d7fbe2 806 mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0);
4d32de81 807
5467fb02
DW		 808 goto out;
809
810 out_irq:
811 /* Disable NAND IRQ in global IRQ mask register */
195a253b 812 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
5467fb02
DW		 813 free_irq(pdev->irq, mtd);
814 out_free_dma:
815 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
816 out_ior:
817 pci_iounmap(pdev, cafe->mmio);
818 out_free_mtd:
819 kfree(mtd);
820 out:
821 return err;
822}
823
824static void __devexit cafe_nand_remove(struct pci_dev *pdev)
825{
826 struct mtd_info *mtd = pci_get_drvdata(pdev);
827 struct cafe_priv *cafe = mtd->priv;
828
5467fb02 829 /* Disable NAND IRQ in global IRQ mask register */
195a253b 830 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
5467fb02
DW		 831 free_irq(pdev->irq, mtd);
832 nand_release(mtd);
8c61b7a7 833 free_rs(cafe->rs);
5467fb02
DW		 834 pci_iounmap(pdev, cafe->mmio);
835 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
836 kfree(mtd);
837}
838
377ace08 839static const struct pci_device_id cafe_nand_tbl[] = {
514fca43
DW		 840 { PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_88ALP01_NAND,
841 PCI_ANY_ID, PCI_ANY_ID },
06ed24e5 842 { }
5467fb02
DW		 843};
844
845MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
846
1fcf8ce5
DW		 847static int cafe_nand_resume(struct pci_dev *pdev)
848{
849 uint32_t ctrl;
850 struct mtd_info *mtd = pci_get_drvdata(pdev);
851 struct cafe_priv *cafe = mtd->priv;
852
853 /* Start off by resetting the NAND controller completely */
854 cafe_writel(cafe, 1, NAND_RESET);
855 cafe_writel(cafe, 0, NAND_RESET);
856 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
857
858 /* Restore timing configuration */
859 cafe_writel(cafe, timing[0], NAND_TIMING1);
860 cafe_writel(cafe, timing[1], NAND_TIMING2);
861 cafe_writel(cafe, timing[2], NAND_TIMING3);
862
863 /* Disable master reset, enable NAND clock */
864 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
865 ctrl &= 0xffffeff0;
866 ctrl |= 0x00007000;
867 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
868 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
869 cafe_writel(cafe, 0, NAND_DMA_CTRL);
870 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
871 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
872
873 /* Set up DMA address */
874 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
875 if (sizeof(cafe->dmaaddr) > 4)
876 /* Shift in two parts to shut the compiler up */
877 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
878 else
879 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
880
881 /* Enable NAND IRQ in global IRQ mask register */
882 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
883 return 0;
884}
885
5467fb02
DW		 886static struct pci_driver cafe_nand_pci_driver = {
887 .name = "CAFÉ NAND",
888 .id_table = cafe_nand_tbl,
889 .probe = cafe_nand_probe,
890 .remove = __devexit_p(cafe_nand_remove),
5467fb02 891 .resume = cafe_nand_resume,
5467fb02
DW		 892};
893
4d16cd65 894module_pci_driver(cafe_nand_pci_driver);
5467fb02
DW		 895
896MODULE_LICENSE("GPL");
897MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
f7c37d7b 898MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip");
Linux kernel - Deliverables
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