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76b10467 SW |
1 | /* Freescale Enhanced Local Bus Controller NAND driver |
2 | * | |
3ab8f2a2 | 3 | * Copyright © 2006-2007, 2010 Freescale Semiconductor |
76b10467 SW |
4 | * |
5 | * Authors: Nick Spence <nick.spence@freescale.com>, | |
6 | * Scott Wood <scottwood@freescale.com> | |
3ab8f2a2 RZ |
7 | * Jack Lan <jack.lan@freescale.com> |
8 | * Roy Zang <tie-fei.zang@freescale.com> | |
76b10467 SW |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <linux/module.h> | |
26 | #include <linux/types.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/kernel.h> | |
29 | #include <linux/string.h> | |
30 | #include <linux/ioport.h> | |
31 | #include <linux/of_platform.h> | |
3ab8f2a2 | 32 | #include <linux/platform_device.h> |
76b10467 SW |
33 | #include <linux/slab.h> |
34 | #include <linux/interrupt.h> | |
35 | ||
36 | #include <linux/mtd/mtd.h> | |
37 | #include <linux/mtd/nand.h> | |
38 | #include <linux/mtd/nand_ecc.h> | |
39 | #include <linux/mtd/partitions.h> | |
40 | ||
41 | #include <asm/io.h> | |
d4a32fe4 | 42 | #include <asm/fsl_lbc.h> |
76b10467 SW |
43 | |
44 | #define MAX_BANKS 8 | |
45 | #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ | |
46 | #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */ | |
47 | ||
76b10467 SW |
48 | /* mtd information per set */ |
49 | ||
50 | struct fsl_elbc_mtd { | |
51 | struct mtd_info mtd; | |
52 | struct nand_chip chip; | |
3ab8f2a2 | 53 | struct fsl_lbc_ctrl *ctrl; |
76b10467 SW |
54 | |
55 | struct device *dev; | |
56 | int bank; /* Chip select bank number */ | |
57 | u8 __iomem *vbase; /* Chip select base virtual address */ | |
58 | int page_size; /* NAND page size (0=512, 1=2048) */ | |
59 | unsigned int fmr; /* FCM Flash Mode Register value */ | |
60 | }; | |
61 | ||
25985edc | 62 | /* Freescale eLBC FCM controller information */ |
76b10467 | 63 | |
3ab8f2a2 | 64 | struct fsl_elbc_fcm_ctrl { |
76b10467 SW |
65 | struct nand_hw_control controller; |
66 | struct fsl_elbc_mtd *chips[MAX_BANKS]; | |
67 | ||
76b10467 SW |
68 | u8 __iomem *addr; /* Address of assigned FCM buffer */ |
69 | unsigned int page; /* Last page written to / read from */ | |
70 | unsigned int read_bytes; /* Number of bytes read during command */ | |
71 | unsigned int column; /* Saved column from SEQIN */ | |
72 | unsigned int index; /* Pointer to next byte to 'read' */ | |
73 | unsigned int status; /* status read from LTESR after last op */ | |
74 | unsigned int mdr; /* UPM/FCM Data Register value */ | |
75 | unsigned int use_mdr; /* Non zero if the MDR is to be set */ | |
76 | unsigned int oob; /* Non zero if operating on OOB data */ | |
3ab8f2a2 | 77 | unsigned int counter; /* counter for the initializations */ |
3f91e94f | 78 | unsigned int max_bitflips; /* Saved during READ0 cmd */ |
76b10467 SW |
79 | }; |
80 | ||
81 | /* These map to the positions used by the FCM hardware ECC generator */ | |
82 | ||
83 | /* Small Page FLASH with FMR[ECCM] = 0 */ | |
84 | static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = { | |
85 | .eccbytes = 3, | |
86 | .eccpos = {6, 7, 8}, | |
87 | .oobfree = { {0, 5}, {9, 7} }, | |
76b10467 SW |
88 | }; |
89 | ||
90 | /* Small Page FLASH with FMR[ECCM] = 1 */ | |
91 | static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = { | |
92 | .eccbytes = 3, | |
93 | .eccpos = {8, 9, 10}, | |
94 | .oobfree = { {0, 5}, {6, 2}, {11, 5} }, | |
76b10467 SW |
95 | }; |
96 | ||
97 | /* Large Page FLASH with FMR[ECCM] = 0 */ | |
98 | static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = { | |
99 | .eccbytes = 12, | |
100 | .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56}, | |
101 | .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} }, | |
76b10467 SW |
102 | }; |
103 | ||
104 | /* Large Page FLASH with FMR[ECCM] = 1 */ | |
105 | static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = { | |
106 | .eccbytes = 12, | |
107 | .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, | |
108 | .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} }, | |
76b10467 SW |
109 | }; |
110 | ||
452db272 AV |
111 | /* |
112 | * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset | |
113 | * 1, so we have to adjust bad block pattern. This pattern should be used for | |
114 | * x8 chips only. So far hardware does not support x16 chips anyway. | |
115 | */ | |
116 | static u8 scan_ff_pattern[] = { 0xff, }; | |
117 | ||
118 | static struct nand_bbt_descr largepage_memorybased = { | |
119 | .options = 0, | |
120 | .offs = 0, | |
121 | .len = 1, | |
122 | .pattern = scan_ff_pattern, | |
123 | }; | |
124 | ||
ec6e0ea3 AV |
125 | /* |
126 | * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt, | |
127 | * interfere with ECC positions, that's why we implement our own descriptors. | |
128 | * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0. | |
129 | */ | |
130 | static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; | |
131 | static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; | |
132 | ||
133 | static struct nand_bbt_descr bbt_main_descr = { | |
134 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | | |
135 | NAND_BBT_2BIT | NAND_BBT_VERSION, | |
136 | .offs = 11, | |
137 | .len = 4, | |
138 | .veroffs = 15, | |
139 | .maxblocks = 4, | |
140 | .pattern = bbt_pattern, | |
141 | }; | |
142 | ||
143 | static struct nand_bbt_descr bbt_mirror_descr = { | |
144 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | | |
145 | NAND_BBT_2BIT | NAND_BBT_VERSION, | |
146 | .offs = 11, | |
147 | .len = 4, | |
148 | .veroffs = 15, | |
149 | .maxblocks = 4, | |
150 | .pattern = mirror_pattern, | |
151 | }; | |
152 | ||
76b10467 SW |
153 | /*=================================*/ |
154 | ||
155 | /* | |
156 | * Set up the FCM hardware block and page address fields, and the fcm | |
157 | * structure addr field to point to the correct FCM buffer in memory | |
158 | */ | |
159 | static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) | |
160 | { | |
161 | struct nand_chip *chip = mtd->priv; | |
162 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 163 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
d4a32fe4 | 164 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
3ab8f2a2 | 165 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; |
76b10467 SW |
166 | int buf_num; |
167 | ||
3ab8f2a2 | 168 | elbc_fcm_ctrl->page = page_addr; |
76b10467 | 169 | |
76b10467 | 170 | if (priv->page_size) { |
9ae84fe8 LS |
171 | /* |
172 | * large page size chip : FPAR[PI] save the lowest 6 bits, | |
173 | * FBAR[BLK] save the other bits. | |
174 | */ | |
175 | out_be32(&lbc->fbar, page_addr >> 6); | |
76b10467 SW |
176 | out_be32(&lbc->fpar, |
177 | ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) | | |
178 | (oob ? FPAR_LP_MS : 0) | column); | |
179 | buf_num = (page_addr & 1) << 2; | |
180 | } else { | |
9ae84fe8 LS |
181 | /* |
182 | * small page size chip : FPAR[PI] save the lowest 5 bits, | |
183 | * FBAR[BLK] save the other bits. | |
184 | */ | |
185 | out_be32(&lbc->fbar, page_addr >> 5); | |
76b10467 SW |
186 | out_be32(&lbc->fpar, |
187 | ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) | | |
188 | (oob ? FPAR_SP_MS : 0) | column); | |
189 | buf_num = page_addr & 7; | |
190 | } | |
191 | ||
3ab8f2a2 RZ |
192 | elbc_fcm_ctrl->addr = priv->vbase + buf_num * 1024; |
193 | elbc_fcm_ctrl->index = column; | |
76b10467 SW |
194 | |
195 | /* for OOB data point to the second half of the buffer */ | |
196 | if (oob) | |
3ab8f2a2 | 197 | elbc_fcm_ctrl->index += priv->page_size ? 2048 : 512; |
76b10467 | 198 | |
3ab8f2a2 RZ |
199 | dev_vdbg(priv->dev, "set_addr: bank=%d, " |
200 | "elbc_fcm_ctrl->addr=0x%p (0x%p), " | |
76b10467 | 201 | "index %x, pes %d ps %d\n", |
3ab8f2a2 RZ |
202 | buf_num, elbc_fcm_ctrl->addr, priv->vbase, |
203 | elbc_fcm_ctrl->index, | |
76b10467 SW |
204 | chip->phys_erase_shift, chip->page_shift); |
205 | } | |
206 | ||
207 | /* | |
208 | * execute FCM command and wait for it to complete | |
209 | */ | |
210 | static int fsl_elbc_run_command(struct mtd_info *mtd) | |
211 | { | |
212 | struct nand_chip *chip = mtd->priv; | |
213 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 RZ |
214 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
215 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; | |
d4a32fe4 | 216 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
217 | |
218 | /* Setup the FMR[OP] to execute without write protection */ | |
219 | out_be32(&lbc->fmr, priv->fmr | 3); | |
3ab8f2a2 RZ |
220 | if (elbc_fcm_ctrl->use_mdr) |
221 | out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr); | |
76b10467 | 222 | |
3ab8f2a2 | 223 | dev_vdbg(priv->dev, |
76b10467 SW |
224 | "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n", |
225 | in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr)); | |
3ab8f2a2 | 226 | dev_vdbg(priv->dev, |
76b10467 SW |
227 | "fsl_elbc_run_command: fbar=%08x fpar=%08x " |
228 | "fbcr=%08x bank=%d\n", | |
229 | in_be32(&lbc->fbar), in_be32(&lbc->fpar), | |
230 | in_be32(&lbc->fbcr), priv->bank); | |
231 | ||
1938de46 | 232 | ctrl->irq_status = 0; |
76b10467 SW |
233 | /* execute special operation */ |
234 | out_be32(&lbc->lsor, priv->bank); | |
235 | ||
236 | /* wait for FCM complete flag or timeout */ | |
76b10467 SW |
237 | wait_event_timeout(ctrl->irq_wait, ctrl->irq_status, |
238 | FCM_TIMEOUT_MSECS * HZ/1000); | |
3ab8f2a2 | 239 | elbc_fcm_ctrl->status = ctrl->irq_status; |
76b10467 | 240 | /* store mdr value in case it was needed */ |
3ab8f2a2 RZ |
241 | if (elbc_fcm_ctrl->use_mdr) |
242 | elbc_fcm_ctrl->mdr = in_be32(&lbc->mdr); | |
76b10467 | 243 | |
3ab8f2a2 | 244 | elbc_fcm_ctrl->use_mdr = 0; |
76b10467 | 245 | |
3ab8f2a2 RZ |
246 | if (elbc_fcm_ctrl->status != LTESR_CC) { |
247 | dev_info(priv->dev, | |
c1317f71 SW |
248 | "command failed: fir %x fcr %x status %x mdr %x\n", |
249 | in_be32(&lbc->fir), in_be32(&lbc->fcr), | |
3ab8f2a2 | 250 | elbc_fcm_ctrl->status, elbc_fcm_ctrl->mdr); |
c1317f71 SW |
251 | return -EIO; |
252 | } | |
76b10467 | 253 | |
f975c6bc MH |
254 | if (chip->ecc.mode != NAND_ECC_HW) |
255 | return 0; | |
256 | ||
3f91e94f MD |
257 | elbc_fcm_ctrl->max_bitflips = 0; |
258 | ||
f975c6bc MH |
259 | if (elbc_fcm_ctrl->read_bytes == mtd->writesize + mtd->oobsize) { |
260 | uint32_t lteccr = in_be32(&lbc->lteccr); | |
261 | /* | |
262 | * if command was a full page read and the ELBC | |
263 | * has the LTECCR register, then bits 12-15 (ppc order) of | |
264 | * LTECCR indicates which 512 byte sub-pages had fixed errors. | |
265 | * bits 28-31 are uncorrectable errors, marked elsewhere. | |
266 | * for small page nand only 1 bit is used. | |
267 | * if the ELBC doesn't have the lteccr register it reads 0 | |
3f91e94f MD |
268 | * FIXME: 4 bits can be corrected on NANDs with 2k pages, so |
269 | * count the number of sub-pages with bitflips and update | |
270 | * ecc_stats.corrected accordingly. | |
f975c6bc MH |
271 | */ |
272 | if (lteccr & 0x000F000F) | |
273 | out_be32(&lbc->lteccr, 0x000F000F); /* clear lteccr */ | |
3f91e94f | 274 | if (lteccr & 0x000F0000) { |
f975c6bc | 275 | mtd->ecc_stats.corrected++; |
3f91e94f MD |
276 | elbc_fcm_ctrl->max_bitflips = 1; |
277 | } | |
f975c6bc MH |
278 | } |
279 | ||
c1317f71 | 280 | return 0; |
76b10467 SW |
281 | } |
282 | ||
283 | static void fsl_elbc_do_read(struct nand_chip *chip, int oob) | |
284 | { | |
285 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 286 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
d4a32fe4 | 287 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
288 | |
289 | if (priv->page_size) { | |
290 | out_be32(&lbc->fir, | |
476459a6 | 291 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | |
76b10467 SW |
292 | (FIR_OP_CA << FIR_OP1_SHIFT) | |
293 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
476459a6 | 294 | (FIR_OP_CM1 << FIR_OP3_SHIFT) | |
76b10467 SW |
295 | (FIR_OP_RBW << FIR_OP4_SHIFT)); |
296 | ||
297 | out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | | |
298 | (NAND_CMD_READSTART << FCR_CMD1_SHIFT)); | |
299 | } else { | |
300 | out_be32(&lbc->fir, | |
476459a6 | 301 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | |
76b10467 SW |
302 | (FIR_OP_CA << FIR_OP1_SHIFT) | |
303 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
304 | (FIR_OP_RBW << FIR_OP3_SHIFT)); | |
305 | ||
306 | if (oob) | |
307 | out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT); | |
308 | else | |
309 | out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); | |
310 | } | |
311 | } | |
312 | ||
313 | /* cmdfunc send commands to the FCM */ | |
314 | static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command, | |
315 | int column, int page_addr) | |
316 | { | |
317 | struct nand_chip *chip = mtd->priv; | |
318 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 RZ |
319 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
320 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; | |
d4a32fe4 | 321 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 | 322 | |
3ab8f2a2 | 323 | elbc_fcm_ctrl->use_mdr = 0; |
76b10467 SW |
324 | |
325 | /* clear the read buffer */ | |
3ab8f2a2 | 326 | elbc_fcm_ctrl->read_bytes = 0; |
76b10467 | 327 | if (command != NAND_CMD_PAGEPROG) |
3ab8f2a2 | 328 | elbc_fcm_ctrl->index = 0; |
76b10467 SW |
329 | |
330 | switch (command) { | |
331 | /* READ0 and READ1 read the entire buffer to use hardware ECC. */ | |
332 | case NAND_CMD_READ1: | |
333 | column += 256; | |
334 | ||
335 | /* fall-through */ | |
336 | case NAND_CMD_READ0: | |
3ab8f2a2 | 337 | dev_dbg(priv->dev, |
76b10467 SW |
338 | "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:" |
339 | " 0x%x, column: 0x%x.\n", page_addr, column); | |
340 | ||
341 | ||
342 | out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */ | |
343 | set_addr(mtd, 0, page_addr, 0); | |
344 | ||
3ab8f2a2 RZ |
345 | elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize; |
346 | elbc_fcm_ctrl->index += column; | |
76b10467 SW |
347 | |
348 | fsl_elbc_do_read(chip, 0); | |
349 | fsl_elbc_run_command(mtd); | |
350 | return; | |
351 | ||
352 | /* READOOB reads only the OOB because no ECC is performed. */ | |
353 | case NAND_CMD_READOOB: | |
3ab8f2a2 | 354 | dev_vdbg(priv->dev, |
76b10467 SW |
355 | "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:" |
356 | " 0x%x, column: 0x%x.\n", page_addr, column); | |
357 | ||
358 | out_be32(&lbc->fbcr, mtd->oobsize - column); | |
359 | set_addr(mtd, column, page_addr, 1); | |
360 | ||
3ab8f2a2 | 361 | elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize; |
76b10467 SW |
362 | |
363 | fsl_elbc_do_read(chip, 1); | |
364 | fsl_elbc_run_command(mtd); | |
365 | return; | |
366 | ||
76b10467 | 367 | case NAND_CMD_READID: |
f57eb5cc SL |
368 | case NAND_CMD_PARAM: |
369 | dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD %x\n", command); | |
76b10467 | 370 | |
476459a6 | 371 | out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) | |
76b10467 SW |
372 | (FIR_OP_UA << FIR_OP1_SHIFT) | |
373 | (FIR_OP_RBW << FIR_OP2_SHIFT)); | |
f57eb5cc SL |
374 | out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT); |
375 | /* | |
376 | * although currently it's 8 bytes for READID, we always read | |
377 | * the maximum 256 bytes(for PARAM) | |
378 | */ | |
379 | out_be32(&lbc->fbcr, 256); | |
380 | elbc_fcm_ctrl->read_bytes = 256; | |
3ab8f2a2 | 381 | elbc_fcm_ctrl->use_mdr = 1; |
f57eb5cc | 382 | elbc_fcm_ctrl->mdr = column; |
76b10467 SW |
383 | set_addr(mtd, 0, 0, 0); |
384 | fsl_elbc_run_command(mtd); | |
385 | return; | |
386 | ||
387 | /* ERASE1 stores the block and page address */ | |
388 | case NAND_CMD_ERASE1: | |
3ab8f2a2 | 389 | dev_vdbg(priv->dev, |
76b10467 SW |
390 | "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, " |
391 | "page_addr: 0x%x.\n", page_addr); | |
392 | set_addr(mtd, 0, page_addr, 0); | |
393 | return; | |
394 | ||
395 | /* ERASE2 uses the block and page address from ERASE1 */ | |
396 | case NAND_CMD_ERASE2: | |
3ab8f2a2 | 397 | dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n"); |
76b10467 SW |
398 | |
399 | out_be32(&lbc->fir, | |
476459a6 | 400 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | |
76b10467 | 401 | (FIR_OP_PA << FIR_OP1_SHIFT) | |
476459a6 SW |
402 | (FIR_OP_CM2 << FIR_OP2_SHIFT) | |
403 | (FIR_OP_CW1 << FIR_OP3_SHIFT) | | |
404 | (FIR_OP_RS << FIR_OP4_SHIFT)); | |
76b10467 SW |
405 | |
406 | out_be32(&lbc->fcr, | |
407 | (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) | | |
476459a6 SW |
408 | (NAND_CMD_STATUS << FCR_CMD1_SHIFT) | |
409 | (NAND_CMD_ERASE2 << FCR_CMD2_SHIFT)); | |
76b10467 SW |
410 | |
411 | out_be32(&lbc->fbcr, 0); | |
3ab8f2a2 RZ |
412 | elbc_fcm_ctrl->read_bytes = 0; |
413 | elbc_fcm_ctrl->use_mdr = 1; | |
76b10467 SW |
414 | |
415 | fsl_elbc_run_command(mtd); | |
416 | return; | |
417 | ||
418 | /* SEQIN sets up the addr buffer and all registers except the length */ | |
419 | case NAND_CMD_SEQIN: { | |
420 | __be32 fcr; | |
3ab8f2a2 RZ |
421 | dev_vdbg(priv->dev, |
422 | "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, " | |
76b10467 SW |
423 | "page_addr: 0x%x, column: 0x%x.\n", |
424 | page_addr, column); | |
425 | ||
eeda667a | 426 | elbc_fcm_ctrl->column = column; |
3ab8f2a2 | 427 | elbc_fcm_ctrl->use_mdr = 1; |
76b10467 | 428 | |
a9a552f0 LS |
429 | if (column >= mtd->writesize) { |
430 | /* OOB area */ | |
431 | column -= mtd->writesize; | |
432 | elbc_fcm_ctrl->oob = 1; | |
433 | } else { | |
434 | WARN_ON(column != 0); | |
435 | elbc_fcm_ctrl->oob = 0; | |
436 | } | |
437 | ||
476459a6 SW |
438 | fcr = (NAND_CMD_STATUS << FCR_CMD1_SHIFT) | |
439 | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT) | | |
440 | (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT); | |
57650664 | 441 | |
476459a6 | 442 | if (priv->page_size) { |
76b10467 | 443 | out_be32(&lbc->fir, |
476459a6 | 444 | (FIR_OP_CM2 << FIR_OP0_SHIFT) | |
76b10467 SW |
445 | (FIR_OP_CA << FIR_OP1_SHIFT) | |
446 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
447 | (FIR_OP_WB << FIR_OP3_SHIFT) | | |
476459a6 SW |
448 | (FIR_OP_CM3 << FIR_OP4_SHIFT) | |
449 | (FIR_OP_CW1 << FIR_OP5_SHIFT) | | |
450 | (FIR_OP_RS << FIR_OP6_SHIFT)); | |
76b10467 SW |
451 | } else { |
452 | out_be32(&lbc->fir, | |
476459a6 | 453 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | |
76b10467 SW |
454 | (FIR_OP_CM2 << FIR_OP1_SHIFT) | |
455 | (FIR_OP_CA << FIR_OP2_SHIFT) | | |
456 | (FIR_OP_PA << FIR_OP3_SHIFT) | | |
457 | (FIR_OP_WB << FIR_OP4_SHIFT) | | |
476459a6 SW |
458 | (FIR_OP_CM3 << FIR_OP5_SHIFT) | |
459 | (FIR_OP_CW1 << FIR_OP6_SHIFT) | | |
460 | (FIR_OP_RS << FIR_OP7_SHIFT)); | |
76b10467 | 461 | |
a9a552f0 | 462 | if (elbc_fcm_ctrl->oob) |
76b10467 | 463 | /* OOB area --> READOOB */ |
76b10467 | 464 | fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT; |
a9a552f0 | 465 | else |
76b10467 SW |
466 | /* First 256 bytes --> READ0 */ |
467 | fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT; | |
76b10467 SW |
468 | } |
469 | ||
470 | out_be32(&lbc->fcr, fcr); | |
3ab8f2a2 | 471 | set_addr(mtd, column, page_addr, elbc_fcm_ctrl->oob); |
76b10467 SW |
472 | return; |
473 | } | |
474 | ||
475 | /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ | |
476 | case NAND_CMD_PAGEPROG: { | |
3ab8f2a2 | 477 | dev_vdbg(priv->dev, |
76b10467 | 478 | "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG " |
3ab8f2a2 | 479 | "writing %d bytes.\n", elbc_fcm_ctrl->index); |
76b10467 SW |
480 | |
481 | /* if the write did not start at 0 or is not a full page | |
482 | * then set the exact length, otherwise use a full page | |
483 | * write so the HW generates the ECC. | |
484 | */ | |
3ab8f2a2 | 485 | if (elbc_fcm_ctrl->oob || elbc_fcm_ctrl->column != 0 || |
52a474de | 486 | elbc_fcm_ctrl->index != mtd->writesize + mtd->oobsize) |
e32de766 LS |
487 | out_be32(&lbc->fbcr, |
488 | elbc_fcm_ctrl->index - elbc_fcm_ctrl->column); | |
52a474de | 489 | else |
76b10467 | 490 | out_be32(&lbc->fbcr, 0); |
76b10467 SW |
491 | |
492 | fsl_elbc_run_command(mtd); | |
76b10467 SW |
493 | return; |
494 | } | |
495 | ||
496 | /* CMD_STATUS must read the status byte while CEB is active */ | |
497 | /* Note - it does not wait for the ready line */ | |
498 | case NAND_CMD_STATUS: | |
499 | out_be32(&lbc->fir, | |
500 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | | |
501 | (FIR_OP_RBW << FIR_OP1_SHIFT)); | |
502 | out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); | |
503 | out_be32(&lbc->fbcr, 1); | |
504 | set_addr(mtd, 0, 0, 0); | |
3ab8f2a2 | 505 | elbc_fcm_ctrl->read_bytes = 1; |
76b10467 SW |
506 | |
507 | fsl_elbc_run_command(mtd); | |
508 | ||
509 | /* The chip always seems to report that it is | |
510 | * write-protected, even when it is not. | |
511 | */ | |
3ab8f2a2 | 512 | setbits8(elbc_fcm_ctrl->addr, NAND_STATUS_WP); |
76b10467 SW |
513 | return; |
514 | ||
515 | /* RESET without waiting for the ready line */ | |
516 | case NAND_CMD_RESET: | |
3ab8f2a2 | 517 | dev_dbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n"); |
76b10467 SW |
518 | out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT); |
519 | out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT); | |
520 | fsl_elbc_run_command(mtd); | |
521 | return; | |
522 | ||
523 | default: | |
3ab8f2a2 | 524 | dev_err(priv->dev, |
76b10467 SW |
525 | "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n", |
526 | command); | |
527 | } | |
528 | } | |
529 | ||
530 | static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip) | |
531 | { | |
532 | /* The hardware does not seem to support multiple | |
533 | * chips per bank. | |
534 | */ | |
535 | } | |
536 | ||
537 | /* | |
538 | * Write buf to the FCM Controller Data Buffer | |
539 | */ | |
540 | static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) | |
541 | { | |
542 | struct nand_chip *chip = mtd->priv; | |
543 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 544 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 SW |
545 | unsigned int bufsize = mtd->writesize + mtd->oobsize; |
546 | ||
0ff6631b | 547 | if (len <= 0) { |
3ab8f2a2 RZ |
548 | dev_err(priv->dev, "write_buf of %d bytes", len); |
549 | elbc_fcm_ctrl->status = 0; | |
76b10467 SW |
550 | return; |
551 | } | |
552 | ||
3ab8f2a2 RZ |
553 | if ((unsigned int)len > bufsize - elbc_fcm_ctrl->index) { |
554 | dev_err(priv->dev, | |
76b10467 SW |
555 | "write_buf beyond end of buffer " |
556 | "(%d requested, %u available)\n", | |
3ab8f2a2 RZ |
557 | len, bufsize - elbc_fcm_ctrl->index); |
558 | len = bufsize - elbc_fcm_ctrl->index; | |
76b10467 SW |
559 | } |
560 | ||
3ab8f2a2 | 561 | memcpy_toio(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], buf, len); |
0ff6631b AV |
562 | /* |
563 | * This is workaround for the weird elbc hangs during nand write, | |
564 | * Scott Wood says: "...perhaps difference in how long it takes a | |
565 | * write to make it through the localbus compared to a write to IMMR | |
566 | * is causing problems, and sync isn't helping for some reason." | |
567 | * Reading back the last byte helps though. | |
568 | */ | |
3ab8f2a2 | 569 | in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index] + len - 1); |
0ff6631b | 570 | |
3ab8f2a2 | 571 | elbc_fcm_ctrl->index += len; |
76b10467 SW |
572 | } |
573 | ||
574 | /* | |
575 | * read a byte from either the FCM hardware buffer if it has any data left | |
576 | * otherwise issue a command to read a single byte. | |
577 | */ | |
578 | static u8 fsl_elbc_read_byte(struct mtd_info *mtd) | |
579 | { | |
580 | struct nand_chip *chip = mtd->priv; | |
581 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 582 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 SW |
583 | |
584 | /* If there are still bytes in the FCM, then use the next byte. */ | |
3ab8f2a2 RZ |
585 | if (elbc_fcm_ctrl->index < elbc_fcm_ctrl->read_bytes) |
586 | return in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index++]); | |
76b10467 | 587 | |
3ab8f2a2 | 588 | dev_err(priv->dev, "read_byte beyond end of buffer\n"); |
76b10467 SW |
589 | return ERR_BYTE; |
590 | } | |
591 | ||
592 | /* | |
593 | * Read from the FCM Controller Data Buffer | |
594 | */ | |
595 | static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len) | |
596 | { | |
597 | struct nand_chip *chip = mtd->priv; | |
598 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 599 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 SW |
600 | int avail; |
601 | ||
602 | if (len < 0) | |
603 | return; | |
604 | ||
3ab8f2a2 RZ |
605 | avail = min((unsigned int)len, |
606 | elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index); | |
607 | memcpy_fromio(buf, &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], avail); | |
608 | elbc_fcm_ctrl->index += avail; | |
76b10467 SW |
609 | |
610 | if (len > avail) | |
3ab8f2a2 | 611 | dev_err(priv->dev, |
76b10467 SW |
612 | "read_buf beyond end of buffer " |
613 | "(%d requested, %d available)\n", | |
614 | len, avail); | |
615 | } | |
616 | ||
76b10467 SW |
617 | /* This function is called after Program and Erase Operations to |
618 | * check for success or failure. | |
619 | */ | |
620 | static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
621 | { | |
622 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 623 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 | 624 | |
3ab8f2a2 | 625 | if (elbc_fcm_ctrl->status != LTESR_CC) |
76b10467 SW |
626 | return NAND_STATUS_FAIL; |
627 | ||
628 | /* The chip always seems to report that it is | |
629 | * write-protected, even when it is not. | |
630 | */ | |
3ab8f2a2 | 631 | return (elbc_fcm_ctrl->mdr & 0xff) | NAND_STATUS_WP; |
76b10467 SW |
632 | } |
633 | ||
634 | static int fsl_elbc_chip_init_tail(struct mtd_info *mtd) | |
635 | { | |
636 | struct nand_chip *chip = mtd->priv; | |
637 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 638 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
d4a32fe4 | 639 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
640 | unsigned int al; |
641 | ||
642 | /* calculate FMR Address Length field */ | |
643 | al = 0; | |
644 | if (chip->pagemask & 0xffff0000) | |
645 | al++; | |
646 | if (chip->pagemask & 0xff000000) | |
647 | al++; | |
648 | ||
d8251108 | 649 | priv->fmr |= al << FMR_AL_SHIFT; |
76b10467 | 650 | |
3ab8f2a2 | 651 | dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n", |
76b10467 | 652 | chip->numchips); |
3ab8f2a2 | 653 | dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n", |
76b10467 | 654 | chip->chipsize); |
3ab8f2a2 | 655 | dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n", |
76b10467 | 656 | chip->pagemask); |
3ab8f2a2 | 657 | dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_delay = %d\n", |
76b10467 | 658 | chip->chip_delay); |
3ab8f2a2 | 659 | dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n", |
76b10467 | 660 | chip->badblockpos); |
3ab8f2a2 | 661 | dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n", |
76b10467 | 662 | chip->chip_shift); |
3ab8f2a2 | 663 | dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n", |
76b10467 | 664 | chip->page_shift); |
3ab8f2a2 | 665 | dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n", |
76b10467 | 666 | chip->phys_erase_shift); |
3ab8f2a2 | 667 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecclayout = %p\n", |
76b10467 | 668 | chip->ecclayout); |
3ab8f2a2 | 669 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n", |
76b10467 | 670 | chip->ecc.mode); |
3ab8f2a2 | 671 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n", |
76b10467 | 672 | chip->ecc.steps); |
3ab8f2a2 | 673 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n", |
76b10467 | 674 | chip->ecc.bytes); |
3ab8f2a2 | 675 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n", |
76b10467 | 676 | chip->ecc.total); |
3ab8f2a2 | 677 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.layout = %p\n", |
76b10467 | 678 | chip->ecc.layout); |
3ab8f2a2 RZ |
679 | dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags); |
680 | dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size); | |
681 | dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n", | |
76b10467 | 682 | mtd->erasesize); |
3ab8f2a2 | 683 | dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n", |
76b10467 | 684 | mtd->writesize); |
3ab8f2a2 | 685 | dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n", |
76b10467 SW |
686 | mtd->oobsize); |
687 | ||
688 | /* adjust Option Register and ECC to match Flash page size */ | |
689 | if (mtd->writesize == 512) { | |
690 | priv->page_size = 0; | |
1938de46 | 691 | clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); |
76b10467 SW |
692 | } else if (mtd->writesize == 2048) { |
693 | priv->page_size = 1; | |
694 | setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); | |
695 | /* adjust ecc setup if needed */ | |
696 | if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) == | |
697 | BR_DECC_CHK_GEN) { | |
698 | chip->ecc.size = 512; | |
699 | chip->ecc.layout = (priv->fmr & FMR_ECCM) ? | |
700 | &fsl_elbc_oob_lp_eccm1 : | |
701 | &fsl_elbc_oob_lp_eccm0; | |
452db272 | 702 | chip->badblock_pattern = &largepage_memorybased; |
76b10467 SW |
703 | } |
704 | } else { | |
3ab8f2a2 | 705 | dev_err(priv->dev, |
76b10467 SW |
706 | "fsl_elbc_init: page size %d is not supported\n", |
707 | mtd->writesize); | |
708 | return -1; | |
709 | } | |
710 | ||
76b10467 SW |
711 | return 0; |
712 | } | |
713 | ||
1fbb938d BN |
714 | static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip, |
715 | uint8_t *buf, int oob_required, int page) | |
76b10467 | 716 | { |
3f91e94f MD |
717 | struct fsl_elbc_mtd *priv = chip->priv; |
718 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; | |
719 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; | |
720 | ||
76b10467 | 721 | fsl_elbc_read_buf(mtd, buf, mtd->writesize); |
d112dc7f BN |
722 | if (oob_required) |
723 | fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
76b10467 SW |
724 | |
725 | if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL) | |
726 | mtd->ecc_stats.failed++; | |
727 | ||
3f91e94f | 728 | return elbc_fcm_ctrl->max_bitflips; |
76b10467 SW |
729 | } |
730 | ||
731 | /* ECC will be calculated automatically, and errors will be detected in | |
732 | * waitfunc. | |
733 | */ | |
fdbad98d | 734 | static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 735 | const uint8_t *buf, int oob_required) |
76b10467 | 736 | { |
76b10467 SW |
737 | fsl_elbc_write_buf(mtd, buf, mtd->writesize); |
738 | fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
739 | |
740 | return 0; | |
76b10467 SW |
741 | } |
742 | ||
743 | static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv) | |
744 | { | |
3ab8f2a2 | 745 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
d4a32fe4 | 746 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
3ab8f2a2 | 747 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; |
76b10467 SW |
748 | struct nand_chip *chip = &priv->chip; |
749 | ||
750 | dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank); | |
751 | ||
752 | /* Fill in fsl_elbc_mtd structure */ | |
753 | priv->mtd.priv = chip; | |
754 | priv->mtd.owner = THIS_MODULE; | |
03ed1078 | 755 | |
d8251108 SL |
756 | /* set timeout to maximum */ |
757 | priv->fmr = 15 << FMR_CWTO_SHIFT; | |
758 | if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS) | |
759 | priv->fmr |= FMR_ECCM; | |
76b10467 SW |
760 | |
761 | /* fill in nand_chip structure */ | |
762 | /* set up function call table */ | |
763 | chip->read_byte = fsl_elbc_read_byte; | |
764 | chip->write_buf = fsl_elbc_write_buf; | |
765 | chip->read_buf = fsl_elbc_read_buf; | |
76b10467 SW |
766 | chip->select_chip = fsl_elbc_select_chip; |
767 | chip->cmdfunc = fsl_elbc_cmdfunc; | |
768 | chip->waitfunc = fsl_elbc_wait; | |
769 | ||
ec6e0ea3 AV |
770 | chip->bbt_td = &bbt_main_descr; |
771 | chip->bbt_md = &bbt_mirror_descr; | |
772 | ||
76b10467 | 773 | /* set up nand options */ |
bb9ebd4e | 774 | chip->bbt_options = NAND_BBT_USE_FLASH; |
76b10467 | 775 | |
3ab8f2a2 | 776 | chip->controller = &elbc_fcm_ctrl->controller; |
76b10467 SW |
777 | chip->priv = priv; |
778 | ||
779 | chip->ecc.read_page = fsl_elbc_read_page; | |
780 | chip->ecc.write_page = fsl_elbc_write_page; | |
781 | ||
782 | /* If CS Base Register selects full hardware ECC then use it */ | |
783 | if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) == | |
784 | BR_DECC_CHK_GEN) { | |
785 | chip->ecc.mode = NAND_ECC_HW; | |
786 | /* put in small page settings and adjust later if needed */ | |
787 | chip->ecc.layout = (priv->fmr & FMR_ECCM) ? | |
788 | &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0; | |
789 | chip->ecc.size = 512; | |
790 | chip->ecc.bytes = 3; | |
6a918bad | 791 | chip->ecc.strength = 1; |
76b10467 SW |
792 | } else { |
793 | /* otherwise fall back to default software ECC */ | |
794 | chip->ecc.mode = NAND_ECC_SOFT; | |
795 | } | |
796 | ||
797 | return 0; | |
798 | } | |
799 | ||
800 | static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv) | |
801 | { | |
3ab8f2a2 | 802 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 SW |
803 | nand_release(&priv->mtd); |
804 | ||
9ebed3e6 AV |
805 | kfree(priv->mtd.name); |
806 | ||
76b10467 SW |
807 | if (priv->vbase) |
808 | iounmap(priv->vbase); | |
809 | ||
3ab8f2a2 | 810 | elbc_fcm_ctrl->chips[priv->bank] = NULL; |
76b10467 | 811 | kfree(priv); |
76b10467 SW |
812 | return 0; |
813 | } | |
814 | ||
3ab8f2a2 RZ |
815 | static DEFINE_MUTEX(fsl_elbc_nand_mutex); |
816 | ||
817 | static int __devinit fsl_elbc_nand_probe(struct platform_device *pdev) | |
76b10467 | 818 | { |
3ab8f2a2 | 819 | struct fsl_lbc_regs __iomem *lbc; |
76b10467 SW |
820 | struct fsl_elbc_mtd *priv; |
821 | struct resource res; | |
3ab8f2a2 | 822 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl; |
76b10467 | 823 | static const char *part_probe_types[] |
b6b0fae7 | 824 | = { "cmdlinepart", "RedBoot", "ofpart", NULL }; |
76b10467 SW |
825 | int ret; |
826 | int bank; | |
3ab8f2a2 RZ |
827 | struct device *dev; |
828 | struct device_node *node = pdev->dev.of_node; | |
b6b0fae7 | 829 | struct mtd_part_parser_data ppdata; |
3ab8f2a2 | 830 | |
b6b0fae7 | 831 | ppdata.of_node = pdev->dev.of_node; |
3ab8f2a2 RZ |
832 | if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs) |
833 | return -ENODEV; | |
834 | lbc = fsl_lbc_ctrl_dev->regs; | |
835 | dev = fsl_lbc_ctrl_dev->dev; | |
76b10467 SW |
836 | |
837 | /* get, allocate and map the memory resource */ | |
838 | ret = of_address_to_resource(node, 0, &res); | |
839 | if (ret) { | |
3ab8f2a2 | 840 | dev_err(dev, "failed to get resource\n"); |
76b10467 SW |
841 | return ret; |
842 | } | |
843 | ||
844 | /* find which chip select it is connected to */ | |
845 | for (bank = 0; bank < MAX_BANKS; bank++) | |
846 | if ((in_be32(&lbc->bank[bank].br) & BR_V) && | |
847 | (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM && | |
848 | (in_be32(&lbc->bank[bank].br) & | |
849 | in_be32(&lbc->bank[bank].or) & BR_BA) | |
0b824d2b | 850 | == fsl_lbc_addr(res.start)) |
76b10467 SW |
851 | break; |
852 | ||
853 | if (bank >= MAX_BANKS) { | |
3ab8f2a2 | 854 | dev_err(dev, "address did not match any chip selects\n"); |
76b10467 SW |
855 | return -ENODEV; |
856 | } | |
857 | ||
858 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
859 | if (!priv) | |
860 | return -ENOMEM; | |
861 | ||
3ab8f2a2 RZ |
862 | mutex_lock(&fsl_elbc_nand_mutex); |
863 | if (!fsl_lbc_ctrl_dev->nand) { | |
864 | elbc_fcm_ctrl = kzalloc(sizeof(*elbc_fcm_ctrl), GFP_KERNEL); | |
865 | if (!elbc_fcm_ctrl) { | |
866 | dev_err(dev, "failed to allocate memory\n"); | |
867 | mutex_unlock(&fsl_elbc_nand_mutex); | |
868 | ret = -ENOMEM; | |
869 | goto err; | |
870 | } | |
871 | elbc_fcm_ctrl->counter++; | |
872 | ||
873 | spin_lock_init(&elbc_fcm_ctrl->controller.lock); | |
874 | init_waitqueue_head(&elbc_fcm_ctrl->controller.wq); | |
875 | fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl; | |
876 | } else { | |
877 | elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand; | |
878 | } | |
879 | mutex_unlock(&fsl_elbc_nand_mutex); | |
880 | ||
881 | elbc_fcm_ctrl->chips[bank] = priv; | |
76b10467 | 882 | priv->bank = bank; |
3ab8f2a2 | 883 | priv->ctrl = fsl_lbc_ctrl_dev; |
874d72c4 SW |
884 | priv->dev = &pdev->dev; |
885 | dev_set_drvdata(priv->dev, priv); | |
76b10467 | 886 | |
8a19b558 | 887 | priv->vbase = ioremap(res.start, resource_size(&res)); |
76b10467 | 888 | if (!priv->vbase) { |
3ab8f2a2 | 889 | dev_err(dev, "failed to map chip region\n"); |
76b10467 SW |
890 | ret = -ENOMEM; |
891 | goto err; | |
892 | } | |
893 | ||
650da9d0 | 894 | priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start); |
9ebed3e6 AV |
895 | if (!priv->mtd.name) { |
896 | ret = -ENOMEM; | |
897 | goto err; | |
898 | } | |
899 | ||
76b10467 SW |
900 | ret = fsl_elbc_chip_init(priv); |
901 | if (ret) | |
902 | goto err; | |
903 | ||
5e81e88a | 904 | ret = nand_scan_ident(&priv->mtd, 1, NULL); |
76b10467 SW |
905 | if (ret) |
906 | goto err; | |
907 | ||
908 | ret = fsl_elbc_chip_init_tail(&priv->mtd); | |
909 | if (ret) | |
910 | goto err; | |
911 | ||
912 | ret = nand_scan_tail(&priv->mtd); | |
913 | if (ret) | |
914 | goto err; | |
915 | ||
76b10467 SW |
916 | /* First look for RedBoot table or partitions on the command |
917 | * line, these take precedence over device tree information */ | |
99add422 DES |
918 | mtd_device_parse_register(&priv->mtd, part_probe_types, &ppdata, |
919 | NULL, 0); | |
76b10467 | 920 | |
4712fff9 SR |
921 | printk(KERN_INFO "eLBC NAND device at 0x%llx, bank %d\n", |
922 | (unsigned long long)res.start, priv->bank); | |
76b10467 SW |
923 | return 0; |
924 | ||
925 | err: | |
926 | fsl_elbc_chip_remove(priv); | |
927 | return ret; | |
928 | } | |
929 | ||
3ab8f2a2 | 930 | static int fsl_elbc_nand_remove(struct platform_device *pdev) |
76b10467 | 931 | { |
3ab8f2a2 | 932 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand; |
874d72c4 SW |
933 | struct fsl_elbc_mtd *priv = dev_get_drvdata(&pdev->dev); |
934 | ||
935 | fsl_elbc_chip_remove(priv); | |
3ab8f2a2 RZ |
936 | |
937 | mutex_lock(&fsl_elbc_nand_mutex); | |
938 | elbc_fcm_ctrl->counter--; | |
939 | if (!elbc_fcm_ctrl->counter) { | |
940 | fsl_lbc_ctrl_dev->nand = NULL; | |
941 | kfree(elbc_fcm_ctrl); | |
76b10467 | 942 | } |
3ab8f2a2 | 943 | mutex_unlock(&fsl_elbc_nand_mutex); |
76b10467 SW |
944 | |
945 | return 0; | |
946 | ||
76b10467 SW |
947 | } |
948 | ||
3ab8f2a2 RZ |
949 | static const struct of_device_id fsl_elbc_nand_match[] = { |
950 | { .compatible = "fsl,elbc-fcm-nand", }, | |
76b10467 SW |
951 | {} |
952 | }; | |
953 | ||
3ab8f2a2 | 954 | static struct platform_driver fsl_elbc_nand_driver = { |
76b10467 | 955 | .driver = { |
3ab8f2a2 | 956 | .name = "fsl,elbc-fcm-nand", |
4018294b | 957 | .owner = THIS_MODULE, |
3ab8f2a2 | 958 | .of_match_table = fsl_elbc_nand_match, |
76b10467 | 959 | }, |
3ab8f2a2 RZ |
960 | .probe = fsl_elbc_nand_probe, |
961 | .remove = fsl_elbc_nand_remove, | |
76b10467 SW |
962 | }; |
963 | ||
f99640de | 964 | module_platform_driver(fsl_elbc_nand_driver); |
76b10467 SW |
965 | |
966 | MODULE_LICENSE("GPL"); | |
967 | MODULE_AUTHOR("Freescale"); | |
968 | MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver"); |