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76b10467 SW |
1 | /* Freescale Enhanced Local Bus Controller NAND driver |
2 | * | |
3 | * Copyright (c) 2006-2007 Freescale Semiconductor | |
4 | * | |
5 | * Authors: Nick Spence <nick.spence@freescale.com>, | |
6 | * Scott Wood <scottwood@freescale.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <linux/module.h> | |
24 | #include <linux/types.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/string.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/of_platform.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/interrupt.h> | |
32 | ||
33 | #include <linux/mtd/mtd.h> | |
34 | #include <linux/mtd/nand.h> | |
35 | #include <linux/mtd/nand_ecc.h> | |
36 | #include <linux/mtd/partitions.h> | |
37 | ||
38 | #include <asm/io.h> | |
d4a32fe4 | 39 | #include <asm/fsl_lbc.h> |
76b10467 SW |
40 | |
41 | #define MAX_BANKS 8 | |
42 | #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ | |
43 | #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */ | |
44 | ||
76b10467 SW |
45 | struct fsl_elbc_ctrl; |
46 | ||
47 | /* mtd information per set */ | |
48 | ||
49 | struct fsl_elbc_mtd { | |
50 | struct mtd_info mtd; | |
51 | struct nand_chip chip; | |
52 | struct fsl_elbc_ctrl *ctrl; | |
53 | ||
54 | struct device *dev; | |
55 | int bank; /* Chip select bank number */ | |
56 | u8 __iomem *vbase; /* Chip select base virtual address */ | |
57 | int page_size; /* NAND page size (0=512, 1=2048) */ | |
58 | unsigned int fmr; /* FCM Flash Mode Register value */ | |
59 | }; | |
60 | ||
61 | /* overview of the fsl elbc controller */ | |
62 | ||
63 | struct fsl_elbc_ctrl { | |
64 | struct nand_hw_control controller; | |
65 | struct fsl_elbc_mtd *chips[MAX_BANKS]; | |
66 | ||
67 | /* device info */ | |
68 | struct device *dev; | |
d4a32fe4 | 69 | struct fsl_lbc_regs __iomem *regs; |
76b10467 SW |
70 | int irq; |
71 | wait_queue_head_t irq_wait; | |
72 | unsigned int irq_status; /* status read from LTESR by irq handler */ | |
73 | u8 __iomem *addr; /* Address of assigned FCM buffer */ | |
74 | unsigned int page; /* Last page written to / read from */ | |
75 | unsigned int read_bytes; /* Number of bytes read during command */ | |
76 | unsigned int column; /* Saved column from SEQIN */ | |
77 | unsigned int index; /* Pointer to next byte to 'read' */ | |
78 | unsigned int status; /* status read from LTESR after last op */ | |
79 | unsigned int mdr; /* UPM/FCM Data Register value */ | |
80 | unsigned int use_mdr; /* Non zero if the MDR is to be set */ | |
81 | unsigned int oob; /* Non zero if operating on OOB data */ | |
82 | char *oob_poi; /* Place to write ECC after read back */ | |
83 | }; | |
84 | ||
85 | /* These map to the positions used by the FCM hardware ECC generator */ | |
86 | ||
87 | /* Small Page FLASH with FMR[ECCM] = 0 */ | |
88 | static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = { | |
89 | .eccbytes = 3, | |
90 | .eccpos = {6, 7, 8}, | |
91 | .oobfree = { {0, 5}, {9, 7} }, | |
76b10467 SW |
92 | }; |
93 | ||
94 | /* Small Page FLASH with FMR[ECCM] = 1 */ | |
95 | static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = { | |
96 | .eccbytes = 3, | |
97 | .eccpos = {8, 9, 10}, | |
98 | .oobfree = { {0, 5}, {6, 2}, {11, 5} }, | |
76b10467 SW |
99 | }; |
100 | ||
101 | /* Large Page FLASH with FMR[ECCM] = 0 */ | |
102 | static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = { | |
103 | .eccbytes = 12, | |
104 | .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56}, | |
105 | .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} }, | |
76b10467 SW |
106 | }; |
107 | ||
108 | /* Large Page FLASH with FMR[ECCM] = 1 */ | |
109 | static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = { | |
110 | .eccbytes = 12, | |
111 | .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, | |
112 | .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} }, | |
76b10467 SW |
113 | }; |
114 | ||
452db272 AV |
115 | /* |
116 | * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset | |
117 | * 1, so we have to adjust bad block pattern. This pattern should be used for | |
118 | * x8 chips only. So far hardware does not support x16 chips anyway. | |
119 | */ | |
120 | static u8 scan_ff_pattern[] = { 0xff, }; | |
121 | ||
122 | static struct nand_bbt_descr largepage_memorybased = { | |
123 | .options = 0, | |
124 | .offs = 0, | |
125 | .len = 1, | |
126 | .pattern = scan_ff_pattern, | |
127 | }; | |
128 | ||
ec6e0ea3 AV |
129 | /* |
130 | * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt, | |
131 | * interfere with ECC positions, that's why we implement our own descriptors. | |
132 | * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0. | |
133 | */ | |
134 | static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; | |
135 | static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; | |
136 | ||
137 | static struct nand_bbt_descr bbt_main_descr = { | |
138 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | | |
139 | NAND_BBT_2BIT | NAND_BBT_VERSION, | |
140 | .offs = 11, | |
141 | .len = 4, | |
142 | .veroffs = 15, | |
143 | .maxblocks = 4, | |
144 | .pattern = bbt_pattern, | |
145 | }; | |
146 | ||
147 | static struct nand_bbt_descr bbt_mirror_descr = { | |
148 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | | |
149 | NAND_BBT_2BIT | NAND_BBT_VERSION, | |
150 | .offs = 11, | |
151 | .len = 4, | |
152 | .veroffs = 15, | |
153 | .maxblocks = 4, | |
154 | .pattern = mirror_pattern, | |
155 | }; | |
156 | ||
76b10467 SW |
157 | /*=================================*/ |
158 | ||
159 | /* | |
160 | * Set up the FCM hardware block and page address fields, and the fcm | |
161 | * structure addr field to point to the correct FCM buffer in memory | |
162 | */ | |
163 | static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) | |
164 | { | |
165 | struct nand_chip *chip = mtd->priv; | |
166 | struct fsl_elbc_mtd *priv = chip->priv; | |
167 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
d4a32fe4 | 168 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
169 | int buf_num; |
170 | ||
171 | ctrl->page = page_addr; | |
172 | ||
173 | out_be32(&lbc->fbar, | |
174 | page_addr >> (chip->phys_erase_shift - chip->page_shift)); | |
175 | ||
176 | if (priv->page_size) { | |
177 | out_be32(&lbc->fpar, | |
178 | ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) | | |
179 | (oob ? FPAR_LP_MS : 0) | column); | |
180 | buf_num = (page_addr & 1) << 2; | |
181 | } else { | |
182 | out_be32(&lbc->fpar, | |
183 | ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) | | |
184 | (oob ? FPAR_SP_MS : 0) | column); | |
185 | buf_num = page_addr & 7; | |
186 | } | |
187 | ||
188 | ctrl->addr = priv->vbase + buf_num * 1024; | |
189 | ctrl->index = column; | |
190 | ||
191 | /* for OOB data point to the second half of the buffer */ | |
192 | if (oob) | |
193 | ctrl->index += priv->page_size ? 2048 : 512; | |
194 | ||
195 | dev_vdbg(ctrl->dev, "set_addr: bank=%d, ctrl->addr=0x%p (0x%p), " | |
196 | "index %x, pes %d ps %d\n", | |
197 | buf_num, ctrl->addr, priv->vbase, ctrl->index, | |
198 | chip->phys_erase_shift, chip->page_shift); | |
199 | } | |
200 | ||
201 | /* | |
202 | * execute FCM command and wait for it to complete | |
203 | */ | |
204 | static int fsl_elbc_run_command(struct mtd_info *mtd) | |
205 | { | |
206 | struct nand_chip *chip = mtd->priv; | |
207 | struct fsl_elbc_mtd *priv = chip->priv; | |
208 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
d4a32fe4 | 209 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
210 | |
211 | /* Setup the FMR[OP] to execute without write protection */ | |
212 | out_be32(&lbc->fmr, priv->fmr | 3); | |
213 | if (ctrl->use_mdr) | |
214 | out_be32(&lbc->mdr, ctrl->mdr); | |
215 | ||
216 | dev_vdbg(ctrl->dev, | |
217 | "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n", | |
218 | in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr)); | |
219 | dev_vdbg(ctrl->dev, | |
220 | "fsl_elbc_run_command: fbar=%08x fpar=%08x " | |
221 | "fbcr=%08x bank=%d\n", | |
222 | in_be32(&lbc->fbar), in_be32(&lbc->fpar), | |
223 | in_be32(&lbc->fbcr), priv->bank); | |
224 | ||
1938de46 | 225 | ctrl->irq_status = 0; |
76b10467 SW |
226 | /* execute special operation */ |
227 | out_be32(&lbc->lsor, priv->bank); | |
228 | ||
229 | /* wait for FCM complete flag or timeout */ | |
76b10467 SW |
230 | wait_event_timeout(ctrl->irq_wait, ctrl->irq_status, |
231 | FCM_TIMEOUT_MSECS * HZ/1000); | |
232 | ctrl->status = ctrl->irq_status; | |
233 | ||
234 | /* store mdr value in case it was needed */ | |
235 | if (ctrl->use_mdr) | |
236 | ctrl->mdr = in_be32(&lbc->mdr); | |
237 | ||
238 | ctrl->use_mdr = 0; | |
239 | ||
240 | dev_vdbg(ctrl->dev, | |
241 | "fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n", | |
242 | ctrl->status, ctrl->mdr, in_be32(&lbc->fmr)); | |
243 | ||
244 | /* returns 0 on success otherwise non-zero) */ | |
245 | return ctrl->status == LTESR_CC ? 0 : -EIO; | |
246 | } | |
247 | ||
248 | static void fsl_elbc_do_read(struct nand_chip *chip, int oob) | |
249 | { | |
250 | struct fsl_elbc_mtd *priv = chip->priv; | |
251 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
d4a32fe4 | 252 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
253 | |
254 | if (priv->page_size) { | |
255 | out_be32(&lbc->fir, | |
256 | (FIR_OP_CW0 << FIR_OP0_SHIFT) | | |
257 | (FIR_OP_CA << FIR_OP1_SHIFT) | | |
258 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
259 | (FIR_OP_CW1 << FIR_OP3_SHIFT) | | |
260 | (FIR_OP_RBW << FIR_OP4_SHIFT)); | |
261 | ||
262 | out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | | |
263 | (NAND_CMD_READSTART << FCR_CMD1_SHIFT)); | |
264 | } else { | |
265 | out_be32(&lbc->fir, | |
266 | (FIR_OP_CW0 << FIR_OP0_SHIFT) | | |
267 | (FIR_OP_CA << FIR_OP1_SHIFT) | | |
268 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
269 | (FIR_OP_RBW << FIR_OP3_SHIFT)); | |
270 | ||
271 | if (oob) | |
272 | out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT); | |
273 | else | |
274 | out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); | |
275 | } | |
276 | } | |
277 | ||
278 | /* cmdfunc send commands to the FCM */ | |
279 | static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command, | |
280 | int column, int page_addr) | |
281 | { | |
282 | struct nand_chip *chip = mtd->priv; | |
283 | struct fsl_elbc_mtd *priv = chip->priv; | |
284 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
d4a32fe4 | 285 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
286 | |
287 | ctrl->use_mdr = 0; | |
288 | ||
289 | /* clear the read buffer */ | |
290 | ctrl->read_bytes = 0; | |
291 | if (command != NAND_CMD_PAGEPROG) | |
292 | ctrl->index = 0; | |
293 | ||
294 | switch (command) { | |
295 | /* READ0 and READ1 read the entire buffer to use hardware ECC. */ | |
296 | case NAND_CMD_READ1: | |
297 | column += 256; | |
298 | ||
299 | /* fall-through */ | |
300 | case NAND_CMD_READ0: | |
301 | dev_dbg(ctrl->dev, | |
302 | "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:" | |
303 | " 0x%x, column: 0x%x.\n", page_addr, column); | |
304 | ||
305 | ||
306 | out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */ | |
307 | set_addr(mtd, 0, page_addr, 0); | |
308 | ||
309 | ctrl->read_bytes = mtd->writesize + mtd->oobsize; | |
310 | ctrl->index += column; | |
311 | ||
312 | fsl_elbc_do_read(chip, 0); | |
313 | fsl_elbc_run_command(mtd); | |
314 | return; | |
315 | ||
316 | /* READOOB reads only the OOB because no ECC is performed. */ | |
317 | case NAND_CMD_READOOB: | |
318 | dev_vdbg(ctrl->dev, | |
319 | "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:" | |
320 | " 0x%x, column: 0x%x.\n", page_addr, column); | |
321 | ||
322 | out_be32(&lbc->fbcr, mtd->oobsize - column); | |
323 | set_addr(mtd, column, page_addr, 1); | |
324 | ||
325 | ctrl->read_bytes = mtd->writesize + mtd->oobsize; | |
326 | ||
327 | fsl_elbc_do_read(chip, 1); | |
328 | fsl_elbc_run_command(mtd); | |
329 | return; | |
330 | ||
331 | /* READID must read all 5 possible bytes while CEB is active */ | |
332 | case NAND_CMD_READID: | |
333 | dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n"); | |
334 | ||
335 | out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) | | |
336 | (FIR_OP_UA << FIR_OP1_SHIFT) | | |
337 | (FIR_OP_RBW << FIR_OP2_SHIFT)); | |
338 | out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT); | |
339 | /* 5 bytes for manuf, device and exts */ | |
340 | out_be32(&lbc->fbcr, 5); | |
341 | ctrl->read_bytes = 5; | |
342 | ctrl->use_mdr = 1; | |
343 | ctrl->mdr = 0; | |
344 | ||
345 | set_addr(mtd, 0, 0, 0); | |
346 | fsl_elbc_run_command(mtd); | |
347 | return; | |
348 | ||
349 | /* ERASE1 stores the block and page address */ | |
350 | case NAND_CMD_ERASE1: | |
351 | dev_vdbg(ctrl->dev, | |
352 | "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, " | |
353 | "page_addr: 0x%x.\n", page_addr); | |
354 | set_addr(mtd, 0, page_addr, 0); | |
355 | return; | |
356 | ||
357 | /* ERASE2 uses the block and page address from ERASE1 */ | |
358 | case NAND_CMD_ERASE2: | |
359 | dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n"); | |
360 | ||
361 | out_be32(&lbc->fir, | |
362 | (FIR_OP_CW0 << FIR_OP0_SHIFT) | | |
363 | (FIR_OP_PA << FIR_OP1_SHIFT) | | |
364 | (FIR_OP_CM1 << FIR_OP2_SHIFT)); | |
365 | ||
366 | out_be32(&lbc->fcr, | |
367 | (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) | | |
368 | (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT)); | |
369 | ||
370 | out_be32(&lbc->fbcr, 0); | |
371 | ctrl->read_bytes = 0; | |
372 | ||
373 | fsl_elbc_run_command(mtd); | |
374 | return; | |
375 | ||
376 | /* SEQIN sets up the addr buffer and all registers except the length */ | |
377 | case NAND_CMD_SEQIN: { | |
378 | __be32 fcr; | |
379 | dev_vdbg(ctrl->dev, | |
380 | "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, " | |
381 | "page_addr: 0x%x, column: 0x%x.\n", | |
382 | page_addr, column); | |
383 | ||
384 | ctrl->column = column; | |
385 | ctrl->oob = 0; | |
386 | ||
76b10467 | 387 | if (priv->page_size) { |
57650664 SW |
388 | fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) | |
389 | (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT); | |
390 | ||
76b10467 SW |
391 | out_be32(&lbc->fir, |
392 | (FIR_OP_CW0 << FIR_OP0_SHIFT) | | |
393 | (FIR_OP_CA << FIR_OP1_SHIFT) | | |
394 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
395 | (FIR_OP_WB << FIR_OP3_SHIFT) | | |
396 | (FIR_OP_CW1 << FIR_OP4_SHIFT)); | |
76b10467 | 397 | } else { |
57650664 SW |
398 | fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) | |
399 | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT); | |
400 | ||
76b10467 SW |
401 | out_be32(&lbc->fir, |
402 | (FIR_OP_CW0 << FIR_OP0_SHIFT) | | |
403 | (FIR_OP_CM2 << FIR_OP1_SHIFT) | | |
404 | (FIR_OP_CA << FIR_OP2_SHIFT) | | |
405 | (FIR_OP_PA << FIR_OP3_SHIFT) | | |
406 | (FIR_OP_WB << FIR_OP4_SHIFT) | | |
407 | (FIR_OP_CW1 << FIR_OP5_SHIFT)); | |
408 | ||
409 | if (column >= mtd->writesize) { | |
410 | /* OOB area --> READOOB */ | |
411 | column -= mtd->writesize; | |
412 | fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT; | |
413 | ctrl->oob = 1; | |
414 | } else if (column < 256) { | |
415 | /* First 256 bytes --> READ0 */ | |
416 | fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT; | |
417 | } else { | |
418 | /* Second 256 bytes --> READ1 */ | |
419 | fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT; | |
420 | } | |
421 | } | |
422 | ||
423 | out_be32(&lbc->fcr, fcr); | |
424 | set_addr(mtd, column, page_addr, ctrl->oob); | |
425 | return; | |
426 | } | |
427 | ||
428 | /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ | |
429 | case NAND_CMD_PAGEPROG: { | |
430 | int full_page; | |
431 | dev_vdbg(ctrl->dev, | |
432 | "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG " | |
433 | "writing %d bytes.\n", ctrl->index); | |
434 | ||
435 | /* if the write did not start at 0 or is not a full page | |
436 | * then set the exact length, otherwise use a full page | |
437 | * write so the HW generates the ECC. | |
438 | */ | |
439 | if (ctrl->oob || ctrl->column != 0 || | |
440 | ctrl->index != mtd->writesize + mtd->oobsize) { | |
441 | out_be32(&lbc->fbcr, ctrl->index); | |
442 | full_page = 0; | |
443 | } else { | |
444 | out_be32(&lbc->fbcr, 0); | |
445 | full_page = 1; | |
446 | } | |
447 | ||
448 | fsl_elbc_run_command(mtd); | |
449 | ||
450 | /* Read back the page in order to fill in the ECC for the | |
451 | * caller. Is this really needed? | |
452 | */ | |
453 | if (full_page && ctrl->oob_poi) { | |
454 | out_be32(&lbc->fbcr, 3); | |
455 | set_addr(mtd, 6, page_addr, 1); | |
456 | ||
457 | ctrl->read_bytes = mtd->writesize + 9; | |
458 | ||
459 | fsl_elbc_do_read(chip, 1); | |
460 | fsl_elbc_run_command(mtd); | |
461 | ||
462 | memcpy_fromio(ctrl->oob_poi + 6, | |
463 | &ctrl->addr[ctrl->index], 3); | |
464 | ctrl->index += 3; | |
465 | } | |
466 | ||
467 | ctrl->oob_poi = NULL; | |
468 | return; | |
469 | } | |
470 | ||
471 | /* CMD_STATUS must read the status byte while CEB is active */ | |
472 | /* Note - it does not wait for the ready line */ | |
473 | case NAND_CMD_STATUS: | |
474 | out_be32(&lbc->fir, | |
475 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | | |
476 | (FIR_OP_RBW << FIR_OP1_SHIFT)); | |
477 | out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); | |
478 | out_be32(&lbc->fbcr, 1); | |
479 | set_addr(mtd, 0, 0, 0); | |
480 | ctrl->read_bytes = 1; | |
481 | ||
482 | fsl_elbc_run_command(mtd); | |
483 | ||
484 | /* The chip always seems to report that it is | |
485 | * write-protected, even when it is not. | |
486 | */ | |
487 | setbits8(ctrl->addr, NAND_STATUS_WP); | |
488 | return; | |
489 | ||
490 | /* RESET without waiting for the ready line */ | |
491 | case NAND_CMD_RESET: | |
492 | dev_dbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n"); | |
493 | out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT); | |
494 | out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT); | |
495 | fsl_elbc_run_command(mtd); | |
496 | return; | |
497 | ||
498 | default: | |
499 | dev_err(ctrl->dev, | |
500 | "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n", | |
501 | command); | |
502 | } | |
503 | } | |
504 | ||
505 | static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip) | |
506 | { | |
507 | /* The hardware does not seem to support multiple | |
508 | * chips per bank. | |
509 | */ | |
510 | } | |
511 | ||
512 | /* | |
513 | * Write buf to the FCM Controller Data Buffer | |
514 | */ | |
515 | static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) | |
516 | { | |
517 | struct nand_chip *chip = mtd->priv; | |
518 | struct fsl_elbc_mtd *priv = chip->priv; | |
519 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
520 | unsigned int bufsize = mtd->writesize + mtd->oobsize; | |
521 | ||
0ff6631b | 522 | if (len <= 0) { |
76b10467 SW |
523 | dev_err(ctrl->dev, "write_buf of %d bytes", len); |
524 | ctrl->status = 0; | |
525 | return; | |
526 | } | |
527 | ||
528 | if ((unsigned int)len > bufsize - ctrl->index) { | |
529 | dev_err(ctrl->dev, | |
530 | "write_buf beyond end of buffer " | |
531 | "(%d requested, %u available)\n", | |
532 | len, bufsize - ctrl->index); | |
533 | len = bufsize - ctrl->index; | |
534 | } | |
535 | ||
536 | memcpy_toio(&ctrl->addr[ctrl->index], buf, len); | |
0ff6631b AV |
537 | /* |
538 | * This is workaround for the weird elbc hangs during nand write, | |
539 | * Scott Wood says: "...perhaps difference in how long it takes a | |
540 | * write to make it through the localbus compared to a write to IMMR | |
541 | * is causing problems, and sync isn't helping for some reason." | |
542 | * Reading back the last byte helps though. | |
543 | */ | |
544 | in_8(&ctrl->addr[ctrl->index] + len - 1); | |
545 | ||
76b10467 SW |
546 | ctrl->index += len; |
547 | } | |
548 | ||
549 | /* | |
550 | * read a byte from either the FCM hardware buffer if it has any data left | |
551 | * otherwise issue a command to read a single byte. | |
552 | */ | |
553 | static u8 fsl_elbc_read_byte(struct mtd_info *mtd) | |
554 | { | |
555 | struct nand_chip *chip = mtd->priv; | |
556 | struct fsl_elbc_mtd *priv = chip->priv; | |
557 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
558 | ||
559 | /* If there are still bytes in the FCM, then use the next byte. */ | |
560 | if (ctrl->index < ctrl->read_bytes) | |
561 | return in_8(&ctrl->addr[ctrl->index++]); | |
562 | ||
563 | dev_err(ctrl->dev, "read_byte beyond end of buffer\n"); | |
564 | return ERR_BYTE; | |
565 | } | |
566 | ||
567 | /* | |
568 | * Read from the FCM Controller Data Buffer | |
569 | */ | |
570 | static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len) | |
571 | { | |
572 | struct nand_chip *chip = mtd->priv; | |
573 | struct fsl_elbc_mtd *priv = chip->priv; | |
574 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
575 | int avail; | |
576 | ||
577 | if (len < 0) | |
578 | return; | |
579 | ||
580 | avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index); | |
581 | memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail); | |
582 | ctrl->index += avail; | |
583 | ||
584 | if (len > avail) | |
585 | dev_err(ctrl->dev, | |
586 | "read_buf beyond end of buffer " | |
587 | "(%d requested, %d available)\n", | |
588 | len, avail); | |
589 | } | |
590 | ||
591 | /* | |
592 | * Verify buffer against the FCM Controller Data Buffer | |
593 | */ | |
594 | static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) | |
595 | { | |
596 | struct nand_chip *chip = mtd->priv; | |
597 | struct fsl_elbc_mtd *priv = chip->priv; | |
598 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
599 | int i; | |
600 | ||
601 | if (len < 0) { | |
602 | dev_err(ctrl->dev, "write_buf of %d bytes", len); | |
603 | return -EINVAL; | |
604 | } | |
605 | ||
606 | if ((unsigned int)len > ctrl->read_bytes - ctrl->index) { | |
607 | dev_err(ctrl->dev, | |
608 | "verify_buf beyond end of buffer " | |
609 | "(%d requested, %u available)\n", | |
610 | len, ctrl->read_bytes - ctrl->index); | |
611 | ||
612 | ctrl->index = ctrl->read_bytes; | |
613 | return -EINVAL; | |
614 | } | |
615 | ||
616 | for (i = 0; i < len; i++) | |
617 | if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i]) | |
618 | break; | |
619 | ||
620 | ctrl->index += len; | |
621 | return i == len && ctrl->status == LTESR_CC ? 0 : -EIO; | |
622 | } | |
623 | ||
624 | /* This function is called after Program and Erase Operations to | |
625 | * check for success or failure. | |
626 | */ | |
627 | static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
628 | { | |
629 | struct fsl_elbc_mtd *priv = chip->priv; | |
630 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
d4a32fe4 | 631 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
632 | |
633 | if (ctrl->status != LTESR_CC) | |
634 | return NAND_STATUS_FAIL; | |
635 | ||
636 | /* Use READ_STATUS command, but wait for the device to be ready */ | |
637 | ctrl->use_mdr = 0; | |
638 | out_be32(&lbc->fir, | |
639 | (FIR_OP_CW0 << FIR_OP0_SHIFT) | | |
640 | (FIR_OP_RBW << FIR_OP1_SHIFT)); | |
641 | out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); | |
642 | out_be32(&lbc->fbcr, 1); | |
643 | set_addr(mtd, 0, 0, 0); | |
644 | ctrl->read_bytes = 1; | |
645 | ||
646 | fsl_elbc_run_command(mtd); | |
647 | ||
648 | if (ctrl->status != LTESR_CC) | |
649 | return NAND_STATUS_FAIL; | |
650 | ||
651 | /* The chip always seems to report that it is | |
652 | * write-protected, even when it is not. | |
653 | */ | |
654 | setbits8(ctrl->addr, NAND_STATUS_WP); | |
655 | return fsl_elbc_read_byte(mtd); | |
656 | } | |
657 | ||
658 | static int fsl_elbc_chip_init_tail(struct mtd_info *mtd) | |
659 | { | |
660 | struct nand_chip *chip = mtd->priv; | |
661 | struct fsl_elbc_mtd *priv = chip->priv; | |
662 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
d4a32fe4 | 663 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
664 | unsigned int al; |
665 | ||
666 | /* calculate FMR Address Length field */ | |
667 | al = 0; | |
668 | if (chip->pagemask & 0xffff0000) | |
669 | al++; | |
670 | if (chip->pagemask & 0xff000000) | |
671 | al++; | |
672 | ||
673 | /* add to ECCM mode set in fsl_elbc_init */ | |
674 | priv->fmr |= (12 << FMR_CWTO_SHIFT) | /* Timeout > 12 ms */ | |
675 | (al << FMR_AL_SHIFT); | |
676 | ||
677 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->numchips = %d\n", | |
678 | chip->numchips); | |
679 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chipsize = %ld\n", | |
680 | chip->chipsize); | |
681 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->pagemask = %8x\n", | |
682 | chip->pagemask); | |
683 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_delay = %d\n", | |
684 | chip->chip_delay); | |
685 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->badblockpos = %d\n", | |
686 | chip->badblockpos); | |
687 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_shift = %d\n", | |
688 | chip->chip_shift); | |
689 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->page_shift = %d\n", | |
690 | chip->page_shift); | |
691 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n", | |
692 | chip->phys_erase_shift); | |
693 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecclayout = %p\n", | |
694 | chip->ecclayout); | |
695 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.mode = %d\n", | |
696 | chip->ecc.mode); | |
697 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.steps = %d\n", | |
698 | chip->ecc.steps); | |
699 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n", | |
700 | chip->ecc.bytes); | |
701 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.total = %d\n", | |
702 | chip->ecc.total); | |
703 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.layout = %p\n", | |
704 | chip->ecc.layout); | |
705 | dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags); | |
706 | dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->size = %d\n", mtd->size); | |
707 | dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->erasesize = %d\n", | |
708 | mtd->erasesize); | |
709 | dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->writesize = %d\n", | |
710 | mtd->writesize); | |
711 | dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->oobsize = %d\n", | |
712 | mtd->oobsize); | |
713 | ||
714 | /* adjust Option Register and ECC to match Flash page size */ | |
715 | if (mtd->writesize == 512) { | |
716 | priv->page_size = 0; | |
1938de46 | 717 | clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); |
76b10467 SW |
718 | } else if (mtd->writesize == 2048) { |
719 | priv->page_size = 1; | |
720 | setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); | |
721 | /* adjust ecc setup if needed */ | |
722 | if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) == | |
723 | BR_DECC_CHK_GEN) { | |
724 | chip->ecc.size = 512; | |
725 | chip->ecc.layout = (priv->fmr & FMR_ECCM) ? | |
726 | &fsl_elbc_oob_lp_eccm1 : | |
727 | &fsl_elbc_oob_lp_eccm0; | |
452db272 | 728 | chip->badblock_pattern = &largepage_memorybased; |
76b10467 SW |
729 | } |
730 | } else { | |
731 | dev_err(ctrl->dev, | |
732 | "fsl_elbc_init: page size %d is not supported\n", | |
733 | mtd->writesize); | |
734 | return -1; | |
735 | } | |
736 | ||
76b10467 SW |
737 | return 0; |
738 | } | |
739 | ||
740 | static int fsl_elbc_read_page(struct mtd_info *mtd, | |
741 | struct nand_chip *chip, | |
742 | uint8_t *buf) | |
743 | { | |
744 | fsl_elbc_read_buf(mtd, buf, mtd->writesize); | |
745 | fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
746 | ||
747 | if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL) | |
748 | mtd->ecc_stats.failed++; | |
749 | ||
750 | return 0; | |
751 | } | |
752 | ||
753 | /* ECC will be calculated automatically, and errors will be detected in | |
754 | * waitfunc. | |
755 | */ | |
756 | static void fsl_elbc_write_page(struct mtd_info *mtd, | |
757 | struct nand_chip *chip, | |
758 | const uint8_t *buf) | |
759 | { | |
760 | struct fsl_elbc_mtd *priv = chip->priv; | |
761 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
762 | ||
763 | fsl_elbc_write_buf(mtd, buf, mtd->writesize); | |
764 | fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
765 | ||
766 | ctrl->oob_poi = chip->oob_poi; | |
767 | } | |
768 | ||
769 | static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv) | |
770 | { | |
771 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
d4a32fe4 | 772 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
773 | struct nand_chip *chip = &priv->chip; |
774 | ||
775 | dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank); | |
776 | ||
777 | /* Fill in fsl_elbc_mtd structure */ | |
778 | priv->mtd.priv = chip; | |
779 | priv->mtd.owner = THIS_MODULE; | |
780 | priv->fmr = 0; /* rest filled in later */ | |
781 | ||
782 | /* fill in nand_chip structure */ | |
783 | /* set up function call table */ | |
784 | chip->read_byte = fsl_elbc_read_byte; | |
785 | chip->write_buf = fsl_elbc_write_buf; | |
786 | chip->read_buf = fsl_elbc_read_buf; | |
787 | chip->verify_buf = fsl_elbc_verify_buf; | |
788 | chip->select_chip = fsl_elbc_select_chip; | |
789 | chip->cmdfunc = fsl_elbc_cmdfunc; | |
790 | chip->waitfunc = fsl_elbc_wait; | |
791 | ||
ec6e0ea3 AV |
792 | chip->bbt_td = &bbt_main_descr; |
793 | chip->bbt_md = &bbt_mirror_descr; | |
794 | ||
76b10467 | 795 | /* set up nand options */ |
ec6e0ea3 AV |
796 | chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR | |
797 | NAND_USE_FLASH_BBT; | |
76b10467 SW |
798 | |
799 | chip->controller = &ctrl->controller; | |
800 | chip->priv = priv; | |
801 | ||
802 | chip->ecc.read_page = fsl_elbc_read_page; | |
803 | chip->ecc.write_page = fsl_elbc_write_page; | |
804 | ||
805 | /* If CS Base Register selects full hardware ECC then use it */ | |
806 | if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) == | |
807 | BR_DECC_CHK_GEN) { | |
808 | chip->ecc.mode = NAND_ECC_HW; | |
809 | /* put in small page settings and adjust later if needed */ | |
810 | chip->ecc.layout = (priv->fmr & FMR_ECCM) ? | |
811 | &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0; | |
812 | chip->ecc.size = 512; | |
813 | chip->ecc.bytes = 3; | |
814 | } else { | |
815 | /* otherwise fall back to default software ECC */ | |
816 | chip->ecc.mode = NAND_ECC_SOFT; | |
817 | } | |
818 | ||
819 | return 0; | |
820 | } | |
821 | ||
822 | static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv) | |
823 | { | |
824 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
825 | ||
826 | nand_release(&priv->mtd); | |
827 | ||
9ebed3e6 AV |
828 | kfree(priv->mtd.name); |
829 | ||
76b10467 SW |
830 | if (priv->vbase) |
831 | iounmap(priv->vbase); | |
832 | ||
833 | ctrl->chips[priv->bank] = NULL; | |
834 | kfree(priv); | |
835 | ||
836 | return 0; | |
837 | } | |
838 | ||
55679df3 AV |
839 | static int __devinit fsl_elbc_chip_probe(struct fsl_elbc_ctrl *ctrl, |
840 | struct device_node *node) | |
76b10467 | 841 | { |
d4a32fe4 | 842 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
843 | struct fsl_elbc_mtd *priv; |
844 | struct resource res; | |
845 | #ifdef CONFIG_MTD_PARTITIONS | |
846 | static const char *part_probe_types[] | |
847 | = { "cmdlinepart", "RedBoot", NULL }; | |
848 | struct mtd_partition *parts; | |
849 | #endif | |
850 | int ret; | |
851 | int bank; | |
852 | ||
853 | /* get, allocate and map the memory resource */ | |
854 | ret = of_address_to_resource(node, 0, &res); | |
855 | if (ret) { | |
856 | dev_err(ctrl->dev, "failed to get resource\n"); | |
857 | return ret; | |
858 | } | |
859 | ||
860 | /* find which chip select it is connected to */ | |
861 | for (bank = 0; bank < MAX_BANKS; bank++) | |
862 | if ((in_be32(&lbc->bank[bank].br) & BR_V) && | |
863 | (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM && | |
864 | (in_be32(&lbc->bank[bank].br) & | |
865 | in_be32(&lbc->bank[bank].or) & BR_BA) | |
866 | == res.start) | |
867 | break; | |
868 | ||
869 | if (bank >= MAX_BANKS) { | |
870 | dev_err(ctrl->dev, "address did not match any chip selects\n"); | |
871 | return -ENODEV; | |
872 | } | |
873 | ||
874 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
875 | if (!priv) | |
876 | return -ENOMEM; | |
877 | ||
878 | ctrl->chips[bank] = priv; | |
879 | priv->bank = bank; | |
880 | priv->ctrl = ctrl; | |
881 | priv->dev = ctrl->dev; | |
882 | ||
883 | priv->vbase = ioremap(res.start, res.end - res.start + 1); | |
884 | if (!priv->vbase) { | |
885 | dev_err(ctrl->dev, "failed to map chip region\n"); | |
886 | ret = -ENOMEM; | |
887 | goto err; | |
888 | } | |
889 | ||
650da9d0 | 890 | priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start); |
9ebed3e6 AV |
891 | if (!priv->mtd.name) { |
892 | ret = -ENOMEM; | |
893 | goto err; | |
894 | } | |
895 | ||
76b10467 SW |
896 | ret = fsl_elbc_chip_init(priv); |
897 | if (ret) | |
898 | goto err; | |
899 | ||
900 | ret = nand_scan_ident(&priv->mtd, 1); | |
901 | if (ret) | |
902 | goto err; | |
903 | ||
904 | ret = fsl_elbc_chip_init_tail(&priv->mtd); | |
905 | if (ret) | |
906 | goto err; | |
907 | ||
908 | ret = nand_scan_tail(&priv->mtd); | |
909 | if (ret) | |
910 | goto err; | |
911 | ||
912 | #ifdef CONFIG_MTD_PARTITIONS | |
913 | /* First look for RedBoot table or partitions on the command | |
914 | * line, these take precedence over device tree information */ | |
915 | ret = parse_mtd_partitions(&priv->mtd, part_probe_types, &parts, 0); | |
916 | if (ret < 0) | |
917 | goto err; | |
918 | ||
919 | #ifdef CONFIG_MTD_OF_PARTS | |
920 | if (ret == 0) { | |
69fd3a8d | 921 | ret = of_mtd_parse_partitions(priv->dev, node, &parts); |
76b10467 SW |
922 | if (ret < 0) |
923 | goto err; | |
924 | } | |
925 | #endif | |
926 | ||
927 | if (ret > 0) | |
928 | add_mtd_partitions(&priv->mtd, parts, ret); | |
929 | else | |
930 | #endif | |
931 | add_mtd_device(&priv->mtd); | |
932 | ||
933 | printk(KERN_INFO "eLBC NAND device at 0x%zx, bank %d\n", | |
934 | res.start, priv->bank); | |
935 | return 0; | |
936 | ||
937 | err: | |
938 | fsl_elbc_chip_remove(priv); | |
939 | return ret; | |
940 | } | |
941 | ||
942 | static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl) | |
943 | { | |
d4a32fe4 | 944 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
945 | |
946 | /* clear event registers */ | |
947 | setbits32(&lbc->ltesr, LTESR_NAND_MASK); | |
948 | out_be32(&lbc->lteatr, 0); | |
949 | ||
950 | /* Enable interrupts for any detected events */ | |
951 | out_be32(&lbc->lteir, LTESR_NAND_MASK); | |
952 | ||
953 | ctrl->read_bytes = 0; | |
954 | ctrl->index = 0; | |
955 | ctrl->addr = NULL; | |
956 | ||
957 | return 0; | |
958 | } | |
959 | ||
aa83570e | 960 | static int fsl_elbc_ctrl_remove(struct of_device *ofdev) |
76b10467 SW |
961 | { |
962 | struct fsl_elbc_ctrl *ctrl = dev_get_drvdata(&ofdev->dev); | |
963 | int i; | |
964 | ||
965 | for (i = 0; i < MAX_BANKS; i++) | |
966 | if (ctrl->chips[i]) | |
967 | fsl_elbc_chip_remove(ctrl->chips[i]); | |
968 | ||
969 | if (ctrl->irq) | |
970 | free_irq(ctrl->irq, ctrl); | |
971 | ||
972 | if (ctrl->regs) | |
973 | iounmap(ctrl->regs); | |
974 | ||
975 | dev_set_drvdata(&ofdev->dev, NULL); | |
976 | kfree(ctrl); | |
977 | return 0; | |
978 | } | |
979 | ||
980 | /* NOTE: This interrupt is also used to report other localbus events, | |
981 | * such as transaction errors on other chipselects. If we want to | |
982 | * capture those, we'll need to move the IRQ code into a shared | |
983 | * LBC driver. | |
984 | */ | |
985 | ||
986 | static irqreturn_t fsl_elbc_ctrl_irq(int irqno, void *data) | |
987 | { | |
988 | struct fsl_elbc_ctrl *ctrl = data; | |
d4a32fe4 | 989 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
990 | __be32 status = in_be32(&lbc->ltesr) & LTESR_NAND_MASK; |
991 | ||
992 | if (status) { | |
993 | out_be32(&lbc->ltesr, status); | |
994 | out_be32(&lbc->lteatr, 0); | |
995 | ||
996 | ctrl->irq_status = status; | |
997 | smp_wmb(); | |
998 | wake_up(&ctrl->irq_wait); | |
999 | ||
1000 | return IRQ_HANDLED; | |
1001 | } | |
1002 | ||
1003 | return IRQ_NONE; | |
1004 | } | |
1005 | ||
1006 | /* fsl_elbc_ctrl_probe | |
1007 | * | |
1008 | * called by device layer when it finds a device matching | |
1009 | * one our driver can handled. This code allocates all of | |
1010 | * the resources needed for the controller only. The | |
1011 | * resources for the NAND banks themselves are allocated | |
1012 | * in the chip probe function. | |
1013 | */ | |
1014 | ||
1015 | static int __devinit fsl_elbc_ctrl_probe(struct of_device *ofdev, | |
1016 | const struct of_device_id *match) | |
1017 | { | |
1018 | struct device_node *child; | |
1019 | struct fsl_elbc_ctrl *ctrl; | |
1020 | int ret; | |
1021 | ||
1022 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); | |
1023 | if (!ctrl) | |
1024 | return -ENOMEM; | |
1025 | ||
1026 | dev_set_drvdata(&ofdev->dev, ctrl); | |
1027 | ||
1028 | spin_lock_init(&ctrl->controller.lock); | |
1029 | init_waitqueue_head(&ctrl->controller.wq); | |
1030 | init_waitqueue_head(&ctrl->irq_wait); | |
1031 | ||
1032 | ctrl->regs = of_iomap(ofdev->node, 0); | |
1033 | if (!ctrl->regs) { | |
1034 | dev_err(&ofdev->dev, "failed to get memory region\n"); | |
1035 | ret = -ENODEV; | |
1036 | goto err; | |
1037 | } | |
1038 | ||
1039 | ctrl->irq = of_irq_to_resource(ofdev->node, 0, NULL); | |
1040 | if (ctrl->irq == NO_IRQ) { | |
1041 | dev_err(&ofdev->dev, "failed to get irq resource\n"); | |
1042 | ret = -ENODEV; | |
1043 | goto err; | |
1044 | } | |
1045 | ||
1046 | ctrl->dev = &ofdev->dev; | |
1047 | ||
1048 | ret = fsl_elbc_ctrl_init(ctrl); | |
1049 | if (ret < 0) | |
1050 | goto err; | |
1051 | ||
1052 | ret = request_irq(ctrl->irq, fsl_elbc_ctrl_irq, 0, "fsl-elbc", ctrl); | |
1053 | if (ret != 0) { | |
1054 | dev_err(&ofdev->dev, "failed to install irq (%d)\n", | |
1055 | ctrl->irq); | |
1056 | ret = ctrl->irq; | |
1057 | goto err; | |
1058 | } | |
1059 | ||
1060 | for_each_child_of_node(ofdev->node, child) | |
1061 | if (of_device_is_compatible(child, "fsl,elbc-fcm-nand")) | |
1062 | fsl_elbc_chip_probe(ctrl, child); | |
1063 | ||
1064 | return 0; | |
1065 | ||
1066 | err: | |
1067 | fsl_elbc_ctrl_remove(ofdev); | |
1068 | return ret; | |
1069 | } | |
1070 | ||
1071 | static const struct of_device_id fsl_elbc_match[] = { | |
1072 | { | |
1073 | .compatible = "fsl,elbc", | |
1074 | }, | |
1075 | {} | |
1076 | }; | |
1077 | ||
1078 | static struct of_platform_driver fsl_elbc_ctrl_driver = { | |
1079 | .driver = { | |
1080 | .name = "fsl-elbc", | |
1081 | }, | |
1082 | .match_table = fsl_elbc_match, | |
1083 | .probe = fsl_elbc_ctrl_probe, | |
aa83570e | 1084 | .remove = fsl_elbc_ctrl_remove, |
76b10467 SW |
1085 | }; |
1086 | ||
1087 | static int __init fsl_elbc_init(void) | |
1088 | { | |
1089 | return of_register_platform_driver(&fsl_elbc_ctrl_driver); | |
1090 | } | |
1091 | ||
1092 | static void __exit fsl_elbc_exit(void) | |
1093 | { | |
1094 | of_unregister_platform_driver(&fsl_elbc_ctrl_driver); | |
1095 | } | |
1096 | ||
1097 | module_init(fsl_elbc_init); | |
1098 | module_exit(fsl_elbc_exit); | |
1099 | ||
1100 | MODULE_LICENSE("GPL"); | |
1101 | MODULE_AUTHOR("Freescale"); | |
1102 | MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver"); |