Commit | Line | Data |
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5c249c5a AV |
1 | /* |
2 | * Freescale UPM NAND driver. | |
3 | * | |
4 | * Copyright © 2007-2008 MontaVista Software, Inc. | |
5 | * | |
6 | * Author: Anton Vorontsov <avorontsov@ru.mvista.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
13f53697 | 16 | #include <linux/delay.h> |
5c249c5a AV |
17 | #include <linux/mtd/nand.h> |
18 | #include <linux/mtd/nand_ecc.h> | |
19 | #include <linux/mtd/partitions.h> | |
20 | #include <linux/mtd/mtd.h> | |
21 | #include <linux/of_platform.h> | |
22 | #include <linux/of_gpio.h> | |
23 | #include <linux/io.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
5c249c5a AV |
25 | #include <asm/fsl_lbc.h> |
26 | ||
ade92a63 WG |
27 | #define FSL_UPM_WAIT_RUN_PATTERN 0x1 |
28 | #define FSL_UPM_WAIT_WRITE_BYTE 0x2 | |
29 | #define FSL_UPM_WAIT_WRITE_BUFFER 0x4 | |
30 | ||
5c249c5a AV |
31 | struct fsl_upm_nand { |
32 | struct device *dev; | |
33 | struct mtd_info mtd; | |
34 | struct nand_chip chip; | |
35 | int last_ctrl; | |
36 | #ifdef CONFIG_MTD_PARTITIONS | |
37 | struct mtd_partition *parts; | |
38 | #endif | |
39 | ||
40 | struct fsl_upm upm; | |
41 | uint8_t upm_addr_offset; | |
42 | uint8_t upm_cmd_offset; | |
43 | void __iomem *io_base; | |
b6e0e8c0 WG |
44 | int rnb_gpio[NAND_MAX_CHIPS]; |
45 | uint32_t mchip_offsets[NAND_MAX_CHIPS]; | |
46 | uint32_t mchip_count; | |
47 | uint32_t mchip_number; | |
13f53697 | 48 | int chip_delay; |
ade92a63 | 49 | uint32_t wait_flags; |
5c249c5a AV |
50 | }; |
51 | ||
52 | #define to_fsl_upm_nand(mtd) container_of(mtd, struct fsl_upm_nand, mtd) | |
53 | ||
54 | static int fun_chip_ready(struct mtd_info *mtd) | |
55 | { | |
56 | struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd); | |
57 | ||
b6e0e8c0 | 58 | if (gpio_get_value(fun->rnb_gpio[fun->mchip_number])) |
5c249c5a AV |
59 | return 1; |
60 | ||
61 | dev_vdbg(fun->dev, "busy\n"); | |
62 | return 0; | |
63 | } | |
64 | ||
65 | static void fun_wait_rnb(struct fsl_upm_nand *fun) | |
66 | { | |
b6e0e8c0 WG |
67 | if (fun->rnb_gpio[fun->mchip_number] >= 0) { |
68 | int cnt = 1000000; | |
5c249c5a | 69 | |
5c249c5a AV |
70 | while (--cnt && !fun_chip_ready(&fun->mtd)) |
71 | cpu_relax(); | |
13f53697 WG |
72 | if (!cnt) |
73 | dev_err(fun->dev, "tired waiting for RNB\n"); | |
74 | } else { | |
75 | ndelay(100); | |
5c249c5a | 76 | } |
5c249c5a AV |
77 | } |
78 | ||
79 | static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
80 | { | |
b6e0e8c0 | 81 | struct nand_chip *chip = mtd->priv; |
5c249c5a | 82 | struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd); |
b6e0e8c0 | 83 | u32 mar; |
5c249c5a AV |
84 | |
85 | if (!(ctrl & fun->last_ctrl)) { | |
86 | fsl_upm_end_pattern(&fun->upm); | |
87 | ||
88 | if (cmd == NAND_CMD_NONE) | |
89 | return; | |
90 | ||
91 | fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE); | |
92 | } | |
93 | ||
94 | if (ctrl & NAND_CTRL_CHANGE) { | |
95 | if (ctrl & NAND_ALE) | |
96 | fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset); | |
97 | else if (ctrl & NAND_CLE) | |
98 | fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset); | |
99 | } | |
100 | ||
b6e0e8c0 WG |
101 | mar = (cmd << (32 - fun->upm.width)) | |
102 | fun->mchip_offsets[fun->mchip_number]; | |
103 | fsl_upm_run_pattern(&fun->upm, chip->IO_ADDR_R, mar); | |
5c249c5a | 104 | |
ade92a63 WG |
105 | if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN) |
106 | fun_wait_rnb(fun); | |
5c249c5a AV |
107 | } |
108 | ||
b6e0e8c0 WG |
109 | static void fun_select_chip(struct mtd_info *mtd, int mchip_nr) |
110 | { | |
111 | struct nand_chip *chip = mtd->priv; | |
112 | struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd); | |
113 | ||
114 | if (mchip_nr == -1) { | |
115 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); | |
35016dd7 | 116 | } else if (mchip_nr >= 0 && mchip_nr < NAND_MAX_CHIPS) { |
b6e0e8c0 WG |
117 | fun->mchip_number = mchip_nr; |
118 | chip->IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr]; | |
119 | chip->IO_ADDR_W = chip->IO_ADDR_R; | |
120 | } else { | |
121 | BUG(); | |
122 | } | |
123 | } | |
124 | ||
5c249c5a AV |
125 | static uint8_t fun_read_byte(struct mtd_info *mtd) |
126 | { | |
127 | struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd); | |
128 | ||
129 | return in_8(fun->chip.IO_ADDR_R); | |
130 | } | |
131 | ||
132 | static void fun_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
133 | { | |
134 | struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd); | |
135 | int i; | |
136 | ||
137 | for (i = 0; i < len; i++) | |
138 | buf[i] = in_8(fun->chip.IO_ADDR_R); | |
139 | } | |
140 | ||
141 | static void fun_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) | |
142 | { | |
143 | struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd); | |
144 | int i; | |
145 | ||
146 | for (i = 0; i < len; i++) { | |
147 | out_8(fun->chip.IO_ADDR_W, buf[i]); | |
ade92a63 WG |
148 | if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE) |
149 | fun_wait_rnb(fun); | |
5c249c5a | 150 | } |
ade92a63 WG |
151 | if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER) |
152 | fun_wait_rnb(fun); | |
5c249c5a AV |
153 | } |
154 | ||
95ebffd7 AV |
155 | static int __devinit fun_chip_init(struct fsl_upm_nand *fun, |
156 | const struct device_node *upm_np, | |
157 | const struct resource *io_res) | |
5c249c5a AV |
158 | { |
159 | int ret; | |
95ebffd7 | 160 | struct device_node *flash_np; |
5c249c5a AV |
161 | #ifdef CONFIG_MTD_PARTITIONS |
162 | static const char *part_types[] = { "cmdlinepart", NULL, }; | |
163 | #endif | |
164 | ||
165 | fun->chip.IO_ADDR_R = fun->io_base; | |
166 | fun->chip.IO_ADDR_W = fun->io_base; | |
167 | fun->chip.cmd_ctrl = fun_cmd_ctrl; | |
13f53697 | 168 | fun->chip.chip_delay = fun->chip_delay; |
5c249c5a AV |
169 | fun->chip.read_byte = fun_read_byte; |
170 | fun->chip.read_buf = fun_read_buf; | |
171 | fun->chip.write_buf = fun_write_buf; | |
172 | fun->chip.ecc.mode = NAND_ECC_SOFT; | |
b6e0e8c0 WG |
173 | if (fun->mchip_count > 1) |
174 | fun->chip.select_chip = fun_select_chip; | |
5c249c5a | 175 | |
b6e0e8c0 | 176 | if (fun->rnb_gpio[0] >= 0) |
5c249c5a AV |
177 | fun->chip.dev_ready = fun_chip_ready; |
178 | ||
179 | fun->mtd.priv = &fun->chip; | |
180 | fun->mtd.owner = THIS_MODULE; | |
181 | ||
95ebffd7 AV |
182 | flash_np = of_get_next_child(upm_np, NULL); |
183 | if (!flash_np) | |
184 | return -ENODEV; | |
185 | ||
186 | fun->mtd.name = kasprintf(GFP_KERNEL, "%x.%s", io_res->start, | |
187 | flash_np->name); | |
188 | if (!fun->mtd.name) { | |
189 | ret = -ENOMEM; | |
190 | goto err; | |
191 | } | |
192 | ||
b6e0e8c0 | 193 | ret = nand_scan(&fun->mtd, fun->mchip_count); |
5c249c5a | 194 | if (ret) |
95ebffd7 | 195 | goto err; |
5c249c5a AV |
196 | |
197 | #ifdef CONFIG_MTD_PARTITIONS | |
198 | ret = parse_mtd_partitions(&fun->mtd, part_types, &fun->parts, 0); | |
95ebffd7 AV |
199 | |
200 | #ifdef CONFIG_MTD_OF_PARTS | |
29b65861 WG |
201 | if (ret == 0) { |
202 | ret = of_mtd_parse_partitions(fun->dev, flash_np, &fun->parts); | |
203 | if (ret < 0) | |
204 | goto err; | |
205 | } | |
95ebffd7 | 206 | #endif |
5c249c5a | 207 | if (ret > 0) |
95ebffd7 AV |
208 | ret = add_mtd_partitions(&fun->mtd, fun->parts, ret); |
209 | else | |
5c249c5a | 210 | #endif |
95ebffd7 AV |
211 | ret = add_mtd_device(&fun->mtd); |
212 | err: | |
213 | of_node_put(flash_np); | |
214 | return ret; | |
5c249c5a AV |
215 | } |
216 | ||
217 | static int __devinit fun_probe(struct of_device *ofdev, | |
218 | const struct of_device_id *ofid) | |
219 | { | |
220 | struct fsl_upm_nand *fun; | |
221 | struct resource io_res; | |
222 | const uint32_t *prop; | |
b6e0e8c0 | 223 | int rnb_gpio; |
5c249c5a AV |
224 | int ret; |
225 | int size; | |
b6e0e8c0 | 226 | int i; |
5c249c5a AV |
227 | |
228 | fun = kzalloc(sizeof(*fun), GFP_KERNEL); | |
229 | if (!fun) | |
230 | return -ENOMEM; | |
231 | ||
232 | ret = of_address_to_resource(ofdev->node, 0, &io_res); | |
233 | if (ret) { | |
234 | dev_err(&ofdev->dev, "can't get IO base\n"); | |
235 | goto err1; | |
236 | } | |
237 | ||
238 | ret = fsl_upm_find(io_res.start, &fun->upm); | |
239 | if (ret) { | |
240 | dev_err(&ofdev->dev, "can't find UPM\n"); | |
241 | goto err1; | |
242 | } | |
243 | ||
244 | prop = of_get_property(ofdev->node, "fsl,upm-addr-offset", &size); | |
245 | if (!prop || size != sizeof(uint32_t)) { | |
246 | dev_err(&ofdev->dev, "can't get UPM address offset\n"); | |
247 | ret = -EINVAL; | |
b6e0e8c0 | 248 | goto err1; |
5c249c5a AV |
249 | } |
250 | fun->upm_addr_offset = *prop; | |
251 | ||
252 | prop = of_get_property(ofdev->node, "fsl,upm-cmd-offset", &size); | |
253 | if (!prop || size != sizeof(uint32_t)) { | |
254 | dev_err(&ofdev->dev, "can't get UPM command offset\n"); | |
255 | ret = -EINVAL; | |
b6e0e8c0 | 256 | goto err1; |
5c249c5a AV |
257 | } |
258 | fun->upm_cmd_offset = *prop; | |
259 | ||
b6e0e8c0 WG |
260 | prop = of_get_property(ofdev->node, |
261 | "fsl,upm-addr-line-cs-offsets", &size); | |
262 | if (prop && (size / sizeof(uint32_t)) > 0) { | |
263 | fun->mchip_count = size / sizeof(uint32_t); | |
264 | if (fun->mchip_count >= NAND_MAX_CHIPS) { | |
265 | dev_err(&ofdev->dev, "too much multiple chips\n"); | |
266 | goto err1; | |
267 | } | |
268 | for (i = 0; i < fun->mchip_count; i++) | |
269 | fun->mchip_offsets[i] = prop[i]; | |
270 | } else { | |
271 | fun->mchip_count = 1; | |
272 | } | |
273 | ||
274 | for (i = 0; i < fun->mchip_count; i++) { | |
275 | fun->rnb_gpio[i] = -1; | |
276 | rnb_gpio = of_get_gpio(ofdev->node, i); | |
277 | if (rnb_gpio >= 0) { | |
278 | ret = gpio_request(rnb_gpio, dev_name(&ofdev->dev)); | |
279 | if (ret) { | |
280 | dev_err(&ofdev->dev, | |
281 | "can't request RNB gpio #%d\n", i); | |
282 | goto err2; | |
283 | } | |
284 | gpio_direction_input(rnb_gpio); | |
285 | fun->rnb_gpio[i] = rnb_gpio; | |
286 | } else if (rnb_gpio == -EINVAL) { | |
287 | dev_err(&ofdev->dev, "RNB gpio #%d is invalid\n", i); | |
5c249c5a AV |
288 | goto err2; |
289 | } | |
5c249c5a AV |
290 | } |
291 | ||
13f53697 WG |
292 | prop = of_get_property(ofdev->node, "chip-delay", NULL); |
293 | if (prop) | |
294 | fun->chip_delay = *prop; | |
295 | else | |
296 | fun->chip_delay = 50; | |
297 | ||
ade92a63 WG |
298 | prop = of_get_property(ofdev->node, "fsl,upm-wait-flags", &size); |
299 | if (prop && size == sizeof(uint32_t)) | |
300 | fun->wait_flags = *prop; | |
301 | else | |
302 | fun->wait_flags = FSL_UPM_WAIT_RUN_PATTERN | | |
303 | FSL_UPM_WAIT_WRITE_BYTE; | |
304 | ||
5c249c5a | 305 | fun->io_base = devm_ioremap_nocache(&ofdev->dev, io_res.start, |
b6e0e8c0 | 306 | io_res.end - io_res.start + 1); |
5c249c5a AV |
307 | if (!fun->io_base) { |
308 | ret = -ENOMEM; | |
309 | goto err2; | |
310 | } | |
311 | ||
312 | fun->dev = &ofdev->dev; | |
313 | fun->last_ctrl = NAND_CLE; | |
5c249c5a | 314 | |
95ebffd7 | 315 | ret = fun_chip_init(fun, ofdev->node, &io_res); |
5c249c5a AV |
316 | if (ret) |
317 | goto err2; | |
318 | ||
319 | dev_set_drvdata(&ofdev->dev, fun); | |
320 | ||
321 | return 0; | |
322 | err2: | |
b6e0e8c0 WG |
323 | for (i = 0; i < fun->mchip_count; i++) { |
324 | if (fun->rnb_gpio[i] < 0) | |
325 | break; | |
326 | gpio_free(fun->rnb_gpio[i]); | |
327 | } | |
5c249c5a AV |
328 | err1: |
329 | kfree(fun); | |
330 | ||
331 | return ret; | |
332 | } | |
333 | ||
334 | static int __devexit fun_remove(struct of_device *ofdev) | |
335 | { | |
336 | struct fsl_upm_nand *fun = dev_get_drvdata(&ofdev->dev); | |
b6e0e8c0 | 337 | int i; |
5c249c5a AV |
338 | |
339 | nand_release(&fun->mtd); | |
95ebffd7 | 340 | kfree(fun->mtd.name); |
5c249c5a | 341 | |
b6e0e8c0 WG |
342 | for (i = 0; i < fun->mchip_count; i++) { |
343 | if (fun->rnb_gpio[i] < 0) | |
344 | break; | |
345 | gpio_free(fun->rnb_gpio[i]); | |
346 | } | |
5c249c5a AV |
347 | |
348 | kfree(fun); | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
353 | static struct of_device_id of_fun_match[] = { | |
354 | { .compatible = "fsl,upm-nand" }, | |
355 | {}, | |
356 | }; | |
357 | MODULE_DEVICE_TABLE(of, of_fun_match); | |
358 | ||
359 | static struct of_platform_driver of_fun_driver = { | |
4018294b GL |
360 | .driver = { |
361 | .name = "fsl,upm-nand", | |
362 | .owner = THIS_MODULE, | |
363 | .of_match_table = of_fun_match, | |
364 | }, | |
5c249c5a AV |
365 | .probe = fun_probe, |
366 | .remove = __devexit_p(fun_remove), | |
367 | }; | |
368 | ||
369 | static int __init fun_module_init(void) | |
370 | { | |
371 | return of_register_platform_driver(&of_fun_driver); | |
372 | } | |
373 | module_init(fun_module_init); | |
374 | ||
375 | static void __exit fun_module_exit(void) | |
376 | { | |
377 | of_unregister_platform_driver(&of_fun_driver); | |
378 | } | |
379 | module_exit(fun_module_exit); | |
380 | ||
381 | MODULE_LICENSE("GPL"); | |
382 | MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>"); | |
383 | MODULE_DESCRIPTION("Driver for NAND chips working through Freescale " | |
384 | "LocalBus User-Programmable Machine"); |