Commit | Line | Data |
---|---|---|
6c009ab8 LW |
1 | /* |
2 | * drivers/mtd/nand/fsmc_nand.c | |
3 | * | |
4 | * ST Microelectronics | |
5 | * Flexible Static Memory Controller (FSMC) | |
6 | * Driver for NAND portions | |
7 | * | |
8 | * Copyright © 2010 ST Microelectronics | |
9 | * Vipin Kumar <vipin.kumar@st.com> | |
10 | * Ashish Priyadarshi | |
11 | * | |
12 | * Based on drivers/mtd/nand/nomadik_nand.c | |
13 | * | |
14 | * This file is licensed under the terms of the GNU General Public | |
15 | * License version 2. This program is licensed "as is" without any | |
16 | * warranty of any kind, whether express or implied. | |
17 | */ | |
18 | ||
19 | #include <linux/clk.h> | |
4774fb0a VK |
20 | #include <linux/completion.h> |
21 | #include <linux/dmaengine.h> | |
22 | #include <linux/dma-direction.h> | |
23 | #include <linux/dma-mapping.h> | |
6c009ab8 LW |
24 | #include <linux/err.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/resource.h> | |
28 | #include <linux/sched.h> | |
29 | #include <linux/types.h> | |
30 | #include <linux/mtd/mtd.h> | |
31 | #include <linux/mtd/nand.h> | |
32 | #include <linux/mtd/nand_ecc.h> | |
33 | #include <linux/platform_device.h> | |
eea62819 | 34 | #include <linux/of.h> |
6c009ab8 LW |
35 | #include <linux/mtd/partitions.h> |
36 | #include <linux/io.h> | |
37 | #include <linux/slab.h> | |
38 | #include <linux/mtd/fsmc.h> | |
593cd871 | 39 | #include <linux/amba/bus.h> |
6c009ab8 LW |
40 | #include <mtd/mtd-abi.h> |
41 | ||
e29ee57b | 42 | static struct nand_ecclayout fsmc_ecc1_128_layout = { |
6c009ab8 LW |
43 | .eccbytes = 24, |
44 | .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52, | |
45 | 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116}, | |
46 | .oobfree = { | |
47 | {.offset = 8, .length = 8}, | |
48 | {.offset = 24, .length = 8}, | |
49 | {.offset = 40, .length = 8}, | |
50 | {.offset = 56, .length = 8}, | |
51 | {.offset = 72, .length = 8}, | |
52 | {.offset = 88, .length = 8}, | |
53 | {.offset = 104, .length = 8}, | |
54 | {.offset = 120, .length = 8} | |
55 | } | |
56 | }; | |
57 | ||
e29ee57b BY |
58 | static struct nand_ecclayout fsmc_ecc1_64_layout = { |
59 | .eccbytes = 12, | |
60 | .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52}, | |
61 | .oobfree = { | |
62 | {.offset = 8, .length = 8}, | |
63 | {.offset = 24, .length = 8}, | |
64 | {.offset = 40, .length = 8}, | |
65 | {.offset = 56, .length = 8}, | |
66 | } | |
67 | }; | |
68 | ||
69 | static struct nand_ecclayout fsmc_ecc1_16_layout = { | |
70 | .eccbytes = 3, | |
71 | .eccpos = {2, 3, 4}, | |
72 | .oobfree = { | |
73 | {.offset = 8, .length = 8}, | |
74 | } | |
75 | }; | |
76 | ||
77 | /* | |
78 | * ECC4 layout for NAND of pagesize 8192 bytes & OOBsize 256 bytes. 13*16 bytes | |
79 | * of OB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 46 | |
80 | * bytes are free for use. | |
81 | */ | |
82 | static struct nand_ecclayout fsmc_ecc4_256_layout = { | |
83 | .eccbytes = 208, | |
84 | .eccpos = { 2, 3, 4, 5, 6, 7, 8, | |
85 | 9, 10, 11, 12, 13, 14, | |
86 | 18, 19, 20, 21, 22, 23, 24, | |
87 | 25, 26, 27, 28, 29, 30, | |
88 | 34, 35, 36, 37, 38, 39, 40, | |
89 | 41, 42, 43, 44, 45, 46, | |
90 | 50, 51, 52, 53, 54, 55, 56, | |
91 | 57, 58, 59, 60, 61, 62, | |
92 | 66, 67, 68, 69, 70, 71, 72, | |
93 | 73, 74, 75, 76, 77, 78, | |
94 | 82, 83, 84, 85, 86, 87, 88, | |
95 | 89, 90, 91, 92, 93, 94, | |
96 | 98, 99, 100, 101, 102, 103, 104, | |
97 | 105, 106, 107, 108, 109, 110, | |
98 | 114, 115, 116, 117, 118, 119, 120, | |
99 | 121, 122, 123, 124, 125, 126, | |
100 | 130, 131, 132, 133, 134, 135, 136, | |
101 | 137, 138, 139, 140, 141, 142, | |
102 | 146, 147, 148, 149, 150, 151, 152, | |
103 | 153, 154, 155, 156, 157, 158, | |
104 | 162, 163, 164, 165, 166, 167, 168, | |
105 | 169, 170, 171, 172, 173, 174, | |
106 | 178, 179, 180, 181, 182, 183, 184, | |
107 | 185, 186, 187, 188, 189, 190, | |
108 | 194, 195, 196, 197, 198, 199, 200, | |
109 | 201, 202, 203, 204, 205, 206, | |
110 | 210, 211, 212, 213, 214, 215, 216, | |
111 | 217, 218, 219, 220, 221, 222, | |
112 | 226, 227, 228, 229, 230, 231, 232, | |
113 | 233, 234, 235, 236, 237, 238, | |
114 | 242, 243, 244, 245, 246, 247, 248, | |
115 | 249, 250, 251, 252, 253, 254 | |
116 | }, | |
117 | .oobfree = { | |
118 | {.offset = 15, .length = 3}, | |
119 | {.offset = 31, .length = 3}, | |
120 | {.offset = 47, .length = 3}, | |
121 | {.offset = 63, .length = 3}, | |
122 | {.offset = 79, .length = 3}, | |
123 | {.offset = 95, .length = 3}, | |
124 | {.offset = 111, .length = 3}, | |
125 | {.offset = 127, .length = 3}, | |
126 | {.offset = 143, .length = 3}, | |
127 | {.offset = 159, .length = 3}, | |
128 | {.offset = 175, .length = 3}, | |
129 | {.offset = 191, .length = 3}, | |
130 | {.offset = 207, .length = 3}, | |
131 | {.offset = 223, .length = 3}, | |
132 | {.offset = 239, .length = 3}, | |
133 | {.offset = 255, .length = 1} | |
134 | } | |
135 | }; | |
136 | ||
0c78e93b AV |
137 | /* |
138 | * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes | |
139 | * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118 | |
140 | * bytes are free for use. | |
141 | */ | |
142 | static struct nand_ecclayout fsmc_ecc4_224_layout = { | |
143 | .eccbytes = 104, | |
144 | .eccpos = { 2, 3, 4, 5, 6, 7, 8, | |
145 | 9, 10, 11, 12, 13, 14, | |
146 | 18, 19, 20, 21, 22, 23, 24, | |
147 | 25, 26, 27, 28, 29, 30, | |
148 | 34, 35, 36, 37, 38, 39, 40, | |
149 | 41, 42, 43, 44, 45, 46, | |
150 | 50, 51, 52, 53, 54, 55, 56, | |
151 | 57, 58, 59, 60, 61, 62, | |
152 | 66, 67, 68, 69, 70, 71, 72, | |
153 | 73, 74, 75, 76, 77, 78, | |
154 | 82, 83, 84, 85, 86, 87, 88, | |
155 | 89, 90, 91, 92, 93, 94, | |
156 | 98, 99, 100, 101, 102, 103, 104, | |
157 | 105, 106, 107, 108, 109, 110, | |
158 | 114, 115, 116, 117, 118, 119, 120, | |
159 | 121, 122, 123, 124, 125, 126 | |
160 | }, | |
161 | .oobfree = { | |
162 | {.offset = 15, .length = 3}, | |
163 | {.offset = 31, .length = 3}, | |
164 | {.offset = 47, .length = 3}, | |
165 | {.offset = 63, .length = 3}, | |
166 | {.offset = 79, .length = 3}, | |
167 | {.offset = 95, .length = 3}, | |
168 | {.offset = 111, .length = 3}, | |
169 | {.offset = 127, .length = 97} | |
170 | } | |
171 | }; | |
172 | ||
e29ee57b BY |
173 | /* |
174 | * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 128 bytes. 13*8 bytes | |
175 | * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 22 | |
176 | * bytes are free for use. | |
177 | */ | |
178 | static struct nand_ecclayout fsmc_ecc4_128_layout = { | |
6c009ab8 LW |
179 | .eccbytes = 104, |
180 | .eccpos = { 2, 3, 4, 5, 6, 7, 8, | |
181 | 9, 10, 11, 12, 13, 14, | |
182 | 18, 19, 20, 21, 22, 23, 24, | |
183 | 25, 26, 27, 28, 29, 30, | |
184 | 34, 35, 36, 37, 38, 39, 40, | |
185 | 41, 42, 43, 44, 45, 46, | |
186 | 50, 51, 52, 53, 54, 55, 56, | |
187 | 57, 58, 59, 60, 61, 62, | |
188 | 66, 67, 68, 69, 70, 71, 72, | |
189 | 73, 74, 75, 76, 77, 78, | |
190 | 82, 83, 84, 85, 86, 87, 88, | |
191 | 89, 90, 91, 92, 93, 94, | |
192 | 98, 99, 100, 101, 102, 103, 104, | |
193 | 105, 106, 107, 108, 109, 110, | |
194 | 114, 115, 116, 117, 118, 119, 120, | |
195 | 121, 122, 123, 124, 125, 126 | |
196 | }, | |
197 | .oobfree = { | |
198 | {.offset = 15, .length = 3}, | |
199 | {.offset = 31, .length = 3}, | |
200 | {.offset = 47, .length = 3}, | |
201 | {.offset = 63, .length = 3}, | |
202 | {.offset = 79, .length = 3}, | |
203 | {.offset = 95, .length = 3}, | |
204 | {.offset = 111, .length = 3}, | |
205 | {.offset = 127, .length = 1} | |
206 | } | |
207 | }; | |
208 | ||
e29ee57b BY |
209 | /* |
210 | * ECC4 layout for NAND of pagesize 2048 bytes & OOBsize 64 bytes. 13*4 bytes of | |
211 | * OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 10 | |
212 | * bytes are free for use. | |
213 | */ | |
214 | static struct nand_ecclayout fsmc_ecc4_64_layout = { | |
215 | .eccbytes = 52, | |
216 | .eccpos = { 2, 3, 4, 5, 6, 7, 8, | |
217 | 9, 10, 11, 12, 13, 14, | |
218 | 18, 19, 20, 21, 22, 23, 24, | |
219 | 25, 26, 27, 28, 29, 30, | |
220 | 34, 35, 36, 37, 38, 39, 40, | |
221 | 41, 42, 43, 44, 45, 46, | |
222 | 50, 51, 52, 53, 54, 55, 56, | |
223 | 57, 58, 59, 60, 61, 62, | |
224 | }, | |
225 | .oobfree = { | |
226 | {.offset = 15, .length = 3}, | |
227 | {.offset = 31, .length = 3}, | |
228 | {.offset = 47, .length = 3}, | |
229 | {.offset = 63, .length = 1}, | |
230 | } | |
231 | }; | |
232 | ||
233 | /* | |
234 | * ECC4 layout for NAND of pagesize 512 bytes & OOBsize 16 bytes. 13 bytes of | |
235 | * OOB size is reserved for ECC, Byte no. 4 & 5 reserved for bad block and One | |
236 | * byte is free for use. | |
237 | */ | |
238 | static struct nand_ecclayout fsmc_ecc4_16_layout = { | |
239 | .eccbytes = 13, | |
240 | .eccpos = { 0, 1, 2, 3, 6, 7, 8, | |
241 | 9, 10, 11, 12, 13, 14 | |
242 | }, | |
243 | .oobfree = { | |
244 | {.offset = 15, .length = 1}, | |
245 | } | |
246 | }; | |
247 | ||
6c009ab8 LW |
248 | /* |
249 | * ECC placement definitions in oobfree type format. | |
250 | * There are 13 bytes of ecc for every 512 byte block and it has to be read | |
251 | * consecutively and immediately after the 512 byte data block for hardware to | |
252 | * generate the error bit offsets in 512 byte data. | |
253 | * Managing the ecc bytes in the following way makes it easier for software to | |
254 | * read ecc bytes consecutive to data bytes. This way is similar to | |
255 | * oobfree structure maintained already in generic nand driver | |
256 | */ | |
257 | static struct fsmc_eccplace fsmc_ecc4_lp_place = { | |
258 | .eccplace = { | |
259 | {.offset = 2, .length = 13}, | |
260 | {.offset = 18, .length = 13}, | |
261 | {.offset = 34, .length = 13}, | |
262 | {.offset = 50, .length = 13}, | |
263 | {.offset = 66, .length = 13}, | |
264 | {.offset = 82, .length = 13}, | |
265 | {.offset = 98, .length = 13}, | |
266 | {.offset = 114, .length = 13} | |
267 | } | |
268 | }; | |
269 | ||
6c009ab8 LW |
270 | static struct fsmc_eccplace fsmc_ecc4_sp_place = { |
271 | .eccplace = { | |
272 | {.offset = 0, .length = 4}, | |
273 | {.offset = 6, .length = 9} | |
274 | } | |
275 | }; | |
276 | ||
6c009ab8 | 277 | /** |
593cd871 | 278 | * struct fsmc_nand_data - structure for FSMC NAND device state |
6c009ab8 | 279 | * |
593cd871 | 280 | * @pid: Part ID on the AMBA PrimeCell format |
6c009ab8 LW |
281 | * @mtd: MTD info for a NAND flash. |
282 | * @nand: Chip related info for a NAND flash. | |
71470324 VK |
283 | * @partitions: Partition info for a NAND Flash. |
284 | * @nr_partitions: Total number of partition of a NAND flash. | |
6c009ab8 LW |
285 | * |
286 | * @ecc_place: ECC placing locations in oobfree type format. | |
287 | * @bank: Bank number for probed device. | |
288 | * @clk: Clock structure for FSMC. | |
289 | * | |
4774fb0a VK |
290 | * @read_dma_chan: DMA channel for read access |
291 | * @write_dma_chan: DMA channel for write access to NAND | |
292 | * @dma_access_complete: Completion structure | |
293 | * | |
294 | * @data_pa: NAND Physical port for Data. | |
6c009ab8 LW |
295 | * @data_va: NAND port for Data. |
296 | * @cmd_va: NAND port for Command. | |
297 | * @addr_va: NAND port for Address. | |
298 | * @regs_va: FSMC regs base address. | |
299 | */ | |
300 | struct fsmc_nand_data { | |
593cd871 | 301 | u32 pid; |
6c009ab8 | 302 | struct nand_chip nand; |
71470324 VK |
303 | struct mtd_partition *partitions; |
304 | unsigned int nr_partitions; | |
6c009ab8 LW |
305 | |
306 | struct fsmc_eccplace *ecc_place; | |
307 | unsigned int bank; | |
712c4add | 308 | struct device *dev; |
4774fb0a | 309 | enum access_mode mode; |
6c009ab8 LW |
310 | struct clk *clk; |
311 | ||
4774fb0a VK |
312 | /* DMA related objects */ |
313 | struct dma_chan *read_dma_chan; | |
314 | struct dma_chan *write_dma_chan; | |
315 | struct completion dma_access_complete; | |
316 | ||
e2f6bce8 VK |
317 | struct fsmc_nand_timings *dev_timings; |
318 | ||
4774fb0a | 319 | dma_addr_t data_pa; |
6c009ab8 LW |
320 | void __iomem *data_va; |
321 | void __iomem *cmd_va; | |
322 | void __iomem *addr_va; | |
323 | void __iomem *regs_va; | |
324 | ||
325 | void (*select_chip)(uint32_t bank, uint32_t busw); | |
326 | }; | |
327 | ||
277af429 BB |
328 | static inline struct fsmc_nand_data *mtd_to_fsmc(struct mtd_info *mtd) |
329 | { | |
bdf3a555 | 330 | return container_of(mtd_to_nand(mtd), struct fsmc_nand_data, nand); |
277af429 BB |
331 | } |
332 | ||
6c009ab8 LW |
333 | /* Assert CS signal based on chipnr */ |
334 | static void fsmc_select_chip(struct mtd_info *mtd, int chipnr) | |
335 | { | |
4bd4ebcc | 336 | struct nand_chip *chip = mtd_to_nand(mtd); |
6c009ab8 LW |
337 | struct fsmc_nand_data *host; |
338 | ||
277af429 | 339 | host = mtd_to_fsmc(mtd); |
6c009ab8 LW |
340 | |
341 | switch (chipnr) { | |
342 | case -1: | |
343 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); | |
344 | break; | |
345 | case 0: | |
346 | case 1: | |
347 | case 2: | |
348 | case 3: | |
349 | if (host->select_chip) | |
350 | host->select_chip(chipnr, | |
351 | chip->options & NAND_BUSWIDTH_16); | |
352 | break; | |
353 | ||
354 | default: | |
6efadcf9 | 355 | dev_err(host->dev, "unsupported chip-select %d\n", chipnr); |
6c009ab8 LW |
356 | } |
357 | } | |
358 | ||
359 | /* | |
360 | * fsmc_cmd_ctrl - For facilitaing Hardware access | |
361 | * This routine allows hardware specific access to control-lines(ALE,CLE) | |
362 | */ | |
363 | static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
364 | { | |
4bd4ebcc | 365 | struct nand_chip *this = mtd_to_nand(mtd); |
277af429 | 366 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
605add7d | 367 | void __iomem *regs = host->regs_va; |
6c009ab8 LW |
368 | unsigned int bank = host->bank; |
369 | ||
370 | if (ctrl & NAND_CTRL_CHANGE) { | |
2a5dbead VK |
371 | u32 pc; |
372 | ||
6c009ab8 | 373 | if (ctrl & NAND_CLE) { |
2a5dbead VK |
374 | this->IO_ADDR_R = host->cmd_va; |
375 | this->IO_ADDR_W = host->cmd_va; | |
6c009ab8 | 376 | } else if (ctrl & NAND_ALE) { |
2a5dbead VK |
377 | this->IO_ADDR_R = host->addr_va; |
378 | this->IO_ADDR_W = host->addr_va; | |
6c009ab8 | 379 | } else { |
2a5dbead VK |
380 | this->IO_ADDR_R = host->data_va; |
381 | this->IO_ADDR_W = host->data_va; | |
6c009ab8 LW |
382 | } |
383 | ||
2a5dbead VK |
384 | pc = readl(FSMC_NAND_REG(regs, bank, PC)); |
385 | if (ctrl & NAND_NCE) | |
386 | pc |= FSMC_ENABLE; | |
387 | else | |
388 | pc &= ~FSMC_ENABLE; | |
a4742d51 | 389 | writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC)); |
6c009ab8 LW |
390 | } |
391 | ||
392 | mb(); | |
393 | ||
394 | if (cmd != NAND_CMD_NONE) | |
a4742d51 | 395 | writeb_relaxed(cmd, this->IO_ADDR_W); |
6c009ab8 LW |
396 | } |
397 | ||
398 | /* | |
399 | * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine | |
400 | * | |
401 | * This routine initializes timing parameters related to NAND memory access in | |
402 | * FSMC registers | |
403 | */ | |
2a5dbead | 404 | static void fsmc_nand_setup(void __iomem *regs, uint32_t bank, |
e2f6bce8 | 405 | uint32_t busw, struct fsmc_nand_timings *timings) |
6c009ab8 LW |
406 | { |
407 | uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON; | |
e2f6bce8 VK |
408 | uint32_t tclr, tar, thiz, thold, twait, tset; |
409 | struct fsmc_nand_timings *tims; | |
410 | struct fsmc_nand_timings default_timings = { | |
411 | .tclr = FSMC_TCLR_1, | |
412 | .tar = FSMC_TAR_1, | |
413 | .thiz = FSMC_THIZ_1, | |
414 | .thold = FSMC_THOLD_4, | |
415 | .twait = FSMC_TWAIT_6, | |
416 | .tset = FSMC_TSET_0, | |
417 | }; | |
418 | ||
419 | if (timings) | |
420 | tims = timings; | |
421 | else | |
422 | tims = &default_timings; | |
423 | ||
424 | tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT; | |
425 | tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT; | |
426 | thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT; | |
427 | thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT; | |
428 | twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT; | |
429 | tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT; | |
6c009ab8 LW |
430 | |
431 | if (busw) | |
a4742d51 VK |
432 | writel_relaxed(value | FSMC_DEVWID_16, |
433 | FSMC_NAND_REG(regs, bank, PC)); | |
6c009ab8 | 434 | else |
a4742d51 VK |
435 | writel_relaxed(value | FSMC_DEVWID_8, |
436 | FSMC_NAND_REG(regs, bank, PC)); | |
6c009ab8 | 437 | |
a4742d51 | 438 | writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar, |
2a5dbead | 439 | FSMC_NAND_REG(regs, bank, PC)); |
a4742d51 VK |
440 | writel_relaxed(thiz | thold | twait | tset, |
441 | FSMC_NAND_REG(regs, bank, COMM)); | |
442 | writel_relaxed(thiz | thold | twait | tset, | |
443 | FSMC_NAND_REG(regs, bank, ATTRIB)); | |
6c009ab8 LW |
444 | } |
445 | ||
446 | /* | |
447 | * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers | |
448 | */ | |
449 | static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode) | |
450 | { | |
277af429 | 451 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
2a5dbead | 452 | void __iomem *regs = host->regs_va; |
6c009ab8 LW |
453 | uint32_t bank = host->bank; |
454 | ||
a4742d51 | 455 | writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256, |
2a5dbead | 456 | FSMC_NAND_REG(regs, bank, PC)); |
a4742d51 | 457 | writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN, |
2a5dbead | 458 | FSMC_NAND_REG(regs, bank, PC)); |
a4742d51 | 459 | writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN, |
2a5dbead | 460 | FSMC_NAND_REG(regs, bank, PC)); |
6c009ab8 LW |
461 | } |
462 | ||
463 | /* | |
464 | * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by | |
25985edc | 465 | * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to |
6c009ab8 LW |
466 | * max of 8-bits) |
467 | */ | |
468 | static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data, | |
469 | uint8_t *ecc) | |
470 | { | |
277af429 | 471 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
2a5dbead | 472 | void __iomem *regs = host->regs_va; |
6c009ab8 LW |
473 | uint32_t bank = host->bank; |
474 | uint32_t ecc_tmp; | |
475 | unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT; | |
476 | ||
477 | do { | |
a4742d51 | 478 | if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY) |
6c009ab8 LW |
479 | break; |
480 | else | |
481 | cond_resched(); | |
482 | } while (!time_after_eq(jiffies, deadline)); | |
483 | ||
712c4add VK |
484 | if (time_after_eq(jiffies, deadline)) { |
485 | dev_err(host->dev, "calculate ecc timed out\n"); | |
486 | return -ETIMEDOUT; | |
487 | } | |
488 | ||
a4742d51 | 489 | ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1)); |
6c009ab8 LW |
490 | ecc[0] = (uint8_t) (ecc_tmp >> 0); |
491 | ecc[1] = (uint8_t) (ecc_tmp >> 8); | |
492 | ecc[2] = (uint8_t) (ecc_tmp >> 16); | |
493 | ecc[3] = (uint8_t) (ecc_tmp >> 24); | |
494 | ||
a4742d51 | 495 | ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2)); |
6c009ab8 LW |
496 | ecc[4] = (uint8_t) (ecc_tmp >> 0); |
497 | ecc[5] = (uint8_t) (ecc_tmp >> 8); | |
498 | ecc[6] = (uint8_t) (ecc_tmp >> 16); | |
499 | ecc[7] = (uint8_t) (ecc_tmp >> 24); | |
500 | ||
a4742d51 | 501 | ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3)); |
6c009ab8 LW |
502 | ecc[8] = (uint8_t) (ecc_tmp >> 0); |
503 | ecc[9] = (uint8_t) (ecc_tmp >> 8); | |
504 | ecc[10] = (uint8_t) (ecc_tmp >> 16); | |
505 | ecc[11] = (uint8_t) (ecc_tmp >> 24); | |
506 | ||
a4742d51 | 507 | ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS)); |
6c009ab8 LW |
508 | ecc[12] = (uint8_t) (ecc_tmp >> 16); |
509 | ||
510 | return 0; | |
511 | } | |
512 | ||
513 | /* | |
514 | * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by | |
25985edc | 515 | * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to |
6c009ab8 LW |
516 | * max of 1-bit) |
517 | */ | |
518 | static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data, | |
519 | uint8_t *ecc) | |
520 | { | |
277af429 | 521 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
2a5dbead | 522 | void __iomem *regs = host->regs_va; |
6c009ab8 LW |
523 | uint32_t bank = host->bank; |
524 | uint32_t ecc_tmp; | |
525 | ||
a4742d51 | 526 | ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1)); |
6c009ab8 LW |
527 | ecc[0] = (uint8_t) (ecc_tmp >> 0); |
528 | ecc[1] = (uint8_t) (ecc_tmp >> 8); | |
529 | ecc[2] = (uint8_t) (ecc_tmp >> 16); | |
530 | ||
531 | return 0; | |
532 | } | |
533 | ||
519300cf VK |
534 | /* Count the number of 0's in buff upto a max of max_bits */ |
535 | static int count_written_bits(uint8_t *buff, int size, int max_bits) | |
536 | { | |
537 | int k, written_bits = 0; | |
538 | ||
539 | for (k = 0; k < size; k++) { | |
540 | written_bits += hweight8(~buff[k]); | |
541 | if (written_bits > max_bits) | |
542 | break; | |
543 | } | |
544 | ||
545 | return written_bits; | |
546 | } | |
547 | ||
4774fb0a VK |
548 | static void dma_complete(void *param) |
549 | { | |
550 | struct fsmc_nand_data *host = param; | |
551 | ||
552 | complete(&host->dma_access_complete); | |
553 | } | |
554 | ||
555 | static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len, | |
556 | enum dma_data_direction direction) | |
557 | { | |
558 | struct dma_chan *chan; | |
559 | struct dma_device *dma_dev; | |
560 | struct dma_async_tx_descriptor *tx; | |
561 | dma_addr_t dma_dst, dma_src, dma_addr; | |
562 | dma_cookie_t cookie; | |
563 | unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; | |
564 | int ret; | |
818a45b1 | 565 | unsigned long time_left; |
4774fb0a VK |
566 | |
567 | if (direction == DMA_TO_DEVICE) | |
568 | chan = host->write_dma_chan; | |
569 | else if (direction == DMA_FROM_DEVICE) | |
570 | chan = host->read_dma_chan; | |
571 | else | |
572 | return -EINVAL; | |
573 | ||
574 | dma_dev = chan->device; | |
575 | dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction); | |
576 | ||
577 | if (direction == DMA_TO_DEVICE) { | |
578 | dma_src = dma_addr; | |
579 | dma_dst = host->data_pa; | |
4774fb0a VK |
580 | } else { |
581 | dma_src = host->data_pa; | |
582 | dma_dst = dma_addr; | |
4774fb0a VK |
583 | } |
584 | ||
585 | tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src, | |
586 | len, flags); | |
4774fb0a VK |
587 | if (!tx) { |
588 | dev_err(host->dev, "device_prep_dma_memcpy error\n"); | |
d1806a5c BZ |
589 | ret = -EIO; |
590 | goto unmap_dma; | |
4774fb0a VK |
591 | } |
592 | ||
593 | tx->callback = dma_complete; | |
594 | tx->callback_param = host; | |
595 | cookie = tx->tx_submit(tx); | |
596 | ||
597 | ret = dma_submit_error(cookie); | |
598 | if (ret) { | |
599 | dev_err(host->dev, "dma_submit_error %d\n", cookie); | |
d1806a5c | 600 | goto unmap_dma; |
4774fb0a VK |
601 | } |
602 | ||
603 | dma_async_issue_pending(chan); | |
604 | ||
818a45b1 | 605 | time_left = |
928aa2ae | 606 | wait_for_completion_timeout(&host->dma_access_complete, |
4774fb0a | 607 | msecs_to_jiffies(3000)); |
818a45b1 | 608 | if (time_left == 0) { |
b177ea34 | 609 | dmaengine_terminate_all(chan); |
4774fb0a | 610 | dev_err(host->dev, "wait_for_completion_timeout\n"); |
0bda3e19 | 611 | ret = -ETIMEDOUT; |
d1806a5c | 612 | goto unmap_dma; |
4774fb0a VK |
613 | } |
614 | ||
d1806a5c BZ |
615 | ret = 0; |
616 | ||
617 | unmap_dma: | |
618 | dma_unmap_single(dma_dev->dev, dma_addr, len, direction); | |
619 | ||
620 | return ret; | |
4774fb0a VK |
621 | } |
622 | ||
604e7544 VK |
623 | /* |
624 | * fsmc_write_buf - write buffer to chip | |
625 | * @mtd: MTD device structure | |
626 | * @buf: data buffer | |
627 | * @len: number of bytes to write | |
628 | */ | |
629 | static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) | |
630 | { | |
631 | int i; | |
4bd4ebcc | 632 | struct nand_chip *chip = mtd_to_nand(mtd); |
604e7544 VK |
633 | |
634 | if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) && | |
635 | IS_ALIGNED(len, sizeof(uint32_t))) { | |
636 | uint32_t *p = (uint32_t *)buf; | |
637 | len = len >> 2; | |
638 | for (i = 0; i < len; i++) | |
a4742d51 | 639 | writel_relaxed(p[i], chip->IO_ADDR_W); |
604e7544 VK |
640 | } else { |
641 | for (i = 0; i < len; i++) | |
a4742d51 | 642 | writeb_relaxed(buf[i], chip->IO_ADDR_W); |
604e7544 VK |
643 | } |
644 | } | |
645 | ||
646 | /* | |
647 | * fsmc_read_buf - read chip data into buffer | |
648 | * @mtd: MTD device structure | |
649 | * @buf: buffer to store date | |
650 | * @len: number of bytes to read | |
651 | */ | |
652 | static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
653 | { | |
654 | int i; | |
4bd4ebcc | 655 | struct nand_chip *chip = mtd_to_nand(mtd); |
604e7544 VK |
656 | |
657 | if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) && | |
658 | IS_ALIGNED(len, sizeof(uint32_t))) { | |
659 | uint32_t *p = (uint32_t *)buf; | |
660 | len = len >> 2; | |
661 | for (i = 0; i < len; i++) | |
a4742d51 | 662 | p[i] = readl_relaxed(chip->IO_ADDR_R); |
604e7544 VK |
663 | } else { |
664 | for (i = 0; i < len; i++) | |
a4742d51 | 665 | buf[i] = readb_relaxed(chip->IO_ADDR_R); |
604e7544 VK |
666 | } |
667 | } | |
668 | ||
4774fb0a VK |
669 | /* |
670 | * fsmc_read_buf_dma - read chip data into buffer | |
671 | * @mtd: MTD device structure | |
672 | * @buf: buffer to store date | |
673 | * @len: number of bytes to read | |
674 | */ | |
675 | static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len) | |
676 | { | |
277af429 | 677 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
4774fb0a | 678 | |
4774fb0a VK |
679 | dma_xfer(host, buf, len, DMA_FROM_DEVICE); |
680 | } | |
681 | ||
682 | /* | |
683 | * fsmc_write_buf_dma - write buffer to chip | |
684 | * @mtd: MTD device structure | |
685 | * @buf: data buffer | |
686 | * @len: number of bytes to write | |
687 | */ | |
688 | static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf, | |
689 | int len) | |
690 | { | |
277af429 | 691 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
4774fb0a | 692 | |
4774fb0a VK |
693 | dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE); |
694 | } | |
695 | ||
6c009ab8 LW |
696 | /* |
697 | * fsmc_read_page_hwecc | |
698 | * @mtd: mtd info structure | |
699 | * @chip: nand chip info structure | |
700 | * @buf: buffer to store read data | |
1fbb938d | 701 | * @oob_required: caller expects OOB data read to chip->oob_poi |
6c009ab8 LW |
702 | * @page: page number to read |
703 | * | |
25985edc | 704 | * This routine is needed for fsmc version 8 as reading from NAND chip has to be |
6c009ab8 LW |
705 | * performed in a strict sequence as follows: |
706 | * data(512 byte) -> ecc(13 byte) | |
25985edc | 707 | * After this read, fsmc hardware generates and reports error data bits(up to a |
6c009ab8 LW |
708 | * max of 8 bits) |
709 | */ | |
710 | static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 711 | uint8_t *buf, int oob_required, int page) |
6c009ab8 | 712 | { |
277af429 | 713 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
6c009ab8 LW |
714 | struct fsmc_eccplace *ecc_place = host->ecc_place; |
715 | int i, j, s, stat, eccsize = chip->ecc.size; | |
716 | int eccbytes = chip->ecc.bytes; | |
717 | int eccsteps = chip->ecc.steps; | |
718 | uint8_t *p = buf; | |
719 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
720 | uint8_t *ecc_code = chip->buffers->ecccode; | |
721 | int off, len, group = 0; | |
722 | /* | |
723 | * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we | |
724 | * end up reading 14 bytes (7 words) from oob. The local array is | |
725 | * to maintain word alignment | |
726 | */ | |
727 | uint16_t ecc_oob[7]; | |
728 | uint8_t *oob = (uint8_t *)&ecc_oob[0]; | |
3f91e94f | 729 | unsigned int max_bitflips = 0; |
6c009ab8 LW |
730 | |
731 | for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) { | |
6c009ab8 LW |
732 | chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page); |
733 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
734 | chip->read_buf(mtd, p, eccsize); | |
735 | ||
736 | for (j = 0; j < eccbytes;) { | |
737 | off = ecc_place->eccplace[group].offset; | |
738 | len = ecc_place->eccplace[group].length; | |
739 | group++; | |
740 | ||
741 | /* | |
4cbe1bf0 VK |
742 | * length is intentionally kept a higher multiple of 2 |
743 | * to read at least 13 bytes even in case of 16 bit NAND | |
744 | * devices | |
745 | */ | |
aea686b4 VK |
746 | if (chip->options & NAND_BUSWIDTH_16) |
747 | len = roundup(len, 2); | |
748 | ||
6c009ab8 LW |
749 | chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page); |
750 | chip->read_buf(mtd, oob + j, len); | |
751 | j += len; | |
752 | } | |
753 | ||
519300cf | 754 | memcpy(&ecc_code[i], oob, chip->ecc.bytes); |
6c009ab8 LW |
755 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
756 | ||
757 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
3f91e94f | 758 | if (stat < 0) { |
6c009ab8 | 759 | mtd->ecc_stats.failed++; |
3f91e94f | 760 | } else { |
6c009ab8 | 761 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
762 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
763 | } | |
6c009ab8 LW |
764 | } |
765 | ||
3f91e94f | 766 | return max_bitflips; |
6c009ab8 LW |
767 | } |
768 | ||
769 | /* | |
753e0139 | 770 | * fsmc_bch8_correct_data |
6c009ab8 LW |
771 | * @mtd: mtd info structure |
772 | * @dat: buffer of read data | |
773 | * @read_ecc: ecc read from device spare area | |
774 | * @calc_ecc: ecc calculated from read data | |
775 | * | |
776 | * calc_ecc is a 104 bit information containing maximum of 8 error | |
777 | * offset informations of 13 bits each in 512 bytes of read data. | |
778 | */ | |
753e0139 | 779 | static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat, |
6c009ab8 LW |
780 | uint8_t *read_ecc, uint8_t *calc_ecc) |
781 | { | |
4bd4ebcc | 782 | struct nand_chip *chip = mtd_to_nand(mtd); |
277af429 | 783 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
2a5dbead | 784 | void __iomem *regs = host->regs_va; |
6c009ab8 | 785 | unsigned int bank = host->bank; |
a612c2ae | 786 | uint32_t err_idx[8]; |
6c009ab8 | 787 | uint32_t num_err, i; |
753e0139 | 788 | uint32_t ecc1, ecc2, ecc3, ecc4; |
6c009ab8 | 789 | |
a4742d51 | 790 | num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF; |
519300cf VK |
791 | |
792 | /* no bit flipping */ | |
793 | if (likely(num_err == 0)) | |
794 | return 0; | |
795 | ||
796 | /* too many errors */ | |
797 | if (unlikely(num_err > 8)) { | |
798 | /* | |
799 | * This is a temporary erase check. A newly erased page read | |
800 | * would result in an ecc error because the oob data is also | |
801 | * erased to FF and the calculated ecc for an FF data is not | |
802 | * FF..FF. | |
803 | * This is a workaround to skip performing correction in case | |
804 | * data is FF..FF | |
805 | * | |
806 | * Logic: | |
807 | * For every page, each bit written as 0 is counted until these | |
808 | * number of bits are greater than 8 (the maximum correction | |
809 | * capability of FSMC for each 512 + 13 bytes) | |
810 | */ | |
811 | ||
812 | int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8); | |
813 | int bits_data = count_written_bits(dat, chip->ecc.size, 8); | |
814 | ||
815 | if ((bits_ecc + bits_data) <= 8) { | |
816 | if (bits_data) | |
817 | memset(dat, 0xff, chip->ecc.size); | |
818 | return bits_data; | |
819 | } | |
820 | ||
821 | return -EBADMSG; | |
822 | } | |
823 | ||
6c009ab8 LW |
824 | /* |
825 | * ------------------- calc_ecc[] bit wise -----------|--13 bits--| | |
826 | * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--| | |
827 | * | |
828 | * calc_ecc is a 104 bit information containing maximum of 8 error | |
829 | * offset informations of 13 bits each. calc_ecc is copied into a | |
830 | * uint64_t array and error offset indexes are populated in err_idx | |
831 | * array | |
832 | */ | |
a4742d51 VK |
833 | ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1)); |
834 | ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2)); | |
835 | ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3)); | |
836 | ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS)); | |
753e0139 AV |
837 | |
838 | err_idx[0] = (ecc1 >> 0) & 0x1FFF; | |
839 | err_idx[1] = (ecc1 >> 13) & 0x1FFF; | |
840 | err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F); | |
841 | err_idx[3] = (ecc2 >> 7) & 0x1FFF; | |
842 | err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF); | |
843 | err_idx[5] = (ecc3 >> 1) & 0x1FFF; | |
844 | err_idx[6] = (ecc3 >> 14) & 0x1FFF; | |
845 | err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F); | |
6c009ab8 LW |
846 | |
847 | i = 0; | |
848 | while (num_err--) { | |
849 | change_bit(0, (unsigned long *)&err_idx[i]); | |
850 | change_bit(1, (unsigned long *)&err_idx[i]); | |
851 | ||
b533f8d8 | 852 | if (err_idx[i] < chip->ecc.size * 8) { |
6c009ab8 LW |
853 | change_bit(err_idx[i], (unsigned long *)dat); |
854 | i++; | |
855 | } | |
856 | } | |
857 | return i; | |
858 | } | |
859 | ||
4774fb0a VK |
860 | static bool filter(struct dma_chan *chan, void *slave) |
861 | { | |
862 | chan->private = slave; | |
863 | return true; | |
864 | } | |
865 | ||
eea62819 | 866 | #ifdef CONFIG_OF |
06f25510 | 867 | static int fsmc_nand_probe_config_dt(struct platform_device *pdev, |
d8929942 | 868 | struct device_node *np) |
eea62819 SR |
869 | { |
870 | struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev); | |
871 | u32 val; | |
62b57f4c | 872 | int ret; |
eea62819 SR |
873 | |
874 | /* Set default NAND width to 8 bits */ | |
875 | pdata->width = 8; | |
876 | if (!of_property_read_u32(np, "bank-width", &val)) { | |
877 | if (val == 2) { | |
878 | pdata->width = 16; | |
879 | } else if (val != 1) { | |
880 | dev_err(&pdev->dev, "invalid bank-width %u\n", val); | |
881 | return -EINVAL; | |
882 | } | |
883 | } | |
eea62819 SR |
884 | if (of_get_property(np, "nand-skip-bbtscan", NULL)) |
885 | pdata->options = NAND_SKIP_BBTSCAN; | |
886 | ||
64ddba4d MYK |
887 | pdata->nand_timings = devm_kzalloc(&pdev->dev, |
888 | sizeof(*pdata->nand_timings), GFP_KERNEL); | |
d9a21ae8 | 889 | if (!pdata->nand_timings) |
64ddba4d | 890 | return -ENOMEM; |
62b57f4c | 891 | ret = of_property_read_u8_array(np, "timings", (u8 *)pdata->nand_timings, |
64ddba4d | 892 | sizeof(*pdata->nand_timings)); |
62b57f4c SR |
893 | if (ret) { |
894 | dev_info(&pdev->dev, "No timings in dts specified, using default timings!\n"); | |
895 | pdata->nand_timings = NULL; | |
896 | } | |
64ddba4d MYK |
897 | |
898 | /* Set default NAND bank to 0 */ | |
899 | pdata->bank = 0; | |
900 | if (!of_property_read_u32(np, "bank", &val)) { | |
901 | if (val > 3) { | |
902 | dev_err(&pdev->dev, "invalid bank %u\n", val); | |
903 | return -EINVAL; | |
904 | } | |
905 | pdata->bank = val; | |
906 | } | |
eea62819 SR |
907 | return 0; |
908 | } | |
909 | #else | |
06f25510 | 910 | static int fsmc_nand_probe_config_dt(struct platform_device *pdev, |
d8929942 | 911 | struct device_node *np) |
eea62819 SR |
912 | { |
913 | return -ENOSYS; | |
914 | } | |
915 | #endif | |
916 | ||
6c009ab8 LW |
917 | /* |
918 | * fsmc_nand_probe - Probe function | |
919 | * @pdev: platform device structure | |
920 | */ | |
921 | static int __init fsmc_nand_probe(struct platform_device *pdev) | |
922 | { | |
923 | struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev); | |
eea62819 | 924 | struct device_node __maybe_unused *np = pdev->dev.of_node; |
6c009ab8 LW |
925 | struct fsmc_nand_data *host; |
926 | struct mtd_info *mtd; | |
927 | struct nand_chip *nand; | |
6c009ab8 | 928 | struct resource *res; |
4774fb0a | 929 | dma_cap_mask_t mask; |
4ad916bc | 930 | int ret = 0; |
593cd871 LW |
931 | u32 pid; |
932 | int i; | |
6c009ab8 | 933 | |
eea62819 SR |
934 | if (np) { |
935 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
936 | pdev->dev.platform_data = pdata; | |
937 | ret = fsmc_nand_probe_config_dt(pdev, np); | |
938 | if (ret) { | |
939 | dev_err(&pdev->dev, "no platform data\n"); | |
940 | return -ENODEV; | |
941 | } | |
942 | } | |
943 | ||
6c009ab8 LW |
944 | if (!pdata) { |
945 | dev_err(&pdev->dev, "platform data is NULL\n"); | |
946 | return -EINVAL; | |
947 | } | |
948 | ||
949 | /* Allocate memory for the device structure (and zero it) */ | |
82b9dbe2 | 950 | host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); |
d9a21ae8 | 951 | if (!host) |
6c009ab8 | 952 | return -ENOMEM; |
6c009ab8 LW |
953 | |
954 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data"); | |
b0de774c TR |
955 | host->data_va = devm_ioremap_resource(&pdev->dev, res); |
956 | if (IS_ERR(host->data_va)) | |
957 | return PTR_ERR(host->data_va); | |
cbf29b83 | 958 | |
6d7b42a4 | 959 | host->data_pa = (dma_addr_t)res->start; |
6c009ab8 | 960 | |
6d7b42a4 | 961 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr"); |
b0de774c TR |
962 | host->addr_va = devm_ioremap_resource(&pdev->dev, res); |
963 | if (IS_ERR(host->addr_va)) | |
964 | return PTR_ERR(host->addr_va); | |
6c009ab8 | 965 | |
6d7b42a4 | 966 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd"); |
b0de774c TR |
967 | host->cmd_va = devm_ioremap_resource(&pdev->dev, res); |
968 | if (IS_ERR(host->cmd_va)) | |
969 | return PTR_ERR(host->cmd_va); | |
6c009ab8 LW |
970 | |
971 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs"); | |
b0de774c TR |
972 | host->regs_va = devm_ioremap_resource(&pdev->dev, res); |
973 | if (IS_ERR(host->regs_va)) | |
974 | return PTR_ERR(host->regs_va); | |
6c009ab8 LW |
975 | |
976 | host->clk = clk_get(&pdev->dev, NULL); | |
977 | if (IS_ERR(host->clk)) { | |
978 | dev_err(&pdev->dev, "failed to fetch block clock\n"); | |
82b9dbe2 | 979 | return PTR_ERR(host->clk); |
6c009ab8 LW |
980 | } |
981 | ||
e25da1c0 | 982 | ret = clk_prepare_enable(host->clk); |
6c009ab8 | 983 | if (ret) |
e25da1c0 | 984 | goto err_clk_prepare_enable; |
6c009ab8 | 985 | |
593cd871 LW |
986 | /* |
987 | * This device ID is actually a common AMBA ID as used on the | |
988 | * AMBA PrimeCell bus. However it is not a PrimeCell. | |
989 | */ | |
990 | for (pid = 0, i = 0; i < 4; i++) | |
991 | pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8); | |
992 | host->pid = pid; | |
993 | dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, " | |
994 | "revision %02x, config %02x\n", | |
995 | AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid), | |
996 | AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid)); | |
997 | ||
6c009ab8 LW |
998 | host->bank = pdata->bank; |
999 | host->select_chip = pdata->select_bank; | |
71470324 VK |
1000 | host->partitions = pdata->partitions; |
1001 | host->nr_partitions = pdata->nr_partitions; | |
712c4add | 1002 | host->dev = &pdev->dev; |
e2f6bce8 | 1003 | host->dev_timings = pdata->nand_timings; |
4774fb0a VK |
1004 | host->mode = pdata->mode; |
1005 | ||
1006 | if (host->mode == USE_DMA_ACCESS) | |
1007 | init_completion(&host->dma_access_complete); | |
1008 | ||
6c009ab8 | 1009 | /* Link all private pointers */ |
bdf3a555 | 1010 | mtd = nand_to_mtd(&host->nand); |
6c009ab8 LW |
1011 | nand = &host->nand; |
1012 | mtd->priv = nand; | |
1013 | nand->priv = host; | |
a61ae81a | 1014 | nand_set_flash_node(nand, np); |
6c009ab8 | 1015 | |
bdf3a555 | 1016 | mtd->dev.parent = &pdev->dev; |
6c009ab8 LW |
1017 | nand->IO_ADDR_R = host->data_va; |
1018 | nand->IO_ADDR_W = host->data_va; | |
1019 | nand->cmd_ctrl = fsmc_cmd_ctrl; | |
1020 | nand->chip_delay = 30; | |
1021 | ||
e278fc71 SR |
1022 | /* |
1023 | * Setup default ECC mode. nand_dt_init() called from nand_scan_ident() | |
1024 | * can overwrite this value if the DT provides a different value. | |
1025 | */ | |
6c009ab8 LW |
1026 | nand->ecc.mode = NAND_ECC_HW; |
1027 | nand->ecc.hwctl = fsmc_enable_hwecc; | |
1028 | nand->ecc.size = 512; | |
1029 | nand->options = pdata->options; | |
1030 | nand->select_chip = fsmc_select_chip; | |
467e6e7b | 1031 | nand->badblockbits = 7; |
63752199 | 1032 | nand_set_flash_node(nand, np); |
6c009ab8 LW |
1033 | |
1034 | if (pdata->width == FSMC_NAND_BW16) | |
1035 | nand->options |= NAND_BUSWIDTH_16; | |
1036 | ||
4774fb0a VK |
1037 | switch (host->mode) { |
1038 | case USE_DMA_ACCESS: | |
1039 | dma_cap_zero(mask); | |
1040 | dma_cap_set(DMA_MEMCPY, mask); | |
1041 | host->read_dma_chan = dma_request_channel(mask, filter, | |
1042 | pdata->read_dma_priv); | |
1043 | if (!host->read_dma_chan) { | |
1044 | dev_err(&pdev->dev, "Unable to get read dma channel\n"); | |
1045 | goto err_req_read_chnl; | |
1046 | } | |
1047 | host->write_dma_chan = dma_request_channel(mask, filter, | |
1048 | pdata->write_dma_priv); | |
1049 | if (!host->write_dma_chan) { | |
1050 | dev_err(&pdev->dev, "Unable to get write dma channel\n"); | |
1051 | goto err_req_write_chnl; | |
1052 | } | |
1053 | nand->read_buf = fsmc_read_buf_dma; | |
1054 | nand->write_buf = fsmc_write_buf_dma; | |
1055 | break; | |
1056 | ||
1057 | default: | |
1058 | case USE_WORD_ACCESS: | |
604e7544 VK |
1059 | nand->read_buf = fsmc_read_buf; |
1060 | nand->write_buf = fsmc_write_buf; | |
4774fb0a | 1061 | break; |
604e7544 VK |
1062 | } |
1063 | ||
2a5dbead VK |
1064 | fsmc_nand_setup(host->regs_va, host->bank, |
1065 | nand->options & NAND_BUSWIDTH_16, | |
e2f6bce8 | 1066 | host->dev_timings); |
6c009ab8 | 1067 | |
593cd871 | 1068 | if (AMBA_REV_BITS(host->pid) >= 8) { |
6c009ab8 LW |
1069 | nand->ecc.read_page = fsmc_read_page_hwecc; |
1070 | nand->ecc.calculate = fsmc_read_hwecc_ecc4; | |
753e0139 | 1071 | nand->ecc.correct = fsmc_bch8_correct_data; |
6c009ab8 | 1072 | nand->ecc.bytes = 13; |
6a918bad | 1073 | nand->ecc.strength = 8; |
6c009ab8 LW |
1074 | } |
1075 | ||
1076 | /* | |
25985edc | 1077 | * Scan to find existence of the device |
6c009ab8 | 1078 | */ |
bdf3a555 | 1079 | if (nand_scan_ident(mtd, 1, NULL)) { |
6c009ab8 LW |
1080 | ret = -ENXIO; |
1081 | dev_err(&pdev->dev, "No NAND Device found!\n"); | |
82b9dbe2 | 1082 | goto err_scan_ident; |
6c009ab8 LW |
1083 | } |
1084 | ||
593cd871 | 1085 | if (AMBA_REV_BITS(host->pid) >= 8) { |
bdf3a555 | 1086 | switch (mtd->oobsize) { |
e29ee57b BY |
1087 | case 16: |
1088 | nand->ecc.layout = &fsmc_ecc4_16_layout; | |
6c009ab8 | 1089 | host->ecc_place = &fsmc_ecc4_sp_place; |
e29ee57b BY |
1090 | break; |
1091 | case 64: | |
1092 | nand->ecc.layout = &fsmc_ecc4_64_layout; | |
1093 | host->ecc_place = &fsmc_ecc4_lp_place; | |
1094 | break; | |
1095 | case 128: | |
1096 | nand->ecc.layout = &fsmc_ecc4_128_layout; | |
1097 | host->ecc_place = &fsmc_ecc4_lp_place; | |
1098 | break; | |
0c78e93b AV |
1099 | case 224: |
1100 | nand->ecc.layout = &fsmc_ecc4_224_layout; | |
1101 | host->ecc_place = &fsmc_ecc4_lp_place; | |
1102 | break; | |
e29ee57b BY |
1103 | case 256: |
1104 | nand->ecc.layout = &fsmc_ecc4_256_layout; | |
6c009ab8 | 1105 | host->ecc_place = &fsmc_ecc4_lp_place; |
e29ee57b BY |
1106 | break; |
1107 | default: | |
67b19a63 JH |
1108 | dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n", |
1109 | mtd->oobsize); | |
6efadcf9 SR |
1110 | ret = -EINVAL; |
1111 | goto err_probe; | |
6c009ab8 LW |
1112 | } |
1113 | } else { | |
e278fc71 SR |
1114 | switch (nand->ecc.mode) { |
1115 | case NAND_ECC_HW: | |
1116 | dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n"); | |
1117 | nand->ecc.calculate = fsmc_read_hwecc_ecc1; | |
1118 | nand->ecc.correct = nand_correct_data; | |
1119 | nand->ecc.bytes = 3; | |
1120 | nand->ecc.strength = 1; | |
e29ee57b | 1121 | break; |
e278fc71 SR |
1122 | |
1123 | case NAND_ECC_SOFT_BCH: | |
1124 | dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n"); | |
e29ee57b | 1125 | break; |
e278fc71 | 1126 | |
e29ee57b | 1127 | default: |
e278fc71 | 1128 | dev_err(&pdev->dev, "Unsupported ECC mode!\n"); |
6efadcf9 | 1129 | goto err_probe; |
e29ee57b | 1130 | } |
e278fc71 SR |
1131 | |
1132 | /* | |
1133 | * Don't set layout for BCH4 SW ECC. This will be | |
1134 | * generated later in nand_bch_init() later. | |
1135 | */ | |
1136 | if (nand->ecc.mode != NAND_ECC_SOFT_BCH) { | |
bdf3a555 | 1137 | switch (mtd->oobsize) { |
e278fc71 SR |
1138 | case 16: |
1139 | nand->ecc.layout = &fsmc_ecc1_16_layout; | |
1140 | break; | |
1141 | case 64: | |
1142 | nand->ecc.layout = &fsmc_ecc1_64_layout; | |
1143 | break; | |
1144 | case 128: | |
1145 | nand->ecc.layout = &fsmc_ecc1_128_layout; | |
1146 | break; | |
1147 | default: | |
1148 | dev_warn(&pdev->dev, | |
1149 | "No oob scheme defined for oobsize %d\n", | |
1150 | mtd->oobsize); | |
1151 | ret = -EINVAL; | |
1152 | goto err_probe; | |
1153 | } | |
1154 | } | |
6c009ab8 LW |
1155 | } |
1156 | ||
1157 | /* Second stage of scan to fill MTD data-structures */ | |
bdf3a555 | 1158 | if (nand_scan_tail(mtd)) { |
6c009ab8 LW |
1159 | ret = -ENXIO; |
1160 | goto err_probe; | |
1161 | } | |
1162 | ||
1163 | /* | |
1164 | * The partition information can is accessed by (in the same precedence) | |
1165 | * | |
1166 | * command line through Bootloader, | |
1167 | * platform data, | |
1168 | * default partition information present in driver. | |
1169 | */ | |
6c009ab8 | 1170 | /* |
8d3f8bb8 | 1171 | * Check for partition info passed |
6c009ab8 | 1172 | */ |
bdf3a555 BB |
1173 | mtd->name = "nand"; |
1174 | ret = mtd_device_register(mtd, host->partitions, host->nr_partitions); | |
99335d00 | 1175 | if (ret) |
6c009ab8 | 1176 | goto err_probe; |
6c009ab8 LW |
1177 | |
1178 | platform_set_drvdata(pdev, host); | |
1179 | dev_info(&pdev->dev, "FSMC NAND driver registration successful\n"); | |
1180 | return 0; | |
1181 | ||
1182 | err_probe: | |
82b9dbe2 | 1183 | err_scan_ident: |
4774fb0a VK |
1184 | if (host->mode == USE_DMA_ACCESS) |
1185 | dma_release_channel(host->write_dma_chan); | |
1186 | err_req_write_chnl: | |
1187 | if (host->mode == USE_DMA_ACCESS) | |
1188 | dma_release_channel(host->read_dma_chan); | |
1189 | err_req_read_chnl: | |
e25da1c0 VK |
1190 | clk_disable_unprepare(host->clk); |
1191 | err_clk_prepare_enable: | |
82b9dbe2 | 1192 | clk_put(host->clk); |
6c009ab8 LW |
1193 | return ret; |
1194 | } | |
1195 | ||
1196 | /* | |
1197 | * Clean up routine | |
1198 | */ | |
1199 | static int fsmc_nand_remove(struct platform_device *pdev) | |
1200 | { | |
1201 | struct fsmc_nand_data *host = platform_get_drvdata(pdev); | |
1202 | ||
6c009ab8 | 1203 | if (host) { |
bdf3a555 | 1204 | nand_release(nand_to_mtd(&host->nand)); |
4774fb0a VK |
1205 | |
1206 | if (host->mode == USE_DMA_ACCESS) { | |
1207 | dma_release_channel(host->write_dma_chan); | |
1208 | dma_release_channel(host->read_dma_chan); | |
1209 | } | |
e25da1c0 | 1210 | clk_disable_unprepare(host->clk); |
6c009ab8 | 1211 | clk_put(host->clk); |
6c009ab8 | 1212 | } |
82b9dbe2 | 1213 | |
6c009ab8 LW |
1214 | return 0; |
1215 | } | |
1216 | ||
80ce4dde | 1217 | #ifdef CONFIG_PM_SLEEP |
6c009ab8 LW |
1218 | static int fsmc_nand_suspend(struct device *dev) |
1219 | { | |
1220 | struct fsmc_nand_data *host = dev_get_drvdata(dev); | |
1221 | if (host) | |
e25da1c0 | 1222 | clk_disable_unprepare(host->clk); |
6c009ab8 LW |
1223 | return 0; |
1224 | } | |
1225 | ||
1226 | static int fsmc_nand_resume(struct device *dev) | |
1227 | { | |
1228 | struct fsmc_nand_data *host = dev_get_drvdata(dev); | |
f63acb75 | 1229 | if (host) { |
e25da1c0 | 1230 | clk_prepare_enable(host->clk); |
f63acb75 | 1231 | fsmc_nand_setup(host->regs_va, host->bank, |
e2f6bce8 VK |
1232 | host->nand.options & NAND_BUSWIDTH_16, |
1233 | host->dev_timings); | |
f63acb75 | 1234 | } |
6c009ab8 LW |
1235 | return 0; |
1236 | } | |
80ce4dde | 1237 | #endif |
6c009ab8 | 1238 | |
f63acb75 | 1239 | static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume); |
6c009ab8 | 1240 | |
eea62819 SR |
1241 | #ifdef CONFIG_OF |
1242 | static const struct of_device_id fsmc_nand_id_table[] = { | |
1243 | { .compatible = "st,spear600-fsmc-nand" }, | |
ba785205 | 1244 | { .compatible = "stericsson,fsmc-nand" }, |
eea62819 SR |
1245 | {} |
1246 | }; | |
1247 | MODULE_DEVICE_TABLE(of, fsmc_nand_id_table); | |
1248 | #endif | |
1249 | ||
6c009ab8 LW |
1250 | static struct platform_driver fsmc_nand_driver = { |
1251 | .remove = fsmc_nand_remove, | |
1252 | .driver = { | |
6c009ab8 | 1253 | .name = "fsmc-nand", |
eea62819 | 1254 | .of_match_table = of_match_ptr(fsmc_nand_id_table), |
6c009ab8 | 1255 | .pm = &fsmc_nand_pm_ops, |
6c009ab8 LW |
1256 | }, |
1257 | }; | |
1258 | ||
307d2a51 | 1259 | module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe); |
6c009ab8 LW |
1260 | |
1261 | MODULE_LICENSE("GPL"); | |
1262 | MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi"); | |
1263 | MODULE_DESCRIPTION("NAND driver for SPEAr Platforms"); |