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34f6e157 SH |
1 | /* |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright 2008 Sascha Hauer, kernel@pengutronix.de | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
17 | * MA 02110-1301, USA. | |
18 | */ | |
19 | ||
20 | #include <linux/delay.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/mtd/mtd.h> | |
25 | #include <linux/mtd/nand.h> | |
26 | #include <linux/mtd/partitions.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/device.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/clk.h> | |
31 | #include <linux/err.h> | |
32 | #include <linux/io.h> | |
63f1474c SH |
33 | #include <linux/irq.h> |
34 | #include <linux/completion.h> | |
d367e37e | 35 | #include <linux/of.h> |
6436356b UKK |
36 | #include <linux/of_device.h> |
37 | #include <linux/of_mtd.h> | |
34f6e157 SH |
38 | |
39 | #include <asm/mach/flash.h> | |
82906b13 | 40 | #include <linux/platform_data/mtd-mxc_nand.h> |
34f6e157 SH |
41 | |
42 | #define DRIVER_NAME "mxc_nand" | |
43 | ||
44 | /* Addresses for NFC registers */ | |
1bc99180 SH |
45 | #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00) |
46 | #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04) | |
47 | #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06) | |
48 | #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08) | |
49 | #define NFC_V1_V2_CONFIG (host->regs + 0x0a) | |
50 | #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c) | |
51 | #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e) | |
52 | #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10) | |
53 | #define NFC_V1_V2_WRPROT (host->regs + 0x12) | |
54 | #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14) | |
55 | #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16) | |
d178e3e8 BS |
56 | #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20) |
57 | #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24) | |
58 | #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28) | |
59 | #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c) | |
60 | #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22) | |
61 | #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26) | |
62 | #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a) | |
63 | #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e) | |
1bc99180 SH |
64 | #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18) |
65 | #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a) | |
66 | #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c) | |
67 | ||
6e85dfdc | 68 | #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) |
1bc99180 SH |
69 | #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2) |
70 | #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) | |
71 | #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4) | |
72 | #define NFC_V1_V2_CONFIG1_BIG (1 << 5) | |
73 | #define NFC_V1_V2_CONFIG1_RST (1 << 6) | |
74 | #define NFC_V1_V2_CONFIG1_CE (1 << 7) | |
b8db2f51 SH |
75 | #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8) |
76 | #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9) | |
77 | #define NFC_V2_CONFIG1_FP_INT (1 << 11) | |
1bc99180 SH |
78 | |
79 | #define NFC_V1_V2_CONFIG2_INT (1 << 15) | |
80 | ||
81 | /* | |
82 | * Operation modes for the NFC. Valid for v1, v2 and v3 | |
83 | * type controllers. | |
84 | */ | |
85 | #define NFC_CMD (1 << 0) | |
86 | #define NFC_ADDR (1 << 1) | |
87 | #define NFC_INPUT (1 << 2) | |
88 | #define NFC_OUTPUT (1 << 3) | |
89 | #define NFC_ID (1 << 4) | |
90 | #define NFC_STATUS (1 << 5) | |
34f6e157 | 91 | |
71ec5155 SH |
92 | #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00) |
93 | #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04) | |
94 | ||
95 | #define NFC_V3_CONFIG1 (host->regs_axi + 0x34) | |
96 | #define NFC_V3_CONFIG1_SP_EN (1 << 0) | |
97 | #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4) | |
98 | ||
99 | #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38) | |
100 | ||
101 | #define NFC_V3_LAUNCH (host->regs_axi + 0x40) | |
102 | ||
103 | #define NFC_V3_WRPROT (host->regs_ip + 0x0) | |
104 | #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0) | |
105 | #define NFC_V3_WRPROT_LOCK (1 << 1) | |
106 | #define NFC_V3_WRPROT_UNLOCK (1 << 2) | |
107 | #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6) | |
108 | ||
109 | #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04) | |
110 | ||
111 | #define NFC_V3_CONFIG2 (host->regs_ip + 0x24) | |
112 | #define NFC_V3_CONFIG2_PS_512 (0 << 0) | |
113 | #define NFC_V3_CONFIG2_PS_2048 (1 << 0) | |
114 | #define NFC_V3_CONFIG2_PS_4096 (2 << 0) | |
115 | #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2) | |
116 | #define NFC_V3_CONFIG2_ECC_EN (1 << 3) | |
117 | #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4) | |
118 | #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5) | |
119 | #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6) | |
71718a8e | 120 | #define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift) |
71ec5155 SH |
121 | #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12) |
122 | #define NFC_V3_CONFIG2_INT_MSK (1 << 15) | |
123 | #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24) | |
124 | #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16) | |
125 | ||
126 | #define NFC_V3_CONFIG3 (host->regs_ip + 0x28) | |
127 | #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0) | |
128 | #define NFC_V3_CONFIG3_FW8 (1 << 3) | |
129 | #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8) | |
130 | #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12) | |
131 | #define NFC_V3_CONFIG3_RBB_MODE (1 << 15) | |
132 | #define NFC_V3_CONFIG3_NO_SDMA (1 << 20) | |
133 | ||
134 | #define NFC_V3_IPC (host->regs_ip + 0x2C) | |
135 | #define NFC_V3_IPC_CREQ (1 << 0) | |
136 | #define NFC_V3_IPC_INT (1 << 31) | |
137 | ||
138 | #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34) | |
34f6e157 | 139 | |
e4303b25 UKK |
140 | struct mxc_nand_host; |
141 | ||
142 | struct mxc_nand_devtype_data { | |
143 | void (*preset)(struct mtd_info *); | |
144 | void (*send_cmd)(struct mxc_nand_host *, uint16_t, int); | |
145 | void (*send_addr)(struct mxc_nand_host *, uint16_t, int); | |
146 | void (*send_page)(struct mtd_info *, unsigned int); | |
147 | void (*send_read_id)(struct mxc_nand_host *); | |
148 | uint16_t (*get_dev_status)(struct mxc_nand_host *); | |
149 | int (*check_int)(struct mxc_nand_host *); | |
150 | void (*irq_control)(struct mxc_nand_host *, int); | |
6d38af25 | 151 | u32 (*get_ecc_status)(struct mxc_nand_host *); |
6dcdf99d | 152 | struct nand_ecclayout *ecclayout_512, *ecclayout_2k, *ecclayout_4k; |
5e05a2d6 | 153 | void (*select_chip)(struct mtd_info *mtd, int chip); |
69d023be UKK |
154 | int (*correct_data)(struct mtd_info *mtd, u_char *dat, |
155 | u_char *read_ecc, u_char *calc_ecc); | |
f48d0f9a UKK |
156 | |
157 | /* | |
158 | * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked | |
159 | * (CONFIG1:INT_MSK is set). To handle this the driver uses | |
160 | * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK | |
161 | */ | |
162 | int irqpending_quirk; | |
163 | int needs_ip; | |
164 | ||
165 | size_t regs_offset; | |
166 | size_t spare0_offset; | |
167 | size_t axi_offset; | |
168 | ||
169 | int spare_len; | |
170 | int eccbytes; | |
171 | int eccsize; | |
71718a8e | 172 | int ppb_shift; |
e4303b25 UKK |
173 | }; |
174 | ||
34f6e157 SH |
175 | struct mxc_nand_host { |
176 | struct mtd_info mtd; | |
177 | struct nand_chip nand; | |
34f6e157 SH |
178 | struct device *dev; |
179 | ||
4b6f05e1 UKK |
180 | void __iomem *spare0; |
181 | void __iomem *main_area0; | |
c6de7e1b SH |
182 | |
183 | void __iomem *base; | |
34f6e157 | 184 | void __iomem *regs; |
71ec5155 SH |
185 | void __iomem *regs_axi; |
186 | void __iomem *regs_ip; | |
34f6e157 | 187 | int status_request; |
34f6e157 SH |
188 | struct clk *clk; |
189 | int clk_act; | |
190 | int irq; | |
94f77e50 | 191 | int eccsize; |
d178e3e8 | 192 | int active_cs; |
34f6e157 | 193 | |
63f1474c | 194 | struct completion op_completion; |
34f6e157 | 195 | |
f8f9608d SH |
196 | uint8_t *data_buf; |
197 | unsigned int buf_start; | |
5f97304e | 198 | |
e4303b25 | 199 | const struct mxc_nand_devtype_data *devtype_data; |
6436356b | 200 | struct mxc_nand_platform_data pdata; |
34f6e157 SH |
201 | }; |
202 | ||
34f6e157 | 203 | /* OOB placement block for use with hardware ecc generation */ |
9467114e | 204 | static struct nand_ecclayout nandv1_hw_eccoob_smallpage = { |
34f6e157 SH |
205 | .eccbytes = 5, |
206 | .eccpos = {6, 7, 8, 9, 10}, | |
8c1fd89a | 207 | .oobfree = {{0, 5}, {12, 4}, } |
bd3fd62e VB |
208 | }; |
209 | ||
9467114e | 210 | static struct nand_ecclayout nandv1_hw_eccoob_largepage = { |
bd3fd62e VB |
211 | .eccbytes = 20, |
212 | .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26, | |
213 | 38, 39, 40, 41, 42, 54, 55, 56, 57, 58}, | |
214 | .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, } | |
34f6e157 SH |
215 | }; |
216 | ||
9467114e SH |
217 | /* OOB description for 512 byte pages with 16 byte OOB */ |
218 | static struct nand_ecclayout nandv2_hw_eccoob_smallpage = { | |
219 | .eccbytes = 1 * 9, | |
220 | .eccpos = { | |
221 | 7, 8, 9, 10, 11, 12, 13, 14, 15 | |
222 | }, | |
223 | .oobfree = { | |
224 | {.offset = 0, .length = 5} | |
225 | } | |
226 | }; | |
227 | ||
228 | /* OOB description for 2048 byte pages with 64 byte OOB */ | |
229 | static struct nand_ecclayout nandv2_hw_eccoob_largepage = { | |
230 | .eccbytes = 4 * 9, | |
231 | .eccpos = { | |
232 | 7, 8, 9, 10, 11, 12, 13, 14, 15, | |
233 | 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
234 | 39, 40, 41, 42, 43, 44, 45, 46, 47, | |
235 | 55, 56, 57, 58, 59, 60, 61, 62, 63 | |
236 | }, | |
237 | .oobfree = { | |
238 | {.offset = 2, .length = 4}, | |
239 | {.offset = 16, .length = 7}, | |
240 | {.offset = 32, .length = 7}, | |
241 | {.offset = 48, .length = 7} | |
242 | } | |
243 | }; | |
244 | ||
2c1c5f19 BS |
245 | /* OOB description for 4096 byte pages with 128 byte OOB */ |
246 | static struct nand_ecclayout nandv2_hw_eccoob_4k = { | |
247 | .eccbytes = 8 * 9, | |
248 | .eccpos = { | |
249 | 7, 8, 9, 10, 11, 12, 13, 14, 15, | |
250 | 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
251 | 39, 40, 41, 42, 43, 44, 45, 46, 47, | |
252 | 55, 56, 57, 58, 59, 60, 61, 62, 63, | |
253 | 71, 72, 73, 74, 75, 76, 77, 78, 79, | |
254 | 87, 88, 89, 90, 91, 92, 93, 94, 95, | |
255 | 103, 104, 105, 106, 107, 108, 109, 110, 111, | |
256 | 119, 120, 121, 122, 123, 124, 125, 126, 127, | |
257 | }, | |
258 | .oobfree = { | |
259 | {.offset = 2, .length = 4}, | |
260 | {.offset = 16, .length = 7}, | |
261 | {.offset = 32, .length = 7}, | |
262 | {.offset = 48, .length = 7}, | |
263 | {.offset = 64, .length = 7}, | |
264 | {.offset = 80, .length = 7}, | |
265 | {.offset = 96, .length = 7}, | |
266 | {.offset = 112, .length = 7}, | |
267 | } | |
268 | }; | |
269 | ||
b2ac0376 | 270 | static const char * const part_probes[] = { |
740bb0c4 | 271 | "cmdlinepart", "RedBoot", "ofpart", NULL }; |
34f6e157 | 272 | |
096bcc23 SH |
273 | static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size) |
274 | { | |
275 | int i; | |
276 | u32 *t = trg; | |
277 | const __iomem u32 *s = src; | |
278 | ||
279 | for (i = 0; i < (size >> 2); i++) | |
280 | *t++ = __raw_readl(s++); | |
281 | } | |
282 | ||
283 | static void memcpy32_toio(void __iomem *trg, const void *src, int size) | |
284 | { | |
285 | int i; | |
286 | u32 __iomem *t = trg; | |
287 | const u32 *s = src; | |
288 | ||
289 | for (i = 0; i < (size >> 2); i++) | |
290 | __raw_writel(*s++, t++); | |
291 | } | |
292 | ||
71ec5155 SH |
293 | static int check_int_v3(struct mxc_nand_host *host) |
294 | { | |
295 | uint32_t tmp; | |
296 | ||
297 | tmp = readl(NFC_V3_IPC); | |
298 | if (!(tmp & NFC_V3_IPC_INT)) | |
299 | return 0; | |
300 | ||
301 | tmp &= ~NFC_V3_IPC_INT; | |
302 | writel(tmp, NFC_V3_IPC); | |
303 | ||
304 | return 1; | |
305 | } | |
306 | ||
7aaf28ac SH |
307 | static int check_int_v1_v2(struct mxc_nand_host *host) |
308 | { | |
309 | uint32_t tmp; | |
310 | ||
1bc99180 SH |
311 | tmp = readw(NFC_V1_V2_CONFIG2); |
312 | if (!(tmp & NFC_V1_V2_CONFIG2_INT)) | |
7aaf28ac SH |
313 | return 0; |
314 | ||
f48d0f9a | 315 | if (!host->devtype_data->irqpending_quirk) |
63f1474c | 316 | writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2); |
7aaf28ac SH |
317 | |
318 | return 1; | |
319 | } | |
320 | ||
63f1474c SH |
321 | static void irq_control_v1_v2(struct mxc_nand_host *host, int activate) |
322 | { | |
323 | uint16_t tmp; | |
324 | ||
325 | tmp = readw(NFC_V1_V2_CONFIG1); | |
326 | ||
327 | if (activate) | |
328 | tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK; | |
329 | else | |
330 | tmp |= NFC_V1_V2_CONFIG1_INT_MSK; | |
331 | ||
332 | writew(tmp, NFC_V1_V2_CONFIG1); | |
333 | } | |
334 | ||
335 | static void irq_control_v3(struct mxc_nand_host *host, int activate) | |
336 | { | |
337 | uint32_t tmp; | |
338 | ||
339 | tmp = readl(NFC_V3_CONFIG2); | |
340 | ||
341 | if (activate) | |
342 | tmp &= ~NFC_V3_CONFIG2_INT_MSK; | |
343 | else | |
344 | tmp |= NFC_V3_CONFIG2_INT_MSK; | |
345 | ||
346 | writel(tmp, NFC_V3_CONFIG2); | |
347 | } | |
348 | ||
8556958a UKK |
349 | static void irq_control(struct mxc_nand_host *host, int activate) |
350 | { | |
f48d0f9a | 351 | if (host->devtype_data->irqpending_quirk) { |
8556958a UKK |
352 | if (activate) |
353 | enable_irq(host->irq); | |
354 | else | |
355 | disable_irq_nosync(host->irq); | |
356 | } else { | |
e4303b25 | 357 | host->devtype_data->irq_control(host, activate); |
8556958a UKK |
358 | } |
359 | } | |
360 | ||
6d38af25 UKK |
361 | static u32 get_ecc_status_v1(struct mxc_nand_host *host) |
362 | { | |
363 | return readw(NFC_V1_V2_ECC_STATUS_RESULT); | |
364 | } | |
365 | ||
366 | static u32 get_ecc_status_v2(struct mxc_nand_host *host) | |
367 | { | |
368 | return readl(NFC_V1_V2_ECC_STATUS_RESULT); | |
369 | } | |
370 | ||
371 | static u32 get_ecc_status_v3(struct mxc_nand_host *host) | |
372 | { | |
373 | return readl(NFC_V3_ECC_STATUS_RESULT); | |
374 | } | |
375 | ||
8556958a UKK |
376 | static irqreturn_t mxc_nfc_irq(int irq, void *dev_id) |
377 | { | |
378 | struct mxc_nand_host *host = dev_id; | |
379 | ||
e4303b25 | 380 | if (!host->devtype_data->check_int(host)) |
8556958a UKK |
381 | return IRQ_NONE; |
382 | ||
383 | irq_control(host, 0); | |
384 | ||
385 | complete(&host->op_completion); | |
386 | ||
387 | return IRQ_HANDLED; | |
388 | } | |
389 | ||
34f6e157 SH |
390 | /* This function polls the NANDFC to wait for the basic operation to |
391 | * complete by checking the INT bit of config2 register. | |
392 | */ | |
c110eaf4 | 393 | static void wait_op_done(struct mxc_nand_host *host, int useirq) |
34f6e157 | 394 | { |
a47bfd2e | 395 | int max_retries = 8000; |
34f6e157 SH |
396 | |
397 | if (useirq) { | |
e4303b25 | 398 | if (!host->devtype_data->check_int(host)) { |
16735d02 | 399 | reinit_completion(&host->op_completion); |
8556958a | 400 | irq_control(host, 1); |
63f1474c | 401 | wait_for_completion(&host->op_completion); |
34f6e157 SH |
402 | } |
403 | } else { | |
404 | while (max_retries-- > 0) { | |
e4303b25 | 405 | if (host->devtype_data->check_int(host)) |
34f6e157 | 406 | break; |
7aaf28ac | 407 | |
34f6e157 SH |
408 | udelay(1); |
409 | } | |
43950a60 | 410 | if (max_retries < 0) |
0a32a102 | 411 | pr_debug("%s: INT not set\n", __func__); |
34f6e157 SH |
412 | } |
413 | } | |
414 | ||
71ec5155 SH |
415 | static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq) |
416 | { | |
417 | /* fill command */ | |
418 | writel(cmd, NFC_V3_FLASH_CMD); | |
419 | ||
420 | /* send out command */ | |
421 | writel(NFC_CMD, NFC_V3_LAUNCH); | |
422 | ||
423 | /* Wait for operation to complete */ | |
424 | wait_op_done(host, useirq); | |
425 | } | |
426 | ||
34f6e157 SH |
427 | /* This function issues the specified command to the NAND device and |
428 | * waits for completion. */ | |
5f97304e | 429 | static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq) |
34f6e157 | 430 | { |
289c0522 | 431 | pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq); |
34f6e157 | 432 | |
1bc99180 SH |
433 | writew(cmd, NFC_V1_V2_FLASH_CMD); |
434 | writew(NFC_CMD, NFC_V1_V2_CONFIG2); | |
34f6e157 | 435 | |
f48d0f9a | 436 | if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) { |
a47bfd2e IC |
437 | int max_retries = 100; |
438 | /* Reset completion is indicated by NFC_CONFIG2 */ | |
439 | /* being set to 0 */ | |
440 | while (max_retries-- > 0) { | |
1bc99180 | 441 | if (readw(NFC_V1_V2_CONFIG2) == 0) { |
a47bfd2e IC |
442 | break; |
443 | } | |
444 | udelay(1); | |
445 | } | |
446 | if (max_retries < 0) | |
0a32a102 | 447 | pr_debug("%s: RESET failed\n", __func__); |
a47bfd2e IC |
448 | } else { |
449 | /* Wait for operation to complete */ | |
450 | wait_op_done(host, useirq); | |
451 | } | |
34f6e157 SH |
452 | } |
453 | ||
71ec5155 SH |
454 | static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast) |
455 | { | |
456 | /* fill address */ | |
457 | writel(addr, NFC_V3_FLASH_ADDR0); | |
458 | ||
459 | /* send out address */ | |
460 | writel(NFC_ADDR, NFC_V3_LAUNCH); | |
461 | ||
462 | wait_op_done(host, 0); | |
463 | } | |
464 | ||
34f6e157 SH |
465 | /* This function sends an address (or partial address) to the |
466 | * NAND device. The address is used to select the source/destination for | |
467 | * a NAND command. */ | |
5f97304e | 468 | static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast) |
34f6e157 | 469 | { |
289c0522 | 470 | pr_debug("send_addr(host, 0x%x %d)\n", addr, islast); |
34f6e157 | 471 | |
1bc99180 SH |
472 | writew(addr, NFC_V1_V2_FLASH_ADDR); |
473 | writew(NFC_ADDR, NFC_V1_V2_CONFIG2); | |
34f6e157 SH |
474 | |
475 | /* Wait for operation to complete */ | |
c110eaf4 | 476 | wait_op_done(host, islast); |
34f6e157 SH |
477 | } |
478 | ||
71ec5155 SH |
479 | static void send_page_v3(struct mtd_info *mtd, unsigned int ops) |
480 | { | |
481 | struct nand_chip *nand_chip = mtd->priv; | |
482 | struct mxc_nand_host *host = nand_chip->priv; | |
483 | uint32_t tmp; | |
484 | ||
485 | tmp = readl(NFC_V3_CONFIG1); | |
486 | tmp &= ~(7 << 4); | |
487 | writel(tmp, NFC_V3_CONFIG1); | |
488 | ||
489 | /* transfer data from NFC ram to nand */ | |
490 | writel(ops, NFC_V3_LAUNCH); | |
491 | ||
492 | wait_op_done(host, false); | |
493 | } | |
494 | ||
6d38af25 UKK |
495 | static void send_page_v2(struct mtd_info *mtd, unsigned int ops) |
496 | { | |
497 | struct nand_chip *nand_chip = mtd->priv; | |
498 | struct mxc_nand_host *host = nand_chip->priv; | |
499 | ||
500 | /* NANDFC buffer 0 is used for page read/write */ | |
501 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); | |
502 | ||
503 | writew(ops, NFC_V1_V2_CONFIG2); | |
504 | ||
505 | /* Wait for operation to complete */ | |
506 | wait_op_done(host, true); | |
507 | } | |
508 | ||
509 | static void send_page_v1(struct mtd_info *mtd, unsigned int ops) | |
34f6e157 | 510 | { |
2d69c7fa SH |
511 | struct nand_chip *nand_chip = mtd->priv; |
512 | struct mxc_nand_host *host = nand_chip->priv; | |
c5d23f1b | 513 | int bufs, i; |
34f6e157 | 514 | |
6d38af25 | 515 | if (mtd->writesize > 512) |
c5d23f1b SH |
516 | bufs = 4; |
517 | else | |
518 | bufs = 1; | |
34f6e157 | 519 | |
c5d23f1b | 520 | for (i = 0; i < bufs; i++) { |
34f6e157 | 521 | |
c5d23f1b | 522 | /* NANDFC buffer 0 is used for page read/write */ |
d178e3e8 | 523 | writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR); |
34f6e157 | 524 | |
1bc99180 | 525 | writew(ops, NFC_V1_V2_CONFIG2); |
34f6e157 | 526 | |
c5d23f1b | 527 | /* Wait for operation to complete */ |
c110eaf4 | 528 | wait_op_done(host, true); |
34f6e157 | 529 | } |
34f6e157 SH |
530 | } |
531 | ||
71ec5155 SH |
532 | static void send_read_id_v3(struct mxc_nand_host *host) |
533 | { | |
a8459f21 RS |
534 | struct nand_chip *this = &host->nand; |
535 | ||
71ec5155 SH |
536 | /* Read ID into main buffer */ |
537 | writel(NFC_ID, NFC_V3_LAUNCH); | |
538 | ||
539 | wait_op_done(host, true); | |
540 | ||
096bcc23 | 541 | memcpy32_fromio(host->data_buf, host->main_area0, 16); |
a8459f21 RS |
542 | |
543 | if (this->options & NAND_BUSWIDTH_16) { | |
544 | /* compress the ID info */ | |
545 | host->data_buf[1] = host->data_buf[2]; | |
546 | host->data_buf[2] = host->data_buf[4]; | |
547 | host->data_buf[3] = host->data_buf[6]; | |
548 | host->data_buf[4] = host->data_buf[8]; | |
549 | host->data_buf[5] = host->data_buf[10]; | |
550 | } | |
71ec5155 SH |
551 | } |
552 | ||
34f6e157 | 553 | /* Request the NANDFC to perform a read of the NAND device ID. */ |
5f97304e | 554 | static void send_read_id_v1_v2(struct mxc_nand_host *host) |
34f6e157 SH |
555 | { |
556 | struct nand_chip *this = &host->nand; | |
34f6e157 SH |
557 | |
558 | /* NANDFC buffer 0 is used for device ID output */ | |
d178e3e8 | 559 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); |
34f6e157 | 560 | |
1bc99180 | 561 | writew(NFC_ID, NFC_V1_V2_CONFIG2); |
34f6e157 SH |
562 | |
563 | /* Wait for operation to complete */ | |
c110eaf4 | 564 | wait_op_done(host, true); |
34f6e157 | 565 | |
096bcc23 | 566 | memcpy32_fromio(host->data_buf, host->main_area0, 16); |
f7b66e5e | 567 | |
34f6e157 | 568 | if (this->options & NAND_BUSWIDTH_16) { |
34f6e157 | 569 | /* compress the ID info */ |
f7b66e5e JO |
570 | host->data_buf[1] = host->data_buf[2]; |
571 | host->data_buf[2] = host->data_buf[4]; | |
572 | host->data_buf[3] = host->data_buf[6]; | |
573 | host->data_buf[4] = host->data_buf[8]; | |
574 | host->data_buf[5] = host->data_buf[10]; | |
34f6e157 SH |
575 | } |
576 | } | |
577 | ||
71ec5155 SH |
578 | static uint16_t get_dev_status_v3(struct mxc_nand_host *host) |
579 | { | |
580 | writew(NFC_STATUS, NFC_V3_LAUNCH); | |
581 | wait_op_done(host, true); | |
582 | ||
583 | return readl(NFC_V3_CONFIG1) >> 16; | |
584 | } | |
585 | ||
34f6e157 SH |
586 | /* This function requests the NANDFC to perform a read of the |
587 | * NAND device status and returns the current status. */ | |
5f97304e | 588 | static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host) |
34f6e157 | 589 | { |
c29c607a | 590 | void __iomem *main_buf = host->main_area0; |
34f6e157 | 591 | uint32_t store; |
f06368f7 | 592 | uint16_t ret; |
34f6e157 | 593 | |
d178e3e8 | 594 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); |
34f6e157 | 595 | |
c29c607a SH |
596 | /* |
597 | * The device status is stored in main_area0. To | |
598 | * prevent corruption of the buffer save the value | |
599 | * and restore it afterwards. | |
600 | */ | |
34f6e157 | 601 | store = readl(main_buf); |
34f6e157 | 602 | |
1bc99180 | 603 | writew(NFC_STATUS, NFC_V1_V2_CONFIG2); |
c110eaf4 | 604 | wait_op_done(host, true); |
34f6e157 | 605 | |
34f6e157 | 606 | ret = readw(main_buf); |
c29c607a | 607 | |
34f6e157 SH |
608 | writel(store, main_buf); |
609 | ||
610 | return ret; | |
611 | } | |
612 | ||
613 | /* This functions is used by upper layer to checks if device is ready */ | |
614 | static int mxc_nand_dev_ready(struct mtd_info *mtd) | |
615 | { | |
616 | /* | |
617 | * NFC handles R/B internally. Therefore, this function | |
618 | * always returns status as ready. | |
619 | */ | |
620 | return 1; | |
621 | } | |
622 | ||
623 | static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode) | |
624 | { | |
625 | /* | |
626 | * If HW ECC is enabled, we turn it on during init. There is | |
627 | * no need to enable again here. | |
628 | */ | |
629 | } | |
630 | ||
94f77e50 | 631 | static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat, |
34f6e157 SH |
632 | u_char *read_ecc, u_char *calc_ecc) |
633 | { | |
634 | struct nand_chip *nand_chip = mtd->priv; | |
635 | struct mxc_nand_host *host = nand_chip->priv; | |
636 | ||
637 | /* | |
638 | * 1-Bit errors are automatically corrected in HW. No need for | |
639 | * additional correction. 2-Bit errors cannot be corrected by | |
640 | * HW ECC, so we need to return failure | |
641 | */ | |
6d38af25 | 642 | uint16_t ecc_status = get_ecc_status_v1(host); |
34f6e157 SH |
643 | |
644 | if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) { | |
289c0522 | 645 | pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n"); |
34f6e157 SH |
646 | return -1; |
647 | } | |
648 | ||
649 | return 0; | |
650 | } | |
651 | ||
94f77e50 SH |
652 | static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat, |
653 | u_char *read_ecc, u_char *calc_ecc) | |
654 | { | |
655 | struct nand_chip *nand_chip = mtd->priv; | |
656 | struct mxc_nand_host *host = nand_chip->priv; | |
657 | u32 ecc_stat, err; | |
658 | int no_subpages = 1; | |
659 | int ret = 0; | |
660 | u8 ecc_bit_mask, err_limit; | |
661 | ||
662 | ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf; | |
663 | err_limit = (host->eccsize == 4) ? 0x4 : 0x8; | |
664 | ||
665 | no_subpages = mtd->writesize >> 9; | |
666 | ||
6d38af25 | 667 | ecc_stat = host->devtype_data->get_ecc_status(host); |
94f77e50 SH |
668 | |
669 | do { | |
670 | err = ecc_stat & ecc_bit_mask; | |
671 | if (err > err_limit) { | |
672 | printk(KERN_WARNING "UnCorrectable RS-ECC Error\n"); | |
673 | return -1; | |
674 | } else { | |
675 | ret += err; | |
676 | } | |
677 | ecc_stat >>= 4; | |
678 | } while (--no_subpages); | |
679 | ||
680 | mtd->ecc_stats.corrected += ret; | |
681 | pr_debug("%d Symbol Correctable RS-ECC Error\n", ret); | |
682 | ||
683 | return ret; | |
684 | } | |
685 | ||
34f6e157 SH |
686 | static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
687 | u_char *ecc_code) | |
688 | { | |
689 | return 0; | |
690 | } | |
691 | ||
692 | static u_char mxc_nand_read_byte(struct mtd_info *mtd) | |
693 | { | |
694 | struct nand_chip *nand_chip = mtd->priv; | |
695 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d | 696 | uint8_t ret; |
34f6e157 SH |
697 | |
698 | /* Check for status request */ | |
699 | if (host->status_request) | |
e4303b25 | 700 | return host->devtype_data->get_dev_status(host) & 0xFF; |
34f6e157 | 701 | |
f8f9608d SH |
702 | ret = *(uint8_t *)(host->data_buf + host->buf_start); |
703 | host->buf_start++; | |
34f6e157 SH |
704 | |
705 | return ret; | |
706 | } | |
707 | ||
708 | static uint16_t mxc_nand_read_word(struct mtd_info *mtd) | |
709 | { | |
710 | struct nand_chip *nand_chip = mtd->priv; | |
711 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d | 712 | uint16_t ret; |
34f6e157 | 713 | |
f8f9608d SH |
714 | ret = *(uint16_t *)(host->data_buf + host->buf_start); |
715 | host->buf_start += 2; | |
34f6e157 SH |
716 | |
717 | return ret; | |
718 | } | |
719 | ||
720 | /* Write data of length len to buffer buf. The data to be | |
721 | * written on NAND Flash is first copied to RAMbuffer. After the Data Input | |
722 | * Operation by the NFC, the data is written to NAND Flash */ | |
723 | static void mxc_nand_write_buf(struct mtd_info *mtd, | |
724 | const u_char *buf, int len) | |
725 | { | |
726 | struct nand_chip *nand_chip = mtd->priv; | |
727 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d SH |
728 | u16 col = host->buf_start; |
729 | int n = mtd->oobsize + mtd->writesize - col; | |
34f6e157 | 730 | |
f8f9608d | 731 | n = min(n, len); |
34f6e157 | 732 | |
f8f9608d | 733 | memcpy(host->data_buf + col, buf, n); |
34f6e157 | 734 | |
f8f9608d | 735 | host->buf_start += n; |
34f6e157 SH |
736 | } |
737 | ||
738 | /* Read the data buffer from the NAND Flash. To read the data from NAND | |
739 | * Flash first the data output cycle is initiated by the NFC, which copies | |
740 | * the data to RAMbuffer. This data of length len is then copied to buffer buf. | |
741 | */ | |
742 | static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
743 | { | |
744 | struct nand_chip *nand_chip = mtd->priv; | |
745 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d SH |
746 | u16 col = host->buf_start; |
747 | int n = mtd->oobsize + mtd->writesize - col; | |
34f6e157 | 748 | |
f8f9608d | 749 | n = min(n, len); |
34f6e157 | 750 | |
5d9d9936 | 751 | memcpy(buf, host->data_buf + col, n); |
34f6e157 | 752 | |
5d9d9936 | 753 | host->buf_start += n; |
34f6e157 SH |
754 | } |
755 | ||
34f6e157 SH |
756 | /* This function is used by upper layer for select and |
757 | * deselect of the NAND chip */ | |
5e05a2d6 | 758 | static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip) |
34f6e157 SH |
759 | { |
760 | struct nand_chip *nand_chip = mtd->priv; | |
761 | struct mxc_nand_host *host = nand_chip->priv; | |
762 | ||
d178e3e8 | 763 | if (chip == -1) { |
34f6e157 SH |
764 | /* Disable the NFC clock */ |
765 | if (host->clk_act) { | |
97c3213f | 766 | clk_disable_unprepare(host->clk); |
34f6e157 SH |
767 | host->clk_act = 0; |
768 | } | |
d178e3e8 BS |
769 | return; |
770 | } | |
771 | ||
772 | if (!host->clk_act) { | |
34f6e157 | 773 | /* Enable the NFC clock */ |
97c3213f | 774 | clk_prepare_enable(host->clk); |
d178e3e8 BS |
775 | host->clk_act = 1; |
776 | } | |
5e05a2d6 | 777 | } |
34f6e157 | 778 | |
5e05a2d6 UKK |
779 | static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip) |
780 | { | |
781 | struct nand_chip *nand_chip = mtd->priv; | |
782 | struct mxc_nand_host *host = nand_chip->priv; | |
783 | ||
784 | if (chip == -1) { | |
785 | /* Disable the NFC clock */ | |
786 | if (host->clk_act) { | |
3d059693 | 787 | clk_disable_unprepare(host->clk); |
5e05a2d6 UKK |
788 | host->clk_act = 0; |
789 | } | |
790 | return; | |
791 | } | |
34f6e157 | 792 | |
5e05a2d6 UKK |
793 | if (!host->clk_act) { |
794 | /* Enable the NFC clock */ | |
3d059693 | 795 | clk_prepare_enable(host->clk); |
5e05a2d6 | 796 | host->clk_act = 1; |
34f6e157 | 797 | } |
5e05a2d6 UKK |
798 | |
799 | host->active_cs = chip; | |
800 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); | |
34f6e157 SH |
801 | } |
802 | ||
f8f9608d SH |
803 | /* |
804 | * Function to transfer data to/from spare area. | |
805 | */ | |
806 | static void copy_spare(struct mtd_info *mtd, bool bfrom) | |
34f6e157 | 807 | { |
f8f9608d SH |
808 | struct nand_chip *this = mtd->priv; |
809 | struct mxc_nand_host *host = this->priv; | |
810 | u16 i, j; | |
811 | u16 n = mtd->writesize >> 9; | |
812 | u8 *d = host->data_buf + mtd->writesize; | |
4b6f05e1 | 813 | u8 __iomem *s = host->spare0; |
f48d0f9a | 814 | u16 t = host->devtype_data->spare_len; |
f8f9608d SH |
815 | |
816 | j = (mtd->oobsize / n >> 1) << 1; | |
817 | ||
818 | if (bfrom) { | |
819 | for (i = 0; i < n - 1; i++) | |
096bcc23 | 820 | memcpy32_fromio(d + i * j, s + i * t, j); |
f8f9608d SH |
821 | |
822 | /* the last section */ | |
096bcc23 | 823 | memcpy32_fromio(d + i * j, s + i * t, mtd->oobsize - i * j); |
f8f9608d SH |
824 | } else { |
825 | for (i = 0; i < n - 1; i++) | |
096bcc23 | 826 | memcpy32_toio(&s[i * t], &d[i * j], j); |
34f6e157 | 827 | |
f8f9608d | 828 | /* the last section */ |
096bcc23 | 829 | memcpy32_toio(&s[i * t], &d[i * j], mtd->oobsize - i * j); |
34f6e157 | 830 | } |
f8f9608d | 831 | } |
34f6e157 | 832 | |
a3e65b64 SH |
833 | static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr) |
834 | { | |
835 | struct nand_chip *nand_chip = mtd->priv; | |
836 | struct mxc_nand_host *host = nand_chip->priv; | |
34f6e157 SH |
837 | |
838 | /* Write out column address, if necessary */ | |
839 | if (column != -1) { | |
840 | /* | |
841 | * MXC NANDFC can only perform full page+spare or | |
842 | * spare-only read/write. When the upper layers | |
177b241d GE |
843 | * perform a read/write buf operation, the saved column |
844 | * address is used to index into the full page. | |
34f6e157 | 845 | */ |
e4303b25 | 846 | host->devtype_data->send_addr(host, 0, page_addr == -1); |
2d69c7fa | 847 | if (mtd->writesize > 512) |
34f6e157 | 848 | /* another col addr cycle for 2k page */ |
e4303b25 | 849 | host->devtype_data->send_addr(host, 0, false); |
34f6e157 SH |
850 | } |
851 | ||
852 | /* Write out page address, if necessary */ | |
853 | if (page_addr != -1) { | |
854 | /* paddr_0 - p_addr_7 */ | |
e4303b25 | 855 | host->devtype_data->send_addr(host, (page_addr & 0xff), false); |
34f6e157 | 856 | |
2d69c7fa | 857 | if (mtd->writesize > 512) { |
bd3fd62e VB |
858 | if (mtd->size >= 0x10000000) { |
859 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
860 | host->devtype_data->send_addr(host, |
861 | (page_addr >> 8) & 0xff, | |
862 | false); | |
863 | host->devtype_data->send_addr(host, | |
864 | (page_addr >> 16) & 0xff, | |
865 | true); | |
bd3fd62e VB |
866 | } else |
867 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
868 | host->devtype_data->send_addr(host, |
869 | (page_addr >> 8) & 0xff, true); | |
34f6e157 SH |
870 | } else { |
871 | /* One more address cycle for higher density devices */ | |
872 | if (mtd->size >= 0x4000000) { | |
873 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
874 | host->devtype_data->send_addr(host, |
875 | (page_addr >> 8) & 0xff, | |
876 | false); | |
877 | host->devtype_data->send_addr(host, | |
878 | (page_addr >> 16) & 0xff, | |
879 | true); | |
34f6e157 SH |
880 | } else |
881 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
882 | host->devtype_data->send_addr(host, |
883 | (page_addr >> 8) & 0xff, true); | |
34f6e157 SH |
884 | } |
885 | } | |
a3e65b64 SH |
886 | } |
887 | ||
6e85dfdc SH |
888 | /* |
889 | * v2 and v3 type controllers can do 4bit or 8bit ecc depending | |
890 | * on how much oob the nand chip has. For 8bit ecc we need at least | |
891 | * 26 bytes of oob data per 512 byte block. | |
892 | */ | |
893 | static int get_eccsize(struct mtd_info *mtd) | |
894 | { | |
895 | int oobbytes_per_512 = 0; | |
896 | ||
897 | oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize; | |
898 | ||
899 | if (oobbytes_per_512 < 26) | |
900 | return 4; | |
901 | else | |
902 | return 8; | |
903 | } | |
904 | ||
6d38af25 | 905 | static void preset_v1(struct mtd_info *mtd) |
d4840180 IC |
906 | { |
907 | struct nand_chip *nand_chip = mtd->priv; | |
908 | struct mxc_nand_host *host = nand_chip->priv; | |
b8db2f51 SH |
909 | uint16_t config1 = 0; |
910 | ||
911 | if (nand_chip->ecc.mode == NAND_ECC_HW) | |
912 | config1 |= NFC_V1_V2_CONFIG1_ECC_EN; | |
913 | ||
f48d0f9a | 914 | if (!host->devtype_data->irqpending_quirk) |
6d38af25 UKK |
915 | config1 |= NFC_V1_V2_CONFIG1_INT_MSK; |
916 | ||
917 | host->eccsize = 1; | |
918 | ||
919 | writew(config1, NFC_V1_V2_CONFIG1); | |
920 | /* preset operation */ | |
921 | ||
922 | /* Unlock the internal RAM Buffer */ | |
923 | writew(0x2, NFC_V1_V2_CONFIG); | |
924 | ||
925 | /* Blocks to be unlocked */ | |
926 | writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR); | |
927 | writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR); | |
928 | ||
929 | /* Unlock Block Command for given address range */ | |
930 | writew(0x4, NFC_V1_V2_WRPROT); | |
931 | } | |
932 | ||
933 | static void preset_v2(struct mtd_info *mtd) | |
d4840180 IC |
934 | { |
935 | struct nand_chip *nand_chip = mtd->priv; | |
936 | struct mxc_nand_host *host = nand_chip->priv; | |
b8db2f51 SH |
937 | uint16_t config1 = 0; |
938 | ||
939 | if (nand_chip->ecc.mode == NAND_ECC_HW) | |
940 | config1 |= NFC_V1_V2_CONFIG1_ECC_EN; | |
941 | ||
6d38af25 | 942 | config1 |= NFC_V2_CONFIG1_FP_INT; |
b8db2f51 | 943 | |
f48d0f9a | 944 | if (!host->devtype_data->irqpending_quirk) |
b8db2f51 | 945 | config1 |= NFC_V1_V2_CONFIG1_INT_MSK; |
6e85dfdc | 946 | |
6d38af25 | 947 | if (mtd->writesize) { |
b8db2f51 SH |
948 | uint16_t pages_per_block = mtd->erasesize / mtd->writesize; |
949 | ||
6e85dfdc SH |
950 | host->eccsize = get_eccsize(mtd); |
951 | if (host->eccsize == 4) | |
b8db2f51 SH |
952 | config1 |= NFC_V2_CONFIG1_ECC_MODE_4; |
953 | ||
954 | config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6); | |
d4840180 | 955 | } else { |
6e85dfdc | 956 | host->eccsize = 1; |
d4840180 | 957 | } |
6e85dfdc | 958 | |
b8db2f51 | 959 | writew(config1, NFC_V1_V2_CONFIG1); |
d4840180 IC |
960 | /* preset operation */ |
961 | ||
962 | /* Unlock the internal RAM Buffer */ | |
1bc99180 | 963 | writew(0x2, NFC_V1_V2_CONFIG); |
d4840180 IC |
964 | |
965 | /* Blocks to be unlocked */ | |
6d38af25 UKK |
966 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0); |
967 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1); | |
968 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2); | |
969 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3); | |
970 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0); | |
971 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1); | |
972 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2); | |
973 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3); | |
d4840180 IC |
974 | |
975 | /* Unlock Block Command for given address range */ | |
1bc99180 | 976 | writew(0x4, NFC_V1_V2_WRPROT); |
d4840180 IC |
977 | } |
978 | ||
71ec5155 SH |
979 | static void preset_v3(struct mtd_info *mtd) |
980 | { | |
981 | struct nand_chip *chip = mtd->priv; | |
982 | struct mxc_nand_host *host = chip->priv; | |
983 | uint32_t config2, config3; | |
984 | int i, addr_phases; | |
985 | ||
986 | writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1); | |
987 | writel(NFC_V3_IPC_CREQ, NFC_V3_IPC); | |
988 | ||
989 | /* Unlock the internal RAM Buffer */ | |
990 | writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK, | |
991 | NFC_V3_WRPROT); | |
992 | ||
993 | /* Blocks to be unlocked */ | |
994 | for (i = 0; i < NAND_MAX_CHIPS; i++) | |
995 | writel(0x0 | (0xffff << 16), | |
996 | NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2)); | |
997 | ||
998 | writel(0, NFC_V3_IPC); | |
999 | ||
1000 | config2 = NFC_V3_CONFIG2_ONE_CYCLE | | |
1001 | NFC_V3_CONFIG2_2CMD_PHASES | | |
1002 | NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) | | |
1003 | NFC_V3_CONFIG2_ST_CMD(0x70) | | |
63f1474c | 1004 | NFC_V3_CONFIG2_INT_MSK | |
71ec5155 SH |
1005 | NFC_V3_CONFIG2_NUM_ADDR_PHASE0; |
1006 | ||
1007 | if (chip->ecc.mode == NAND_ECC_HW) | |
1008 | config2 |= NFC_V3_CONFIG2_ECC_EN; | |
1009 | ||
1010 | addr_phases = fls(chip->pagemask) >> 3; | |
1011 | ||
1012 | if (mtd->writesize == 2048) { | |
1013 | config2 |= NFC_V3_CONFIG2_PS_2048; | |
1014 | config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); | |
1015 | } else if (mtd->writesize == 4096) { | |
1016 | config2 |= NFC_V3_CONFIG2_PS_4096; | |
1017 | config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); | |
1018 | } else { | |
1019 | config2 |= NFC_V3_CONFIG2_PS_512; | |
1020 | config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1); | |
1021 | } | |
1022 | ||
1023 | if (mtd->writesize) { | |
71718a8e SH |
1024 | config2 |= NFC_V3_CONFIG2_PPB( |
1025 | ffs(mtd->erasesize / mtd->writesize) - 6, | |
1026 | host->devtype_data->ppb_shift); | |
71ec5155 SH |
1027 | host->eccsize = get_eccsize(mtd); |
1028 | if (host->eccsize == 8) | |
1029 | config2 |= NFC_V3_CONFIG2_ECC_MODE_8; | |
1030 | } | |
1031 | ||
1032 | writel(config2, NFC_V3_CONFIG2); | |
1033 | ||
1034 | config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) | | |
1035 | NFC_V3_CONFIG3_NO_SDMA | | |
1036 | NFC_V3_CONFIG3_RBB_MODE | | |
1037 | NFC_V3_CONFIG3_SBB(6) | /* Reset default */ | |
1038 | NFC_V3_CONFIG3_ADD_OP(0); | |
1039 | ||
1040 | if (!(chip->options & NAND_BUSWIDTH_16)) | |
1041 | config3 |= NFC_V3_CONFIG3_FW8; | |
1042 | ||
1043 | writel(config3, NFC_V3_CONFIG3); | |
1044 | ||
1045 | writel(0, NFC_V3_DELAY_LINE); | |
d4840180 IC |
1046 | } |
1047 | ||
34f6e157 SH |
1048 | /* Used by the upper layer to write command to NAND Flash for |
1049 | * different operations to be carried out on NAND Flash */ | |
1050 | static void mxc_nand_command(struct mtd_info *mtd, unsigned command, | |
1051 | int column, int page_addr) | |
1052 | { | |
1053 | struct nand_chip *nand_chip = mtd->priv; | |
1054 | struct mxc_nand_host *host = nand_chip->priv; | |
34f6e157 | 1055 | |
289c0522 | 1056 | pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n", |
34f6e157 SH |
1057 | command, column, page_addr); |
1058 | ||
1059 | /* Reset command state information */ | |
1060 | host->status_request = false; | |
34f6e157 | 1061 | |
34f6e157 | 1062 | /* Command pre-processing step */ |
34f6e157 | 1063 | switch (command) { |
d4840180 | 1064 | case NAND_CMD_RESET: |
e4303b25 UKK |
1065 | host->devtype_data->preset(mtd); |
1066 | host->devtype_data->send_cmd(host, command, false); | |
d4840180 | 1067 | break; |
34f6e157 | 1068 | |
34f6e157 | 1069 | case NAND_CMD_STATUS: |
f8f9608d | 1070 | host->buf_start = 0; |
34f6e157 | 1071 | host->status_request = true; |
34f6e157 | 1072 | |
e4303b25 | 1073 | host->devtype_data->send_cmd(host, command, true); |
89121a6b | 1074 | mxc_do_addr_cycle(mtd, column, page_addr); |
34f6e157 SH |
1075 | break; |
1076 | ||
34f6e157 | 1077 | case NAND_CMD_READ0: |
34f6e157 | 1078 | case NAND_CMD_READOOB: |
89121a6b SH |
1079 | if (command == NAND_CMD_READ0) |
1080 | host->buf_start = column; | |
1081 | else | |
1082 | host->buf_start = column + mtd->writesize; | |
f8f9608d | 1083 | |
5ea32021 | 1084 | command = NAND_CMD_READ0; /* only READ0 is valid */ |
89121a6b | 1085 | |
e4303b25 | 1086 | host->devtype_data->send_cmd(host, command, false); |
89121a6b SH |
1087 | mxc_do_addr_cycle(mtd, column, page_addr); |
1088 | ||
2d69c7fa | 1089 | if (mtd->writesize > 512) |
e4303b25 UKK |
1090 | host->devtype_data->send_cmd(host, |
1091 | NAND_CMD_READSTART, true); | |
c5d23f1b | 1092 | |
e4303b25 | 1093 | host->devtype_data->send_page(mtd, NFC_OUTPUT); |
89121a6b | 1094 | |
096bcc23 SH |
1095 | memcpy32_fromio(host->data_buf, host->main_area0, |
1096 | mtd->writesize); | |
89121a6b | 1097 | copy_spare(mtd, true); |
34f6e157 SH |
1098 | break; |
1099 | ||
34f6e157 | 1100 | case NAND_CMD_SEQIN: |
5ea32021 SH |
1101 | if (column >= mtd->writesize) |
1102 | /* call ourself to read a page */ | |
1103 | mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr); | |
34f6e157 | 1104 | |
5ea32021 | 1105 | host->buf_start = column; |
89121a6b | 1106 | |
e4303b25 | 1107 | host->devtype_data->send_cmd(host, command, false); |
89121a6b | 1108 | mxc_do_addr_cycle(mtd, column, page_addr); |
34f6e157 SH |
1109 | break; |
1110 | ||
1111 | case NAND_CMD_PAGEPROG: | |
096bcc23 | 1112 | memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize); |
f8f9608d | 1113 | copy_spare(mtd, false); |
e4303b25 UKK |
1114 | host->devtype_data->send_page(mtd, NFC_INPUT); |
1115 | host->devtype_data->send_cmd(host, command, true); | |
89121a6b | 1116 | mxc_do_addr_cycle(mtd, column, page_addr); |
34f6e157 SH |
1117 | break; |
1118 | ||
34f6e157 | 1119 | case NAND_CMD_READID: |
e4303b25 | 1120 | host->devtype_data->send_cmd(host, command, true); |
89121a6b | 1121 | mxc_do_addr_cycle(mtd, column, page_addr); |
e4303b25 | 1122 | host->devtype_data->send_read_id(host); |
9467114e | 1123 | host->buf_start = column; |
34f6e157 SH |
1124 | break; |
1125 | ||
89121a6b | 1126 | case NAND_CMD_ERASE1: |
34f6e157 | 1127 | case NAND_CMD_ERASE2: |
e4303b25 | 1128 | host->devtype_data->send_cmd(host, command, false); |
89121a6b SH |
1129 | mxc_do_addr_cycle(mtd, column, page_addr); |
1130 | ||
34f6e157 SH |
1131 | break; |
1132 | } | |
1133 | } | |
1134 | ||
f1372055 SH |
1135 | /* |
1136 | * The generic flash bbt decriptors overlap with our ecc | |
1137 | * hardware, so define some i.MX specific ones. | |
1138 | */ | |
1139 | static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' }; | |
1140 | static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' }; | |
1141 | ||
1142 | static struct nand_bbt_descr bbt_main_descr = { | |
1143 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1144 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1145 | .offs = 0, | |
1146 | .len = 4, | |
1147 | .veroffs = 4, | |
1148 | .maxblocks = 4, | |
1149 | .pattern = bbt_pattern, | |
1150 | }; | |
1151 | ||
1152 | static struct nand_bbt_descr bbt_mirror_descr = { | |
1153 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1154 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1155 | .offs = 0, | |
1156 | .len = 4, | |
1157 | .veroffs = 4, | |
1158 | .maxblocks = 4, | |
1159 | .pattern = mirror_pattern, | |
1160 | }; | |
1161 | ||
f48d0f9a | 1162 | /* v1 + irqpending_quirk: i.MX21 */ |
e4303b25 | 1163 | static const struct mxc_nand_devtype_data imx21_nand_devtype_data = { |
6d38af25 | 1164 | .preset = preset_v1, |
e4303b25 UKK |
1165 | .send_cmd = send_cmd_v1_v2, |
1166 | .send_addr = send_addr_v1_v2, | |
6d38af25 | 1167 | .send_page = send_page_v1, |
e4303b25 UKK |
1168 | .send_read_id = send_read_id_v1_v2, |
1169 | .get_dev_status = get_dev_status_v1_v2, | |
1170 | .check_int = check_int_v1_v2, | |
1171 | .irq_control = irq_control_v1_v2, | |
6d38af25 | 1172 | .get_ecc_status = get_ecc_status_v1, |
6dcdf99d UKK |
1173 | .ecclayout_512 = &nandv1_hw_eccoob_smallpage, |
1174 | .ecclayout_2k = &nandv1_hw_eccoob_largepage, | |
1175 | .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */ | |
5e05a2d6 | 1176 | .select_chip = mxc_nand_select_chip_v1_v3, |
69d023be | 1177 | .correct_data = mxc_nand_correct_data_v1, |
f48d0f9a UKK |
1178 | .irqpending_quirk = 1, |
1179 | .needs_ip = 0, | |
1180 | .regs_offset = 0xe00, | |
1181 | .spare0_offset = 0x800, | |
1182 | .spare_len = 16, | |
1183 | .eccbytes = 3, | |
1184 | .eccsize = 1, | |
1185 | }; | |
1186 | ||
1187 | /* v1 + !irqpending_quirk: i.MX27, i.MX31 */ | |
1188 | static const struct mxc_nand_devtype_data imx27_nand_devtype_data = { | |
1189 | .preset = preset_v1, | |
1190 | .send_cmd = send_cmd_v1_v2, | |
1191 | .send_addr = send_addr_v1_v2, | |
1192 | .send_page = send_page_v1, | |
1193 | .send_read_id = send_read_id_v1_v2, | |
1194 | .get_dev_status = get_dev_status_v1_v2, | |
1195 | .check_int = check_int_v1_v2, | |
1196 | .irq_control = irq_control_v1_v2, | |
1197 | .get_ecc_status = get_ecc_status_v1, | |
1198 | .ecclayout_512 = &nandv1_hw_eccoob_smallpage, | |
1199 | .ecclayout_2k = &nandv1_hw_eccoob_largepage, | |
1200 | .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */ | |
1201 | .select_chip = mxc_nand_select_chip_v1_v3, | |
1202 | .correct_data = mxc_nand_correct_data_v1, | |
1203 | .irqpending_quirk = 0, | |
1204 | .needs_ip = 0, | |
1205 | .regs_offset = 0xe00, | |
1206 | .spare0_offset = 0x800, | |
1207 | .axi_offset = 0, | |
1208 | .spare_len = 16, | |
1209 | .eccbytes = 3, | |
1210 | .eccsize = 1, | |
e4303b25 UKK |
1211 | }; |
1212 | ||
1213 | /* v21: i.MX25, i.MX35 */ | |
1214 | static const struct mxc_nand_devtype_data imx25_nand_devtype_data = { | |
6d38af25 | 1215 | .preset = preset_v2, |
e4303b25 UKK |
1216 | .send_cmd = send_cmd_v1_v2, |
1217 | .send_addr = send_addr_v1_v2, | |
6d38af25 | 1218 | .send_page = send_page_v2, |
e4303b25 UKK |
1219 | .send_read_id = send_read_id_v1_v2, |
1220 | .get_dev_status = get_dev_status_v1_v2, | |
1221 | .check_int = check_int_v1_v2, | |
1222 | .irq_control = irq_control_v1_v2, | |
6d38af25 | 1223 | .get_ecc_status = get_ecc_status_v2, |
6dcdf99d UKK |
1224 | .ecclayout_512 = &nandv2_hw_eccoob_smallpage, |
1225 | .ecclayout_2k = &nandv2_hw_eccoob_largepage, | |
1226 | .ecclayout_4k = &nandv2_hw_eccoob_4k, | |
5e05a2d6 | 1227 | .select_chip = mxc_nand_select_chip_v2, |
69d023be | 1228 | .correct_data = mxc_nand_correct_data_v2_v3, |
f48d0f9a UKK |
1229 | .irqpending_quirk = 0, |
1230 | .needs_ip = 0, | |
1231 | .regs_offset = 0x1e00, | |
1232 | .spare0_offset = 0x1000, | |
1233 | .axi_offset = 0, | |
1234 | .spare_len = 64, | |
1235 | .eccbytes = 9, | |
1236 | .eccsize = 0, | |
e4303b25 UKK |
1237 | }; |
1238 | ||
71718a8e | 1239 | /* v3.2a: i.MX51 */ |
e4303b25 UKK |
1240 | static const struct mxc_nand_devtype_data imx51_nand_devtype_data = { |
1241 | .preset = preset_v3, | |
1242 | .send_cmd = send_cmd_v3, | |
1243 | .send_addr = send_addr_v3, | |
1244 | .send_page = send_page_v3, | |
1245 | .send_read_id = send_read_id_v3, | |
1246 | .get_dev_status = get_dev_status_v3, | |
1247 | .check_int = check_int_v3, | |
1248 | .irq_control = irq_control_v3, | |
6d38af25 | 1249 | .get_ecc_status = get_ecc_status_v3, |
6dcdf99d UKK |
1250 | .ecclayout_512 = &nandv2_hw_eccoob_smallpage, |
1251 | .ecclayout_2k = &nandv2_hw_eccoob_largepage, | |
1252 | .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */ | |
5e05a2d6 | 1253 | .select_chip = mxc_nand_select_chip_v1_v3, |
69d023be | 1254 | .correct_data = mxc_nand_correct_data_v2_v3, |
f48d0f9a UKK |
1255 | .irqpending_quirk = 0, |
1256 | .needs_ip = 1, | |
1257 | .regs_offset = 0, | |
1258 | .spare0_offset = 0x1000, | |
1259 | .axi_offset = 0x1e00, | |
1260 | .spare_len = 64, | |
1261 | .eccbytes = 0, | |
1262 | .eccsize = 0, | |
71718a8e SH |
1263 | .ppb_shift = 7, |
1264 | }; | |
1265 | ||
1266 | /* v3.2b: i.MX53 */ | |
1267 | static const struct mxc_nand_devtype_data imx53_nand_devtype_data = { | |
1268 | .preset = preset_v3, | |
1269 | .send_cmd = send_cmd_v3, | |
1270 | .send_addr = send_addr_v3, | |
1271 | .send_page = send_page_v3, | |
1272 | .send_read_id = send_read_id_v3, | |
1273 | .get_dev_status = get_dev_status_v3, | |
1274 | .check_int = check_int_v3, | |
1275 | .irq_control = irq_control_v3, | |
1276 | .get_ecc_status = get_ecc_status_v3, | |
1277 | .ecclayout_512 = &nandv2_hw_eccoob_smallpage, | |
1278 | .ecclayout_2k = &nandv2_hw_eccoob_largepage, | |
1279 | .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */ | |
1280 | .select_chip = mxc_nand_select_chip_v1_v3, | |
1281 | .correct_data = mxc_nand_correct_data_v2_v3, | |
1282 | .irqpending_quirk = 0, | |
1283 | .needs_ip = 1, | |
1284 | .regs_offset = 0, | |
1285 | .spare0_offset = 0x1000, | |
1286 | .axi_offset = 0x1e00, | |
1287 | .spare_len = 64, | |
1288 | .eccbytes = 0, | |
1289 | .eccsize = 0, | |
1290 | .ppb_shift = 8, | |
e4303b25 UKK |
1291 | }; |
1292 | ||
4d62435f SG |
1293 | static inline int is_imx21_nfc(struct mxc_nand_host *host) |
1294 | { | |
1295 | return host->devtype_data == &imx21_nand_devtype_data; | |
1296 | } | |
1297 | ||
1298 | static inline int is_imx27_nfc(struct mxc_nand_host *host) | |
1299 | { | |
1300 | return host->devtype_data == &imx27_nand_devtype_data; | |
1301 | } | |
1302 | ||
1303 | static inline int is_imx25_nfc(struct mxc_nand_host *host) | |
1304 | { | |
1305 | return host->devtype_data == &imx25_nand_devtype_data; | |
1306 | } | |
1307 | ||
1308 | static inline int is_imx51_nfc(struct mxc_nand_host *host) | |
1309 | { | |
1310 | return host->devtype_data == &imx51_nand_devtype_data; | |
1311 | } | |
1312 | ||
1313 | static inline int is_imx53_nfc(struct mxc_nand_host *host) | |
1314 | { | |
1315 | return host->devtype_data == &imx53_nand_devtype_data; | |
1316 | } | |
1317 | ||
1318 | static struct platform_device_id mxcnd_devtype[] = { | |
1319 | { | |
1320 | .name = "imx21-nand", | |
1321 | .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data, | |
1322 | }, { | |
1323 | .name = "imx27-nand", | |
1324 | .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data, | |
1325 | }, { | |
1326 | .name = "imx25-nand", | |
1327 | .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data, | |
1328 | }, { | |
1329 | .name = "imx51-nand", | |
1330 | .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data, | |
1331 | }, { | |
1332 | .name = "imx53-nand", | |
1333 | .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data, | |
1334 | }, { | |
1335 | /* sentinel */ | |
1336 | } | |
1337 | }; | |
1338 | MODULE_DEVICE_TABLE(platform, mxcnd_devtype); | |
1339 | ||
6436356b UKK |
1340 | #ifdef CONFIG_OF_MTD |
1341 | static const struct of_device_id mxcnd_dt_ids[] = { | |
1342 | { | |
1343 | .compatible = "fsl,imx21-nand", | |
1344 | .data = &imx21_nand_devtype_data, | |
1345 | }, { | |
1346 | .compatible = "fsl,imx27-nand", | |
1347 | .data = &imx27_nand_devtype_data, | |
1348 | }, { | |
1349 | .compatible = "fsl,imx25-nand", | |
1350 | .data = &imx25_nand_devtype_data, | |
1351 | }, { | |
1352 | .compatible = "fsl,imx51-nand", | |
1353 | .data = &imx51_nand_devtype_data, | |
71718a8e SH |
1354 | }, { |
1355 | .compatible = "fsl,imx53-nand", | |
1356 | .data = &imx53_nand_devtype_data, | |
6436356b UKK |
1357 | }, |
1358 | { /* sentinel */ } | |
1359 | }; | |
1360 | ||
1361 | static int __init mxcnd_probe_dt(struct mxc_nand_host *host) | |
1362 | { | |
1363 | struct device_node *np = host->dev->of_node; | |
1364 | struct mxc_nand_platform_data *pdata = &host->pdata; | |
1365 | const struct of_device_id *of_id = | |
1366 | of_match_device(mxcnd_dt_ids, host->dev); | |
1367 | int buswidth; | |
1368 | ||
1369 | if (!np) | |
1370 | return 1; | |
1371 | ||
1372 | if (of_get_nand_ecc_mode(np) >= 0) | |
1373 | pdata->hw_ecc = 1; | |
1374 | ||
1375 | pdata->flash_bbt = of_get_nand_on_flash_bbt(np); | |
1376 | ||
1377 | buswidth = of_get_nand_bus_width(np); | |
1378 | if (buswidth < 0) | |
1379 | return buswidth; | |
1380 | ||
1381 | pdata->width = buswidth / 8; | |
1382 | ||
1383 | host->devtype_data = of_id->data; | |
1384 | ||
1385 | return 0; | |
1386 | } | |
1387 | #else | |
1388 | static int __init mxcnd_probe_dt(struct mxc_nand_host *host) | |
1389 | { | |
1390 | return 1; | |
1391 | } | |
1392 | #endif | |
1393 | ||
06f25510 | 1394 | static int mxcnd_probe(struct platform_device *pdev) |
34f6e157 SH |
1395 | { |
1396 | struct nand_chip *this; | |
1397 | struct mtd_info *mtd; | |
34f6e157 SH |
1398 | struct mxc_nand_host *host; |
1399 | struct resource *res; | |
d4ed8f12 | 1400 | int err = 0; |
34f6e157 SH |
1401 | |
1402 | /* Allocate memory for MTD device structure and private data */ | |
e4a09cbf SH |
1403 | host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host) + |
1404 | NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, GFP_KERNEL); | |
34f6e157 SH |
1405 | if (!host) |
1406 | return -ENOMEM; | |
1407 | ||
f8f9608d | 1408 | host->data_buf = (uint8_t *)(host + 1); |
f8f9608d | 1409 | |
34f6e157 SH |
1410 | host->dev = &pdev->dev; |
1411 | /* structures must be linked */ | |
1412 | this = &host->nand; | |
1413 | mtd = &host->mtd; | |
1414 | mtd->priv = this; | |
1415 | mtd->owner = THIS_MODULE; | |
87f39f04 | 1416 | mtd->dev.parent = &pdev->dev; |
1fbff0a6 | 1417 | mtd->name = DRIVER_NAME; |
34f6e157 SH |
1418 | |
1419 | /* 50 us command delay time */ | |
1420 | this->chip_delay = 5; | |
1421 | ||
1422 | this->priv = host; | |
1423 | this->dev_ready = mxc_nand_dev_ready; | |
1424 | this->cmdfunc = mxc_nand_command; | |
34f6e157 SH |
1425 | this->read_byte = mxc_nand_read_byte; |
1426 | this->read_word = mxc_nand_read_word; | |
1427 | this->write_buf = mxc_nand_write_buf; | |
1428 | this->read_buf = mxc_nand_read_buf; | |
34f6e157 | 1429 | |
24b82d3c | 1430 | host->clk = devm_clk_get(&pdev->dev, NULL); |
e4a09cbf SH |
1431 | if (IS_ERR(host->clk)) |
1432 | return PTR_ERR(host->clk); | |
34f6e157 | 1433 | |
71885b65 | 1434 | err = mxcnd_probe_dt(host); |
4d62435f | 1435 | if (err > 0) { |
453810b7 JH |
1436 | struct mxc_nand_platform_data *pdata = |
1437 | dev_get_platdata(&pdev->dev); | |
4d62435f SG |
1438 | if (pdata) { |
1439 | host->pdata = *pdata; | |
1440 | host->devtype_data = (struct mxc_nand_devtype_data *) | |
1441 | pdev->id_entry->driver_data; | |
1442 | } else { | |
1443 | err = -ENODEV; | |
1444 | } | |
1445 | } | |
71885b65 SH |
1446 | if (err < 0) |
1447 | return err; | |
1448 | ||
1449 | if (host->devtype_data->needs_ip) { | |
1450 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
b0de774c TR |
1451 | host->regs_ip = devm_ioremap_resource(&pdev->dev, res); |
1452 | if (IS_ERR(host->regs_ip)) | |
1453 | return PTR_ERR(host->regs_ip); | |
71885b65 SH |
1454 | |
1455 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1456 | } else { | |
1457 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1458 | } | |
1459 | ||
b0de774c TR |
1460 | host->base = devm_ioremap_resource(&pdev->dev, res); |
1461 | if (IS_ERR(host->base)) | |
1462 | return PTR_ERR(host->base); | |
34f6e157 | 1463 | |
c6de7e1b | 1464 | host->main_area0 = host->base; |
9467114e | 1465 | |
f48d0f9a UKK |
1466 | if (host->devtype_data->regs_offset) |
1467 | host->regs = host->base + host->devtype_data->regs_offset; | |
1468 | host->spare0 = host->base + host->devtype_data->spare0_offset; | |
1469 | if (host->devtype_data->axi_offset) | |
1470 | host->regs_axi = host->base + host->devtype_data->axi_offset; | |
1471 | ||
1472 | this->ecc.bytes = host->devtype_data->eccbytes; | |
1473 | host->eccsize = host->devtype_data->eccsize; | |
1474 | ||
1475 | this->select_chip = host->devtype_data->select_chip; | |
1476 | this->ecc.size = 512; | |
1477 | this->ecc.layout = host->devtype_data->ecclayout_512; | |
1478 | ||
6436356b | 1479 | if (host->pdata.hw_ecc) { |
34f6e157 SH |
1480 | this->ecc.calculate = mxc_nand_calculate_ecc; |
1481 | this->ecc.hwctl = mxc_nand_enable_hwecc; | |
69d023be | 1482 | this->ecc.correct = host->devtype_data->correct_data; |
34f6e157 | 1483 | this->ecc.mode = NAND_ECC_HW; |
34f6e157 | 1484 | } else { |
34f6e157 | 1485 | this->ecc.mode = NAND_ECC_SOFT; |
34f6e157 SH |
1486 | } |
1487 | ||
6436356b UKK |
1488 | /* NAND bus width determines access functions used by upper layer */ |
1489 | if (host->pdata.width == 2) | |
34f6e157 | 1490 | this->options |= NAND_BUSWIDTH_16; |
34f6e157 | 1491 | |
6436356b | 1492 | if (host->pdata.flash_bbt) { |
f1372055 SH |
1493 | this->bbt_td = &bbt_main_descr; |
1494 | this->bbt_md = &bbt_mirror_descr; | |
1495 | /* update flash based bbt */ | |
bb9ebd4e | 1496 | this->bbt_options |= NAND_BBT_USE_FLASH; |
34f6e157 SH |
1497 | } |
1498 | ||
63f1474c | 1499 | init_completion(&host->op_completion); |
d4840180 IC |
1500 | |
1501 | host->irq = platform_get_irq(pdev, 0); | |
1502 | ||
63f1474c | 1503 | /* |
e4303b25 UKK |
1504 | * Use host->devtype_data->irq_control() here instead of irq_control() |
1505 | * because we must not disable_irq_nosync without having requested the | |
1506 | * irq. | |
63f1474c | 1507 | */ |
e4303b25 | 1508 | host->devtype_data->irq_control(host, 0); |
63f1474c | 1509 | |
e4a09cbf | 1510 | err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq, |
b1eb234f | 1511 | 0, DRIVER_NAME, host); |
d4840180 | 1512 | if (err) |
e4a09cbf SH |
1513 | return err; |
1514 | ||
1515 | clk_prepare_enable(host->clk); | |
1516 | host->clk_act = 1; | |
d4840180 | 1517 | |
63f1474c | 1518 | /* |
8556958a UKK |
1519 | * Now that we "own" the interrupt make sure the interrupt mask bit is |
1520 | * cleared on i.MX21. Otherwise we can't read the interrupt status bit | |
1521 | * on this machine. | |
63f1474c | 1522 | */ |
f48d0f9a | 1523 | if (host->devtype_data->irqpending_quirk) { |
8556958a | 1524 | disable_irq_nosync(host->irq); |
e4303b25 | 1525 | host->devtype_data->irq_control(host, 1); |
8556958a | 1526 | } |
63f1474c | 1527 | |
bd3fd62e | 1528 | /* first scan to find the device and get the page size */ |
4d62435f | 1529 | if (nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL)) { |
bd3fd62e VB |
1530 | err = -ENXIO; |
1531 | goto escan; | |
1532 | } | |
34f6e157 | 1533 | |
6e85dfdc | 1534 | /* Call preset again, with correct writesize this time */ |
e4303b25 | 1535 | host->devtype_data->preset(mtd); |
6e85dfdc | 1536 | |
2d69c7fa | 1537 | if (mtd->writesize == 2048) |
6dcdf99d UKK |
1538 | this->ecc.layout = host->devtype_data->ecclayout_2k; |
1539 | else if (mtd->writesize == 4096) | |
1540 | this->ecc.layout = host->devtype_data->ecclayout_4k; | |
34f6e157 | 1541 | |
6a918bad | 1542 | if (this->ecc.mode == NAND_ECC_HW) { |
4d62435f | 1543 | if (is_imx21_nfc(host) || is_imx27_nfc(host)) |
6a918bad MD |
1544 | this->ecc.strength = 1; |
1545 | else | |
1546 | this->ecc.strength = (host->eccsize == 4) ? 4 : 8; | |
1547 | } | |
1548 | ||
4a43faf5 SH |
1549 | /* second phase scan */ |
1550 | if (nand_scan_tail(mtd)) { | |
1551 | err = -ENXIO; | |
1552 | goto escan; | |
1553 | } | |
1554 | ||
34f6e157 | 1555 | /* Register the partitions */ |
6436356b UKK |
1556 | mtd_device_parse_register(mtd, part_probes, |
1557 | &(struct mtd_part_parser_data){ | |
1558 | .of_node = pdev->dev.of_node, | |
1559 | }, | |
1560 | host->pdata.parts, | |
1561 | host->pdata.nr_parts); | |
34f6e157 SH |
1562 | |
1563 | platform_set_drvdata(pdev, host); | |
1564 | ||
1565 | return 0; | |
1566 | ||
1567 | escan: | |
c10d8ee3 LW |
1568 | if (host->clk_act) |
1569 | clk_disable_unprepare(host->clk); | |
34f6e157 SH |
1570 | |
1571 | return err; | |
1572 | } | |
1573 | ||
810b7e06 | 1574 | static int mxcnd_remove(struct platform_device *pdev) |
34f6e157 SH |
1575 | { |
1576 | struct mxc_nand_host *host = platform_get_drvdata(pdev); | |
1577 | ||
34f6e157 | 1578 | nand_release(&host->mtd); |
34f6e157 SH |
1579 | |
1580 | return 0; | |
1581 | } | |
1582 | ||
34f6e157 SH |
1583 | static struct platform_driver mxcnd_driver = { |
1584 | .driver = { | |
1585 | .name = DRIVER_NAME, | |
8d1fd16d | 1586 | .owner = THIS_MODULE, |
6436356b | 1587 | .of_match_table = of_match_ptr(mxcnd_dt_ids), |
04dd0d3a | 1588 | }, |
4d62435f | 1589 | .id_table = mxcnd_devtype, |
ddf16d62 | 1590 | .probe = mxcnd_probe, |
5153b88c | 1591 | .remove = mxcnd_remove, |
34f6e157 | 1592 | }; |
ddf16d62 | 1593 | module_platform_driver(mxcnd_driver); |
34f6e157 SH |
1594 | |
1595 | MODULE_AUTHOR("Freescale Semiconductor, Inc."); | |
1596 | MODULE_DESCRIPTION("MXC NAND MTD driver"); | |
1597 | MODULE_LICENSE("GPL"); |