Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Overview: |
3 | * This is the generic MTD driver for NAND flash devices. It should be | |
4 | * capable of working with almost all NAND chips currently available. | |
61b03bd7 | 5 | * |
1da177e4 | 6 | * Additional technical information is available on |
8b2b403c | 7 | * http://www.linux-mtd.infradead.org/doc/nand.html |
61b03bd7 | 8 | * |
1da177e4 | 9 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 10 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 11 | * |
ace4dfee | 12 | * Credits: |
61b03bd7 TG |
13 | * David Woodhouse for adding multichip support |
14 | * | |
1da177e4 LT |
15 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
16 | * rework for 2K page size chips | |
17 | * | |
ace4dfee | 18 | * TODO: |
1da177e4 LT |
19 | * Enable cached programming for 2k page size chips |
20 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
7854d3f7 | 21 | * if we have HW ECC support. |
c0b8ba7b | 22 | * BBT table is not serialized, has to be fixed |
1da177e4 | 23 | * |
1da177e4 LT |
24 | * This program is free software; you can redistribute it and/or modify |
25 | * it under the terms of the GNU General Public License version 2 as | |
26 | * published by the Free Software Foundation. | |
27 | * | |
28 | */ | |
29 | ||
20171642 EG |
30 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
31 | ||
552d9205 | 32 | #include <linux/module.h> |
1da177e4 LT |
33 | #include <linux/delay.h> |
34 | #include <linux/errno.h> | |
7aa65bfd | 35 | #include <linux/err.h> |
1da177e4 LT |
36 | #include <linux/sched.h> |
37 | #include <linux/slab.h> | |
66507c7b | 38 | #include <linux/mm.h> |
1da177e4 LT |
39 | #include <linux/types.h> |
40 | #include <linux/mtd/mtd.h> | |
41 | #include <linux/mtd/nand.h> | |
42 | #include <linux/mtd/nand_ecc.h> | |
193bd400 | 43 | #include <linux/mtd/nand_bch.h> |
1da177e4 LT |
44 | #include <linux/interrupt.h> |
45 | #include <linux/bitops.h> | |
8fe833c1 | 46 | #include <linux/leds.h> |
7351d3a5 | 47 | #include <linux/io.h> |
1da177e4 | 48 | #include <linux/mtd/partitions.h> |
5844feea | 49 | #include <linux/of_mtd.h> |
1da177e4 LT |
50 | |
51 | /* Define default oob placement schemes for large and small page devices */ | |
5bd34c09 | 52 | static struct nand_ecclayout nand_oob_8 = { |
1da177e4 LT |
53 | .eccbytes = 3, |
54 | .eccpos = {0, 1, 2}, | |
5bd34c09 TG |
55 | .oobfree = { |
56 | {.offset = 3, | |
57 | .length = 2}, | |
58 | {.offset = 6, | |
f8ac0414 | 59 | .length = 2} } |
1da177e4 LT |
60 | }; |
61 | ||
5bd34c09 | 62 | static struct nand_ecclayout nand_oob_16 = { |
1da177e4 LT |
63 | .eccbytes = 6, |
64 | .eccpos = {0, 1, 2, 3, 6, 7}, | |
5bd34c09 TG |
65 | .oobfree = { |
66 | {.offset = 8, | |
f8ac0414 | 67 | . length = 8} } |
1da177e4 LT |
68 | }; |
69 | ||
5bd34c09 | 70 | static struct nand_ecclayout nand_oob_64 = { |
1da177e4 LT |
71 | .eccbytes = 24, |
72 | .eccpos = { | |
e0c7d767 DW |
73 | 40, 41, 42, 43, 44, 45, 46, 47, |
74 | 48, 49, 50, 51, 52, 53, 54, 55, | |
75 | 56, 57, 58, 59, 60, 61, 62, 63}, | |
5bd34c09 TG |
76 | .oobfree = { |
77 | {.offset = 2, | |
f8ac0414 | 78 | .length = 38} } |
1da177e4 LT |
79 | }; |
80 | ||
81ec5364 TG |
81 | static struct nand_ecclayout nand_oob_128 = { |
82 | .eccbytes = 48, | |
83 | .eccpos = { | |
84 | 80, 81, 82, 83, 84, 85, 86, 87, | |
85 | 88, 89, 90, 91, 92, 93, 94, 95, | |
86 | 96, 97, 98, 99, 100, 101, 102, 103, | |
87 | 104, 105, 106, 107, 108, 109, 110, 111, | |
88 | 112, 113, 114, 115, 116, 117, 118, 119, | |
89 | 120, 121, 122, 123, 124, 125, 126, 127}, | |
90 | .oobfree = { | |
91 | {.offset = 2, | |
f8ac0414 | 92 | .length = 78} } |
81ec5364 TG |
93 | }; |
94 | ||
6a8214aa | 95 | static int nand_get_device(struct mtd_info *mtd, int new_state); |
1da177e4 | 96 | |
8593fbc6 TG |
97 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
98 | struct mtd_oob_ops *ops); | |
99 | ||
d470a97c | 100 | /* |
8e87d782 | 101 | * For devices which display every fart in the system on a separate LED. Is |
d470a97c TG |
102 | * compiled away when LED support is disabled. |
103 | */ | |
104 | DEFINE_LED_TRIGGER(nand_led_trigger); | |
105 | ||
6fe5a6ac VS |
106 | static int check_offs_len(struct mtd_info *mtd, |
107 | loff_t ofs, uint64_t len) | |
108 | { | |
862eba51 | 109 | struct nand_chip *chip = mtd_to_nand(mtd); |
6fe5a6ac VS |
110 | int ret = 0; |
111 | ||
112 | /* Start address must align on block boundary */ | |
daae74ca | 113 | if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 114 | pr_debug("%s: unaligned address\n", __func__); |
6fe5a6ac VS |
115 | ret = -EINVAL; |
116 | } | |
117 | ||
118 | /* Length must align on block boundary */ | |
daae74ca | 119 | if (len & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 120 | pr_debug("%s: length not block aligned\n", __func__); |
6fe5a6ac VS |
121 | ret = -EINVAL; |
122 | } | |
123 | ||
6fe5a6ac VS |
124 | return ret; |
125 | } | |
126 | ||
1da177e4 LT |
127 | /** |
128 | * nand_release_device - [GENERIC] release chip | |
8b6e50c9 | 129 | * @mtd: MTD device structure |
61b03bd7 | 130 | * |
b0bb6903 | 131 | * Release chip lock and wake up anyone waiting on the device. |
1da177e4 | 132 | */ |
e0c7d767 | 133 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 134 | { |
862eba51 | 135 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 136 | |
a36ed299 | 137 | /* Release the controller and the chip */ |
ace4dfee TG |
138 | spin_lock(&chip->controller->lock); |
139 | chip->controller->active = NULL; | |
140 | chip->state = FL_READY; | |
141 | wake_up(&chip->controller->wq); | |
142 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
143 | } |
144 | ||
145 | /** | |
146 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
8b6e50c9 | 147 | * @mtd: MTD device structure |
1da177e4 | 148 | * |
7854d3f7 | 149 | * Default read function for 8bit buswidth |
1da177e4 | 150 | */ |
58dd8f2b | 151 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 152 | { |
862eba51 | 153 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee | 154 | return readb(chip->IO_ADDR_R); |
1da177e4 LT |
155 | } |
156 | ||
1da177e4 | 157 | /** |
7854d3f7 | 158 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
8b6e50c9 | 159 | * @mtd: MTD device structure |
1da177e4 | 160 | * |
7854d3f7 BN |
161 | * Default read function for 16bit buswidth with endianness conversion. |
162 | * | |
1da177e4 | 163 | */ |
58dd8f2b | 164 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 165 | { |
862eba51 | 166 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee | 167 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); |
1da177e4 LT |
168 | } |
169 | ||
1da177e4 LT |
170 | /** |
171 | * nand_read_word - [DEFAULT] read one word from the chip | |
8b6e50c9 | 172 | * @mtd: MTD device structure |
1da177e4 | 173 | * |
7854d3f7 | 174 | * Default read function for 16bit buswidth without endianness conversion. |
1da177e4 LT |
175 | */ |
176 | static u16 nand_read_word(struct mtd_info *mtd) | |
177 | { | |
862eba51 | 178 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee | 179 | return readw(chip->IO_ADDR_R); |
1da177e4 LT |
180 | } |
181 | ||
1da177e4 LT |
182 | /** |
183 | * nand_select_chip - [DEFAULT] control CE line | |
8b6e50c9 BN |
184 | * @mtd: MTD device structure |
185 | * @chipnr: chipnumber to select, -1 for deselect | |
1da177e4 LT |
186 | * |
187 | * Default select function for 1 chip devices. | |
188 | */ | |
ace4dfee | 189 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 190 | { |
862eba51 | 191 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee TG |
192 | |
193 | switch (chipnr) { | |
1da177e4 | 194 | case -1: |
ace4dfee | 195 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
196 | break; |
197 | case 0: | |
1da177e4 LT |
198 | break; |
199 | ||
200 | default: | |
201 | BUG(); | |
202 | } | |
203 | } | |
204 | ||
05f78359 UKK |
205 | /** |
206 | * nand_write_byte - [DEFAULT] write single byte to chip | |
207 | * @mtd: MTD device structure | |
208 | * @byte: value to write | |
209 | * | |
210 | * Default function to write a byte to I/O[7:0] | |
211 | */ | |
212 | static void nand_write_byte(struct mtd_info *mtd, uint8_t byte) | |
213 | { | |
862eba51 | 214 | struct nand_chip *chip = mtd_to_nand(mtd); |
05f78359 UKK |
215 | |
216 | chip->write_buf(mtd, &byte, 1); | |
217 | } | |
218 | ||
219 | /** | |
220 | * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16 | |
221 | * @mtd: MTD device structure | |
222 | * @byte: value to write | |
223 | * | |
224 | * Default function to write a byte to I/O[7:0] on a 16-bit wide chip. | |
225 | */ | |
226 | static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte) | |
227 | { | |
862eba51 | 228 | struct nand_chip *chip = mtd_to_nand(mtd); |
05f78359 UKK |
229 | uint16_t word = byte; |
230 | ||
231 | /* | |
232 | * It's not entirely clear what should happen to I/O[15:8] when writing | |
233 | * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads: | |
234 | * | |
235 | * When the host supports a 16-bit bus width, only data is | |
236 | * transferred at the 16-bit width. All address and command line | |
237 | * transfers shall use only the lower 8-bits of the data bus. During | |
238 | * command transfers, the host may place any value on the upper | |
239 | * 8-bits of the data bus. During address transfers, the host shall | |
240 | * set the upper 8-bits of the data bus to 00h. | |
241 | * | |
242 | * One user of the write_byte callback is nand_onfi_set_features. The | |
243 | * four parameters are specified to be written to I/O[7:0], but this is | |
244 | * neither an address nor a command transfer. Let's assume a 0 on the | |
245 | * upper I/O lines is OK. | |
246 | */ | |
247 | chip->write_buf(mtd, (uint8_t *)&word, 2); | |
248 | } | |
249 | ||
1da177e4 LT |
250 | /** |
251 | * nand_write_buf - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
252 | * @mtd: MTD device structure |
253 | * @buf: data buffer | |
254 | * @len: number of bytes to write | |
1da177e4 | 255 | * |
7854d3f7 | 256 | * Default write function for 8bit buswidth. |
1da177e4 | 257 | */ |
58dd8f2b | 258 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 259 | { |
862eba51 | 260 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 261 | |
76413839 | 262 | iowrite8_rep(chip->IO_ADDR_W, buf, len); |
1da177e4 LT |
263 | } |
264 | ||
265 | /** | |
61b03bd7 | 266 | * nand_read_buf - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
267 | * @mtd: MTD device structure |
268 | * @buf: buffer to store date | |
269 | * @len: number of bytes to read | |
1da177e4 | 270 | * |
7854d3f7 | 271 | * Default read function for 8bit buswidth. |
1da177e4 | 272 | */ |
58dd8f2b | 273 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 274 | { |
862eba51 | 275 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 276 | |
76413839 | 277 | ioread8_rep(chip->IO_ADDR_R, buf, len); |
1da177e4 LT |
278 | } |
279 | ||
1da177e4 LT |
280 | /** |
281 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
282 | * @mtd: MTD device structure |
283 | * @buf: data buffer | |
284 | * @len: number of bytes to write | |
1da177e4 | 285 | * |
7854d3f7 | 286 | * Default write function for 16bit buswidth. |
1da177e4 | 287 | */ |
58dd8f2b | 288 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 289 | { |
862eba51 | 290 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 291 | u16 *p = (u16 *) buf; |
61b03bd7 | 292 | |
76413839 | 293 | iowrite16_rep(chip->IO_ADDR_W, p, len >> 1); |
1da177e4 LT |
294 | } |
295 | ||
296 | /** | |
61b03bd7 | 297 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
298 | * @mtd: MTD device structure |
299 | * @buf: buffer to store date | |
300 | * @len: number of bytes to read | |
1da177e4 | 301 | * |
7854d3f7 | 302 | * Default read function for 16bit buswidth. |
1da177e4 | 303 | */ |
58dd8f2b | 304 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 305 | { |
862eba51 | 306 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 307 | u16 *p = (u16 *) buf; |
1da177e4 | 308 | |
76413839 | 309 | ioread16_rep(chip->IO_ADDR_R, p, len >> 1); |
1da177e4 LT |
310 | } |
311 | ||
1da177e4 LT |
312 | /** |
313 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
8b6e50c9 BN |
314 | * @mtd: MTD device structure |
315 | * @ofs: offset from device start | |
1da177e4 | 316 | * |
61b03bd7 | 317 | * Check, if the block is bad. |
1da177e4 | 318 | */ |
9f3e0429 | 319 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 320 | { |
9f3e0429 | 321 | int page, res = 0, i = 0; |
862eba51 | 322 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 LT |
323 | u16 bad; |
324 | ||
5fb1549d | 325 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
b60b08b0 KC |
326 | ofs += mtd->erasesize - mtd->writesize; |
327 | ||
1a12f46a TK |
328 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
329 | ||
cdbec050 BN |
330 | do { |
331 | if (chip->options & NAND_BUSWIDTH_16) { | |
332 | chip->cmdfunc(mtd, NAND_CMD_READOOB, | |
333 | chip->badblockpos & 0xFE, page); | |
334 | bad = cpu_to_le16(chip->read_word(mtd)); | |
335 | if (chip->badblockpos & 0x1) | |
336 | bad >>= 8; | |
337 | else | |
338 | bad &= 0xFF; | |
339 | } else { | |
340 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, | |
341 | page); | |
342 | bad = chip->read_byte(mtd); | |
343 | } | |
344 | ||
345 | if (likely(chip->badblockbits == 8)) | |
346 | res = bad != 0xFF; | |
e0b58d0a | 347 | else |
cdbec050 BN |
348 | res = hweight8(bad) < chip->badblockbits; |
349 | ofs += mtd->writesize; | |
350 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; | |
351 | i++; | |
352 | } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE)); | |
e0b58d0a | 353 | |
1da177e4 LT |
354 | return res; |
355 | } | |
356 | ||
357 | /** | |
5a0edb25 | 358 | * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker |
8b6e50c9 BN |
359 | * @mtd: MTD device structure |
360 | * @ofs: offset from device start | |
1da177e4 | 361 | * |
8b6e50c9 | 362 | * This is the default implementation, which can be overridden by a hardware |
5a0edb25 BN |
363 | * specific driver. It provides the details for writing a bad block marker to a |
364 | * block. | |
365 | */ | |
366 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
367 | { | |
862eba51 | 368 | struct nand_chip *chip = mtd_to_nand(mtd); |
5a0edb25 BN |
369 | struct mtd_oob_ops ops; |
370 | uint8_t buf[2] = { 0, 0 }; | |
371 | int ret = 0, res, i = 0; | |
372 | ||
0ec56dc4 | 373 | memset(&ops, 0, sizeof(ops)); |
5a0edb25 BN |
374 | ops.oobbuf = buf; |
375 | ops.ooboffs = chip->badblockpos; | |
376 | if (chip->options & NAND_BUSWIDTH_16) { | |
377 | ops.ooboffs &= ~0x01; | |
378 | ops.len = ops.ooblen = 2; | |
379 | } else { | |
380 | ops.len = ops.ooblen = 1; | |
381 | } | |
382 | ops.mode = MTD_OPS_PLACE_OOB; | |
383 | ||
384 | /* Write to first/last page(s) if necessary */ | |
385 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) | |
386 | ofs += mtd->erasesize - mtd->writesize; | |
387 | do { | |
388 | res = nand_do_write_oob(mtd, ofs, &ops); | |
389 | if (!ret) | |
390 | ret = res; | |
391 | ||
392 | i++; | |
393 | ofs += mtd->writesize; | |
394 | } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); | |
395 | ||
396 | return ret; | |
397 | } | |
398 | ||
399 | /** | |
400 | * nand_block_markbad_lowlevel - mark a block bad | |
401 | * @mtd: MTD device structure | |
402 | * @ofs: offset from device start | |
403 | * | |
404 | * This function performs the generic NAND bad block marking steps (i.e., bad | |
405 | * block table(s) and/or marker(s)). We only allow the hardware driver to | |
406 | * specify how to write bad block markers to OOB (chip->block_markbad). | |
407 | * | |
b32843b7 | 408 | * We try operations in the following order: |
e2414f4c | 409 | * (1) erase the affected block, to allow OOB marker to be written cleanly |
b32843b7 BN |
410 | * (2) write bad block marker to OOB area of affected block (unless flag |
411 | * NAND_BBT_NO_OOB_BBM is present) | |
412 | * (3) update the BBT | |
413 | * Note that we retain the first error encountered in (2) or (3), finish the | |
e2414f4c | 414 | * procedures, and dump the error in the end. |
1da177e4 | 415 | */ |
5a0edb25 | 416 | static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 417 | { |
862eba51 | 418 | struct nand_chip *chip = mtd_to_nand(mtd); |
b32843b7 | 419 | int res, ret = 0; |
61b03bd7 | 420 | |
b32843b7 | 421 | if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { |
00918429 BN |
422 | struct erase_info einfo; |
423 | ||
424 | /* Attempt erase before marking OOB */ | |
425 | memset(&einfo, 0, sizeof(einfo)); | |
426 | einfo.mtd = mtd; | |
427 | einfo.addr = ofs; | |
daae74ca | 428 | einfo.len = 1ULL << chip->phys_erase_shift; |
00918429 | 429 | nand_erase_nand(mtd, &einfo, 0); |
1da177e4 | 430 | |
b32843b7 | 431 | /* Write bad block marker to OOB */ |
6a8214aa | 432 | nand_get_device(mtd, FL_WRITING); |
5a0edb25 | 433 | ret = chip->block_markbad(mtd, ofs); |
c0b8ba7b | 434 | nand_release_device(mtd); |
f1a28c02 | 435 | } |
e2414f4c | 436 | |
b32843b7 BN |
437 | /* Mark block bad in BBT */ |
438 | if (chip->bbt) { | |
439 | res = nand_markbad_bbt(mtd, ofs); | |
e2414f4c BN |
440 | if (!ret) |
441 | ret = res; | |
442 | } | |
443 | ||
f1a28c02 TG |
444 | if (!ret) |
445 | mtd->ecc_stats.badblocks++; | |
c0b8ba7b | 446 | |
f1a28c02 | 447 | return ret; |
1da177e4 LT |
448 | } |
449 | ||
61b03bd7 | 450 | /** |
1da177e4 | 451 | * nand_check_wp - [GENERIC] check if the chip is write protected |
8b6e50c9 | 452 | * @mtd: MTD device structure |
1da177e4 | 453 | * |
8b6e50c9 BN |
454 | * Check, if the device is write protected. The function expects, that the |
455 | * device is already selected. | |
1da177e4 | 456 | */ |
e0c7d767 | 457 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 458 | { |
862eba51 | 459 | struct nand_chip *chip = mtd_to_nand(mtd); |
93edbad6 | 460 | |
8b6e50c9 | 461 | /* Broken xD cards report WP despite being writable */ |
93edbad6 ML |
462 | if (chip->options & NAND_BROKEN_XD) |
463 | return 0; | |
464 | ||
1da177e4 | 465 | /* Check the WP bit */ |
ace4dfee TG |
466 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
467 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
468 | } |
469 | ||
8471bb73 | 470 | /** |
c30e1f79 | 471 | * nand_block_isreserved - [GENERIC] Check if a block is marked reserved. |
8471bb73 EG |
472 | * @mtd: MTD device structure |
473 | * @ofs: offset from device start | |
474 | * | |
c30e1f79 | 475 | * Check if the block is marked as reserved. |
8471bb73 EG |
476 | */ |
477 | static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) | |
478 | { | |
862eba51 | 479 | struct nand_chip *chip = mtd_to_nand(mtd); |
8471bb73 EG |
480 | |
481 | if (!chip->bbt) | |
482 | return 0; | |
483 | /* Return info from the table */ | |
484 | return nand_isreserved_bbt(mtd, ofs); | |
485 | } | |
486 | ||
1da177e4 LT |
487 | /** |
488 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
8b6e50c9 BN |
489 | * @mtd: MTD device structure |
490 | * @ofs: offset from device start | |
8b6e50c9 | 491 | * @allowbbt: 1, if its allowed to access the bbt area |
1da177e4 LT |
492 | * |
493 | * Check, if the block is bad. Either by reading the bad block table or | |
494 | * calling of the scan function. | |
495 | */ | |
9f3e0429 | 496 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt) |
1da177e4 | 497 | { |
862eba51 | 498 | struct nand_chip *chip = mtd_to_nand(mtd); |
61b03bd7 | 499 | |
ace4dfee | 500 | if (!chip->bbt) |
9f3e0429 | 501 | return chip->block_bad(mtd, ofs); |
61b03bd7 | 502 | |
1da177e4 | 503 | /* Return info from the table */ |
e0c7d767 | 504 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
505 | } |
506 | ||
2af7c653 SK |
507 | /** |
508 | * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
8b6e50c9 BN |
509 | * @mtd: MTD device structure |
510 | * @timeo: Timeout | |
2af7c653 SK |
511 | * |
512 | * Helper function for nand_wait_ready used when needing to wait in interrupt | |
513 | * context. | |
514 | */ | |
515 | static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) | |
516 | { | |
862eba51 | 517 | struct nand_chip *chip = mtd_to_nand(mtd); |
2af7c653 SK |
518 | int i; |
519 | ||
520 | /* Wait for the device to get ready */ | |
521 | for (i = 0; i < timeo; i++) { | |
522 | if (chip->dev_ready(mtd)) | |
523 | break; | |
524 | touch_softlockup_watchdog(); | |
525 | mdelay(1); | |
526 | } | |
527 | } | |
528 | ||
b70af9be AS |
529 | /** |
530 | * nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
531 | * @mtd: MTD device structure | |
532 | * | |
533 | * Wait for the ready pin after a command, and warn if a timeout occurs. | |
534 | */ | |
4b648b02 | 535 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 536 | { |
862eba51 | 537 | struct nand_chip *chip = mtd_to_nand(mtd); |
b70af9be | 538 | unsigned long timeo = 400; |
3b88775c | 539 | |
2af7c653 | 540 | if (in_interrupt() || oops_in_progress) |
b70af9be | 541 | return panic_nand_wait_ready(mtd, timeo); |
2af7c653 | 542 | |
8fe833c1 | 543 | led_trigger_event(nand_led_trigger, LED_FULL); |
7854d3f7 | 544 | /* Wait until command is processed or timeout occurs */ |
b70af9be | 545 | timeo = jiffies + msecs_to_jiffies(timeo); |
3b88775c | 546 | do { |
ace4dfee | 547 | if (chip->dev_ready(mtd)) |
b70af9be AS |
548 | goto out; |
549 | cond_resched(); | |
61b03bd7 | 550 | } while (time_before(jiffies, timeo)); |
b70af9be | 551 | |
9ebfdf5b BN |
552 | if (!chip->dev_ready(mtd)) |
553 | pr_warn_ratelimited("timeout while waiting for chip to become ready\n"); | |
b70af9be | 554 | out: |
8fe833c1 | 555 | led_trigger_event(nand_led_trigger, LED_OFF); |
3b88775c | 556 | } |
4b648b02 | 557 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 558 | |
60c70d66 RQ |
559 | /** |
560 | * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands. | |
561 | * @mtd: MTD device structure | |
562 | * @timeo: Timeout in ms | |
563 | * | |
564 | * Wait for status ready (i.e. command done) or timeout. | |
565 | */ | |
566 | static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo) | |
567 | { | |
862eba51 | 568 | register struct nand_chip *chip = mtd_to_nand(mtd); |
60c70d66 RQ |
569 | |
570 | timeo = jiffies + msecs_to_jiffies(timeo); | |
571 | do { | |
572 | if ((chip->read_byte(mtd) & NAND_STATUS_READY)) | |
573 | break; | |
574 | touch_softlockup_watchdog(); | |
575 | } while (time_before(jiffies, timeo)); | |
576 | }; | |
577 | ||
1da177e4 LT |
578 | /** |
579 | * nand_command - [DEFAULT] Send command to NAND device | |
8b6e50c9 BN |
580 | * @mtd: MTD device structure |
581 | * @command: the command to be sent | |
582 | * @column: the column address for this command, -1 if none | |
583 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 584 | * |
8b6e50c9 | 585 | * Send command to NAND device. This function is used for small page devices |
51148f1f | 586 | * (512 Bytes per page). |
1da177e4 | 587 | */ |
7abd3ef9 TG |
588 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
589 | int column, int page_addr) | |
1da177e4 | 590 | { |
862eba51 | 591 | register struct nand_chip *chip = mtd_to_nand(mtd); |
7abd3ef9 | 592 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 593 | |
8b6e50c9 | 594 | /* Write out the command to the device */ |
1da177e4 LT |
595 | if (command == NAND_CMD_SEQIN) { |
596 | int readcmd; | |
597 | ||
28318776 | 598 | if (column >= mtd->writesize) { |
1da177e4 | 599 | /* OOB area */ |
28318776 | 600 | column -= mtd->writesize; |
1da177e4 LT |
601 | readcmd = NAND_CMD_READOOB; |
602 | } else if (column < 256) { | |
603 | /* First 256 bytes --> READ0 */ | |
604 | readcmd = NAND_CMD_READ0; | |
605 | } else { | |
606 | column -= 256; | |
607 | readcmd = NAND_CMD_READ1; | |
608 | } | |
ace4dfee | 609 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 610 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 611 | } |
ace4dfee | 612 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 613 | |
8b6e50c9 | 614 | /* Address cycle, when necessary */ |
7abd3ef9 TG |
615 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; |
616 | /* Serially input address */ | |
617 | if (column != -1) { | |
618 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
619 | if (chip->options & NAND_BUSWIDTH_16 && |
620 | !nand_opcode_8bits(command)) | |
7abd3ef9 | 621 | column >>= 1; |
ace4dfee | 622 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
623 | ctrl &= ~NAND_CTRL_CHANGE; |
624 | } | |
625 | if (page_addr != -1) { | |
ace4dfee | 626 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 627 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 628 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 629 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
630 | if (chip->chipsize > (32 << 20)) |
631 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 632 | } |
ace4dfee | 633 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
634 | |
635 | /* | |
8b6e50c9 BN |
636 | * Program and erase have their own busy handlers status and sequential |
637 | * in needs no delay | |
e0c7d767 | 638 | */ |
1da177e4 | 639 | switch (command) { |
61b03bd7 | 640 | |
1da177e4 LT |
641 | case NAND_CMD_PAGEPROG: |
642 | case NAND_CMD_ERASE1: | |
643 | case NAND_CMD_ERASE2: | |
644 | case NAND_CMD_SEQIN: | |
645 | case NAND_CMD_STATUS: | |
646 | return; | |
647 | ||
648 | case NAND_CMD_RESET: | |
ace4dfee | 649 | if (chip->dev_ready) |
1da177e4 | 650 | break; |
ace4dfee TG |
651 | udelay(chip->chip_delay); |
652 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 653 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
654 | chip->cmd_ctrl(mtd, |
655 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
60c70d66 RQ |
656 | /* EZ-NAND can take upto 250ms as per ONFi v4.0 */ |
657 | nand_wait_status_ready(mtd, 250); | |
1da177e4 LT |
658 | return; |
659 | ||
e0c7d767 | 660 | /* This applies to read commands */ |
1da177e4 | 661 | default: |
61b03bd7 | 662 | /* |
1da177e4 LT |
663 | * If we don't have access to the busy pin, we apply the given |
664 | * command delay | |
e0c7d767 | 665 | */ |
ace4dfee TG |
666 | if (!chip->dev_ready) { |
667 | udelay(chip->chip_delay); | |
1da177e4 | 668 | return; |
61b03bd7 | 669 | } |
1da177e4 | 670 | } |
8b6e50c9 BN |
671 | /* |
672 | * Apply this short delay always to ensure that we do wait tWB in | |
673 | * any case on any machine. | |
674 | */ | |
e0c7d767 | 675 | ndelay(100); |
3b88775c TG |
676 | |
677 | nand_wait_ready(mtd); | |
1da177e4 LT |
678 | } |
679 | ||
680 | /** | |
681 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
8b6e50c9 BN |
682 | * @mtd: MTD device structure |
683 | * @command: the command to be sent | |
684 | * @column: the column address for this command, -1 if none | |
685 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 686 | * |
7abd3ef9 | 687 | * Send command to NAND device. This is the version for the new large page |
7854d3f7 BN |
688 | * devices. We don't have the separate regions as we have in the small page |
689 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 690 | */ |
7abd3ef9 TG |
691 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
692 | int column, int page_addr) | |
1da177e4 | 693 | { |
862eba51 | 694 | register struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 LT |
695 | |
696 | /* Emulate NAND_CMD_READOOB */ | |
697 | if (command == NAND_CMD_READOOB) { | |
28318776 | 698 | column += mtd->writesize; |
1da177e4 LT |
699 | command = NAND_CMD_READ0; |
700 | } | |
61b03bd7 | 701 | |
7abd3ef9 | 702 | /* Command latch cycle */ |
fb066ada | 703 | chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
704 | |
705 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 706 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
707 | |
708 | /* Serially input address */ | |
709 | if (column != -1) { | |
710 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
711 | if (chip->options & NAND_BUSWIDTH_16 && |
712 | !nand_opcode_8bits(command)) | |
1da177e4 | 713 | column >>= 1; |
ace4dfee | 714 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 715 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 716 | chip->cmd_ctrl(mtd, column >> 8, ctrl); |
61b03bd7 | 717 | } |
1da177e4 | 718 | if (page_addr != -1) { |
ace4dfee TG |
719 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
720 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 721 | NAND_NCE | NAND_ALE); |
1da177e4 | 722 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
723 | if (chip->chipsize > (128 << 20)) |
724 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 725 | NAND_NCE | NAND_ALE); |
1da177e4 | 726 | } |
1da177e4 | 727 | } |
ace4dfee | 728 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
729 | |
730 | /* | |
8b6e50c9 | 731 | * Program and erase have their own busy handlers status, sequential |
7a442f17 | 732 | * in and status need no delay. |
30f464b7 | 733 | */ |
1da177e4 | 734 | switch (command) { |
61b03bd7 | 735 | |
1da177e4 LT |
736 | case NAND_CMD_CACHEDPROG: |
737 | case NAND_CMD_PAGEPROG: | |
738 | case NAND_CMD_ERASE1: | |
739 | case NAND_CMD_ERASE2: | |
740 | case NAND_CMD_SEQIN: | |
7bc3312b | 741 | case NAND_CMD_RNDIN: |
1da177e4 | 742 | case NAND_CMD_STATUS: |
30f464b7 | 743 | return; |
1da177e4 LT |
744 | |
745 | case NAND_CMD_RESET: | |
ace4dfee | 746 | if (chip->dev_ready) |
1da177e4 | 747 | break; |
ace4dfee | 748 | udelay(chip->chip_delay); |
12efdde3 TG |
749 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
750 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
751 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
752 | NAND_NCE | NAND_CTRL_CHANGE); | |
60c70d66 RQ |
753 | /* EZ-NAND can take upto 250ms as per ONFi v4.0 */ |
754 | nand_wait_status_ready(mtd, 250); | |
1da177e4 LT |
755 | return; |
756 | ||
7bc3312b TG |
757 | case NAND_CMD_RNDOUT: |
758 | /* No ready / busy check necessary */ | |
759 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
760 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
761 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
762 | NAND_NCE | NAND_CTRL_CHANGE); | |
763 | return; | |
764 | ||
1da177e4 | 765 | case NAND_CMD_READ0: |
12efdde3 TG |
766 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
767 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
768 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
769 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 770 | |
e0c7d767 | 771 | /* This applies to read commands */ |
1da177e4 | 772 | default: |
61b03bd7 | 773 | /* |
1da177e4 | 774 | * If we don't have access to the busy pin, we apply the given |
8b6e50c9 | 775 | * command delay. |
e0c7d767 | 776 | */ |
ace4dfee TG |
777 | if (!chip->dev_ready) { |
778 | udelay(chip->chip_delay); | |
1da177e4 | 779 | return; |
61b03bd7 | 780 | } |
1da177e4 | 781 | } |
3b88775c | 782 | |
8b6e50c9 BN |
783 | /* |
784 | * Apply this short delay always to ensure that we do wait tWB in | |
785 | * any case on any machine. | |
786 | */ | |
e0c7d767 | 787 | ndelay(100); |
3b88775c TG |
788 | |
789 | nand_wait_ready(mtd); | |
1da177e4 LT |
790 | } |
791 | ||
2af7c653 SK |
792 | /** |
793 | * panic_nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
794 | * @chip: the nand chip descriptor |
795 | * @mtd: MTD device structure | |
796 | * @new_state: the state which is requested | |
2af7c653 SK |
797 | * |
798 | * Used when in panic, no locks are taken. | |
799 | */ | |
800 | static void panic_nand_get_device(struct nand_chip *chip, | |
801 | struct mtd_info *mtd, int new_state) | |
802 | { | |
7854d3f7 | 803 | /* Hardware controller shared among independent devices */ |
2af7c653 SK |
804 | chip->controller->active = chip; |
805 | chip->state = new_state; | |
806 | } | |
807 | ||
1da177e4 LT |
808 | /** |
809 | * nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
810 | * @mtd: MTD device structure |
811 | * @new_state: the state which is requested | |
1da177e4 LT |
812 | * |
813 | * Get the device and lock it for exclusive access | |
814 | */ | |
2c0a2bed | 815 | static int |
6a8214aa | 816 | nand_get_device(struct mtd_info *mtd, int new_state) |
1da177e4 | 817 | { |
862eba51 | 818 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee TG |
819 | spinlock_t *lock = &chip->controller->lock; |
820 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 821 | DECLARE_WAITQUEUE(wait, current); |
7351d3a5 | 822 | retry: |
0dfc6246 TG |
823 | spin_lock(lock); |
824 | ||
b8b3ee9a | 825 | /* Hardware controller shared among independent devices */ |
ace4dfee TG |
826 | if (!chip->controller->active) |
827 | chip->controller->active = chip; | |
a36ed299 | 828 | |
ace4dfee TG |
829 | if (chip->controller->active == chip && chip->state == FL_READY) { |
830 | chip->state = new_state; | |
0dfc6246 | 831 | spin_unlock(lock); |
962034f4 VW |
832 | return 0; |
833 | } | |
834 | if (new_state == FL_PM_SUSPENDED) { | |
6b0d9a84 LY |
835 | if (chip->controller->active->state == FL_PM_SUSPENDED) { |
836 | chip->state = FL_PM_SUSPENDED; | |
837 | spin_unlock(lock); | |
838 | return 0; | |
6b0d9a84 | 839 | } |
0dfc6246 TG |
840 | } |
841 | set_current_state(TASK_UNINTERRUPTIBLE); | |
842 | add_wait_queue(wq, &wait); | |
843 | spin_unlock(lock); | |
844 | schedule(); | |
845 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
846 | goto retry; |
847 | } | |
848 | ||
2af7c653 | 849 | /** |
8b6e50c9 BN |
850 | * panic_nand_wait - [GENERIC] wait until the command is done |
851 | * @mtd: MTD device structure | |
852 | * @chip: NAND chip structure | |
853 | * @timeo: timeout | |
2af7c653 SK |
854 | * |
855 | * Wait for command done. This is a helper function for nand_wait used when | |
856 | * we are in interrupt context. May happen when in panic and trying to write | |
b595076a | 857 | * an oops through mtdoops. |
2af7c653 SK |
858 | */ |
859 | static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, | |
860 | unsigned long timeo) | |
861 | { | |
862 | int i; | |
863 | for (i = 0; i < timeo; i++) { | |
864 | if (chip->dev_ready) { | |
865 | if (chip->dev_ready(mtd)) | |
866 | break; | |
867 | } else { | |
868 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
869 | break; | |
870 | } | |
871 | mdelay(1); | |
f8ac0414 | 872 | } |
2af7c653 SK |
873 | } |
874 | ||
1da177e4 | 875 | /** |
8b6e50c9 BN |
876 | * nand_wait - [DEFAULT] wait until the command is done |
877 | * @mtd: MTD device structure | |
878 | * @chip: NAND chip structure | |
1da177e4 | 879 | * |
b70af9be | 880 | * Wait for command done. This applies to erase and program only. |
844d3b42 | 881 | */ |
7bc3312b | 882 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
883 | { |
884 | ||
b70af9be AS |
885 | int status; |
886 | unsigned long timeo = 400; | |
1da177e4 | 887 | |
8fe833c1 RP |
888 | led_trigger_event(nand_led_trigger, LED_FULL); |
889 | ||
8b6e50c9 BN |
890 | /* |
891 | * Apply this short delay always to ensure that we do wait tWB in any | |
892 | * case on any machine. | |
893 | */ | |
e0c7d767 | 894 | ndelay(100); |
1da177e4 | 895 | |
14c65786 | 896 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 897 | |
2af7c653 SK |
898 | if (in_interrupt() || oops_in_progress) |
899 | panic_nand_wait(mtd, chip, timeo); | |
900 | else { | |
6d2559f8 | 901 | timeo = jiffies + msecs_to_jiffies(timeo); |
b70af9be | 902 | do { |
2af7c653 SK |
903 | if (chip->dev_ready) { |
904 | if (chip->dev_ready(mtd)) | |
905 | break; | |
906 | } else { | |
907 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
908 | break; | |
909 | } | |
910 | cond_resched(); | |
b70af9be | 911 | } while (time_before(jiffies, timeo)); |
1da177e4 | 912 | } |
8fe833c1 RP |
913 | led_trigger_event(nand_led_trigger, LED_OFF); |
914 | ||
ace4dfee | 915 | status = (int)chip->read_byte(mtd); |
f251b8df MC |
916 | /* This can happen if in case of timeout or buggy dev_ready */ |
917 | WARN_ON(!(status & NAND_STATUS_READY)); | |
1da177e4 LT |
918 | return status; |
919 | } | |
920 | ||
7d70f334 | 921 | /** |
b6d676db | 922 | * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
923 | * @mtd: mtd info |
924 | * @ofs: offset to start unlock from | |
925 | * @len: length to unlock | |
8b6e50c9 BN |
926 | * @invert: when = 0, unlock the range of blocks within the lower and |
927 | * upper boundary address | |
928 | * when = 1, unlock the range of blocks outside the boundaries | |
929 | * of the lower and upper boundary address | |
7d70f334 | 930 | * |
8b6e50c9 | 931 | * Returs unlock status. |
7d70f334 VS |
932 | */ |
933 | static int __nand_unlock(struct mtd_info *mtd, loff_t ofs, | |
934 | uint64_t len, int invert) | |
935 | { | |
936 | int ret = 0; | |
937 | int status, page; | |
862eba51 | 938 | struct nand_chip *chip = mtd_to_nand(mtd); |
7d70f334 VS |
939 | |
940 | /* Submit address of first page to unlock */ | |
941 | page = ofs >> chip->page_shift; | |
942 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); | |
943 | ||
944 | /* Submit address of last page to unlock */ | |
945 | page = (ofs + len) >> chip->page_shift; | |
946 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, | |
947 | (page | invert) & chip->pagemask); | |
948 | ||
949 | /* Call wait ready function */ | |
950 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 951 | /* See if device thinks it succeeded */ |
74830966 | 952 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 953 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
954 | __func__, status); |
955 | ret = -EIO; | |
956 | } | |
957 | ||
958 | return ret; | |
959 | } | |
960 | ||
961 | /** | |
b6d676db | 962 | * nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
963 | * @mtd: mtd info |
964 | * @ofs: offset to start unlock from | |
965 | * @len: length to unlock | |
7d70f334 | 966 | * |
8b6e50c9 | 967 | * Returns unlock status. |
7d70f334 VS |
968 | */ |
969 | int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
970 | { | |
971 | int ret = 0; | |
972 | int chipnr; | |
862eba51 | 973 | struct nand_chip *chip = mtd_to_nand(mtd); |
7d70f334 | 974 | |
289c0522 | 975 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
976 | __func__, (unsigned long long)ofs, len); |
977 | ||
978 | if (check_offs_len(mtd, ofs, len)) | |
b1a2348a | 979 | return -EINVAL; |
7d70f334 VS |
980 | |
981 | /* Align to last block address if size addresses end of the device */ | |
982 | if (ofs + len == mtd->size) | |
983 | len -= mtd->erasesize; | |
984 | ||
6a8214aa | 985 | nand_get_device(mtd, FL_UNLOCKING); |
7d70f334 VS |
986 | |
987 | /* Shift to get chip number */ | |
988 | chipnr = ofs >> chip->chip_shift; | |
989 | ||
990 | chip->select_chip(mtd, chipnr); | |
991 | ||
57d3a9a8 WD |
992 | /* |
993 | * Reset the chip. | |
994 | * If we want to check the WP through READ STATUS and check the bit 7 | |
995 | * we must reset the chip | |
996 | * some operation can also clear the bit 7 of status register | |
997 | * eg. erase/program a locked block | |
998 | */ | |
999 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1000 | ||
7d70f334 VS |
1001 | /* Check, if it is write protected */ |
1002 | if (nand_check_wp(mtd)) { | |
289c0522 | 1003 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
1004 | __func__); |
1005 | ret = -EIO; | |
1006 | goto out; | |
1007 | } | |
1008 | ||
1009 | ret = __nand_unlock(mtd, ofs, len, 0); | |
1010 | ||
1011 | out: | |
b0bb6903 | 1012 | chip->select_chip(mtd, -1); |
7d70f334 VS |
1013 | nand_release_device(mtd); |
1014 | ||
1015 | return ret; | |
1016 | } | |
7351d3a5 | 1017 | EXPORT_SYMBOL(nand_unlock); |
7d70f334 VS |
1018 | |
1019 | /** | |
b6d676db | 1020 | * nand_lock - [REPLACEABLE] locks all blocks present in the device |
b6d676db RD |
1021 | * @mtd: mtd info |
1022 | * @ofs: offset to start unlock from | |
1023 | * @len: length to unlock | |
7d70f334 | 1024 | * |
8b6e50c9 BN |
1025 | * This feature is not supported in many NAND parts. 'Micron' NAND parts do |
1026 | * have this feature, but it allows only to lock all blocks, not for specified | |
1027 | * range for block. Implementing 'lock' feature by making use of 'unlock', for | |
1028 | * now. | |
7d70f334 | 1029 | * |
8b6e50c9 | 1030 | * Returns lock status. |
7d70f334 VS |
1031 | */ |
1032 | int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
1033 | { | |
1034 | int ret = 0; | |
1035 | int chipnr, status, page; | |
862eba51 | 1036 | struct nand_chip *chip = mtd_to_nand(mtd); |
7d70f334 | 1037 | |
289c0522 | 1038 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
1039 | __func__, (unsigned long long)ofs, len); |
1040 | ||
1041 | if (check_offs_len(mtd, ofs, len)) | |
b1a2348a | 1042 | return -EINVAL; |
7d70f334 | 1043 | |
6a8214aa | 1044 | nand_get_device(mtd, FL_LOCKING); |
7d70f334 VS |
1045 | |
1046 | /* Shift to get chip number */ | |
1047 | chipnr = ofs >> chip->chip_shift; | |
1048 | ||
1049 | chip->select_chip(mtd, chipnr); | |
1050 | ||
57d3a9a8 WD |
1051 | /* |
1052 | * Reset the chip. | |
1053 | * If we want to check the WP through READ STATUS and check the bit 7 | |
1054 | * we must reset the chip | |
1055 | * some operation can also clear the bit 7 of status register | |
1056 | * eg. erase/program a locked block | |
1057 | */ | |
1058 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1059 | ||
7d70f334 VS |
1060 | /* Check, if it is write protected */ |
1061 | if (nand_check_wp(mtd)) { | |
289c0522 | 1062 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
1063 | __func__); |
1064 | status = MTD_ERASE_FAILED; | |
1065 | ret = -EIO; | |
1066 | goto out; | |
1067 | } | |
1068 | ||
1069 | /* Submit address of first page to lock */ | |
1070 | page = ofs >> chip->page_shift; | |
1071 | chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask); | |
1072 | ||
1073 | /* Call wait ready function */ | |
1074 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 1075 | /* See if device thinks it succeeded */ |
74830966 | 1076 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 1077 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
1078 | __func__, status); |
1079 | ret = -EIO; | |
1080 | goto out; | |
1081 | } | |
1082 | ||
1083 | ret = __nand_unlock(mtd, ofs, len, 0x1); | |
1084 | ||
1085 | out: | |
b0bb6903 | 1086 | chip->select_chip(mtd, -1); |
7d70f334 VS |
1087 | nand_release_device(mtd); |
1088 | ||
1089 | return ret; | |
1090 | } | |
7351d3a5 | 1091 | EXPORT_SYMBOL(nand_lock); |
7d70f334 | 1092 | |
730a43fb BB |
1093 | /** |
1094 | * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data | |
1095 | * @buf: buffer to test | |
1096 | * @len: buffer length | |
1097 | * @bitflips_threshold: maximum number of bitflips | |
1098 | * | |
1099 | * Check if a buffer contains only 0xff, which means the underlying region | |
1100 | * has been erased and is ready to be programmed. | |
1101 | * The bitflips_threshold specify the maximum number of bitflips before | |
1102 | * considering the region is not erased. | |
1103 | * Note: The logic of this function has been extracted from the memweight | |
1104 | * implementation, except that nand_check_erased_buf function exit before | |
1105 | * testing the whole buffer if the number of bitflips exceed the | |
1106 | * bitflips_threshold value. | |
1107 | * | |
1108 | * Returns a positive number of bitflips less than or equal to | |
1109 | * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the | |
1110 | * threshold. | |
1111 | */ | |
1112 | static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold) | |
1113 | { | |
1114 | const unsigned char *bitmap = buf; | |
1115 | int bitflips = 0; | |
1116 | int weight; | |
1117 | ||
1118 | for (; len && ((uintptr_t)bitmap) % sizeof(long); | |
1119 | len--, bitmap++) { | |
1120 | weight = hweight8(*bitmap); | |
1121 | bitflips += BITS_PER_BYTE - weight; | |
1122 | if (unlikely(bitflips > bitflips_threshold)) | |
1123 | return -EBADMSG; | |
1124 | } | |
1125 | ||
1126 | for (; len >= sizeof(long); | |
1127 | len -= sizeof(long), bitmap += sizeof(long)) { | |
1128 | weight = hweight_long(*((unsigned long *)bitmap)); | |
1129 | bitflips += BITS_PER_LONG - weight; | |
1130 | if (unlikely(bitflips > bitflips_threshold)) | |
1131 | return -EBADMSG; | |
1132 | } | |
1133 | ||
1134 | for (; len > 0; len--, bitmap++) { | |
1135 | weight = hweight8(*bitmap); | |
1136 | bitflips += BITS_PER_BYTE - weight; | |
1137 | if (unlikely(bitflips > bitflips_threshold)) | |
1138 | return -EBADMSG; | |
1139 | } | |
1140 | ||
1141 | return bitflips; | |
1142 | } | |
1143 | ||
1144 | /** | |
1145 | * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only | |
1146 | * 0xff data | |
1147 | * @data: data buffer to test | |
1148 | * @datalen: data length | |
1149 | * @ecc: ECC buffer | |
1150 | * @ecclen: ECC length | |
1151 | * @extraoob: extra OOB buffer | |
1152 | * @extraooblen: extra OOB length | |
1153 | * @bitflips_threshold: maximum number of bitflips | |
1154 | * | |
1155 | * Check if a data buffer and its associated ECC and OOB data contains only | |
1156 | * 0xff pattern, which means the underlying region has been erased and is | |
1157 | * ready to be programmed. | |
1158 | * The bitflips_threshold specify the maximum number of bitflips before | |
1159 | * considering the region as not erased. | |
1160 | * | |
1161 | * Note: | |
1162 | * 1/ ECC algorithms are working on pre-defined block sizes which are usually | |
1163 | * different from the NAND page size. When fixing bitflips, ECC engines will | |
1164 | * report the number of errors per chunk, and the NAND core infrastructure | |
1165 | * expect you to return the maximum number of bitflips for the whole page. | |
1166 | * This is why you should always use this function on a single chunk and | |
1167 | * not on the whole page. After checking each chunk you should update your | |
1168 | * max_bitflips value accordingly. | |
1169 | * 2/ When checking for bitflips in erased pages you should not only check | |
1170 | * the payload data but also their associated ECC data, because a user might | |
1171 | * have programmed almost all bits to 1 but a few. In this case, we | |
1172 | * shouldn't consider the chunk as erased, and checking ECC bytes prevent | |
1173 | * this case. | |
1174 | * 3/ The extraoob argument is optional, and should be used if some of your OOB | |
1175 | * data are protected by the ECC engine. | |
1176 | * It could also be used if you support subpages and want to attach some | |
1177 | * extra OOB data to an ECC chunk. | |
1178 | * | |
1179 | * Returns a positive number of bitflips less than or equal to | |
1180 | * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the | |
1181 | * threshold. In case of success, the passed buffers are filled with 0xff. | |
1182 | */ | |
1183 | int nand_check_erased_ecc_chunk(void *data, int datalen, | |
1184 | void *ecc, int ecclen, | |
1185 | void *extraoob, int extraooblen, | |
1186 | int bitflips_threshold) | |
1187 | { | |
1188 | int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0; | |
1189 | ||
1190 | data_bitflips = nand_check_erased_buf(data, datalen, | |
1191 | bitflips_threshold); | |
1192 | if (data_bitflips < 0) | |
1193 | return data_bitflips; | |
1194 | ||
1195 | bitflips_threshold -= data_bitflips; | |
1196 | ||
1197 | ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold); | |
1198 | if (ecc_bitflips < 0) | |
1199 | return ecc_bitflips; | |
1200 | ||
1201 | bitflips_threshold -= ecc_bitflips; | |
1202 | ||
1203 | extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen, | |
1204 | bitflips_threshold); | |
1205 | if (extraoob_bitflips < 0) | |
1206 | return extraoob_bitflips; | |
1207 | ||
1208 | if (data_bitflips) | |
1209 | memset(data, 0xff, datalen); | |
1210 | ||
1211 | if (ecc_bitflips) | |
1212 | memset(ecc, 0xff, ecclen); | |
1213 | ||
1214 | if (extraoob_bitflips) | |
1215 | memset(extraoob, 0xff, extraooblen); | |
1216 | ||
1217 | return data_bitflips + ecc_bitflips + extraoob_bitflips; | |
1218 | } | |
1219 | EXPORT_SYMBOL(nand_check_erased_ecc_chunk); | |
1220 | ||
8593fbc6 | 1221 | /** |
7854d3f7 | 1222 | * nand_read_page_raw - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1223 | * @mtd: mtd info structure |
1224 | * @chip: nand chip info structure | |
1225 | * @buf: buffer to store read data | |
1fbb938d | 1226 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1227 | * @page: page number to read |
52ff49df | 1228 | * |
7854d3f7 | 1229 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 TG |
1230 | */ |
1231 | static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1232 | uint8_t *buf, int oob_required, int page) |
8593fbc6 TG |
1233 | { |
1234 | chip->read_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
1235 | if (oob_required) |
1236 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
8593fbc6 TG |
1237 | return 0; |
1238 | } | |
1239 | ||
52ff49df | 1240 | /** |
7854d3f7 | 1241 | * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1242 | * @mtd: mtd info structure |
1243 | * @chip: nand chip info structure | |
1244 | * @buf: buffer to store read data | |
1fbb938d | 1245 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1246 | * @page: page number to read |
52ff49df DB |
1247 | * |
1248 | * We need a special oob layout and handling even when OOB isn't used. | |
1249 | */ | |
7351d3a5 | 1250 | static int nand_read_page_raw_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
1251 | struct nand_chip *chip, uint8_t *buf, |
1252 | int oob_required, int page) | |
52ff49df DB |
1253 | { |
1254 | int eccsize = chip->ecc.size; | |
1255 | int eccbytes = chip->ecc.bytes; | |
1256 | uint8_t *oob = chip->oob_poi; | |
1257 | int steps, size; | |
1258 | ||
1259 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1260 | chip->read_buf(mtd, buf, eccsize); | |
1261 | buf += eccsize; | |
1262 | ||
1263 | if (chip->ecc.prepad) { | |
1264 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1265 | oob += chip->ecc.prepad; | |
1266 | } | |
1267 | ||
1268 | chip->read_buf(mtd, oob, eccbytes); | |
1269 | oob += eccbytes; | |
1270 | ||
1271 | if (chip->ecc.postpad) { | |
1272 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1273 | oob += chip->ecc.postpad; | |
1274 | } | |
1275 | } | |
1276 | ||
1277 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1278 | if (size) | |
1279 | chip->read_buf(mtd, oob, size); | |
1280 | ||
1281 | return 0; | |
1282 | } | |
1283 | ||
1da177e4 | 1284 | /** |
7854d3f7 | 1285 | * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function |
8b6e50c9 BN |
1286 | * @mtd: mtd info structure |
1287 | * @chip: nand chip info structure | |
1288 | * @buf: buffer to store read data | |
1fbb938d | 1289 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1290 | * @page: page number to read |
068e3c0a | 1291 | */ |
f5bbdacc | 1292 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1293 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1294 | { |
f5bbdacc TG |
1295 | int i, eccsize = chip->ecc.size; |
1296 | int eccbytes = chip->ecc.bytes; | |
1297 | int eccsteps = chip->ecc.steps; | |
1298 | uint8_t *p = buf; | |
4bf63fcb DW |
1299 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1300 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1301 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
3f91e94f | 1302 | unsigned int max_bitflips = 0; |
f5bbdacc | 1303 | |
1fbb938d | 1304 | chip->ecc.read_page_raw(mtd, chip, buf, 1, page); |
f5bbdacc TG |
1305 | |
1306 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1307 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1308 | ||
1309 | for (i = 0; i < chip->ecc.total; i++) | |
f75e5097 | 1310 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
f5bbdacc TG |
1311 | |
1312 | eccsteps = chip->ecc.steps; | |
1313 | p = buf; | |
1314 | ||
1315 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1316 | int stat; | |
1317 | ||
1318 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
3f91e94f | 1319 | if (stat < 0) { |
f5bbdacc | 1320 | mtd->ecc_stats.failed++; |
3f91e94f | 1321 | } else { |
f5bbdacc | 1322 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1323 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1324 | } | |
f5bbdacc | 1325 | } |
3f91e94f | 1326 | return max_bitflips; |
22c60f5f | 1327 | } |
1da177e4 | 1328 | |
3d459559 | 1329 | /** |
837a6ba4 | 1330 | * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function |
8b6e50c9 BN |
1331 | * @mtd: mtd info structure |
1332 | * @chip: nand chip info structure | |
1333 | * @data_offs: offset of requested data within the page | |
1334 | * @readlen: data length | |
1335 | * @bufpoi: buffer to store read data | |
e004debd | 1336 | * @page: page number to read |
3d459559 | 1337 | */ |
7351d3a5 | 1338 | static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, |
e004debd HS |
1339 | uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi, |
1340 | int page) | |
3d459559 AK |
1341 | { |
1342 | int start_step, end_step, num_steps; | |
1343 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1344 | uint8_t *p; | |
1345 | int data_col_addr, i, gaps = 0; | |
1346 | int datafrag_len, eccfrag_len, aligned_len, aligned_pos; | |
1347 | int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; | |
4a4163ca | 1348 | int index; |
3f91e94f | 1349 | unsigned int max_bitflips = 0; |
3d459559 | 1350 | |
7854d3f7 | 1351 | /* Column address within the page aligned to ECC size (256bytes) */ |
3d459559 AK |
1352 | start_step = data_offs / chip->ecc.size; |
1353 | end_step = (data_offs + readlen - 1) / chip->ecc.size; | |
1354 | num_steps = end_step - start_step + 1; | |
4a4163ca | 1355 | index = start_step * chip->ecc.bytes; |
3d459559 | 1356 | |
8b6e50c9 | 1357 | /* Data size aligned to ECC ecc.size */ |
3d459559 AK |
1358 | datafrag_len = num_steps * chip->ecc.size; |
1359 | eccfrag_len = num_steps * chip->ecc.bytes; | |
1360 | ||
1361 | data_col_addr = start_step * chip->ecc.size; | |
1362 | /* If we read not a page aligned data */ | |
1363 | if (data_col_addr != 0) | |
1364 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); | |
1365 | ||
1366 | p = bufpoi + data_col_addr; | |
1367 | chip->read_buf(mtd, p, datafrag_len); | |
1368 | ||
8b6e50c9 | 1369 | /* Calculate ECC */ |
3d459559 AK |
1370 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) |
1371 | chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); | |
1372 | ||
8b6e50c9 BN |
1373 | /* |
1374 | * The performance is faster if we position offsets according to | |
7854d3f7 | 1375 | * ecc.pos. Let's make sure that there are no gaps in ECC positions. |
8b6e50c9 | 1376 | */ |
3d459559 | 1377 | for (i = 0; i < eccfrag_len - 1; i++) { |
47570bb1 | 1378 | if (eccpos[i + index] + 1 != eccpos[i + index + 1]) { |
3d459559 AK |
1379 | gaps = 1; |
1380 | break; | |
1381 | } | |
1382 | } | |
1383 | if (gaps) { | |
1384 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
1385 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1386 | } else { | |
8b6e50c9 | 1387 | /* |
7854d3f7 | 1388 | * Send the command to read the particular ECC bytes take care |
8b6e50c9 BN |
1389 | * about buswidth alignment in read_buf. |
1390 | */ | |
7351d3a5 | 1391 | aligned_pos = eccpos[index] & ~(busw - 1); |
3d459559 | 1392 | aligned_len = eccfrag_len; |
7351d3a5 | 1393 | if (eccpos[index] & (busw - 1)) |
3d459559 | 1394 | aligned_len++; |
7351d3a5 | 1395 | if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1)) |
3d459559 AK |
1396 | aligned_len++; |
1397 | ||
7351d3a5 FF |
1398 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, |
1399 | mtd->writesize + aligned_pos, -1); | |
3d459559 AK |
1400 | chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); |
1401 | } | |
1402 | ||
1403 | for (i = 0; i < eccfrag_len; i++) | |
7351d3a5 | 1404 | chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]]; |
3d459559 AK |
1405 | |
1406 | p = bufpoi + data_col_addr; | |
1407 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { | |
1408 | int stat; | |
1409 | ||
7351d3a5 FF |
1410 | stat = chip->ecc.correct(mtd, p, |
1411 | &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); | |
40cbe6ee BB |
1412 | if (stat == -EBADMSG && |
1413 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
1414 | /* check for empty pages with bitflips */ | |
1415 | stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, | |
1416 | &chip->buffers->ecccode[i], | |
1417 | chip->ecc.bytes, | |
1418 | NULL, 0, | |
1419 | chip->ecc.strength); | |
1420 | } | |
1421 | ||
3f91e94f | 1422 | if (stat < 0) { |
3d459559 | 1423 | mtd->ecc_stats.failed++; |
3f91e94f | 1424 | } else { |
3d459559 | 1425 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1426 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1427 | } | |
3d459559 | 1428 | } |
3f91e94f | 1429 | return max_bitflips; |
3d459559 AK |
1430 | } |
1431 | ||
068e3c0a | 1432 | /** |
7854d3f7 | 1433 | * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function |
8b6e50c9 BN |
1434 | * @mtd: mtd info structure |
1435 | * @chip: nand chip info structure | |
1436 | * @buf: buffer to store read data | |
1fbb938d | 1437 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1438 | * @page: page number to read |
068e3c0a | 1439 | * |
7854d3f7 | 1440 | * Not for syndrome calculating ECC controllers which need a special oob layout. |
068e3c0a | 1441 | */ |
f5bbdacc | 1442 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1443 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1444 | { |
f5bbdacc TG |
1445 | int i, eccsize = chip->ecc.size; |
1446 | int eccbytes = chip->ecc.bytes; | |
1447 | int eccsteps = chip->ecc.steps; | |
1448 | uint8_t *p = buf; | |
4bf63fcb DW |
1449 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1450 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1451 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
3f91e94f | 1452 | unsigned int max_bitflips = 0; |
f5bbdacc TG |
1453 | |
1454 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1455 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1456 | chip->read_buf(mtd, p, eccsize); | |
1457 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 1458 | } |
f75e5097 | 1459 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 1460 | |
f5bbdacc | 1461 | for (i = 0; i < chip->ecc.total; i++) |
f75e5097 | 1462 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
1da177e4 | 1463 | |
f5bbdacc TG |
1464 | eccsteps = chip->ecc.steps; |
1465 | p = buf; | |
61b03bd7 | 1466 | |
f5bbdacc TG |
1467 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1468 | int stat; | |
1da177e4 | 1469 | |
f5bbdacc | 1470 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
40cbe6ee BB |
1471 | if (stat == -EBADMSG && |
1472 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
1473 | /* check for empty pages with bitflips */ | |
1474 | stat = nand_check_erased_ecc_chunk(p, eccsize, | |
1475 | &ecc_code[i], eccbytes, | |
1476 | NULL, 0, | |
1477 | chip->ecc.strength); | |
1478 | } | |
1479 | ||
3f91e94f | 1480 | if (stat < 0) { |
f5bbdacc | 1481 | mtd->ecc_stats.failed++; |
3f91e94f | 1482 | } else { |
f5bbdacc | 1483 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1484 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1485 | } | |
f5bbdacc | 1486 | } |
3f91e94f | 1487 | return max_bitflips; |
f5bbdacc | 1488 | } |
1da177e4 | 1489 | |
6e0cb135 | 1490 | /** |
7854d3f7 | 1491 | * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first |
8b6e50c9 BN |
1492 | * @mtd: mtd info structure |
1493 | * @chip: nand chip info structure | |
1494 | * @buf: buffer to store read data | |
1fbb938d | 1495 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1496 | * @page: page number to read |
6e0cb135 | 1497 | * |
8b6e50c9 BN |
1498 | * Hardware ECC for large page chips, require OOB to be read first. For this |
1499 | * ECC mode, the write_page method is re-used from ECC_HW. These methods | |
1500 | * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with | |
1501 | * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from | |
1502 | * the data area, by overwriting the NAND manufacturer bad block markings. | |
6e0cb135 SN |
1503 | */ |
1504 | static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, | |
1fbb938d | 1505 | struct nand_chip *chip, uint8_t *buf, int oob_required, int page) |
6e0cb135 SN |
1506 | { |
1507 | int i, eccsize = chip->ecc.size; | |
1508 | int eccbytes = chip->ecc.bytes; | |
1509 | int eccsteps = chip->ecc.steps; | |
1510 | uint8_t *p = buf; | |
1511 | uint8_t *ecc_code = chip->buffers->ecccode; | |
1512 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1513 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
3f91e94f | 1514 | unsigned int max_bitflips = 0; |
6e0cb135 SN |
1515 | |
1516 | /* Read the OOB area first */ | |
1517 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1518 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1519 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1520 | ||
1521 | for (i = 0; i < chip->ecc.total; i++) | |
1522 | ecc_code[i] = chip->oob_poi[eccpos[i]]; | |
1523 | ||
1524 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1525 | int stat; | |
1526 | ||
1527 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1528 | chip->read_buf(mtd, p, eccsize); | |
1529 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1530 | ||
1531 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); | |
40cbe6ee BB |
1532 | if (stat == -EBADMSG && |
1533 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
1534 | /* check for empty pages with bitflips */ | |
1535 | stat = nand_check_erased_ecc_chunk(p, eccsize, | |
1536 | &ecc_code[i], eccbytes, | |
1537 | NULL, 0, | |
1538 | chip->ecc.strength); | |
1539 | } | |
1540 | ||
3f91e94f | 1541 | if (stat < 0) { |
6e0cb135 | 1542 | mtd->ecc_stats.failed++; |
3f91e94f | 1543 | } else { |
6e0cb135 | 1544 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1545 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1546 | } | |
6e0cb135 | 1547 | } |
3f91e94f | 1548 | return max_bitflips; |
6e0cb135 SN |
1549 | } |
1550 | ||
f5bbdacc | 1551 | /** |
7854d3f7 | 1552 | * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read |
8b6e50c9 BN |
1553 | * @mtd: mtd info structure |
1554 | * @chip: nand chip info structure | |
1555 | * @buf: buffer to store read data | |
1fbb938d | 1556 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1557 | * @page: page number to read |
f5bbdacc | 1558 | * |
8b6e50c9 BN |
1559 | * The hw generator calculates the error syndrome automatically. Therefore we |
1560 | * need a special oob layout and handling. | |
f5bbdacc TG |
1561 | */ |
1562 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1563 | uint8_t *buf, int oob_required, int page) |
f5bbdacc TG |
1564 | { |
1565 | int i, eccsize = chip->ecc.size; | |
1566 | int eccbytes = chip->ecc.bytes; | |
1567 | int eccsteps = chip->ecc.steps; | |
40cbe6ee | 1568 | int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad; |
f5bbdacc | 1569 | uint8_t *p = buf; |
f75e5097 | 1570 | uint8_t *oob = chip->oob_poi; |
3f91e94f | 1571 | unsigned int max_bitflips = 0; |
1da177e4 | 1572 | |
f5bbdacc TG |
1573 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1574 | int stat; | |
61b03bd7 | 1575 | |
f5bbdacc TG |
1576 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
1577 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 1578 | |
f5bbdacc TG |
1579 | if (chip->ecc.prepad) { |
1580 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1581 | oob += chip->ecc.prepad; | |
1582 | } | |
1da177e4 | 1583 | |
f5bbdacc TG |
1584 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
1585 | chip->read_buf(mtd, oob, eccbytes); | |
1586 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 1587 | |
f5bbdacc | 1588 | oob += eccbytes; |
1da177e4 | 1589 | |
f5bbdacc TG |
1590 | if (chip->ecc.postpad) { |
1591 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1592 | oob += chip->ecc.postpad; | |
61b03bd7 | 1593 | } |
40cbe6ee BB |
1594 | |
1595 | if (stat == -EBADMSG && | |
1596 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
1597 | /* check for empty pages with bitflips */ | |
1598 | stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, | |
1599 | oob - eccpadbytes, | |
1600 | eccpadbytes, | |
1601 | NULL, 0, | |
1602 | chip->ecc.strength); | |
1603 | } | |
1604 | ||
1605 | if (stat < 0) { | |
1606 | mtd->ecc_stats.failed++; | |
1607 | } else { | |
1608 | mtd->ecc_stats.corrected += stat; | |
1609 | max_bitflips = max_t(unsigned int, max_bitflips, stat); | |
1610 | } | |
f5bbdacc | 1611 | } |
1da177e4 | 1612 | |
f5bbdacc | 1613 | /* Calculate remaining oob bytes */ |
7e4178f9 | 1614 | i = mtd->oobsize - (oob - chip->oob_poi); |
f5bbdacc TG |
1615 | if (i) |
1616 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 1617 | |
3f91e94f | 1618 | return max_bitflips; |
f5bbdacc | 1619 | } |
1da177e4 | 1620 | |
f5bbdacc | 1621 | /** |
7854d3f7 | 1622 | * nand_transfer_oob - [INTERN] Transfer oob to client buffer |
8b6e50c9 BN |
1623 | * @chip: nand chip structure |
1624 | * @oob: oob destination address | |
1625 | * @ops: oob ops structure | |
1626 | * @len: size of oob to transfer | |
8593fbc6 TG |
1627 | */ |
1628 | static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, | |
7014568b | 1629 | struct mtd_oob_ops *ops, size_t len) |
8593fbc6 | 1630 | { |
f8ac0414 | 1631 | switch (ops->mode) { |
8593fbc6 | 1632 | |
0612b9dd BN |
1633 | case MTD_OPS_PLACE_OOB: |
1634 | case MTD_OPS_RAW: | |
8593fbc6 TG |
1635 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); |
1636 | return oob + len; | |
1637 | ||
0612b9dd | 1638 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 1639 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
1640 | uint32_t boffs = 0, roffs = ops->ooboffs; |
1641 | size_t bytes = 0; | |
8593fbc6 | 1642 | |
f8ac0414 | 1643 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 1644 | /* Read request not from offset 0? */ |
7bc3312b TG |
1645 | if (unlikely(roffs)) { |
1646 | if (roffs >= free->length) { | |
1647 | roffs -= free->length; | |
1648 | continue; | |
1649 | } | |
1650 | boffs = free->offset + roffs; | |
1651 | bytes = min_t(size_t, len, | |
1652 | (free->length - roffs)); | |
1653 | roffs = 0; | |
1654 | } else { | |
1655 | bytes = min_t(size_t, len, free->length); | |
1656 | boffs = free->offset; | |
1657 | } | |
1658 | memcpy(oob, chip->oob_poi + boffs, bytes); | |
8593fbc6 TG |
1659 | oob += bytes; |
1660 | } | |
1661 | return oob; | |
1662 | } | |
1663 | default: | |
1664 | BUG(); | |
1665 | } | |
1666 | return NULL; | |
1667 | } | |
1668 | ||
ba84fb59 BN |
1669 | /** |
1670 | * nand_setup_read_retry - [INTERN] Set the READ RETRY mode | |
1671 | * @mtd: MTD device structure | |
1672 | * @retry_mode: the retry mode to use | |
1673 | * | |
1674 | * Some vendors supply a special command to shift the Vt threshold, to be used | |
1675 | * when there are too many bitflips in a page (i.e., ECC error). After setting | |
1676 | * a new threshold, the host should retry reading the page. | |
1677 | */ | |
1678 | static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) | |
1679 | { | |
862eba51 | 1680 | struct nand_chip *chip = mtd_to_nand(mtd); |
ba84fb59 BN |
1681 | |
1682 | pr_debug("setting READ RETRY mode %d\n", retry_mode); | |
1683 | ||
1684 | if (retry_mode >= chip->read_retries) | |
1685 | return -EINVAL; | |
1686 | ||
1687 | if (!chip->setup_read_retry) | |
1688 | return -EOPNOTSUPP; | |
1689 | ||
1690 | return chip->setup_read_retry(mtd, retry_mode); | |
1691 | } | |
1692 | ||
8593fbc6 | 1693 | /** |
7854d3f7 | 1694 | * nand_do_read_ops - [INTERN] Read data with ECC |
8b6e50c9 BN |
1695 | * @mtd: MTD device structure |
1696 | * @from: offset to read from | |
1697 | * @ops: oob ops structure | |
f5bbdacc TG |
1698 | * |
1699 | * Internal function. Called with chip held. | |
1700 | */ | |
8593fbc6 TG |
1701 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
1702 | struct mtd_oob_ops *ops) | |
f5bbdacc | 1703 | { |
e47f3db4 | 1704 | int chipnr, page, realpage, col, bytes, aligned, oob_required; |
862eba51 | 1705 | struct nand_chip *chip = mtd_to_nand(mtd); |
f5bbdacc | 1706 | int ret = 0; |
8593fbc6 | 1707 | uint32_t readlen = ops->len; |
7014568b | 1708 | uint32_t oobreadlen = ops->ooblen; |
29f1058a | 1709 | uint32_t max_oobsize = mtd_oobavail(mtd, ops); |
9aca334e | 1710 | |
8593fbc6 | 1711 | uint8_t *bufpoi, *oob, *buf; |
66507c7b | 1712 | int use_bufpoi; |
edbc4540 | 1713 | unsigned int max_bitflips = 0; |
ba84fb59 | 1714 | int retry_mode = 0; |
b72f3dfb | 1715 | bool ecc_fail = false; |
1da177e4 | 1716 | |
f5bbdacc TG |
1717 | chipnr = (int)(from >> chip->chip_shift); |
1718 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 1719 | |
f5bbdacc TG |
1720 | realpage = (int)(from >> chip->page_shift); |
1721 | page = realpage & chip->pagemask; | |
1da177e4 | 1722 | |
f5bbdacc | 1723 | col = (int)(from & (mtd->writesize - 1)); |
61b03bd7 | 1724 | |
8593fbc6 TG |
1725 | buf = ops->datbuf; |
1726 | oob = ops->oobbuf; | |
e47f3db4 | 1727 | oob_required = oob ? 1 : 0; |
8593fbc6 | 1728 | |
f8ac0414 | 1729 | while (1) { |
b72f3dfb BN |
1730 | unsigned int ecc_failures = mtd->ecc_stats.failed; |
1731 | ||
f5bbdacc TG |
1732 | bytes = min(mtd->writesize - col, readlen); |
1733 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 1734 | |
66507c7b KD |
1735 | if (!aligned) |
1736 | use_bufpoi = 1; | |
1737 | else if (chip->options & NAND_USE_BOUNCE_BUFFER) | |
1738 | use_bufpoi = !virt_addr_valid(buf); | |
1739 | else | |
1740 | use_bufpoi = 0; | |
1741 | ||
8b6e50c9 | 1742 | /* Is the current page in the buffer? */ |
8593fbc6 | 1743 | if (realpage != chip->pagebuf || oob) { |
66507c7b KD |
1744 | bufpoi = use_bufpoi ? chip->buffers->databuf : buf; |
1745 | ||
1746 | if (use_bufpoi && aligned) | |
1747 | pr_debug("%s: using read bounce buffer for buf@%p\n", | |
1748 | __func__, buf); | |
61b03bd7 | 1749 | |
ba84fb59 | 1750 | read_retry: |
c00a0991 | 1751 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); |
1da177e4 | 1752 | |
edbc4540 MD |
1753 | /* |
1754 | * Now read the page into the buffer. Absent an error, | |
1755 | * the read methods return max bitflips per ecc step. | |
1756 | */ | |
0612b9dd | 1757 | if (unlikely(ops->mode == MTD_OPS_RAW)) |
1fbb938d | 1758 | ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, |
e47f3db4 BN |
1759 | oob_required, |
1760 | page); | |
a5ff4f10 JW |
1761 | else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && |
1762 | !oob) | |
7351d3a5 | 1763 | ret = chip->ecc.read_subpage(mtd, chip, |
e004debd HS |
1764 | col, bytes, bufpoi, |
1765 | page); | |
956e944c | 1766 | else |
46a8cf2d | 1767 | ret = chip->ecc.read_page(mtd, chip, bufpoi, |
e47f3db4 | 1768 | oob_required, page); |
6d77b9d0 | 1769 | if (ret < 0) { |
66507c7b | 1770 | if (use_bufpoi) |
6d77b9d0 BN |
1771 | /* Invalidate page cache */ |
1772 | chip->pagebuf = -1; | |
1da177e4 | 1773 | break; |
6d77b9d0 | 1774 | } |
f5bbdacc | 1775 | |
edbc4540 MD |
1776 | max_bitflips = max_t(unsigned int, max_bitflips, ret); |
1777 | ||
f5bbdacc | 1778 | /* Transfer not aligned data */ |
66507c7b | 1779 | if (use_bufpoi) { |
a5ff4f10 | 1780 | if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && |
b72f3dfb | 1781 | !(mtd->ecc_stats.failed - ecc_failures) && |
edbc4540 | 1782 | (ops->mode != MTD_OPS_RAW)) { |
3d459559 | 1783 | chip->pagebuf = realpage; |
edbc4540 MD |
1784 | chip->pagebuf_bitflips = ret; |
1785 | } else { | |
6d77b9d0 BN |
1786 | /* Invalidate page cache */ |
1787 | chip->pagebuf = -1; | |
edbc4540 | 1788 | } |
4bf63fcb | 1789 | memcpy(buf, chip->buffers->databuf + col, bytes); |
f5bbdacc TG |
1790 | } |
1791 | ||
8593fbc6 | 1792 | if (unlikely(oob)) { |
b64d39d8 ML |
1793 | int toread = min(oobreadlen, max_oobsize); |
1794 | ||
1795 | if (toread) { | |
1796 | oob = nand_transfer_oob(chip, | |
1797 | oob, ops, toread); | |
1798 | oobreadlen -= toread; | |
1799 | } | |
8593fbc6 | 1800 | } |
5bc7c33c BN |
1801 | |
1802 | if (chip->options & NAND_NEED_READRDY) { | |
1803 | /* Apply delay or wait for ready/busy pin */ | |
1804 | if (!chip->dev_ready) | |
1805 | udelay(chip->chip_delay); | |
1806 | else | |
1807 | nand_wait_ready(mtd); | |
1808 | } | |
b72f3dfb | 1809 | |
ba84fb59 | 1810 | if (mtd->ecc_stats.failed - ecc_failures) { |
28fa65e6 | 1811 | if (retry_mode + 1 < chip->read_retries) { |
ba84fb59 BN |
1812 | retry_mode++; |
1813 | ret = nand_setup_read_retry(mtd, | |
1814 | retry_mode); | |
1815 | if (ret < 0) | |
1816 | break; | |
1817 | ||
1818 | /* Reset failures; retry */ | |
1819 | mtd->ecc_stats.failed = ecc_failures; | |
1820 | goto read_retry; | |
1821 | } else { | |
1822 | /* No more retry modes; real failure */ | |
1823 | ecc_fail = true; | |
1824 | } | |
1825 | } | |
1826 | ||
1827 | buf += bytes; | |
8593fbc6 | 1828 | } else { |
4bf63fcb | 1829 | memcpy(buf, chip->buffers->databuf + col, bytes); |
8593fbc6 | 1830 | buf += bytes; |
edbc4540 MD |
1831 | max_bitflips = max_t(unsigned int, max_bitflips, |
1832 | chip->pagebuf_bitflips); | |
8593fbc6 | 1833 | } |
1da177e4 | 1834 | |
f5bbdacc | 1835 | readlen -= bytes; |
61b03bd7 | 1836 | |
ba84fb59 BN |
1837 | /* Reset to retry mode 0 */ |
1838 | if (retry_mode) { | |
1839 | ret = nand_setup_read_retry(mtd, 0); | |
1840 | if (ret < 0) | |
1841 | break; | |
1842 | retry_mode = 0; | |
1843 | } | |
1844 | ||
f5bbdacc | 1845 | if (!readlen) |
61b03bd7 | 1846 | break; |
1da177e4 | 1847 | |
8b6e50c9 | 1848 | /* For subsequent reads align to page boundary */ |
1da177e4 LT |
1849 | col = 0; |
1850 | /* Increment page address */ | |
1851 | realpage++; | |
1852 | ||
ace4dfee | 1853 | page = realpage & chip->pagemask; |
1da177e4 LT |
1854 | /* Check, if we cross a chip boundary */ |
1855 | if (!page) { | |
1856 | chipnr++; | |
ace4dfee TG |
1857 | chip->select_chip(mtd, -1); |
1858 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1859 | } |
1da177e4 | 1860 | } |
b0bb6903 | 1861 | chip->select_chip(mtd, -1); |
1da177e4 | 1862 | |
8593fbc6 | 1863 | ops->retlen = ops->len - (size_t) readlen; |
7014568b VW |
1864 | if (oob) |
1865 | ops->oobretlen = ops->ooblen - oobreadlen; | |
1da177e4 | 1866 | |
3f91e94f | 1867 | if (ret < 0) |
f5bbdacc TG |
1868 | return ret; |
1869 | ||
b72f3dfb | 1870 | if (ecc_fail) |
9a1fcdfd TG |
1871 | return -EBADMSG; |
1872 | ||
edbc4540 | 1873 | return max_bitflips; |
f5bbdacc TG |
1874 | } |
1875 | ||
1876 | /** | |
25985edc | 1877 | * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc |
8b6e50c9 BN |
1878 | * @mtd: MTD device structure |
1879 | * @from: offset to read from | |
1880 | * @len: number of bytes to read | |
1881 | * @retlen: pointer to variable to store the number of read bytes | |
1882 | * @buf: the databuffer to put data | |
f5bbdacc | 1883 | * |
8b6e50c9 | 1884 | * Get hold of the chip and call nand_do_read. |
f5bbdacc TG |
1885 | */ |
1886 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1887 | size_t *retlen, uint8_t *buf) | |
1888 | { | |
4a89ff88 | 1889 | struct mtd_oob_ops ops; |
f5bbdacc TG |
1890 | int ret; |
1891 | ||
6a8214aa | 1892 | nand_get_device(mtd, FL_READING); |
0ec56dc4 | 1893 | memset(&ops, 0, sizeof(ops)); |
4a89ff88 BN |
1894 | ops.len = len; |
1895 | ops.datbuf = buf; | |
11041ae6 | 1896 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 1897 | ret = nand_do_read_ops(mtd, from, &ops); |
4a89ff88 | 1898 | *retlen = ops.retlen; |
f5bbdacc | 1899 | nand_release_device(mtd); |
f5bbdacc | 1900 | return ret; |
1da177e4 LT |
1901 | } |
1902 | ||
7bc3312b | 1903 | /** |
7854d3f7 | 1904 | * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function |
8b6e50c9 BN |
1905 | * @mtd: mtd info structure |
1906 | * @chip: nand chip info structure | |
1907 | * @page: page number to read | |
7bc3312b TG |
1908 | */ |
1909 | static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
5c2ffb11 | 1910 | int page) |
7bc3312b | 1911 | { |
5c2ffb11 | 1912 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); |
7bc3312b | 1913 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
5c2ffb11 | 1914 | return 0; |
7bc3312b TG |
1915 | } |
1916 | ||
1917 | /** | |
7854d3f7 | 1918 | * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC |
7bc3312b | 1919 | * with syndromes |
8b6e50c9 BN |
1920 | * @mtd: mtd info structure |
1921 | * @chip: nand chip info structure | |
1922 | * @page: page number to read | |
7bc3312b TG |
1923 | */ |
1924 | static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
5c2ffb11 | 1925 | int page) |
7bc3312b | 1926 | { |
7bc3312b TG |
1927 | int length = mtd->oobsize; |
1928 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1929 | int eccsize = chip->ecc.size; | |
2ea69d21 | 1930 | uint8_t *bufpoi = chip->oob_poi; |
7bc3312b TG |
1931 | int i, toread, sndrnd = 0, pos; |
1932 | ||
1933 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); | |
1934 | for (i = 0; i < chip->ecc.steps; i++) { | |
1935 | if (sndrnd) { | |
1936 | pos = eccsize + i * (eccsize + chunk); | |
1937 | if (mtd->writesize > 512) | |
1938 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); | |
1939 | else | |
1940 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); | |
1941 | } else | |
1942 | sndrnd = 1; | |
1943 | toread = min_t(int, length, chunk); | |
1944 | chip->read_buf(mtd, bufpoi, toread); | |
1945 | bufpoi += toread; | |
1946 | length -= toread; | |
1947 | } | |
1948 | if (length > 0) | |
1949 | chip->read_buf(mtd, bufpoi, length); | |
1950 | ||
5c2ffb11 | 1951 | return 0; |
7bc3312b TG |
1952 | } |
1953 | ||
1954 | /** | |
7854d3f7 | 1955 | * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function |
8b6e50c9 BN |
1956 | * @mtd: mtd info structure |
1957 | * @chip: nand chip info structure | |
1958 | * @page: page number to write | |
7bc3312b TG |
1959 | */ |
1960 | static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1961 | int page) | |
1962 | { | |
1963 | int status = 0; | |
1964 | const uint8_t *buf = chip->oob_poi; | |
1965 | int length = mtd->oobsize; | |
1966 | ||
1967 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
1968 | chip->write_buf(mtd, buf, length); | |
1969 | /* Send command to program the OOB data */ | |
1970 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1971 | ||
1972 | status = chip->waitfunc(mtd, chip); | |
1973 | ||
0d420f9d | 1974 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
7bc3312b TG |
1975 | } |
1976 | ||
1977 | /** | |
7854d3f7 | 1978 | * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC |
8b6e50c9 BN |
1979 | * with syndrome - only for large page flash |
1980 | * @mtd: mtd info structure | |
1981 | * @chip: nand chip info structure | |
1982 | * @page: page number to write | |
7bc3312b TG |
1983 | */ |
1984 | static int nand_write_oob_syndrome(struct mtd_info *mtd, | |
1985 | struct nand_chip *chip, int page) | |
1986 | { | |
1987 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1988 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
1989 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; | |
1990 | const uint8_t *bufpoi = chip->oob_poi; | |
1991 | ||
1992 | /* | |
1993 | * data-ecc-data-ecc ... ecc-oob | |
1994 | * or | |
1995 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
1996 | */ | |
1997 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
1998 | pos = steps * (eccsize + chunk); | |
1999 | steps = 0; | |
2000 | } else | |
8b0036ee | 2001 | pos = eccsize; |
7bc3312b TG |
2002 | |
2003 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); | |
2004 | for (i = 0; i < steps; i++) { | |
2005 | if (sndcmd) { | |
2006 | if (mtd->writesize <= 512) { | |
2007 | uint32_t fill = 0xFFFFFFFF; | |
2008 | ||
2009 | len = eccsize; | |
2010 | while (len > 0) { | |
2011 | int num = min_t(int, len, 4); | |
2012 | chip->write_buf(mtd, (uint8_t *)&fill, | |
2013 | num); | |
2014 | len -= num; | |
2015 | } | |
2016 | } else { | |
2017 | pos = eccsize + i * (eccsize + chunk); | |
2018 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); | |
2019 | } | |
2020 | } else | |
2021 | sndcmd = 1; | |
2022 | len = min_t(int, length, chunk); | |
2023 | chip->write_buf(mtd, bufpoi, len); | |
2024 | bufpoi += len; | |
2025 | length -= len; | |
2026 | } | |
2027 | if (length > 0) | |
2028 | chip->write_buf(mtd, bufpoi, length); | |
2029 | ||
2030 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
2031 | status = chip->waitfunc(mtd, chip); | |
2032 | ||
2033 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
2034 | } | |
2035 | ||
1da177e4 | 2036 | /** |
7854d3f7 | 2037 | * nand_do_read_oob - [INTERN] NAND read out-of-band |
8b6e50c9 BN |
2038 | * @mtd: MTD device structure |
2039 | * @from: offset to read from | |
2040 | * @ops: oob operations description structure | |
1da177e4 | 2041 | * |
8b6e50c9 | 2042 | * NAND read out-of-band data from the spare area. |
1da177e4 | 2043 | */ |
8593fbc6 TG |
2044 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
2045 | struct mtd_oob_ops *ops) | |
1da177e4 | 2046 | { |
c00a0991 | 2047 | int page, realpage, chipnr; |
862eba51 | 2048 | struct nand_chip *chip = mtd_to_nand(mtd); |
041e4575 | 2049 | struct mtd_ecc_stats stats; |
7014568b VW |
2050 | int readlen = ops->ooblen; |
2051 | int len; | |
7bc3312b | 2052 | uint8_t *buf = ops->oobbuf; |
1951f2f7 | 2053 | int ret = 0; |
61b03bd7 | 2054 | |
289c0522 | 2055 | pr_debug("%s: from = 0x%08Lx, len = %i\n", |
20d8e248 | 2056 | __func__, (unsigned long long)from, readlen); |
1da177e4 | 2057 | |
041e4575 BN |
2058 | stats = mtd->ecc_stats; |
2059 | ||
29f1058a | 2060 | len = mtd_oobavail(mtd, ops); |
03736155 AH |
2061 | |
2062 | if (unlikely(ops->ooboffs >= len)) { | |
289c0522 BN |
2063 | pr_debug("%s: attempt to start read outside oob\n", |
2064 | __func__); | |
03736155 AH |
2065 | return -EINVAL; |
2066 | } | |
2067 | ||
2068 | /* Do not allow reads past end of device */ | |
2069 | if (unlikely(from >= mtd->size || | |
2070 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - | |
2071 | (from >> chip->page_shift)) * len)) { | |
289c0522 BN |
2072 | pr_debug("%s: attempt to read beyond end of device\n", |
2073 | __func__); | |
03736155 AH |
2074 | return -EINVAL; |
2075 | } | |
7014568b | 2076 | |
7314e9e7 | 2077 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 2078 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2079 | |
7314e9e7 TG |
2080 | /* Shift to get page */ |
2081 | realpage = (int)(from >> chip->page_shift); | |
2082 | page = realpage & chip->pagemask; | |
1da177e4 | 2083 | |
f8ac0414 | 2084 | while (1) { |
0612b9dd | 2085 | if (ops->mode == MTD_OPS_RAW) |
1951f2f7 | 2086 | ret = chip->ecc.read_oob_raw(mtd, chip, page); |
c46f6483 | 2087 | else |
1951f2f7 SL |
2088 | ret = chip->ecc.read_oob(mtd, chip, page); |
2089 | ||
2090 | if (ret < 0) | |
2091 | break; | |
7014568b VW |
2092 | |
2093 | len = min(len, readlen); | |
2094 | buf = nand_transfer_oob(chip, buf, ops, len); | |
8593fbc6 | 2095 | |
5bc7c33c BN |
2096 | if (chip->options & NAND_NEED_READRDY) { |
2097 | /* Apply delay or wait for ready/busy pin */ | |
2098 | if (!chip->dev_ready) | |
2099 | udelay(chip->chip_delay); | |
2100 | else | |
2101 | nand_wait_ready(mtd); | |
2102 | } | |
2103 | ||
7014568b | 2104 | readlen -= len; |
0d420f9d SZ |
2105 | if (!readlen) |
2106 | break; | |
2107 | ||
7314e9e7 TG |
2108 | /* Increment page address */ |
2109 | realpage++; | |
2110 | ||
2111 | page = realpage & chip->pagemask; | |
2112 | /* Check, if we cross a chip boundary */ | |
2113 | if (!page) { | |
2114 | chipnr++; | |
2115 | chip->select_chip(mtd, -1); | |
2116 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2117 | } |
2118 | } | |
b0bb6903 | 2119 | chip->select_chip(mtd, -1); |
1da177e4 | 2120 | |
1951f2f7 SL |
2121 | ops->oobretlen = ops->ooblen - readlen; |
2122 | ||
2123 | if (ret < 0) | |
2124 | return ret; | |
041e4575 BN |
2125 | |
2126 | if (mtd->ecc_stats.failed - stats.failed) | |
2127 | return -EBADMSG; | |
2128 | ||
2129 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
1da177e4 LT |
2130 | } |
2131 | ||
2132 | /** | |
8593fbc6 | 2133 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
8b6e50c9 BN |
2134 | * @mtd: MTD device structure |
2135 | * @from: offset to read from | |
2136 | * @ops: oob operation description structure | |
1da177e4 | 2137 | * |
8b6e50c9 | 2138 | * NAND read data and/or out-of-band data. |
1da177e4 | 2139 | */ |
8593fbc6 TG |
2140 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
2141 | struct mtd_oob_ops *ops) | |
1da177e4 | 2142 | { |
8593fbc6 TG |
2143 | int ret = -ENOTSUPP; |
2144 | ||
2145 | ops->retlen = 0; | |
1da177e4 LT |
2146 | |
2147 | /* Do not allow reads past end of device */ | |
7014568b | 2148 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
289c0522 BN |
2149 | pr_debug("%s: attempt to read beyond end of device\n", |
2150 | __func__); | |
1da177e4 LT |
2151 | return -EINVAL; |
2152 | } | |
2153 | ||
6a8214aa | 2154 | nand_get_device(mtd, FL_READING); |
1da177e4 | 2155 | |
f8ac0414 | 2156 | switch (ops->mode) { |
0612b9dd BN |
2157 | case MTD_OPS_PLACE_OOB: |
2158 | case MTD_OPS_AUTO_OOB: | |
2159 | case MTD_OPS_RAW: | |
8593fbc6 | 2160 | break; |
1da177e4 | 2161 | |
8593fbc6 TG |
2162 | default: |
2163 | goto out; | |
2164 | } | |
1da177e4 | 2165 | |
8593fbc6 TG |
2166 | if (!ops->datbuf) |
2167 | ret = nand_do_read_oob(mtd, from, ops); | |
2168 | else | |
2169 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 2170 | |
7351d3a5 | 2171 | out: |
8593fbc6 TG |
2172 | nand_release_device(mtd); |
2173 | return ret; | |
2174 | } | |
61b03bd7 | 2175 | |
1da177e4 | 2176 | |
8593fbc6 | 2177 | /** |
7854d3f7 | 2178 | * nand_write_page_raw - [INTERN] raw page write function |
8b6e50c9 BN |
2179 | * @mtd: mtd info structure |
2180 | * @chip: nand chip info structure | |
2181 | * @buf: data buffer | |
1fbb938d | 2182 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2183 | * @page: page number to write |
52ff49df | 2184 | * |
7854d3f7 | 2185 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 | 2186 | */ |
fdbad98d | 2187 | static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 | 2188 | const uint8_t *buf, int oob_required, int page) |
8593fbc6 TG |
2189 | { |
2190 | chip->write_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
2191 | if (oob_required) |
2192 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
2193 | |
2194 | return 0; | |
1da177e4 LT |
2195 | } |
2196 | ||
52ff49df | 2197 | /** |
7854d3f7 | 2198 | * nand_write_page_raw_syndrome - [INTERN] raw page write function |
8b6e50c9 BN |
2199 | * @mtd: mtd info structure |
2200 | * @chip: nand chip info structure | |
2201 | * @buf: data buffer | |
1fbb938d | 2202 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2203 | * @page: page number to write |
52ff49df DB |
2204 | * |
2205 | * We need a special oob layout and handling even when ECC isn't checked. | |
2206 | */ | |
fdbad98d | 2207 | static int nand_write_page_raw_syndrome(struct mtd_info *mtd, |
7351d3a5 | 2208 | struct nand_chip *chip, |
45aaeff9 BB |
2209 | const uint8_t *buf, int oob_required, |
2210 | int page) | |
52ff49df DB |
2211 | { |
2212 | int eccsize = chip->ecc.size; | |
2213 | int eccbytes = chip->ecc.bytes; | |
2214 | uint8_t *oob = chip->oob_poi; | |
2215 | int steps, size; | |
2216 | ||
2217 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
2218 | chip->write_buf(mtd, buf, eccsize); | |
2219 | buf += eccsize; | |
2220 | ||
2221 | if (chip->ecc.prepad) { | |
2222 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2223 | oob += chip->ecc.prepad; | |
2224 | } | |
2225 | ||
60c3bc1f | 2226 | chip->write_buf(mtd, oob, eccbytes); |
52ff49df DB |
2227 | oob += eccbytes; |
2228 | ||
2229 | if (chip->ecc.postpad) { | |
2230 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2231 | oob += chip->ecc.postpad; | |
2232 | } | |
2233 | } | |
2234 | ||
2235 | size = mtd->oobsize - (oob - chip->oob_poi); | |
2236 | if (size) | |
2237 | chip->write_buf(mtd, oob, size); | |
fdbad98d JW |
2238 | |
2239 | return 0; | |
52ff49df | 2240 | } |
9223a456 | 2241 | /** |
7854d3f7 | 2242 | * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function |
8b6e50c9 BN |
2243 | * @mtd: mtd info structure |
2244 | * @chip: nand chip info structure | |
2245 | * @buf: data buffer | |
1fbb938d | 2246 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2247 | * @page: page number to write |
9223a456 | 2248 | */ |
fdbad98d | 2249 | static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 BB |
2250 | const uint8_t *buf, int oob_required, |
2251 | int page) | |
9223a456 | 2252 | { |
f75e5097 TG |
2253 | int i, eccsize = chip->ecc.size; |
2254 | int eccbytes = chip->ecc.bytes; | |
2255 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2256 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2257 | const uint8_t *p = buf; |
8b099a39 | 2258 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 2259 | |
7854d3f7 | 2260 | /* Software ECC calculation */ |
8593fbc6 TG |
2261 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) |
2262 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 2263 | |
8593fbc6 TG |
2264 | for (i = 0; i < chip->ecc.total; i++) |
2265 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
9223a456 | 2266 | |
45aaeff9 | 2267 | return chip->ecc.write_page_raw(mtd, chip, buf, 1, page); |
f75e5097 | 2268 | } |
9223a456 | 2269 | |
f75e5097 | 2270 | /** |
7854d3f7 | 2271 | * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function |
8b6e50c9 BN |
2272 | * @mtd: mtd info structure |
2273 | * @chip: nand chip info structure | |
2274 | * @buf: data buffer | |
1fbb938d | 2275 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2276 | * @page: page number to write |
f75e5097 | 2277 | */ |
fdbad98d | 2278 | static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 BB |
2279 | const uint8_t *buf, int oob_required, |
2280 | int page) | |
f75e5097 TG |
2281 | { |
2282 | int i, eccsize = chip->ecc.size; | |
2283 | int eccbytes = chip->ecc.bytes; | |
2284 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2285 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2286 | const uint8_t *p = buf; |
8b099a39 | 2287 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 2288 | |
f75e5097 TG |
2289 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
2290 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 2291 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 2292 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
2293 | } |
2294 | ||
f75e5097 TG |
2295 | for (i = 0; i < chip->ecc.total; i++) |
2296 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
2297 | ||
2298 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
2299 | |
2300 | return 0; | |
9223a456 TG |
2301 | } |
2302 | ||
837a6ba4 GP |
2303 | |
2304 | /** | |
73c8aaf4 | 2305 | * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write |
837a6ba4 GP |
2306 | * @mtd: mtd info structure |
2307 | * @chip: nand chip info structure | |
d6a95080 | 2308 | * @offset: column address of subpage within the page |
837a6ba4 | 2309 | * @data_len: data length |
d6a95080 | 2310 | * @buf: data buffer |
837a6ba4 | 2311 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2312 | * @page: page number to write |
837a6ba4 GP |
2313 | */ |
2314 | static int nand_write_subpage_hwecc(struct mtd_info *mtd, | |
2315 | struct nand_chip *chip, uint32_t offset, | |
d6a95080 | 2316 | uint32_t data_len, const uint8_t *buf, |
45aaeff9 | 2317 | int oob_required, int page) |
837a6ba4 GP |
2318 | { |
2319 | uint8_t *oob_buf = chip->oob_poi; | |
2320 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
2321 | int ecc_size = chip->ecc.size; | |
2322 | int ecc_bytes = chip->ecc.bytes; | |
2323 | int ecc_steps = chip->ecc.steps; | |
2324 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
2325 | uint32_t start_step = offset / ecc_size; | |
2326 | uint32_t end_step = (offset + data_len - 1) / ecc_size; | |
2327 | int oob_bytes = mtd->oobsize / ecc_steps; | |
2328 | int step, i; | |
2329 | ||
2330 | for (step = 0; step < ecc_steps; step++) { | |
2331 | /* configure controller for WRITE access */ | |
2332 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
2333 | ||
2334 | /* write data (untouched subpages already masked by 0xFF) */ | |
d6a95080 | 2335 | chip->write_buf(mtd, buf, ecc_size); |
837a6ba4 GP |
2336 | |
2337 | /* mask ECC of un-touched subpages by padding 0xFF */ | |
2338 | if ((step < start_step) || (step > end_step)) | |
2339 | memset(ecc_calc, 0xff, ecc_bytes); | |
2340 | else | |
d6a95080 | 2341 | chip->ecc.calculate(mtd, buf, ecc_calc); |
837a6ba4 GP |
2342 | |
2343 | /* mask OOB of un-touched subpages by padding 0xFF */ | |
2344 | /* if oob_required, preserve OOB metadata of written subpage */ | |
2345 | if (!oob_required || (step < start_step) || (step > end_step)) | |
2346 | memset(oob_buf, 0xff, oob_bytes); | |
2347 | ||
d6a95080 | 2348 | buf += ecc_size; |
837a6ba4 GP |
2349 | ecc_calc += ecc_bytes; |
2350 | oob_buf += oob_bytes; | |
2351 | } | |
2352 | ||
2353 | /* copy calculated ECC for whole page to chip->buffer->oob */ | |
2354 | /* this include masked-value(0xFF) for unwritten subpages */ | |
2355 | ecc_calc = chip->buffers->ecccalc; | |
2356 | for (i = 0; i < chip->ecc.total; i++) | |
2357 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
2358 | ||
2359 | /* write OOB buffer to NAND device */ | |
2360 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
2361 | ||
2362 | return 0; | |
2363 | } | |
2364 | ||
2365 | ||
61b03bd7 | 2366 | /** |
7854d3f7 | 2367 | * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write |
8b6e50c9 BN |
2368 | * @mtd: mtd info structure |
2369 | * @chip: nand chip info structure | |
2370 | * @buf: data buffer | |
1fbb938d | 2371 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2372 | * @page: page number to write |
1da177e4 | 2373 | * |
8b6e50c9 BN |
2374 | * The hw generator calculates the error syndrome automatically. Therefore we |
2375 | * need a special oob layout and handling. | |
f75e5097 | 2376 | */ |
fdbad98d | 2377 | static int nand_write_page_syndrome(struct mtd_info *mtd, |
1fbb938d | 2378 | struct nand_chip *chip, |
45aaeff9 BB |
2379 | const uint8_t *buf, int oob_required, |
2380 | int page) | |
1da177e4 | 2381 | { |
f75e5097 TG |
2382 | int i, eccsize = chip->ecc.size; |
2383 | int eccbytes = chip->ecc.bytes; | |
2384 | int eccsteps = chip->ecc.steps; | |
2385 | const uint8_t *p = buf; | |
2386 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 2387 | |
f75e5097 | 2388 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 2389 | |
f75e5097 TG |
2390 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
2391 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 2392 | |
f75e5097 TG |
2393 | if (chip->ecc.prepad) { |
2394 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2395 | oob += chip->ecc.prepad; | |
2396 | } | |
2397 | ||
2398 | chip->ecc.calculate(mtd, p, oob); | |
2399 | chip->write_buf(mtd, oob, eccbytes); | |
2400 | oob += eccbytes; | |
2401 | ||
2402 | if (chip->ecc.postpad) { | |
2403 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2404 | oob += chip->ecc.postpad; | |
1da177e4 | 2405 | } |
1da177e4 | 2406 | } |
f75e5097 TG |
2407 | |
2408 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 2409 | i = mtd->oobsize - (oob - chip->oob_poi); |
f75e5097 TG |
2410 | if (i) |
2411 | chip->write_buf(mtd, oob, i); | |
fdbad98d JW |
2412 | |
2413 | return 0; | |
f75e5097 TG |
2414 | } |
2415 | ||
2416 | /** | |
956e944c | 2417 | * nand_write_page - [REPLACEABLE] write one page |
8b6e50c9 BN |
2418 | * @mtd: MTD device structure |
2419 | * @chip: NAND chip descriptor | |
837a6ba4 GP |
2420 | * @offset: address offset within the page |
2421 | * @data_len: length of actual data to be written | |
8b6e50c9 | 2422 | * @buf: the data to write |
1fbb938d | 2423 | * @oob_required: must write chip->oob_poi to OOB |
8b6e50c9 BN |
2424 | * @page: page number to write |
2425 | * @cached: cached programming | |
2426 | * @raw: use _raw version of write_page | |
f75e5097 TG |
2427 | */ |
2428 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
837a6ba4 GP |
2429 | uint32_t offset, int data_len, const uint8_t *buf, |
2430 | int oob_required, int page, int cached, int raw) | |
f75e5097 | 2431 | { |
837a6ba4 GP |
2432 | int status, subpage; |
2433 | ||
2434 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && | |
2435 | chip->ecc.write_subpage) | |
2436 | subpage = offset || (data_len < mtd->writesize); | |
2437 | else | |
2438 | subpage = 0; | |
f75e5097 TG |
2439 | |
2440 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
2441 | ||
956e944c | 2442 | if (unlikely(raw)) |
837a6ba4 | 2443 | status = chip->ecc.write_page_raw(mtd, chip, buf, |
45aaeff9 | 2444 | oob_required, page); |
837a6ba4 GP |
2445 | else if (subpage) |
2446 | status = chip->ecc.write_subpage(mtd, chip, offset, data_len, | |
45aaeff9 | 2447 | buf, oob_required, page); |
956e944c | 2448 | else |
45aaeff9 BB |
2449 | status = chip->ecc.write_page(mtd, chip, buf, oob_required, |
2450 | page); | |
fdbad98d JW |
2451 | |
2452 | if (status < 0) | |
2453 | return status; | |
f75e5097 TG |
2454 | |
2455 | /* | |
7854d3f7 | 2456 | * Cached progamming disabled for now. Not sure if it's worth the |
8b6e50c9 | 2457 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s). |
f75e5097 TG |
2458 | */ |
2459 | cached = 0; | |
2460 | ||
3239a6cd | 2461 | if (!cached || !NAND_HAS_CACHEPROG(chip)) { |
f75e5097 TG |
2462 | |
2463 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
7bc3312b | 2464 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2465 | /* |
2466 | * See if operation failed and additional status checks are | |
8b6e50c9 | 2467 | * available. |
f75e5097 TG |
2468 | */ |
2469 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2470 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
2471 | page); | |
2472 | ||
2473 | if (status & NAND_STATUS_FAIL) | |
2474 | return -EIO; | |
2475 | } else { | |
2476 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
7bc3312b | 2477 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2478 | } |
2479 | ||
f75e5097 | 2480 | return 0; |
1da177e4 LT |
2481 | } |
2482 | ||
8593fbc6 | 2483 | /** |
7854d3f7 | 2484 | * nand_fill_oob - [INTERN] Transfer client buffer to oob |
f722013e | 2485 | * @mtd: MTD device structure |
8b6e50c9 BN |
2486 | * @oob: oob data buffer |
2487 | * @len: oob data write length | |
2488 | * @ops: oob ops structure | |
8593fbc6 | 2489 | */ |
f722013e TAA |
2490 | static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, |
2491 | struct mtd_oob_ops *ops) | |
8593fbc6 | 2492 | { |
862eba51 | 2493 | struct nand_chip *chip = mtd_to_nand(mtd); |
f722013e TAA |
2494 | |
2495 | /* | |
2496 | * Initialise to all 0xFF, to avoid the possibility of left over OOB | |
2497 | * data from a previous OOB read. | |
2498 | */ | |
2499 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
2500 | ||
f8ac0414 | 2501 | switch (ops->mode) { |
8593fbc6 | 2502 | |
0612b9dd BN |
2503 | case MTD_OPS_PLACE_OOB: |
2504 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2505 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); |
2506 | return oob + len; | |
2507 | ||
0612b9dd | 2508 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 2509 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
2510 | uint32_t boffs = 0, woffs = ops->ooboffs; |
2511 | size_t bytes = 0; | |
8593fbc6 | 2512 | |
f8ac0414 | 2513 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 2514 | /* Write request not from offset 0? */ |
7bc3312b TG |
2515 | if (unlikely(woffs)) { |
2516 | if (woffs >= free->length) { | |
2517 | woffs -= free->length; | |
2518 | continue; | |
2519 | } | |
2520 | boffs = free->offset + woffs; | |
2521 | bytes = min_t(size_t, len, | |
2522 | (free->length - woffs)); | |
2523 | woffs = 0; | |
2524 | } else { | |
2525 | bytes = min_t(size_t, len, free->length); | |
2526 | boffs = free->offset; | |
2527 | } | |
8b0036ee | 2528 | memcpy(chip->oob_poi + boffs, oob, bytes); |
8593fbc6 TG |
2529 | oob += bytes; |
2530 | } | |
2531 | return oob; | |
2532 | } | |
2533 | default: | |
2534 | BUG(); | |
2535 | } | |
2536 | return NULL; | |
2537 | } | |
2538 | ||
f8ac0414 | 2539 | #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) |
1da177e4 LT |
2540 | |
2541 | /** | |
7854d3f7 | 2542 | * nand_do_write_ops - [INTERN] NAND write with ECC |
8b6e50c9 BN |
2543 | * @mtd: MTD device structure |
2544 | * @to: offset to write to | |
2545 | * @ops: oob operations description structure | |
1da177e4 | 2546 | * |
8b6e50c9 | 2547 | * NAND write with ECC. |
1da177e4 | 2548 | */ |
8593fbc6 TG |
2549 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
2550 | struct mtd_oob_ops *ops) | |
1da177e4 | 2551 | { |
29072b96 | 2552 | int chipnr, realpage, page, blockmask, column; |
862eba51 | 2553 | struct nand_chip *chip = mtd_to_nand(mtd); |
8593fbc6 | 2554 | uint32_t writelen = ops->len; |
782ce79a ML |
2555 | |
2556 | uint32_t oobwritelen = ops->ooblen; | |
29f1058a | 2557 | uint32_t oobmaxlen = mtd_oobavail(mtd, ops); |
782ce79a | 2558 | |
8593fbc6 TG |
2559 | uint8_t *oob = ops->oobbuf; |
2560 | uint8_t *buf = ops->datbuf; | |
837a6ba4 | 2561 | int ret; |
e47f3db4 | 2562 | int oob_required = oob ? 1 : 0; |
1da177e4 | 2563 | |
8593fbc6 | 2564 | ops->retlen = 0; |
29072b96 TG |
2565 | if (!writelen) |
2566 | return 0; | |
1da177e4 | 2567 | |
8b6e50c9 | 2568 | /* Reject writes, which are not page aligned */ |
8593fbc6 | 2569 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
d0370219 BN |
2570 | pr_notice("%s: attempt to write non page aligned data\n", |
2571 | __func__); | |
1da177e4 LT |
2572 | return -EINVAL; |
2573 | } | |
2574 | ||
29072b96 | 2575 | column = to & (mtd->writesize - 1); |
1da177e4 | 2576 | |
6a930961 TG |
2577 | chipnr = (int)(to >> chip->chip_shift); |
2578 | chip->select_chip(mtd, chipnr); | |
2579 | ||
1da177e4 | 2580 | /* Check, if it is write protected */ |
b0bb6903 HS |
2581 | if (nand_check_wp(mtd)) { |
2582 | ret = -EIO; | |
2583 | goto err_out; | |
2584 | } | |
1da177e4 | 2585 | |
f75e5097 TG |
2586 | realpage = (int)(to >> chip->page_shift); |
2587 | page = realpage & chip->pagemask; | |
2588 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
2589 | ||
2590 | /* Invalidate the page cache, when we write to the cached page */ | |
537ab1bd BN |
2591 | if (to <= ((loff_t)chip->pagebuf << chip->page_shift) && |
2592 | ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len)) | |
ace4dfee | 2593 | chip->pagebuf = -1; |
61b03bd7 | 2594 | |
782ce79a | 2595 | /* Don't allow multipage oob writes with offset */ |
b0bb6903 HS |
2596 | if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { |
2597 | ret = -EINVAL; | |
2598 | goto err_out; | |
2599 | } | |
782ce79a | 2600 | |
f8ac0414 | 2601 | while (1) { |
29072b96 | 2602 | int bytes = mtd->writesize; |
f75e5097 | 2603 | int cached = writelen > bytes && page != blockmask; |
29072b96 | 2604 | uint8_t *wbuf = buf; |
66507c7b KD |
2605 | int use_bufpoi; |
2606 | int part_pagewr = (column || writelen < (mtd->writesize - 1)); | |
2607 | ||
2608 | if (part_pagewr) | |
2609 | use_bufpoi = 1; | |
2610 | else if (chip->options & NAND_USE_BOUNCE_BUFFER) | |
2611 | use_bufpoi = !virt_addr_valid(buf); | |
2612 | else | |
2613 | use_bufpoi = 0; | |
29072b96 | 2614 | |
66507c7b KD |
2615 | /* Partial page write?, or need to use bounce buffer */ |
2616 | if (use_bufpoi) { | |
2617 | pr_debug("%s: using write bounce buffer for buf@%p\n", | |
2618 | __func__, buf); | |
29072b96 | 2619 | cached = 0; |
66507c7b KD |
2620 | if (part_pagewr) |
2621 | bytes = min_t(int, bytes - column, writelen); | |
29072b96 TG |
2622 | chip->pagebuf = -1; |
2623 | memset(chip->buffers->databuf, 0xff, mtd->writesize); | |
2624 | memcpy(&chip->buffers->databuf[column], buf, bytes); | |
2625 | wbuf = chip->buffers->databuf; | |
2626 | } | |
1da177e4 | 2627 | |
782ce79a ML |
2628 | if (unlikely(oob)) { |
2629 | size_t len = min(oobwritelen, oobmaxlen); | |
f722013e | 2630 | oob = nand_fill_oob(mtd, oob, len, ops); |
782ce79a | 2631 | oobwritelen -= len; |
f722013e TAA |
2632 | } else { |
2633 | /* We still need to erase leftover OOB data */ | |
2634 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
782ce79a | 2635 | } |
837a6ba4 GP |
2636 | ret = chip->write_page(mtd, chip, column, bytes, wbuf, |
2637 | oob_required, page, cached, | |
2638 | (ops->mode == MTD_OPS_RAW)); | |
f75e5097 TG |
2639 | if (ret) |
2640 | break; | |
2641 | ||
2642 | writelen -= bytes; | |
2643 | if (!writelen) | |
2644 | break; | |
2645 | ||
29072b96 | 2646 | column = 0; |
f75e5097 TG |
2647 | buf += bytes; |
2648 | realpage++; | |
2649 | ||
2650 | page = realpage & chip->pagemask; | |
2651 | /* Check, if we cross a chip boundary */ | |
2652 | if (!page) { | |
2653 | chipnr++; | |
2654 | chip->select_chip(mtd, -1); | |
2655 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2656 | } |
2657 | } | |
8593fbc6 | 2658 | |
8593fbc6 | 2659 | ops->retlen = ops->len - writelen; |
7014568b VW |
2660 | if (unlikely(oob)) |
2661 | ops->oobretlen = ops->ooblen; | |
b0bb6903 HS |
2662 | |
2663 | err_out: | |
2664 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
2665 | return ret; |
2666 | } | |
2667 | ||
2af7c653 SK |
2668 | /** |
2669 | * panic_nand_write - [MTD Interface] NAND write with ECC | |
8b6e50c9 BN |
2670 | * @mtd: MTD device structure |
2671 | * @to: offset to write to | |
2672 | * @len: number of bytes to write | |
2673 | * @retlen: pointer to variable to store the number of written bytes | |
2674 | * @buf: the data to write | |
2af7c653 SK |
2675 | * |
2676 | * NAND write with ECC. Used when performing writes in interrupt context, this | |
2677 | * may for example be called by mtdoops when writing an oops while in panic. | |
2678 | */ | |
2679 | static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, | |
2680 | size_t *retlen, const uint8_t *buf) | |
2681 | { | |
862eba51 | 2682 | struct nand_chip *chip = mtd_to_nand(mtd); |
4a89ff88 | 2683 | struct mtd_oob_ops ops; |
2af7c653 SK |
2684 | int ret; |
2685 | ||
8b6e50c9 | 2686 | /* Wait for the device to get ready */ |
2af7c653 SK |
2687 | panic_nand_wait(mtd, chip, 400); |
2688 | ||
8b6e50c9 | 2689 | /* Grab the device */ |
2af7c653 SK |
2690 | panic_nand_get_device(chip, mtd, FL_WRITING); |
2691 | ||
0ec56dc4 | 2692 | memset(&ops, 0, sizeof(ops)); |
4a89ff88 BN |
2693 | ops.len = len; |
2694 | ops.datbuf = (uint8_t *)buf; | |
11041ae6 | 2695 | ops.mode = MTD_OPS_PLACE_OOB; |
2af7c653 | 2696 | |
4a89ff88 | 2697 | ret = nand_do_write_ops(mtd, to, &ops); |
2af7c653 | 2698 | |
4a89ff88 | 2699 | *retlen = ops.retlen; |
2af7c653 SK |
2700 | return ret; |
2701 | } | |
2702 | ||
f75e5097 | 2703 | /** |
8593fbc6 | 2704 | * nand_write - [MTD Interface] NAND write with ECC |
8b6e50c9 BN |
2705 | * @mtd: MTD device structure |
2706 | * @to: offset to write to | |
2707 | * @len: number of bytes to write | |
2708 | * @retlen: pointer to variable to store the number of written bytes | |
2709 | * @buf: the data to write | |
f75e5097 | 2710 | * |
8b6e50c9 | 2711 | * NAND write with ECC. |
f75e5097 | 2712 | */ |
8593fbc6 TG |
2713 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
2714 | size_t *retlen, const uint8_t *buf) | |
f75e5097 | 2715 | { |
4a89ff88 | 2716 | struct mtd_oob_ops ops; |
f75e5097 TG |
2717 | int ret; |
2718 | ||
6a8214aa | 2719 | nand_get_device(mtd, FL_WRITING); |
0ec56dc4 | 2720 | memset(&ops, 0, sizeof(ops)); |
4a89ff88 BN |
2721 | ops.len = len; |
2722 | ops.datbuf = (uint8_t *)buf; | |
11041ae6 | 2723 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 2724 | ret = nand_do_write_ops(mtd, to, &ops); |
4a89ff88 | 2725 | *retlen = ops.retlen; |
f75e5097 | 2726 | nand_release_device(mtd); |
8593fbc6 | 2727 | return ret; |
f75e5097 | 2728 | } |
7314e9e7 | 2729 | |
1da177e4 | 2730 | /** |
8593fbc6 | 2731 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
8b6e50c9 BN |
2732 | * @mtd: MTD device structure |
2733 | * @to: offset to write to | |
2734 | * @ops: oob operation description structure | |
1da177e4 | 2735 | * |
8b6e50c9 | 2736 | * NAND write out-of-band. |
1da177e4 | 2737 | */ |
8593fbc6 TG |
2738 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
2739 | struct mtd_oob_ops *ops) | |
1da177e4 | 2740 | { |
03736155 | 2741 | int chipnr, page, status, len; |
862eba51 | 2742 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 2743 | |
289c0522 | 2744 | pr_debug("%s: to = 0x%08x, len = %i\n", |
20d8e248 | 2745 | __func__, (unsigned int)to, (int)ops->ooblen); |
1da177e4 | 2746 | |
29f1058a | 2747 | len = mtd_oobavail(mtd, ops); |
03736155 | 2748 | |
1da177e4 | 2749 | /* Do not allow write past end of page */ |
03736155 | 2750 | if ((ops->ooboffs + ops->ooblen) > len) { |
289c0522 BN |
2751 | pr_debug("%s: attempt to write past end of page\n", |
2752 | __func__); | |
1da177e4 LT |
2753 | return -EINVAL; |
2754 | } | |
2755 | ||
03736155 | 2756 | if (unlikely(ops->ooboffs >= len)) { |
289c0522 BN |
2757 | pr_debug("%s: attempt to start write outside oob\n", |
2758 | __func__); | |
03736155 AH |
2759 | return -EINVAL; |
2760 | } | |
2761 | ||
775adc3d | 2762 | /* Do not allow write past end of device */ |
03736155 AH |
2763 | if (unlikely(to >= mtd->size || |
2764 | ops->ooboffs + ops->ooblen > | |
2765 | ((mtd->size >> chip->page_shift) - | |
2766 | (to >> chip->page_shift)) * len)) { | |
289c0522 BN |
2767 | pr_debug("%s: attempt to write beyond end of device\n", |
2768 | __func__); | |
03736155 AH |
2769 | return -EINVAL; |
2770 | } | |
2771 | ||
7314e9e7 | 2772 | chipnr = (int)(to >> chip->chip_shift); |
ace4dfee | 2773 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2774 | |
7314e9e7 TG |
2775 | /* Shift to get page */ |
2776 | page = (int)(to >> chip->page_shift); | |
2777 | ||
2778 | /* | |
2779 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
2780 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
2781 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
2782 | * it in the doc2000 driver in August 1999. dwmw2. | |
2783 | */ | |
ace4dfee | 2784 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
1da177e4 LT |
2785 | |
2786 | /* Check, if it is write protected */ | |
b0bb6903 HS |
2787 | if (nand_check_wp(mtd)) { |
2788 | chip->select_chip(mtd, -1); | |
8593fbc6 | 2789 | return -EROFS; |
b0bb6903 | 2790 | } |
61b03bd7 | 2791 | |
1da177e4 | 2792 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
2793 | if (page == chip->pagebuf) |
2794 | chip->pagebuf = -1; | |
1da177e4 | 2795 | |
f722013e | 2796 | nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops); |
9ce244b3 | 2797 | |
0612b9dd | 2798 | if (ops->mode == MTD_OPS_RAW) |
9ce244b3 BN |
2799 | status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask); |
2800 | else | |
2801 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); | |
1da177e4 | 2802 | |
b0bb6903 HS |
2803 | chip->select_chip(mtd, -1); |
2804 | ||
7bc3312b TG |
2805 | if (status) |
2806 | return status; | |
1da177e4 | 2807 | |
7014568b | 2808 | ops->oobretlen = ops->ooblen; |
1da177e4 | 2809 | |
7bc3312b | 2810 | return 0; |
8593fbc6 TG |
2811 | } |
2812 | ||
2813 | /** | |
2814 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
8b6e50c9 BN |
2815 | * @mtd: MTD device structure |
2816 | * @to: offset to write to | |
2817 | * @ops: oob operation description structure | |
8593fbc6 TG |
2818 | */ |
2819 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
2820 | struct mtd_oob_ops *ops) | |
2821 | { | |
8593fbc6 TG |
2822 | int ret = -ENOTSUPP; |
2823 | ||
2824 | ops->retlen = 0; | |
2825 | ||
2826 | /* Do not allow writes past end of device */ | |
7014568b | 2827 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
289c0522 BN |
2828 | pr_debug("%s: attempt to write beyond end of device\n", |
2829 | __func__); | |
8593fbc6 TG |
2830 | return -EINVAL; |
2831 | } | |
2832 | ||
6a8214aa | 2833 | nand_get_device(mtd, FL_WRITING); |
8593fbc6 | 2834 | |
f8ac0414 | 2835 | switch (ops->mode) { |
0612b9dd BN |
2836 | case MTD_OPS_PLACE_OOB: |
2837 | case MTD_OPS_AUTO_OOB: | |
2838 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2839 | break; |
2840 | ||
2841 | default: | |
2842 | goto out; | |
2843 | } | |
2844 | ||
2845 | if (!ops->datbuf) | |
2846 | ret = nand_do_write_oob(mtd, to, ops); | |
2847 | else | |
2848 | ret = nand_do_write_ops(mtd, to, ops); | |
2849 | ||
7351d3a5 | 2850 | out: |
1da177e4 | 2851 | nand_release_device(mtd); |
1da177e4 LT |
2852 | return ret; |
2853 | } | |
2854 | ||
1da177e4 | 2855 | /** |
49c50b97 | 2856 | * single_erase - [GENERIC] NAND standard block erase command function |
8b6e50c9 BN |
2857 | * @mtd: MTD device structure |
2858 | * @page: the page address of the block which will be erased | |
1da177e4 | 2859 | * |
49c50b97 | 2860 | * Standard erase command for NAND chips. Returns NAND status. |
1da177e4 | 2861 | */ |
49c50b97 | 2862 | static int single_erase(struct mtd_info *mtd, int page) |
1da177e4 | 2863 | { |
862eba51 | 2864 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 2865 | /* Send commands to erase a block */ |
ace4dfee TG |
2866 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
2867 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
49c50b97 BN |
2868 | |
2869 | return chip->waitfunc(mtd, chip); | |
1da177e4 LT |
2870 | } |
2871 | ||
1da177e4 LT |
2872 | /** |
2873 | * nand_erase - [MTD Interface] erase block(s) | |
8b6e50c9 BN |
2874 | * @mtd: MTD device structure |
2875 | * @instr: erase instruction | |
1da177e4 | 2876 | * |
8b6e50c9 | 2877 | * Erase one ore more blocks. |
1da177e4 | 2878 | */ |
e0c7d767 | 2879 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 2880 | { |
e0c7d767 | 2881 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 2882 | } |
61b03bd7 | 2883 | |
1da177e4 | 2884 | /** |
7854d3f7 | 2885 | * nand_erase_nand - [INTERN] erase block(s) |
8b6e50c9 BN |
2886 | * @mtd: MTD device structure |
2887 | * @instr: erase instruction | |
2888 | * @allowbbt: allow erasing the bbt area | |
1da177e4 | 2889 | * |
8b6e50c9 | 2890 | * Erase one ore more blocks. |
1da177e4 | 2891 | */ |
ace4dfee TG |
2892 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
2893 | int allowbbt) | |
1da177e4 | 2894 | { |
69423d99 | 2895 | int page, status, pages_per_block, ret, chipnr; |
862eba51 | 2896 | struct nand_chip *chip = mtd_to_nand(mtd); |
69423d99 | 2897 | loff_t len; |
1da177e4 | 2898 | |
289c0522 BN |
2899 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
2900 | __func__, (unsigned long long)instr->addr, | |
2901 | (unsigned long long)instr->len); | |
1da177e4 | 2902 | |
6fe5a6ac | 2903 | if (check_offs_len(mtd, instr->addr, instr->len)) |
1da177e4 | 2904 | return -EINVAL; |
1da177e4 | 2905 | |
1da177e4 | 2906 | /* Grab the lock and see if the device is available */ |
6a8214aa | 2907 | nand_get_device(mtd, FL_ERASING); |
1da177e4 LT |
2908 | |
2909 | /* Shift to get first page */ | |
ace4dfee TG |
2910 | page = (int)(instr->addr >> chip->page_shift); |
2911 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
2912 | |
2913 | /* Calculate pages in each block */ | |
ace4dfee | 2914 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
2915 | |
2916 | /* Select the NAND device */ | |
ace4dfee | 2917 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2918 | |
1da177e4 LT |
2919 | /* Check, if it is write protected */ |
2920 | if (nand_check_wp(mtd)) { | |
289c0522 BN |
2921 | pr_debug("%s: device is write protected!\n", |
2922 | __func__); | |
1da177e4 LT |
2923 | instr->state = MTD_ERASE_FAILED; |
2924 | goto erase_exit; | |
2925 | } | |
2926 | ||
2927 | /* Loop through the pages */ | |
2928 | len = instr->len; | |
2929 | ||
2930 | instr->state = MTD_ERASING; | |
2931 | ||
2932 | while (len) { | |
12183a20 | 2933 | /* Check if we have a bad block, we do not erase bad blocks! */ |
ace4dfee | 2934 | if (nand_block_checkbad(mtd, ((loff_t) page) << |
9f3e0429 | 2935 | chip->page_shift, allowbbt)) { |
d0370219 BN |
2936 | pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", |
2937 | __func__, page); | |
1da177e4 LT |
2938 | instr->state = MTD_ERASE_FAILED; |
2939 | goto erase_exit; | |
2940 | } | |
61b03bd7 | 2941 | |
ace4dfee TG |
2942 | /* |
2943 | * Invalidate the page cache, if we erase the block which | |
8b6e50c9 | 2944 | * contains the current cached page. |
ace4dfee TG |
2945 | */ |
2946 | if (page <= chip->pagebuf && chip->pagebuf < | |
2947 | (page + pages_per_block)) | |
2948 | chip->pagebuf = -1; | |
1da177e4 | 2949 | |
49c50b97 | 2950 | status = chip->erase(mtd, page & chip->pagemask); |
1da177e4 | 2951 | |
ace4dfee TG |
2952 | /* |
2953 | * See if operation failed and additional status checks are | |
2954 | * available | |
2955 | */ | |
2956 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2957 | status = chip->errstat(mtd, chip, FL_ERASING, | |
2958 | status, page); | |
068e3c0a | 2959 | |
1da177e4 | 2960 | /* See if block erase succeeded */ |
a4ab4c5d | 2961 | if (status & NAND_STATUS_FAIL) { |
289c0522 BN |
2962 | pr_debug("%s: failed erase, page 0x%08x\n", |
2963 | __func__, page); | |
1da177e4 | 2964 | instr->state = MTD_ERASE_FAILED; |
69423d99 AH |
2965 | instr->fail_addr = |
2966 | ((loff_t)page << chip->page_shift); | |
1da177e4 LT |
2967 | goto erase_exit; |
2968 | } | |
30f464b7 | 2969 | |
1da177e4 | 2970 | /* Increment page address and decrement length */ |
daae74ca | 2971 | len -= (1ULL << chip->phys_erase_shift); |
1da177e4 LT |
2972 | page += pages_per_block; |
2973 | ||
2974 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 2975 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 2976 | chipnr++; |
ace4dfee TG |
2977 | chip->select_chip(mtd, -1); |
2978 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2979 | } |
2980 | } | |
2981 | instr->state = MTD_ERASE_DONE; | |
2982 | ||
7351d3a5 | 2983 | erase_exit: |
1da177e4 LT |
2984 | |
2985 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1da177e4 LT |
2986 | |
2987 | /* Deselect and wake up anyone waiting on the device */ | |
b0bb6903 | 2988 | chip->select_chip(mtd, -1); |
1da177e4 LT |
2989 | nand_release_device(mtd); |
2990 | ||
49defc01 DW |
2991 | /* Do call back function */ |
2992 | if (!ret) | |
2993 | mtd_erase_callback(instr); | |
2994 | ||
1da177e4 LT |
2995 | /* Return more or less happy */ |
2996 | return ret; | |
2997 | } | |
2998 | ||
2999 | /** | |
3000 | * nand_sync - [MTD Interface] sync | |
8b6e50c9 | 3001 | * @mtd: MTD device structure |
1da177e4 | 3002 | * |
8b6e50c9 | 3003 | * Sync is actually a wait for chip ready function. |
1da177e4 | 3004 | */ |
e0c7d767 | 3005 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 3006 | { |
289c0522 | 3007 | pr_debug("%s: called\n", __func__); |
1da177e4 LT |
3008 | |
3009 | /* Grab the lock and see if the device is available */ | |
6a8214aa | 3010 | nand_get_device(mtd, FL_SYNCING); |
1da177e4 | 3011 | /* Release it and go back */ |
e0c7d767 | 3012 | nand_release_device(mtd); |
1da177e4 LT |
3013 | } |
3014 | ||
1da177e4 | 3015 | /** |
ace4dfee | 3016 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
8b6e50c9 BN |
3017 | * @mtd: MTD device structure |
3018 | * @offs: offset relative to mtd start | |
1da177e4 | 3019 | */ |
ace4dfee | 3020 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 | 3021 | { |
9f3e0429 AT |
3022 | struct nand_chip *chip = mtd_to_nand(mtd); |
3023 | int chipnr = (int)(offs >> chip->chip_shift); | |
3024 | int ret; | |
3025 | ||
3026 | /* Select the NAND device */ | |
3027 | nand_get_device(mtd, FL_READING); | |
3028 | chip->select_chip(mtd, chipnr); | |
3029 | ||
3030 | ret = nand_block_checkbad(mtd, offs, 0); | |
3031 | ||
3032 | chip->select_chip(mtd, -1); | |
3033 | nand_release_device(mtd); | |
3034 | ||
3035 | return ret; | |
1da177e4 LT |
3036 | } |
3037 | ||
3038 | /** | |
ace4dfee | 3039 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
8b6e50c9 BN |
3040 | * @mtd: MTD device structure |
3041 | * @ofs: offset relative to mtd start | |
1da177e4 | 3042 | */ |
e0c7d767 | 3043 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 3044 | { |
1da177e4 LT |
3045 | int ret; |
3046 | ||
f8ac0414 FF |
3047 | ret = nand_block_isbad(mtd, ofs); |
3048 | if (ret) { | |
8b6e50c9 | 3049 | /* If it was bad already, return success and do nothing */ |
1da177e4 LT |
3050 | if (ret > 0) |
3051 | return 0; | |
e0c7d767 DW |
3052 | return ret; |
3053 | } | |
1da177e4 | 3054 | |
5a0edb25 | 3055 | return nand_block_markbad_lowlevel(mtd, ofs); |
1da177e4 LT |
3056 | } |
3057 | ||
7db03ecc HS |
3058 | /** |
3059 | * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand | |
3060 | * @mtd: MTD device structure | |
3061 | * @chip: nand chip info structure | |
3062 | * @addr: feature address. | |
3063 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
3064 | */ | |
3065 | static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, | |
3066 | int addr, uint8_t *subfeature_param) | |
3067 | { | |
3068 | int status; | |
05f78359 | 3069 | int i; |
7db03ecc | 3070 | |
d914c932 DM |
3071 | if (!chip->onfi_version || |
3072 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
3073 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
3074 | return -EINVAL; |
3075 | ||
3076 | chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1); | |
05f78359 UKK |
3077 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) |
3078 | chip->write_byte(mtd, subfeature_param[i]); | |
3079 | ||
7db03ecc HS |
3080 | status = chip->waitfunc(mtd, chip); |
3081 | if (status & NAND_STATUS_FAIL) | |
3082 | return -EIO; | |
3083 | return 0; | |
3084 | } | |
3085 | ||
3086 | /** | |
3087 | * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand | |
3088 | * @mtd: MTD device structure | |
3089 | * @chip: nand chip info structure | |
3090 | * @addr: feature address. | |
3091 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
3092 | */ | |
3093 | static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip, | |
3094 | int addr, uint8_t *subfeature_param) | |
3095 | { | |
05f78359 UKK |
3096 | int i; |
3097 | ||
d914c932 DM |
3098 | if (!chip->onfi_version || |
3099 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
3100 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
3101 | return -EINVAL; |
3102 | ||
7db03ecc | 3103 | chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1); |
05f78359 UKK |
3104 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) |
3105 | *subfeature_param++ = chip->read_byte(mtd); | |
7db03ecc HS |
3106 | return 0; |
3107 | } | |
3108 | ||
962034f4 VW |
3109 | /** |
3110 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
8b6e50c9 | 3111 | * @mtd: MTD device structure |
962034f4 VW |
3112 | */ |
3113 | static int nand_suspend(struct mtd_info *mtd) | |
3114 | { | |
6a8214aa | 3115 | return nand_get_device(mtd, FL_PM_SUSPENDED); |
962034f4 VW |
3116 | } |
3117 | ||
3118 | /** | |
3119 | * nand_resume - [MTD Interface] Resume the NAND flash | |
8b6e50c9 | 3120 | * @mtd: MTD device structure |
962034f4 VW |
3121 | */ |
3122 | static void nand_resume(struct mtd_info *mtd) | |
3123 | { | |
862eba51 | 3124 | struct nand_chip *chip = mtd_to_nand(mtd); |
962034f4 | 3125 | |
ace4dfee | 3126 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
3127 | nand_release_device(mtd); |
3128 | else | |
d0370219 BN |
3129 | pr_err("%s called for a chip which is not in suspended state\n", |
3130 | __func__); | |
962034f4 VW |
3131 | } |
3132 | ||
72ea4036 SB |
3133 | /** |
3134 | * nand_shutdown - [MTD Interface] Finish the current NAND operation and | |
3135 | * prevent further operations | |
3136 | * @mtd: MTD device structure | |
3137 | */ | |
3138 | static void nand_shutdown(struct mtd_info *mtd) | |
3139 | { | |
9ca641b0 | 3140 | nand_get_device(mtd, FL_PM_SUSPENDED); |
72ea4036 SB |
3141 | } |
3142 | ||
8b6e50c9 | 3143 | /* Set default functions */ |
ace4dfee | 3144 | static void nand_set_defaults(struct nand_chip *chip, int busw) |
7aa65bfd | 3145 | { |
1da177e4 | 3146 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
3147 | if (!chip->chip_delay) |
3148 | chip->chip_delay = 20; | |
1da177e4 LT |
3149 | |
3150 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
3151 | if (chip->cmdfunc == NULL) |
3152 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
3153 | |
3154 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
3155 | if (chip->waitfunc == NULL) |
3156 | chip->waitfunc = nand_wait; | |
3157 | ||
3158 | if (!chip->select_chip) | |
3159 | chip->select_chip = nand_select_chip; | |
68e80780 | 3160 | |
4204cccd HS |
3161 | /* set for ONFI nand */ |
3162 | if (!chip->onfi_set_features) | |
3163 | chip->onfi_set_features = nand_onfi_set_features; | |
3164 | if (!chip->onfi_get_features) | |
3165 | chip->onfi_get_features = nand_onfi_get_features; | |
3166 | ||
68e80780 BN |
3167 | /* If called twice, pointers that depend on busw may need to be reset */ |
3168 | if (!chip->read_byte || chip->read_byte == nand_read_byte) | |
ace4dfee TG |
3169 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; |
3170 | if (!chip->read_word) | |
3171 | chip->read_word = nand_read_word; | |
3172 | if (!chip->block_bad) | |
3173 | chip->block_bad = nand_block_bad; | |
3174 | if (!chip->block_markbad) | |
3175 | chip->block_markbad = nand_default_block_markbad; | |
68e80780 | 3176 | if (!chip->write_buf || chip->write_buf == nand_write_buf) |
ace4dfee | 3177 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; |
05f78359 UKK |
3178 | if (!chip->write_byte || chip->write_byte == nand_write_byte) |
3179 | chip->write_byte = busw ? nand_write_byte16 : nand_write_byte; | |
68e80780 | 3180 | if (!chip->read_buf || chip->read_buf == nand_read_buf) |
ace4dfee | 3181 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; |
ace4dfee TG |
3182 | if (!chip->scan_bbt) |
3183 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
3184 | |
3185 | if (!chip->controller) { | |
3186 | chip->controller = &chip->hwcontrol; | |
3187 | spin_lock_init(&chip->controller->lock); | |
3188 | init_waitqueue_head(&chip->controller->wq); | |
3189 | } | |
3190 | ||
7aa65bfd TG |
3191 | } |
3192 | ||
8b6e50c9 | 3193 | /* Sanitize ONFI strings so we can safely print them */ |
d1e1f4e4 FF |
3194 | static void sanitize_string(uint8_t *s, size_t len) |
3195 | { | |
3196 | ssize_t i; | |
3197 | ||
8b6e50c9 | 3198 | /* Null terminate */ |
d1e1f4e4 FF |
3199 | s[len - 1] = 0; |
3200 | ||
8b6e50c9 | 3201 | /* Remove non printable chars */ |
d1e1f4e4 FF |
3202 | for (i = 0; i < len - 1; i++) { |
3203 | if (s[i] < ' ' || s[i] > 127) | |
3204 | s[i] = '?'; | |
3205 | } | |
3206 | ||
8b6e50c9 | 3207 | /* Remove trailing spaces */ |
d1e1f4e4 FF |
3208 | strim(s); |
3209 | } | |
3210 | ||
3211 | static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) | |
3212 | { | |
3213 | int i; | |
3214 | while (len--) { | |
3215 | crc ^= *p++ << 8; | |
3216 | for (i = 0; i < 8; i++) | |
3217 | crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); | |
3218 | } | |
3219 | ||
3220 | return crc; | |
3221 | } | |
3222 | ||
6dcbe0cd HS |
3223 | /* Parse the Extended Parameter Page. */ |
3224 | static int nand_flash_detect_ext_param_page(struct mtd_info *mtd, | |
3225 | struct nand_chip *chip, struct nand_onfi_params *p) | |
3226 | { | |
3227 | struct onfi_ext_param_page *ep; | |
3228 | struct onfi_ext_section *s; | |
3229 | struct onfi_ext_ecc_info *ecc; | |
3230 | uint8_t *cursor; | |
3231 | int ret = -EINVAL; | |
3232 | int len; | |
3233 | int i; | |
3234 | ||
3235 | len = le16_to_cpu(p->ext_param_page_length) * 16; | |
3236 | ep = kmalloc(len, GFP_KERNEL); | |
5cb13271 BN |
3237 | if (!ep) |
3238 | return -ENOMEM; | |
6dcbe0cd HS |
3239 | |
3240 | /* Send our own NAND_CMD_PARAM. */ | |
3241 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); | |
3242 | ||
3243 | /* Use the Change Read Column command to skip the ONFI param pages. */ | |
3244 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, | |
3245 | sizeof(*p) * p->num_of_param_pages , -1); | |
3246 | ||
3247 | /* Read out the Extended Parameter Page. */ | |
3248 | chip->read_buf(mtd, (uint8_t *)ep, len); | |
3249 | if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2) | |
3250 | != le16_to_cpu(ep->crc))) { | |
3251 | pr_debug("fail in the CRC.\n"); | |
3252 | goto ext_out; | |
3253 | } | |
3254 | ||
3255 | /* | |
3256 | * Check the signature. | |
3257 | * Do not strictly follow the ONFI spec, maybe changed in future. | |
3258 | */ | |
3259 | if (strncmp(ep->sig, "EPPS", 4)) { | |
3260 | pr_debug("The signature is invalid.\n"); | |
3261 | goto ext_out; | |
3262 | } | |
3263 | ||
3264 | /* find the ECC section. */ | |
3265 | cursor = (uint8_t *)(ep + 1); | |
3266 | for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) { | |
3267 | s = ep->sections + i; | |
3268 | if (s->type == ONFI_SECTION_TYPE_2) | |
3269 | break; | |
3270 | cursor += s->length * 16; | |
3271 | } | |
3272 | if (i == ONFI_EXT_SECTION_MAX) { | |
3273 | pr_debug("We can not find the ECC section.\n"); | |
3274 | goto ext_out; | |
3275 | } | |
3276 | ||
3277 | /* get the info we want. */ | |
3278 | ecc = (struct onfi_ext_ecc_info *)cursor; | |
3279 | ||
4ae7d228 BN |
3280 | if (!ecc->codeword_size) { |
3281 | pr_debug("Invalid codeword size\n"); | |
3282 | goto ext_out; | |
6dcbe0cd HS |
3283 | } |
3284 | ||
4ae7d228 BN |
3285 | chip->ecc_strength_ds = ecc->ecc_bits; |
3286 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
5cb13271 | 3287 | ret = 0; |
6dcbe0cd HS |
3288 | |
3289 | ext_out: | |
3290 | kfree(ep); | |
3291 | return ret; | |
3292 | } | |
3293 | ||
8429bb39 BN |
3294 | static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode) |
3295 | { | |
862eba51 | 3296 | struct nand_chip *chip = mtd_to_nand(mtd); |
8429bb39 BN |
3297 | uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; |
3298 | ||
3299 | return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, | |
3300 | feature); | |
3301 | } | |
3302 | ||
3303 | /* | |
3304 | * Configure chip properties from Micron vendor-specific ONFI table | |
3305 | */ | |
3306 | static void nand_onfi_detect_micron(struct nand_chip *chip, | |
3307 | struct nand_onfi_params *p) | |
3308 | { | |
3309 | struct nand_onfi_vendor_micron *micron = (void *)p->vendor; | |
3310 | ||
3311 | if (le16_to_cpu(p->vendor_revision) < 1) | |
3312 | return; | |
3313 | ||
3314 | chip->read_retries = micron->read_retry_options; | |
3315 | chip->setup_read_retry = nand_setup_read_retry_micron; | |
3316 | } | |
3317 | ||
6fb277ba | 3318 | /* |
8b6e50c9 | 3319 | * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. |
6fb277ba FF |
3320 | */ |
3321 | static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, | |
08c248fb | 3322 | int *busw) |
6fb277ba FF |
3323 | { |
3324 | struct nand_onfi_params *p = &chip->onfi_params; | |
bd9c6e99 | 3325 | int i, j; |
6fb277ba FF |
3326 | int val; |
3327 | ||
7854d3f7 | 3328 | /* Try ONFI for unknown chip or LP */ |
6fb277ba FF |
3329 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); |
3330 | if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || | |
3331 | chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') | |
3332 | return 0; | |
3333 | ||
6fb277ba FF |
3334 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); |
3335 | for (i = 0; i < 3; i++) { | |
bd9c6e99 BN |
3336 | for (j = 0; j < sizeof(*p); j++) |
3337 | ((uint8_t *)p)[j] = chip->read_byte(mtd); | |
6fb277ba FF |
3338 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == |
3339 | le16_to_cpu(p->crc)) { | |
6fb277ba FF |
3340 | break; |
3341 | } | |
3342 | } | |
3343 | ||
c7f23a70 BN |
3344 | if (i == 3) { |
3345 | pr_err("Could not find valid ONFI parameter page; aborting\n"); | |
6fb277ba | 3346 | return 0; |
c7f23a70 | 3347 | } |
6fb277ba | 3348 | |
8b6e50c9 | 3349 | /* Check version */ |
6fb277ba | 3350 | val = le16_to_cpu(p->revision); |
b7b1a29d BN |
3351 | if (val & (1 << 5)) |
3352 | chip->onfi_version = 23; | |
3353 | else if (val & (1 << 4)) | |
6fb277ba FF |
3354 | chip->onfi_version = 22; |
3355 | else if (val & (1 << 3)) | |
3356 | chip->onfi_version = 21; | |
3357 | else if (val & (1 << 2)) | |
3358 | chip->onfi_version = 20; | |
b7b1a29d | 3359 | else if (val & (1 << 1)) |
6fb277ba | 3360 | chip->onfi_version = 10; |
b7b1a29d BN |
3361 | |
3362 | if (!chip->onfi_version) { | |
20171642 | 3363 | pr_info("unsupported ONFI version: %d\n", val); |
b7b1a29d BN |
3364 | return 0; |
3365 | } | |
6fb277ba FF |
3366 | |
3367 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
3368 | sanitize_string(p->model, sizeof(p->model)); | |
3369 | if (!mtd->name) | |
3370 | mtd->name = p->model; | |
4355b70c | 3371 | |
6fb277ba | 3372 | mtd->writesize = le32_to_cpu(p->byte_per_page); |
4355b70c BN |
3373 | |
3374 | /* | |
3375 | * pages_per_block and blocks_per_lun may not be a power-of-2 size | |
3376 | * (don't ask me who thought of this...). MTD assumes that these | |
3377 | * dimensions will be power-of-2, so just truncate the remaining area. | |
3378 | */ | |
3379 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
3380 | mtd->erasesize *= mtd->writesize; | |
3381 | ||
6fb277ba | 3382 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); |
4355b70c BN |
3383 | |
3384 | /* See erasesize comment */ | |
3385 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
63795755 | 3386 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; |
13fbd179 | 3387 | chip->bits_per_cell = p->bits_per_cell; |
e2985fc1 HS |
3388 | |
3389 | if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) | |
08c248fb | 3390 | *busw = NAND_BUSWIDTH_16; |
e2985fc1 HS |
3391 | else |
3392 | *busw = 0; | |
6fb277ba | 3393 | |
10c86bab HS |
3394 | if (p->ecc_bits != 0xff) { |
3395 | chip->ecc_strength_ds = p->ecc_bits; | |
3396 | chip->ecc_step_ds = 512; | |
6dcbe0cd HS |
3397 | } else if (chip->onfi_version >= 21 && |
3398 | (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) { | |
3399 | ||
3400 | /* | |
3401 | * The nand_flash_detect_ext_param_page() uses the | |
3402 | * Change Read Column command which maybe not supported | |
3403 | * by the chip->cmdfunc. So try to update the chip->cmdfunc | |
3404 | * now. We do not replace user supplied command function. | |
3405 | */ | |
3406 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) | |
3407 | chip->cmdfunc = nand_command_lp; | |
3408 | ||
3409 | /* The Extended Parameter Page is supported since ONFI 2.1. */ | |
3410 | if (nand_flash_detect_ext_param_page(mtd, chip, p)) | |
c7f23a70 BN |
3411 | pr_warn("Failed to detect ONFI extended param page\n"); |
3412 | } else { | |
3413 | pr_warn("Could not retrieve ONFI ECC requirements\n"); | |
10c86bab HS |
3414 | } |
3415 | ||
8429bb39 BN |
3416 | if (p->jedec_id == NAND_MFR_MICRON) |
3417 | nand_onfi_detect_micron(chip, p); | |
3418 | ||
6fb277ba FF |
3419 | return 1; |
3420 | } | |
3421 | ||
91361818 HS |
3422 | /* |
3423 | * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise. | |
3424 | */ | |
3425 | static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip, | |
3426 | int *busw) | |
3427 | { | |
3428 | struct nand_jedec_params *p = &chip->jedec_params; | |
3429 | struct jedec_ecc_info *ecc; | |
3430 | int val; | |
3431 | int i, j; | |
3432 | ||
3433 | /* Try JEDEC for unknown chip or LP */ | |
3434 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1); | |
3435 | if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' || | |
3436 | chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' || | |
3437 | chip->read_byte(mtd) != 'C') | |
3438 | return 0; | |
3439 | ||
3440 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1); | |
3441 | for (i = 0; i < 3; i++) { | |
3442 | for (j = 0; j < sizeof(*p); j++) | |
3443 | ((uint8_t *)p)[j] = chip->read_byte(mtd); | |
3444 | ||
3445 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) == | |
3446 | le16_to_cpu(p->crc)) | |
3447 | break; | |
3448 | } | |
3449 | ||
3450 | if (i == 3) { | |
3451 | pr_err("Could not find valid JEDEC parameter page; aborting\n"); | |
3452 | return 0; | |
3453 | } | |
3454 | ||
3455 | /* Check version */ | |
3456 | val = le16_to_cpu(p->revision); | |
3457 | if (val & (1 << 2)) | |
3458 | chip->jedec_version = 10; | |
3459 | else if (val & (1 << 1)) | |
3460 | chip->jedec_version = 1; /* vendor specific version */ | |
3461 | ||
3462 | if (!chip->jedec_version) { | |
3463 | pr_info("unsupported JEDEC version: %d\n", val); | |
3464 | return 0; | |
3465 | } | |
3466 | ||
3467 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
3468 | sanitize_string(p->model, sizeof(p->model)); | |
3469 | if (!mtd->name) | |
3470 | mtd->name = p->model; | |
3471 | ||
3472 | mtd->writesize = le32_to_cpu(p->byte_per_page); | |
3473 | ||
3474 | /* Please reference to the comment for nand_flash_detect_onfi. */ | |
3475 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
3476 | mtd->erasesize *= mtd->writesize; | |
3477 | ||
3478 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); | |
3479 | ||
3480 | /* Please reference to the comment for nand_flash_detect_onfi. */ | |
3481 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
3482 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; | |
3483 | chip->bits_per_cell = p->bits_per_cell; | |
3484 | ||
3485 | if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS) | |
3486 | *busw = NAND_BUSWIDTH_16; | |
3487 | else | |
3488 | *busw = 0; | |
3489 | ||
3490 | /* ECC info */ | |
3491 | ecc = &p->ecc_info[0]; | |
3492 | ||
3493 | if (ecc->codeword_size >= 9) { | |
3494 | chip->ecc_strength_ds = ecc->ecc_bits; | |
3495 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
3496 | } else { | |
3497 | pr_warn("Invalid codeword size\n"); | |
3498 | } | |
3499 | ||
3500 | return 1; | |
3501 | } | |
3502 | ||
e3b88bd6 BN |
3503 | /* |
3504 | * nand_id_has_period - Check if an ID string has a given wraparound period | |
3505 | * @id_data: the ID string | |
3506 | * @arrlen: the length of the @id_data array | |
3507 | * @period: the period of repitition | |
3508 | * | |
3509 | * Check if an ID string is repeated within a given sequence of bytes at | |
3510 | * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a | |
d4d4f1bf | 3511 | * period of 3). This is a helper function for nand_id_len(). Returns non-zero |
e3b88bd6 BN |
3512 | * if the repetition has a period of @period; otherwise, returns zero. |
3513 | */ | |
3514 | static int nand_id_has_period(u8 *id_data, int arrlen, int period) | |
3515 | { | |
3516 | int i, j; | |
3517 | for (i = 0; i < period; i++) | |
3518 | for (j = i + period; j < arrlen; j += period) | |
3519 | if (id_data[i] != id_data[j]) | |
3520 | return 0; | |
3521 | return 1; | |
3522 | } | |
3523 | ||
3524 | /* | |
3525 | * nand_id_len - Get the length of an ID string returned by CMD_READID | |
3526 | * @id_data: the ID string | |
3527 | * @arrlen: the length of the @id_data array | |
3528 | ||
3529 | * Returns the length of the ID string, according to known wraparound/trailing | |
3530 | * zero patterns. If no pattern exists, returns the length of the array. | |
3531 | */ | |
3532 | static int nand_id_len(u8 *id_data, int arrlen) | |
3533 | { | |
3534 | int last_nonzero, period; | |
3535 | ||
3536 | /* Find last non-zero byte */ | |
3537 | for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) | |
3538 | if (id_data[last_nonzero]) | |
3539 | break; | |
3540 | ||
3541 | /* All zeros */ | |
3542 | if (last_nonzero < 0) | |
3543 | return 0; | |
3544 | ||
3545 | /* Calculate wraparound period */ | |
3546 | for (period = 1; period < arrlen; period++) | |
3547 | if (nand_id_has_period(id_data, arrlen, period)) | |
3548 | break; | |
3549 | ||
3550 | /* There's a repeated pattern */ | |
3551 | if (period < arrlen) | |
3552 | return period; | |
3553 | ||
3554 | /* There are trailing zeros */ | |
3555 | if (last_nonzero < arrlen - 1) | |
3556 | return last_nonzero + 1; | |
3557 | ||
3558 | /* No pattern detected */ | |
3559 | return arrlen; | |
3560 | } | |
3561 | ||
7db906b7 HS |
3562 | /* Extract the bits of per cell from the 3rd byte of the extended ID */ |
3563 | static int nand_get_bits_per_cell(u8 cellinfo) | |
3564 | { | |
3565 | int bits; | |
3566 | ||
3567 | bits = cellinfo & NAND_CI_CELLTYPE_MSK; | |
3568 | bits >>= NAND_CI_CELLTYPE_SHIFT; | |
3569 | return bits + 1; | |
3570 | } | |
3571 | ||
fc09bbc0 BN |
3572 | /* |
3573 | * Many new NAND share similar device ID codes, which represent the size of the | |
3574 | * chip. The rest of the parameters must be decoded according to generic or | |
3575 | * manufacturer-specific "extended ID" decoding patterns. | |
3576 | */ | |
3577 | static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, | |
3578 | u8 id_data[8], int *busw) | |
3579 | { | |
e3b88bd6 | 3580 | int extid, id_len; |
fc09bbc0 | 3581 | /* The 3rd id byte holds MLC / multichip data */ |
7db906b7 | 3582 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
fc09bbc0 BN |
3583 | /* The 4th id byte is the important one */ |
3584 | extid = id_data[3]; | |
3585 | ||
e3b88bd6 BN |
3586 | id_len = nand_id_len(id_data, 8); |
3587 | ||
fc09bbc0 BN |
3588 | /* |
3589 | * Field definitions are in the following datasheets: | |
3590 | * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) | |
af451af4 | 3591 | * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44) |
73ca392f | 3592 | * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) |
fc09bbc0 | 3593 | * |
af451af4 BN |
3594 | * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung |
3595 | * ID to decide what to do. | |
fc09bbc0 | 3596 | */ |
af451af4 | 3597 | if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && |
1d0ed69d | 3598 | !nand_is_slc(chip) && id_data[5] != 0x00) { |
fc09bbc0 BN |
3599 | /* Calc pagesize */ |
3600 | mtd->writesize = 2048 << (extid & 0x03); | |
3601 | extid >>= 2; | |
3602 | /* Calc oobsize */ | |
e2d3a35e | 3603 | switch (((extid >> 2) & 0x04) | (extid & 0x03)) { |
fc09bbc0 BN |
3604 | case 1: |
3605 | mtd->oobsize = 128; | |
3606 | break; | |
3607 | case 2: | |
3608 | mtd->oobsize = 218; | |
3609 | break; | |
3610 | case 3: | |
3611 | mtd->oobsize = 400; | |
3612 | break; | |
e2d3a35e | 3613 | case 4: |
fc09bbc0 BN |
3614 | mtd->oobsize = 436; |
3615 | break; | |
e2d3a35e BN |
3616 | case 5: |
3617 | mtd->oobsize = 512; | |
3618 | break; | |
3619 | case 6: | |
e2d3a35e BN |
3620 | mtd->oobsize = 640; |
3621 | break; | |
94d04e82 HS |
3622 | case 7: |
3623 | default: /* Other cases are "reserved" (unknown) */ | |
3624 | mtd->oobsize = 1024; | |
3625 | break; | |
fc09bbc0 BN |
3626 | } |
3627 | extid >>= 2; | |
3628 | /* Calc blocksize */ | |
3629 | mtd->erasesize = (128 * 1024) << | |
3630 | (((extid >> 1) & 0x04) | (extid & 0x03)); | |
3631 | *busw = 0; | |
73ca392f | 3632 | } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && |
1d0ed69d | 3633 | !nand_is_slc(chip)) { |
73ca392f BN |
3634 | unsigned int tmp; |
3635 | ||
3636 | /* Calc pagesize */ | |
3637 | mtd->writesize = 2048 << (extid & 0x03); | |
3638 | extid >>= 2; | |
3639 | /* Calc oobsize */ | |
3640 | switch (((extid >> 2) & 0x04) | (extid & 0x03)) { | |
3641 | case 0: | |
3642 | mtd->oobsize = 128; | |
3643 | break; | |
3644 | case 1: | |
3645 | mtd->oobsize = 224; | |
3646 | break; | |
3647 | case 2: | |
3648 | mtd->oobsize = 448; | |
3649 | break; | |
3650 | case 3: | |
3651 | mtd->oobsize = 64; | |
3652 | break; | |
3653 | case 4: | |
3654 | mtd->oobsize = 32; | |
3655 | break; | |
3656 | case 5: | |
3657 | mtd->oobsize = 16; | |
3658 | break; | |
3659 | default: | |
3660 | mtd->oobsize = 640; | |
3661 | break; | |
3662 | } | |
3663 | extid >>= 2; | |
3664 | /* Calc blocksize */ | |
3665 | tmp = ((extid >> 1) & 0x04) | (extid & 0x03); | |
3666 | if (tmp < 0x03) | |
3667 | mtd->erasesize = (128 * 1024) << tmp; | |
3668 | else if (tmp == 0x03) | |
3669 | mtd->erasesize = 768 * 1024; | |
3670 | else | |
3671 | mtd->erasesize = (64 * 1024) << tmp; | |
3672 | *busw = 0; | |
fc09bbc0 BN |
3673 | } else { |
3674 | /* Calc pagesize */ | |
3675 | mtd->writesize = 1024 << (extid & 0x03); | |
3676 | extid >>= 2; | |
3677 | /* Calc oobsize */ | |
3678 | mtd->oobsize = (8 << (extid & 0x01)) * | |
3679 | (mtd->writesize >> 9); | |
3680 | extid >>= 2; | |
3681 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
3682 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
3683 | extid >>= 2; | |
3684 | /* Get buswidth information */ | |
3685 | *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; | |
60c67382 BN |
3686 | |
3687 | /* | |
3688 | * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per | |
3689 | * 512B page. For Toshiba SLC, we decode the 5th/6th byte as | |
3690 | * follows: | |
3691 | * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, | |
3692 | * 110b -> 24nm | |
3693 | * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC | |
3694 | */ | |
3695 | if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA && | |
1d0ed69d | 3696 | nand_is_slc(chip) && |
60c67382 BN |
3697 | (id_data[5] & 0x7) == 0x6 /* 24nm */ && |
3698 | !(id_data[4] & 0x80) /* !BENAND */) { | |
3699 | mtd->oobsize = 32 * mtd->writesize >> 9; | |
3700 | } | |
3701 | ||
fc09bbc0 BN |
3702 | } |
3703 | } | |
3704 | ||
f23a481c BN |
3705 | /* |
3706 | * Old devices have chip data hardcoded in the device ID table. nand_decode_id | |
3707 | * decodes a matching ID table entry and assigns the MTD size parameters for | |
3708 | * the chip. | |
3709 | */ | |
3710 | static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, | |
3711 | struct nand_flash_dev *type, u8 id_data[8], | |
3712 | int *busw) | |
3713 | { | |
3714 | int maf_id = id_data[0]; | |
3715 | ||
3716 | mtd->erasesize = type->erasesize; | |
3717 | mtd->writesize = type->pagesize; | |
3718 | mtd->oobsize = mtd->writesize / 32; | |
3719 | *busw = type->options & NAND_BUSWIDTH_16; | |
3720 | ||
1c195e90 HS |
3721 | /* All legacy ID NAND are small-page, SLC */ |
3722 | chip->bits_per_cell = 1; | |
3723 | ||
f23a481c BN |
3724 | /* |
3725 | * Check for Spansion/AMD ID + repeating 5th, 6th byte since | |
3726 | * some Spansion chips have erasesize that conflicts with size | |
3727 | * listed in nand_ids table. | |
3728 | * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) | |
3729 | */ | |
3730 | if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00 | |
3731 | && id_data[6] == 0x00 && id_data[7] == 0x00 | |
3732 | && mtd->writesize == 512) { | |
3733 | mtd->erasesize = 128 * 1024; | |
3734 | mtd->erasesize <<= ((id_data[3] & 0x03) << 1); | |
3735 | } | |
3736 | } | |
3737 | ||
7e74c2d7 BN |
3738 | /* |
3739 | * Set the bad block marker/indicator (BBM/BBI) patterns according to some | |
3740 | * heuristic patterns using various detected parameters (e.g., manufacturer, | |
3741 | * page size, cell-type information). | |
3742 | */ | |
3743 | static void nand_decode_bbm_options(struct mtd_info *mtd, | |
3744 | struct nand_chip *chip, u8 id_data[8]) | |
3745 | { | |
3746 | int maf_id = id_data[0]; | |
3747 | ||
3748 | /* Set the bad block position */ | |
3749 | if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) | |
3750 | chip->badblockpos = NAND_LARGE_BADBLOCK_POS; | |
3751 | else | |
3752 | chip->badblockpos = NAND_SMALL_BADBLOCK_POS; | |
3753 | ||
3754 | /* | |
3755 | * Bad block marker is stored in the last page of each block on Samsung | |
3756 | * and Hynix MLC devices; stored in first two pages of each block on | |
3757 | * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, | |
3758 | * AMD/Spansion, and Macronix. All others scan only the first page. | |
3759 | */ | |
1d0ed69d | 3760 | if (!nand_is_slc(chip) && |
7e74c2d7 BN |
3761 | (maf_id == NAND_MFR_SAMSUNG || |
3762 | maf_id == NAND_MFR_HYNIX)) | |
3763 | chip->bbt_options |= NAND_BBT_SCANLASTPAGE; | |
1d0ed69d | 3764 | else if ((nand_is_slc(chip) && |
7e74c2d7 BN |
3765 | (maf_id == NAND_MFR_SAMSUNG || |
3766 | maf_id == NAND_MFR_HYNIX || | |
3767 | maf_id == NAND_MFR_TOSHIBA || | |
3768 | maf_id == NAND_MFR_AMD || | |
3769 | maf_id == NAND_MFR_MACRONIX)) || | |
3770 | (mtd->writesize == 2048 && | |
3771 | maf_id == NAND_MFR_MICRON)) | |
3772 | chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; | |
3773 | } | |
3774 | ||
ec6e87e3 HS |
3775 | static inline bool is_full_id_nand(struct nand_flash_dev *type) |
3776 | { | |
3777 | return type->id_len; | |
3778 | } | |
3779 | ||
3780 | static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, | |
3781 | struct nand_flash_dev *type, u8 *id_data, int *busw) | |
3782 | { | |
3783 | if (!strncmp(type->id, id_data, type->id_len)) { | |
3784 | mtd->writesize = type->pagesize; | |
3785 | mtd->erasesize = type->erasesize; | |
3786 | mtd->oobsize = type->oobsize; | |
3787 | ||
7db906b7 | 3788 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
ec6e87e3 HS |
3789 | chip->chipsize = (uint64_t)type->chipsize << 20; |
3790 | chip->options |= type->options; | |
57219342 HS |
3791 | chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); |
3792 | chip->ecc_step_ds = NAND_ECC_STEP(type); | |
57a94e24 BB |
3793 | chip->onfi_timing_mode_default = |
3794 | type->onfi_timing_mode_default; | |
ec6e87e3 HS |
3795 | |
3796 | *busw = type->options & NAND_BUSWIDTH_16; | |
3797 | ||
092b6a1d CZ |
3798 | if (!mtd->name) |
3799 | mtd->name = type->name; | |
3800 | ||
ec6e87e3 HS |
3801 | return true; |
3802 | } | |
3803 | return false; | |
3804 | } | |
3805 | ||
7aa65bfd | 3806 | /* |
8b6e50c9 | 3807 | * Get the flash and manufacturer id and lookup if the type is supported. |
7aa65bfd TG |
3808 | */ |
3809 | static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, | |
ace4dfee | 3810 | struct nand_chip *chip, |
7351d3a5 | 3811 | int *maf_id, int *dev_id, |
5e81e88a | 3812 | struct nand_flash_dev *type) |
7aa65bfd | 3813 | { |
bb77082f | 3814 | int busw; |
d1e1f4e4 | 3815 | int i, maf_idx; |
426c457a | 3816 | u8 id_data[8]; |
1da177e4 LT |
3817 | |
3818 | /* Select the device */ | |
ace4dfee | 3819 | chip->select_chip(mtd, 0); |
1da177e4 | 3820 | |
ef89a880 KB |
3821 | /* |
3822 | * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) | |
8b6e50c9 | 3823 | * after power-up. |
ef89a880 KB |
3824 | */ |
3825 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
3826 | ||
1da177e4 | 3827 | /* Send the command for reading device ID */ |
ace4dfee | 3828 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
3829 | |
3830 | /* Read manufacturer and device IDs */ | |
ace4dfee | 3831 | *maf_id = chip->read_byte(mtd); |
d1e1f4e4 | 3832 | *dev_id = chip->read_byte(mtd); |
1da177e4 | 3833 | |
8b6e50c9 BN |
3834 | /* |
3835 | * Try again to make sure, as some systems the bus-hold or other | |
ed8165c7 BD |
3836 | * interface concerns can cause random data which looks like a |
3837 | * possibly credible NAND flash to appear. If the two results do | |
3838 | * not match, ignore the device completely. | |
3839 | */ | |
3840 | ||
3841 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
3842 | ||
4aef9b78 BN |
3843 | /* Read entire ID string */ |
3844 | for (i = 0; i < 8; i++) | |
426c457a | 3845 | id_data[i] = chip->read_byte(mtd); |
ed8165c7 | 3846 | |
d1e1f4e4 | 3847 | if (id_data[0] != *maf_id || id_data[1] != *dev_id) { |
20171642 | 3848 | pr_info("second ID read did not match %02x,%02x against %02x,%02x\n", |
d0370219 | 3849 | *maf_id, *dev_id, id_data[0], id_data[1]); |
ed8165c7 BD |
3850 | return ERR_PTR(-ENODEV); |
3851 | } | |
3852 | ||
7aa65bfd | 3853 | if (!type) |
5e81e88a DW |
3854 | type = nand_flash_ids; |
3855 | ||
ec6e87e3 HS |
3856 | for (; type->name != NULL; type++) { |
3857 | if (is_full_id_nand(type)) { | |
3858 | if (find_full_id_nand(mtd, chip, type, id_data, &busw)) | |
3859 | goto ident_done; | |
3860 | } else if (*dev_id == type->dev_id) { | |
db5b09f6 | 3861 | break; |
ec6e87e3 HS |
3862 | } |
3863 | } | |
5e81e88a | 3864 | |
d1e1f4e4 FF |
3865 | chip->onfi_version = 0; |
3866 | if (!type->name || !type->pagesize) { | |
35fc5195 | 3867 | /* Check if the chip is ONFI compliant */ |
47450b35 | 3868 | if (nand_flash_detect_onfi(mtd, chip, &busw)) |
6fb277ba | 3869 | goto ident_done; |
91361818 HS |
3870 | |
3871 | /* Check if the chip is JEDEC compliant */ | |
3872 | if (nand_flash_detect_jedec(mtd, chip, &busw)) | |
3873 | goto ident_done; | |
d1e1f4e4 FF |
3874 | } |
3875 | ||
5e81e88a | 3876 | if (!type->name) |
7aa65bfd TG |
3877 | return ERR_PTR(-ENODEV); |
3878 | ||
ba0251fe TG |
3879 | if (!mtd->name) |
3880 | mtd->name = type->name; | |
3881 | ||
69423d99 | 3882 | chip->chipsize = (uint64_t)type->chipsize << 20; |
7aa65bfd | 3883 | |
a7f5ba40 | 3884 | if (!type->pagesize) { |
fc09bbc0 BN |
3885 | /* Decode parameters from extended ID */ |
3886 | nand_decode_ext_id(mtd, chip, id_data, &busw); | |
7aa65bfd | 3887 | } else { |
f23a481c | 3888 | nand_decode_id(mtd, chip, type, id_data, &busw); |
7aa65bfd | 3889 | } |
bf7a01bf BN |
3890 | /* Get chip options */ |
3891 | chip->options |= type->options; | |
d1e1f4e4 | 3892 | |
8b6e50c9 BN |
3893 | /* |
3894 | * Check if chip is not a Samsung device. Do not clear the | |
3895 | * options for chips which do not have an extended id. | |
d1e1f4e4 FF |
3896 | */ |
3897 | if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) | |
3898 | chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; | |
3899 | ident_done: | |
3900 | ||
7aa65bfd | 3901 | /* Try to identify manufacturer */ |
9a909867 | 3902 | for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { |
7aa65bfd TG |
3903 | if (nand_manuf_ids[maf_idx].id == *maf_id) |
3904 | break; | |
3905 | } | |
0ea4a755 | 3906 | |
64b37b2a MC |
3907 | if (chip->options & NAND_BUSWIDTH_AUTO) { |
3908 | WARN_ON(chip->options & NAND_BUSWIDTH_16); | |
3909 | chip->options |= busw; | |
3910 | nand_set_defaults(chip, busw); | |
3911 | } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { | |
3912 | /* | |
3913 | * Check, if buswidth is correct. Hardware drivers should set | |
3914 | * chip correct! | |
3915 | */ | |
20171642 EG |
3916 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
3917 | *maf_id, *dev_id); | |
3918 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name); | |
3919 | pr_warn("bus width %d instead %d bit\n", | |
d0370219 BN |
3920 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, |
3921 | busw ? 16 : 8); | |
7aa65bfd TG |
3922 | return ERR_PTR(-EINVAL); |
3923 | } | |
61b03bd7 | 3924 | |
7e74c2d7 BN |
3925 | nand_decode_bbm_options(mtd, chip, id_data); |
3926 | ||
7aa65bfd | 3927 | /* Calculate the address shift from the page size */ |
ace4dfee | 3928 | chip->page_shift = ffs(mtd->writesize) - 1; |
8b6e50c9 | 3929 | /* Convert chipsize to number of pages per chip -1 */ |
ace4dfee | 3930 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 3931 | |
ace4dfee | 3932 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 3933 | ffs(mtd->erasesize) - 1; |
69423d99 AH |
3934 | if (chip->chipsize & 0xffffffff) |
3935 | chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; | |
7351d3a5 FF |
3936 | else { |
3937 | chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)); | |
3938 | chip->chip_shift += 32 - 1; | |
3939 | } | |
1da177e4 | 3940 | |
26d9be11 | 3941 | chip->badblockbits = 8; |
49c50b97 | 3942 | chip->erase = single_erase; |
7aa65bfd | 3943 | |
8b6e50c9 | 3944 | /* Do not replace user supplied command function! */ |
ace4dfee TG |
3945 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
3946 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd | 3947 | |
20171642 EG |
3948 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
3949 | *maf_id, *dev_id); | |
ffdac6cd HS |
3950 | |
3951 | if (chip->onfi_version) | |
3952 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, | |
3953 | chip->onfi_params.model); | |
3954 | else if (chip->jedec_version) | |
3955 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, | |
3956 | chip->jedec_params.model); | |
3957 | else | |
3958 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, | |
3959 | type->name); | |
3960 | ||
3755a991 | 3961 | pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n", |
3723e93c | 3962 | (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC", |
3755a991 | 3963 | mtd->erasesize >> 10, mtd->writesize, mtd->oobsize); |
7aa65bfd TG |
3964 | return type; |
3965 | } | |
3966 | ||
7194a29a | 3967 | static int nand_dt_init(struct nand_chip *chip) |
5844feea | 3968 | { |
7194a29a | 3969 | struct device_node *dn = nand_get_flash_node(chip); |
5844feea BN |
3970 | int ecc_mode, ecc_strength, ecc_step; |
3971 | ||
7194a29a BB |
3972 | if (!dn) |
3973 | return 0; | |
3974 | ||
5844feea BN |
3975 | if (of_get_nand_bus_width(dn) == 16) |
3976 | chip->options |= NAND_BUSWIDTH_16; | |
3977 | ||
3978 | if (of_get_nand_on_flash_bbt(dn)) | |
3979 | chip->bbt_options |= NAND_BBT_USE_FLASH; | |
3980 | ||
3981 | ecc_mode = of_get_nand_ecc_mode(dn); | |
3982 | ecc_strength = of_get_nand_ecc_strength(dn); | |
3983 | ecc_step = of_get_nand_ecc_step_size(dn); | |
3984 | ||
3985 | if ((ecc_step >= 0 && !(ecc_strength >= 0)) || | |
3986 | (!(ecc_step >= 0) && ecc_strength >= 0)) { | |
3987 | pr_err("must set both strength and step size in DT\n"); | |
3988 | return -EINVAL; | |
3989 | } | |
3990 | ||
3991 | if (ecc_mode >= 0) | |
3992 | chip->ecc.mode = ecc_mode; | |
3993 | ||
3994 | if (ecc_strength >= 0) | |
3995 | chip->ecc.strength = ecc_strength; | |
3996 | ||
3997 | if (ecc_step > 0) | |
3998 | chip->ecc.size = ecc_step; | |
3999 | ||
4000 | return 0; | |
4001 | } | |
4002 | ||
7aa65bfd | 4003 | /** |
3b85c321 | 4004 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
8b6e50c9 BN |
4005 | * @mtd: MTD device structure |
4006 | * @maxchips: number of chips to scan for | |
4007 | * @table: alternative NAND ID table | |
7aa65bfd | 4008 | * |
8b6e50c9 BN |
4009 | * This is the first phase of the normal nand_scan() function. It reads the |
4010 | * flash ID and sets up MTD fields accordingly. | |
7aa65bfd TG |
4011 | * |
4012 | */ | |
5e81e88a DW |
4013 | int nand_scan_ident(struct mtd_info *mtd, int maxchips, |
4014 | struct nand_flash_dev *table) | |
7aa65bfd | 4015 | { |
bb77082f | 4016 | int i, nand_maf_id, nand_dev_id; |
862eba51 | 4017 | struct nand_chip *chip = mtd_to_nand(mtd); |
7aa65bfd | 4018 | struct nand_flash_dev *type; |
5844feea BN |
4019 | int ret; |
4020 | ||
7194a29a BB |
4021 | ret = nand_dt_init(chip); |
4022 | if (ret) | |
4023 | return ret; | |
7aa65bfd | 4024 | |
f7a8e38f BN |
4025 | if (!mtd->name && mtd->dev.parent) |
4026 | mtd->name = dev_name(mtd->dev.parent); | |
4027 | ||
7aa65bfd | 4028 | /* Set the default functions */ |
bb77082f | 4029 | nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16); |
7aa65bfd TG |
4030 | |
4031 | /* Read the flash type */ | |
bb77082f CZ |
4032 | type = nand_get_flash_type(mtd, chip, &nand_maf_id, |
4033 | &nand_dev_id, table); | |
7aa65bfd TG |
4034 | |
4035 | if (IS_ERR(type)) { | |
b1c6e6db | 4036 | if (!(chip->options & NAND_SCAN_SILENT_NODEV)) |
d0370219 | 4037 | pr_warn("No NAND device found\n"); |
ace4dfee | 4038 | chip->select_chip(mtd, -1); |
7aa65bfd | 4039 | return PTR_ERR(type); |
1da177e4 LT |
4040 | } |
4041 | ||
07300164 HS |
4042 | chip->select_chip(mtd, -1); |
4043 | ||
7aa65bfd | 4044 | /* Check for a chip array */ |
e0c7d767 | 4045 | for (i = 1; i < maxchips; i++) { |
ace4dfee | 4046 | chip->select_chip(mtd, i); |
ef89a880 KB |
4047 | /* See comment in nand_get_flash_type for reset */ |
4048 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1da177e4 | 4049 | /* Send the command for reading device ID */ |
ace4dfee | 4050 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 4051 | /* Read manufacturer and device IDs */ |
ace4dfee | 4052 | if (nand_maf_id != chip->read_byte(mtd) || |
07300164 HS |
4053 | nand_dev_id != chip->read_byte(mtd)) { |
4054 | chip->select_chip(mtd, -1); | |
1da177e4 | 4055 | break; |
07300164 HS |
4056 | } |
4057 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
4058 | } |
4059 | if (i > 1) | |
20171642 | 4060 | pr_info("%d chips detected\n", i); |
61b03bd7 | 4061 | |
1da177e4 | 4062 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
4063 | chip->numchips = i; |
4064 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 4065 | |
3b85c321 DW |
4066 | return 0; |
4067 | } | |
7351d3a5 | 4068 | EXPORT_SYMBOL(nand_scan_ident); |
3b85c321 | 4069 | |
67a9ad9b EG |
4070 | /* |
4071 | * Check if the chip configuration meet the datasheet requirements. | |
4072 | ||
4073 | * If our configuration corrects A bits per B bytes and the minimum | |
4074 | * required correction level is X bits per Y bytes, then we must ensure | |
4075 | * both of the following are true: | |
4076 | * | |
4077 | * (1) A / B >= X / Y | |
4078 | * (2) A >= X | |
4079 | * | |
4080 | * Requirement (1) ensures we can correct for the required bitflip density. | |
4081 | * Requirement (2) ensures we can correct even when all bitflips are clumped | |
4082 | * in the same sector. | |
4083 | */ | |
4084 | static bool nand_ecc_strength_good(struct mtd_info *mtd) | |
4085 | { | |
862eba51 | 4086 | struct nand_chip *chip = mtd_to_nand(mtd); |
67a9ad9b EG |
4087 | struct nand_ecc_ctrl *ecc = &chip->ecc; |
4088 | int corr, ds_corr; | |
4089 | ||
4090 | if (ecc->size == 0 || chip->ecc_step_ds == 0) | |
4091 | /* Not enough information */ | |
4092 | return true; | |
4093 | ||
4094 | /* | |
4095 | * We get the number of corrected bits per page to compare | |
4096 | * the correction density. | |
4097 | */ | |
4098 | corr = (mtd->writesize * ecc->strength) / ecc->size; | |
4099 | ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds; | |
4100 | ||
4101 | return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds; | |
4102 | } | |
3b85c321 DW |
4103 | |
4104 | /** | |
4105 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
8b6e50c9 | 4106 | * @mtd: MTD device structure |
3b85c321 | 4107 | * |
8b6e50c9 BN |
4108 | * This is the second phase of the normal nand_scan() function. It fills out |
4109 | * all the uninitialized function pointers with the defaults and scans for a | |
4110 | * bad block table if appropriate. | |
3b85c321 DW |
4111 | */ |
4112 | int nand_scan_tail(struct mtd_info *mtd) | |
4113 | { | |
4114 | int i; | |
862eba51 | 4115 | struct nand_chip *chip = mtd_to_nand(mtd); |
97de79e0 | 4116 | struct nand_ecc_ctrl *ecc = &chip->ecc; |
f02ea4e6 | 4117 | struct nand_buffers *nbuf; |
3b85c321 | 4118 | |
e2414f4c BN |
4119 | /* New bad blocks should be marked in OOB, flash-based BBT, or both */ |
4120 | BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && | |
4121 | !(chip->bbt_options & NAND_BBT_USE_FLASH)); | |
4122 | ||
f02ea4e6 HS |
4123 | if (!(chip->options & NAND_OWN_BUFFERS)) { |
4124 | nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize | |
4125 | + mtd->oobsize * 3, GFP_KERNEL); | |
4126 | if (!nbuf) | |
4127 | return -ENOMEM; | |
4128 | nbuf->ecccalc = (uint8_t *)(nbuf + 1); | |
4129 | nbuf->ecccode = nbuf->ecccalc + mtd->oobsize; | |
4130 | nbuf->databuf = nbuf->ecccode + mtd->oobsize; | |
4131 | ||
4132 | chip->buffers = nbuf; | |
4133 | } else { | |
4134 | if (!chip->buffers) | |
4135 | return -ENOMEM; | |
4136 | } | |
4bf63fcb | 4137 | |
7dcdcbef | 4138 | /* Set the internal oob buffer location, just after the page data */ |
784f4d5e | 4139 | chip->oob_poi = chip->buffers->databuf + mtd->writesize; |
1da177e4 | 4140 | |
7aa65bfd | 4141 | /* |
8b6e50c9 | 4142 | * If no default placement scheme is given, select an appropriate one. |
7aa65bfd | 4143 | */ |
97de79e0 | 4144 | if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) { |
61b03bd7 | 4145 | switch (mtd->oobsize) { |
1da177e4 | 4146 | case 8: |
97de79e0 | 4147 | ecc->layout = &nand_oob_8; |
1da177e4 LT |
4148 | break; |
4149 | case 16: | |
97de79e0 | 4150 | ecc->layout = &nand_oob_16; |
1da177e4 LT |
4151 | break; |
4152 | case 64: | |
97de79e0 | 4153 | ecc->layout = &nand_oob_64; |
1da177e4 | 4154 | break; |
81ec5364 | 4155 | case 128: |
97de79e0 | 4156 | ecc->layout = &nand_oob_128; |
81ec5364 | 4157 | break; |
1da177e4 | 4158 | default: |
d0370219 BN |
4159 | pr_warn("No oob scheme defined for oobsize %d\n", |
4160 | mtd->oobsize); | |
1da177e4 LT |
4161 | BUG(); |
4162 | } | |
4163 | } | |
61b03bd7 | 4164 | |
956e944c DW |
4165 | if (!chip->write_page) |
4166 | chip->write_page = nand_write_page; | |
4167 | ||
61b03bd7 | 4168 | /* |
8b6e50c9 | 4169 | * Check ECC mode, default to software if 3byte/512byte hardware ECC is |
7aa65bfd | 4170 | * selected and we have 256 byte pagesize fallback to software ECC |
e0c7d767 | 4171 | */ |
956e944c | 4172 | |
97de79e0 | 4173 | switch (ecc->mode) { |
6e0cb135 SN |
4174 | case NAND_ECC_HW_OOB_FIRST: |
4175 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ | |
97de79e0 | 4176 | if (!ecc->calculate || !ecc->correct || !ecc->hwctl) { |
2ac63d90 | 4177 | pr_warn("No ECC functions supplied; hardware ECC not possible\n"); |
6e0cb135 SN |
4178 | BUG(); |
4179 | } | |
97de79e0 HS |
4180 | if (!ecc->read_page) |
4181 | ecc->read_page = nand_read_page_hwecc_oob_first; | |
6e0cb135 | 4182 | |
6dfc6d25 | 4183 | case NAND_ECC_HW: |
8b6e50c9 | 4184 | /* Use standard hwecc read page function? */ |
97de79e0 HS |
4185 | if (!ecc->read_page) |
4186 | ecc->read_page = nand_read_page_hwecc; | |
4187 | if (!ecc->write_page) | |
4188 | ecc->write_page = nand_write_page_hwecc; | |
4189 | if (!ecc->read_page_raw) | |
4190 | ecc->read_page_raw = nand_read_page_raw; | |
4191 | if (!ecc->write_page_raw) | |
4192 | ecc->write_page_raw = nand_write_page_raw; | |
4193 | if (!ecc->read_oob) | |
4194 | ecc->read_oob = nand_read_oob_std; | |
4195 | if (!ecc->write_oob) | |
4196 | ecc->write_oob = nand_write_oob_std; | |
4197 | if (!ecc->read_subpage) | |
4198 | ecc->read_subpage = nand_read_subpage; | |
44991b3d | 4199 | if (!ecc->write_subpage && ecc->hwctl && ecc->calculate) |
97de79e0 | 4200 | ecc->write_subpage = nand_write_subpage_hwecc; |
f5bbdacc | 4201 | |
6dfc6d25 | 4202 | case NAND_ECC_HW_SYNDROME: |
97de79e0 HS |
4203 | if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && |
4204 | (!ecc->read_page || | |
4205 | ecc->read_page == nand_read_page_hwecc || | |
4206 | !ecc->write_page || | |
4207 | ecc->write_page == nand_write_page_hwecc)) { | |
2ac63d90 | 4208 | pr_warn("No ECC functions supplied; hardware ECC not possible\n"); |
6dfc6d25 TG |
4209 | BUG(); |
4210 | } | |
8b6e50c9 | 4211 | /* Use standard syndrome read/write page function? */ |
97de79e0 HS |
4212 | if (!ecc->read_page) |
4213 | ecc->read_page = nand_read_page_syndrome; | |
4214 | if (!ecc->write_page) | |
4215 | ecc->write_page = nand_write_page_syndrome; | |
4216 | if (!ecc->read_page_raw) | |
4217 | ecc->read_page_raw = nand_read_page_raw_syndrome; | |
4218 | if (!ecc->write_page_raw) | |
4219 | ecc->write_page_raw = nand_write_page_raw_syndrome; | |
4220 | if (!ecc->read_oob) | |
4221 | ecc->read_oob = nand_read_oob_syndrome; | |
4222 | if (!ecc->write_oob) | |
4223 | ecc->write_oob = nand_write_oob_syndrome; | |
4224 | ||
4225 | if (mtd->writesize >= ecc->size) { | |
4226 | if (!ecc->strength) { | |
e2788c98 MD |
4227 | pr_warn("Driver must set ecc.strength when using hardware ECC\n"); |
4228 | BUG(); | |
4229 | } | |
6dfc6d25 | 4230 | break; |
e2788c98 | 4231 | } |
2ac63d90 RM |
4232 | pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n", |
4233 | ecc->size, mtd->writesize); | |
97de79e0 | 4234 | ecc->mode = NAND_ECC_SOFT; |
61b03bd7 | 4235 | |
6dfc6d25 | 4236 | case NAND_ECC_SOFT: |
97de79e0 HS |
4237 | ecc->calculate = nand_calculate_ecc; |
4238 | ecc->correct = nand_correct_data; | |
4239 | ecc->read_page = nand_read_page_swecc; | |
4240 | ecc->read_subpage = nand_read_subpage; | |
4241 | ecc->write_page = nand_write_page_swecc; | |
4242 | ecc->read_page_raw = nand_read_page_raw; | |
4243 | ecc->write_page_raw = nand_write_page_raw; | |
4244 | ecc->read_oob = nand_read_oob_std; | |
4245 | ecc->write_oob = nand_write_oob_std; | |
4246 | if (!ecc->size) | |
4247 | ecc->size = 256; | |
4248 | ecc->bytes = 3; | |
4249 | ecc->strength = 1; | |
1da177e4 | 4250 | break; |
61b03bd7 | 4251 | |
193bd400 ID |
4252 | case NAND_ECC_SOFT_BCH: |
4253 | if (!mtd_nand_has_bch()) { | |
148256fa | 4254 | pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n"); |
193bd400 ID |
4255 | BUG(); |
4256 | } | |
97de79e0 HS |
4257 | ecc->calculate = nand_bch_calculate_ecc; |
4258 | ecc->correct = nand_bch_correct_data; | |
4259 | ecc->read_page = nand_read_page_swecc; | |
4260 | ecc->read_subpage = nand_read_subpage; | |
4261 | ecc->write_page = nand_write_page_swecc; | |
4262 | ecc->read_page_raw = nand_read_page_raw; | |
4263 | ecc->write_page_raw = nand_write_page_raw; | |
4264 | ecc->read_oob = nand_read_oob_std; | |
4265 | ecc->write_oob = nand_write_oob_std; | |
193bd400 | 4266 | /* |
e0377cde AS |
4267 | * Board driver should supply ecc.size and ecc.strength values |
4268 | * to select how many bits are correctable. Otherwise, default | |
4269 | * to 4 bits for large page devices. | |
193bd400 | 4270 | */ |
97de79e0 HS |
4271 | if (!ecc->size && (mtd->oobsize >= 64)) { |
4272 | ecc->size = 512; | |
e0377cde | 4273 | ecc->strength = 4; |
193bd400 | 4274 | } |
e0377cde AS |
4275 | |
4276 | /* See nand_bch_init() for details. */ | |
a8c65d50 BB |
4277 | ecc->bytes = 0; |
4278 | ecc->priv = nand_bch_init(mtd); | |
97de79e0 | 4279 | if (!ecc->priv) { |
9a4d4d69 | 4280 | pr_warn("BCH ECC initialization failed!\n"); |
193bd400 ID |
4281 | BUG(); |
4282 | } | |
4283 | break; | |
4284 | ||
61b03bd7 | 4285 | case NAND_ECC_NONE: |
2ac63d90 | 4286 | pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n"); |
97de79e0 HS |
4287 | ecc->read_page = nand_read_page_raw; |
4288 | ecc->write_page = nand_write_page_raw; | |
4289 | ecc->read_oob = nand_read_oob_std; | |
4290 | ecc->read_page_raw = nand_read_page_raw; | |
4291 | ecc->write_page_raw = nand_write_page_raw; | |
4292 | ecc->write_oob = nand_write_oob_std; | |
4293 | ecc->size = mtd->writesize; | |
4294 | ecc->bytes = 0; | |
4295 | ecc->strength = 0; | |
1da177e4 | 4296 | break; |
956e944c | 4297 | |
1da177e4 | 4298 | default: |
97de79e0 | 4299 | pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode); |
61b03bd7 | 4300 | BUG(); |
1da177e4 | 4301 | } |
61b03bd7 | 4302 | |
9ce244b3 | 4303 | /* For many systems, the standard OOB write also works for raw */ |
97de79e0 HS |
4304 | if (!ecc->read_oob_raw) |
4305 | ecc->read_oob_raw = ecc->read_oob; | |
4306 | if (!ecc->write_oob_raw) | |
4307 | ecc->write_oob_raw = ecc->write_oob; | |
9ce244b3 | 4308 | |
5bd34c09 TG |
4309 | /* |
4310 | * The number of bytes available for a client to place data into | |
8b6e50c9 | 4311 | * the out of band area. |
5bd34c09 | 4312 | */ |
f5b8aa78 BB |
4313 | mtd->oobavail = 0; |
4314 | if (ecc->layout) { | |
4315 | for (i = 0; ecc->layout->oobfree[i].length; i++) | |
4316 | mtd->oobavail += ecc->layout->oobfree[i].length; | |
4317 | } | |
5bd34c09 | 4318 | |
54c39e9b TP |
4319 | /* ECC sanity check: warn if it's too weak */ |
4320 | if (!nand_ecc_strength_good(mtd)) | |
4321 | pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n", | |
4322 | mtd->name); | |
67a9ad9b | 4323 | |
7aa65bfd TG |
4324 | /* |
4325 | * Set the number of read / write steps for one page depending on ECC | |
8b6e50c9 | 4326 | * mode. |
7aa65bfd | 4327 | */ |
97de79e0 HS |
4328 | ecc->steps = mtd->writesize / ecc->size; |
4329 | if (ecc->steps * ecc->size != mtd->writesize) { | |
9a4d4d69 | 4330 | pr_warn("Invalid ECC parameters\n"); |
6dfc6d25 | 4331 | BUG(); |
1da177e4 | 4332 | } |
97de79e0 | 4333 | ecc->total = ecc->steps * ecc->bytes; |
61b03bd7 | 4334 | |
8b6e50c9 | 4335 | /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ |
1d0ed69d | 4336 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { |
97de79e0 | 4337 | switch (ecc->steps) { |
29072b96 TG |
4338 | case 2: |
4339 | mtd->subpage_sft = 1; | |
4340 | break; | |
4341 | case 4: | |
4342 | case 8: | |
81ec5364 | 4343 | case 16: |
29072b96 TG |
4344 | mtd->subpage_sft = 2; |
4345 | break; | |
4346 | } | |
4347 | } | |
4348 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; | |
4349 | ||
04bbd0ea | 4350 | /* Initialize state */ |
ace4dfee | 4351 | chip->state = FL_READY; |
1da177e4 | 4352 | |
1da177e4 | 4353 | /* Invalidate the pagebuffer reference */ |
ace4dfee | 4354 | chip->pagebuf = -1; |
1da177e4 | 4355 | |
a5ff4f10 | 4356 | /* Large page NAND with SOFT_ECC should support subpage reads */ |
4007e2d1 RL |
4357 | switch (ecc->mode) { |
4358 | case NAND_ECC_SOFT: | |
4359 | case NAND_ECC_SOFT_BCH: | |
4360 | if (chip->page_shift > 9) | |
4361 | chip->options |= NAND_SUBPAGE_READ; | |
4362 | break; | |
4363 | ||
4364 | default: | |
4365 | break; | |
4366 | } | |
a5ff4f10 | 4367 | |
1da177e4 | 4368 | /* Fill in remaining MTD driver data */ |
963d1c28 | 4369 | mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH; |
93edbad6 ML |
4370 | mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : |
4371 | MTD_CAP_NANDFLASH; | |
3c3c10bb AB |
4372 | mtd->_erase = nand_erase; |
4373 | mtd->_point = NULL; | |
4374 | mtd->_unpoint = NULL; | |
4375 | mtd->_read = nand_read; | |
4376 | mtd->_write = nand_write; | |
4377 | mtd->_panic_write = panic_nand_write; | |
4378 | mtd->_read_oob = nand_read_oob; | |
4379 | mtd->_write_oob = nand_write_oob; | |
4380 | mtd->_sync = nand_sync; | |
4381 | mtd->_lock = NULL; | |
4382 | mtd->_unlock = NULL; | |
4383 | mtd->_suspend = nand_suspend; | |
4384 | mtd->_resume = nand_resume; | |
72ea4036 | 4385 | mtd->_reboot = nand_shutdown; |
8471bb73 | 4386 | mtd->_block_isreserved = nand_block_isreserved; |
3c3c10bb AB |
4387 | mtd->_block_isbad = nand_block_isbad; |
4388 | mtd->_block_markbad = nand_block_markbad; | |
cbcab65a | 4389 | mtd->writebufsize = mtd->writesize; |
1da177e4 | 4390 | |
6a918bad | 4391 | /* propagate ecc info to mtd_info */ |
97de79e0 HS |
4392 | mtd->ecclayout = ecc->layout; |
4393 | mtd->ecc_strength = ecc->strength; | |
4394 | mtd->ecc_step_size = ecc->size; | |
ea3b2ea2 SL |
4395 | /* |
4396 | * Initialize bitflip_threshold to its default prior scan_bbt() call. | |
4397 | * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be | |
4398 | * properly set. | |
4399 | */ | |
4400 | if (!mtd->bitflip_threshold) | |
240181fd | 4401 | mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4); |
1da177e4 | 4402 | |
0040bf38 | 4403 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 4404 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 4405 | return 0; |
1da177e4 LT |
4406 | |
4407 | /* Build bad block table */ | |
ace4dfee | 4408 | return chip->scan_bbt(mtd); |
1da177e4 | 4409 | } |
7351d3a5 | 4410 | EXPORT_SYMBOL(nand_scan_tail); |
1da177e4 | 4411 | |
8b6e50c9 BN |
4412 | /* |
4413 | * is_module_text_address() isn't exported, and it's mostly a pointless | |
7351d3a5 | 4414 | * test if this is a module _anyway_ -- they'd have to try _really_ hard |
8b6e50c9 BN |
4415 | * to call us from in-kernel code if the core NAND support is modular. |
4416 | */ | |
3b85c321 DW |
4417 | #ifdef MODULE |
4418 | #define caller_is_module() (1) | |
4419 | #else | |
4420 | #define caller_is_module() \ | |
a6e6abd5 | 4421 | is_module_text_address((unsigned long)__builtin_return_address(0)) |
3b85c321 DW |
4422 | #endif |
4423 | ||
4424 | /** | |
4425 | * nand_scan - [NAND Interface] Scan for the NAND device | |
8b6e50c9 BN |
4426 | * @mtd: MTD device structure |
4427 | * @maxchips: number of chips to scan for | |
3b85c321 | 4428 | * |
8b6e50c9 BN |
4429 | * This fills out all the uninitialized function pointers with the defaults. |
4430 | * The flash ID is read and the mtd/chip structures are filled with the | |
20c07a5b | 4431 | * appropriate values. |
3b85c321 DW |
4432 | */ |
4433 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
4434 | { | |
4435 | int ret; | |
4436 | ||
5e81e88a | 4437 | ret = nand_scan_ident(mtd, maxchips, NULL); |
3b85c321 DW |
4438 | if (!ret) |
4439 | ret = nand_scan_tail(mtd); | |
4440 | return ret; | |
4441 | } | |
7351d3a5 | 4442 | EXPORT_SYMBOL(nand_scan); |
3b85c321 | 4443 | |
1da177e4 | 4444 | /** |
61b03bd7 | 4445 | * nand_release - [NAND Interface] Free resources held by the NAND device |
8b6e50c9 BN |
4446 | * @mtd: MTD device structure |
4447 | */ | |
e0c7d767 | 4448 | void nand_release(struct mtd_info *mtd) |
1da177e4 | 4449 | { |
862eba51 | 4450 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 4451 | |
193bd400 ID |
4452 | if (chip->ecc.mode == NAND_ECC_SOFT_BCH) |
4453 | nand_bch_free((struct nand_bch_control *)chip->ecc.priv); | |
4454 | ||
5ffcaf3d | 4455 | mtd_device_unregister(mtd); |
1da177e4 | 4456 | |
fa671646 | 4457 | /* Free bad block table memory */ |
ace4dfee | 4458 | kfree(chip->bbt); |
4bf63fcb DW |
4459 | if (!(chip->options & NAND_OWN_BUFFERS)) |
4460 | kfree(chip->buffers); | |
58373ff0 BN |
4461 | |
4462 | /* Free bad block descriptor memory */ | |
4463 | if (chip->badblock_pattern && chip->badblock_pattern->options | |
4464 | & NAND_BBT_DYNAMICSTRUCT) | |
4465 | kfree(chip->badblock_pattern); | |
1da177e4 | 4466 | } |
e0c7d767 | 4467 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 RP |
4468 | |
4469 | static int __init nand_base_init(void) | |
4470 | { | |
4471 | led_trigger_register_simple("nand-disk", &nand_led_trigger); | |
4472 | return 0; | |
4473 | } | |
4474 | ||
4475 | static void __exit nand_base_exit(void) | |
4476 | { | |
4477 | led_trigger_unregister_simple(nand_led_trigger); | |
4478 | } | |
4479 | ||
4480 | module_init(nand_base_init); | |
4481 | module_exit(nand_base_exit); | |
4482 | ||
e0c7d767 | 4483 | MODULE_LICENSE("GPL"); |
7351d3a5 FF |
4484 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); |
4485 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
e0c7d767 | 4486 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |