Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nandids.c | |
3 | * | |
4 | * Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de) | |
bd7bcf52 | 5 | * |
61b03bd7 | 6 | * $Id: nand_ids.c,v 1.16 2005/11/07 11:14:31 gleixner Exp $ |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | */ | |
13 | #include <linux/module.h> | |
14 | #include <linux/mtd/nand.h> | |
15 | /* | |
16 | * Chip ID list | |
61b03bd7 | 17 | * |
1da177e4 LT |
18 | * Name. ID code, pagesize, chipsize in MegaByte, eraseblock size, |
19 | * options | |
61b03bd7 | 20 | * |
7a30601b TG |
21 | * Pagesize; 0, 256, 512 |
22 | * 0 get this information from the extended chip ID | |
1da177e4 | 23 | + 256 256 Byte page size |
61b03bd7 | 24 | * 512 512 Byte page size |
1da177e4 LT |
25 | */ |
26 | struct nand_flash_dev nand_flash_ids[] = { | |
7a30601b TG |
27 | {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0}, |
28 | {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0}, | |
29 | {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0}, | |
30 | {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0}, | |
31 | {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0}, | |
32 | {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0}, | |
33 | {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0}, | |
34 | {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0}, | |
35 | {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0}, | |
36 | {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0}, | |
37 | ||
38 | {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0}, | |
39 | {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0}, | |
40 | {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16}, | |
41 | {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16}, | |
42 | ||
43 | {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0}, | |
44 | {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0}, | |
45 | {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16}, | |
46 | {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16}, | |
47 | ||
48 | {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0}, | |
49 | {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0}, | |
50 | {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16}, | |
51 | {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16}, | |
52 | ||
53 | {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0}, | |
54 | {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0}, | |
55 | {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16}, | |
56 | {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16}, | |
57 | ||
58 | {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0}, | |
59 | {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0}, | |
60 | {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0}, | |
61 | {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16}, | |
62 | {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16}, | |
63 | {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16}, | |
64 | {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16}, | |
65 | ||
66 | {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0}, | |
67 | ||
68 | /* | |
69 | * These are the new chips with large page size. The pagesize and the | |
70 | * erasesize is determined from the extended id bytes | |
71 | */ | |
72 | #define LP_OPTIONS (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR) | |
73 | #define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16) | |
74 | ||
bd7bcf52 | 75 | /*512 Megabit */ |
7a30601b TG |
76 | {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS}, |
77 | {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS}, | |
78 | {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16}, | |
79 | {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16}, | |
61b03bd7 | 80 | |
1da177e4 | 81 | /* 1 Gigabit */ |
7a30601b TG |
82 | {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS}, |
83 | {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS}, | |
84 | {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16}, | |
85 | {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16}, | |
1da177e4 LT |
86 | |
87 | /* 2 Gigabit */ | |
7a30601b TG |
88 | {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS}, |
89 | {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS}, | |
90 | {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16}, | |
91 | {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16}, | |
61b03bd7 | 92 | |
1da177e4 | 93 | /* 4 Gigabit */ |
7a30601b TG |
94 | {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS}, |
95 | {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS}, | |
96 | {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16}, | |
97 | {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16}, | |
61b03bd7 | 98 | |
1da177e4 | 99 | /* 8 Gigabit */ |
7a30601b TG |
100 | {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS}, |
101 | {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS}, | |
102 | {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16}, | |
103 | {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16}, | |
1da177e4 LT |
104 | |
105 | /* 16 Gigabit */ | |
7a30601b TG |
106 | {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS}, |
107 | {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS}, | |
108 | {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16}, | |
109 | {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16}, | |
110 | ||
111 | /* | |
112 | * Renesas AND 1 Gigabit. Those chips do not support extended id and | |
113 | * have a strange page/block layout ! The chosen minimum erasesize is | |
114 | * 4 * 2 * 2048 = 16384 Byte, as those chips have an array of 4 page | |
115 | * planes 1 block = 2 pages, but due to plane arrangement the blocks | |
116 | * 0-3 consists of page 0 + 4,1 + 5, 2 + 6, 3 + 7 Anyway JFFS2 would | |
117 | * increase the eraseblock size so we chose a combined one which can be | |
118 | * erased in one go There are more speed improvements for reads and | |
119 | * writes possible, but not implemented now | |
1da177e4 | 120 | */ |
7a30601b TG |
121 | {"AND 128MiB 3,3V 8-bit", 0x01, 2048, 128, 0x4000, |
122 | NAND_IS_AND | NAND_NO_AUTOINCR |NAND_NO_READRDY | NAND_4PAGE_ARRAY | | |
123 | BBT_AUTO_REFRESH | |
124 | }, | |
1da177e4 LT |
125 | |
126 | {NULL,} | |
127 | }; | |
128 | ||
129 | /* | |
130 | * Manufacturer ID list | |
131 | */ | |
132 | struct nand_manufacturers nand_manuf_ids[] = { | |
133 | {NAND_MFR_TOSHIBA, "Toshiba"}, | |
134 | {NAND_MFR_SAMSUNG, "Samsung"}, | |
135 | {NAND_MFR_FUJITSU, "Fujitsu"}, | |
136 | {NAND_MFR_NATIONAL, "National"}, | |
137 | {NAND_MFR_RENESAS, "Renesas"}, | |
138 | {NAND_MFR_STMICRO, "ST Micro"}, | |
e0c7d767 | 139 | {NAND_MFR_HYNIX, "Hynix"}, |
8c60e547 | 140 | {NAND_MFR_MICRON, "Micron"}, |
1da177e4 LT |
141 | {0x0, "Unknown"} |
142 | }; | |
143 | ||
e0c7d767 DW |
144 | EXPORT_SYMBOL(nand_manuf_ids); |
145 | EXPORT_SYMBOL(nand_flash_ids); | |
1da177e4 | 146 | |
e0c7d767 DW |
147 | MODULE_LICENSE("GPL"); |
148 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
149 | MODULE_DESCRIPTION("Nand device & manufacturer IDs"); |