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67ce04bf VS |
1 | /* |
2 | * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com> | |
3 | * Copyright © 2004 Micron Technology Inc. | |
4 | * Copyright © 2004 David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/platform_device.h> | |
763e7359 | 12 | #include <linux/dmaengine.h> |
67ce04bf VS |
13 | #include <linux/dma-mapping.h> |
14 | #include <linux/delay.h> | |
a0e5cc58 | 15 | #include <linux/module.h> |
4e070376 | 16 | #include <linux/interrupt.h> |
c276aca4 | 17 | #include <linux/jiffies.h> |
18 | #include <linux/sched.h> | |
67ce04bf VS |
19 | #include <linux/mtd/mtd.h> |
20 | #include <linux/mtd/nand.h> | |
21 | #include <linux/mtd/partitions.h> | |
763e7359 | 22 | #include <linux/omap-dma.h> |
67ce04bf | 23 | #include <linux/io.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
67ce04bf | 25 | |
0e618ef0 ID |
26 | #ifdef CONFIG_MTD_NAND_OMAP_BCH |
27 | #include <linux/bch.h> | |
28 | #endif | |
29 | ||
2203747c | 30 | #include <linux/platform_data/mtd-nand-omap2.h> |
67ce04bf | 31 | |
67ce04bf | 32 | #define DRIVER_NAME "omap2-nand" |
4e070376 | 33 | #define OMAP_NAND_TIMEOUT_MS 5000 |
67ce04bf | 34 | |
67ce04bf VS |
35 | #define NAND_Ecc_P1e (1 << 0) |
36 | #define NAND_Ecc_P2e (1 << 1) | |
37 | #define NAND_Ecc_P4e (1 << 2) | |
38 | #define NAND_Ecc_P8e (1 << 3) | |
39 | #define NAND_Ecc_P16e (1 << 4) | |
40 | #define NAND_Ecc_P32e (1 << 5) | |
41 | #define NAND_Ecc_P64e (1 << 6) | |
42 | #define NAND_Ecc_P128e (1 << 7) | |
43 | #define NAND_Ecc_P256e (1 << 8) | |
44 | #define NAND_Ecc_P512e (1 << 9) | |
45 | #define NAND_Ecc_P1024e (1 << 10) | |
46 | #define NAND_Ecc_P2048e (1 << 11) | |
47 | ||
48 | #define NAND_Ecc_P1o (1 << 16) | |
49 | #define NAND_Ecc_P2o (1 << 17) | |
50 | #define NAND_Ecc_P4o (1 << 18) | |
51 | #define NAND_Ecc_P8o (1 << 19) | |
52 | #define NAND_Ecc_P16o (1 << 20) | |
53 | #define NAND_Ecc_P32o (1 << 21) | |
54 | #define NAND_Ecc_P64o (1 << 22) | |
55 | #define NAND_Ecc_P128o (1 << 23) | |
56 | #define NAND_Ecc_P256o (1 << 24) | |
57 | #define NAND_Ecc_P512o (1 << 25) | |
58 | #define NAND_Ecc_P1024o (1 << 26) | |
59 | #define NAND_Ecc_P2048o (1 << 27) | |
60 | ||
61 | #define TF(value) (value ? 1 : 0) | |
62 | ||
63 | #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0) | |
64 | #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1) | |
65 | #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2) | |
66 | #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3) | |
67 | #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4) | |
68 | #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5) | |
69 | #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6) | |
70 | #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7) | |
71 | ||
72 | #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0) | |
73 | #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1) | |
74 | #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2) | |
75 | #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3) | |
76 | #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4) | |
77 | #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5) | |
78 | #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6) | |
79 | #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7) | |
80 | ||
81 | #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0) | |
82 | #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1) | |
83 | #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2) | |
84 | #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3) | |
85 | #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4) | |
86 | #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5) | |
87 | #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6) | |
88 | #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7) | |
89 | ||
90 | #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0) | |
91 | #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1) | |
92 | #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2) | |
93 | #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3) | |
94 | #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4) | |
95 | #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5) | |
96 | #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6) | |
97 | #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7) | |
98 | ||
99 | #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) | |
100 | #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) | |
101 | ||
65b97cf6 AM |
102 | #define PREFETCH_CONFIG1_CS_SHIFT 24 |
103 | #define ECC_CONFIG_CS_SHIFT 1 | |
104 | #define CS_MASK 0x7 | |
105 | #define ENABLE_PREFETCH (0x1 << 7) | |
106 | #define DMA_MPU_MODE_SHIFT 2 | |
2ef9f3dd | 107 | #define ECCSIZE0_SHIFT 12 |
65b97cf6 AM |
108 | #define ECCSIZE1_SHIFT 22 |
109 | #define ECC1RESULTSIZE 0x1 | |
110 | #define ECCCLEAR 0x100 | |
111 | #define ECC1 0x1 | |
47f88af4 AM |
112 | #define PREFETCH_FIFOTHRESHOLD_MAX 0x40 |
113 | #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) | |
114 | #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) | |
115 | #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) | |
116 | #define STATUS_BUFF_EMPTY 0x00000001 | |
65b97cf6 | 117 | |
d5e7c864 LV |
118 | #define OMAP24XX_DMA_GPMC 4 |
119 | ||
f040d332 SG |
120 | /* oob info generated runtime depending on ecc algorithm and layout selected */ |
121 | static struct nand_ecclayout omap_oobinfo; | |
122 | /* Define some generic bad / good block scan pattern which are used | |
123 | * while scanning a device for factory marked good / bad blocks | |
124 | */ | |
125 | static uint8_t scan_ff_pattern[] = { 0xff }; | |
126 | static struct nand_bbt_descr bb_descrip_flashbased = { | |
127 | .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES, | |
128 | .offs = 0, | |
129 | .len = 1, | |
130 | .pattern = scan_ff_pattern, | |
131 | }; | |
dfe32893 | 132 | |
59e9c5ae | 133 | |
67ce04bf VS |
134 | struct omap_nand_info { |
135 | struct nand_hw_control controller; | |
136 | struct omap_nand_platform_data *pdata; | |
137 | struct mtd_info mtd; | |
67ce04bf VS |
138 | struct nand_chip nand; |
139 | struct platform_device *pdev; | |
140 | ||
141 | int gpmc_cs; | |
142 | unsigned long phys_base; | |
9c4c2f8b | 143 | unsigned long mem_size; |
dfe32893 | 144 | struct completion comp; |
763e7359 | 145 | struct dma_chan *dma; |
5c468455 AM |
146 | int gpmc_irq_fifo; |
147 | int gpmc_irq_count; | |
4e070376 SG |
148 | enum { |
149 | OMAP_NAND_IO_READ = 0, /* read */ | |
150 | OMAP_NAND_IO_WRITE, /* write */ | |
151 | } iomode; | |
152 | u_char *buf; | |
153 | int buf_len; | |
65b97cf6 | 154 | struct gpmc_nand_regs reg; |
0e618ef0 ID |
155 | |
156 | #ifdef CONFIG_MTD_NAND_OMAP_BCH | |
157 | struct bch_control *bch; | |
158 | struct nand_ecclayout ecclayout; | |
159 | #endif | |
67ce04bf VS |
160 | }; |
161 | ||
65b97cf6 AM |
162 | /** |
163 | * omap_prefetch_enable - configures and starts prefetch transfer | |
164 | * @cs: cs (chip select) number | |
165 | * @fifo_th: fifo threshold to be used for read/ write | |
166 | * @dma_mode: dma mode enable (1) or disable (0) | |
167 | * @u32_count: number of bytes to be transferred | |
168 | * @is_write: prefetch read(0) or write post(1) mode | |
169 | */ | |
170 | static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode, | |
171 | unsigned int u32_count, int is_write, struct omap_nand_info *info) | |
172 | { | |
173 | u32 val; | |
174 | ||
175 | if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) | |
176 | return -1; | |
177 | ||
178 | if (readl(info->reg.gpmc_prefetch_control)) | |
179 | return -EBUSY; | |
180 | ||
181 | /* Set the amount of bytes to be prefetched */ | |
182 | writel(u32_count, info->reg.gpmc_prefetch_config2); | |
183 | ||
184 | /* Set dma/mpu mode, the prefetch read / post write and | |
185 | * enable the engine. Set which cs is has requested for. | |
186 | */ | |
187 | val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) | | |
188 | PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH | | |
189 | (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write)); | |
190 | writel(val, info->reg.gpmc_prefetch_config1); | |
191 | ||
192 | /* Start the prefetch engine */ | |
193 | writel(0x1, info->reg.gpmc_prefetch_control); | |
194 | ||
195 | return 0; | |
196 | } | |
197 | ||
198 | /** | |
199 | * omap_prefetch_reset - disables and stops the prefetch engine | |
200 | */ | |
201 | static int omap_prefetch_reset(int cs, struct omap_nand_info *info) | |
202 | { | |
203 | u32 config1; | |
204 | ||
205 | /* check if the same module/cs is trying to reset */ | |
206 | config1 = readl(info->reg.gpmc_prefetch_config1); | |
207 | if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs) | |
208 | return -EINVAL; | |
209 | ||
210 | /* Stop the PFPW engine */ | |
211 | writel(0x0, info->reg.gpmc_prefetch_control); | |
212 | ||
213 | /* Reset/disable the PFPW engine */ | |
214 | writel(0x0, info->reg.gpmc_prefetch_config1); | |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
67ce04bf VS |
219 | /** |
220 | * omap_hwcontrol - hardware specific access to control-lines | |
221 | * @mtd: MTD device structure | |
222 | * @cmd: command to device | |
223 | * @ctrl: | |
224 | * NAND_NCE: bit 0 -> don't care | |
225 | * NAND_CLE: bit 1 -> Command Latch | |
226 | * NAND_ALE: bit 2 -> Address Latch | |
227 | * | |
228 | * NOTE: boards may use different bits for these!! | |
229 | */ | |
230 | static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
231 | { | |
232 | struct omap_nand_info *info = container_of(mtd, | |
233 | struct omap_nand_info, mtd); | |
67ce04bf | 234 | |
2c01946c SG |
235 | if (cmd != NAND_CMD_NONE) { |
236 | if (ctrl & NAND_CLE) | |
65b97cf6 | 237 | writeb(cmd, info->reg.gpmc_nand_command); |
2c01946c SG |
238 | |
239 | else if (ctrl & NAND_ALE) | |
65b97cf6 | 240 | writeb(cmd, info->reg.gpmc_nand_address); |
2c01946c SG |
241 | |
242 | else /* NAND_NCE */ | |
65b97cf6 | 243 | writeb(cmd, info->reg.gpmc_nand_data); |
2c01946c | 244 | } |
67ce04bf VS |
245 | } |
246 | ||
59e9c5ae | 247 | /** |
248 | * omap_read_buf8 - read data from NAND controller into buffer | |
249 | * @mtd: MTD device structure | |
250 | * @buf: buffer to store date | |
251 | * @len: number of bytes to read | |
252 | */ | |
253 | static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len) | |
254 | { | |
255 | struct nand_chip *nand = mtd->priv; | |
256 | ||
257 | ioread8_rep(nand->IO_ADDR_R, buf, len); | |
258 | } | |
259 | ||
260 | /** | |
261 | * omap_write_buf8 - write buffer to NAND controller | |
262 | * @mtd: MTD device structure | |
263 | * @buf: data buffer | |
264 | * @len: number of bytes to write | |
265 | */ | |
266 | static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len) | |
267 | { | |
268 | struct omap_nand_info *info = container_of(mtd, | |
269 | struct omap_nand_info, mtd); | |
270 | u_char *p = (u_char *)buf; | |
2c01946c | 271 | u32 status = 0; |
59e9c5ae | 272 | |
273 | while (len--) { | |
274 | iowrite8(*p++, info->nand.IO_ADDR_W); | |
2c01946c SG |
275 | /* wait until buffer is available for write */ |
276 | do { | |
65b97cf6 | 277 | status = readl(info->reg.gpmc_status) & |
47f88af4 | 278 | STATUS_BUFF_EMPTY; |
2c01946c | 279 | } while (!status); |
59e9c5ae | 280 | } |
281 | } | |
282 | ||
67ce04bf VS |
283 | /** |
284 | * omap_read_buf16 - read data from NAND controller into buffer | |
285 | * @mtd: MTD device structure | |
286 | * @buf: buffer to store date | |
287 | * @len: number of bytes to read | |
288 | */ | |
289 | static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len) | |
290 | { | |
291 | struct nand_chip *nand = mtd->priv; | |
292 | ||
59e9c5ae | 293 | ioread16_rep(nand->IO_ADDR_R, buf, len / 2); |
67ce04bf VS |
294 | } |
295 | ||
296 | /** | |
297 | * omap_write_buf16 - write buffer to NAND controller | |
298 | * @mtd: MTD device structure | |
299 | * @buf: data buffer | |
300 | * @len: number of bytes to write | |
301 | */ | |
302 | static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len) | |
303 | { | |
304 | struct omap_nand_info *info = container_of(mtd, | |
305 | struct omap_nand_info, mtd); | |
306 | u16 *p = (u16 *) buf; | |
2c01946c | 307 | u32 status = 0; |
67ce04bf VS |
308 | /* FIXME try bursts of writesw() or DMA ... */ |
309 | len >>= 1; | |
310 | ||
311 | while (len--) { | |
59e9c5ae | 312 | iowrite16(*p++, info->nand.IO_ADDR_W); |
2c01946c SG |
313 | /* wait until buffer is available for write */ |
314 | do { | |
65b97cf6 | 315 | status = readl(info->reg.gpmc_status) & |
47f88af4 | 316 | STATUS_BUFF_EMPTY; |
2c01946c | 317 | } while (!status); |
67ce04bf VS |
318 | } |
319 | } | |
59e9c5ae | 320 | |
321 | /** | |
322 | * omap_read_buf_pref - read data from NAND controller into buffer | |
323 | * @mtd: MTD device structure | |
324 | * @buf: buffer to store date | |
325 | * @len: number of bytes to read | |
326 | */ | |
327 | static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) | |
328 | { | |
329 | struct omap_nand_info *info = container_of(mtd, | |
330 | struct omap_nand_info, mtd); | |
2c01946c | 331 | uint32_t r_count = 0; |
59e9c5ae | 332 | int ret = 0; |
333 | u32 *p = (u32 *)buf; | |
334 | ||
335 | /* take care of subpage reads */ | |
c3341d0c VS |
336 | if (len % 4) { |
337 | if (info->nand.options & NAND_BUSWIDTH_16) | |
338 | omap_read_buf16(mtd, buf, len % 4); | |
339 | else | |
340 | omap_read_buf8(mtd, buf, len % 4); | |
341 | p = (u32 *) (buf + len % 4); | |
342 | len -= len % 4; | |
59e9c5ae | 343 | } |
59e9c5ae | 344 | |
345 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
346 | ret = omap_prefetch_enable(info->gpmc_cs, |
347 | PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info); | |
59e9c5ae | 348 | if (ret) { |
349 | /* PFPW engine is busy, use cpu copy method */ | |
350 | if (info->nand.options & NAND_BUSWIDTH_16) | |
c5d8c0ca | 351 | omap_read_buf16(mtd, (u_char *)p, len); |
59e9c5ae | 352 | else |
c5d8c0ca | 353 | omap_read_buf8(mtd, (u_char *)p, len); |
59e9c5ae | 354 | } else { |
355 | do { | |
65b97cf6 | 356 | r_count = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 357 | r_count = PREFETCH_STATUS_FIFO_CNT(r_count); |
2c01946c SG |
358 | r_count = r_count >> 2; |
359 | ioread32_rep(info->nand.IO_ADDR_R, p, r_count); | |
59e9c5ae | 360 | p += r_count; |
361 | len -= r_count << 2; | |
362 | } while (len); | |
59e9c5ae | 363 | /* disable and stop the PFPW engine */ |
65b97cf6 | 364 | omap_prefetch_reset(info->gpmc_cs, info); |
59e9c5ae | 365 | } |
366 | } | |
367 | ||
368 | /** | |
369 | * omap_write_buf_pref - write buffer to NAND controller | |
370 | * @mtd: MTD device structure | |
371 | * @buf: data buffer | |
372 | * @len: number of bytes to write | |
373 | */ | |
374 | static void omap_write_buf_pref(struct mtd_info *mtd, | |
375 | const u_char *buf, int len) | |
376 | { | |
377 | struct omap_nand_info *info = container_of(mtd, | |
378 | struct omap_nand_info, mtd); | |
4e070376 | 379 | uint32_t w_count = 0; |
59e9c5ae | 380 | int i = 0, ret = 0; |
c5d8c0ca | 381 | u16 *p = (u16 *)buf; |
4e070376 | 382 | unsigned long tim, limit; |
65b97cf6 | 383 | u32 val; |
59e9c5ae | 384 | |
385 | /* take care of subpage writes */ | |
386 | if (len % 2 != 0) { | |
2c01946c | 387 | writeb(*buf, info->nand.IO_ADDR_W); |
59e9c5ae | 388 | p = (u16 *)(buf + 1); |
389 | len--; | |
390 | } | |
391 | ||
392 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
393 | ret = omap_prefetch_enable(info->gpmc_cs, |
394 | PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info); | |
59e9c5ae | 395 | if (ret) { |
396 | /* PFPW engine is busy, use cpu copy method */ | |
397 | if (info->nand.options & NAND_BUSWIDTH_16) | |
c5d8c0ca | 398 | omap_write_buf16(mtd, (u_char *)p, len); |
59e9c5ae | 399 | else |
c5d8c0ca | 400 | omap_write_buf8(mtd, (u_char *)p, len); |
59e9c5ae | 401 | } else { |
2c01946c | 402 | while (len) { |
65b97cf6 | 403 | w_count = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 404 | w_count = PREFETCH_STATUS_FIFO_CNT(w_count); |
2c01946c | 405 | w_count = w_count >> 1; |
59e9c5ae | 406 | for (i = 0; (i < w_count) && len; i++, len -= 2) |
2c01946c | 407 | iowrite16(*p++, info->nand.IO_ADDR_W); |
59e9c5ae | 408 | } |
2c01946c | 409 | /* wait for data to flushed-out before reset the prefetch */ |
4e070376 SG |
410 | tim = 0; |
411 | limit = (loops_per_jiffy * | |
412 | msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 | 413 | do { |
4e070376 | 414 | cpu_relax(); |
65b97cf6 | 415 | val = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 416 | val = PREFETCH_STATUS_COUNT(val); |
65b97cf6 | 417 | } while (val && (tim++ < limit)); |
4e070376 | 418 | |
59e9c5ae | 419 | /* disable and stop the PFPW engine */ |
65b97cf6 | 420 | omap_prefetch_reset(info->gpmc_cs, info); |
59e9c5ae | 421 | } |
422 | } | |
423 | ||
dfe32893 | 424 | /* |
2df41d05 | 425 | * omap_nand_dma_callback: callback on the completion of dma transfer |
dfe32893 | 426 | * @data: pointer to completion data structure |
427 | */ | |
763e7359 RK |
428 | static void omap_nand_dma_callback(void *data) |
429 | { | |
430 | complete((struct completion *) data); | |
431 | } | |
dfe32893 | 432 | |
433 | /* | |
4cacbe22 | 434 | * omap_nand_dma_transfer: configure and start dma transfer |
dfe32893 | 435 | * @mtd: MTD device structure |
436 | * @addr: virtual address in RAM of source/destination | |
437 | * @len: number of data bytes to be transferred | |
438 | * @is_write: flag for read/write operation | |
439 | */ | |
440 | static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, | |
441 | unsigned int len, int is_write) | |
442 | { | |
443 | struct omap_nand_info *info = container_of(mtd, | |
444 | struct omap_nand_info, mtd); | |
2df41d05 | 445 | struct dma_async_tx_descriptor *tx; |
dfe32893 | 446 | enum dma_data_direction dir = is_write ? DMA_TO_DEVICE : |
447 | DMA_FROM_DEVICE; | |
2df41d05 | 448 | struct scatterlist sg; |
4e070376 | 449 | unsigned long tim, limit; |
2df41d05 RK |
450 | unsigned n; |
451 | int ret; | |
65b97cf6 | 452 | u32 val; |
dfe32893 | 453 | |
454 | if (addr >= high_memory) { | |
455 | struct page *p1; | |
456 | ||
457 | if (((size_t)addr & PAGE_MASK) != | |
458 | ((size_t)(addr + len - 1) & PAGE_MASK)) | |
459 | goto out_copy; | |
460 | p1 = vmalloc_to_page(addr); | |
461 | if (!p1) | |
462 | goto out_copy; | |
463 | addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK); | |
464 | } | |
465 | ||
2df41d05 RK |
466 | sg_init_one(&sg, addr, len); |
467 | n = dma_map_sg(info->dma->device->dev, &sg, 1, dir); | |
468 | if (n == 0) { | |
dfe32893 | 469 | dev_err(&info->pdev->dev, |
470 | "Couldn't DMA map a %d byte buffer\n", len); | |
471 | goto out_copy; | |
472 | } | |
473 | ||
2df41d05 RK |
474 | tx = dmaengine_prep_slave_sg(info->dma, &sg, n, |
475 | is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, | |
476 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
477 | if (!tx) | |
478 | goto out_copy_unmap; | |
479 | ||
480 | tx->callback = omap_nand_dma_callback; | |
481 | tx->callback_param = &info->comp; | |
482 | dmaengine_submit(tx); | |
483 | ||
65b97cf6 AM |
484 | /* configure and start prefetch transfer */ |
485 | ret = omap_prefetch_enable(info->gpmc_cs, | |
486 | PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info); | |
dfe32893 | 487 | if (ret) |
4e070376 | 488 | /* PFPW engine is busy, use cpu copy method */ |
d7efe228 | 489 | goto out_copy_unmap; |
dfe32893 | 490 | |
491 | init_completion(&info->comp); | |
2df41d05 | 492 | dma_async_issue_pending(info->dma); |
dfe32893 | 493 | |
494 | /* setup and start DMA using dma_addr */ | |
495 | wait_for_completion(&info->comp); | |
4e070376 SG |
496 | tim = 0; |
497 | limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 AM |
498 | |
499 | do { | |
4e070376 | 500 | cpu_relax(); |
65b97cf6 | 501 | val = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 502 | val = PREFETCH_STATUS_COUNT(val); |
65b97cf6 | 503 | } while (val && (tim++ < limit)); |
dfe32893 | 504 | |
dfe32893 | 505 | /* disable and stop the PFPW engine */ |
65b97cf6 | 506 | omap_prefetch_reset(info->gpmc_cs, info); |
dfe32893 | 507 | |
2df41d05 | 508 | dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); |
dfe32893 | 509 | return 0; |
510 | ||
d7efe228 | 511 | out_copy_unmap: |
2df41d05 | 512 | dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); |
dfe32893 | 513 | out_copy: |
514 | if (info->nand.options & NAND_BUSWIDTH_16) | |
515 | is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len) | |
516 | : omap_write_buf16(mtd, (u_char *) addr, len); | |
517 | else | |
518 | is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len) | |
519 | : omap_write_buf8(mtd, (u_char *) addr, len); | |
520 | return 0; | |
521 | } | |
dfe32893 | 522 | |
523 | /** | |
524 | * omap_read_buf_dma_pref - read data from NAND controller into buffer | |
525 | * @mtd: MTD device structure | |
526 | * @buf: buffer to store date | |
527 | * @len: number of bytes to read | |
528 | */ | |
529 | static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len) | |
530 | { | |
531 | if (len <= mtd->oobsize) | |
532 | omap_read_buf_pref(mtd, buf, len); | |
533 | else | |
534 | /* start transfer in DMA mode */ | |
535 | omap_nand_dma_transfer(mtd, buf, len, 0x0); | |
536 | } | |
537 | ||
538 | /** | |
539 | * omap_write_buf_dma_pref - write buffer to NAND controller | |
540 | * @mtd: MTD device structure | |
541 | * @buf: data buffer | |
542 | * @len: number of bytes to write | |
543 | */ | |
544 | static void omap_write_buf_dma_pref(struct mtd_info *mtd, | |
545 | const u_char *buf, int len) | |
546 | { | |
547 | if (len <= mtd->oobsize) | |
548 | omap_write_buf_pref(mtd, buf, len); | |
549 | else | |
550 | /* start transfer in DMA mode */ | |
bdaefc41 | 551 | omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1); |
dfe32893 | 552 | } |
553 | ||
4e070376 | 554 | /* |
4cacbe22 | 555 | * omap_nand_irq - GPMC irq handler |
4e070376 SG |
556 | * @this_irq: gpmc irq number |
557 | * @dev: omap_nand_info structure pointer is passed here | |
558 | */ | |
559 | static irqreturn_t omap_nand_irq(int this_irq, void *dev) | |
560 | { | |
561 | struct omap_nand_info *info = (struct omap_nand_info *) dev; | |
562 | u32 bytes; | |
4e070376 | 563 | |
65b97cf6 | 564 | bytes = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 565 | bytes = PREFETCH_STATUS_FIFO_CNT(bytes); |
4e070376 SG |
566 | bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ |
567 | if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ | |
5c468455 | 568 | if (this_irq == info->gpmc_irq_count) |
4e070376 SG |
569 | goto done; |
570 | ||
571 | if (info->buf_len && (info->buf_len < bytes)) | |
572 | bytes = info->buf_len; | |
573 | else if (!info->buf_len) | |
574 | bytes = 0; | |
575 | iowrite32_rep(info->nand.IO_ADDR_W, | |
576 | (u32 *)info->buf, bytes >> 2); | |
577 | info->buf = info->buf + bytes; | |
578 | info->buf_len -= bytes; | |
579 | ||
580 | } else { | |
581 | ioread32_rep(info->nand.IO_ADDR_R, | |
582 | (u32 *)info->buf, bytes >> 2); | |
583 | info->buf = info->buf + bytes; | |
584 | ||
5c468455 | 585 | if (this_irq == info->gpmc_irq_count) |
4e070376 SG |
586 | goto done; |
587 | } | |
4e070376 SG |
588 | |
589 | return IRQ_HANDLED; | |
590 | ||
591 | done: | |
592 | complete(&info->comp); | |
4e070376 | 593 | |
5c468455 AM |
594 | disable_irq_nosync(info->gpmc_irq_fifo); |
595 | disable_irq_nosync(info->gpmc_irq_count); | |
4e070376 SG |
596 | |
597 | return IRQ_HANDLED; | |
598 | } | |
599 | ||
600 | /* | |
601 | * omap_read_buf_irq_pref - read data from NAND controller into buffer | |
602 | * @mtd: MTD device structure | |
603 | * @buf: buffer to store date | |
604 | * @len: number of bytes to read | |
605 | */ | |
606 | static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) | |
607 | { | |
608 | struct omap_nand_info *info = container_of(mtd, | |
609 | struct omap_nand_info, mtd); | |
610 | int ret = 0; | |
611 | ||
612 | if (len <= mtd->oobsize) { | |
613 | omap_read_buf_pref(mtd, buf, len); | |
614 | return; | |
615 | } | |
616 | ||
617 | info->iomode = OMAP_NAND_IO_READ; | |
618 | info->buf = buf; | |
619 | init_completion(&info->comp); | |
620 | ||
621 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
622 | ret = omap_prefetch_enable(info->gpmc_cs, |
623 | PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info); | |
4e070376 SG |
624 | if (ret) |
625 | /* PFPW engine is busy, use cpu copy method */ | |
626 | goto out_copy; | |
627 | ||
628 | info->buf_len = len; | |
5c468455 AM |
629 | |
630 | enable_irq(info->gpmc_irq_count); | |
631 | enable_irq(info->gpmc_irq_fifo); | |
4e070376 SG |
632 | |
633 | /* waiting for read to complete */ | |
634 | wait_for_completion(&info->comp); | |
635 | ||
636 | /* disable and stop the PFPW engine */ | |
65b97cf6 | 637 | omap_prefetch_reset(info->gpmc_cs, info); |
4e070376 SG |
638 | return; |
639 | ||
640 | out_copy: | |
641 | if (info->nand.options & NAND_BUSWIDTH_16) | |
642 | omap_read_buf16(mtd, buf, len); | |
643 | else | |
644 | omap_read_buf8(mtd, buf, len); | |
645 | } | |
646 | ||
647 | /* | |
648 | * omap_write_buf_irq_pref - write buffer to NAND controller | |
649 | * @mtd: MTD device structure | |
650 | * @buf: data buffer | |
651 | * @len: number of bytes to write | |
652 | */ | |
653 | static void omap_write_buf_irq_pref(struct mtd_info *mtd, | |
654 | const u_char *buf, int len) | |
655 | { | |
656 | struct omap_nand_info *info = container_of(mtd, | |
657 | struct omap_nand_info, mtd); | |
658 | int ret = 0; | |
659 | unsigned long tim, limit; | |
65b97cf6 | 660 | u32 val; |
4e070376 SG |
661 | |
662 | if (len <= mtd->oobsize) { | |
663 | omap_write_buf_pref(mtd, buf, len); | |
664 | return; | |
665 | } | |
666 | ||
667 | info->iomode = OMAP_NAND_IO_WRITE; | |
668 | info->buf = (u_char *) buf; | |
669 | init_completion(&info->comp); | |
670 | ||
317379a9 | 671 | /* configure and start prefetch transfer : size=24 */ |
65b97cf6 AM |
672 | ret = omap_prefetch_enable(info->gpmc_cs, |
673 | (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info); | |
4e070376 SG |
674 | if (ret) |
675 | /* PFPW engine is busy, use cpu copy method */ | |
676 | goto out_copy; | |
677 | ||
678 | info->buf_len = len; | |
5c468455 AM |
679 | |
680 | enable_irq(info->gpmc_irq_count); | |
681 | enable_irq(info->gpmc_irq_fifo); | |
4e070376 SG |
682 | |
683 | /* waiting for write to complete */ | |
684 | wait_for_completion(&info->comp); | |
5c468455 | 685 | |
4e070376 SG |
686 | /* wait for data to flushed-out before reset the prefetch */ |
687 | tim = 0; | |
688 | limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 AM |
689 | do { |
690 | val = readl(info->reg.gpmc_prefetch_status); | |
47f88af4 | 691 | val = PREFETCH_STATUS_COUNT(val); |
4e070376 | 692 | cpu_relax(); |
65b97cf6 | 693 | } while (val && (tim++ < limit)); |
4e070376 SG |
694 | |
695 | /* disable and stop the PFPW engine */ | |
65b97cf6 | 696 | omap_prefetch_reset(info->gpmc_cs, info); |
4e070376 SG |
697 | return; |
698 | ||
699 | out_copy: | |
700 | if (info->nand.options & NAND_BUSWIDTH_16) | |
701 | omap_write_buf16(mtd, buf, len); | |
702 | else | |
703 | omap_write_buf8(mtd, buf, len); | |
704 | } | |
705 | ||
67ce04bf VS |
706 | /** |
707 | * gen_true_ecc - This function will generate true ECC value | |
708 | * @ecc_buf: buffer to store ecc code | |
709 | * | |
710 | * This generated true ECC value can be used when correcting | |
711 | * data read from NAND flash memory core | |
712 | */ | |
713 | static void gen_true_ecc(u8 *ecc_buf) | |
714 | { | |
715 | u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) | | |
716 | ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8); | |
717 | ||
718 | ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | | |
719 | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp)); | |
720 | ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | | |
721 | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp)); | |
722 | ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | | |
723 | P1e(tmp) | P2048o(tmp) | P2048e(tmp)); | |
724 | } | |
725 | ||
726 | /** | |
727 | * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data | |
728 | * @ecc_data1: ecc code from nand spare area | |
729 | * @ecc_data2: ecc code from hardware register obtained from hardware ecc | |
730 | * @page_data: page data | |
731 | * | |
732 | * This function compares two ECC's and indicates if there is an error. | |
733 | * If the error can be corrected it will be corrected to the buffer. | |
74f1b724 JO |
734 | * If there is no error, %0 is returned. If there is an error but it |
735 | * was corrected, %1 is returned. Otherwise, %-1 is returned. | |
67ce04bf VS |
736 | */ |
737 | static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */ | |
738 | u8 *ecc_data2, /* read from register */ | |
739 | u8 *page_data) | |
740 | { | |
741 | uint i; | |
742 | u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8]; | |
743 | u8 comp0_bit[8], comp1_bit[8], comp2_bit[8]; | |
744 | u8 ecc_bit[24]; | |
745 | u8 ecc_sum = 0; | |
746 | u8 find_bit = 0; | |
747 | uint find_byte = 0; | |
748 | int isEccFF; | |
749 | ||
750 | isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF); | |
751 | ||
752 | gen_true_ecc(ecc_data1); | |
753 | gen_true_ecc(ecc_data2); | |
754 | ||
755 | for (i = 0; i <= 2; i++) { | |
756 | *(ecc_data1 + i) = ~(*(ecc_data1 + i)); | |
757 | *(ecc_data2 + i) = ~(*(ecc_data2 + i)); | |
758 | } | |
759 | ||
760 | for (i = 0; i < 8; i++) { | |
761 | tmp0_bit[i] = *ecc_data1 % 2; | |
762 | *ecc_data1 = *ecc_data1 / 2; | |
763 | } | |
764 | ||
765 | for (i = 0; i < 8; i++) { | |
766 | tmp1_bit[i] = *(ecc_data1 + 1) % 2; | |
767 | *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2; | |
768 | } | |
769 | ||
770 | for (i = 0; i < 8; i++) { | |
771 | tmp2_bit[i] = *(ecc_data1 + 2) % 2; | |
772 | *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2; | |
773 | } | |
774 | ||
775 | for (i = 0; i < 8; i++) { | |
776 | comp0_bit[i] = *ecc_data2 % 2; | |
777 | *ecc_data2 = *ecc_data2 / 2; | |
778 | } | |
779 | ||
780 | for (i = 0; i < 8; i++) { | |
781 | comp1_bit[i] = *(ecc_data2 + 1) % 2; | |
782 | *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2; | |
783 | } | |
784 | ||
785 | for (i = 0; i < 8; i++) { | |
786 | comp2_bit[i] = *(ecc_data2 + 2) % 2; | |
787 | *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2; | |
788 | } | |
789 | ||
790 | for (i = 0; i < 6; i++) | |
791 | ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2]; | |
792 | ||
793 | for (i = 0; i < 8; i++) | |
794 | ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i]; | |
795 | ||
796 | for (i = 0; i < 8; i++) | |
797 | ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i]; | |
798 | ||
799 | ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0]; | |
800 | ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1]; | |
801 | ||
802 | for (i = 0; i < 24; i++) | |
803 | ecc_sum += ecc_bit[i]; | |
804 | ||
805 | switch (ecc_sum) { | |
806 | case 0: | |
807 | /* Not reached because this function is not called if | |
808 | * ECC values are equal | |
809 | */ | |
810 | return 0; | |
811 | ||
812 | case 1: | |
813 | /* Uncorrectable error */ | |
289c0522 | 814 | pr_debug("ECC UNCORRECTED_ERROR 1\n"); |
67ce04bf VS |
815 | return -1; |
816 | ||
817 | case 11: | |
818 | /* UN-Correctable error */ | |
289c0522 | 819 | pr_debug("ECC UNCORRECTED_ERROR B\n"); |
67ce04bf VS |
820 | return -1; |
821 | ||
822 | case 12: | |
823 | /* Correctable error */ | |
824 | find_byte = (ecc_bit[23] << 8) + | |
825 | (ecc_bit[21] << 7) + | |
826 | (ecc_bit[19] << 6) + | |
827 | (ecc_bit[17] << 5) + | |
828 | (ecc_bit[15] << 4) + | |
829 | (ecc_bit[13] << 3) + | |
830 | (ecc_bit[11] << 2) + | |
831 | (ecc_bit[9] << 1) + | |
832 | ecc_bit[7]; | |
833 | ||
834 | find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; | |
835 | ||
0a32a102 BN |
836 | pr_debug("Correcting single bit ECC error at offset: " |
837 | "%d, bit: %d\n", find_byte, find_bit); | |
67ce04bf VS |
838 | |
839 | page_data[find_byte] ^= (1 << find_bit); | |
840 | ||
74f1b724 | 841 | return 1; |
67ce04bf VS |
842 | default: |
843 | if (isEccFF) { | |
844 | if (ecc_data2[0] == 0 && | |
845 | ecc_data2[1] == 0 && | |
846 | ecc_data2[2] == 0) | |
847 | return 0; | |
848 | } | |
289c0522 | 849 | pr_debug("UNCORRECTED_ERROR default\n"); |
67ce04bf VS |
850 | return -1; |
851 | } | |
852 | } | |
853 | ||
854 | /** | |
855 | * omap_correct_data - Compares the ECC read with HW generated ECC | |
856 | * @mtd: MTD device structure | |
857 | * @dat: page data | |
858 | * @read_ecc: ecc read from nand flash | |
859 | * @calc_ecc: ecc read from HW ECC registers | |
860 | * | |
861 | * Compares the ecc read from nand spare area with ECC registers values | |
74f1b724 JO |
862 | * and if ECC's mismatched, it will call 'omap_compare_ecc' for error |
863 | * detection and correction. If there are no errors, %0 is returned. If | |
864 | * there were errors and all of the errors were corrected, the number of | |
865 | * corrected errors is returned. If uncorrectable errors exist, %-1 is | |
866 | * returned. | |
67ce04bf VS |
867 | */ |
868 | static int omap_correct_data(struct mtd_info *mtd, u_char *dat, | |
869 | u_char *read_ecc, u_char *calc_ecc) | |
870 | { | |
871 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
872 | mtd); | |
873 | int blockCnt = 0, i = 0, ret = 0; | |
74f1b724 | 874 | int stat = 0; |
67ce04bf VS |
875 | |
876 | /* Ex NAND_ECC_HW12_2048 */ | |
877 | if ((info->nand.ecc.mode == NAND_ECC_HW) && | |
878 | (info->nand.ecc.size == 2048)) | |
879 | blockCnt = 4; | |
880 | else | |
881 | blockCnt = 1; | |
882 | ||
883 | for (i = 0; i < blockCnt; i++) { | |
884 | if (memcmp(read_ecc, calc_ecc, 3) != 0) { | |
885 | ret = omap_compare_ecc(read_ecc, calc_ecc, dat); | |
886 | if (ret < 0) | |
887 | return ret; | |
74f1b724 JO |
888 | /* keep track of the number of corrected errors */ |
889 | stat += ret; | |
67ce04bf VS |
890 | } |
891 | read_ecc += 3; | |
892 | calc_ecc += 3; | |
893 | dat += 512; | |
894 | } | |
74f1b724 | 895 | return stat; |
67ce04bf VS |
896 | } |
897 | ||
898 | /** | |
899 | * omap_calcuate_ecc - Generate non-inverted ECC bytes. | |
900 | * @mtd: MTD device structure | |
901 | * @dat: The pointer to data on which ecc is computed | |
902 | * @ecc_code: The ecc_code buffer | |
903 | * | |
904 | * Using noninverted ECC can be considered ugly since writing a blank | |
905 | * page ie. padding will clear the ECC bytes. This is no problem as long | |
906 | * nobody is trying to write data on the seemingly unused page. Reading | |
907 | * an erased page will produce an ECC mismatch between generated and read | |
908 | * ECC bytes that has to be dealt with separately. | |
909 | */ | |
910 | static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat, | |
911 | u_char *ecc_code) | |
912 | { | |
913 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
914 | mtd); | |
65b97cf6 AM |
915 | u32 val; |
916 | ||
917 | val = readl(info->reg.gpmc_ecc_config); | |
918 | if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs) | |
919 | return -EINVAL; | |
920 | ||
921 | /* read ecc result */ | |
922 | val = readl(info->reg.gpmc_ecc1_result); | |
923 | *ecc_code++ = val; /* P128e, ..., P1e */ | |
924 | *ecc_code++ = val >> 16; /* P128o, ..., P1o */ | |
925 | /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ | |
926 | *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); | |
927 | ||
928 | return 0; | |
67ce04bf VS |
929 | } |
930 | ||
931 | /** | |
932 | * omap_enable_hwecc - This function enables the hardware ecc functionality | |
933 | * @mtd: MTD device structure | |
934 | * @mode: Read/Write mode | |
935 | */ | |
936 | static void omap_enable_hwecc(struct mtd_info *mtd, int mode) | |
937 | { | |
938 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
939 | mtd); | |
940 | struct nand_chip *chip = mtd->priv; | |
941 | unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; | |
65b97cf6 AM |
942 | u32 val; |
943 | ||
944 | /* clear ecc and enable bits */ | |
945 | val = ECCCLEAR | ECC1; | |
946 | writel(val, info->reg.gpmc_ecc_control); | |
67ce04bf | 947 | |
65b97cf6 AM |
948 | /* program ecc and result sizes */ |
949 | val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) | | |
950 | ECC1RESULTSIZE); | |
951 | writel(val, info->reg.gpmc_ecc_size_config); | |
952 | ||
953 | switch (mode) { | |
954 | case NAND_ECC_READ: | |
955 | case NAND_ECC_WRITE: | |
956 | writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); | |
957 | break; | |
958 | case NAND_ECC_READSYN: | |
959 | writel(ECCCLEAR, info->reg.gpmc_ecc_control); | |
960 | break; | |
961 | default: | |
962 | dev_info(&info->pdev->dev, | |
963 | "error: unrecognized Mode[%d]!\n", mode); | |
964 | break; | |
965 | } | |
67ce04bf | 966 | |
65b97cf6 AM |
967 | /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ |
968 | val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); | |
969 | writel(val, info->reg.gpmc_ecc_config); | |
67ce04bf | 970 | } |
2c01946c | 971 | |
67ce04bf VS |
972 | /** |
973 | * omap_wait - wait until the command is done | |
974 | * @mtd: MTD device structure | |
975 | * @chip: NAND Chip structure | |
976 | * | |
977 | * Wait function is called during Program and erase operations and | |
978 | * the way it is called from MTD layer, we should wait till the NAND | |
979 | * chip is ready after the programming/erase operation has completed. | |
980 | * | |
981 | * Erase can take up to 400ms and program up to 20ms according to | |
982 | * general NAND and SmartMedia specs | |
983 | */ | |
984 | static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
985 | { | |
986 | struct nand_chip *this = mtd->priv; | |
987 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
988 | mtd); | |
989 | unsigned long timeo = jiffies; | |
a9c465f0 | 990 | int status, state = this->state; |
67ce04bf VS |
991 | |
992 | if (state == FL_ERASING) | |
993 | timeo += (HZ * 400) / 1000; | |
994 | else | |
995 | timeo += (HZ * 20) / 1000; | |
996 | ||
65b97cf6 | 997 | writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command); |
67ce04bf | 998 | while (time_before(jiffies, timeo)) { |
65b97cf6 | 999 | status = readb(info->reg.gpmc_nand_data); |
c276aca4 | 1000 | if (status & NAND_STATUS_READY) |
67ce04bf | 1001 | break; |
c276aca4 | 1002 | cond_resched(); |
67ce04bf | 1003 | } |
a9c465f0 | 1004 | |
4ea1e4ba | 1005 | status = readb(info->reg.gpmc_nand_data); |
67ce04bf VS |
1006 | return status; |
1007 | } | |
1008 | ||
1009 | /** | |
1010 | * omap_dev_ready - calls the platform specific dev_ready function | |
1011 | * @mtd: MTD device structure | |
1012 | */ | |
1013 | static int omap_dev_ready(struct mtd_info *mtd) | |
1014 | { | |
2c01946c | 1015 | unsigned int val = 0; |
67ce04bf VS |
1016 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
1017 | mtd); | |
67ce04bf | 1018 | |
65b97cf6 AM |
1019 | val = readl(info->reg.gpmc_status); |
1020 | ||
67ce04bf | 1021 | if ((val & 0x100) == 0x100) { |
65b97cf6 | 1022 | return 1; |
67ce04bf | 1023 | } else { |
65b97cf6 | 1024 | return 0; |
67ce04bf | 1025 | } |
67ce04bf VS |
1026 | } |
1027 | ||
0e618ef0 ID |
1028 | #ifdef CONFIG_MTD_NAND_OMAP_BCH |
1029 | ||
1030 | /** | |
1031 | * omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction | |
1032 | * @mtd: MTD device structure | |
1033 | * @mode: Read/Write mode | |
1034 | */ | |
1035 | static void omap3_enable_hwecc_bch(struct mtd_info *mtd, int mode) | |
1036 | { | |
1037 | int nerrors; | |
2ef9f3dd | 1038 | unsigned int dev_width, nsectors; |
0e618ef0 ID |
1039 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
1040 | mtd); | |
1041 | struct nand_chip *chip = mtd->priv; | |
2ef9f3dd | 1042 | u32 val; |
0e618ef0 ID |
1043 | |
1044 | nerrors = (info->nand.ecc.bytes == 13) ? 8 : 4; | |
1045 | dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; | |
2ef9f3dd | 1046 | nsectors = 1; |
0e618ef0 ID |
1047 | /* |
1048 | * Program GPMC to perform correction on one 512-byte sector at a time. | |
1049 | * Using 4 sectors at a time (i.e. ecc.size = 2048) is also possible and | |
1050 | * gives a slight (5%) performance gain (but requires additional code). | |
1051 | */ | |
2ef9f3dd AM |
1052 | |
1053 | writel(ECC1, info->reg.gpmc_ecc_control); | |
1054 | ||
1055 | /* | |
1056 | * When using BCH, sector size is hardcoded to 512 bytes. | |
1057 | * Here we are using wrapping mode 6 both for reading and writing, with: | |
1058 | * size0 = 0 (no additional protected byte in spare area) | |
1059 | * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area) | |
1060 | */ | |
1061 | val = (32 << ECCSIZE1_SHIFT) | (0 << ECCSIZE0_SHIFT); | |
1062 | writel(val, info->reg.gpmc_ecc_size_config); | |
1063 | ||
1064 | /* BCH configuration */ | |
1065 | val = ((1 << 16) | /* enable BCH */ | |
1066 | (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */ | |
1067 | (0x06 << 8) | /* wrap mode = 6 */ | |
1068 | (dev_width << 7) | /* bus width */ | |
1069 | (((nsectors-1) & 0x7) << 4) | /* number of sectors */ | |
1070 | (info->gpmc_cs << 1) | /* ECC CS */ | |
1071 | (0x1)); /* enable ECC */ | |
1072 | ||
1073 | writel(val, info->reg.gpmc_ecc_config); | |
1074 | ||
1075 | /* clear ecc and enable bits */ | |
1076 | writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); | |
0e618ef0 ID |
1077 | } |
1078 | ||
1079 | /** | |
1080 | * omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC bytes | |
1081 | * @mtd: MTD device structure | |
1082 | * @dat: The pointer to data on which ecc is computed | |
1083 | * @ecc_code: The ecc_code buffer | |
1084 | */ | |
1085 | static int omap3_calculate_ecc_bch4(struct mtd_info *mtd, const u_char *dat, | |
1086 | u_char *ecc_code) | |
1087 | { | |
1088 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1089 | mtd); | |
2ef9f3dd AM |
1090 | unsigned long nsectors, val1, val2; |
1091 | int i; | |
1092 | ||
1093 | nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1; | |
1094 | ||
1095 | for (i = 0; i < nsectors; i++) { | |
1096 | ||
1097 | /* Read hw-computed remainder */ | |
1098 | val1 = readl(info->reg.gpmc_bch_result0[i]); | |
1099 | val2 = readl(info->reg.gpmc_bch_result1[i]); | |
1100 | ||
1101 | /* | |
1102 | * Add constant polynomial to remainder, in order to get an ecc | |
1103 | * sequence of 0xFFs for a buffer filled with 0xFFs; and | |
1104 | * left-justify the resulting polynomial. | |
1105 | */ | |
1106 | *ecc_code++ = 0x28 ^ ((val2 >> 12) & 0xFF); | |
1107 | *ecc_code++ = 0x13 ^ ((val2 >> 4) & 0xFF); | |
1108 | *ecc_code++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF)); | |
1109 | *ecc_code++ = 0x39 ^ ((val1 >> 20) & 0xFF); | |
1110 | *ecc_code++ = 0x96 ^ ((val1 >> 12) & 0xFF); | |
1111 | *ecc_code++ = 0xac ^ ((val1 >> 4) & 0xFF); | |
1112 | *ecc_code++ = 0x7f ^ ((val1 & 0xF) << 4); | |
1113 | } | |
1114 | ||
1115 | return 0; | |
0e618ef0 ID |
1116 | } |
1117 | ||
1118 | /** | |
1119 | * omap3_calculate_ecc_bch8 - Generate 13 bytes of ECC bytes | |
1120 | * @mtd: MTD device structure | |
1121 | * @dat: The pointer to data on which ecc is computed | |
1122 | * @ecc_code: The ecc_code buffer | |
1123 | */ | |
1124 | static int omap3_calculate_ecc_bch8(struct mtd_info *mtd, const u_char *dat, | |
1125 | u_char *ecc_code) | |
1126 | { | |
1127 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1128 | mtd); | |
2ef9f3dd AM |
1129 | unsigned long nsectors, val1, val2, val3, val4; |
1130 | int i; | |
1131 | ||
1132 | nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1; | |
1133 | ||
1134 | for (i = 0; i < nsectors; i++) { | |
1135 | ||
1136 | /* Read hw-computed remainder */ | |
1137 | val1 = readl(info->reg.gpmc_bch_result0[i]); | |
1138 | val2 = readl(info->reg.gpmc_bch_result1[i]); | |
1139 | val3 = readl(info->reg.gpmc_bch_result2[i]); | |
1140 | val4 = readl(info->reg.gpmc_bch_result3[i]); | |
1141 | ||
1142 | /* | |
1143 | * Add constant polynomial to remainder, in order to get an ecc | |
1144 | * sequence of 0xFFs for a buffer filled with 0xFFs. | |
1145 | */ | |
1146 | *ecc_code++ = 0xef ^ (val4 & 0xFF); | |
1147 | *ecc_code++ = 0x51 ^ ((val3 >> 24) & 0xFF); | |
1148 | *ecc_code++ = 0x2e ^ ((val3 >> 16) & 0xFF); | |
1149 | *ecc_code++ = 0x09 ^ ((val3 >> 8) & 0xFF); | |
1150 | *ecc_code++ = 0xed ^ (val3 & 0xFF); | |
1151 | *ecc_code++ = 0x93 ^ ((val2 >> 24) & 0xFF); | |
1152 | *ecc_code++ = 0x9a ^ ((val2 >> 16) & 0xFF); | |
1153 | *ecc_code++ = 0xc2 ^ ((val2 >> 8) & 0xFF); | |
1154 | *ecc_code++ = 0x97 ^ (val2 & 0xFF); | |
1155 | *ecc_code++ = 0x79 ^ ((val1 >> 24) & 0xFF); | |
1156 | *ecc_code++ = 0xe5 ^ ((val1 >> 16) & 0xFF); | |
1157 | *ecc_code++ = 0x24 ^ ((val1 >> 8) & 0xFF); | |
1158 | *ecc_code++ = 0xb5 ^ (val1 & 0xFF); | |
1159 | } | |
1160 | ||
1161 | return 0; | |
0e618ef0 ID |
1162 | } |
1163 | ||
1164 | /** | |
1165 | * omap3_correct_data_bch - Decode received data and correct errors | |
1166 | * @mtd: MTD device structure | |
1167 | * @data: page data | |
1168 | * @read_ecc: ecc read from nand flash | |
1169 | * @calc_ecc: ecc read from HW ECC registers | |
1170 | */ | |
1171 | static int omap3_correct_data_bch(struct mtd_info *mtd, u_char *data, | |
1172 | u_char *read_ecc, u_char *calc_ecc) | |
1173 | { | |
1174 | int i, count; | |
1175 | /* cannot correct more than 8 errors */ | |
1176 | unsigned int errloc[8]; | |
1177 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1178 | mtd); | |
1179 | ||
1180 | count = decode_bch(info->bch, NULL, 512, read_ecc, calc_ecc, NULL, | |
1181 | errloc); | |
1182 | if (count > 0) { | |
1183 | /* correct errors */ | |
1184 | for (i = 0; i < count; i++) { | |
1185 | /* correct data only, not ecc bytes */ | |
1186 | if (errloc[i] < 8*512) | |
1187 | data[errloc[i]/8] ^= 1 << (errloc[i] & 7); | |
1188 | pr_debug("corrected bitflip %u\n", errloc[i]); | |
1189 | } | |
1190 | } else if (count < 0) { | |
1191 | pr_err("ecc unrecoverable error\n"); | |
1192 | } | |
1193 | return count; | |
1194 | } | |
1195 | ||
1196 | /** | |
1197 | * omap3_free_bch - Release BCH ecc resources | |
1198 | * @mtd: MTD device structure | |
1199 | */ | |
1200 | static void omap3_free_bch(struct mtd_info *mtd) | |
1201 | { | |
1202 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1203 | mtd); | |
1204 | if (info->bch) { | |
1205 | free_bch(info->bch); | |
1206 | info->bch = NULL; | |
1207 | } | |
1208 | } | |
1209 | ||
1210 | /** | |
1211 | * omap3_init_bch - Initialize BCH ECC | |
1212 | * @mtd: MTD device structure | |
1213 | * @ecc_opt: OMAP ECC mode (OMAP_ECC_BCH4_CODE_HW or OMAP_ECC_BCH8_CODE_HW) | |
1214 | */ | |
1215 | static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt) | |
1216 | { | |
2ef9f3dd | 1217 | int max_errors; |
0e618ef0 ID |
1218 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
1219 | mtd); | |
1220 | #ifdef CONFIG_MTD_NAND_OMAP_BCH8 | |
1221 | const int hw_errors = 8; | |
1222 | #else | |
1223 | const int hw_errors = 4; | |
1224 | #endif | |
1225 | info->bch = NULL; | |
1226 | ||
1227 | max_errors = (ecc_opt == OMAP_ECC_BCH8_CODE_HW) ? 8 : 4; | |
1228 | if (max_errors != hw_errors) { | |
1229 | pr_err("cannot configure %d-bit BCH ecc, only %d-bit supported", | |
1230 | max_errors, hw_errors); | |
1231 | goto fail; | |
1232 | } | |
1233 | ||
0e618ef0 ID |
1234 | /* software bch library is only used to detect and locate errors */ |
1235 | info->bch = init_bch(13, max_errors, 0x201b /* hw polynomial */); | |
1236 | if (!info->bch) | |
1237 | goto fail; | |
1238 | ||
1239 | info->nand.ecc.size = 512; | |
1240 | info->nand.ecc.hwctl = omap3_enable_hwecc_bch; | |
1241 | info->nand.ecc.correct = omap3_correct_data_bch; | |
1242 | info->nand.ecc.mode = NAND_ECC_HW; | |
1243 | ||
1244 | /* | |
1245 | * The number of corrected errors in an ecc block that will trigger | |
1246 | * block scrubbing defaults to the ecc strength (4 or 8). | |
1247 | * Set mtd->bitflip_threshold here to define a custom threshold. | |
1248 | */ | |
1249 | ||
1250 | if (max_errors == 8) { | |
1251 | info->nand.ecc.strength = 8; | |
1252 | info->nand.ecc.bytes = 13; | |
1253 | info->nand.ecc.calculate = omap3_calculate_ecc_bch8; | |
1254 | } else { | |
1255 | info->nand.ecc.strength = 4; | |
1256 | info->nand.ecc.bytes = 7; | |
1257 | info->nand.ecc.calculate = omap3_calculate_ecc_bch4; | |
1258 | } | |
1259 | ||
1260 | pr_info("enabling NAND BCH ecc with %d-bit correction\n", max_errors); | |
1261 | return 0; | |
1262 | fail: | |
1263 | omap3_free_bch(mtd); | |
1264 | return -1; | |
1265 | } | |
1266 | ||
1267 | /** | |
1268 | * omap3_init_bch_tail - Build an oob layout for BCH ECC correction. | |
1269 | * @mtd: MTD device structure | |
1270 | */ | |
1271 | static int omap3_init_bch_tail(struct mtd_info *mtd) | |
1272 | { | |
1273 | int i, steps; | |
1274 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1275 | mtd); | |
1276 | struct nand_ecclayout *layout = &info->ecclayout; | |
1277 | ||
1278 | /* build oob layout */ | |
1279 | steps = mtd->writesize/info->nand.ecc.size; | |
1280 | layout->eccbytes = steps*info->nand.ecc.bytes; | |
1281 | ||
1282 | /* do not bother creating special oob layouts for small page devices */ | |
1283 | if (mtd->oobsize < 64) { | |
1284 | pr_err("BCH ecc is not supported on small page devices\n"); | |
1285 | goto fail; | |
1286 | } | |
1287 | ||
1288 | /* reserve 2 bytes for bad block marker */ | |
1289 | if (layout->eccbytes+2 > mtd->oobsize) { | |
1290 | pr_err("no oob layout available for oobsize %d eccbytes %u\n", | |
1291 | mtd->oobsize, layout->eccbytes); | |
1292 | goto fail; | |
1293 | } | |
1294 | ||
1295 | /* put ecc bytes at oob tail */ | |
1296 | for (i = 0; i < layout->eccbytes; i++) | |
1297 | layout->eccpos[i] = mtd->oobsize-layout->eccbytes+i; | |
1298 | ||
1299 | layout->oobfree[0].offset = 2; | |
1300 | layout->oobfree[0].length = mtd->oobsize-2-layout->eccbytes; | |
1301 | info->nand.ecc.layout = layout; | |
1302 | ||
1303 | if (!(info->nand.options & NAND_BUSWIDTH_16)) | |
1304 | info->nand.badblock_pattern = &bb_descrip_flashbased; | |
1305 | return 0; | |
1306 | fail: | |
1307 | omap3_free_bch(mtd); | |
1308 | return -1; | |
1309 | } | |
1310 | ||
1311 | #else | |
1312 | static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt) | |
1313 | { | |
1314 | pr_err("CONFIG_MTD_NAND_OMAP_BCH is not enabled\n"); | |
1315 | return -1; | |
1316 | } | |
1317 | static int omap3_init_bch_tail(struct mtd_info *mtd) | |
1318 | { | |
1319 | return -1; | |
1320 | } | |
1321 | static void omap3_free_bch(struct mtd_info *mtd) | |
1322 | { | |
1323 | } | |
1324 | #endif /* CONFIG_MTD_NAND_OMAP_BCH */ | |
1325 | ||
67ce04bf VS |
1326 | static int __devinit omap_nand_probe(struct platform_device *pdev) |
1327 | { | |
1328 | struct omap_nand_info *info; | |
1329 | struct omap_nand_platform_data *pdata; | |
1330 | int err; | |
f040d332 | 1331 | int i, offset; |
763e7359 RK |
1332 | dma_cap_mask_t mask; |
1333 | unsigned sig; | |
9c4c2f8b | 1334 | struct resource *res; |
67ce04bf VS |
1335 | |
1336 | pdata = pdev->dev.platform_data; | |
1337 | if (pdata == NULL) { | |
1338 | dev_err(&pdev->dev, "platform data missing\n"); | |
1339 | return -ENODEV; | |
1340 | } | |
1341 | ||
1342 | info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL); | |
1343 | if (!info) | |
1344 | return -ENOMEM; | |
1345 | ||
1346 | platform_set_drvdata(pdev, info); | |
1347 | ||
1348 | spin_lock_init(&info->controller.lock); | |
1349 | init_waitqueue_head(&info->controller.wq); | |
1350 | ||
1351 | info->pdev = pdev; | |
1352 | ||
1353 | info->gpmc_cs = pdata->cs; | |
65b97cf6 | 1354 | info->reg = pdata->reg; |
67ce04bf VS |
1355 | |
1356 | info->mtd.priv = &info->nand; | |
1357 | info->mtd.name = dev_name(&pdev->dev); | |
1358 | info->mtd.owner = THIS_MODULE; | |
1359 | ||
d5ce2b65 | 1360 | info->nand.options = pdata->devsize; |
2f70a1e9 | 1361 | info->nand.options |= NAND_SKIP_BBTSCAN; |
67ce04bf | 1362 | |
9c4c2f8b AM |
1363 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1364 | if (res == NULL) { | |
1365 | err = -EINVAL; | |
1366 | dev_err(&pdev->dev, "error getting memory resource\n"); | |
1367 | goto out_free_info; | |
1368 | } | |
67ce04bf | 1369 | |
9c4c2f8b AM |
1370 | info->phys_base = res->start; |
1371 | info->mem_size = resource_size(res); | |
1372 | ||
1373 | if (!request_mem_region(info->phys_base, info->mem_size, | |
67ce04bf VS |
1374 | pdev->dev.driver->name)) { |
1375 | err = -EBUSY; | |
2f70a1e9 | 1376 | goto out_free_info; |
67ce04bf VS |
1377 | } |
1378 | ||
9c4c2f8b | 1379 | info->nand.IO_ADDR_R = ioremap(info->phys_base, info->mem_size); |
67ce04bf VS |
1380 | if (!info->nand.IO_ADDR_R) { |
1381 | err = -ENOMEM; | |
1382 | goto out_release_mem_region; | |
1383 | } | |
59e9c5ae | 1384 | |
67ce04bf VS |
1385 | info->nand.controller = &info->controller; |
1386 | ||
1387 | info->nand.IO_ADDR_W = info->nand.IO_ADDR_R; | |
1388 | info->nand.cmd_ctrl = omap_hwcontrol; | |
1389 | ||
67ce04bf VS |
1390 | /* |
1391 | * If RDY/BSY line is connected to OMAP then use the omap ready | |
4cacbe22 PM |
1392 | * function and the generic nand_wait function which reads the status |
1393 | * register after monitoring the RDY/BSY line. Otherwise use a standard | |
67ce04bf VS |
1394 | * chip delay which is slightly more than tR (AC Timing) of the NAND |
1395 | * device and read status register until you get a failure or success | |
1396 | */ | |
1397 | if (pdata->dev_ready) { | |
1398 | info->nand.dev_ready = omap_dev_ready; | |
1399 | info->nand.chip_delay = 0; | |
1400 | } else { | |
1401 | info->nand.waitfunc = omap_wait; | |
1402 | info->nand.chip_delay = 50; | |
1403 | } | |
1404 | ||
1b0b323c SG |
1405 | switch (pdata->xfer_type) { |
1406 | case NAND_OMAP_PREFETCH_POLLED: | |
59e9c5ae | 1407 | info->nand.read_buf = omap_read_buf_pref; |
1408 | info->nand.write_buf = omap_write_buf_pref; | |
1b0b323c SG |
1409 | break; |
1410 | ||
1411 | case NAND_OMAP_POLLED: | |
59e9c5ae | 1412 | if (info->nand.options & NAND_BUSWIDTH_16) { |
1413 | info->nand.read_buf = omap_read_buf16; | |
1414 | info->nand.write_buf = omap_write_buf16; | |
1415 | } else { | |
1416 | info->nand.read_buf = omap_read_buf8; | |
1417 | info->nand.write_buf = omap_write_buf8; | |
1418 | } | |
1b0b323c SG |
1419 | break; |
1420 | ||
1421 | case NAND_OMAP_PREFETCH_DMA: | |
763e7359 RK |
1422 | dma_cap_zero(mask); |
1423 | dma_cap_set(DMA_SLAVE, mask); | |
1424 | sig = OMAP24XX_DMA_GPMC; | |
1425 | info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig); | |
1426 | if (!info->dma) { | |
2df41d05 RK |
1427 | dev_err(&pdev->dev, "DMA engine request failed\n"); |
1428 | err = -ENXIO; | |
1429 | goto out_release_mem_region; | |
763e7359 RK |
1430 | } else { |
1431 | struct dma_slave_config cfg; | |
763e7359 RK |
1432 | |
1433 | memset(&cfg, 0, sizeof(cfg)); | |
1434 | cfg.src_addr = info->phys_base; | |
1435 | cfg.dst_addr = info->phys_base; | |
1436 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1437 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1438 | cfg.src_maxburst = 16; | |
1439 | cfg.dst_maxburst = 16; | |
d680e2c1 AB |
1440 | err = dmaengine_slave_config(info->dma, &cfg); |
1441 | if (err) { | |
763e7359 | 1442 | dev_err(&pdev->dev, "DMA engine slave config failed: %d\n", |
d680e2c1 | 1443 | err); |
763e7359 RK |
1444 | goto out_release_mem_region; |
1445 | } | |
1446 | info->nand.read_buf = omap_read_buf_dma_pref; | |
1447 | info->nand.write_buf = omap_write_buf_dma_pref; | |
1b0b323c SG |
1448 | } |
1449 | break; | |
1450 | ||
4e070376 | 1451 | case NAND_OMAP_PREFETCH_IRQ: |
5c468455 AM |
1452 | info->gpmc_irq_fifo = platform_get_irq(pdev, 0); |
1453 | if (info->gpmc_irq_fifo <= 0) { | |
1454 | dev_err(&pdev->dev, "error getting fifo irq\n"); | |
1455 | err = -ENODEV; | |
1456 | goto out_release_mem_region; | |
1457 | } | |
1458 | err = request_irq(info->gpmc_irq_fifo, omap_nand_irq, | |
1459 | IRQF_SHARED, "gpmc-nand-fifo", info); | |
4e070376 SG |
1460 | if (err) { |
1461 | dev_err(&pdev->dev, "requesting irq(%d) error:%d", | |
5c468455 AM |
1462 | info->gpmc_irq_fifo, err); |
1463 | info->gpmc_irq_fifo = 0; | |
1464 | goto out_release_mem_region; | |
1465 | } | |
1466 | ||
1467 | info->gpmc_irq_count = platform_get_irq(pdev, 1); | |
1468 | if (info->gpmc_irq_count <= 0) { | |
1469 | dev_err(&pdev->dev, "error getting count irq\n"); | |
1470 | err = -ENODEV; | |
1471 | goto out_release_mem_region; | |
1472 | } | |
1473 | err = request_irq(info->gpmc_irq_count, omap_nand_irq, | |
1474 | IRQF_SHARED, "gpmc-nand-count", info); | |
1475 | if (err) { | |
1476 | dev_err(&pdev->dev, "requesting irq(%d) error:%d", | |
1477 | info->gpmc_irq_count, err); | |
1478 | info->gpmc_irq_count = 0; | |
4e070376 | 1479 | goto out_release_mem_region; |
4e070376 | 1480 | } |
5c468455 AM |
1481 | |
1482 | info->nand.read_buf = omap_read_buf_irq_pref; | |
1483 | info->nand.write_buf = omap_write_buf_irq_pref; | |
1484 | ||
4e070376 SG |
1485 | break; |
1486 | ||
1b0b323c SG |
1487 | default: |
1488 | dev_err(&pdev->dev, | |
1489 | "xfer_type(%d) not supported!\n", pdata->xfer_type); | |
1490 | err = -EINVAL; | |
1491 | goto out_release_mem_region; | |
59e9c5ae | 1492 | } |
59e9c5ae | 1493 | |
4cacbe22 | 1494 | /* select the ecc type */ |
f3d73f36 SG |
1495 | if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT) |
1496 | info->nand.ecc.mode = NAND_ECC_SOFT; | |
f040d332 SG |
1497 | else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) || |
1498 | (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) { | |
f3d73f36 SG |
1499 | info->nand.ecc.bytes = 3; |
1500 | info->nand.ecc.size = 512; | |
6a918bad | 1501 | info->nand.ecc.strength = 1; |
f3d73f36 SG |
1502 | info->nand.ecc.calculate = omap_calculate_ecc; |
1503 | info->nand.ecc.hwctl = omap_enable_hwecc; | |
1504 | info->nand.ecc.correct = omap_correct_data; | |
1505 | info->nand.ecc.mode = NAND_ECC_HW; | |
0e618ef0 ID |
1506 | } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) || |
1507 | (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) { | |
1508 | err = omap3_init_bch(&info->mtd, pdata->ecc_opt); | |
1509 | if (err) { | |
1510 | err = -EINVAL; | |
1511 | goto out_release_mem_region; | |
1512 | } | |
f3d73f36 | 1513 | } |
67ce04bf VS |
1514 | |
1515 | /* DIP switches on some boards change between 8 and 16 bit | |
1516 | * bus widths for flash. Try the other width if the first try fails. | |
1517 | */ | |
a80f1c1f | 1518 | if (nand_scan_ident(&info->mtd, 1, NULL)) { |
67ce04bf | 1519 | info->nand.options ^= NAND_BUSWIDTH_16; |
a80f1c1f | 1520 | if (nand_scan_ident(&info->mtd, 1, NULL)) { |
67ce04bf VS |
1521 | err = -ENXIO; |
1522 | goto out_release_mem_region; | |
1523 | } | |
1524 | } | |
1525 | ||
f040d332 SG |
1526 | /* rom code layout */ |
1527 | if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) { | |
1528 | ||
1529 | if (info->nand.options & NAND_BUSWIDTH_16) | |
1530 | offset = 2; | |
1531 | else { | |
1532 | offset = 1; | |
1533 | info->nand.badblock_pattern = &bb_descrip_flashbased; | |
1534 | } | |
1535 | omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16); | |
1536 | for (i = 0; i < omap_oobinfo.eccbytes; i++) | |
1537 | omap_oobinfo.eccpos[i] = i+offset; | |
1538 | ||
1539 | omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes; | |
1540 | omap_oobinfo.oobfree->length = info->mtd.oobsize - | |
1541 | (offset + omap_oobinfo.eccbytes); | |
1542 | ||
1543 | info->nand.ecc.layout = &omap_oobinfo; | |
0e618ef0 ID |
1544 | } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) || |
1545 | (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) { | |
1546 | /* build OOB layout for BCH ECC correction */ | |
1547 | err = omap3_init_bch_tail(&info->mtd); | |
1548 | if (err) { | |
1549 | err = -EINVAL; | |
1550 | goto out_release_mem_region; | |
1551 | } | |
f040d332 | 1552 | } |
1b0b323c | 1553 | |
a80f1c1f JW |
1554 | /* second phase scan */ |
1555 | if (nand_scan_tail(&info->mtd)) { | |
1556 | err = -ENXIO; | |
1557 | goto out_release_mem_region; | |
1558 | } | |
1559 | ||
42d7fbe2 AB |
1560 | mtd_device_parse_register(&info->mtd, NULL, NULL, pdata->parts, |
1561 | pdata->nr_parts); | |
67ce04bf VS |
1562 | |
1563 | platform_set_drvdata(pdev, &info->mtd); | |
1564 | ||
1565 | return 0; | |
1566 | ||
1567 | out_release_mem_region: | |
763e7359 RK |
1568 | if (info->dma) |
1569 | dma_release_channel(info->dma); | |
5c468455 AM |
1570 | if (info->gpmc_irq_count > 0) |
1571 | free_irq(info->gpmc_irq_count, info); | |
1572 | if (info->gpmc_irq_fifo > 0) | |
1573 | free_irq(info->gpmc_irq_fifo, info); | |
9c4c2f8b | 1574 | release_mem_region(info->phys_base, info->mem_size); |
67ce04bf VS |
1575 | out_free_info: |
1576 | kfree(info); | |
1577 | ||
1578 | return err; | |
1579 | } | |
1580 | ||
1581 | static int omap_nand_remove(struct platform_device *pdev) | |
1582 | { | |
1583 | struct mtd_info *mtd = platform_get_drvdata(pdev); | |
f35b6eda VS |
1584 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
1585 | mtd); | |
0e618ef0 | 1586 | omap3_free_bch(&info->mtd); |
67ce04bf VS |
1587 | |
1588 | platform_set_drvdata(pdev, NULL); | |
763e7359 RK |
1589 | if (info->dma) |
1590 | dma_release_channel(info->dma); | |
1591 | ||
5c468455 AM |
1592 | if (info->gpmc_irq_count > 0) |
1593 | free_irq(info->gpmc_irq_count, info); | |
1594 | if (info->gpmc_irq_fifo > 0) | |
1595 | free_irq(info->gpmc_irq_fifo, info); | |
4e070376 | 1596 | |
67ce04bf VS |
1597 | /* Release NAND device, its internal structures and partitions */ |
1598 | nand_release(&info->mtd); | |
2c01946c | 1599 | iounmap(info->nand.IO_ADDR_R); |
48b51d4d | 1600 | release_mem_region(info->phys_base, info->mem_size); |
7d9b1102 | 1601 | kfree(info); |
67ce04bf VS |
1602 | return 0; |
1603 | } | |
1604 | ||
1605 | static struct platform_driver omap_nand_driver = { | |
1606 | .probe = omap_nand_probe, | |
1607 | .remove = omap_nand_remove, | |
1608 | .driver = { | |
1609 | .name = DRIVER_NAME, | |
1610 | .owner = THIS_MODULE, | |
1611 | }, | |
1612 | }; | |
1613 | ||
f99640de | 1614 | module_platform_driver(omap_nand_driver); |
67ce04bf | 1615 | |
c804c733 | 1616 | MODULE_ALIAS("platform:" DRIVER_NAME); |
67ce04bf VS |
1617 | MODULE_LICENSE("GPL"); |
1618 | MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards"); |