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67ce04bf VS |
1 | /* |
2 | * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com> | |
3 | * Copyright © 2004 Micron Technology Inc. | |
4 | * Copyright © 2004 David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/platform_device.h> | |
763e7359 | 12 | #include <linux/dmaengine.h> |
67ce04bf VS |
13 | #include <linux/dma-mapping.h> |
14 | #include <linux/delay.h> | |
a0e5cc58 | 15 | #include <linux/module.h> |
4e070376 | 16 | #include <linux/interrupt.h> |
c276aca4 | 17 | #include <linux/jiffies.h> |
18 | #include <linux/sched.h> | |
67ce04bf VS |
19 | #include <linux/mtd/mtd.h> |
20 | #include <linux/mtd/nand.h> | |
21 | #include <linux/mtd/partitions.h> | |
763e7359 | 22 | #include <linux/omap-dma.h> |
67ce04bf | 23 | #include <linux/io.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
67ce04bf | 25 | |
0e618ef0 ID |
26 | #ifdef CONFIG_MTD_NAND_OMAP_BCH |
27 | #include <linux/bch.h> | |
28 | #endif | |
29 | ||
ce491cf8 TL |
30 | #include <plat/dma.h> |
31 | #include <plat/gpmc.h> | |
2203747c | 32 | #include <linux/platform_data/mtd-nand-omap2.h> |
67ce04bf | 33 | |
67ce04bf | 34 | #define DRIVER_NAME "omap2-nand" |
4e070376 | 35 | #define OMAP_NAND_TIMEOUT_MS 5000 |
67ce04bf | 36 | |
67ce04bf VS |
37 | #define NAND_Ecc_P1e (1 << 0) |
38 | #define NAND_Ecc_P2e (1 << 1) | |
39 | #define NAND_Ecc_P4e (1 << 2) | |
40 | #define NAND_Ecc_P8e (1 << 3) | |
41 | #define NAND_Ecc_P16e (1 << 4) | |
42 | #define NAND_Ecc_P32e (1 << 5) | |
43 | #define NAND_Ecc_P64e (1 << 6) | |
44 | #define NAND_Ecc_P128e (1 << 7) | |
45 | #define NAND_Ecc_P256e (1 << 8) | |
46 | #define NAND_Ecc_P512e (1 << 9) | |
47 | #define NAND_Ecc_P1024e (1 << 10) | |
48 | #define NAND_Ecc_P2048e (1 << 11) | |
49 | ||
50 | #define NAND_Ecc_P1o (1 << 16) | |
51 | #define NAND_Ecc_P2o (1 << 17) | |
52 | #define NAND_Ecc_P4o (1 << 18) | |
53 | #define NAND_Ecc_P8o (1 << 19) | |
54 | #define NAND_Ecc_P16o (1 << 20) | |
55 | #define NAND_Ecc_P32o (1 << 21) | |
56 | #define NAND_Ecc_P64o (1 << 22) | |
57 | #define NAND_Ecc_P128o (1 << 23) | |
58 | #define NAND_Ecc_P256o (1 << 24) | |
59 | #define NAND_Ecc_P512o (1 << 25) | |
60 | #define NAND_Ecc_P1024o (1 << 26) | |
61 | #define NAND_Ecc_P2048o (1 << 27) | |
62 | ||
63 | #define TF(value) (value ? 1 : 0) | |
64 | ||
65 | #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0) | |
66 | #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1) | |
67 | #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2) | |
68 | #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3) | |
69 | #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4) | |
70 | #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5) | |
71 | #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6) | |
72 | #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7) | |
73 | ||
74 | #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0) | |
75 | #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1) | |
76 | #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2) | |
77 | #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3) | |
78 | #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4) | |
79 | #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5) | |
80 | #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6) | |
81 | #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7) | |
82 | ||
83 | #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0) | |
84 | #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1) | |
85 | #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2) | |
86 | #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3) | |
87 | #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4) | |
88 | #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5) | |
89 | #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6) | |
90 | #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7) | |
91 | ||
92 | #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0) | |
93 | #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1) | |
94 | #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2) | |
95 | #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3) | |
96 | #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4) | |
97 | #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5) | |
98 | #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6) | |
99 | #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7) | |
100 | ||
101 | #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) | |
102 | #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) | |
103 | ||
65b97cf6 AM |
104 | #define PREFETCH_CONFIG1_CS_SHIFT 24 |
105 | #define ECC_CONFIG_CS_SHIFT 1 | |
106 | #define CS_MASK 0x7 | |
107 | #define ENABLE_PREFETCH (0x1 << 7) | |
108 | #define DMA_MPU_MODE_SHIFT 2 | |
109 | #define ECCSIZE1_SHIFT 22 | |
110 | #define ECC1RESULTSIZE 0x1 | |
111 | #define ECCCLEAR 0x100 | |
112 | #define ECC1 0x1 | |
47f88af4 AM |
113 | #define PREFETCH_FIFOTHRESHOLD_MAX 0x40 |
114 | #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) | |
115 | #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) | |
116 | #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) | |
117 | #define STATUS_BUFF_EMPTY 0x00000001 | |
65b97cf6 | 118 | |
f040d332 SG |
119 | /* oob info generated runtime depending on ecc algorithm and layout selected */ |
120 | static struct nand_ecclayout omap_oobinfo; | |
121 | /* Define some generic bad / good block scan pattern which are used | |
122 | * while scanning a device for factory marked good / bad blocks | |
123 | */ | |
124 | static uint8_t scan_ff_pattern[] = { 0xff }; | |
125 | static struct nand_bbt_descr bb_descrip_flashbased = { | |
126 | .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES, | |
127 | .offs = 0, | |
128 | .len = 1, | |
129 | .pattern = scan_ff_pattern, | |
130 | }; | |
dfe32893 | 131 | |
59e9c5ae | 132 | |
67ce04bf VS |
133 | struct omap_nand_info { |
134 | struct nand_hw_control controller; | |
135 | struct omap_nand_platform_data *pdata; | |
136 | struct mtd_info mtd; | |
67ce04bf VS |
137 | struct nand_chip nand; |
138 | struct platform_device *pdev; | |
139 | ||
140 | int gpmc_cs; | |
141 | unsigned long phys_base; | |
9c4c2f8b | 142 | unsigned long mem_size; |
dfe32893 | 143 | struct completion comp; |
763e7359 | 144 | struct dma_chan *dma; |
5c468455 AM |
145 | int gpmc_irq_fifo; |
146 | int gpmc_irq_count; | |
4e070376 SG |
147 | enum { |
148 | OMAP_NAND_IO_READ = 0, /* read */ | |
149 | OMAP_NAND_IO_WRITE, /* write */ | |
150 | } iomode; | |
151 | u_char *buf; | |
152 | int buf_len; | |
65b97cf6 | 153 | struct gpmc_nand_regs reg; |
0e618ef0 ID |
154 | |
155 | #ifdef CONFIG_MTD_NAND_OMAP_BCH | |
156 | struct bch_control *bch; | |
157 | struct nand_ecclayout ecclayout; | |
158 | #endif | |
67ce04bf VS |
159 | }; |
160 | ||
65b97cf6 AM |
161 | /** |
162 | * omap_prefetch_enable - configures and starts prefetch transfer | |
163 | * @cs: cs (chip select) number | |
164 | * @fifo_th: fifo threshold to be used for read/ write | |
165 | * @dma_mode: dma mode enable (1) or disable (0) | |
166 | * @u32_count: number of bytes to be transferred | |
167 | * @is_write: prefetch read(0) or write post(1) mode | |
168 | */ | |
169 | static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode, | |
170 | unsigned int u32_count, int is_write, struct omap_nand_info *info) | |
171 | { | |
172 | u32 val; | |
173 | ||
174 | if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) | |
175 | return -1; | |
176 | ||
177 | if (readl(info->reg.gpmc_prefetch_control)) | |
178 | return -EBUSY; | |
179 | ||
180 | /* Set the amount of bytes to be prefetched */ | |
181 | writel(u32_count, info->reg.gpmc_prefetch_config2); | |
182 | ||
183 | /* Set dma/mpu mode, the prefetch read / post write and | |
184 | * enable the engine. Set which cs is has requested for. | |
185 | */ | |
186 | val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) | | |
187 | PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH | | |
188 | (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write)); | |
189 | writel(val, info->reg.gpmc_prefetch_config1); | |
190 | ||
191 | /* Start the prefetch engine */ | |
192 | writel(0x1, info->reg.gpmc_prefetch_control); | |
193 | ||
194 | return 0; | |
195 | } | |
196 | ||
197 | /** | |
198 | * omap_prefetch_reset - disables and stops the prefetch engine | |
199 | */ | |
200 | static int omap_prefetch_reset(int cs, struct omap_nand_info *info) | |
201 | { | |
202 | u32 config1; | |
203 | ||
204 | /* check if the same module/cs is trying to reset */ | |
205 | config1 = readl(info->reg.gpmc_prefetch_config1); | |
206 | if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs) | |
207 | return -EINVAL; | |
208 | ||
209 | /* Stop the PFPW engine */ | |
210 | writel(0x0, info->reg.gpmc_prefetch_control); | |
211 | ||
212 | /* Reset/disable the PFPW engine */ | |
213 | writel(0x0, info->reg.gpmc_prefetch_config1); | |
214 | ||
215 | return 0; | |
216 | } | |
217 | ||
67ce04bf VS |
218 | /** |
219 | * omap_hwcontrol - hardware specific access to control-lines | |
220 | * @mtd: MTD device structure | |
221 | * @cmd: command to device | |
222 | * @ctrl: | |
223 | * NAND_NCE: bit 0 -> don't care | |
224 | * NAND_CLE: bit 1 -> Command Latch | |
225 | * NAND_ALE: bit 2 -> Address Latch | |
226 | * | |
227 | * NOTE: boards may use different bits for these!! | |
228 | */ | |
229 | static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
230 | { | |
231 | struct omap_nand_info *info = container_of(mtd, | |
232 | struct omap_nand_info, mtd); | |
67ce04bf | 233 | |
2c01946c SG |
234 | if (cmd != NAND_CMD_NONE) { |
235 | if (ctrl & NAND_CLE) | |
65b97cf6 | 236 | writeb(cmd, info->reg.gpmc_nand_command); |
2c01946c SG |
237 | |
238 | else if (ctrl & NAND_ALE) | |
65b97cf6 | 239 | writeb(cmd, info->reg.gpmc_nand_address); |
2c01946c SG |
240 | |
241 | else /* NAND_NCE */ | |
65b97cf6 | 242 | writeb(cmd, info->reg.gpmc_nand_data); |
2c01946c | 243 | } |
67ce04bf VS |
244 | } |
245 | ||
59e9c5ae | 246 | /** |
247 | * omap_read_buf8 - read data from NAND controller into buffer | |
248 | * @mtd: MTD device structure | |
249 | * @buf: buffer to store date | |
250 | * @len: number of bytes to read | |
251 | */ | |
252 | static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len) | |
253 | { | |
254 | struct nand_chip *nand = mtd->priv; | |
255 | ||
256 | ioread8_rep(nand->IO_ADDR_R, buf, len); | |
257 | } | |
258 | ||
259 | /** | |
260 | * omap_write_buf8 - write buffer to NAND controller | |
261 | * @mtd: MTD device structure | |
262 | * @buf: data buffer | |
263 | * @len: number of bytes to write | |
264 | */ | |
265 | static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len) | |
266 | { | |
267 | struct omap_nand_info *info = container_of(mtd, | |
268 | struct omap_nand_info, mtd); | |
269 | u_char *p = (u_char *)buf; | |
2c01946c | 270 | u32 status = 0; |
59e9c5ae | 271 | |
272 | while (len--) { | |
273 | iowrite8(*p++, info->nand.IO_ADDR_W); | |
2c01946c SG |
274 | /* wait until buffer is available for write */ |
275 | do { | |
65b97cf6 | 276 | status = readl(info->reg.gpmc_status) & |
47f88af4 | 277 | STATUS_BUFF_EMPTY; |
2c01946c | 278 | } while (!status); |
59e9c5ae | 279 | } |
280 | } | |
281 | ||
67ce04bf VS |
282 | /** |
283 | * omap_read_buf16 - read data from NAND controller into buffer | |
284 | * @mtd: MTD device structure | |
285 | * @buf: buffer to store date | |
286 | * @len: number of bytes to read | |
287 | */ | |
288 | static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len) | |
289 | { | |
290 | struct nand_chip *nand = mtd->priv; | |
291 | ||
59e9c5ae | 292 | ioread16_rep(nand->IO_ADDR_R, buf, len / 2); |
67ce04bf VS |
293 | } |
294 | ||
295 | /** | |
296 | * omap_write_buf16 - write buffer to NAND controller | |
297 | * @mtd: MTD device structure | |
298 | * @buf: data buffer | |
299 | * @len: number of bytes to write | |
300 | */ | |
301 | static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len) | |
302 | { | |
303 | struct omap_nand_info *info = container_of(mtd, | |
304 | struct omap_nand_info, mtd); | |
305 | u16 *p = (u16 *) buf; | |
2c01946c | 306 | u32 status = 0; |
67ce04bf VS |
307 | /* FIXME try bursts of writesw() or DMA ... */ |
308 | len >>= 1; | |
309 | ||
310 | while (len--) { | |
59e9c5ae | 311 | iowrite16(*p++, info->nand.IO_ADDR_W); |
2c01946c SG |
312 | /* wait until buffer is available for write */ |
313 | do { | |
65b97cf6 | 314 | status = readl(info->reg.gpmc_status) & |
47f88af4 | 315 | STATUS_BUFF_EMPTY; |
2c01946c | 316 | } while (!status); |
67ce04bf VS |
317 | } |
318 | } | |
59e9c5ae | 319 | |
320 | /** | |
321 | * omap_read_buf_pref - read data from NAND controller into buffer | |
322 | * @mtd: MTD device structure | |
323 | * @buf: buffer to store date | |
324 | * @len: number of bytes to read | |
325 | */ | |
326 | static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) | |
327 | { | |
328 | struct omap_nand_info *info = container_of(mtd, | |
329 | struct omap_nand_info, mtd); | |
2c01946c | 330 | uint32_t r_count = 0; |
59e9c5ae | 331 | int ret = 0; |
332 | u32 *p = (u32 *)buf; | |
333 | ||
334 | /* take care of subpage reads */ | |
c3341d0c VS |
335 | if (len % 4) { |
336 | if (info->nand.options & NAND_BUSWIDTH_16) | |
337 | omap_read_buf16(mtd, buf, len % 4); | |
338 | else | |
339 | omap_read_buf8(mtd, buf, len % 4); | |
340 | p = (u32 *) (buf + len % 4); | |
341 | len -= len % 4; | |
59e9c5ae | 342 | } |
59e9c5ae | 343 | |
344 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
345 | ret = omap_prefetch_enable(info->gpmc_cs, |
346 | PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info); | |
59e9c5ae | 347 | if (ret) { |
348 | /* PFPW engine is busy, use cpu copy method */ | |
349 | if (info->nand.options & NAND_BUSWIDTH_16) | |
c5d8c0ca | 350 | omap_read_buf16(mtd, (u_char *)p, len); |
59e9c5ae | 351 | else |
c5d8c0ca | 352 | omap_read_buf8(mtd, (u_char *)p, len); |
59e9c5ae | 353 | } else { |
354 | do { | |
65b97cf6 | 355 | r_count = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 356 | r_count = PREFETCH_STATUS_FIFO_CNT(r_count); |
2c01946c SG |
357 | r_count = r_count >> 2; |
358 | ioread32_rep(info->nand.IO_ADDR_R, p, r_count); | |
59e9c5ae | 359 | p += r_count; |
360 | len -= r_count << 2; | |
361 | } while (len); | |
59e9c5ae | 362 | /* disable and stop the PFPW engine */ |
65b97cf6 | 363 | omap_prefetch_reset(info->gpmc_cs, info); |
59e9c5ae | 364 | } |
365 | } | |
366 | ||
367 | /** | |
368 | * omap_write_buf_pref - write buffer to NAND controller | |
369 | * @mtd: MTD device structure | |
370 | * @buf: data buffer | |
371 | * @len: number of bytes to write | |
372 | */ | |
373 | static void omap_write_buf_pref(struct mtd_info *mtd, | |
374 | const u_char *buf, int len) | |
375 | { | |
376 | struct omap_nand_info *info = container_of(mtd, | |
377 | struct omap_nand_info, mtd); | |
4e070376 | 378 | uint32_t w_count = 0; |
59e9c5ae | 379 | int i = 0, ret = 0; |
c5d8c0ca | 380 | u16 *p = (u16 *)buf; |
4e070376 | 381 | unsigned long tim, limit; |
65b97cf6 | 382 | u32 val; |
59e9c5ae | 383 | |
384 | /* take care of subpage writes */ | |
385 | if (len % 2 != 0) { | |
2c01946c | 386 | writeb(*buf, info->nand.IO_ADDR_W); |
59e9c5ae | 387 | p = (u16 *)(buf + 1); |
388 | len--; | |
389 | } | |
390 | ||
391 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
392 | ret = omap_prefetch_enable(info->gpmc_cs, |
393 | PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info); | |
59e9c5ae | 394 | if (ret) { |
395 | /* PFPW engine is busy, use cpu copy method */ | |
396 | if (info->nand.options & NAND_BUSWIDTH_16) | |
c5d8c0ca | 397 | omap_write_buf16(mtd, (u_char *)p, len); |
59e9c5ae | 398 | else |
c5d8c0ca | 399 | omap_write_buf8(mtd, (u_char *)p, len); |
59e9c5ae | 400 | } else { |
2c01946c | 401 | while (len) { |
65b97cf6 | 402 | w_count = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 403 | w_count = PREFETCH_STATUS_FIFO_CNT(w_count); |
2c01946c | 404 | w_count = w_count >> 1; |
59e9c5ae | 405 | for (i = 0; (i < w_count) && len; i++, len -= 2) |
2c01946c | 406 | iowrite16(*p++, info->nand.IO_ADDR_W); |
59e9c5ae | 407 | } |
2c01946c | 408 | /* wait for data to flushed-out before reset the prefetch */ |
4e070376 SG |
409 | tim = 0; |
410 | limit = (loops_per_jiffy * | |
411 | msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 | 412 | do { |
4e070376 | 413 | cpu_relax(); |
65b97cf6 | 414 | val = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 415 | val = PREFETCH_STATUS_COUNT(val); |
65b97cf6 | 416 | } while (val && (tim++ < limit)); |
4e070376 | 417 | |
59e9c5ae | 418 | /* disable and stop the PFPW engine */ |
65b97cf6 | 419 | omap_prefetch_reset(info->gpmc_cs, info); |
59e9c5ae | 420 | } |
421 | } | |
422 | ||
dfe32893 | 423 | /* |
2df41d05 | 424 | * omap_nand_dma_callback: callback on the completion of dma transfer |
dfe32893 | 425 | * @data: pointer to completion data structure |
426 | */ | |
763e7359 RK |
427 | static void omap_nand_dma_callback(void *data) |
428 | { | |
429 | complete((struct completion *) data); | |
430 | } | |
dfe32893 | 431 | |
432 | /* | |
4cacbe22 | 433 | * omap_nand_dma_transfer: configure and start dma transfer |
dfe32893 | 434 | * @mtd: MTD device structure |
435 | * @addr: virtual address in RAM of source/destination | |
436 | * @len: number of data bytes to be transferred | |
437 | * @is_write: flag for read/write operation | |
438 | */ | |
439 | static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, | |
440 | unsigned int len, int is_write) | |
441 | { | |
442 | struct omap_nand_info *info = container_of(mtd, | |
443 | struct omap_nand_info, mtd); | |
2df41d05 | 444 | struct dma_async_tx_descriptor *tx; |
dfe32893 | 445 | enum dma_data_direction dir = is_write ? DMA_TO_DEVICE : |
446 | DMA_FROM_DEVICE; | |
2df41d05 | 447 | struct scatterlist sg; |
4e070376 | 448 | unsigned long tim, limit; |
2df41d05 RK |
449 | unsigned n; |
450 | int ret; | |
65b97cf6 | 451 | u32 val; |
dfe32893 | 452 | |
453 | if (addr >= high_memory) { | |
454 | struct page *p1; | |
455 | ||
456 | if (((size_t)addr & PAGE_MASK) != | |
457 | ((size_t)(addr + len - 1) & PAGE_MASK)) | |
458 | goto out_copy; | |
459 | p1 = vmalloc_to_page(addr); | |
460 | if (!p1) | |
461 | goto out_copy; | |
462 | addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK); | |
463 | } | |
464 | ||
2df41d05 RK |
465 | sg_init_one(&sg, addr, len); |
466 | n = dma_map_sg(info->dma->device->dev, &sg, 1, dir); | |
467 | if (n == 0) { | |
dfe32893 | 468 | dev_err(&info->pdev->dev, |
469 | "Couldn't DMA map a %d byte buffer\n", len); | |
470 | goto out_copy; | |
471 | } | |
472 | ||
2df41d05 RK |
473 | tx = dmaengine_prep_slave_sg(info->dma, &sg, n, |
474 | is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, | |
475 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
476 | if (!tx) | |
477 | goto out_copy_unmap; | |
478 | ||
479 | tx->callback = omap_nand_dma_callback; | |
480 | tx->callback_param = &info->comp; | |
481 | dmaengine_submit(tx); | |
482 | ||
65b97cf6 AM |
483 | /* configure and start prefetch transfer */ |
484 | ret = omap_prefetch_enable(info->gpmc_cs, | |
485 | PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info); | |
dfe32893 | 486 | if (ret) |
4e070376 | 487 | /* PFPW engine is busy, use cpu copy method */ |
d7efe228 | 488 | goto out_copy_unmap; |
dfe32893 | 489 | |
490 | init_completion(&info->comp); | |
2df41d05 | 491 | dma_async_issue_pending(info->dma); |
dfe32893 | 492 | |
493 | /* setup and start DMA using dma_addr */ | |
494 | wait_for_completion(&info->comp); | |
4e070376 SG |
495 | tim = 0; |
496 | limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 AM |
497 | |
498 | do { | |
4e070376 | 499 | cpu_relax(); |
65b97cf6 | 500 | val = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 501 | val = PREFETCH_STATUS_COUNT(val); |
65b97cf6 | 502 | } while (val && (tim++ < limit)); |
dfe32893 | 503 | |
dfe32893 | 504 | /* disable and stop the PFPW engine */ |
65b97cf6 | 505 | omap_prefetch_reset(info->gpmc_cs, info); |
dfe32893 | 506 | |
2df41d05 | 507 | dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); |
dfe32893 | 508 | return 0; |
509 | ||
d7efe228 | 510 | out_copy_unmap: |
2df41d05 | 511 | dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); |
dfe32893 | 512 | out_copy: |
513 | if (info->nand.options & NAND_BUSWIDTH_16) | |
514 | is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len) | |
515 | : omap_write_buf16(mtd, (u_char *) addr, len); | |
516 | else | |
517 | is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len) | |
518 | : omap_write_buf8(mtd, (u_char *) addr, len); | |
519 | return 0; | |
520 | } | |
dfe32893 | 521 | |
522 | /** | |
523 | * omap_read_buf_dma_pref - read data from NAND controller into buffer | |
524 | * @mtd: MTD device structure | |
525 | * @buf: buffer to store date | |
526 | * @len: number of bytes to read | |
527 | */ | |
528 | static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len) | |
529 | { | |
530 | if (len <= mtd->oobsize) | |
531 | omap_read_buf_pref(mtd, buf, len); | |
532 | else | |
533 | /* start transfer in DMA mode */ | |
534 | omap_nand_dma_transfer(mtd, buf, len, 0x0); | |
535 | } | |
536 | ||
537 | /** | |
538 | * omap_write_buf_dma_pref - write buffer to NAND controller | |
539 | * @mtd: MTD device structure | |
540 | * @buf: data buffer | |
541 | * @len: number of bytes to write | |
542 | */ | |
543 | static void omap_write_buf_dma_pref(struct mtd_info *mtd, | |
544 | const u_char *buf, int len) | |
545 | { | |
546 | if (len <= mtd->oobsize) | |
547 | omap_write_buf_pref(mtd, buf, len); | |
548 | else | |
549 | /* start transfer in DMA mode */ | |
bdaefc41 | 550 | omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1); |
dfe32893 | 551 | } |
552 | ||
4e070376 | 553 | /* |
4cacbe22 | 554 | * omap_nand_irq - GPMC irq handler |
4e070376 SG |
555 | * @this_irq: gpmc irq number |
556 | * @dev: omap_nand_info structure pointer is passed here | |
557 | */ | |
558 | static irqreturn_t omap_nand_irq(int this_irq, void *dev) | |
559 | { | |
560 | struct omap_nand_info *info = (struct omap_nand_info *) dev; | |
561 | u32 bytes; | |
4e070376 | 562 | |
65b97cf6 | 563 | bytes = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 564 | bytes = PREFETCH_STATUS_FIFO_CNT(bytes); |
4e070376 SG |
565 | bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ |
566 | if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ | |
5c468455 | 567 | if (this_irq == info->gpmc_irq_count) |
4e070376 SG |
568 | goto done; |
569 | ||
570 | if (info->buf_len && (info->buf_len < bytes)) | |
571 | bytes = info->buf_len; | |
572 | else if (!info->buf_len) | |
573 | bytes = 0; | |
574 | iowrite32_rep(info->nand.IO_ADDR_W, | |
575 | (u32 *)info->buf, bytes >> 2); | |
576 | info->buf = info->buf + bytes; | |
577 | info->buf_len -= bytes; | |
578 | ||
579 | } else { | |
580 | ioread32_rep(info->nand.IO_ADDR_R, | |
581 | (u32 *)info->buf, bytes >> 2); | |
582 | info->buf = info->buf + bytes; | |
583 | ||
5c468455 | 584 | if (this_irq == info->gpmc_irq_count) |
4e070376 SG |
585 | goto done; |
586 | } | |
4e070376 SG |
587 | |
588 | return IRQ_HANDLED; | |
589 | ||
590 | done: | |
591 | complete(&info->comp); | |
4e070376 | 592 | |
5c468455 AM |
593 | disable_irq_nosync(info->gpmc_irq_fifo); |
594 | disable_irq_nosync(info->gpmc_irq_count); | |
4e070376 SG |
595 | |
596 | return IRQ_HANDLED; | |
597 | } | |
598 | ||
599 | /* | |
600 | * omap_read_buf_irq_pref - read data from NAND controller into buffer | |
601 | * @mtd: MTD device structure | |
602 | * @buf: buffer to store date | |
603 | * @len: number of bytes to read | |
604 | */ | |
605 | static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) | |
606 | { | |
607 | struct omap_nand_info *info = container_of(mtd, | |
608 | struct omap_nand_info, mtd); | |
609 | int ret = 0; | |
610 | ||
611 | if (len <= mtd->oobsize) { | |
612 | omap_read_buf_pref(mtd, buf, len); | |
613 | return; | |
614 | } | |
615 | ||
616 | info->iomode = OMAP_NAND_IO_READ; | |
617 | info->buf = buf; | |
618 | init_completion(&info->comp); | |
619 | ||
620 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
621 | ret = omap_prefetch_enable(info->gpmc_cs, |
622 | PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info); | |
4e070376 SG |
623 | if (ret) |
624 | /* PFPW engine is busy, use cpu copy method */ | |
625 | goto out_copy; | |
626 | ||
627 | info->buf_len = len; | |
5c468455 AM |
628 | |
629 | enable_irq(info->gpmc_irq_count); | |
630 | enable_irq(info->gpmc_irq_fifo); | |
4e070376 SG |
631 | |
632 | /* waiting for read to complete */ | |
633 | wait_for_completion(&info->comp); | |
634 | ||
635 | /* disable and stop the PFPW engine */ | |
65b97cf6 | 636 | omap_prefetch_reset(info->gpmc_cs, info); |
4e070376 SG |
637 | return; |
638 | ||
639 | out_copy: | |
640 | if (info->nand.options & NAND_BUSWIDTH_16) | |
641 | omap_read_buf16(mtd, buf, len); | |
642 | else | |
643 | omap_read_buf8(mtd, buf, len); | |
644 | } | |
645 | ||
646 | /* | |
647 | * omap_write_buf_irq_pref - write buffer to NAND controller | |
648 | * @mtd: MTD device structure | |
649 | * @buf: data buffer | |
650 | * @len: number of bytes to write | |
651 | */ | |
652 | static void omap_write_buf_irq_pref(struct mtd_info *mtd, | |
653 | const u_char *buf, int len) | |
654 | { | |
655 | struct omap_nand_info *info = container_of(mtd, | |
656 | struct omap_nand_info, mtd); | |
657 | int ret = 0; | |
658 | unsigned long tim, limit; | |
65b97cf6 | 659 | u32 val; |
4e070376 SG |
660 | |
661 | if (len <= mtd->oobsize) { | |
662 | omap_write_buf_pref(mtd, buf, len); | |
663 | return; | |
664 | } | |
665 | ||
666 | info->iomode = OMAP_NAND_IO_WRITE; | |
667 | info->buf = (u_char *) buf; | |
668 | init_completion(&info->comp); | |
669 | ||
317379a9 | 670 | /* configure and start prefetch transfer : size=24 */ |
65b97cf6 AM |
671 | ret = omap_prefetch_enable(info->gpmc_cs, |
672 | (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info); | |
4e070376 SG |
673 | if (ret) |
674 | /* PFPW engine is busy, use cpu copy method */ | |
675 | goto out_copy; | |
676 | ||
677 | info->buf_len = len; | |
5c468455 AM |
678 | |
679 | enable_irq(info->gpmc_irq_count); | |
680 | enable_irq(info->gpmc_irq_fifo); | |
4e070376 SG |
681 | |
682 | /* waiting for write to complete */ | |
683 | wait_for_completion(&info->comp); | |
5c468455 | 684 | |
4e070376 SG |
685 | /* wait for data to flushed-out before reset the prefetch */ |
686 | tim = 0; | |
687 | limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 AM |
688 | do { |
689 | val = readl(info->reg.gpmc_prefetch_status); | |
47f88af4 | 690 | val = PREFETCH_STATUS_COUNT(val); |
4e070376 | 691 | cpu_relax(); |
65b97cf6 | 692 | } while (val && (tim++ < limit)); |
4e070376 SG |
693 | |
694 | /* disable and stop the PFPW engine */ | |
65b97cf6 | 695 | omap_prefetch_reset(info->gpmc_cs, info); |
4e070376 SG |
696 | return; |
697 | ||
698 | out_copy: | |
699 | if (info->nand.options & NAND_BUSWIDTH_16) | |
700 | omap_write_buf16(mtd, buf, len); | |
701 | else | |
702 | omap_write_buf8(mtd, buf, len); | |
703 | } | |
704 | ||
67ce04bf VS |
705 | /** |
706 | * gen_true_ecc - This function will generate true ECC value | |
707 | * @ecc_buf: buffer to store ecc code | |
708 | * | |
709 | * This generated true ECC value can be used when correcting | |
710 | * data read from NAND flash memory core | |
711 | */ | |
712 | static void gen_true_ecc(u8 *ecc_buf) | |
713 | { | |
714 | u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) | | |
715 | ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8); | |
716 | ||
717 | ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | | |
718 | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp)); | |
719 | ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | | |
720 | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp)); | |
721 | ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | | |
722 | P1e(tmp) | P2048o(tmp) | P2048e(tmp)); | |
723 | } | |
724 | ||
725 | /** | |
726 | * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data | |
727 | * @ecc_data1: ecc code from nand spare area | |
728 | * @ecc_data2: ecc code from hardware register obtained from hardware ecc | |
729 | * @page_data: page data | |
730 | * | |
731 | * This function compares two ECC's and indicates if there is an error. | |
732 | * If the error can be corrected it will be corrected to the buffer. | |
74f1b724 JO |
733 | * If there is no error, %0 is returned. If there is an error but it |
734 | * was corrected, %1 is returned. Otherwise, %-1 is returned. | |
67ce04bf VS |
735 | */ |
736 | static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */ | |
737 | u8 *ecc_data2, /* read from register */ | |
738 | u8 *page_data) | |
739 | { | |
740 | uint i; | |
741 | u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8]; | |
742 | u8 comp0_bit[8], comp1_bit[8], comp2_bit[8]; | |
743 | u8 ecc_bit[24]; | |
744 | u8 ecc_sum = 0; | |
745 | u8 find_bit = 0; | |
746 | uint find_byte = 0; | |
747 | int isEccFF; | |
748 | ||
749 | isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF); | |
750 | ||
751 | gen_true_ecc(ecc_data1); | |
752 | gen_true_ecc(ecc_data2); | |
753 | ||
754 | for (i = 0; i <= 2; i++) { | |
755 | *(ecc_data1 + i) = ~(*(ecc_data1 + i)); | |
756 | *(ecc_data2 + i) = ~(*(ecc_data2 + i)); | |
757 | } | |
758 | ||
759 | for (i = 0; i < 8; i++) { | |
760 | tmp0_bit[i] = *ecc_data1 % 2; | |
761 | *ecc_data1 = *ecc_data1 / 2; | |
762 | } | |
763 | ||
764 | for (i = 0; i < 8; i++) { | |
765 | tmp1_bit[i] = *(ecc_data1 + 1) % 2; | |
766 | *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2; | |
767 | } | |
768 | ||
769 | for (i = 0; i < 8; i++) { | |
770 | tmp2_bit[i] = *(ecc_data1 + 2) % 2; | |
771 | *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2; | |
772 | } | |
773 | ||
774 | for (i = 0; i < 8; i++) { | |
775 | comp0_bit[i] = *ecc_data2 % 2; | |
776 | *ecc_data2 = *ecc_data2 / 2; | |
777 | } | |
778 | ||
779 | for (i = 0; i < 8; i++) { | |
780 | comp1_bit[i] = *(ecc_data2 + 1) % 2; | |
781 | *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2; | |
782 | } | |
783 | ||
784 | for (i = 0; i < 8; i++) { | |
785 | comp2_bit[i] = *(ecc_data2 + 2) % 2; | |
786 | *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2; | |
787 | } | |
788 | ||
789 | for (i = 0; i < 6; i++) | |
790 | ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2]; | |
791 | ||
792 | for (i = 0; i < 8; i++) | |
793 | ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i]; | |
794 | ||
795 | for (i = 0; i < 8; i++) | |
796 | ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i]; | |
797 | ||
798 | ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0]; | |
799 | ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1]; | |
800 | ||
801 | for (i = 0; i < 24; i++) | |
802 | ecc_sum += ecc_bit[i]; | |
803 | ||
804 | switch (ecc_sum) { | |
805 | case 0: | |
806 | /* Not reached because this function is not called if | |
807 | * ECC values are equal | |
808 | */ | |
809 | return 0; | |
810 | ||
811 | case 1: | |
812 | /* Uncorrectable error */ | |
289c0522 | 813 | pr_debug("ECC UNCORRECTED_ERROR 1\n"); |
67ce04bf VS |
814 | return -1; |
815 | ||
816 | case 11: | |
817 | /* UN-Correctable error */ | |
289c0522 | 818 | pr_debug("ECC UNCORRECTED_ERROR B\n"); |
67ce04bf VS |
819 | return -1; |
820 | ||
821 | case 12: | |
822 | /* Correctable error */ | |
823 | find_byte = (ecc_bit[23] << 8) + | |
824 | (ecc_bit[21] << 7) + | |
825 | (ecc_bit[19] << 6) + | |
826 | (ecc_bit[17] << 5) + | |
827 | (ecc_bit[15] << 4) + | |
828 | (ecc_bit[13] << 3) + | |
829 | (ecc_bit[11] << 2) + | |
830 | (ecc_bit[9] << 1) + | |
831 | ecc_bit[7]; | |
832 | ||
833 | find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; | |
834 | ||
0a32a102 BN |
835 | pr_debug("Correcting single bit ECC error at offset: " |
836 | "%d, bit: %d\n", find_byte, find_bit); | |
67ce04bf VS |
837 | |
838 | page_data[find_byte] ^= (1 << find_bit); | |
839 | ||
74f1b724 | 840 | return 1; |
67ce04bf VS |
841 | default: |
842 | if (isEccFF) { | |
843 | if (ecc_data2[0] == 0 && | |
844 | ecc_data2[1] == 0 && | |
845 | ecc_data2[2] == 0) | |
846 | return 0; | |
847 | } | |
289c0522 | 848 | pr_debug("UNCORRECTED_ERROR default\n"); |
67ce04bf VS |
849 | return -1; |
850 | } | |
851 | } | |
852 | ||
853 | /** | |
854 | * omap_correct_data - Compares the ECC read with HW generated ECC | |
855 | * @mtd: MTD device structure | |
856 | * @dat: page data | |
857 | * @read_ecc: ecc read from nand flash | |
858 | * @calc_ecc: ecc read from HW ECC registers | |
859 | * | |
860 | * Compares the ecc read from nand spare area with ECC registers values | |
74f1b724 JO |
861 | * and if ECC's mismatched, it will call 'omap_compare_ecc' for error |
862 | * detection and correction. If there are no errors, %0 is returned. If | |
863 | * there were errors and all of the errors were corrected, the number of | |
864 | * corrected errors is returned. If uncorrectable errors exist, %-1 is | |
865 | * returned. | |
67ce04bf VS |
866 | */ |
867 | static int omap_correct_data(struct mtd_info *mtd, u_char *dat, | |
868 | u_char *read_ecc, u_char *calc_ecc) | |
869 | { | |
870 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
871 | mtd); | |
872 | int blockCnt = 0, i = 0, ret = 0; | |
74f1b724 | 873 | int stat = 0; |
67ce04bf VS |
874 | |
875 | /* Ex NAND_ECC_HW12_2048 */ | |
876 | if ((info->nand.ecc.mode == NAND_ECC_HW) && | |
877 | (info->nand.ecc.size == 2048)) | |
878 | blockCnt = 4; | |
879 | else | |
880 | blockCnt = 1; | |
881 | ||
882 | for (i = 0; i < blockCnt; i++) { | |
883 | if (memcmp(read_ecc, calc_ecc, 3) != 0) { | |
884 | ret = omap_compare_ecc(read_ecc, calc_ecc, dat); | |
885 | if (ret < 0) | |
886 | return ret; | |
74f1b724 JO |
887 | /* keep track of the number of corrected errors */ |
888 | stat += ret; | |
67ce04bf VS |
889 | } |
890 | read_ecc += 3; | |
891 | calc_ecc += 3; | |
892 | dat += 512; | |
893 | } | |
74f1b724 | 894 | return stat; |
67ce04bf VS |
895 | } |
896 | ||
897 | /** | |
898 | * omap_calcuate_ecc - Generate non-inverted ECC bytes. | |
899 | * @mtd: MTD device structure | |
900 | * @dat: The pointer to data on which ecc is computed | |
901 | * @ecc_code: The ecc_code buffer | |
902 | * | |
903 | * Using noninverted ECC can be considered ugly since writing a blank | |
904 | * page ie. padding will clear the ECC bytes. This is no problem as long | |
905 | * nobody is trying to write data on the seemingly unused page. Reading | |
906 | * an erased page will produce an ECC mismatch between generated and read | |
907 | * ECC bytes that has to be dealt with separately. | |
908 | */ | |
909 | static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat, | |
910 | u_char *ecc_code) | |
911 | { | |
912 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
913 | mtd); | |
65b97cf6 AM |
914 | u32 val; |
915 | ||
916 | val = readl(info->reg.gpmc_ecc_config); | |
917 | if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs) | |
918 | return -EINVAL; | |
919 | ||
920 | /* read ecc result */ | |
921 | val = readl(info->reg.gpmc_ecc1_result); | |
922 | *ecc_code++ = val; /* P128e, ..., P1e */ | |
923 | *ecc_code++ = val >> 16; /* P128o, ..., P1o */ | |
924 | /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ | |
925 | *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); | |
926 | ||
927 | return 0; | |
67ce04bf VS |
928 | } |
929 | ||
930 | /** | |
931 | * omap_enable_hwecc - This function enables the hardware ecc functionality | |
932 | * @mtd: MTD device structure | |
933 | * @mode: Read/Write mode | |
934 | */ | |
935 | static void omap_enable_hwecc(struct mtd_info *mtd, int mode) | |
936 | { | |
937 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
938 | mtd); | |
939 | struct nand_chip *chip = mtd->priv; | |
940 | unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; | |
65b97cf6 AM |
941 | u32 val; |
942 | ||
943 | /* clear ecc and enable bits */ | |
944 | val = ECCCLEAR | ECC1; | |
945 | writel(val, info->reg.gpmc_ecc_control); | |
67ce04bf | 946 | |
65b97cf6 AM |
947 | /* program ecc and result sizes */ |
948 | val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) | | |
949 | ECC1RESULTSIZE); | |
950 | writel(val, info->reg.gpmc_ecc_size_config); | |
951 | ||
952 | switch (mode) { | |
953 | case NAND_ECC_READ: | |
954 | case NAND_ECC_WRITE: | |
955 | writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); | |
956 | break; | |
957 | case NAND_ECC_READSYN: | |
958 | writel(ECCCLEAR, info->reg.gpmc_ecc_control); | |
959 | break; | |
960 | default: | |
961 | dev_info(&info->pdev->dev, | |
962 | "error: unrecognized Mode[%d]!\n", mode); | |
963 | break; | |
964 | } | |
67ce04bf | 965 | |
65b97cf6 AM |
966 | /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ |
967 | val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); | |
968 | writel(val, info->reg.gpmc_ecc_config); | |
67ce04bf | 969 | } |
2c01946c | 970 | |
67ce04bf VS |
971 | /** |
972 | * omap_wait - wait until the command is done | |
973 | * @mtd: MTD device structure | |
974 | * @chip: NAND Chip structure | |
975 | * | |
976 | * Wait function is called during Program and erase operations and | |
977 | * the way it is called from MTD layer, we should wait till the NAND | |
978 | * chip is ready after the programming/erase operation has completed. | |
979 | * | |
980 | * Erase can take up to 400ms and program up to 20ms according to | |
981 | * general NAND and SmartMedia specs | |
982 | */ | |
983 | static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
984 | { | |
985 | struct nand_chip *this = mtd->priv; | |
986 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
987 | mtd); | |
988 | unsigned long timeo = jiffies; | |
a9c465f0 | 989 | int status, state = this->state; |
67ce04bf VS |
990 | |
991 | if (state == FL_ERASING) | |
992 | timeo += (HZ * 400) / 1000; | |
993 | else | |
994 | timeo += (HZ * 20) / 1000; | |
995 | ||
65b97cf6 | 996 | writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command); |
67ce04bf | 997 | while (time_before(jiffies, timeo)) { |
65b97cf6 | 998 | status = readb(info->reg.gpmc_nand_data); |
c276aca4 | 999 | if (status & NAND_STATUS_READY) |
67ce04bf | 1000 | break; |
c276aca4 | 1001 | cond_resched(); |
67ce04bf | 1002 | } |
a9c465f0 | 1003 | |
4ea1e4ba | 1004 | status = readb(info->reg.gpmc_nand_data); |
67ce04bf VS |
1005 | return status; |
1006 | } | |
1007 | ||
1008 | /** | |
1009 | * omap_dev_ready - calls the platform specific dev_ready function | |
1010 | * @mtd: MTD device structure | |
1011 | */ | |
1012 | static int omap_dev_ready(struct mtd_info *mtd) | |
1013 | { | |
2c01946c | 1014 | unsigned int val = 0; |
67ce04bf VS |
1015 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
1016 | mtd); | |
67ce04bf | 1017 | |
65b97cf6 AM |
1018 | val = readl(info->reg.gpmc_status); |
1019 | ||
67ce04bf | 1020 | if ((val & 0x100) == 0x100) { |
65b97cf6 | 1021 | return 1; |
67ce04bf | 1022 | } else { |
65b97cf6 | 1023 | return 0; |
67ce04bf | 1024 | } |
67ce04bf VS |
1025 | } |
1026 | ||
0e618ef0 ID |
1027 | #ifdef CONFIG_MTD_NAND_OMAP_BCH |
1028 | ||
1029 | /** | |
1030 | * omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction | |
1031 | * @mtd: MTD device structure | |
1032 | * @mode: Read/Write mode | |
1033 | */ | |
1034 | static void omap3_enable_hwecc_bch(struct mtd_info *mtd, int mode) | |
1035 | { | |
1036 | int nerrors; | |
1037 | unsigned int dev_width; | |
1038 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1039 | mtd); | |
1040 | struct nand_chip *chip = mtd->priv; | |
1041 | ||
1042 | nerrors = (info->nand.ecc.bytes == 13) ? 8 : 4; | |
1043 | dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; | |
1044 | /* | |
1045 | * Program GPMC to perform correction on one 512-byte sector at a time. | |
1046 | * Using 4 sectors at a time (i.e. ecc.size = 2048) is also possible and | |
1047 | * gives a slight (5%) performance gain (but requires additional code). | |
1048 | */ | |
1049 | (void)gpmc_enable_hwecc_bch(info->gpmc_cs, mode, dev_width, 1, nerrors); | |
1050 | } | |
1051 | ||
1052 | /** | |
1053 | * omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC bytes | |
1054 | * @mtd: MTD device structure | |
1055 | * @dat: The pointer to data on which ecc is computed | |
1056 | * @ecc_code: The ecc_code buffer | |
1057 | */ | |
1058 | static int omap3_calculate_ecc_bch4(struct mtd_info *mtd, const u_char *dat, | |
1059 | u_char *ecc_code) | |
1060 | { | |
1061 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1062 | mtd); | |
1063 | return gpmc_calculate_ecc_bch4(info->gpmc_cs, dat, ecc_code); | |
1064 | } | |
1065 | ||
1066 | /** | |
1067 | * omap3_calculate_ecc_bch8 - Generate 13 bytes of ECC bytes | |
1068 | * @mtd: MTD device structure | |
1069 | * @dat: The pointer to data on which ecc is computed | |
1070 | * @ecc_code: The ecc_code buffer | |
1071 | */ | |
1072 | static int omap3_calculate_ecc_bch8(struct mtd_info *mtd, const u_char *dat, | |
1073 | u_char *ecc_code) | |
1074 | { | |
1075 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1076 | mtd); | |
1077 | return gpmc_calculate_ecc_bch8(info->gpmc_cs, dat, ecc_code); | |
1078 | } | |
1079 | ||
1080 | /** | |
1081 | * omap3_correct_data_bch - Decode received data and correct errors | |
1082 | * @mtd: MTD device structure | |
1083 | * @data: page data | |
1084 | * @read_ecc: ecc read from nand flash | |
1085 | * @calc_ecc: ecc read from HW ECC registers | |
1086 | */ | |
1087 | static int omap3_correct_data_bch(struct mtd_info *mtd, u_char *data, | |
1088 | u_char *read_ecc, u_char *calc_ecc) | |
1089 | { | |
1090 | int i, count; | |
1091 | /* cannot correct more than 8 errors */ | |
1092 | unsigned int errloc[8]; | |
1093 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1094 | mtd); | |
1095 | ||
1096 | count = decode_bch(info->bch, NULL, 512, read_ecc, calc_ecc, NULL, | |
1097 | errloc); | |
1098 | if (count > 0) { | |
1099 | /* correct errors */ | |
1100 | for (i = 0; i < count; i++) { | |
1101 | /* correct data only, not ecc bytes */ | |
1102 | if (errloc[i] < 8*512) | |
1103 | data[errloc[i]/8] ^= 1 << (errloc[i] & 7); | |
1104 | pr_debug("corrected bitflip %u\n", errloc[i]); | |
1105 | } | |
1106 | } else if (count < 0) { | |
1107 | pr_err("ecc unrecoverable error\n"); | |
1108 | } | |
1109 | return count; | |
1110 | } | |
1111 | ||
1112 | /** | |
1113 | * omap3_free_bch - Release BCH ecc resources | |
1114 | * @mtd: MTD device structure | |
1115 | */ | |
1116 | static void omap3_free_bch(struct mtd_info *mtd) | |
1117 | { | |
1118 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1119 | mtd); | |
1120 | if (info->bch) { | |
1121 | free_bch(info->bch); | |
1122 | info->bch = NULL; | |
1123 | } | |
1124 | } | |
1125 | ||
1126 | /** | |
1127 | * omap3_init_bch - Initialize BCH ECC | |
1128 | * @mtd: MTD device structure | |
1129 | * @ecc_opt: OMAP ECC mode (OMAP_ECC_BCH4_CODE_HW or OMAP_ECC_BCH8_CODE_HW) | |
1130 | */ | |
1131 | static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt) | |
1132 | { | |
1133 | int ret, max_errors; | |
1134 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1135 | mtd); | |
1136 | #ifdef CONFIG_MTD_NAND_OMAP_BCH8 | |
1137 | const int hw_errors = 8; | |
1138 | #else | |
1139 | const int hw_errors = 4; | |
1140 | #endif | |
1141 | info->bch = NULL; | |
1142 | ||
1143 | max_errors = (ecc_opt == OMAP_ECC_BCH8_CODE_HW) ? 8 : 4; | |
1144 | if (max_errors != hw_errors) { | |
1145 | pr_err("cannot configure %d-bit BCH ecc, only %d-bit supported", | |
1146 | max_errors, hw_errors); | |
1147 | goto fail; | |
1148 | } | |
1149 | ||
1150 | /* initialize GPMC BCH engine */ | |
1151 | ret = gpmc_init_hwecc_bch(info->gpmc_cs, 1, max_errors); | |
1152 | if (ret) | |
1153 | goto fail; | |
1154 | ||
1155 | /* software bch library is only used to detect and locate errors */ | |
1156 | info->bch = init_bch(13, max_errors, 0x201b /* hw polynomial */); | |
1157 | if (!info->bch) | |
1158 | goto fail; | |
1159 | ||
1160 | info->nand.ecc.size = 512; | |
1161 | info->nand.ecc.hwctl = omap3_enable_hwecc_bch; | |
1162 | info->nand.ecc.correct = omap3_correct_data_bch; | |
1163 | info->nand.ecc.mode = NAND_ECC_HW; | |
1164 | ||
1165 | /* | |
1166 | * The number of corrected errors in an ecc block that will trigger | |
1167 | * block scrubbing defaults to the ecc strength (4 or 8). | |
1168 | * Set mtd->bitflip_threshold here to define a custom threshold. | |
1169 | */ | |
1170 | ||
1171 | if (max_errors == 8) { | |
1172 | info->nand.ecc.strength = 8; | |
1173 | info->nand.ecc.bytes = 13; | |
1174 | info->nand.ecc.calculate = omap3_calculate_ecc_bch8; | |
1175 | } else { | |
1176 | info->nand.ecc.strength = 4; | |
1177 | info->nand.ecc.bytes = 7; | |
1178 | info->nand.ecc.calculate = omap3_calculate_ecc_bch4; | |
1179 | } | |
1180 | ||
1181 | pr_info("enabling NAND BCH ecc with %d-bit correction\n", max_errors); | |
1182 | return 0; | |
1183 | fail: | |
1184 | omap3_free_bch(mtd); | |
1185 | return -1; | |
1186 | } | |
1187 | ||
1188 | /** | |
1189 | * omap3_init_bch_tail - Build an oob layout for BCH ECC correction. | |
1190 | * @mtd: MTD device structure | |
1191 | */ | |
1192 | static int omap3_init_bch_tail(struct mtd_info *mtd) | |
1193 | { | |
1194 | int i, steps; | |
1195 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1196 | mtd); | |
1197 | struct nand_ecclayout *layout = &info->ecclayout; | |
1198 | ||
1199 | /* build oob layout */ | |
1200 | steps = mtd->writesize/info->nand.ecc.size; | |
1201 | layout->eccbytes = steps*info->nand.ecc.bytes; | |
1202 | ||
1203 | /* do not bother creating special oob layouts for small page devices */ | |
1204 | if (mtd->oobsize < 64) { | |
1205 | pr_err("BCH ecc is not supported on small page devices\n"); | |
1206 | goto fail; | |
1207 | } | |
1208 | ||
1209 | /* reserve 2 bytes for bad block marker */ | |
1210 | if (layout->eccbytes+2 > mtd->oobsize) { | |
1211 | pr_err("no oob layout available for oobsize %d eccbytes %u\n", | |
1212 | mtd->oobsize, layout->eccbytes); | |
1213 | goto fail; | |
1214 | } | |
1215 | ||
1216 | /* put ecc bytes at oob tail */ | |
1217 | for (i = 0; i < layout->eccbytes; i++) | |
1218 | layout->eccpos[i] = mtd->oobsize-layout->eccbytes+i; | |
1219 | ||
1220 | layout->oobfree[0].offset = 2; | |
1221 | layout->oobfree[0].length = mtd->oobsize-2-layout->eccbytes; | |
1222 | info->nand.ecc.layout = layout; | |
1223 | ||
1224 | if (!(info->nand.options & NAND_BUSWIDTH_16)) | |
1225 | info->nand.badblock_pattern = &bb_descrip_flashbased; | |
1226 | return 0; | |
1227 | fail: | |
1228 | omap3_free_bch(mtd); | |
1229 | return -1; | |
1230 | } | |
1231 | ||
1232 | #else | |
1233 | static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt) | |
1234 | { | |
1235 | pr_err("CONFIG_MTD_NAND_OMAP_BCH is not enabled\n"); | |
1236 | return -1; | |
1237 | } | |
1238 | static int omap3_init_bch_tail(struct mtd_info *mtd) | |
1239 | { | |
1240 | return -1; | |
1241 | } | |
1242 | static void omap3_free_bch(struct mtd_info *mtd) | |
1243 | { | |
1244 | } | |
1245 | #endif /* CONFIG_MTD_NAND_OMAP_BCH */ | |
1246 | ||
67ce04bf VS |
1247 | static int __devinit omap_nand_probe(struct platform_device *pdev) |
1248 | { | |
1249 | struct omap_nand_info *info; | |
1250 | struct omap_nand_platform_data *pdata; | |
1251 | int err; | |
f040d332 | 1252 | int i, offset; |
763e7359 RK |
1253 | dma_cap_mask_t mask; |
1254 | unsigned sig; | |
9c4c2f8b | 1255 | struct resource *res; |
67ce04bf VS |
1256 | |
1257 | pdata = pdev->dev.platform_data; | |
1258 | if (pdata == NULL) { | |
1259 | dev_err(&pdev->dev, "platform data missing\n"); | |
1260 | return -ENODEV; | |
1261 | } | |
1262 | ||
1263 | info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL); | |
1264 | if (!info) | |
1265 | return -ENOMEM; | |
1266 | ||
1267 | platform_set_drvdata(pdev, info); | |
1268 | ||
1269 | spin_lock_init(&info->controller.lock); | |
1270 | init_waitqueue_head(&info->controller.wq); | |
1271 | ||
1272 | info->pdev = pdev; | |
1273 | ||
1274 | info->gpmc_cs = pdata->cs; | |
65b97cf6 | 1275 | info->reg = pdata->reg; |
67ce04bf VS |
1276 | |
1277 | info->mtd.priv = &info->nand; | |
1278 | info->mtd.name = dev_name(&pdev->dev); | |
1279 | info->mtd.owner = THIS_MODULE; | |
1280 | ||
d5ce2b65 | 1281 | info->nand.options = pdata->devsize; |
2f70a1e9 | 1282 | info->nand.options |= NAND_SKIP_BBTSCAN; |
67ce04bf | 1283 | |
9c4c2f8b AM |
1284 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1285 | if (res == NULL) { | |
1286 | err = -EINVAL; | |
1287 | dev_err(&pdev->dev, "error getting memory resource\n"); | |
1288 | goto out_free_info; | |
1289 | } | |
67ce04bf | 1290 | |
9c4c2f8b AM |
1291 | info->phys_base = res->start; |
1292 | info->mem_size = resource_size(res); | |
1293 | ||
1294 | if (!request_mem_region(info->phys_base, info->mem_size, | |
67ce04bf VS |
1295 | pdev->dev.driver->name)) { |
1296 | err = -EBUSY; | |
2f70a1e9 | 1297 | goto out_free_info; |
67ce04bf VS |
1298 | } |
1299 | ||
9c4c2f8b | 1300 | info->nand.IO_ADDR_R = ioremap(info->phys_base, info->mem_size); |
67ce04bf VS |
1301 | if (!info->nand.IO_ADDR_R) { |
1302 | err = -ENOMEM; | |
1303 | goto out_release_mem_region; | |
1304 | } | |
59e9c5ae | 1305 | |
67ce04bf VS |
1306 | info->nand.controller = &info->controller; |
1307 | ||
1308 | info->nand.IO_ADDR_W = info->nand.IO_ADDR_R; | |
1309 | info->nand.cmd_ctrl = omap_hwcontrol; | |
1310 | ||
67ce04bf VS |
1311 | /* |
1312 | * If RDY/BSY line is connected to OMAP then use the omap ready | |
4cacbe22 PM |
1313 | * function and the generic nand_wait function which reads the status |
1314 | * register after monitoring the RDY/BSY line. Otherwise use a standard | |
67ce04bf VS |
1315 | * chip delay which is slightly more than tR (AC Timing) of the NAND |
1316 | * device and read status register until you get a failure or success | |
1317 | */ | |
1318 | if (pdata->dev_ready) { | |
1319 | info->nand.dev_ready = omap_dev_ready; | |
1320 | info->nand.chip_delay = 0; | |
1321 | } else { | |
1322 | info->nand.waitfunc = omap_wait; | |
1323 | info->nand.chip_delay = 50; | |
1324 | } | |
1325 | ||
1b0b323c SG |
1326 | switch (pdata->xfer_type) { |
1327 | case NAND_OMAP_PREFETCH_POLLED: | |
59e9c5ae | 1328 | info->nand.read_buf = omap_read_buf_pref; |
1329 | info->nand.write_buf = omap_write_buf_pref; | |
1b0b323c SG |
1330 | break; |
1331 | ||
1332 | case NAND_OMAP_POLLED: | |
59e9c5ae | 1333 | if (info->nand.options & NAND_BUSWIDTH_16) { |
1334 | info->nand.read_buf = omap_read_buf16; | |
1335 | info->nand.write_buf = omap_write_buf16; | |
1336 | } else { | |
1337 | info->nand.read_buf = omap_read_buf8; | |
1338 | info->nand.write_buf = omap_write_buf8; | |
1339 | } | |
1b0b323c SG |
1340 | break; |
1341 | ||
1342 | case NAND_OMAP_PREFETCH_DMA: | |
763e7359 RK |
1343 | dma_cap_zero(mask); |
1344 | dma_cap_set(DMA_SLAVE, mask); | |
1345 | sig = OMAP24XX_DMA_GPMC; | |
1346 | info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig); | |
1347 | if (!info->dma) { | |
2df41d05 RK |
1348 | dev_err(&pdev->dev, "DMA engine request failed\n"); |
1349 | err = -ENXIO; | |
1350 | goto out_release_mem_region; | |
763e7359 RK |
1351 | } else { |
1352 | struct dma_slave_config cfg; | |
763e7359 RK |
1353 | |
1354 | memset(&cfg, 0, sizeof(cfg)); | |
1355 | cfg.src_addr = info->phys_base; | |
1356 | cfg.dst_addr = info->phys_base; | |
1357 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1358 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1359 | cfg.src_maxburst = 16; | |
1360 | cfg.dst_maxburst = 16; | |
d680e2c1 AB |
1361 | err = dmaengine_slave_config(info->dma, &cfg); |
1362 | if (err) { | |
763e7359 | 1363 | dev_err(&pdev->dev, "DMA engine slave config failed: %d\n", |
d680e2c1 | 1364 | err); |
763e7359 RK |
1365 | goto out_release_mem_region; |
1366 | } | |
1367 | info->nand.read_buf = omap_read_buf_dma_pref; | |
1368 | info->nand.write_buf = omap_write_buf_dma_pref; | |
1b0b323c SG |
1369 | } |
1370 | break; | |
1371 | ||
4e070376 | 1372 | case NAND_OMAP_PREFETCH_IRQ: |
5c468455 AM |
1373 | info->gpmc_irq_fifo = platform_get_irq(pdev, 0); |
1374 | if (info->gpmc_irq_fifo <= 0) { | |
1375 | dev_err(&pdev->dev, "error getting fifo irq\n"); | |
1376 | err = -ENODEV; | |
1377 | goto out_release_mem_region; | |
1378 | } | |
1379 | err = request_irq(info->gpmc_irq_fifo, omap_nand_irq, | |
1380 | IRQF_SHARED, "gpmc-nand-fifo", info); | |
4e070376 SG |
1381 | if (err) { |
1382 | dev_err(&pdev->dev, "requesting irq(%d) error:%d", | |
5c468455 AM |
1383 | info->gpmc_irq_fifo, err); |
1384 | info->gpmc_irq_fifo = 0; | |
1385 | goto out_release_mem_region; | |
1386 | } | |
1387 | ||
1388 | info->gpmc_irq_count = platform_get_irq(pdev, 1); | |
1389 | if (info->gpmc_irq_count <= 0) { | |
1390 | dev_err(&pdev->dev, "error getting count irq\n"); | |
1391 | err = -ENODEV; | |
1392 | goto out_release_mem_region; | |
1393 | } | |
1394 | err = request_irq(info->gpmc_irq_count, omap_nand_irq, | |
1395 | IRQF_SHARED, "gpmc-nand-count", info); | |
1396 | if (err) { | |
1397 | dev_err(&pdev->dev, "requesting irq(%d) error:%d", | |
1398 | info->gpmc_irq_count, err); | |
1399 | info->gpmc_irq_count = 0; | |
4e070376 | 1400 | goto out_release_mem_region; |
4e070376 | 1401 | } |
5c468455 AM |
1402 | |
1403 | info->nand.read_buf = omap_read_buf_irq_pref; | |
1404 | info->nand.write_buf = omap_write_buf_irq_pref; | |
1405 | ||
4e070376 SG |
1406 | break; |
1407 | ||
1b0b323c SG |
1408 | default: |
1409 | dev_err(&pdev->dev, | |
1410 | "xfer_type(%d) not supported!\n", pdata->xfer_type); | |
1411 | err = -EINVAL; | |
1412 | goto out_release_mem_region; | |
59e9c5ae | 1413 | } |
59e9c5ae | 1414 | |
4cacbe22 | 1415 | /* select the ecc type */ |
f3d73f36 SG |
1416 | if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT) |
1417 | info->nand.ecc.mode = NAND_ECC_SOFT; | |
f040d332 SG |
1418 | else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) || |
1419 | (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) { | |
f3d73f36 SG |
1420 | info->nand.ecc.bytes = 3; |
1421 | info->nand.ecc.size = 512; | |
6a918bad | 1422 | info->nand.ecc.strength = 1; |
f3d73f36 SG |
1423 | info->nand.ecc.calculate = omap_calculate_ecc; |
1424 | info->nand.ecc.hwctl = omap_enable_hwecc; | |
1425 | info->nand.ecc.correct = omap_correct_data; | |
1426 | info->nand.ecc.mode = NAND_ECC_HW; | |
0e618ef0 ID |
1427 | } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) || |
1428 | (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) { | |
1429 | err = omap3_init_bch(&info->mtd, pdata->ecc_opt); | |
1430 | if (err) { | |
1431 | err = -EINVAL; | |
1432 | goto out_release_mem_region; | |
1433 | } | |
f3d73f36 | 1434 | } |
67ce04bf VS |
1435 | |
1436 | /* DIP switches on some boards change between 8 and 16 bit | |
1437 | * bus widths for flash. Try the other width if the first try fails. | |
1438 | */ | |
a80f1c1f | 1439 | if (nand_scan_ident(&info->mtd, 1, NULL)) { |
67ce04bf | 1440 | info->nand.options ^= NAND_BUSWIDTH_16; |
a80f1c1f | 1441 | if (nand_scan_ident(&info->mtd, 1, NULL)) { |
67ce04bf VS |
1442 | err = -ENXIO; |
1443 | goto out_release_mem_region; | |
1444 | } | |
1445 | } | |
1446 | ||
f040d332 SG |
1447 | /* rom code layout */ |
1448 | if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) { | |
1449 | ||
1450 | if (info->nand.options & NAND_BUSWIDTH_16) | |
1451 | offset = 2; | |
1452 | else { | |
1453 | offset = 1; | |
1454 | info->nand.badblock_pattern = &bb_descrip_flashbased; | |
1455 | } | |
1456 | omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16); | |
1457 | for (i = 0; i < omap_oobinfo.eccbytes; i++) | |
1458 | omap_oobinfo.eccpos[i] = i+offset; | |
1459 | ||
1460 | omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes; | |
1461 | omap_oobinfo.oobfree->length = info->mtd.oobsize - | |
1462 | (offset + omap_oobinfo.eccbytes); | |
1463 | ||
1464 | info->nand.ecc.layout = &omap_oobinfo; | |
0e618ef0 ID |
1465 | } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) || |
1466 | (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) { | |
1467 | /* build OOB layout for BCH ECC correction */ | |
1468 | err = omap3_init_bch_tail(&info->mtd); | |
1469 | if (err) { | |
1470 | err = -EINVAL; | |
1471 | goto out_release_mem_region; | |
1472 | } | |
f040d332 | 1473 | } |
1b0b323c | 1474 | |
a80f1c1f JW |
1475 | /* second phase scan */ |
1476 | if (nand_scan_tail(&info->mtd)) { | |
1477 | err = -ENXIO; | |
1478 | goto out_release_mem_region; | |
1479 | } | |
1480 | ||
42d7fbe2 AB |
1481 | mtd_device_parse_register(&info->mtd, NULL, NULL, pdata->parts, |
1482 | pdata->nr_parts); | |
67ce04bf VS |
1483 | |
1484 | platform_set_drvdata(pdev, &info->mtd); | |
1485 | ||
1486 | return 0; | |
1487 | ||
1488 | out_release_mem_region: | |
763e7359 RK |
1489 | if (info->dma) |
1490 | dma_release_channel(info->dma); | |
5c468455 AM |
1491 | if (info->gpmc_irq_count > 0) |
1492 | free_irq(info->gpmc_irq_count, info); | |
1493 | if (info->gpmc_irq_fifo > 0) | |
1494 | free_irq(info->gpmc_irq_fifo, info); | |
9c4c2f8b | 1495 | release_mem_region(info->phys_base, info->mem_size); |
67ce04bf VS |
1496 | out_free_info: |
1497 | kfree(info); | |
1498 | ||
1499 | return err; | |
1500 | } | |
1501 | ||
1502 | static int omap_nand_remove(struct platform_device *pdev) | |
1503 | { | |
1504 | struct mtd_info *mtd = platform_get_drvdata(pdev); | |
f35b6eda VS |
1505 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
1506 | mtd); | |
0e618ef0 | 1507 | omap3_free_bch(&info->mtd); |
67ce04bf VS |
1508 | |
1509 | platform_set_drvdata(pdev, NULL); | |
763e7359 RK |
1510 | if (info->dma) |
1511 | dma_release_channel(info->dma); | |
1512 | ||
5c468455 AM |
1513 | if (info->gpmc_irq_count > 0) |
1514 | free_irq(info->gpmc_irq_count, info); | |
1515 | if (info->gpmc_irq_fifo > 0) | |
1516 | free_irq(info->gpmc_irq_fifo, info); | |
4e070376 | 1517 | |
67ce04bf VS |
1518 | /* Release NAND device, its internal structures and partitions */ |
1519 | nand_release(&info->mtd); | |
2c01946c | 1520 | iounmap(info->nand.IO_ADDR_R); |
48b51d4d | 1521 | release_mem_region(info->phys_base, info->mem_size); |
7d9b1102 | 1522 | kfree(info); |
67ce04bf VS |
1523 | return 0; |
1524 | } | |
1525 | ||
1526 | static struct platform_driver omap_nand_driver = { | |
1527 | .probe = omap_nand_probe, | |
1528 | .remove = omap_nand_remove, | |
1529 | .driver = { | |
1530 | .name = DRIVER_NAME, | |
1531 | .owner = THIS_MODULE, | |
1532 | }, | |
1533 | }; | |
1534 | ||
f99640de | 1535 | module_platform_driver(omap_nand_driver); |
67ce04bf | 1536 | |
c804c733 | 1537 | MODULE_ALIAS("platform:" DRIVER_NAME); |
67ce04bf VS |
1538 | MODULE_LICENSE("GPL"); |
1539 | MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards"); |