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67ce04bf VS |
1 | /* |
2 | * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com> | |
3 | * Copyright © 2004 Micron Technology Inc. | |
4 | * Copyright © 2004 David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/platform_device.h> | |
763e7359 | 12 | #include <linux/dmaengine.h> |
67ce04bf VS |
13 | #include <linux/dma-mapping.h> |
14 | #include <linux/delay.h> | |
a0e5cc58 | 15 | #include <linux/module.h> |
4e070376 | 16 | #include <linux/interrupt.h> |
c276aca4 | 17 | #include <linux/jiffies.h> |
18 | #include <linux/sched.h> | |
67ce04bf VS |
19 | #include <linux/mtd/mtd.h> |
20 | #include <linux/mtd/nand.h> | |
21 | #include <linux/mtd/partitions.h> | |
763e7359 | 22 | #include <linux/omap-dma.h> |
67ce04bf | 23 | #include <linux/io.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
62116e51 PA |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
67ce04bf | 27 | |
32d42a85 | 28 | #include <linux/mtd/nand_bch.h> |
62116e51 | 29 | #include <linux/platform_data/elm.h> |
0e618ef0 | 30 | |
2203747c | 31 | #include <linux/platform_data/mtd-nand-omap2.h> |
67ce04bf | 32 | |
67ce04bf | 33 | #define DRIVER_NAME "omap2-nand" |
4e070376 | 34 | #define OMAP_NAND_TIMEOUT_MS 5000 |
67ce04bf | 35 | |
67ce04bf VS |
36 | #define NAND_Ecc_P1e (1 << 0) |
37 | #define NAND_Ecc_P2e (1 << 1) | |
38 | #define NAND_Ecc_P4e (1 << 2) | |
39 | #define NAND_Ecc_P8e (1 << 3) | |
40 | #define NAND_Ecc_P16e (1 << 4) | |
41 | #define NAND_Ecc_P32e (1 << 5) | |
42 | #define NAND_Ecc_P64e (1 << 6) | |
43 | #define NAND_Ecc_P128e (1 << 7) | |
44 | #define NAND_Ecc_P256e (1 << 8) | |
45 | #define NAND_Ecc_P512e (1 << 9) | |
46 | #define NAND_Ecc_P1024e (1 << 10) | |
47 | #define NAND_Ecc_P2048e (1 << 11) | |
48 | ||
49 | #define NAND_Ecc_P1o (1 << 16) | |
50 | #define NAND_Ecc_P2o (1 << 17) | |
51 | #define NAND_Ecc_P4o (1 << 18) | |
52 | #define NAND_Ecc_P8o (1 << 19) | |
53 | #define NAND_Ecc_P16o (1 << 20) | |
54 | #define NAND_Ecc_P32o (1 << 21) | |
55 | #define NAND_Ecc_P64o (1 << 22) | |
56 | #define NAND_Ecc_P128o (1 << 23) | |
57 | #define NAND_Ecc_P256o (1 << 24) | |
58 | #define NAND_Ecc_P512o (1 << 25) | |
59 | #define NAND_Ecc_P1024o (1 << 26) | |
60 | #define NAND_Ecc_P2048o (1 << 27) | |
61 | ||
62 | #define TF(value) (value ? 1 : 0) | |
63 | ||
64 | #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0) | |
65 | #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1) | |
66 | #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2) | |
67 | #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3) | |
68 | #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4) | |
69 | #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5) | |
70 | #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6) | |
71 | #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7) | |
72 | ||
73 | #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0) | |
74 | #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1) | |
75 | #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2) | |
76 | #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3) | |
77 | #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4) | |
78 | #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5) | |
79 | #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6) | |
80 | #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7) | |
81 | ||
82 | #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0) | |
83 | #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1) | |
84 | #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2) | |
85 | #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3) | |
86 | #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4) | |
87 | #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5) | |
88 | #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6) | |
89 | #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7) | |
90 | ||
91 | #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0) | |
92 | #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1) | |
93 | #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2) | |
94 | #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3) | |
95 | #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4) | |
96 | #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5) | |
97 | #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6) | |
98 | #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7) | |
99 | ||
100 | #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) | |
101 | #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) | |
102 | ||
65b97cf6 AM |
103 | #define PREFETCH_CONFIG1_CS_SHIFT 24 |
104 | #define ECC_CONFIG_CS_SHIFT 1 | |
105 | #define CS_MASK 0x7 | |
106 | #define ENABLE_PREFETCH (0x1 << 7) | |
107 | #define DMA_MPU_MODE_SHIFT 2 | |
2ef9f3dd | 108 | #define ECCSIZE0_SHIFT 12 |
65b97cf6 AM |
109 | #define ECCSIZE1_SHIFT 22 |
110 | #define ECC1RESULTSIZE 0x1 | |
111 | #define ECCCLEAR 0x100 | |
112 | #define ECC1 0x1 | |
47f88af4 AM |
113 | #define PREFETCH_FIFOTHRESHOLD_MAX 0x40 |
114 | #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) | |
115 | #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) | |
116 | #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) | |
117 | #define STATUS_BUFF_EMPTY 0x00000001 | |
65b97cf6 | 118 | |
d5e7c864 LV |
119 | #define OMAP24XX_DMA_GPMC 4 |
120 | ||
62116e51 PA |
121 | #define SECTOR_BYTES 512 |
122 | /* 4 bit padding to make byte aligned, 56 = 52 + 4 */ | |
123 | #define BCH4_BIT_PAD 4 | |
62116e51 PA |
124 | |
125 | /* GPMC ecc engine settings for read */ | |
126 | #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */ | |
127 | #define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */ | |
128 | #define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */ | |
129 | #define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */ | |
130 | #define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */ | |
131 | ||
132 | /* GPMC ecc engine settings for write */ | |
133 | #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */ | |
134 | #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */ | |
135 | #define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */ | |
136 | ||
b491da72 | 137 | #define BADBLOCK_MARKER_LENGTH 2 |
a919e511 | 138 | |
62116e51 PA |
139 | #ifdef CONFIG_MTD_NAND_OMAP_BCH |
140 | static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc, | |
141 | 0xac, 0x6b, 0xff, 0x99, 0x7b}; | |
142 | static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10}; | |
143 | #endif | |
144 | ||
f040d332 SG |
145 | /* oob info generated runtime depending on ecc algorithm and layout selected */ |
146 | static struct nand_ecclayout omap_oobinfo; | |
59e9c5ae | 147 | |
67ce04bf VS |
148 | struct omap_nand_info { |
149 | struct nand_hw_control controller; | |
150 | struct omap_nand_platform_data *pdata; | |
151 | struct mtd_info mtd; | |
67ce04bf VS |
152 | struct nand_chip nand; |
153 | struct platform_device *pdev; | |
154 | ||
155 | int gpmc_cs; | |
156 | unsigned long phys_base; | |
9c4c2f8b | 157 | unsigned long mem_size; |
4e558072 | 158 | enum omap_ecc ecc_opt; |
dfe32893 | 159 | struct completion comp; |
763e7359 | 160 | struct dma_chan *dma; |
5c468455 AM |
161 | int gpmc_irq_fifo; |
162 | int gpmc_irq_count; | |
4e070376 SG |
163 | enum { |
164 | OMAP_NAND_IO_READ = 0, /* read */ | |
165 | OMAP_NAND_IO_WRITE, /* write */ | |
166 | } iomode; | |
167 | u_char *buf; | |
168 | int buf_len; | |
65b97cf6 | 169 | struct gpmc_nand_regs reg; |
a919e511 | 170 | /* fields specific for BCHx_HW ECC scheme */ |
62116e51 PA |
171 | struct device *elm_dev; |
172 | struct device_node *of_node; | |
67ce04bf VS |
173 | }; |
174 | ||
65b97cf6 AM |
175 | /** |
176 | * omap_prefetch_enable - configures and starts prefetch transfer | |
177 | * @cs: cs (chip select) number | |
178 | * @fifo_th: fifo threshold to be used for read/ write | |
179 | * @dma_mode: dma mode enable (1) or disable (0) | |
180 | * @u32_count: number of bytes to be transferred | |
181 | * @is_write: prefetch read(0) or write post(1) mode | |
182 | */ | |
183 | static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode, | |
184 | unsigned int u32_count, int is_write, struct omap_nand_info *info) | |
185 | { | |
186 | u32 val; | |
187 | ||
188 | if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) | |
189 | return -1; | |
190 | ||
191 | if (readl(info->reg.gpmc_prefetch_control)) | |
192 | return -EBUSY; | |
193 | ||
194 | /* Set the amount of bytes to be prefetched */ | |
195 | writel(u32_count, info->reg.gpmc_prefetch_config2); | |
196 | ||
197 | /* Set dma/mpu mode, the prefetch read / post write and | |
198 | * enable the engine. Set which cs is has requested for. | |
199 | */ | |
200 | val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) | | |
201 | PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH | | |
202 | (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write)); | |
203 | writel(val, info->reg.gpmc_prefetch_config1); | |
204 | ||
205 | /* Start the prefetch engine */ | |
206 | writel(0x1, info->reg.gpmc_prefetch_control); | |
207 | ||
208 | return 0; | |
209 | } | |
210 | ||
211 | /** | |
212 | * omap_prefetch_reset - disables and stops the prefetch engine | |
213 | */ | |
214 | static int omap_prefetch_reset(int cs, struct omap_nand_info *info) | |
215 | { | |
216 | u32 config1; | |
217 | ||
218 | /* check if the same module/cs is trying to reset */ | |
219 | config1 = readl(info->reg.gpmc_prefetch_config1); | |
220 | if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs) | |
221 | return -EINVAL; | |
222 | ||
223 | /* Stop the PFPW engine */ | |
224 | writel(0x0, info->reg.gpmc_prefetch_control); | |
225 | ||
226 | /* Reset/disable the PFPW engine */ | |
227 | writel(0x0, info->reg.gpmc_prefetch_config1); | |
228 | ||
229 | return 0; | |
230 | } | |
231 | ||
67ce04bf VS |
232 | /** |
233 | * omap_hwcontrol - hardware specific access to control-lines | |
234 | * @mtd: MTD device structure | |
235 | * @cmd: command to device | |
236 | * @ctrl: | |
237 | * NAND_NCE: bit 0 -> don't care | |
238 | * NAND_CLE: bit 1 -> Command Latch | |
239 | * NAND_ALE: bit 2 -> Address Latch | |
240 | * | |
241 | * NOTE: boards may use different bits for these!! | |
242 | */ | |
243 | static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
244 | { | |
245 | struct omap_nand_info *info = container_of(mtd, | |
246 | struct omap_nand_info, mtd); | |
67ce04bf | 247 | |
2c01946c SG |
248 | if (cmd != NAND_CMD_NONE) { |
249 | if (ctrl & NAND_CLE) | |
65b97cf6 | 250 | writeb(cmd, info->reg.gpmc_nand_command); |
2c01946c SG |
251 | |
252 | else if (ctrl & NAND_ALE) | |
65b97cf6 | 253 | writeb(cmd, info->reg.gpmc_nand_address); |
2c01946c SG |
254 | |
255 | else /* NAND_NCE */ | |
65b97cf6 | 256 | writeb(cmd, info->reg.gpmc_nand_data); |
2c01946c | 257 | } |
67ce04bf VS |
258 | } |
259 | ||
59e9c5ae | 260 | /** |
261 | * omap_read_buf8 - read data from NAND controller into buffer | |
262 | * @mtd: MTD device structure | |
263 | * @buf: buffer to store date | |
264 | * @len: number of bytes to read | |
265 | */ | |
266 | static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len) | |
267 | { | |
268 | struct nand_chip *nand = mtd->priv; | |
269 | ||
270 | ioread8_rep(nand->IO_ADDR_R, buf, len); | |
271 | } | |
272 | ||
273 | /** | |
274 | * omap_write_buf8 - write buffer to NAND controller | |
275 | * @mtd: MTD device structure | |
276 | * @buf: data buffer | |
277 | * @len: number of bytes to write | |
278 | */ | |
279 | static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len) | |
280 | { | |
281 | struct omap_nand_info *info = container_of(mtd, | |
282 | struct omap_nand_info, mtd); | |
283 | u_char *p = (u_char *)buf; | |
2c01946c | 284 | u32 status = 0; |
59e9c5ae | 285 | |
286 | while (len--) { | |
287 | iowrite8(*p++, info->nand.IO_ADDR_W); | |
2c01946c SG |
288 | /* wait until buffer is available for write */ |
289 | do { | |
65b97cf6 | 290 | status = readl(info->reg.gpmc_status) & |
47f88af4 | 291 | STATUS_BUFF_EMPTY; |
2c01946c | 292 | } while (!status); |
59e9c5ae | 293 | } |
294 | } | |
295 | ||
67ce04bf VS |
296 | /** |
297 | * omap_read_buf16 - read data from NAND controller into buffer | |
298 | * @mtd: MTD device structure | |
299 | * @buf: buffer to store date | |
300 | * @len: number of bytes to read | |
301 | */ | |
302 | static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len) | |
303 | { | |
304 | struct nand_chip *nand = mtd->priv; | |
305 | ||
59e9c5ae | 306 | ioread16_rep(nand->IO_ADDR_R, buf, len / 2); |
67ce04bf VS |
307 | } |
308 | ||
309 | /** | |
310 | * omap_write_buf16 - write buffer to NAND controller | |
311 | * @mtd: MTD device structure | |
312 | * @buf: data buffer | |
313 | * @len: number of bytes to write | |
314 | */ | |
315 | static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len) | |
316 | { | |
317 | struct omap_nand_info *info = container_of(mtd, | |
318 | struct omap_nand_info, mtd); | |
319 | u16 *p = (u16 *) buf; | |
2c01946c | 320 | u32 status = 0; |
67ce04bf VS |
321 | /* FIXME try bursts of writesw() or DMA ... */ |
322 | len >>= 1; | |
323 | ||
324 | while (len--) { | |
59e9c5ae | 325 | iowrite16(*p++, info->nand.IO_ADDR_W); |
2c01946c SG |
326 | /* wait until buffer is available for write */ |
327 | do { | |
65b97cf6 | 328 | status = readl(info->reg.gpmc_status) & |
47f88af4 | 329 | STATUS_BUFF_EMPTY; |
2c01946c | 330 | } while (!status); |
67ce04bf VS |
331 | } |
332 | } | |
59e9c5ae | 333 | |
334 | /** | |
335 | * omap_read_buf_pref - read data from NAND controller into buffer | |
336 | * @mtd: MTD device structure | |
337 | * @buf: buffer to store date | |
338 | * @len: number of bytes to read | |
339 | */ | |
340 | static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) | |
341 | { | |
342 | struct omap_nand_info *info = container_of(mtd, | |
343 | struct omap_nand_info, mtd); | |
2c01946c | 344 | uint32_t r_count = 0; |
59e9c5ae | 345 | int ret = 0; |
346 | u32 *p = (u32 *)buf; | |
347 | ||
348 | /* take care of subpage reads */ | |
c3341d0c VS |
349 | if (len % 4) { |
350 | if (info->nand.options & NAND_BUSWIDTH_16) | |
351 | omap_read_buf16(mtd, buf, len % 4); | |
352 | else | |
353 | omap_read_buf8(mtd, buf, len % 4); | |
354 | p = (u32 *) (buf + len % 4); | |
355 | len -= len % 4; | |
59e9c5ae | 356 | } |
59e9c5ae | 357 | |
358 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
359 | ret = omap_prefetch_enable(info->gpmc_cs, |
360 | PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info); | |
59e9c5ae | 361 | if (ret) { |
362 | /* PFPW engine is busy, use cpu copy method */ | |
363 | if (info->nand.options & NAND_BUSWIDTH_16) | |
c5d8c0ca | 364 | omap_read_buf16(mtd, (u_char *)p, len); |
59e9c5ae | 365 | else |
c5d8c0ca | 366 | omap_read_buf8(mtd, (u_char *)p, len); |
59e9c5ae | 367 | } else { |
368 | do { | |
65b97cf6 | 369 | r_count = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 370 | r_count = PREFETCH_STATUS_FIFO_CNT(r_count); |
2c01946c SG |
371 | r_count = r_count >> 2; |
372 | ioread32_rep(info->nand.IO_ADDR_R, p, r_count); | |
59e9c5ae | 373 | p += r_count; |
374 | len -= r_count << 2; | |
375 | } while (len); | |
59e9c5ae | 376 | /* disable and stop the PFPW engine */ |
65b97cf6 | 377 | omap_prefetch_reset(info->gpmc_cs, info); |
59e9c5ae | 378 | } |
379 | } | |
380 | ||
381 | /** | |
382 | * omap_write_buf_pref - write buffer to NAND controller | |
383 | * @mtd: MTD device structure | |
384 | * @buf: data buffer | |
385 | * @len: number of bytes to write | |
386 | */ | |
387 | static void omap_write_buf_pref(struct mtd_info *mtd, | |
388 | const u_char *buf, int len) | |
389 | { | |
390 | struct omap_nand_info *info = container_of(mtd, | |
391 | struct omap_nand_info, mtd); | |
4e070376 | 392 | uint32_t w_count = 0; |
59e9c5ae | 393 | int i = 0, ret = 0; |
c5d8c0ca | 394 | u16 *p = (u16 *)buf; |
4e070376 | 395 | unsigned long tim, limit; |
65b97cf6 | 396 | u32 val; |
59e9c5ae | 397 | |
398 | /* take care of subpage writes */ | |
399 | if (len % 2 != 0) { | |
2c01946c | 400 | writeb(*buf, info->nand.IO_ADDR_W); |
59e9c5ae | 401 | p = (u16 *)(buf + 1); |
402 | len--; | |
403 | } | |
404 | ||
405 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
406 | ret = omap_prefetch_enable(info->gpmc_cs, |
407 | PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info); | |
59e9c5ae | 408 | if (ret) { |
409 | /* PFPW engine is busy, use cpu copy method */ | |
410 | if (info->nand.options & NAND_BUSWIDTH_16) | |
c5d8c0ca | 411 | omap_write_buf16(mtd, (u_char *)p, len); |
59e9c5ae | 412 | else |
c5d8c0ca | 413 | omap_write_buf8(mtd, (u_char *)p, len); |
59e9c5ae | 414 | } else { |
2c01946c | 415 | while (len) { |
65b97cf6 | 416 | w_count = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 417 | w_count = PREFETCH_STATUS_FIFO_CNT(w_count); |
2c01946c | 418 | w_count = w_count >> 1; |
59e9c5ae | 419 | for (i = 0; (i < w_count) && len; i++, len -= 2) |
2c01946c | 420 | iowrite16(*p++, info->nand.IO_ADDR_W); |
59e9c5ae | 421 | } |
2c01946c | 422 | /* wait for data to flushed-out before reset the prefetch */ |
4e070376 SG |
423 | tim = 0; |
424 | limit = (loops_per_jiffy * | |
425 | msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 | 426 | do { |
4e070376 | 427 | cpu_relax(); |
65b97cf6 | 428 | val = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 429 | val = PREFETCH_STATUS_COUNT(val); |
65b97cf6 | 430 | } while (val && (tim++ < limit)); |
4e070376 | 431 | |
59e9c5ae | 432 | /* disable and stop the PFPW engine */ |
65b97cf6 | 433 | omap_prefetch_reset(info->gpmc_cs, info); |
59e9c5ae | 434 | } |
435 | } | |
436 | ||
dfe32893 | 437 | /* |
2df41d05 | 438 | * omap_nand_dma_callback: callback on the completion of dma transfer |
dfe32893 | 439 | * @data: pointer to completion data structure |
440 | */ | |
763e7359 RK |
441 | static void omap_nand_dma_callback(void *data) |
442 | { | |
443 | complete((struct completion *) data); | |
444 | } | |
dfe32893 | 445 | |
446 | /* | |
4cacbe22 | 447 | * omap_nand_dma_transfer: configure and start dma transfer |
dfe32893 | 448 | * @mtd: MTD device structure |
449 | * @addr: virtual address in RAM of source/destination | |
450 | * @len: number of data bytes to be transferred | |
451 | * @is_write: flag for read/write operation | |
452 | */ | |
453 | static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, | |
454 | unsigned int len, int is_write) | |
455 | { | |
456 | struct omap_nand_info *info = container_of(mtd, | |
457 | struct omap_nand_info, mtd); | |
2df41d05 | 458 | struct dma_async_tx_descriptor *tx; |
dfe32893 | 459 | enum dma_data_direction dir = is_write ? DMA_TO_DEVICE : |
460 | DMA_FROM_DEVICE; | |
2df41d05 | 461 | struct scatterlist sg; |
4e070376 | 462 | unsigned long tim, limit; |
2df41d05 RK |
463 | unsigned n; |
464 | int ret; | |
65b97cf6 | 465 | u32 val; |
dfe32893 | 466 | |
467 | if (addr >= high_memory) { | |
468 | struct page *p1; | |
469 | ||
470 | if (((size_t)addr & PAGE_MASK) != | |
471 | ((size_t)(addr + len - 1) & PAGE_MASK)) | |
472 | goto out_copy; | |
473 | p1 = vmalloc_to_page(addr); | |
474 | if (!p1) | |
475 | goto out_copy; | |
476 | addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK); | |
477 | } | |
478 | ||
2df41d05 RK |
479 | sg_init_one(&sg, addr, len); |
480 | n = dma_map_sg(info->dma->device->dev, &sg, 1, dir); | |
481 | if (n == 0) { | |
dfe32893 | 482 | dev_err(&info->pdev->dev, |
483 | "Couldn't DMA map a %d byte buffer\n", len); | |
484 | goto out_copy; | |
485 | } | |
486 | ||
2df41d05 RK |
487 | tx = dmaengine_prep_slave_sg(info->dma, &sg, n, |
488 | is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, | |
489 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
490 | if (!tx) | |
491 | goto out_copy_unmap; | |
492 | ||
493 | tx->callback = omap_nand_dma_callback; | |
494 | tx->callback_param = &info->comp; | |
495 | dmaengine_submit(tx); | |
496 | ||
65b97cf6 AM |
497 | /* configure and start prefetch transfer */ |
498 | ret = omap_prefetch_enable(info->gpmc_cs, | |
499 | PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info); | |
dfe32893 | 500 | if (ret) |
4e070376 | 501 | /* PFPW engine is busy, use cpu copy method */ |
d7efe228 | 502 | goto out_copy_unmap; |
dfe32893 | 503 | |
504 | init_completion(&info->comp); | |
2df41d05 | 505 | dma_async_issue_pending(info->dma); |
dfe32893 | 506 | |
507 | /* setup and start DMA using dma_addr */ | |
508 | wait_for_completion(&info->comp); | |
4e070376 SG |
509 | tim = 0; |
510 | limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 AM |
511 | |
512 | do { | |
4e070376 | 513 | cpu_relax(); |
65b97cf6 | 514 | val = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 515 | val = PREFETCH_STATUS_COUNT(val); |
65b97cf6 | 516 | } while (val && (tim++ < limit)); |
dfe32893 | 517 | |
dfe32893 | 518 | /* disable and stop the PFPW engine */ |
65b97cf6 | 519 | omap_prefetch_reset(info->gpmc_cs, info); |
dfe32893 | 520 | |
2df41d05 | 521 | dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); |
dfe32893 | 522 | return 0; |
523 | ||
d7efe228 | 524 | out_copy_unmap: |
2df41d05 | 525 | dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); |
dfe32893 | 526 | out_copy: |
527 | if (info->nand.options & NAND_BUSWIDTH_16) | |
528 | is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len) | |
529 | : omap_write_buf16(mtd, (u_char *) addr, len); | |
530 | else | |
531 | is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len) | |
532 | : omap_write_buf8(mtd, (u_char *) addr, len); | |
533 | return 0; | |
534 | } | |
dfe32893 | 535 | |
536 | /** | |
537 | * omap_read_buf_dma_pref - read data from NAND controller into buffer | |
538 | * @mtd: MTD device structure | |
539 | * @buf: buffer to store date | |
540 | * @len: number of bytes to read | |
541 | */ | |
542 | static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len) | |
543 | { | |
544 | if (len <= mtd->oobsize) | |
545 | omap_read_buf_pref(mtd, buf, len); | |
546 | else | |
547 | /* start transfer in DMA mode */ | |
548 | omap_nand_dma_transfer(mtd, buf, len, 0x0); | |
549 | } | |
550 | ||
551 | /** | |
552 | * omap_write_buf_dma_pref - write buffer to NAND controller | |
553 | * @mtd: MTD device structure | |
554 | * @buf: data buffer | |
555 | * @len: number of bytes to write | |
556 | */ | |
557 | static void omap_write_buf_dma_pref(struct mtd_info *mtd, | |
558 | const u_char *buf, int len) | |
559 | { | |
560 | if (len <= mtd->oobsize) | |
561 | omap_write_buf_pref(mtd, buf, len); | |
562 | else | |
563 | /* start transfer in DMA mode */ | |
bdaefc41 | 564 | omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1); |
dfe32893 | 565 | } |
566 | ||
4e070376 | 567 | /* |
4cacbe22 | 568 | * omap_nand_irq - GPMC irq handler |
4e070376 SG |
569 | * @this_irq: gpmc irq number |
570 | * @dev: omap_nand_info structure pointer is passed here | |
571 | */ | |
572 | static irqreturn_t omap_nand_irq(int this_irq, void *dev) | |
573 | { | |
574 | struct omap_nand_info *info = (struct omap_nand_info *) dev; | |
575 | u32 bytes; | |
4e070376 | 576 | |
65b97cf6 | 577 | bytes = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 578 | bytes = PREFETCH_STATUS_FIFO_CNT(bytes); |
4e070376 SG |
579 | bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ |
580 | if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ | |
5c468455 | 581 | if (this_irq == info->gpmc_irq_count) |
4e070376 SG |
582 | goto done; |
583 | ||
584 | if (info->buf_len && (info->buf_len < bytes)) | |
585 | bytes = info->buf_len; | |
586 | else if (!info->buf_len) | |
587 | bytes = 0; | |
588 | iowrite32_rep(info->nand.IO_ADDR_W, | |
589 | (u32 *)info->buf, bytes >> 2); | |
590 | info->buf = info->buf + bytes; | |
591 | info->buf_len -= bytes; | |
592 | ||
593 | } else { | |
594 | ioread32_rep(info->nand.IO_ADDR_R, | |
595 | (u32 *)info->buf, bytes >> 2); | |
596 | info->buf = info->buf + bytes; | |
597 | ||
5c468455 | 598 | if (this_irq == info->gpmc_irq_count) |
4e070376 SG |
599 | goto done; |
600 | } | |
4e070376 SG |
601 | |
602 | return IRQ_HANDLED; | |
603 | ||
604 | done: | |
605 | complete(&info->comp); | |
4e070376 | 606 | |
5c468455 AM |
607 | disable_irq_nosync(info->gpmc_irq_fifo); |
608 | disable_irq_nosync(info->gpmc_irq_count); | |
4e070376 SG |
609 | |
610 | return IRQ_HANDLED; | |
611 | } | |
612 | ||
613 | /* | |
614 | * omap_read_buf_irq_pref - read data from NAND controller into buffer | |
615 | * @mtd: MTD device structure | |
616 | * @buf: buffer to store date | |
617 | * @len: number of bytes to read | |
618 | */ | |
619 | static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) | |
620 | { | |
621 | struct omap_nand_info *info = container_of(mtd, | |
622 | struct omap_nand_info, mtd); | |
623 | int ret = 0; | |
624 | ||
625 | if (len <= mtd->oobsize) { | |
626 | omap_read_buf_pref(mtd, buf, len); | |
627 | return; | |
628 | } | |
629 | ||
630 | info->iomode = OMAP_NAND_IO_READ; | |
631 | info->buf = buf; | |
632 | init_completion(&info->comp); | |
633 | ||
634 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
635 | ret = omap_prefetch_enable(info->gpmc_cs, |
636 | PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info); | |
4e070376 SG |
637 | if (ret) |
638 | /* PFPW engine is busy, use cpu copy method */ | |
639 | goto out_copy; | |
640 | ||
641 | info->buf_len = len; | |
5c468455 AM |
642 | |
643 | enable_irq(info->gpmc_irq_count); | |
644 | enable_irq(info->gpmc_irq_fifo); | |
4e070376 SG |
645 | |
646 | /* waiting for read to complete */ | |
647 | wait_for_completion(&info->comp); | |
648 | ||
649 | /* disable and stop the PFPW engine */ | |
65b97cf6 | 650 | omap_prefetch_reset(info->gpmc_cs, info); |
4e070376 SG |
651 | return; |
652 | ||
653 | out_copy: | |
654 | if (info->nand.options & NAND_BUSWIDTH_16) | |
655 | omap_read_buf16(mtd, buf, len); | |
656 | else | |
657 | omap_read_buf8(mtd, buf, len); | |
658 | } | |
659 | ||
660 | /* | |
661 | * omap_write_buf_irq_pref - write buffer to NAND controller | |
662 | * @mtd: MTD device structure | |
663 | * @buf: data buffer | |
664 | * @len: number of bytes to write | |
665 | */ | |
666 | static void omap_write_buf_irq_pref(struct mtd_info *mtd, | |
667 | const u_char *buf, int len) | |
668 | { | |
669 | struct omap_nand_info *info = container_of(mtd, | |
670 | struct omap_nand_info, mtd); | |
671 | int ret = 0; | |
672 | unsigned long tim, limit; | |
65b97cf6 | 673 | u32 val; |
4e070376 SG |
674 | |
675 | if (len <= mtd->oobsize) { | |
676 | omap_write_buf_pref(mtd, buf, len); | |
677 | return; | |
678 | } | |
679 | ||
680 | info->iomode = OMAP_NAND_IO_WRITE; | |
681 | info->buf = (u_char *) buf; | |
682 | init_completion(&info->comp); | |
683 | ||
317379a9 | 684 | /* configure and start prefetch transfer : size=24 */ |
65b97cf6 AM |
685 | ret = omap_prefetch_enable(info->gpmc_cs, |
686 | (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info); | |
4e070376 SG |
687 | if (ret) |
688 | /* PFPW engine is busy, use cpu copy method */ | |
689 | goto out_copy; | |
690 | ||
691 | info->buf_len = len; | |
5c468455 AM |
692 | |
693 | enable_irq(info->gpmc_irq_count); | |
694 | enable_irq(info->gpmc_irq_fifo); | |
4e070376 SG |
695 | |
696 | /* waiting for write to complete */ | |
697 | wait_for_completion(&info->comp); | |
5c468455 | 698 | |
4e070376 SG |
699 | /* wait for data to flushed-out before reset the prefetch */ |
700 | tim = 0; | |
701 | limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 AM |
702 | do { |
703 | val = readl(info->reg.gpmc_prefetch_status); | |
47f88af4 | 704 | val = PREFETCH_STATUS_COUNT(val); |
4e070376 | 705 | cpu_relax(); |
65b97cf6 | 706 | } while (val && (tim++ < limit)); |
4e070376 SG |
707 | |
708 | /* disable and stop the PFPW engine */ | |
65b97cf6 | 709 | omap_prefetch_reset(info->gpmc_cs, info); |
4e070376 SG |
710 | return; |
711 | ||
712 | out_copy: | |
713 | if (info->nand.options & NAND_BUSWIDTH_16) | |
714 | omap_write_buf16(mtd, buf, len); | |
715 | else | |
716 | omap_write_buf8(mtd, buf, len); | |
717 | } | |
718 | ||
67ce04bf VS |
719 | /** |
720 | * gen_true_ecc - This function will generate true ECC value | |
721 | * @ecc_buf: buffer to store ecc code | |
722 | * | |
723 | * This generated true ECC value can be used when correcting | |
724 | * data read from NAND flash memory core | |
725 | */ | |
726 | static void gen_true_ecc(u8 *ecc_buf) | |
727 | { | |
728 | u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) | | |
729 | ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8); | |
730 | ||
731 | ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | | |
732 | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp)); | |
733 | ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | | |
734 | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp)); | |
735 | ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | | |
736 | P1e(tmp) | P2048o(tmp) | P2048e(tmp)); | |
737 | } | |
738 | ||
739 | /** | |
740 | * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data | |
741 | * @ecc_data1: ecc code from nand spare area | |
742 | * @ecc_data2: ecc code from hardware register obtained from hardware ecc | |
743 | * @page_data: page data | |
744 | * | |
745 | * This function compares two ECC's and indicates if there is an error. | |
746 | * If the error can be corrected it will be corrected to the buffer. | |
74f1b724 JO |
747 | * If there is no error, %0 is returned. If there is an error but it |
748 | * was corrected, %1 is returned. Otherwise, %-1 is returned. | |
67ce04bf VS |
749 | */ |
750 | static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */ | |
751 | u8 *ecc_data2, /* read from register */ | |
752 | u8 *page_data) | |
753 | { | |
754 | uint i; | |
755 | u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8]; | |
756 | u8 comp0_bit[8], comp1_bit[8], comp2_bit[8]; | |
757 | u8 ecc_bit[24]; | |
758 | u8 ecc_sum = 0; | |
759 | u8 find_bit = 0; | |
760 | uint find_byte = 0; | |
761 | int isEccFF; | |
762 | ||
763 | isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF); | |
764 | ||
765 | gen_true_ecc(ecc_data1); | |
766 | gen_true_ecc(ecc_data2); | |
767 | ||
768 | for (i = 0; i <= 2; i++) { | |
769 | *(ecc_data1 + i) = ~(*(ecc_data1 + i)); | |
770 | *(ecc_data2 + i) = ~(*(ecc_data2 + i)); | |
771 | } | |
772 | ||
773 | for (i = 0; i < 8; i++) { | |
774 | tmp0_bit[i] = *ecc_data1 % 2; | |
775 | *ecc_data1 = *ecc_data1 / 2; | |
776 | } | |
777 | ||
778 | for (i = 0; i < 8; i++) { | |
779 | tmp1_bit[i] = *(ecc_data1 + 1) % 2; | |
780 | *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2; | |
781 | } | |
782 | ||
783 | for (i = 0; i < 8; i++) { | |
784 | tmp2_bit[i] = *(ecc_data1 + 2) % 2; | |
785 | *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2; | |
786 | } | |
787 | ||
788 | for (i = 0; i < 8; i++) { | |
789 | comp0_bit[i] = *ecc_data2 % 2; | |
790 | *ecc_data2 = *ecc_data2 / 2; | |
791 | } | |
792 | ||
793 | for (i = 0; i < 8; i++) { | |
794 | comp1_bit[i] = *(ecc_data2 + 1) % 2; | |
795 | *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2; | |
796 | } | |
797 | ||
798 | for (i = 0; i < 8; i++) { | |
799 | comp2_bit[i] = *(ecc_data2 + 2) % 2; | |
800 | *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2; | |
801 | } | |
802 | ||
803 | for (i = 0; i < 6; i++) | |
804 | ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2]; | |
805 | ||
806 | for (i = 0; i < 8; i++) | |
807 | ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i]; | |
808 | ||
809 | for (i = 0; i < 8; i++) | |
810 | ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i]; | |
811 | ||
812 | ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0]; | |
813 | ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1]; | |
814 | ||
815 | for (i = 0; i < 24; i++) | |
816 | ecc_sum += ecc_bit[i]; | |
817 | ||
818 | switch (ecc_sum) { | |
819 | case 0: | |
820 | /* Not reached because this function is not called if | |
821 | * ECC values are equal | |
822 | */ | |
823 | return 0; | |
824 | ||
825 | case 1: | |
826 | /* Uncorrectable error */ | |
289c0522 | 827 | pr_debug("ECC UNCORRECTED_ERROR 1\n"); |
67ce04bf VS |
828 | return -1; |
829 | ||
830 | case 11: | |
831 | /* UN-Correctable error */ | |
289c0522 | 832 | pr_debug("ECC UNCORRECTED_ERROR B\n"); |
67ce04bf VS |
833 | return -1; |
834 | ||
835 | case 12: | |
836 | /* Correctable error */ | |
837 | find_byte = (ecc_bit[23] << 8) + | |
838 | (ecc_bit[21] << 7) + | |
839 | (ecc_bit[19] << 6) + | |
840 | (ecc_bit[17] << 5) + | |
841 | (ecc_bit[15] << 4) + | |
842 | (ecc_bit[13] << 3) + | |
843 | (ecc_bit[11] << 2) + | |
844 | (ecc_bit[9] << 1) + | |
845 | ecc_bit[7]; | |
846 | ||
847 | find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; | |
848 | ||
0a32a102 BN |
849 | pr_debug("Correcting single bit ECC error at offset: " |
850 | "%d, bit: %d\n", find_byte, find_bit); | |
67ce04bf VS |
851 | |
852 | page_data[find_byte] ^= (1 << find_bit); | |
853 | ||
74f1b724 | 854 | return 1; |
67ce04bf VS |
855 | default: |
856 | if (isEccFF) { | |
857 | if (ecc_data2[0] == 0 && | |
858 | ecc_data2[1] == 0 && | |
859 | ecc_data2[2] == 0) | |
860 | return 0; | |
861 | } | |
289c0522 | 862 | pr_debug("UNCORRECTED_ERROR default\n"); |
67ce04bf VS |
863 | return -1; |
864 | } | |
865 | } | |
866 | ||
867 | /** | |
868 | * omap_correct_data - Compares the ECC read with HW generated ECC | |
869 | * @mtd: MTD device structure | |
870 | * @dat: page data | |
871 | * @read_ecc: ecc read from nand flash | |
872 | * @calc_ecc: ecc read from HW ECC registers | |
873 | * | |
874 | * Compares the ecc read from nand spare area with ECC registers values | |
74f1b724 JO |
875 | * and if ECC's mismatched, it will call 'omap_compare_ecc' for error |
876 | * detection and correction. If there are no errors, %0 is returned. If | |
877 | * there were errors and all of the errors were corrected, the number of | |
878 | * corrected errors is returned. If uncorrectable errors exist, %-1 is | |
879 | * returned. | |
67ce04bf VS |
880 | */ |
881 | static int omap_correct_data(struct mtd_info *mtd, u_char *dat, | |
882 | u_char *read_ecc, u_char *calc_ecc) | |
883 | { | |
884 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
885 | mtd); | |
886 | int blockCnt = 0, i = 0, ret = 0; | |
74f1b724 | 887 | int stat = 0; |
67ce04bf VS |
888 | |
889 | /* Ex NAND_ECC_HW12_2048 */ | |
890 | if ((info->nand.ecc.mode == NAND_ECC_HW) && | |
891 | (info->nand.ecc.size == 2048)) | |
892 | blockCnt = 4; | |
893 | else | |
894 | blockCnt = 1; | |
895 | ||
896 | for (i = 0; i < blockCnt; i++) { | |
897 | if (memcmp(read_ecc, calc_ecc, 3) != 0) { | |
898 | ret = omap_compare_ecc(read_ecc, calc_ecc, dat); | |
899 | if (ret < 0) | |
900 | return ret; | |
74f1b724 JO |
901 | /* keep track of the number of corrected errors */ |
902 | stat += ret; | |
67ce04bf VS |
903 | } |
904 | read_ecc += 3; | |
905 | calc_ecc += 3; | |
906 | dat += 512; | |
907 | } | |
74f1b724 | 908 | return stat; |
67ce04bf VS |
909 | } |
910 | ||
911 | /** | |
912 | * omap_calcuate_ecc - Generate non-inverted ECC bytes. | |
913 | * @mtd: MTD device structure | |
914 | * @dat: The pointer to data on which ecc is computed | |
915 | * @ecc_code: The ecc_code buffer | |
916 | * | |
917 | * Using noninverted ECC can be considered ugly since writing a blank | |
918 | * page ie. padding will clear the ECC bytes. This is no problem as long | |
919 | * nobody is trying to write data on the seemingly unused page. Reading | |
920 | * an erased page will produce an ECC mismatch between generated and read | |
921 | * ECC bytes that has to be dealt with separately. | |
922 | */ | |
923 | static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat, | |
924 | u_char *ecc_code) | |
925 | { | |
926 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
927 | mtd); | |
65b97cf6 AM |
928 | u32 val; |
929 | ||
930 | val = readl(info->reg.gpmc_ecc_config); | |
931 | if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs) | |
932 | return -EINVAL; | |
933 | ||
934 | /* read ecc result */ | |
935 | val = readl(info->reg.gpmc_ecc1_result); | |
936 | *ecc_code++ = val; /* P128e, ..., P1e */ | |
937 | *ecc_code++ = val >> 16; /* P128o, ..., P1o */ | |
938 | /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ | |
939 | *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); | |
940 | ||
941 | return 0; | |
67ce04bf VS |
942 | } |
943 | ||
944 | /** | |
945 | * omap_enable_hwecc - This function enables the hardware ecc functionality | |
946 | * @mtd: MTD device structure | |
947 | * @mode: Read/Write mode | |
948 | */ | |
949 | static void omap_enable_hwecc(struct mtd_info *mtd, int mode) | |
950 | { | |
951 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
952 | mtd); | |
953 | struct nand_chip *chip = mtd->priv; | |
954 | unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; | |
65b97cf6 AM |
955 | u32 val; |
956 | ||
957 | /* clear ecc and enable bits */ | |
958 | val = ECCCLEAR | ECC1; | |
959 | writel(val, info->reg.gpmc_ecc_control); | |
67ce04bf | 960 | |
65b97cf6 AM |
961 | /* program ecc and result sizes */ |
962 | val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) | | |
963 | ECC1RESULTSIZE); | |
964 | writel(val, info->reg.gpmc_ecc_size_config); | |
965 | ||
966 | switch (mode) { | |
967 | case NAND_ECC_READ: | |
968 | case NAND_ECC_WRITE: | |
969 | writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); | |
970 | break; | |
971 | case NAND_ECC_READSYN: | |
972 | writel(ECCCLEAR, info->reg.gpmc_ecc_control); | |
973 | break; | |
974 | default: | |
975 | dev_info(&info->pdev->dev, | |
976 | "error: unrecognized Mode[%d]!\n", mode); | |
977 | break; | |
978 | } | |
67ce04bf | 979 | |
65b97cf6 AM |
980 | /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ |
981 | val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); | |
982 | writel(val, info->reg.gpmc_ecc_config); | |
67ce04bf | 983 | } |
2c01946c | 984 | |
67ce04bf VS |
985 | /** |
986 | * omap_wait - wait until the command is done | |
987 | * @mtd: MTD device structure | |
988 | * @chip: NAND Chip structure | |
989 | * | |
990 | * Wait function is called during Program and erase operations and | |
991 | * the way it is called from MTD layer, we should wait till the NAND | |
992 | * chip is ready after the programming/erase operation has completed. | |
993 | * | |
994 | * Erase can take up to 400ms and program up to 20ms according to | |
995 | * general NAND and SmartMedia specs | |
996 | */ | |
997 | static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
998 | { | |
999 | struct nand_chip *this = mtd->priv; | |
1000 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1001 | mtd); | |
1002 | unsigned long timeo = jiffies; | |
a9c465f0 | 1003 | int status, state = this->state; |
67ce04bf VS |
1004 | |
1005 | if (state == FL_ERASING) | |
4ff6772b | 1006 | timeo += msecs_to_jiffies(400); |
67ce04bf | 1007 | else |
4ff6772b | 1008 | timeo += msecs_to_jiffies(20); |
67ce04bf | 1009 | |
65b97cf6 | 1010 | writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command); |
67ce04bf | 1011 | while (time_before(jiffies, timeo)) { |
65b97cf6 | 1012 | status = readb(info->reg.gpmc_nand_data); |
c276aca4 | 1013 | if (status & NAND_STATUS_READY) |
67ce04bf | 1014 | break; |
c276aca4 | 1015 | cond_resched(); |
67ce04bf | 1016 | } |
a9c465f0 | 1017 | |
4ea1e4ba | 1018 | status = readb(info->reg.gpmc_nand_data); |
67ce04bf VS |
1019 | return status; |
1020 | } | |
1021 | ||
1022 | /** | |
1023 | * omap_dev_ready - calls the platform specific dev_ready function | |
1024 | * @mtd: MTD device structure | |
1025 | */ | |
1026 | static int omap_dev_ready(struct mtd_info *mtd) | |
1027 | { | |
2c01946c | 1028 | unsigned int val = 0; |
67ce04bf VS |
1029 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
1030 | mtd); | |
67ce04bf | 1031 | |
65b97cf6 AM |
1032 | val = readl(info->reg.gpmc_status); |
1033 | ||
67ce04bf | 1034 | if ((val & 0x100) == 0x100) { |
65b97cf6 | 1035 | return 1; |
67ce04bf | 1036 | } else { |
65b97cf6 | 1037 | return 0; |
67ce04bf | 1038 | } |
67ce04bf VS |
1039 | } |
1040 | ||
0e618ef0 | 1041 | /** |
7c977c3e | 1042 | * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation |
0e618ef0 ID |
1043 | * @mtd: MTD device structure |
1044 | * @mode: Read/Write mode | |
62116e51 PA |
1045 | * |
1046 | * When using BCH, sector size is hardcoded to 512 bytes. | |
1047 | * Using wrapping mode 6 both for reading and writing if ELM module not uses | |
1048 | * for error correction. | |
1049 | * On writing, | |
1050 | * eccsize0 = 0 (no additional protected byte in spare area) | |
1051 | * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area) | |
0e618ef0 | 1052 | */ |
7c977c3e | 1053 | static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, int mode) |
0e618ef0 | 1054 | { |
16e69322 | 1055 | unsigned int bch_type; |
2ef9f3dd | 1056 | unsigned int dev_width, nsectors; |
0e618ef0 ID |
1057 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
1058 | mtd); | |
c5957a32 | 1059 | enum omap_ecc ecc_opt = info->ecc_opt; |
0e618ef0 | 1060 | struct nand_chip *chip = mtd->priv; |
62116e51 PA |
1061 | u32 val, wr_mode; |
1062 | unsigned int ecc_size1, ecc_size0; | |
1063 | ||
c5957a32 PG |
1064 | /* GPMC configurations for calculating ECC */ |
1065 | switch (ecc_opt) { | |
1066 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: | |
16e69322 PG |
1067 | bch_type = 0; |
1068 | nsectors = 1; | |
c5957a32 PG |
1069 | if (mode == NAND_ECC_READ) { |
1070 | wr_mode = BCH_WRAPMODE_6; | |
1071 | ecc_size0 = BCH_ECC_SIZE0; | |
1072 | ecc_size1 = BCH_ECC_SIZE1; | |
1073 | } else { | |
1074 | wr_mode = BCH_WRAPMODE_6; | |
1075 | ecc_size0 = BCH_ECC_SIZE0; | |
1076 | ecc_size1 = BCH_ECC_SIZE1; | |
1077 | } | |
1078 | break; | |
1079 | case OMAP_ECC_BCH4_CODE_HW: | |
16e69322 PG |
1080 | bch_type = 0; |
1081 | nsectors = chip->ecc.steps; | |
c5957a32 PG |
1082 | if (mode == NAND_ECC_READ) { |
1083 | wr_mode = BCH_WRAPMODE_1; | |
1084 | ecc_size0 = BCH4R_ECC_SIZE0; | |
1085 | ecc_size1 = BCH4R_ECC_SIZE1; | |
1086 | } else { | |
1087 | wr_mode = BCH_WRAPMODE_6; | |
1088 | ecc_size0 = BCH_ECC_SIZE0; | |
1089 | ecc_size1 = BCH_ECC_SIZE1; | |
1090 | } | |
1091 | break; | |
1092 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | |
16e69322 PG |
1093 | bch_type = 1; |
1094 | nsectors = 1; | |
c5957a32 PG |
1095 | if (mode == NAND_ECC_READ) { |
1096 | wr_mode = BCH_WRAPMODE_6; | |
1097 | ecc_size0 = BCH_ECC_SIZE0; | |
1098 | ecc_size1 = BCH_ECC_SIZE1; | |
1099 | } else { | |
1100 | wr_mode = BCH_WRAPMODE_6; | |
1101 | ecc_size0 = BCH_ECC_SIZE0; | |
1102 | ecc_size1 = BCH_ECC_SIZE1; | |
1103 | } | |
1104 | break; | |
1105 | case OMAP_ECC_BCH8_CODE_HW: | |
16e69322 PG |
1106 | bch_type = 1; |
1107 | nsectors = chip->ecc.steps; | |
c5957a32 PG |
1108 | if (mode == NAND_ECC_READ) { |
1109 | wr_mode = BCH_WRAPMODE_1; | |
1110 | ecc_size0 = BCH8R_ECC_SIZE0; | |
1111 | ecc_size1 = BCH8R_ECC_SIZE1; | |
1112 | } else { | |
1113 | wr_mode = BCH_WRAPMODE_6; | |
1114 | ecc_size0 = BCH_ECC_SIZE0; | |
1115 | ecc_size1 = BCH_ECC_SIZE1; | |
1116 | } | |
1117 | break; | |
1118 | default: | |
1119 | return; | |
1120 | } | |
2ef9f3dd AM |
1121 | |
1122 | writel(ECC1, info->reg.gpmc_ecc_control); | |
1123 | ||
62116e51 PA |
1124 | /* Configure ecc size for BCH */ |
1125 | val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT); | |
2ef9f3dd AM |
1126 | writel(val, info->reg.gpmc_ecc_size_config); |
1127 | ||
62116e51 PA |
1128 | dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; |
1129 | ||
2ef9f3dd AM |
1130 | /* BCH configuration */ |
1131 | val = ((1 << 16) | /* enable BCH */ | |
16e69322 | 1132 | (bch_type << 12) | /* BCH4/BCH8/BCH16 */ |
62116e51 | 1133 | (wr_mode << 8) | /* wrap mode */ |
2ef9f3dd AM |
1134 | (dev_width << 7) | /* bus width */ |
1135 | (((nsectors-1) & 0x7) << 4) | /* number of sectors */ | |
1136 | (info->gpmc_cs << 1) | /* ECC CS */ | |
1137 | (0x1)); /* enable ECC */ | |
1138 | ||
1139 | writel(val, info->reg.gpmc_ecc_config); | |
1140 | ||
62116e51 | 1141 | /* Clear ecc and enable bits */ |
2ef9f3dd | 1142 | writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); |
0e618ef0 | 1143 | } |
7c977c3e | 1144 | |
2c9f2365 | 1145 | static u8 bch4_polynomial[] = {0x28, 0x13, 0xcc, 0x39, 0x96, 0xac, 0x7f}; |
7bcd1dca PG |
1146 | static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2, |
1147 | 0x97, 0x79, 0xe5, 0x24, 0xb5}; | |
0e618ef0 | 1148 | |
62116e51 | 1149 | /** |
a4c7ca00 | 1150 | * omap_calculate_ecc_bch - Generate bytes of ECC bytes |
62116e51 PA |
1151 | * @mtd: MTD device structure |
1152 | * @dat: The pointer to data on which ecc is computed | |
1153 | * @ecc_code: The ecc_code buffer | |
1154 | * | |
1155 | * Support calculating of BCH4/8 ecc vectors for the page | |
1156 | */ | |
a4c7ca00 | 1157 | static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd, |
f5dc06fb | 1158 | const u_char *dat, u_char *ecc_calc) |
62116e51 PA |
1159 | { |
1160 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1161 | mtd); | |
f5dc06fb PG |
1162 | int eccbytes = info->nand.ecc.bytes; |
1163 | struct gpmc_nand_regs *gpmc_regs = &info->reg; | |
1164 | u8 *ecc_code; | |
62116e51 | 1165 | unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4; |
f5dc06fb | 1166 | int i; |
62116e51 PA |
1167 | |
1168 | nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1; | |
62116e51 | 1169 | for (i = 0; i < nsectors; i++) { |
f5dc06fb PG |
1170 | ecc_code = ecc_calc; |
1171 | switch (info->ecc_opt) { | |
7bcd1dca | 1172 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: |
f5dc06fb PG |
1173 | case OMAP_ECC_BCH8_CODE_HW: |
1174 | bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]); | |
1175 | bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]); | |
1176 | bch_val3 = readl(gpmc_regs->gpmc_bch_result2[i]); | |
1177 | bch_val4 = readl(gpmc_regs->gpmc_bch_result3[i]); | |
62116e51 PA |
1178 | *ecc_code++ = (bch_val4 & 0xFF); |
1179 | *ecc_code++ = ((bch_val3 >> 24) & 0xFF); | |
1180 | *ecc_code++ = ((bch_val3 >> 16) & 0xFF); | |
1181 | *ecc_code++ = ((bch_val3 >> 8) & 0xFF); | |
1182 | *ecc_code++ = (bch_val3 & 0xFF); | |
1183 | *ecc_code++ = ((bch_val2 >> 24) & 0xFF); | |
1184 | *ecc_code++ = ((bch_val2 >> 16) & 0xFF); | |
1185 | *ecc_code++ = ((bch_val2 >> 8) & 0xFF); | |
1186 | *ecc_code++ = (bch_val2 & 0xFF); | |
1187 | *ecc_code++ = ((bch_val1 >> 24) & 0xFF); | |
1188 | *ecc_code++ = ((bch_val1 >> 16) & 0xFF); | |
1189 | *ecc_code++ = ((bch_val1 >> 8) & 0xFF); | |
1190 | *ecc_code++ = (bch_val1 & 0xFF); | |
f5dc06fb | 1191 | break; |
2c9f2365 | 1192 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: |
f5dc06fb PG |
1193 | case OMAP_ECC_BCH4_CODE_HW: |
1194 | bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]); | |
1195 | bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]); | |
62116e51 PA |
1196 | *ecc_code++ = ((bch_val2 >> 12) & 0xFF); |
1197 | *ecc_code++ = ((bch_val2 >> 4) & 0xFF); | |
1198 | *ecc_code++ = ((bch_val2 & 0xF) << 4) | | |
1199 | ((bch_val1 >> 28) & 0xF); | |
1200 | *ecc_code++ = ((bch_val1 >> 20) & 0xFF); | |
1201 | *ecc_code++ = ((bch_val1 >> 12) & 0xFF); | |
1202 | *ecc_code++ = ((bch_val1 >> 4) & 0xFF); | |
1203 | *ecc_code++ = ((bch_val1 & 0xF) << 4); | |
f5dc06fb PG |
1204 | break; |
1205 | default: | |
1206 | return -EINVAL; | |
62116e51 | 1207 | } |
f5dc06fb PG |
1208 | |
1209 | /* ECC scheme specific syndrome customizations */ | |
1210 | switch (info->ecc_opt) { | |
2c9f2365 PG |
1211 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: |
1212 | /* Add constant polynomial to remainder, so that | |
1213 | * ECC of blank pages results in 0x0 on reading back */ | |
1214 | for (i = 0; i < eccbytes; i++) | |
1215 | ecc_calc[i] ^= bch4_polynomial[i]; | |
1216 | break; | |
f5dc06fb PG |
1217 | case OMAP_ECC_BCH4_CODE_HW: |
1218 | /* Set 8th ECC byte as 0x0 for ROM compatibility */ | |
1219 | ecc_calc[eccbytes - 1] = 0x0; | |
1220 | break; | |
7bcd1dca PG |
1221 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: |
1222 | /* Add constant polynomial to remainder, so that | |
1223 | * ECC of blank pages results in 0x0 on reading back */ | |
1224 | for (i = 0; i < eccbytes; i++) | |
1225 | ecc_calc[i] ^= bch8_polynomial[i]; | |
1226 | break; | |
f5dc06fb PG |
1227 | case OMAP_ECC_BCH8_CODE_HW: |
1228 | /* Set 14th ECC byte as 0x0 for ROM compatibility */ | |
1229 | ecc_calc[eccbytes - 1] = 0x0; | |
1230 | break; | |
1231 | default: | |
1232 | return -EINVAL; | |
1233 | } | |
1234 | ||
1235 | ecc_calc += eccbytes; | |
62116e51 PA |
1236 | } |
1237 | ||
1238 | return 0; | |
1239 | } | |
1240 | ||
1241 | /** | |
1242 | * erased_sector_bitflips - count bit flips | |
1243 | * @data: data sector buffer | |
1244 | * @oob: oob buffer | |
1245 | * @info: omap_nand_info | |
1246 | * | |
1247 | * Check the bit flips in erased page falls below correctable level. | |
1248 | * If falls below, report the page as erased with correctable bit | |
1249 | * flip, else report as uncorrectable page. | |
1250 | */ | |
1251 | static int erased_sector_bitflips(u_char *data, u_char *oob, | |
1252 | struct omap_nand_info *info) | |
1253 | { | |
1254 | int flip_bits = 0, i; | |
1255 | ||
1256 | for (i = 0; i < info->nand.ecc.size; i++) { | |
1257 | flip_bits += hweight8(~data[i]); | |
1258 | if (flip_bits > info->nand.ecc.strength) | |
1259 | return 0; | |
1260 | } | |
1261 | ||
1262 | for (i = 0; i < info->nand.ecc.bytes - 1; i++) { | |
1263 | flip_bits += hweight8(~oob[i]); | |
1264 | if (flip_bits > info->nand.ecc.strength) | |
1265 | return 0; | |
1266 | } | |
1267 | ||
1268 | /* | |
1269 | * Bit flips falls in correctable level. | |
1270 | * Fill data area with 0xFF | |
1271 | */ | |
1272 | if (flip_bits) { | |
1273 | memset(data, 0xFF, info->nand.ecc.size); | |
1274 | memset(oob, 0xFF, info->nand.ecc.bytes); | |
1275 | } | |
1276 | ||
1277 | return flip_bits; | |
1278 | } | |
1279 | ||
2c9f2365 | 1280 | #ifdef CONFIG_MTD_NAND_OMAP_BCH |
62116e51 PA |
1281 | /** |
1282 | * omap_elm_correct_data - corrects page data area in case error reported | |
1283 | * @mtd: MTD device structure | |
1284 | * @data: page data | |
1285 | * @read_ecc: ecc read from nand flash | |
1286 | * @calc_ecc: ecc read from HW ECC registers | |
1287 | * | |
1288 | * Calculated ecc vector reported as zero in case of non-error pages. | |
78f43c53 PG |
1289 | * In case of non-zero ecc vector, first filter out erased-pages, and |
1290 | * then process data via ELM to detect bit-flips. | |
62116e51 PA |
1291 | */ |
1292 | static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data, | |
1293 | u_char *read_ecc, u_char *calc_ecc) | |
1294 | { | |
1295 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1296 | mtd); | |
de0a4d69 | 1297 | struct nand_ecc_ctrl *ecc = &info->nand.ecc; |
62116e51 PA |
1298 | int eccsteps = info->nand.ecc.steps; |
1299 | int i , j, stat = 0; | |
de0a4d69 | 1300 | int eccflag, actual_eccbytes; |
62116e51 PA |
1301 | struct elm_errorvec err_vec[ERROR_VECTOR_MAX]; |
1302 | u_char *ecc_vec = calc_ecc; | |
1303 | u_char *spare_ecc = read_ecc; | |
1304 | u_char *erased_ecc_vec; | |
78f43c53 PG |
1305 | u_char *buf; |
1306 | int bitflip_count; | |
62116e51 | 1307 | bool is_error_reported = false; |
b08e1f63 | 1308 | u32 bit_pos, byte_pos, error_max, pos; |
13fbe064 | 1309 | int err; |
62116e51 | 1310 | |
de0a4d69 PG |
1311 | switch (info->ecc_opt) { |
1312 | case OMAP_ECC_BCH4_CODE_HW: | |
1313 | /* omit 7th ECC byte reserved for ROM code compatibility */ | |
1314 | actual_eccbytes = ecc->bytes - 1; | |
78f43c53 | 1315 | erased_ecc_vec = bch4_vector; |
de0a4d69 PG |
1316 | break; |
1317 | case OMAP_ECC_BCH8_CODE_HW: | |
1318 | /* omit 14th ECC byte reserved for ROM code compatibility */ | |
1319 | actual_eccbytes = ecc->bytes - 1; | |
78f43c53 | 1320 | erased_ecc_vec = bch8_vector; |
de0a4d69 PG |
1321 | break; |
1322 | default: | |
1323 | pr_err("invalid driver configuration\n"); | |
1324 | return -EINVAL; | |
1325 | } | |
1326 | ||
62116e51 PA |
1327 | /* Initialize elm error vector to zero */ |
1328 | memset(err_vec, 0, sizeof(err_vec)); | |
1329 | ||
62116e51 PA |
1330 | for (i = 0; i < eccsteps ; i++) { |
1331 | eccflag = 0; /* initialize eccflag */ | |
1332 | ||
1333 | /* | |
1334 | * Check any error reported, | |
1335 | * In case of error, non zero ecc reported. | |
1336 | */ | |
de0a4d69 | 1337 | for (j = 0; j < actual_eccbytes; j++) { |
62116e51 PA |
1338 | if (calc_ecc[j] != 0) { |
1339 | eccflag = 1; /* non zero ecc, error present */ | |
1340 | break; | |
1341 | } | |
1342 | } | |
1343 | ||
1344 | if (eccflag == 1) { | |
78f43c53 PG |
1345 | if (memcmp(calc_ecc, erased_ecc_vec, |
1346 | actual_eccbytes) == 0) { | |
62116e51 | 1347 | /* |
78f43c53 PG |
1348 | * calc_ecc[] matches pattern for ECC(all 0xff) |
1349 | * so this is definitely an erased-page | |
62116e51 | 1350 | */ |
62116e51 | 1351 | } else { |
78f43c53 PG |
1352 | buf = &data[info->nand.ecc.size * i]; |
1353 | /* | |
1354 | * count number of 0-bits in read_buf. | |
1355 | * This check can be removed once a similar | |
1356 | * check is introduced in generic NAND driver | |
1357 | */ | |
1358 | bitflip_count = erased_sector_bitflips( | |
1359 | buf, read_ecc, info); | |
1360 | if (bitflip_count) { | |
1361 | /* | |
1362 | * number of 0-bits within ECC limits | |
1363 | * So this may be an erased-page | |
1364 | */ | |
1365 | stat += bitflip_count; | |
1366 | } else { | |
1367 | /* | |
1368 | * Too many 0-bits. It may be a | |
1369 | * - programmed-page, OR | |
1370 | * - erased-page with many bit-flips | |
1371 | * So this page requires check by ELM | |
1372 | */ | |
1373 | err_vec[i].error_reported = true; | |
1374 | is_error_reported = true; | |
62116e51 PA |
1375 | } |
1376 | } | |
1377 | } | |
1378 | ||
1379 | /* Update the ecc vector */ | |
de0a4d69 PG |
1380 | calc_ecc += ecc->bytes; |
1381 | read_ecc += ecc->bytes; | |
62116e51 PA |
1382 | } |
1383 | ||
1384 | /* Check if any error reported */ | |
1385 | if (!is_error_reported) | |
1386 | return 0; | |
1387 | ||
1388 | /* Decode BCH error using ELM module */ | |
1389 | elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec); | |
1390 | ||
13fbe064 | 1391 | err = 0; |
62116e51 | 1392 | for (i = 0; i < eccsteps; i++) { |
13fbe064 PG |
1393 | if (err_vec[i].error_uncorrectable) { |
1394 | pr_err("nand: uncorrectable bit-flips found\n"); | |
1395 | err = -EBADMSG; | |
1396 | } else if (err_vec[i].error_reported) { | |
62116e51 | 1397 | for (j = 0; j < err_vec[i].error_count; j++) { |
b08e1f63 PG |
1398 | switch (info->ecc_opt) { |
1399 | case OMAP_ECC_BCH4_CODE_HW: | |
1400 | /* Add 4 bits to take care of padding */ | |
62116e51 PA |
1401 | pos = err_vec[i].error_loc[j] + |
1402 | BCH4_BIT_PAD; | |
b08e1f63 PG |
1403 | break; |
1404 | case OMAP_ECC_BCH8_CODE_HW: | |
1405 | pos = err_vec[i].error_loc[j]; | |
1406 | break; | |
1407 | default: | |
1408 | return -EINVAL; | |
1409 | } | |
1410 | error_max = (ecc->size + actual_eccbytes) * 8; | |
62116e51 PA |
1411 | /* Calculate bit position of error */ |
1412 | bit_pos = pos % 8; | |
1413 | ||
1414 | /* Calculate byte position of error */ | |
1415 | byte_pos = (error_max - pos - 1) / 8; | |
1416 | ||
1417 | if (pos < error_max) { | |
13fbe064 PG |
1418 | if (byte_pos < 512) { |
1419 | pr_debug("bitflip@dat[%d]=%x\n", | |
1420 | byte_pos, data[byte_pos]); | |
62116e51 | 1421 | data[byte_pos] ^= 1 << bit_pos; |
13fbe064 PG |
1422 | } else { |
1423 | pr_debug("bitflip@oob[%d]=%x\n", | |
1424 | (byte_pos - 512), | |
1425 | spare_ecc[byte_pos - 512]); | |
62116e51 PA |
1426 | spare_ecc[byte_pos - 512] ^= |
1427 | 1 << bit_pos; | |
13fbe064 PG |
1428 | } |
1429 | } else { | |
1430 | pr_err("invalid bit-flip @ %d:%d\n", | |
1431 | byte_pos, bit_pos); | |
1432 | err = -EBADMSG; | |
62116e51 | 1433 | } |
62116e51 PA |
1434 | } |
1435 | } | |
1436 | ||
1437 | /* Update number of correctable errors */ | |
1438 | stat += err_vec[i].error_count; | |
1439 | ||
1440 | /* Update page data with sector size */ | |
b08e1f63 | 1441 | data += ecc->size; |
de0a4d69 | 1442 | spare_ecc += ecc->bytes; |
62116e51 PA |
1443 | } |
1444 | ||
13fbe064 | 1445 | return (err) ? err : stat; |
62116e51 PA |
1446 | } |
1447 | ||
62116e51 PA |
1448 | /** |
1449 | * omap_write_page_bch - BCH ecc based write page function for entire page | |
1450 | * @mtd: mtd info structure | |
1451 | * @chip: nand chip info structure | |
1452 | * @buf: data buffer | |
1453 | * @oob_required: must write chip->oob_poi to OOB | |
1454 | * | |
1455 | * Custom write page method evolved to support multi sector writing in one shot | |
1456 | */ | |
1457 | static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip, | |
1458 | const uint8_t *buf, int oob_required) | |
1459 | { | |
1460 | int i; | |
1461 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
1462 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1463 | ||
1464 | /* Enable GPMC ecc engine */ | |
1465 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
1466 | ||
1467 | /* Write data */ | |
1468 | chip->write_buf(mtd, buf, mtd->writesize); | |
1469 | ||
1470 | /* Update ecc vector from GPMC result registers */ | |
1471 | chip->ecc.calculate(mtd, buf, &ecc_calc[0]); | |
1472 | ||
1473 | for (i = 0; i < chip->ecc.total; i++) | |
1474 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
1475 | ||
1476 | /* Write ecc vector to OOB area */ | |
1477 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1478 | return 0; | |
1479 | } | |
1480 | ||
1481 | /** | |
1482 | * omap_read_page_bch - BCH ecc based page read function for entire page | |
1483 | * @mtd: mtd info structure | |
1484 | * @chip: nand chip info structure | |
1485 | * @buf: buffer to store read data | |
1486 | * @oob_required: caller requires OOB data read to chip->oob_poi | |
1487 | * @page: page number to read | |
1488 | * | |
1489 | * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module | |
1490 | * used for error correction. | |
1491 | * Custom method evolved to support ELM error correction & multi sector | |
1492 | * reading. On reading page data area is read along with OOB data with | |
1493 | * ecc engine enabled. ecc vector updated after read of OOB data. | |
1494 | * For non error pages ecc vector reported as zero. | |
1495 | */ | |
1496 | static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, | |
1497 | uint8_t *buf, int oob_required, int page) | |
1498 | { | |
1499 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
1500 | uint8_t *ecc_code = chip->buffers->ecccode; | |
1501 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1502 | uint8_t *oob = &chip->oob_poi[eccpos[0]]; | |
1503 | uint32_t oob_pos = mtd->writesize + chip->ecc.layout->eccpos[0]; | |
1504 | int stat; | |
1505 | unsigned int max_bitflips = 0; | |
1506 | ||
1507 | /* Enable GPMC ecc engine */ | |
1508 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1509 | ||
1510 | /* Read data */ | |
1511 | chip->read_buf(mtd, buf, mtd->writesize); | |
1512 | ||
1513 | /* Read oob bytes */ | |
1514 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1); | |
1515 | chip->read_buf(mtd, oob, chip->ecc.total); | |
1516 | ||
1517 | /* Calculate ecc bytes */ | |
1518 | chip->ecc.calculate(mtd, buf, ecc_calc); | |
1519 | ||
1520 | memcpy(ecc_code, &chip->oob_poi[eccpos[0]], chip->ecc.total); | |
1521 | ||
1522 | stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc); | |
1523 | ||
1524 | if (stat < 0) { | |
1525 | mtd->ecc_stats.failed++; | |
1526 | } else { | |
1527 | mtd->ecc_stats.corrected += stat; | |
1528 | max_bitflips = max_t(unsigned int, max_bitflips, stat); | |
1529 | } | |
1530 | ||
1531 | return max_bitflips; | |
1532 | } | |
1533 | ||
0e618ef0 | 1534 | /** |
a919e511 PG |
1535 | * is_elm_present - checks for presence of ELM module by scanning DT nodes |
1536 | * @omap_nand_info: NAND device structure containing platform data | |
1537 | * @bch_type: 0x0=BCH4, 0x1=BCH8, 0x2=BCH16 | |
0e618ef0 | 1538 | */ |
a919e511 PG |
1539 | static int is_elm_present(struct omap_nand_info *info, |
1540 | struct device_node *elm_node, enum bch_ecc bch_type) | |
0e618ef0 | 1541 | { |
a919e511 | 1542 | struct platform_device *pdev; |
3f4eb14b PG |
1543 | struct nand_ecc_ctrl *ecc = &info->nand.ecc; |
1544 | int err; | |
a919e511 PG |
1545 | /* check whether elm-id is passed via DT */ |
1546 | if (!elm_node) { | |
1547 | pr_err("nand: error: ELM DT node not found\n"); | |
1548 | return -ENODEV; | |
1549 | } | |
1550 | pdev = of_find_device_by_node(elm_node); | |
1551 | /* check whether ELM device is registered */ | |
1552 | if (!pdev) { | |
1553 | pr_err("nand: error: ELM device not found\n"); | |
1554 | return -ENODEV; | |
0e618ef0 | 1555 | } |
a919e511 PG |
1556 | /* ELM module available, now configure it */ |
1557 | info->elm_dev = &pdev->dev; | |
3f4eb14b PG |
1558 | err = elm_config(info->elm_dev, bch_type, |
1559 | (info->mtd.writesize / ecc->size), ecc->size, ecc->bytes); | |
1560 | ||
1561 | return err; | |
0e618ef0 | 1562 | } |
a919e511 | 1563 | #endif /* CONFIG_MTD_NAND_ECC_BCH */ |
0e618ef0 | 1564 | |
06f25510 | 1565 | static int omap_nand_probe(struct platform_device *pdev) |
67ce04bf VS |
1566 | { |
1567 | struct omap_nand_info *info; | |
1568 | struct omap_nand_platform_data *pdata; | |
633deb58 PG |
1569 | struct mtd_info *mtd; |
1570 | struct nand_chip *nand_chip; | |
b491da72 | 1571 | struct nand_ecclayout *ecclayout; |
67ce04bf | 1572 | int err; |
b491da72 | 1573 | int i; |
633deb58 PG |
1574 | dma_cap_mask_t mask; |
1575 | unsigned sig; | |
eae39cb4 | 1576 | unsigned oob_index; |
9c4c2f8b | 1577 | struct resource *res; |
ccf04c51 | 1578 | struct mtd_part_parser_data ppdata = {}; |
67ce04bf | 1579 | |
453810b7 | 1580 | pdata = dev_get_platdata(&pdev->dev); |
67ce04bf VS |
1581 | if (pdata == NULL) { |
1582 | dev_err(&pdev->dev, "platform data missing\n"); | |
1583 | return -ENODEV; | |
1584 | } | |
1585 | ||
70ba6d71 PG |
1586 | info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info), |
1587 | GFP_KERNEL); | |
67ce04bf VS |
1588 | if (!info) |
1589 | return -ENOMEM; | |
1590 | ||
1591 | platform_set_drvdata(pdev, info); | |
1592 | ||
1593 | spin_lock_init(&info->controller.lock); | |
1594 | init_waitqueue_head(&info->controller.wq); | |
1595 | ||
633deb58 | 1596 | info->pdev = pdev; |
67ce04bf | 1597 | info->gpmc_cs = pdata->cs; |
65b97cf6 | 1598 | info->reg = pdata->reg; |
a919e511 | 1599 | info->of_node = pdata->of_node; |
4e558072 | 1600 | info->ecc_opt = pdata->ecc_opt; |
633deb58 PG |
1601 | mtd = &info->mtd; |
1602 | mtd->priv = &info->nand; | |
1603 | mtd->name = dev_name(&pdev->dev); | |
1604 | mtd->owner = THIS_MODULE; | |
1605 | nand_chip = &info->nand; | |
32d42a85 | 1606 | nand_chip->ecc.priv = NULL; |
633deb58 | 1607 | nand_chip->options |= NAND_SKIP_BBTSCAN; |
67ce04bf | 1608 | |
9c4c2f8b AM |
1609 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1610 | if (res == NULL) { | |
1611 | err = -EINVAL; | |
1612 | dev_err(&pdev->dev, "error getting memory resource\n"); | |
70ba6d71 | 1613 | goto return_error; |
9c4c2f8b | 1614 | } |
67ce04bf | 1615 | |
9c4c2f8b AM |
1616 | info->phys_base = res->start; |
1617 | info->mem_size = resource_size(res); | |
1618 | ||
70ba6d71 PG |
1619 | if (!devm_request_mem_region(&pdev->dev, info->phys_base, |
1620 | info->mem_size, pdev->dev.driver->name)) { | |
67ce04bf | 1621 | err = -EBUSY; |
70ba6d71 | 1622 | goto return_error; |
67ce04bf VS |
1623 | } |
1624 | ||
70ba6d71 PG |
1625 | nand_chip->IO_ADDR_R = devm_ioremap(&pdev->dev, info->phys_base, |
1626 | info->mem_size); | |
633deb58 | 1627 | if (!nand_chip->IO_ADDR_R) { |
67ce04bf | 1628 | err = -ENOMEM; |
70ba6d71 | 1629 | goto return_error; |
67ce04bf | 1630 | } |
59e9c5ae | 1631 | |
633deb58 | 1632 | nand_chip->controller = &info->controller; |
67ce04bf | 1633 | |
633deb58 PG |
1634 | nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R; |
1635 | nand_chip->cmd_ctrl = omap_hwcontrol; | |
67ce04bf | 1636 | |
67ce04bf VS |
1637 | /* |
1638 | * If RDY/BSY line is connected to OMAP then use the omap ready | |
4cacbe22 PM |
1639 | * function and the generic nand_wait function which reads the status |
1640 | * register after monitoring the RDY/BSY line. Otherwise use a standard | |
67ce04bf VS |
1641 | * chip delay which is slightly more than tR (AC Timing) of the NAND |
1642 | * device and read status register until you get a failure or success | |
1643 | */ | |
1644 | if (pdata->dev_ready) { | |
633deb58 PG |
1645 | nand_chip->dev_ready = omap_dev_ready; |
1646 | nand_chip->chip_delay = 0; | |
67ce04bf | 1647 | } else { |
633deb58 PG |
1648 | nand_chip->waitfunc = omap_wait; |
1649 | nand_chip->chip_delay = 50; | |
67ce04bf VS |
1650 | } |
1651 | ||
f18befb5 PG |
1652 | /* scan NAND device connected to chip controller */ |
1653 | nand_chip->options |= pdata->devsize & NAND_BUSWIDTH_16; | |
1654 | if (nand_scan_ident(mtd, 1, NULL)) { | |
1655 | pr_err("nand device scan failed, may be bus-width mismatch\n"); | |
1656 | err = -ENXIO; | |
70ba6d71 | 1657 | goto return_error; |
f18befb5 PG |
1658 | } |
1659 | ||
b491da72 PG |
1660 | /* check for small page devices */ |
1661 | if ((mtd->oobsize < 64) && (pdata->ecc_opt != OMAP_ECC_HAM1_CODE_HW)) { | |
1662 | pr_err("small page devices are not supported\n"); | |
1663 | err = -EINVAL; | |
70ba6d71 | 1664 | goto return_error; |
b491da72 PG |
1665 | } |
1666 | ||
f18befb5 | 1667 | /* re-populate low-level callbacks based on xfer modes */ |
1b0b323c SG |
1668 | switch (pdata->xfer_type) { |
1669 | case NAND_OMAP_PREFETCH_POLLED: | |
633deb58 PG |
1670 | nand_chip->read_buf = omap_read_buf_pref; |
1671 | nand_chip->write_buf = omap_write_buf_pref; | |
1b0b323c SG |
1672 | break; |
1673 | ||
1674 | case NAND_OMAP_POLLED: | |
cf0e4d2b | 1675 | /* Use nand_base defaults for {read,write}_buf */ |
1b0b323c SG |
1676 | break; |
1677 | ||
1678 | case NAND_OMAP_PREFETCH_DMA: | |
763e7359 RK |
1679 | dma_cap_zero(mask); |
1680 | dma_cap_set(DMA_SLAVE, mask); | |
1681 | sig = OMAP24XX_DMA_GPMC; | |
1682 | info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig); | |
1683 | if (!info->dma) { | |
2df41d05 RK |
1684 | dev_err(&pdev->dev, "DMA engine request failed\n"); |
1685 | err = -ENXIO; | |
70ba6d71 | 1686 | goto return_error; |
763e7359 RK |
1687 | } else { |
1688 | struct dma_slave_config cfg; | |
763e7359 RK |
1689 | |
1690 | memset(&cfg, 0, sizeof(cfg)); | |
1691 | cfg.src_addr = info->phys_base; | |
1692 | cfg.dst_addr = info->phys_base; | |
1693 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1694 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1695 | cfg.src_maxburst = 16; | |
1696 | cfg.dst_maxburst = 16; | |
d680e2c1 AB |
1697 | err = dmaengine_slave_config(info->dma, &cfg); |
1698 | if (err) { | |
763e7359 | 1699 | dev_err(&pdev->dev, "DMA engine slave config failed: %d\n", |
d680e2c1 | 1700 | err); |
70ba6d71 | 1701 | goto return_error; |
763e7359 | 1702 | } |
633deb58 PG |
1703 | nand_chip->read_buf = omap_read_buf_dma_pref; |
1704 | nand_chip->write_buf = omap_write_buf_dma_pref; | |
1b0b323c SG |
1705 | } |
1706 | break; | |
1707 | ||
4e070376 | 1708 | case NAND_OMAP_PREFETCH_IRQ: |
5c468455 AM |
1709 | info->gpmc_irq_fifo = platform_get_irq(pdev, 0); |
1710 | if (info->gpmc_irq_fifo <= 0) { | |
1711 | dev_err(&pdev->dev, "error getting fifo irq\n"); | |
1712 | err = -ENODEV; | |
70ba6d71 | 1713 | goto return_error; |
5c468455 | 1714 | } |
70ba6d71 PG |
1715 | err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo, |
1716 | omap_nand_irq, IRQF_SHARED, | |
1717 | "gpmc-nand-fifo", info); | |
4e070376 SG |
1718 | if (err) { |
1719 | dev_err(&pdev->dev, "requesting irq(%d) error:%d", | |
5c468455 AM |
1720 | info->gpmc_irq_fifo, err); |
1721 | info->gpmc_irq_fifo = 0; | |
70ba6d71 | 1722 | goto return_error; |
5c468455 AM |
1723 | } |
1724 | ||
1725 | info->gpmc_irq_count = platform_get_irq(pdev, 1); | |
1726 | if (info->gpmc_irq_count <= 0) { | |
1727 | dev_err(&pdev->dev, "error getting count irq\n"); | |
1728 | err = -ENODEV; | |
70ba6d71 | 1729 | goto return_error; |
5c468455 | 1730 | } |
70ba6d71 PG |
1731 | err = devm_request_irq(&pdev->dev, info->gpmc_irq_count, |
1732 | omap_nand_irq, IRQF_SHARED, | |
1733 | "gpmc-nand-count", info); | |
5c468455 AM |
1734 | if (err) { |
1735 | dev_err(&pdev->dev, "requesting irq(%d) error:%d", | |
1736 | info->gpmc_irq_count, err); | |
1737 | info->gpmc_irq_count = 0; | |
70ba6d71 | 1738 | goto return_error; |
4e070376 | 1739 | } |
5c468455 | 1740 | |
633deb58 PG |
1741 | nand_chip->read_buf = omap_read_buf_irq_pref; |
1742 | nand_chip->write_buf = omap_write_buf_irq_pref; | |
5c468455 | 1743 | |
4e070376 SG |
1744 | break; |
1745 | ||
1b0b323c SG |
1746 | default: |
1747 | dev_err(&pdev->dev, | |
1748 | "xfer_type(%d) not supported!\n", pdata->xfer_type); | |
1749 | err = -EINVAL; | |
70ba6d71 | 1750 | goto return_error; |
59e9c5ae | 1751 | } |
59e9c5ae | 1752 | |
a919e511 | 1753 | /* populate MTD interface based on ECC scheme */ |
b491da72 PG |
1754 | nand_chip->ecc.layout = &omap_oobinfo; |
1755 | ecclayout = &omap_oobinfo; | |
4e558072 | 1756 | switch (info->ecc_opt) { |
a919e511 PG |
1757 | case OMAP_ECC_HAM1_CODE_HW: |
1758 | pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n"); | |
1759 | nand_chip->ecc.mode = NAND_ECC_HW; | |
633deb58 PG |
1760 | nand_chip->ecc.bytes = 3; |
1761 | nand_chip->ecc.size = 512; | |
1762 | nand_chip->ecc.strength = 1; | |
1763 | nand_chip->ecc.calculate = omap_calculate_ecc; | |
1764 | nand_chip->ecc.hwctl = omap_enable_hwecc; | |
1765 | nand_chip->ecc.correct = omap_correct_data; | |
b491da72 PG |
1766 | /* define ECC layout */ |
1767 | ecclayout->eccbytes = nand_chip->ecc.bytes * | |
1768 | (mtd->writesize / | |
1769 | nand_chip->ecc.size); | |
1770 | if (nand_chip->options & NAND_BUSWIDTH_16) | |
eae39cb4 | 1771 | oob_index = BADBLOCK_MARKER_LENGTH; |
b491da72 | 1772 | else |
eae39cb4 PG |
1773 | oob_index = 1; |
1774 | for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) | |
1775 | ecclayout->eccpos[i] = oob_index; | |
aa6092f9 PG |
1776 | /* no reserved-marker in ecclayout for this ecc-scheme */ |
1777 | ecclayout->oobfree->offset = | |
1778 | ecclayout->eccpos[ecclayout->eccbytes - 1] + 1; | |
a919e511 PG |
1779 | break; |
1780 | ||
1781 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: | |
1782 | #ifdef CONFIG_MTD_NAND_ECC_BCH | |
1783 | pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n"); | |
1784 | nand_chip->ecc.mode = NAND_ECC_HW; | |
1785 | nand_chip->ecc.size = 512; | |
1786 | nand_chip->ecc.bytes = 7; | |
1787 | nand_chip->ecc.strength = 4; | |
7c977c3e | 1788 | nand_chip->ecc.hwctl = omap_enable_hwecc_bch; |
32d42a85 | 1789 | nand_chip->ecc.correct = nand_bch_correct_data; |
2c9f2365 | 1790 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; |
b491da72 PG |
1791 | /* define ECC layout */ |
1792 | ecclayout->eccbytes = nand_chip->ecc.bytes * | |
1793 | (mtd->writesize / | |
1794 | nand_chip->ecc.size); | |
eae39cb4 PG |
1795 | oob_index = BADBLOCK_MARKER_LENGTH; |
1796 | for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) { | |
1797 | ecclayout->eccpos[i] = oob_index; | |
1798 | if (((i + 1) % nand_chip->ecc.bytes) == 0) | |
1799 | oob_index++; | |
1800 | } | |
aa6092f9 PG |
1801 | /* include reserved-marker in ecclayout->oobfree calculation */ |
1802 | ecclayout->oobfree->offset = 1 + | |
1803 | ecclayout->eccpos[ecclayout->eccbytes - 1] + 1; | |
a919e511 | 1804 | /* software bch library is used for locating errors */ |
32d42a85 PG |
1805 | nand_chip->ecc.priv = nand_bch_init(mtd, |
1806 | nand_chip->ecc.size, | |
1807 | nand_chip->ecc.bytes, | |
1808 | &nand_chip->ecc.layout); | |
1809 | if (!nand_chip->ecc.priv) { | |
a919e511 | 1810 | pr_err("nand: error: unable to use s/w BCH library\n"); |
0e618ef0 | 1811 | err = -EINVAL; |
a919e511 PG |
1812 | } |
1813 | break; | |
1814 | #else | |
1815 | pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n"); | |
1816 | err = -EINVAL; | |
70ba6d71 | 1817 | goto return_error; |
a919e511 PG |
1818 | #endif |
1819 | ||
1820 | case OMAP_ECC_BCH4_CODE_HW: | |
1821 | #ifdef CONFIG_MTD_NAND_OMAP_BCH | |
1822 | pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n"); | |
1823 | nand_chip->ecc.mode = NAND_ECC_HW; | |
1824 | nand_chip->ecc.size = 512; | |
1825 | /* 14th bit is kept reserved for ROM-code compatibility */ | |
1826 | nand_chip->ecc.bytes = 7 + 1; | |
1827 | nand_chip->ecc.strength = 4; | |
7c977c3e | 1828 | nand_chip->ecc.hwctl = omap_enable_hwecc_bch; |
a919e511 | 1829 | nand_chip->ecc.correct = omap_elm_correct_data; |
a4c7ca00 | 1830 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; |
a919e511 PG |
1831 | nand_chip->ecc.read_page = omap_read_page_bch; |
1832 | nand_chip->ecc.write_page = omap_write_page_bch; | |
b491da72 PG |
1833 | /* define ECC layout */ |
1834 | ecclayout->eccbytes = nand_chip->ecc.bytes * | |
1835 | (mtd->writesize / | |
1836 | nand_chip->ecc.size); | |
eae39cb4 PG |
1837 | oob_index = BADBLOCK_MARKER_LENGTH; |
1838 | for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) | |
1839 | ecclayout->eccpos[i] = oob_index; | |
aa6092f9 PG |
1840 | /* reserved marker already included in ecclayout->eccbytes */ |
1841 | ecclayout->oobfree->offset = | |
1842 | ecclayout->eccpos[ecclayout->eccbytes - 1] + 1; | |
a919e511 PG |
1843 | /* This ECC scheme requires ELM H/W block */ |
1844 | if (is_elm_present(info, pdata->elm_of_node, BCH4_ECC) < 0) { | |
1845 | pr_err("nand: error: could not initialize ELM\n"); | |
1846 | err = -ENODEV; | |
70ba6d71 | 1847 | goto return_error; |
0e618ef0 | 1848 | } |
a919e511 PG |
1849 | break; |
1850 | #else | |
1851 | pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n"); | |
1852 | err = -EINVAL; | |
70ba6d71 | 1853 | goto return_error; |
a919e511 PG |
1854 | #endif |
1855 | ||
1856 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | |
1857 | #ifdef CONFIG_MTD_NAND_ECC_BCH | |
1858 | pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n"); | |
1859 | nand_chip->ecc.mode = NAND_ECC_HW; | |
1860 | nand_chip->ecc.size = 512; | |
1861 | nand_chip->ecc.bytes = 13; | |
1862 | nand_chip->ecc.strength = 8; | |
7c977c3e | 1863 | nand_chip->ecc.hwctl = omap_enable_hwecc_bch; |
32d42a85 | 1864 | nand_chip->ecc.correct = nand_bch_correct_data; |
7bcd1dca | 1865 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; |
b491da72 PG |
1866 | /* define ECC layout */ |
1867 | ecclayout->eccbytes = nand_chip->ecc.bytes * | |
1868 | (mtd->writesize / | |
1869 | nand_chip->ecc.size); | |
eae39cb4 PG |
1870 | oob_index = BADBLOCK_MARKER_LENGTH; |
1871 | for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) { | |
1872 | ecclayout->eccpos[i] = oob_index; | |
1873 | if (((i + 1) % nand_chip->ecc.bytes) == 0) | |
1874 | oob_index++; | |
1875 | } | |
aa6092f9 PG |
1876 | /* include reserved-marker in ecclayout->oobfree calculation */ |
1877 | ecclayout->oobfree->offset = 1 + | |
1878 | ecclayout->eccpos[ecclayout->eccbytes - 1] + 1; | |
a919e511 | 1879 | /* software bch library is used for locating errors */ |
32d42a85 PG |
1880 | nand_chip->ecc.priv = nand_bch_init(mtd, |
1881 | nand_chip->ecc.size, | |
1882 | nand_chip->ecc.bytes, | |
1883 | &nand_chip->ecc.layout); | |
1884 | if (!nand_chip->ecc.priv) { | |
a919e511 PG |
1885 | pr_err("nand: error: unable to use s/w BCH library\n"); |
1886 | err = -EINVAL; | |
70ba6d71 | 1887 | goto return_error; |
a919e511 PG |
1888 | } |
1889 | break; | |
1890 | #else | |
1891 | pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n"); | |
1892 | err = -EINVAL; | |
70ba6d71 | 1893 | goto return_error; |
a919e511 PG |
1894 | #endif |
1895 | ||
1896 | case OMAP_ECC_BCH8_CODE_HW: | |
1897 | #ifdef CONFIG_MTD_NAND_OMAP_BCH | |
1898 | pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n"); | |
1899 | nand_chip->ecc.mode = NAND_ECC_HW; | |
1900 | nand_chip->ecc.size = 512; | |
1901 | /* 14th bit is kept reserved for ROM-code compatibility */ | |
1902 | nand_chip->ecc.bytes = 13 + 1; | |
1903 | nand_chip->ecc.strength = 8; | |
7c977c3e | 1904 | nand_chip->ecc.hwctl = omap_enable_hwecc_bch; |
a919e511 | 1905 | nand_chip->ecc.correct = omap_elm_correct_data; |
a4c7ca00 | 1906 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; |
a919e511 PG |
1907 | nand_chip->ecc.read_page = omap_read_page_bch; |
1908 | nand_chip->ecc.write_page = omap_write_page_bch; | |
1909 | /* This ECC scheme requires ELM H/W block */ | |
9211439b WY |
1910 | err = is_elm_present(info, pdata->elm_of_node, BCH8_ECC); |
1911 | if (err < 0) { | |
a919e511 | 1912 | pr_err("nand: error: could not initialize ELM\n"); |
70ba6d71 | 1913 | goto return_error; |
a919e511 | 1914 | } |
b491da72 PG |
1915 | /* define ECC layout */ |
1916 | ecclayout->eccbytes = nand_chip->ecc.bytes * | |
1917 | (mtd->writesize / | |
1918 | nand_chip->ecc.size); | |
eae39cb4 PG |
1919 | oob_index = BADBLOCK_MARKER_LENGTH; |
1920 | for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) | |
1921 | ecclayout->eccpos[i] = oob_index; | |
aa6092f9 PG |
1922 | /* reserved marker already included in ecclayout->eccbytes */ |
1923 | ecclayout->oobfree->offset = | |
1924 | ecclayout->eccpos[ecclayout->eccbytes - 1] + 1; | |
a919e511 PG |
1925 | break; |
1926 | #else | |
1927 | pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n"); | |
1928 | err = -EINVAL; | |
70ba6d71 | 1929 | goto return_error; |
a919e511 PG |
1930 | #endif |
1931 | ||
1932 | default: | |
1933 | pr_err("nand: error: invalid or unsupported ECC scheme\n"); | |
1934 | err = -EINVAL; | |
70ba6d71 | 1935 | goto return_error; |
f3d73f36 | 1936 | } |
67ce04bf | 1937 | |
bb38eefb PG |
1938 | /* all OOB bytes from oobfree->offset till end off OOB are free */ |
1939 | ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset; | |
b491da72 PG |
1940 | /* check if NAND device's OOB is enough to store ECC signatures */ |
1941 | if (mtd->oobsize < (ecclayout->eccbytes + BADBLOCK_MARKER_LENGTH)) { | |
1942 | pr_err("not enough OOB bytes required = %d, available=%d\n", | |
1943 | ecclayout->eccbytes, mtd->oobsize); | |
1944 | err = -EINVAL; | |
70ba6d71 | 1945 | goto return_error; |
f040d332 | 1946 | } |
1b0b323c | 1947 | |
a80f1c1f | 1948 | /* second phase scan */ |
633deb58 | 1949 | if (nand_scan_tail(mtd)) { |
a80f1c1f | 1950 | err = -ENXIO; |
70ba6d71 | 1951 | goto return_error; |
a80f1c1f JW |
1952 | } |
1953 | ||
ccf04c51 | 1954 | ppdata.of_node = pdata->of_node; |
633deb58 | 1955 | mtd_device_parse_register(mtd, NULL, &ppdata, pdata->parts, |
42d7fbe2 | 1956 | pdata->nr_parts); |
67ce04bf | 1957 | |
633deb58 | 1958 | platform_set_drvdata(pdev, mtd); |
67ce04bf VS |
1959 | |
1960 | return 0; | |
1961 | ||
70ba6d71 | 1962 | return_error: |
763e7359 RK |
1963 | if (info->dma) |
1964 | dma_release_channel(info->dma); | |
32d42a85 PG |
1965 | if (nand_chip->ecc.priv) { |
1966 | nand_bch_free(nand_chip->ecc.priv); | |
1967 | nand_chip->ecc.priv = NULL; | |
1968 | } | |
67ce04bf VS |
1969 | return err; |
1970 | } | |
1971 | ||
1972 | static int omap_nand_remove(struct platform_device *pdev) | |
1973 | { | |
1974 | struct mtd_info *mtd = platform_get_drvdata(pdev); | |
633deb58 | 1975 | struct nand_chip *nand_chip = mtd->priv; |
f35b6eda VS |
1976 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
1977 | mtd); | |
32d42a85 PG |
1978 | if (nand_chip->ecc.priv) { |
1979 | nand_bch_free(nand_chip->ecc.priv); | |
1980 | nand_chip->ecc.priv = NULL; | |
1981 | } | |
763e7359 RK |
1982 | if (info->dma) |
1983 | dma_release_channel(info->dma); | |
633deb58 | 1984 | nand_release(mtd); |
67ce04bf VS |
1985 | return 0; |
1986 | } | |
1987 | ||
1988 | static struct platform_driver omap_nand_driver = { | |
1989 | .probe = omap_nand_probe, | |
1990 | .remove = omap_nand_remove, | |
1991 | .driver = { | |
1992 | .name = DRIVER_NAME, | |
1993 | .owner = THIS_MODULE, | |
1994 | }, | |
1995 | }; | |
1996 | ||
f99640de | 1997 | module_platform_driver(omap_nand_driver); |
67ce04bf | 1998 | |
c804c733 | 1999 | MODULE_ALIAS("platform:" DRIVER_NAME); |
67ce04bf VS |
2000 | MODULE_LICENSE("GPL"); |
2001 | MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards"); |