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67ce04bf VS |
1 | /* |
2 | * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com> | |
3 | * Copyright © 2004 Micron Technology Inc. | |
4 | * Copyright © 2004 David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/platform_device.h> | |
763e7359 | 12 | #include <linux/dmaengine.h> |
67ce04bf VS |
13 | #include <linux/dma-mapping.h> |
14 | #include <linux/delay.h> | |
a0e5cc58 | 15 | #include <linux/module.h> |
4e070376 | 16 | #include <linux/interrupt.h> |
c276aca4 | 17 | #include <linux/jiffies.h> |
18 | #include <linux/sched.h> | |
67ce04bf VS |
19 | #include <linux/mtd/mtd.h> |
20 | #include <linux/mtd/nand.h> | |
21 | #include <linux/mtd/partitions.h> | |
763e7359 | 22 | #include <linux/omap-dma.h> |
67ce04bf | 23 | #include <linux/io.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
62116e51 PA |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
67ce04bf | 27 | |
32d42a85 | 28 | #include <linux/mtd/nand_bch.h> |
62116e51 | 29 | #include <linux/platform_data/elm.h> |
0e618ef0 | 30 | |
2203747c | 31 | #include <linux/platform_data/mtd-nand-omap2.h> |
67ce04bf | 32 | |
67ce04bf | 33 | #define DRIVER_NAME "omap2-nand" |
4e070376 | 34 | #define OMAP_NAND_TIMEOUT_MS 5000 |
67ce04bf | 35 | |
67ce04bf VS |
36 | #define NAND_Ecc_P1e (1 << 0) |
37 | #define NAND_Ecc_P2e (1 << 1) | |
38 | #define NAND_Ecc_P4e (1 << 2) | |
39 | #define NAND_Ecc_P8e (1 << 3) | |
40 | #define NAND_Ecc_P16e (1 << 4) | |
41 | #define NAND_Ecc_P32e (1 << 5) | |
42 | #define NAND_Ecc_P64e (1 << 6) | |
43 | #define NAND_Ecc_P128e (1 << 7) | |
44 | #define NAND_Ecc_P256e (1 << 8) | |
45 | #define NAND_Ecc_P512e (1 << 9) | |
46 | #define NAND_Ecc_P1024e (1 << 10) | |
47 | #define NAND_Ecc_P2048e (1 << 11) | |
48 | ||
49 | #define NAND_Ecc_P1o (1 << 16) | |
50 | #define NAND_Ecc_P2o (1 << 17) | |
51 | #define NAND_Ecc_P4o (1 << 18) | |
52 | #define NAND_Ecc_P8o (1 << 19) | |
53 | #define NAND_Ecc_P16o (1 << 20) | |
54 | #define NAND_Ecc_P32o (1 << 21) | |
55 | #define NAND_Ecc_P64o (1 << 22) | |
56 | #define NAND_Ecc_P128o (1 << 23) | |
57 | #define NAND_Ecc_P256o (1 << 24) | |
58 | #define NAND_Ecc_P512o (1 << 25) | |
59 | #define NAND_Ecc_P1024o (1 << 26) | |
60 | #define NAND_Ecc_P2048o (1 << 27) | |
61 | ||
62 | #define TF(value) (value ? 1 : 0) | |
63 | ||
64 | #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0) | |
65 | #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1) | |
66 | #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2) | |
67 | #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3) | |
68 | #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4) | |
69 | #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5) | |
70 | #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6) | |
71 | #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7) | |
72 | ||
73 | #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0) | |
74 | #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1) | |
75 | #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2) | |
76 | #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3) | |
77 | #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4) | |
78 | #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5) | |
79 | #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6) | |
80 | #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7) | |
81 | ||
82 | #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0) | |
83 | #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1) | |
84 | #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2) | |
85 | #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3) | |
86 | #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4) | |
87 | #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5) | |
88 | #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6) | |
89 | #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7) | |
90 | ||
91 | #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0) | |
92 | #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1) | |
93 | #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2) | |
94 | #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3) | |
95 | #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4) | |
96 | #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5) | |
97 | #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6) | |
98 | #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7) | |
99 | ||
100 | #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) | |
101 | #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) | |
102 | ||
65b97cf6 AM |
103 | #define PREFETCH_CONFIG1_CS_SHIFT 24 |
104 | #define ECC_CONFIG_CS_SHIFT 1 | |
105 | #define CS_MASK 0x7 | |
106 | #define ENABLE_PREFETCH (0x1 << 7) | |
107 | #define DMA_MPU_MODE_SHIFT 2 | |
2ef9f3dd | 108 | #define ECCSIZE0_SHIFT 12 |
65b97cf6 AM |
109 | #define ECCSIZE1_SHIFT 22 |
110 | #define ECC1RESULTSIZE 0x1 | |
111 | #define ECCCLEAR 0x100 | |
112 | #define ECC1 0x1 | |
47f88af4 AM |
113 | #define PREFETCH_FIFOTHRESHOLD_MAX 0x40 |
114 | #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) | |
115 | #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) | |
116 | #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) | |
117 | #define STATUS_BUFF_EMPTY 0x00000001 | |
65b97cf6 | 118 | |
d5e7c864 LV |
119 | #define OMAP24XX_DMA_GPMC 4 |
120 | ||
62116e51 PA |
121 | #define SECTOR_BYTES 512 |
122 | /* 4 bit padding to make byte aligned, 56 = 52 + 4 */ | |
123 | #define BCH4_BIT_PAD 4 | |
62116e51 PA |
124 | |
125 | /* GPMC ecc engine settings for read */ | |
126 | #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */ | |
127 | #define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */ | |
128 | #define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */ | |
129 | #define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */ | |
130 | #define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */ | |
131 | ||
132 | /* GPMC ecc engine settings for write */ | |
133 | #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */ | |
134 | #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */ | |
135 | #define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */ | |
136 | ||
b491da72 | 137 | #define BADBLOCK_MARKER_LENGTH 2 |
a919e511 | 138 | |
62116e51 PA |
139 | #ifdef CONFIG_MTD_NAND_OMAP_BCH |
140 | static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc, | |
141 | 0xac, 0x6b, 0xff, 0x99, 0x7b}; | |
142 | static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10}; | |
143 | #endif | |
144 | ||
f040d332 SG |
145 | /* oob info generated runtime depending on ecc algorithm and layout selected */ |
146 | static struct nand_ecclayout omap_oobinfo; | |
59e9c5ae | 147 | |
67ce04bf VS |
148 | struct omap_nand_info { |
149 | struct nand_hw_control controller; | |
150 | struct omap_nand_platform_data *pdata; | |
151 | struct mtd_info mtd; | |
67ce04bf VS |
152 | struct nand_chip nand; |
153 | struct platform_device *pdev; | |
154 | ||
155 | int gpmc_cs; | |
156 | unsigned long phys_base; | |
9c4c2f8b | 157 | unsigned long mem_size; |
4e558072 | 158 | enum omap_ecc ecc_opt; |
dfe32893 | 159 | struct completion comp; |
763e7359 | 160 | struct dma_chan *dma; |
5c468455 AM |
161 | int gpmc_irq_fifo; |
162 | int gpmc_irq_count; | |
4e070376 SG |
163 | enum { |
164 | OMAP_NAND_IO_READ = 0, /* read */ | |
165 | OMAP_NAND_IO_WRITE, /* write */ | |
166 | } iomode; | |
167 | u_char *buf; | |
168 | int buf_len; | |
65b97cf6 | 169 | struct gpmc_nand_regs reg; |
a919e511 | 170 | /* fields specific for BCHx_HW ECC scheme */ |
62116e51 PA |
171 | bool is_elm_used; |
172 | struct device *elm_dev; | |
173 | struct device_node *of_node; | |
67ce04bf VS |
174 | }; |
175 | ||
65b97cf6 AM |
176 | /** |
177 | * omap_prefetch_enable - configures and starts prefetch transfer | |
178 | * @cs: cs (chip select) number | |
179 | * @fifo_th: fifo threshold to be used for read/ write | |
180 | * @dma_mode: dma mode enable (1) or disable (0) | |
181 | * @u32_count: number of bytes to be transferred | |
182 | * @is_write: prefetch read(0) or write post(1) mode | |
183 | */ | |
184 | static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode, | |
185 | unsigned int u32_count, int is_write, struct omap_nand_info *info) | |
186 | { | |
187 | u32 val; | |
188 | ||
189 | if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) | |
190 | return -1; | |
191 | ||
192 | if (readl(info->reg.gpmc_prefetch_control)) | |
193 | return -EBUSY; | |
194 | ||
195 | /* Set the amount of bytes to be prefetched */ | |
196 | writel(u32_count, info->reg.gpmc_prefetch_config2); | |
197 | ||
198 | /* Set dma/mpu mode, the prefetch read / post write and | |
199 | * enable the engine. Set which cs is has requested for. | |
200 | */ | |
201 | val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) | | |
202 | PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH | | |
203 | (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write)); | |
204 | writel(val, info->reg.gpmc_prefetch_config1); | |
205 | ||
206 | /* Start the prefetch engine */ | |
207 | writel(0x1, info->reg.gpmc_prefetch_control); | |
208 | ||
209 | return 0; | |
210 | } | |
211 | ||
212 | /** | |
213 | * omap_prefetch_reset - disables and stops the prefetch engine | |
214 | */ | |
215 | static int omap_prefetch_reset(int cs, struct omap_nand_info *info) | |
216 | { | |
217 | u32 config1; | |
218 | ||
219 | /* check if the same module/cs is trying to reset */ | |
220 | config1 = readl(info->reg.gpmc_prefetch_config1); | |
221 | if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs) | |
222 | return -EINVAL; | |
223 | ||
224 | /* Stop the PFPW engine */ | |
225 | writel(0x0, info->reg.gpmc_prefetch_control); | |
226 | ||
227 | /* Reset/disable the PFPW engine */ | |
228 | writel(0x0, info->reg.gpmc_prefetch_config1); | |
229 | ||
230 | return 0; | |
231 | } | |
232 | ||
67ce04bf VS |
233 | /** |
234 | * omap_hwcontrol - hardware specific access to control-lines | |
235 | * @mtd: MTD device structure | |
236 | * @cmd: command to device | |
237 | * @ctrl: | |
238 | * NAND_NCE: bit 0 -> don't care | |
239 | * NAND_CLE: bit 1 -> Command Latch | |
240 | * NAND_ALE: bit 2 -> Address Latch | |
241 | * | |
242 | * NOTE: boards may use different bits for these!! | |
243 | */ | |
244 | static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
245 | { | |
246 | struct omap_nand_info *info = container_of(mtd, | |
247 | struct omap_nand_info, mtd); | |
67ce04bf | 248 | |
2c01946c SG |
249 | if (cmd != NAND_CMD_NONE) { |
250 | if (ctrl & NAND_CLE) | |
65b97cf6 | 251 | writeb(cmd, info->reg.gpmc_nand_command); |
2c01946c SG |
252 | |
253 | else if (ctrl & NAND_ALE) | |
65b97cf6 | 254 | writeb(cmd, info->reg.gpmc_nand_address); |
2c01946c SG |
255 | |
256 | else /* NAND_NCE */ | |
65b97cf6 | 257 | writeb(cmd, info->reg.gpmc_nand_data); |
2c01946c | 258 | } |
67ce04bf VS |
259 | } |
260 | ||
59e9c5ae | 261 | /** |
262 | * omap_read_buf8 - read data from NAND controller into buffer | |
263 | * @mtd: MTD device structure | |
264 | * @buf: buffer to store date | |
265 | * @len: number of bytes to read | |
266 | */ | |
267 | static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len) | |
268 | { | |
269 | struct nand_chip *nand = mtd->priv; | |
270 | ||
271 | ioread8_rep(nand->IO_ADDR_R, buf, len); | |
272 | } | |
273 | ||
274 | /** | |
275 | * omap_write_buf8 - write buffer to NAND controller | |
276 | * @mtd: MTD device structure | |
277 | * @buf: data buffer | |
278 | * @len: number of bytes to write | |
279 | */ | |
280 | static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len) | |
281 | { | |
282 | struct omap_nand_info *info = container_of(mtd, | |
283 | struct omap_nand_info, mtd); | |
284 | u_char *p = (u_char *)buf; | |
2c01946c | 285 | u32 status = 0; |
59e9c5ae | 286 | |
287 | while (len--) { | |
288 | iowrite8(*p++, info->nand.IO_ADDR_W); | |
2c01946c SG |
289 | /* wait until buffer is available for write */ |
290 | do { | |
65b97cf6 | 291 | status = readl(info->reg.gpmc_status) & |
47f88af4 | 292 | STATUS_BUFF_EMPTY; |
2c01946c | 293 | } while (!status); |
59e9c5ae | 294 | } |
295 | } | |
296 | ||
67ce04bf VS |
297 | /** |
298 | * omap_read_buf16 - read data from NAND controller into buffer | |
299 | * @mtd: MTD device structure | |
300 | * @buf: buffer to store date | |
301 | * @len: number of bytes to read | |
302 | */ | |
303 | static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len) | |
304 | { | |
305 | struct nand_chip *nand = mtd->priv; | |
306 | ||
59e9c5ae | 307 | ioread16_rep(nand->IO_ADDR_R, buf, len / 2); |
67ce04bf VS |
308 | } |
309 | ||
310 | /** | |
311 | * omap_write_buf16 - write buffer to NAND controller | |
312 | * @mtd: MTD device structure | |
313 | * @buf: data buffer | |
314 | * @len: number of bytes to write | |
315 | */ | |
316 | static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len) | |
317 | { | |
318 | struct omap_nand_info *info = container_of(mtd, | |
319 | struct omap_nand_info, mtd); | |
320 | u16 *p = (u16 *) buf; | |
2c01946c | 321 | u32 status = 0; |
67ce04bf VS |
322 | /* FIXME try bursts of writesw() or DMA ... */ |
323 | len >>= 1; | |
324 | ||
325 | while (len--) { | |
59e9c5ae | 326 | iowrite16(*p++, info->nand.IO_ADDR_W); |
2c01946c SG |
327 | /* wait until buffer is available for write */ |
328 | do { | |
65b97cf6 | 329 | status = readl(info->reg.gpmc_status) & |
47f88af4 | 330 | STATUS_BUFF_EMPTY; |
2c01946c | 331 | } while (!status); |
67ce04bf VS |
332 | } |
333 | } | |
59e9c5ae | 334 | |
335 | /** | |
336 | * omap_read_buf_pref - read data from NAND controller into buffer | |
337 | * @mtd: MTD device structure | |
338 | * @buf: buffer to store date | |
339 | * @len: number of bytes to read | |
340 | */ | |
341 | static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) | |
342 | { | |
343 | struct omap_nand_info *info = container_of(mtd, | |
344 | struct omap_nand_info, mtd); | |
2c01946c | 345 | uint32_t r_count = 0; |
59e9c5ae | 346 | int ret = 0; |
347 | u32 *p = (u32 *)buf; | |
348 | ||
349 | /* take care of subpage reads */ | |
c3341d0c VS |
350 | if (len % 4) { |
351 | if (info->nand.options & NAND_BUSWIDTH_16) | |
352 | omap_read_buf16(mtd, buf, len % 4); | |
353 | else | |
354 | omap_read_buf8(mtd, buf, len % 4); | |
355 | p = (u32 *) (buf + len % 4); | |
356 | len -= len % 4; | |
59e9c5ae | 357 | } |
59e9c5ae | 358 | |
359 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
360 | ret = omap_prefetch_enable(info->gpmc_cs, |
361 | PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info); | |
59e9c5ae | 362 | if (ret) { |
363 | /* PFPW engine is busy, use cpu copy method */ | |
364 | if (info->nand.options & NAND_BUSWIDTH_16) | |
c5d8c0ca | 365 | omap_read_buf16(mtd, (u_char *)p, len); |
59e9c5ae | 366 | else |
c5d8c0ca | 367 | omap_read_buf8(mtd, (u_char *)p, len); |
59e9c5ae | 368 | } else { |
369 | do { | |
65b97cf6 | 370 | r_count = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 371 | r_count = PREFETCH_STATUS_FIFO_CNT(r_count); |
2c01946c SG |
372 | r_count = r_count >> 2; |
373 | ioread32_rep(info->nand.IO_ADDR_R, p, r_count); | |
59e9c5ae | 374 | p += r_count; |
375 | len -= r_count << 2; | |
376 | } while (len); | |
59e9c5ae | 377 | /* disable and stop the PFPW engine */ |
65b97cf6 | 378 | omap_prefetch_reset(info->gpmc_cs, info); |
59e9c5ae | 379 | } |
380 | } | |
381 | ||
382 | /** | |
383 | * omap_write_buf_pref - write buffer to NAND controller | |
384 | * @mtd: MTD device structure | |
385 | * @buf: data buffer | |
386 | * @len: number of bytes to write | |
387 | */ | |
388 | static void omap_write_buf_pref(struct mtd_info *mtd, | |
389 | const u_char *buf, int len) | |
390 | { | |
391 | struct omap_nand_info *info = container_of(mtd, | |
392 | struct omap_nand_info, mtd); | |
4e070376 | 393 | uint32_t w_count = 0; |
59e9c5ae | 394 | int i = 0, ret = 0; |
c5d8c0ca | 395 | u16 *p = (u16 *)buf; |
4e070376 | 396 | unsigned long tim, limit; |
65b97cf6 | 397 | u32 val; |
59e9c5ae | 398 | |
399 | /* take care of subpage writes */ | |
400 | if (len % 2 != 0) { | |
2c01946c | 401 | writeb(*buf, info->nand.IO_ADDR_W); |
59e9c5ae | 402 | p = (u16 *)(buf + 1); |
403 | len--; | |
404 | } | |
405 | ||
406 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
407 | ret = omap_prefetch_enable(info->gpmc_cs, |
408 | PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info); | |
59e9c5ae | 409 | if (ret) { |
410 | /* PFPW engine is busy, use cpu copy method */ | |
411 | if (info->nand.options & NAND_BUSWIDTH_16) | |
c5d8c0ca | 412 | omap_write_buf16(mtd, (u_char *)p, len); |
59e9c5ae | 413 | else |
c5d8c0ca | 414 | omap_write_buf8(mtd, (u_char *)p, len); |
59e9c5ae | 415 | } else { |
2c01946c | 416 | while (len) { |
65b97cf6 | 417 | w_count = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 418 | w_count = PREFETCH_STATUS_FIFO_CNT(w_count); |
2c01946c | 419 | w_count = w_count >> 1; |
59e9c5ae | 420 | for (i = 0; (i < w_count) && len; i++, len -= 2) |
2c01946c | 421 | iowrite16(*p++, info->nand.IO_ADDR_W); |
59e9c5ae | 422 | } |
2c01946c | 423 | /* wait for data to flushed-out before reset the prefetch */ |
4e070376 SG |
424 | tim = 0; |
425 | limit = (loops_per_jiffy * | |
426 | msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 | 427 | do { |
4e070376 | 428 | cpu_relax(); |
65b97cf6 | 429 | val = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 430 | val = PREFETCH_STATUS_COUNT(val); |
65b97cf6 | 431 | } while (val && (tim++ < limit)); |
4e070376 | 432 | |
59e9c5ae | 433 | /* disable and stop the PFPW engine */ |
65b97cf6 | 434 | omap_prefetch_reset(info->gpmc_cs, info); |
59e9c5ae | 435 | } |
436 | } | |
437 | ||
dfe32893 | 438 | /* |
2df41d05 | 439 | * omap_nand_dma_callback: callback on the completion of dma transfer |
dfe32893 | 440 | * @data: pointer to completion data structure |
441 | */ | |
763e7359 RK |
442 | static void omap_nand_dma_callback(void *data) |
443 | { | |
444 | complete((struct completion *) data); | |
445 | } | |
dfe32893 | 446 | |
447 | /* | |
4cacbe22 | 448 | * omap_nand_dma_transfer: configure and start dma transfer |
dfe32893 | 449 | * @mtd: MTD device structure |
450 | * @addr: virtual address in RAM of source/destination | |
451 | * @len: number of data bytes to be transferred | |
452 | * @is_write: flag for read/write operation | |
453 | */ | |
454 | static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, | |
455 | unsigned int len, int is_write) | |
456 | { | |
457 | struct omap_nand_info *info = container_of(mtd, | |
458 | struct omap_nand_info, mtd); | |
2df41d05 | 459 | struct dma_async_tx_descriptor *tx; |
dfe32893 | 460 | enum dma_data_direction dir = is_write ? DMA_TO_DEVICE : |
461 | DMA_FROM_DEVICE; | |
2df41d05 | 462 | struct scatterlist sg; |
4e070376 | 463 | unsigned long tim, limit; |
2df41d05 RK |
464 | unsigned n; |
465 | int ret; | |
65b97cf6 | 466 | u32 val; |
dfe32893 | 467 | |
468 | if (addr >= high_memory) { | |
469 | struct page *p1; | |
470 | ||
471 | if (((size_t)addr & PAGE_MASK) != | |
472 | ((size_t)(addr + len - 1) & PAGE_MASK)) | |
473 | goto out_copy; | |
474 | p1 = vmalloc_to_page(addr); | |
475 | if (!p1) | |
476 | goto out_copy; | |
477 | addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK); | |
478 | } | |
479 | ||
2df41d05 RK |
480 | sg_init_one(&sg, addr, len); |
481 | n = dma_map_sg(info->dma->device->dev, &sg, 1, dir); | |
482 | if (n == 0) { | |
dfe32893 | 483 | dev_err(&info->pdev->dev, |
484 | "Couldn't DMA map a %d byte buffer\n", len); | |
485 | goto out_copy; | |
486 | } | |
487 | ||
2df41d05 RK |
488 | tx = dmaengine_prep_slave_sg(info->dma, &sg, n, |
489 | is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, | |
490 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
491 | if (!tx) | |
492 | goto out_copy_unmap; | |
493 | ||
494 | tx->callback = omap_nand_dma_callback; | |
495 | tx->callback_param = &info->comp; | |
496 | dmaengine_submit(tx); | |
497 | ||
65b97cf6 AM |
498 | /* configure and start prefetch transfer */ |
499 | ret = omap_prefetch_enable(info->gpmc_cs, | |
500 | PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info); | |
dfe32893 | 501 | if (ret) |
4e070376 | 502 | /* PFPW engine is busy, use cpu copy method */ |
d7efe228 | 503 | goto out_copy_unmap; |
dfe32893 | 504 | |
505 | init_completion(&info->comp); | |
2df41d05 | 506 | dma_async_issue_pending(info->dma); |
dfe32893 | 507 | |
508 | /* setup and start DMA using dma_addr */ | |
509 | wait_for_completion(&info->comp); | |
4e070376 SG |
510 | tim = 0; |
511 | limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 AM |
512 | |
513 | do { | |
4e070376 | 514 | cpu_relax(); |
65b97cf6 | 515 | val = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 516 | val = PREFETCH_STATUS_COUNT(val); |
65b97cf6 | 517 | } while (val && (tim++ < limit)); |
dfe32893 | 518 | |
dfe32893 | 519 | /* disable and stop the PFPW engine */ |
65b97cf6 | 520 | omap_prefetch_reset(info->gpmc_cs, info); |
dfe32893 | 521 | |
2df41d05 | 522 | dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); |
dfe32893 | 523 | return 0; |
524 | ||
d7efe228 | 525 | out_copy_unmap: |
2df41d05 | 526 | dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); |
dfe32893 | 527 | out_copy: |
528 | if (info->nand.options & NAND_BUSWIDTH_16) | |
529 | is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len) | |
530 | : omap_write_buf16(mtd, (u_char *) addr, len); | |
531 | else | |
532 | is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len) | |
533 | : omap_write_buf8(mtd, (u_char *) addr, len); | |
534 | return 0; | |
535 | } | |
dfe32893 | 536 | |
537 | /** | |
538 | * omap_read_buf_dma_pref - read data from NAND controller into buffer | |
539 | * @mtd: MTD device structure | |
540 | * @buf: buffer to store date | |
541 | * @len: number of bytes to read | |
542 | */ | |
543 | static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len) | |
544 | { | |
545 | if (len <= mtd->oobsize) | |
546 | omap_read_buf_pref(mtd, buf, len); | |
547 | else | |
548 | /* start transfer in DMA mode */ | |
549 | omap_nand_dma_transfer(mtd, buf, len, 0x0); | |
550 | } | |
551 | ||
552 | /** | |
553 | * omap_write_buf_dma_pref - write buffer to NAND controller | |
554 | * @mtd: MTD device structure | |
555 | * @buf: data buffer | |
556 | * @len: number of bytes to write | |
557 | */ | |
558 | static void omap_write_buf_dma_pref(struct mtd_info *mtd, | |
559 | const u_char *buf, int len) | |
560 | { | |
561 | if (len <= mtd->oobsize) | |
562 | omap_write_buf_pref(mtd, buf, len); | |
563 | else | |
564 | /* start transfer in DMA mode */ | |
bdaefc41 | 565 | omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1); |
dfe32893 | 566 | } |
567 | ||
4e070376 | 568 | /* |
4cacbe22 | 569 | * omap_nand_irq - GPMC irq handler |
4e070376 SG |
570 | * @this_irq: gpmc irq number |
571 | * @dev: omap_nand_info structure pointer is passed here | |
572 | */ | |
573 | static irqreturn_t omap_nand_irq(int this_irq, void *dev) | |
574 | { | |
575 | struct omap_nand_info *info = (struct omap_nand_info *) dev; | |
576 | u32 bytes; | |
4e070376 | 577 | |
65b97cf6 | 578 | bytes = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 579 | bytes = PREFETCH_STATUS_FIFO_CNT(bytes); |
4e070376 SG |
580 | bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ |
581 | if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ | |
5c468455 | 582 | if (this_irq == info->gpmc_irq_count) |
4e070376 SG |
583 | goto done; |
584 | ||
585 | if (info->buf_len && (info->buf_len < bytes)) | |
586 | bytes = info->buf_len; | |
587 | else if (!info->buf_len) | |
588 | bytes = 0; | |
589 | iowrite32_rep(info->nand.IO_ADDR_W, | |
590 | (u32 *)info->buf, bytes >> 2); | |
591 | info->buf = info->buf + bytes; | |
592 | info->buf_len -= bytes; | |
593 | ||
594 | } else { | |
595 | ioread32_rep(info->nand.IO_ADDR_R, | |
596 | (u32 *)info->buf, bytes >> 2); | |
597 | info->buf = info->buf + bytes; | |
598 | ||
5c468455 | 599 | if (this_irq == info->gpmc_irq_count) |
4e070376 SG |
600 | goto done; |
601 | } | |
4e070376 SG |
602 | |
603 | return IRQ_HANDLED; | |
604 | ||
605 | done: | |
606 | complete(&info->comp); | |
4e070376 | 607 | |
5c468455 AM |
608 | disable_irq_nosync(info->gpmc_irq_fifo); |
609 | disable_irq_nosync(info->gpmc_irq_count); | |
4e070376 SG |
610 | |
611 | return IRQ_HANDLED; | |
612 | } | |
613 | ||
614 | /* | |
615 | * omap_read_buf_irq_pref - read data from NAND controller into buffer | |
616 | * @mtd: MTD device structure | |
617 | * @buf: buffer to store date | |
618 | * @len: number of bytes to read | |
619 | */ | |
620 | static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) | |
621 | { | |
622 | struct omap_nand_info *info = container_of(mtd, | |
623 | struct omap_nand_info, mtd); | |
624 | int ret = 0; | |
625 | ||
626 | if (len <= mtd->oobsize) { | |
627 | omap_read_buf_pref(mtd, buf, len); | |
628 | return; | |
629 | } | |
630 | ||
631 | info->iomode = OMAP_NAND_IO_READ; | |
632 | info->buf = buf; | |
633 | init_completion(&info->comp); | |
634 | ||
635 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
636 | ret = omap_prefetch_enable(info->gpmc_cs, |
637 | PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info); | |
4e070376 SG |
638 | if (ret) |
639 | /* PFPW engine is busy, use cpu copy method */ | |
640 | goto out_copy; | |
641 | ||
642 | info->buf_len = len; | |
5c468455 AM |
643 | |
644 | enable_irq(info->gpmc_irq_count); | |
645 | enable_irq(info->gpmc_irq_fifo); | |
4e070376 SG |
646 | |
647 | /* waiting for read to complete */ | |
648 | wait_for_completion(&info->comp); | |
649 | ||
650 | /* disable and stop the PFPW engine */ | |
65b97cf6 | 651 | omap_prefetch_reset(info->gpmc_cs, info); |
4e070376 SG |
652 | return; |
653 | ||
654 | out_copy: | |
655 | if (info->nand.options & NAND_BUSWIDTH_16) | |
656 | omap_read_buf16(mtd, buf, len); | |
657 | else | |
658 | omap_read_buf8(mtd, buf, len); | |
659 | } | |
660 | ||
661 | /* | |
662 | * omap_write_buf_irq_pref - write buffer to NAND controller | |
663 | * @mtd: MTD device structure | |
664 | * @buf: data buffer | |
665 | * @len: number of bytes to write | |
666 | */ | |
667 | static void omap_write_buf_irq_pref(struct mtd_info *mtd, | |
668 | const u_char *buf, int len) | |
669 | { | |
670 | struct omap_nand_info *info = container_of(mtd, | |
671 | struct omap_nand_info, mtd); | |
672 | int ret = 0; | |
673 | unsigned long tim, limit; | |
65b97cf6 | 674 | u32 val; |
4e070376 SG |
675 | |
676 | if (len <= mtd->oobsize) { | |
677 | omap_write_buf_pref(mtd, buf, len); | |
678 | return; | |
679 | } | |
680 | ||
681 | info->iomode = OMAP_NAND_IO_WRITE; | |
682 | info->buf = (u_char *) buf; | |
683 | init_completion(&info->comp); | |
684 | ||
317379a9 | 685 | /* configure and start prefetch transfer : size=24 */ |
65b97cf6 AM |
686 | ret = omap_prefetch_enable(info->gpmc_cs, |
687 | (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info); | |
4e070376 SG |
688 | if (ret) |
689 | /* PFPW engine is busy, use cpu copy method */ | |
690 | goto out_copy; | |
691 | ||
692 | info->buf_len = len; | |
5c468455 AM |
693 | |
694 | enable_irq(info->gpmc_irq_count); | |
695 | enable_irq(info->gpmc_irq_fifo); | |
4e070376 SG |
696 | |
697 | /* waiting for write to complete */ | |
698 | wait_for_completion(&info->comp); | |
5c468455 | 699 | |
4e070376 SG |
700 | /* wait for data to flushed-out before reset the prefetch */ |
701 | tim = 0; | |
702 | limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 AM |
703 | do { |
704 | val = readl(info->reg.gpmc_prefetch_status); | |
47f88af4 | 705 | val = PREFETCH_STATUS_COUNT(val); |
4e070376 | 706 | cpu_relax(); |
65b97cf6 | 707 | } while (val && (tim++ < limit)); |
4e070376 SG |
708 | |
709 | /* disable and stop the PFPW engine */ | |
65b97cf6 | 710 | omap_prefetch_reset(info->gpmc_cs, info); |
4e070376 SG |
711 | return; |
712 | ||
713 | out_copy: | |
714 | if (info->nand.options & NAND_BUSWIDTH_16) | |
715 | omap_write_buf16(mtd, buf, len); | |
716 | else | |
717 | omap_write_buf8(mtd, buf, len); | |
718 | } | |
719 | ||
67ce04bf VS |
720 | /** |
721 | * gen_true_ecc - This function will generate true ECC value | |
722 | * @ecc_buf: buffer to store ecc code | |
723 | * | |
724 | * This generated true ECC value can be used when correcting | |
725 | * data read from NAND flash memory core | |
726 | */ | |
727 | static void gen_true_ecc(u8 *ecc_buf) | |
728 | { | |
729 | u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) | | |
730 | ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8); | |
731 | ||
732 | ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | | |
733 | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp)); | |
734 | ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | | |
735 | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp)); | |
736 | ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | | |
737 | P1e(tmp) | P2048o(tmp) | P2048e(tmp)); | |
738 | } | |
739 | ||
740 | /** | |
741 | * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data | |
742 | * @ecc_data1: ecc code from nand spare area | |
743 | * @ecc_data2: ecc code from hardware register obtained from hardware ecc | |
744 | * @page_data: page data | |
745 | * | |
746 | * This function compares two ECC's and indicates if there is an error. | |
747 | * If the error can be corrected it will be corrected to the buffer. | |
74f1b724 JO |
748 | * If there is no error, %0 is returned. If there is an error but it |
749 | * was corrected, %1 is returned. Otherwise, %-1 is returned. | |
67ce04bf VS |
750 | */ |
751 | static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */ | |
752 | u8 *ecc_data2, /* read from register */ | |
753 | u8 *page_data) | |
754 | { | |
755 | uint i; | |
756 | u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8]; | |
757 | u8 comp0_bit[8], comp1_bit[8], comp2_bit[8]; | |
758 | u8 ecc_bit[24]; | |
759 | u8 ecc_sum = 0; | |
760 | u8 find_bit = 0; | |
761 | uint find_byte = 0; | |
762 | int isEccFF; | |
763 | ||
764 | isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF); | |
765 | ||
766 | gen_true_ecc(ecc_data1); | |
767 | gen_true_ecc(ecc_data2); | |
768 | ||
769 | for (i = 0; i <= 2; i++) { | |
770 | *(ecc_data1 + i) = ~(*(ecc_data1 + i)); | |
771 | *(ecc_data2 + i) = ~(*(ecc_data2 + i)); | |
772 | } | |
773 | ||
774 | for (i = 0; i < 8; i++) { | |
775 | tmp0_bit[i] = *ecc_data1 % 2; | |
776 | *ecc_data1 = *ecc_data1 / 2; | |
777 | } | |
778 | ||
779 | for (i = 0; i < 8; i++) { | |
780 | tmp1_bit[i] = *(ecc_data1 + 1) % 2; | |
781 | *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2; | |
782 | } | |
783 | ||
784 | for (i = 0; i < 8; i++) { | |
785 | tmp2_bit[i] = *(ecc_data1 + 2) % 2; | |
786 | *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2; | |
787 | } | |
788 | ||
789 | for (i = 0; i < 8; i++) { | |
790 | comp0_bit[i] = *ecc_data2 % 2; | |
791 | *ecc_data2 = *ecc_data2 / 2; | |
792 | } | |
793 | ||
794 | for (i = 0; i < 8; i++) { | |
795 | comp1_bit[i] = *(ecc_data2 + 1) % 2; | |
796 | *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2; | |
797 | } | |
798 | ||
799 | for (i = 0; i < 8; i++) { | |
800 | comp2_bit[i] = *(ecc_data2 + 2) % 2; | |
801 | *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2; | |
802 | } | |
803 | ||
804 | for (i = 0; i < 6; i++) | |
805 | ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2]; | |
806 | ||
807 | for (i = 0; i < 8; i++) | |
808 | ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i]; | |
809 | ||
810 | for (i = 0; i < 8; i++) | |
811 | ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i]; | |
812 | ||
813 | ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0]; | |
814 | ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1]; | |
815 | ||
816 | for (i = 0; i < 24; i++) | |
817 | ecc_sum += ecc_bit[i]; | |
818 | ||
819 | switch (ecc_sum) { | |
820 | case 0: | |
821 | /* Not reached because this function is not called if | |
822 | * ECC values are equal | |
823 | */ | |
824 | return 0; | |
825 | ||
826 | case 1: | |
827 | /* Uncorrectable error */ | |
289c0522 | 828 | pr_debug("ECC UNCORRECTED_ERROR 1\n"); |
67ce04bf VS |
829 | return -1; |
830 | ||
831 | case 11: | |
832 | /* UN-Correctable error */ | |
289c0522 | 833 | pr_debug("ECC UNCORRECTED_ERROR B\n"); |
67ce04bf VS |
834 | return -1; |
835 | ||
836 | case 12: | |
837 | /* Correctable error */ | |
838 | find_byte = (ecc_bit[23] << 8) + | |
839 | (ecc_bit[21] << 7) + | |
840 | (ecc_bit[19] << 6) + | |
841 | (ecc_bit[17] << 5) + | |
842 | (ecc_bit[15] << 4) + | |
843 | (ecc_bit[13] << 3) + | |
844 | (ecc_bit[11] << 2) + | |
845 | (ecc_bit[9] << 1) + | |
846 | ecc_bit[7]; | |
847 | ||
848 | find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; | |
849 | ||
0a32a102 BN |
850 | pr_debug("Correcting single bit ECC error at offset: " |
851 | "%d, bit: %d\n", find_byte, find_bit); | |
67ce04bf VS |
852 | |
853 | page_data[find_byte] ^= (1 << find_bit); | |
854 | ||
74f1b724 | 855 | return 1; |
67ce04bf VS |
856 | default: |
857 | if (isEccFF) { | |
858 | if (ecc_data2[0] == 0 && | |
859 | ecc_data2[1] == 0 && | |
860 | ecc_data2[2] == 0) | |
861 | return 0; | |
862 | } | |
289c0522 | 863 | pr_debug("UNCORRECTED_ERROR default\n"); |
67ce04bf VS |
864 | return -1; |
865 | } | |
866 | } | |
867 | ||
868 | /** | |
869 | * omap_correct_data - Compares the ECC read with HW generated ECC | |
870 | * @mtd: MTD device structure | |
871 | * @dat: page data | |
872 | * @read_ecc: ecc read from nand flash | |
873 | * @calc_ecc: ecc read from HW ECC registers | |
874 | * | |
875 | * Compares the ecc read from nand spare area with ECC registers values | |
74f1b724 JO |
876 | * and if ECC's mismatched, it will call 'omap_compare_ecc' for error |
877 | * detection and correction. If there are no errors, %0 is returned. If | |
878 | * there were errors and all of the errors were corrected, the number of | |
879 | * corrected errors is returned. If uncorrectable errors exist, %-1 is | |
880 | * returned. | |
67ce04bf VS |
881 | */ |
882 | static int omap_correct_data(struct mtd_info *mtd, u_char *dat, | |
883 | u_char *read_ecc, u_char *calc_ecc) | |
884 | { | |
885 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
886 | mtd); | |
887 | int blockCnt = 0, i = 0, ret = 0; | |
74f1b724 | 888 | int stat = 0; |
67ce04bf VS |
889 | |
890 | /* Ex NAND_ECC_HW12_2048 */ | |
891 | if ((info->nand.ecc.mode == NAND_ECC_HW) && | |
892 | (info->nand.ecc.size == 2048)) | |
893 | blockCnt = 4; | |
894 | else | |
895 | blockCnt = 1; | |
896 | ||
897 | for (i = 0; i < blockCnt; i++) { | |
898 | if (memcmp(read_ecc, calc_ecc, 3) != 0) { | |
899 | ret = omap_compare_ecc(read_ecc, calc_ecc, dat); | |
900 | if (ret < 0) | |
901 | return ret; | |
74f1b724 JO |
902 | /* keep track of the number of corrected errors */ |
903 | stat += ret; | |
67ce04bf VS |
904 | } |
905 | read_ecc += 3; | |
906 | calc_ecc += 3; | |
907 | dat += 512; | |
908 | } | |
74f1b724 | 909 | return stat; |
67ce04bf VS |
910 | } |
911 | ||
912 | /** | |
913 | * omap_calcuate_ecc - Generate non-inverted ECC bytes. | |
914 | * @mtd: MTD device structure | |
915 | * @dat: The pointer to data on which ecc is computed | |
916 | * @ecc_code: The ecc_code buffer | |
917 | * | |
918 | * Using noninverted ECC can be considered ugly since writing a blank | |
919 | * page ie. padding will clear the ECC bytes. This is no problem as long | |
920 | * nobody is trying to write data on the seemingly unused page. Reading | |
921 | * an erased page will produce an ECC mismatch between generated and read | |
922 | * ECC bytes that has to be dealt with separately. | |
923 | */ | |
924 | static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat, | |
925 | u_char *ecc_code) | |
926 | { | |
927 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
928 | mtd); | |
65b97cf6 AM |
929 | u32 val; |
930 | ||
931 | val = readl(info->reg.gpmc_ecc_config); | |
932 | if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs) | |
933 | return -EINVAL; | |
934 | ||
935 | /* read ecc result */ | |
936 | val = readl(info->reg.gpmc_ecc1_result); | |
937 | *ecc_code++ = val; /* P128e, ..., P1e */ | |
938 | *ecc_code++ = val >> 16; /* P128o, ..., P1o */ | |
939 | /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ | |
940 | *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); | |
941 | ||
942 | return 0; | |
67ce04bf VS |
943 | } |
944 | ||
945 | /** | |
946 | * omap_enable_hwecc - This function enables the hardware ecc functionality | |
947 | * @mtd: MTD device structure | |
948 | * @mode: Read/Write mode | |
949 | */ | |
950 | static void omap_enable_hwecc(struct mtd_info *mtd, int mode) | |
951 | { | |
952 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
953 | mtd); | |
954 | struct nand_chip *chip = mtd->priv; | |
955 | unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; | |
65b97cf6 AM |
956 | u32 val; |
957 | ||
958 | /* clear ecc and enable bits */ | |
959 | val = ECCCLEAR | ECC1; | |
960 | writel(val, info->reg.gpmc_ecc_control); | |
67ce04bf | 961 | |
65b97cf6 AM |
962 | /* program ecc and result sizes */ |
963 | val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) | | |
964 | ECC1RESULTSIZE); | |
965 | writel(val, info->reg.gpmc_ecc_size_config); | |
966 | ||
967 | switch (mode) { | |
968 | case NAND_ECC_READ: | |
969 | case NAND_ECC_WRITE: | |
970 | writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); | |
971 | break; | |
972 | case NAND_ECC_READSYN: | |
973 | writel(ECCCLEAR, info->reg.gpmc_ecc_control); | |
974 | break; | |
975 | default: | |
976 | dev_info(&info->pdev->dev, | |
977 | "error: unrecognized Mode[%d]!\n", mode); | |
978 | break; | |
979 | } | |
67ce04bf | 980 | |
65b97cf6 AM |
981 | /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ |
982 | val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); | |
983 | writel(val, info->reg.gpmc_ecc_config); | |
67ce04bf | 984 | } |
2c01946c | 985 | |
67ce04bf VS |
986 | /** |
987 | * omap_wait - wait until the command is done | |
988 | * @mtd: MTD device structure | |
989 | * @chip: NAND Chip structure | |
990 | * | |
991 | * Wait function is called during Program and erase operations and | |
992 | * the way it is called from MTD layer, we should wait till the NAND | |
993 | * chip is ready after the programming/erase operation has completed. | |
994 | * | |
995 | * Erase can take up to 400ms and program up to 20ms according to | |
996 | * general NAND and SmartMedia specs | |
997 | */ | |
998 | static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
999 | { | |
1000 | struct nand_chip *this = mtd->priv; | |
1001 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1002 | mtd); | |
1003 | unsigned long timeo = jiffies; | |
a9c465f0 | 1004 | int status, state = this->state; |
67ce04bf VS |
1005 | |
1006 | if (state == FL_ERASING) | |
4ff6772b | 1007 | timeo += msecs_to_jiffies(400); |
67ce04bf | 1008 | else |
4ff6772b | 1009 | timeo += msecs_to_jiffies(20); |
67ce04bf | 1010 | |
65b97cf6 | 1011 | writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command); |
67ce04bf | 1012 | while (time_before(jiffies, timeo)) { |
65b97cf6 | 1013 | status = readb(info->reg.gpmc_nand_data); |
c276aca4 | 1014 | if (status & NAND_STATUS_READY) |
67ce04bf | 1015 | break; |
c276aca4 | 1016 | cond_resched(); |
67ce04bf | 1017 | } |
a9c465f0 | 1018 | |
4ea1e4ba | 1019 | status = readb(info->reg.gpmc_nand_data); |
67ce04bf VS |
1020 | return status; |
1021 | } | |
1022 | ||
1023 | /** | |
1024 | * omap_dev_ready - calls the platform specific dev_ready function | |
1025 | * @mtd: MTD device structure | |
1026 | */ | |
1027 | static int omap_dev_ready(struct mtd_info *mtd) | |
1028 | { | |
2c01946c | 1029 | unsigned int val = 0; |
67ce04bf VS |
1030 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
1031 | mtd); | |
67ce04bf | 1032 | |
65b97cf6 AM |
1033 | val = readl(info->reg.gpmc_status); |
1034 | ||
67ce04bf | 1035 | if ((val & 0x100) == 0x100) { |
65b97cf6 | 1036 | return 1; |
67ce04bf | 1037 | } else { |
65b97cf6 | 1038 | return 0; |
67ce04bf | 1039 | } |
67ce04bf VS |
1040 | } |
1041 | ||
a919e511 | 1042 | #if defined(CONFIG_MTD_NAND_ECC_BCH) || defined(CONFIG_MTD_NAND_OMAP_BCH) |
0e618ef0 ID |
1043 | /** |
1044 | * omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction | |
1045 | * @mtd: MTD device structure | |
1046 | * @mode: Read/Write mode | |
62116e51 PA |
1047 | * |
1048 | * When using BCH, sector size is hardcoded to 512 bytes. | |
1049 | * Using wrapping mode 6 both for reading and writing if ELM module not uses | |
1050 | * for error correction. | |
1051 | * On writing, | |
1052 | * eccsize0 = 0 (no additional protected byte in spare area) | |
1053 | * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area) | |
0e618ef0 ID |
1054 | */ |
1055 | static void omap3_enable_hwecc_bch(struct mtd_info *mtd, int mode) | |
1056 | { | |
1057 | int nerrors; | |
2ef9f3dd | 1058 | unsigned int dev_width, nsectors; |
0e618ef0 ID |
1059 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
1060 | mtd); | |
1061 | struct nand_chip *chip = mtd->priv; | |
62116e51 PA |
1062 | u32 val, wr_mode; |
1063 | unsigned int ecc_size1, ecc_size0; | |
1064 | ||
1065 | /* Using wrapping mode 6 for writing */ | |
1066 | wr_mode = BCH_WRAPMODE_6; | |
0e618ef0 | 1067 | |
0e618ef0 | 1068 | /* |
62116e51 PA |
1069 | * ECC engine enabled for valid ecc_size0 nibbles |
1070 | * and disabled for ecc_size1 nibbles. | |
0e618ef0 | 1071 | */ |
62116e51 PA |
1072 | ecc_size0 = BCH_ECC_SIZE0; |
1073 | ecc_size1 = BCH_ECC_SIZE1; | |
1074 | ||
1075 | /* Perform ecc calculation on 512-byte sector */ | |
1076 | nsectors = 1; | |
1077 | ||
1078 | /* Update number of error correction */ | |
1079 | nerrors = info->nand.ecc.strength; | |
1080 | ||
1081 | /* Multi sector reading/writing for NAND flash with page size < 4096 */ | |
1082 | if (info->is_elm_used && (mtd->writesize <= 4096)) { | |
1083 | if (mode == NAND_ECC_READ) { | |
1084 | /* Using wrapping mode 1 for reading */ | |
1085 | wr_mode = BCH_WRAPMODE_1; | |
1086 | ||
1087 | /* | |
1088 | * ECC engine enabled for ecc_size0 nibbles | |
1089 | * and disabled for ecc_size1 nibbles. | |
1090 | */ | |
1091 | ecc_size0 = (nerrors == 8) ? | |
1092 | BCH8R_ECC_SIZE0 : BCH4R_ECC_SIZE0; | |
1093 | ecc_size1 = (nerrors == 8) ? | |
1094 | BCH8R_ECC_SIZE1 : BCH4R_ECC_SIZE1; | |
1095 | } | |
1096 | ||
1097 | /* Perform ecc calculation for one page (< 4096) */ | |
1098 | nsectors = info->nand.ecc.steps; | |
1099 | } | |
2ef9f3dd AM |
1100 | |
1101 | writel(ECC1, info->reg.gpmc_ecc_control); | |
1102 | ||
62116e51 PA |
1103 | /* Configure ecc size for BCH */ |
1104 | val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT); | |
2ef9f3dd AM |
1105 | writel(val, info->reg.gpmc_ecc_size_config); |
1106 | ||
62116e51 PA |
1107 | dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; |
1108 | ||
2ef9f3dd AM |
1109 | /* BCH configuration */ |
1110 | val = ((1 << 16) | /* enable BCH */ | |
1111 | (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */ | |
62116e51 | 1112 | (wr_mode << 8) | /* wrap mode */ |
2ef9f3dd AM |
1113 | (dev_width << 7) | /* bus width */ |
1114 | (((nsectors-1) & 0x7) << 4) | /* number of sectors */ | |
1115 | (info->gpmc_cs << 1) | /* ECC CS */ | |
1116 | (0x1)); /* enable ECC */ | |
1117 | ||
1118 | writel(val, info->reg.gpmc_ecc_config); | |
1119 | ||
62116e51 | 1120 | /* Clear ecc and enable bits */ |
2ef9f3dd | 1121 | writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); |
0e618ef0 | 1122 | } |
a919e511 | 1123 | #endif |
0e618ef0 | 1124 | |
a919e511 | 1125 | #ifdef CONFIG_MTD_NAND_ECC_BCH |
0e618ef0 ID |
1126 | /** |
1127 | * omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC bytes | |
1128 | * @mtd: MTD device structure | |
1129 | * @dat: The pointer to data on which ecc is computed | |
1130 | * @ecc_code: The ecc_code buffer | |
1131 | */ | |
1132 | static int omap3_calculate_ecc_bch4(struct mtd_info *mtd, const u_char *dat, | |
1133 | u_char *ecc_code) | |
1134 | { | |
1135 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1136 | mtd); | |
2ef9f3dd AM |
1137 | unsigned long nsectors, val1, val2; |
1138 | int i; | |
1139 | ||
1140 | nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1; | |
1141 | ||
1142 | for (i = 0; i < nsectors; i++) { | |
1143 | ||
1144 | /* Read hw-computed remainder */ | |
1145 | val1 = readl(info->reg.gpmc_bch_result0[i]); | |
1146 | val2 = readl(info->reg.gpmc_bch_result1[i]); | |
1147 | ||
1148 | /* | |
1149 | * Add constant polynomial to remainder, in order to get an ecc | |
1150 | * sequence of 0xFFs for a buffer filled with 0xFFs; and | |
1151 | * left-justify the resulting polynomial. | |
1152 | */ | |
1153 | *ecc_code++ = 0x28 ^ ((val2 >> 12) & 0xFF); | |
1154 | *ecc_code++ = 0x13 ^ ((val2 >> 4) & 0xFF); | |
1155 | *ecc_code++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF)); | |
1156 | *ecc_code++ = 0x39 ^ ((val1 >> 20) & 0xFF); | |
1157 | *ecc_code++ = 0x96 ^ ((val1 >> 12) & 0xFF); | |
1158 | *ecc_code++ = 0xac ^ ((val1 >> 4) & 0xFF); | |
1159 | *ecc_code++ = 0x7f ^ ((val1 & 0xF) << 4); | |
1160 | } | |
1161 | ||
1162 | return 0; | |
0e618ef0 ID |
1163 | } |
1164 | ||
1165 | /** | |
1166 | * omap3_calculate_ecc_bch8 - Generate 13 bytes of ECC bytes | |
1167 | * @mtd: MTD device structure | |
1168 | * @dat: The pointer to data on which ecc is computed | |
1169 | * @ecc_code: The ecc_code buffer | |
1170 | */ | |
1171 | static int omap3_calculate_ecc_bch8(struct mtd_info *mtd, const u_char *dat, | |
1172 | u_char *ecc_code) | |
1173 | { | |
1174 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1175 | mtd); | |
2ef9f3dd AM |
1176 | unsigned long nsectors, val1, val2, val3, val4; |
1177 | int i; | |
1178 | ||
1179 | nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1; | |
1180 | ||
1181 | for (i = 0; i < nsectors; i++) { | |
1182 | ||
1183 | /* Read hw-computed remainder */ | |
1184 | val1 = readl(info->reg.gpmc_bch_result0[i]); | |
1185 | val2 = readl(info->reg.gpmc_bch_result1[i]); | |
1186 | val3 = readl(info->reg.gpmc_bch_result2[i]); | |
1187 | val4 = readl(info->reg.gpmc_bch_result3[i]); | |
1188 | ||
1189 | /* | |
1190 | * Add constant polynomial to remainder, in order to get an ecc | |
1191 | * sequence of 0xFFs for a buffer filled with 0xFFs. | |
1192 | */ | |
1193 | *ecc_code++ = 0xef ^ (val4 & 0xFF); | |
1194 | *ecc_code++ = 0x51 ^ ((val3 >> 24) & 0xFF); | |
1195 | *ecc_code++ = 0x2e ^ ((val3 >> 16) & 0xFF); | |
1196 | *ecc_code++ = 0x09 ^ ((val3 >> 8) & 0xFF); | |
1197 | *ecc_code++ = 0xed ^ (val3 & 0xFF); | |
1198 | *ecc_code++ = 0x93 ^ ((val2 >> 24) & 0xFF); | |
1199 | *ecc_code++ = 0x9a ^ ((val2 >> 16) & 0xFF); | |
1200 | *ecc_code++ = 0xc2 ^ ((val2 >> 8) & 0xFF); | |
1201 | *ecc_code++ = 0x97 ^ (val2 & 0xFF); | |
1202 | *ecc_code++ = 0x79 ^ ((val1 >> 24) & 0xFF); | |
1203 | *ecc_code++ = 0xe5 ^ ((val1 >> 16) & 0xFF); | |
1204 | *ecc_code++ = 0x24 ^ ((val1 >> 8) & 0xFF); | |
1205 | *ecc_code++ = 0xb5 ^ (val1 & 0xFF); | |
1206 | } | |
1207 | ||
1208 | return 0; | |
0e618ef0 | 1209 | } |
a919e511 | 1210 | #endif /* CONFIG_MTD_NAND_ECC_BCH */ |
0e618ef0 | 1211 | |
a919e511 | 1212 | #ifdef CONFIG_MTD_NAND_OMAP_BCH |
62116e51 | 1213 | /** |
a4c7ca00 | 1214 | * omap_calculate_ecc_bch - Generate bytes of ECC bytes |
62116e51 PA |
1215 | * @mtd: MTD device structure |
1216 | * @dat: The pointer to data on which ecc is computed | |
1217 | * @ecc_code: The ecc_code buffer | |
1218 | * | |
1219 | * Support calculating of BCH4/8 ecc vectors for the page | |
1220 | */ | |
a4c7ca00 PG |
1221 | static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd, |
1222 | const u_char *dat, u_char *ecc_code) | |
62116e51 PA |
1223 | { |
1224 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1225 | mtd); | |
1226 | unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4; | |
1227 | int i, eccbchtsel; | |
1228 | ||
1229 | nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1; | |
1230 | /* | |
1231 | * find BCH scheme used | |
1232 | * 0 -> BCH4 | |
1233 | * 1 -> BCH8 | |
1234 | */ | |
1235 | eccbchtsel = ((readl(info->reg.gpmc_ecc_config) >> 12) & 0x3); | |
1236 | ||
1237 | for (i = 0; i < nsectors; i++) { | |
1238 | ||
1239 | /* Read hw-computed remainder */ | |
1240 | bch_val1 = readl(info->reg.gpmc_bch_result0[i]); | |
1241 | bch_val2 = readl(info->reg.gpmc_bch_result1[i]); | |
1242 | if (eccbchtsel) { | |
1243 | bch_val3 = readl(info->reg.gpmc_bch_result2[i]); | |
1244 | bch_val4 = readl(info->reg.gpmc_bch_result3[i]); | |
1245 | } | |
1246 | ||
1247 | if (eccbchtsel) { | |
1248 | /* BCH8 ecc scheme */ | |
1249 | *ecc_code++ = (bch_val4 & 0xFF); | |
1250 | *ecc_code++ = ((bch_val3 >> 24) & 0xFF); | |
1251 | *ecc_code++ = ((bch_val3 >> 16) & 0xFF); | |
1252 | *ecc_code++ = ((bch_val3 >> 8) & 0xFF); | |
1253 | *ecc_code++ = (bch_val3 & 0xFF); | |
1254 | *ecc_code++ = ((bch_val2 >> 24) & 0xFF); | |
1255 | *ecc_code++ = ((bch_val2 >> 16) & 0xFF); | |
1256 | *ecc_code++ = ((bch_val2 >> 8) & 0xFF); | |
1257 | *ecc_code++ = (bch_val2 & 0xFF); | |
1258 | *ecc_code++ = ((bch_val1 >> 24) & 0xFF); | |
1259 | *ecc_code++ = ((bch_val1 >> 16) & 0xFF); | |
1260 | *ecc_code++ = ((bch_val1 >> 8) & 0xFF); | |
1261 | *ecc_code++ = (bch_val1 & 0xFF); | |
1262 | /* | |
1263 | * Setting 14th byte to zero to handle | |
1264 | * erased page & maintain compatibility | |
1265 | * with RBL | |
1266 | */ | |
1267 | *ecc_code++ = 0x0; | |
1268 | } else { | |
1269 | /* BCH4 ecc scheme */ | |
1270 | *ecc_code++ = ((bch_val2 >> 12) & 0xFF); | |
1271 | *ecc_code++ = ((bch_val2 >> 4) & 0xFF); | |
1272 | *ecc_code++ = ((bch_val2 & 0xF) << 4) | | |
1273 | ((bch_val1 >> 28) & 0xF); | |
1274 | *ecc_code++ = ((bch_val1 >> 20) & 0xFF); | |
1275 | *ecc_code++ = ((bch_val1 >> 12) & 0xFF); | |
1276 | *ecc_code++ = ((bch_val1 >> 4) & 0xFF); | |
1277 | *ecc_code++ = ((bch_val1 & 0xF) << 4); | |
1278 | /* | |
1279 | * Setting 8th byte to zero to handle | |
1280 | * erased page | |
1281 | */ | |
1282 | *ecc_code++ = 0x0; | |
1283 | } | |
1284 | } | |
1285 | ||
1286 | return 0; | |
1287 | } | |
1288 | ||
1289 | /** | |
1290 | * erased_sector_bitflips - count bit flips | |
1291 | * @data: data sector buffer | |
1292 | * @oob: oob buffer | |
1293 | * @info: omap_nand_info | |
1294 | * | |
1295 | * Check the bit flips in erased page falls below correctable level. | |
1296 | * If falls below, report the page as erased with correctable bit | |
1297 | * flip, else report as uncorrectable page. | |
1298 | */ | |
1299 | static int erased_sector_bitflips(u_char *data, u_char *oob, | |
1300 | struct omap_nand_info *info) | |
1301 | { | |
1302 | int flip_bits = 0, i; | |
1303 | ||
1304 | for (i = 0; i < info->nand.ecc.size; i++) { | |
1305 | flip_bits += hweight8(~data[i]); | |
1306 | if (flip_bits > info->nand.ecc.strength) | |
1307 | return 0; | |
1308 | } | |
1309 | ||
1310 | for (i = 0; i < info->nand.ecc.bytes - 1; i++) { | |
1311 | flip_bits += hweight8(~oob[i]); | |
1312 | if (flip_bits > info->nand.ecc.strength) | |
1313 | return 0; | |
1314 | } | |
1315 | ||
1316 | /* | |
1317 | * Bit flips falls in correctable level. | |
1318 | * Fill data area with 0xFF | |
1319 | */ | |
1320 | if (flip_bits) { | |
1321 | memset(data, 0xFF, info->nand.ecc.size); | |
1322 | memset(oob, 0xFF, info->nand.ecc.bytes); | |
1323 | } | |
1324 | ||
1325 | return flip_bits; | |
1326 | } | |
1327 | ||
1328 | /** | |
1329 | * omap_elm_correct_data - corrects page data area in case error reported | |
1330 | * @mtd: MTD device structure | |
1331 | * @data: page data | |
1332 | * @read_ecc: ecc read from nand flash | |
1333 | * @calc_ecc: ecc read from HW ECC registers | |
1334 | * | |
1335 | * Calculated ecc vector reported as zero in case of non-error pages. | |
78f43c53 PG |
1336 | * In case of non-zero ecc vector, first filter out erased-pages, and |
1337 | * then process data via ELM to detect bit-flips. | |
62116e51 PA |
1338 | */ |
1339 | static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data, | |
1340 | u_char *read_ecc, u_char *calc_ecc) | |
1341 | { | |
1342 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1343 | mtd); | |
de0a4d69 | 1344 | struct nand_ecc_ctrl *ecc = &info->nand.ecc; |
62116e51 PA |
1345 | int eccsteps = info->nand.ecc.steps; |
1346 | int i , j, stat = 0; | |
de0a4d69 | 1347 | int eccflag, actual_eccbytes; |
62116e51 PA |
1348 | struct elm_errorvec err_vec[ERROR_VECTOR_MAX]; |
1349 | u_char *ecc_vec = calc_ecc; | |
1350 | u_char *spare_ecc = read_ecc; | |
1351 | u_char *erased_ecc_vec; | |
78f43c53 PG |
1352 | u_char *buf; |
1353 | int bitflip_count; | |
62116e51 | 1354 | bool is_error_reported = false; |
b08e1f63 | 1355 | u32 bit_pos, byte_pos, error_max, pos; |
13fbe064 | 1356 | int err; |
62116e51 | 1357 | |
de0a4d69 PG |
1358 | switch (info->ecc_opt) { |
1359 | case OMAP_ECC_BCH4_CODE_HW: | |
1360 | /* omit 7th ECC byte reserved for ROM code compatibility */ | |
1361 | actual_eccbytes = ecc->bytes - 1; | |
78f43c53 | 1362 | erased_ecc_vec = bch4_vector; |
de0a4d69 PG |
1363 | break; |
1364 | case OMAP_ECC_BCH8_CODE_HW: | |
1365 | /* omit 14th ECC byte reserved for ROM code compatibility */ | |
1366 | actual_eccbytes = ecc->bytes - 1; | |
78f43c53 | 1367 | erased_ecc_vec = bch8_vector; |
de0a4d69 PG |
1368 | break; |
1369 | default: | |
1370 | pr_err("invalid driver configuration\n"); | |
1371 | return -EINVAL; | |
1372 | } | |
1373 | ||
62116e51 PA |
1374 | /* Initialize elm error vector to zero */ |
1375 | memset(err_vec, 0, sizeof(err_vec)); | |
1376 | ||
62116e51 PA |
1377 | for (i = 0; i < eccsteps ; i++) { |
1378 | eccflag = 0; /* initialize eccflag */ | |
1379 | ||
1380 | /* | |
1381 | * Check any error reported, | |
1382 | * In case of error, non zero ecc reported. | |
1383 | */ | |
de0a4d69 | 1384 | for (j = 0; j < actual_eccbytes; j++) { |
62116e51 PA |
1385 | if (calc_ecc[j] != 0) { |
1386 | eccflag = 1; /* non zero ecc, error present */ | |
1387 | break; | |
1388 | } | |
1389 | } | |
1390 | ||
1391 | if (eccflag == 1) { | |
78f43c53 PG |
1392 | if (memcmp(calc_ecc, erased_ecc_vec, |
1393 | actual_eccbytes) == 0) { | |
62116e51 | 1394 | /* |
78f43c53 PG |
1395 | * calc_ecc[] matches pattern for ECC(all 0xff) |
1396 | * so this is definitely an erased-page | |
62116e51 | 1397 | */ |
62116e51 | 1398 | } else { |
78f43c53 PG |
1399 | buf = &data[info->nand.ecc.size * i]; |
1400 | /* | |
1401 | * count number of 0-bits in read_buf. | |
1402 | * This check can be removed once a similar | |
1403 | * check is introduced in generic NAND driver | |
1404 | */ | |
1405 | bitflip_count = erased_sector_bitflips( | |
1406 | buf, read_ecc, info); | |
1407 | if (bitflip_count) { | |
1408 | /* | |
1409 | * number of 0-bits within ECC limits | |
1410 | * So this may be an erased-page | |
1411 | */ | |
1412 | stat += bitflip_count; | |
1413 | } else { | |
1414 | /* | |
1415 | * Too many 0-bits. It may be a | |
1416 | * - programmed-page, OR | |
1417 | * - erased-page with many bit-flips | |
1418 | * So this page requires check by ELM | |
1419 | */ | |
1420 | err_vec[i].error_reported = true; | |
1421 | is_error_reported = true; | |
62116e51 PA |
1422 | } |
1423 | } | |
1424 | } | |
1425 | ||
1426 | /* Update the ecc vector */ | |
de0a4d69 PG |
1427 | calc_ecc += ecc->bytes; |
1428 | read_ecc += ecc->bytes; | |
62116e51 PA |
1429 | } |
1430 | ||
1431 | /* Check if any error reported */ | |
1432 | if (!is_error_reported) | |
1433 | return 0; | |
1434 | ||
1435 | /* Decode BCH error using ELM module */ | |
1436 | elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec); | |
1437 | ||
13fbe064 | 1438 | err = 0; |
62116e51 | 1439 | for (i = 0; i < eccsteps; i++) { |
13fbe064 PG |
1440 | if (err_vec[i].error_uncorrectable) { |
1441 | pr_err("nand: uncorrectable bit-flips found\n"); | |
1442 | err = -EBADMSG; | |
1443 | } else if (err_vec[i].error_reported) { | |
62116e51 | 1444 | for (j = 0; j < err_vec[i].error_count; j++) { |
b08e1f63 PG |
1445 | switch (info->ecc_opt) { |
1446 | case OMAP_ECC_BCH4_CODE_HW: | |
1447 | /* Add 4 bits to take care of padding */ | |
62116e51 PA |
1448 | pos = err_vec[i].error_loc[j] + |
1449 | BCH4_BIT_PAD; | |
b08e1f63 PG |
1450 | break; |
1451 | case OMAP_ECC_BCH8_CODE_HW: | |
1452 | pos = err_vec[i].error_loc[j]; | |
1453 | break; | |
1454 | default: | |
1455 | return -EINVAL; | |
1456 | } | |
1457 | error_max = (ecc->size + actual_eccbytes) * 8; | |
62116e51 PA |
1458 | /* Calculate bit position of error */ |
1459 | bit_pos = pos % 8; | |
1460 | ||
1461 | /* Calculate byte position of error */ | |
1462 | byte_pos = (error_max - pos - 1) / 8; | |
1463 | ||
1464 | if (pos < error_max) { | |
13fbe064 PG |
1465 | if (byte_pos < 512) { |
1466 | pr_debug("bitflip@dat[%d]=%x\n", | |
1467 | byte_pos, data[byte_pos]); | |
62116e51 | 1468 | data[byte_pos] ^= 1 << bit_pos; |
13fbe064 PG |
1469 | } else { |
1470 | pr_debug("bitflip@oob[%d]=%x\n", | |
1471 | (byte_pos - 512), | |
1472 | spare_ecc[byte_pos - 512]); | |
62116e51 PA |
1473 | spare_ecc[byte_pos - 512] ^= |
1474 | 1 << bit_pos; | |
13fbe064 PG |
1475 | } |
1476 | } else { | |
1477 | pr_err("invalid bit-flip @ %d:%d\n", | |
1478 | byte_pos, bit_pos); | |
1479 | err = -EBADMSG; | |
62116e51 | 1480 | } |
62116e51 PA |
1481 | } |
1482 | } | |
1483 | ||
1484 | /* Update number of correctable errors */ | |
1485 | stat += err_vec[i].error_count; | |
1486 | ||
1487 | /* Update page data with sector size */ | |
b08e1f63 | 1488 | data += ecc->size; |
de0a4d69 | 1489 | spare_ecc += ecc->bytes; |
62116e51 PA |
1490 | } |
1491 | ||
13fbe064 | 1492 | return (err) ? err : stat; |
62116e51 PA |
1493 | } |
1494 | ||
62116e51 PA |
1495 | /** |
1496 | * omap_write_page_bch - BCH ecc based write page function for entire page | |
1497 | * @mtd: mtd info structure | |
1498 | * @chip: nand chip info structure | |
1499 | * @buf: data buffer | |
1500 | * @oob_required: must write chip->oob_poi to OOB | |
1501 | * | |
1502 | * Custom write page method evolved to support multi sector writing in one shot | |
1503 | */ | |
1504 | static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip, | |
1505 | const uint8_t *buf, int oob_required) | |
1506 | { | |
1507 | int i; | |
1508 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
1509 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1510 | ||
1511 | /* Enable GPMC ecc engine */ | |
1512 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
1513 | ||
1514 | /* Write data */ | |
1515 | chip->write_buf(mtd, buf, mtd->writesize); | |
1516 | ||
1517 | /* Update ecc vector from GPMC result registers */ | |
1518 | chip->ecc.calculate(mtd, buf, &ecc_calc[0]); | |
1519 | ||
1520 | for (i = 0; i < chip->ecc.total; i++) | |
1521 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
1522 | ||
1523 | /* Write ecc vector to OOB area */ | |
1524 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1525 | return 0; | |
1526 | } | |
1527 | ||
1528 | /** | |
1529 | * omap_read_page_bch - BCH ecc based page read function for entire page | |
1530 | * @mtd: mtd info structure | |
1531 | * @chip: nand chip info structure | |
1532 | * @buf: buffer to store read data | |
1533 | * @oob_required: caller requires OOB data read to chip->oob_poi | |
1534 | * @page: page number to read | |
1535 | * | |
1536 | * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module | |
1537 | * used for error correction. | |
1538 | * Custom method evolved to support ELM error correction & multi sector | |
1539 | * reading. On reading page data area is read along with OOB data with | |
1540 | * ecc engine enabled. ecc vector updated after read of OOB data. | |
1541 | * For non error pages ecc vector reported as zero. | |
1542 | */ | |
1543 | static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, | |
1544 | uint8_t *buf, int oob_required, int page) | |
1545 | { | |
1546 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
1547 | uint8_t *ecc_code = chip->buffers->ecccode; | |
1548 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1549 | uint8_t *oob = &chip->oob_poi[eccpos[0]]; | |
1550 | uint32_t oob_pos = mtd->writesize + chip->ecc.layout->eccpos[0]; | |
1551 | int stat; | |
1552 | unsigned int max_bitflips = 0; | |
1553 | ||
1554 | /* Enable GPMC ecc engine */ | |
1555 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1556 | ||
1557 | /* Read data */ | |
1558 | chip->read_buf(mtd, buf, mtd->writesize); | |
1559 | ||
1560 | /* Read oob bytes */ | |
1561 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1); | |
1562 | chip->read_buf(mtd, oob, chip->ecc.total); | |
1563 | ||
1564 | /* Calculate ecc bytes */ | |
1565 | chip->ecc.calculate(mtd, buf, ecc_calc); | |
1566 | ||
1567 | memcpy(ecc_code, &chip->oob_poi[eccpos[0]], chip->ecc.total); | |
1568 | ||
1569 | stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc); | |
1570 | ||
1571 | if (stat < 0) { | |
1572 | mtd->ecc_stats.failed++; | |
1573 | } else { | |
1574 | mtd->ecc_stats.corrected += stat; | |
1575 | max_bitflips = max_t(unsigned int, max_bitflips, stat); | |
1576 | } | |
1577 | ||
1578 | return max_bitflips; | |
1579 | } | |
1580 | ||
0e618ef0 | 1581 | /** |
a919e511 PG |
1582 | * is_elm_present - checks for presence of ELM module by scanning DT nodes |
1583 | * @omap_nand_info: NAND device structure containing platform data | |
1584 | * @bch_type: 0x0=BCH4, 0x1=BCH8, 0x2=BCH16 | |
0e618ef0 | 1585 | */ |
a919e511 PG |
1586 | static int is_elm_present(struct omap_nand_info *info, |
1587 | struct device_node *elm_node, enum bch_ecc bch_type) | |
0e618ef0 | 1588 | { |
a919e511 PG |
1589 | struct platform_device *pdev; |
1590 | info->is_elm_used = false; | |
1591 | /* check whether elm-id is passed via DT */ | |
1592 | if (!elm_node) { | |
1593 | pr_err("nand: error: ELM DT node not found\n"); | |
1594 | return -ENODEV; | |
1595 | } | |
1596 | pdev = of_find_device_by_node(elm_node); | |
1597 | /* check whether ELM device is registered */ | |
1598 | if (!pdev) { | |
1599 | pr_err("nand: error: ELM device not found\n"); | |
1600 | return -ENODEV; | |
0e618ef0 | 1601 | } |
a919e511 PG |
1602 | /* ELM module available, now configure it */ |
1603 | info->elm_dev = &pdev->dev; | |
1604 | if (elm_config(info->elm_dev, bch_type)) | |
1605 | return -ENODEV; | |
1606 | info->is_elm_used = true; | |
1607 | return 0; | |
0e618ef0 | 1608 | } |
a919e511 | 1609 | #endif /* CONFIG_MTD_NAND_ECC_BCH */ |
0e618ef0 | 1610 | |
06f25510 | 1611 | static int omap_nand_probe(struct platform_device *pdev) |
67ce04bf VS |
1612 | { |
1613 | struct omap_nand_info *info; | |
1614 | struct omap_nand_platform_data *pdata; | |
633deb58 PG |
1615 | struct mtd_info *mtd; |
1616 | struct nand_chip *nand_chip; | |
b491da72 | 1617 | struct nand_ecclayout *ecclayout; |
67ce04bf | 1618 | int err; |
b491da72 | 1619 | int i; |
633deb58 PG |
1620 | dma_cap_mask_t mask; |
1621 | unsigned sig; | |
eae39cb4 | 1622 | unsigned oob_index; |
9c4c2f8b | 1623 | struct resource *res; |
ccf04c51 | 1624 | struct mtd_part_parser_data ppdata = {}; |
67ce04bf | 1625 | |
453810b7 | 1626 | pdata = dev_get_platdata(&pdev->dev); |
67ce04bf VS |
1627 | if (pdata == NULL) { |
1628 | dev_err(&pdev->dev, "platform data missing\n"); | |
1629 | return -ENODEV; | |
1630 | } | |
1631 | ||
70ba6d71 PG |
1632 | info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info), |
1633 | GFP_KERNEL); | |
67ce04bf VS |
1634 | if (!info) |
1635 | return -ENOMEM; | |
1636 | ||
1637 | platform_set_drvdata(pdev, info); | |
1638 | ||
1639 | spin_lock_init(&info->controller.lock); | |
1640 | init_waitqueue_head(&info->controller.wq); | |
1641 | ||
633deb58 | 1642 | info->pdev = pdev; |
67ce04bf | 1643 | info->gpmc_cs = pdata->cs; |
65b97cf6 | 1644 | info->reg = pdata->reg; |
a919e511 | 1645 | info->of_node = pdata->of_node; |
4e558072 | 1646 | info->ecc_opt = pdata->ecc_opt; |
633deb58 PG |
1647 | mtd = &info->mtd; |
1648 | mtd->priv = &info->nand; | |
1649 | mtd->name = dev_name(&pdev->dev); | |
1650 | mtd->owner = THIS_MODULE; | |
1651 | nand_chip = &info->nand; | |
32d42a85 | 1652 | nand_chip->ecc.priv = NULL; |
633deb58 | 1653 | nand_chip->options |= NAND_SKIP_BBTSCAN; |
67ce04bf | 1654 | |
9c4c2f8b AM |
1655 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1656 | if (res == NULL) { | |
1657 | err = -EINVAL; | |
1658 | dev_err(&pdev->dev, "error getting memory resource\n"); | |
70ba6d71 | 1659 | goto return_error; |
9c4c2f8b | 1660 | } |
67ce04bf | 1661 | |
9c4c2f8b AM |
1662 | info->phys_base = res->start; |
1663 | info->mem_size = resource_size(res); | |
1664 | ||
70ba6d71 PG |
1665 | if (!devm_request_mem_region(&pdev->dev, info->phys_base, |
1666 | info->mem_size, pdev->dev.driver->name)) { | |
67ce04bf | 1667 | err = -EBUSY; |
70ba6d71 | 1668 | goto return_error; |
67ce04bf VS |
1669 | } |
1670 | ||
70ba6d71 PG |
1671 | nand_chip->IO_ADDR_R = devm_ioremap(&pdev->dev, info->phys_base, |
1672 | info->mem_size); | |
633deb58 | 1673 | if (!nand_chip->IO_ADDR_R) { |
67ce04bf | 1674 | err = -ENOMEM; |
70ba6d71 | 1675 | goto return_error; |
67ce04bf | 1676 | } |
59e9c5ae | 1677 | |
633deb58 | 1678 | nand_chip->controller = &info->controller; |
67ce04bf | 1679 | |
633deb58 PG |
1680 | nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R; |
1681 | nand_chip->cmd_ctrl = omap_hwcontrol; | |
67ce04bf | 1682 | |
67ce04bf VS |
1683 | /* |
1684 | * If RDY/BSY line is connected to OMAP then use the omap ready | |
4cacbe22 PM |
1685 | * function and the generic nand_wait function which reads the status |
1686 | * register after monitoring the RDY/BSY line. Otherwise use a standard | |
67ce04bf VS |
1687 | * chip delay which is slightly more than tR (AC Timing) of the NAND |
1688 | * device and read status register until you get a failure or success | |
1689 | */ | |
1690 | if (pdata->dev_ready) { | |
633deb58 PG |
1691 | nand_chip->dev_ready = omap_dev_ready; |
1692 | nand_chip->chip_delay = 0; | |
67ce04bf | 1693 | } else { |
633deb58 PG |
1694 | nand_chip->waitfunc = omap_wait; |
1695 | nand_chip->chip_delay = 50; | |
67ce04bf VS |
1696 | } |
1697 | ||
f18befb5 PG |
1698 | /* scan NAND device connected to chip controller */ |
1699 | nand_chip->options |= pdata->devsize & NAND_BUSWIDTH_16; | |
1700 | if (nand_scan_ident(mtd, 1, NULL)) { | |
1701 | pr_err("nand device scan failed, may be bus-width mismatch\n"); | |
1702 | err = -ENXIO; | |
70ba6d71 | 1703 | goto return_error; |
f18befb5 PG |
1704 | } |
1705 | ||
b491da72 PG |
1706 | /* check for small page devices */ |
1707 | if ((mtd->oobsize < 64) && (pdata->ecc_opt != OMAP_ECC_HAM1_CODE_HW)) { | |
1708 | pr_err("small page devices are not supported\n"); | |
1709 | err = -EINVAL; | |
70ba6d71 | 1710 | goto return_error; |
b491da72 PG |
1711 | } |
1712 | ||
f18befb5 | 1713 | /* re-populate low-level callbacks based on xfer modes */ |
1b0b323c SG |
1714 | switch (pdata->xfer_type) { |
1715 | case NAND_OMAP_PREFETCH_POLLED: | |
633deb58 PG |
1716 | nand_chip->read_buf = omap_read_buf_pref; |
1717 | nand_chip->write_buf = omap_write_buf_pref; | |
1b0b323c SG |
1718 | break; |
1719 | ||
1720 | case NAND_OMAP_POLLED: | |
cf0e4d2b | 1721 | /* Use nand_base defaults for {read,write}_buf */ |
1b0b323c SG |
1722 | break; |
1723 | ||
1724 | case NAND_OMAP_PREFETCH_DMA: | |
763e7359 RK |
1725 | dma_cap_zero(mask); |
1726 | dma_cap_set(DMA_SLAVE, mask); | |
1727 | sig = OMAP24XX_DMA_GPMC; | |
1728 | info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig); | |
1729 | if (!info->dma) { | |
2df41d05 RK |
1730 | dev_err(&pdev->dev, "DMA engine request failed\n"); |
1731 | err = -ENXIO; | |
70ba6d71 | 1732 | goto return_error; |
763e7359 RK |
1733 | } else { |
1734 | struct dma_slave_config cfg; | |
763e7359 RK |
1735 | |
1736 | memset(&cfg, 0, sizeof(cfg)); | |
1737 | cfg.src_addr = info->phys_base; | |
1738 | cfg.dst_addr = info->phys_base; | |
1739 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1740 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1741 | cfg.src_maxburst = 16; | |
1742 | cfg.dst_maxburst = 16; | |
d680e2c1 AB |
1743 | err = dmaengine_slave_config(info->dma, &cfg); |
1744 | if (err) { | |
763e7359 | 1745 | dev_err(&pdev->dev, "DMA engine slave config failed: %d\n", |
d680e2c1 | 1746 | err); |
70ba6d71 | 1747 | goto return_error; |
763e7359 | 1748 | } |
633deb58 PG |
1749 | nand_chip->read_buf = omap_read_buf_dma_pref; |
1750 | nand_chip->write_buf = omap_write_buf_dma_pref; | |
1b0b323c SG |
1751 | } |
1752 | break; | |
1753 | ||
4e070376 | 1754 | case NAND_OMAP_PREFETCH_IRQ: |
5c468455 AM |
1755 | info->gpmc_irq_fifo = platform_get_irq(pdev, 0); |
1756 | if (info->gpmc_irq_fifo <= 0) { | |
1757 | dev_err(&pdev->dev, "error getting fifo irq\n"); | |
1758 | err = -ENODEV; | |
70ba6d71 | 1759 | goto return_error; |
5c468455 | 1760 | } |
70ba6d71 PG |
1761 | err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo, |
1762 | omap_nand_irq, IRQF_SHARED, | |
1763 | "gpmc-nand-fifo", info); | |
4e070376 SG |
1764 | if (err) { |
1765 | dev_err(&pdev->dev, "requesting irq(%d) error:%d", | |
5c468455 AM |
1766 | info->gpmc_irq_fifo, err); |
1767 | info->gpmc_irq_fifo = 0; | |
70ba6d71 | 1768 | goto return_error; |
5c468455 AM |
1769 | } |
1770 | ||
1771 | info->gpmc_irq_count = platform_get_irq(pdev, 1); | |
1772 | if (info->gpmc_irq_count <= 0) { | |
1773 | dev_err(&pdev->dev, "error getting count irq\n"); | |
1774 | err = -ENODEV; | |
70ba6d71 | 1775 | goto return_error; |
5c468455 | 1776 | } |
70ba6d71 PG |
1777 | err = devm_request_irq(&pdev->dev, info->gpmc_irq_count, |
1778 | omap_nand_irq, IRQF_SHARED, | |
1779 | "gpmc-nand-count", info); | |
5c468455 AM |
1780 | if (err) { |
1781 | dev_err(&pdev->dev, "requesting irq(%d) error:%d", | |
1782 | info->gpmc_irq_count, err); | |
1783 | info->gpmc_irq_count = 0; | |
70ba6d71 | 1784 | goto return_error; |
4e070376 | 1785 | } |
5c468455 | 1786 | |
633deb58 PG |
1787 | nand_chip->read_buf = omap_read_buf_irq_pref; |
1788 | nand_chip->write_buf = omap_write_buf_irq_pref; | |
5c468455 | 1789 | |
4e070376 SG |
1790 | break; |
1791 | ||
1b0b323c SG |
1792 | default: |
1793 | dev_err(&pdev->dev, | |
1794 | "xfer_type(%d) not supported!\n", pdata->xfer_type); | |
1795 | err = -EINVAL; | |
70ba6d71 | 1796 | goto return_error; |
59e9c5ae | 1797 | } |
59e9c5ae | 1798 | |
a919e511 | 1799 | /* populate MTD interface based on ECC scheme */ |
b491da72 PG |
1800 | nand_chip->ecc.layout = &omap_oobinfo; |
1801 | ecclayout = &omap_oobinfo; | |
4e558072 | 1802 | switch (info->ecc_opt) { |
a919e511 PG |
1803 | case OMAP_ECC_HAM1_CODE_HW: |
1804 | pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n"); | |
1805 | nand_chip->ecc.mode = NAND_ECC_HW; | |
633deb58 PG |
1806 | nand_chip->ecc.bytes = 3; |
1807 | nand_chip->ecc.size = 512; | |
1808 | nand_chip->ecc.strength = 1; | |
1809 | nand_chip->ecc.calculate = omap_calculate_ecc; | |
1810 | nand_chip->ecc.hwctl = omap_enable_hwecc; | |
1811 | nand_chip->ecc.correct = omap_correct_data; | |
b491da72 PG |
1812 | /* define ECC layout */ |
1813 | ecclayout->eccbytes = nand_chip->ecc.bytes * | |
1814 | (mtd->writesize / | |
1815 | nand_chip->ecc.size); | |
1816 | if (nand_chip->options & NAND_BUSWIDTH_16) | |
eae39cb4 | 1817 | oob_index = BADBLOCK_MARKER_LENGTH; |
b491da72 | 1818 | else |
eae39cb4 PG |
1819 | oob_index = 1; |
1820 | for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) | |
1821 | ecclayout->eccpos[i] = oob_index; | |
aa6092f9 PG |
1822 | /* no reserved-marker in ecclayout for this ecc-scheme */ |
1823 | ecclayout->oobfree->offset = | |
1824 | ecclayout->eccpos[ecclayout->eccbytes - 1] + 1; | |
a919e511 PG |
1825 | break; |
1826 | ||
1827 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: | |
1828 | #ifdef CONFIG_MTD_NAND_ECC_BCH | |
1829 | pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n"); | |
1830 | nand_chip->ecc.mode = NAND_ECC_HW; | |
1831 | nand_chip->ecc.size = 512; | |
1832 | nand_chip->ecc.bytes = 7; | |
1833 | nand_chip->ecc.strength = 4; | |
1834 | nand_chip->ecc.hwctl = omap3_enable_hwecc_bch; | |
32d42a85 | 1835 | nand_chip->ecc.correct = nand_bch_correct_data; |
a919e511 | 1836 | nand_chip->ecc.calculate = omap3_calculate_ecc_bch4; |
b491da72 PG |
1837 | /* define ECC layout */ |
1838 | ecclayout->eccbytes = nand_chip->ecc.bytes * | |
1839 | (mtd->writesize / | |
1840 | nand_chip->ecc.size); | |
eae39cb4 PG |
1841 | oob_index = BADBLOCK_MARKER_LENGTH; |
1842 | for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) { | |
1843 | ecclayout->eccpos[i] = oob_index; | |
1844 | if (((i + 1) % nand_chip->ecc.bytes) == 0) | |
1845 | oob_index++; | |
1846 | } | |
aa6092f9 PG |
1847 | /* include reserved-marker in ecclayout->oobfree calculation */ |
1848 | ecclayout->oobfree->offset = 1 + | |
1849 | ecclayout->eccpos[ecclayout->eccbytes - 1] + 1; | |
a919e511 | 1850 | /* software bch library is used for locating errors */ |
32d42a85 PG |
1851 | nand_chip->ecc.priv = nand_bch_init(mtd, |
1852 | nand_chip->ecc.size, | |
1853 | nand_chip->ecc.bytes, | |
1854 | &nand_chip->ecc.layout); | |
1855 | if (!nand_chip->ecc.priv) { | |
a919e511 | 1856 | pr_err("nand: error: unable to use s/w BCH library\n"); |
0e618ef0 | 1857 | err = -EINVAL; |
a919e511 PG |
1858 | } |
1859 | break; | |
1860 | #else | |
1861 | pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n"); | |
1862 | err = -EINVAL; | |
70ba6d71 | 1863 | goto return_error; |
a919e511 PG |
1864 | #endif |
1865 | ||
1866 | case OMAP_ECC_BCH4_CODE_HW: | |
1867 | #ifdef CONFIG_MTD_NAND_OMAP_BCH | |
1868 | pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n"); | |
1869 | nand_chip->ecc.mode = NAND_ECC_HW; | |
1870 | nand_chip->ecc.size = 512; | |
1871 | /* 14th bit is kept reserved for ROM-code compatibility */ | |
1872 | nand_chip->ecc.bytes = 7 + 1; | |
1873 | nand_chip->ecc.strength = 4; | |
1874 | nand_chip->ecc.hwctl = omap3_enable_hwecc_bch; | |
1875 | nand_chip->ecc.correct = omap_elm_correct_data; | |
a4c7ca00 | 1876 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; |
a919e511 PG |
1877 | nand_chip->ecc.read_page = omap_read_page_bch; |
1878 | nand_chip->ecc.write_page = omap_write_page_bch; | |
b491da72 PG |
1879 | /* define ECC layout */ |
1880 | ecclayout->eccbytes = nand_chip->ecc.bytes * | |
1881 | (mtd->writesize / | |
1882 | nand_chip->ecc.size); | |
eae39cb4 PG |
1883 | oob_index = BADBLOCK_MARKER_LENGTH; |
1884 | for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) | |
1885 | ecclayout->eccpos[i] = oob_index; | |
aa6092f9 PG |
1886 | /* reserved marker already included in ecclayout->eccbytes */ |
1887 | ecclayout->oobfree->offset = | |
1888 | ecclayout->eccpos[ecclayout->eccbytes - 1] + 1; | |
a919e511 PG |
1889 | /* This ECC scheme requires ELM H/W block */ |
1890 | if (is_elm_present(info, pdata->elm_of_node, BCH4_ECC) < 0) { | |
1891 | pr_err("nand: error: could not initialize ELM\n"); | |
1892 | err = -ENODEV; | |
70ba6d71 | 1893 | goto return_error; |
0e618ef0 | 1894 | } |
a919e511 PG |
1895 | break; |
1896 | #else | |
1897 | pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n"); | |
1898 | err = -EINVAL; | |
70ba6d71 | 1899 | goto return_error; |
a919e511 PG |
1900 | #endif |
1901 | ||
1902 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | |
1903 | #ifdef CONFIG_MTD_NAND_ECC_BCH | |
1904 | pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n"); | |
1905 | nand_chip->ecc.mode = NAND_ECC_HW; | |
1906 | nand_chip->ecc.size = 512; | |
1907 | nand_chip->ecc.bytes = 13; | |
1908 | nand_chip->ecc.strength = 8; | |
1909 | nand_chip->ecc.hwctl = omap3_enable_hwecc_bch; | |
32d42a85 | 1910 | nand_chip->ecc.correct = nand_bch_correct_data; |
a919e511 | 1911 | nand_chip->ecc.calculate = omap3_calculate_ecc_bch8; |
b491da72 PG |
1912 | /* define ECC layout */ |
1913 | ecclayout->eccbytes = nand_chip->ecc.bytes * | |
1914 | (mtd->writesize / | |
1915 | nand_chip->ecc.size); | |
eae39cb4 PG |
1916 | oob_index = BADBLOCK_MARKER_LENGTH; |
1917 | for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) { | |
1918 | ecclayout->eccpos[i] = oob_index; | |
1919 | if (((i + 1) % nand_chip->ecc.bytes) == 0) | |
1920 | oob_index++; | |
1921 | } | |
aa6092f9 PG |
1922 | /* include reserved-marker in ecclayout->oobfree calculation */ |
1923 | ecclayout->oobfree->offset = 1 + | |
1924 | ecclayout->eccpos[ecclayout->eccbytes - 1] + 1; | |
a919e511 | 1925 | /* software bch library is used for locating errors */ |
32d42a85 PG |
1926 | nand_chip->ecc.priv = nand_bch_init(mtd, |
1927 | nand_chip->ecc.size, | |
1928 | nand_chip->ecc.bytes, | |
1929 | &nand_chip->ecc.layout); | |
1930 | if (!nand_chip->ecc.priv) { | |
a919e511 PG |
1931 | pr_err("nand: error: unable to use s/w BCH library\n"); |
1932 | err = -EINVAL; | |
70ba6d71 | 1933 | goto return_error; |
a919e511 PG |
1934 | } |
1935 | break; | |
1936 | #else | |
1937 | pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n"); | |
1938 | err = -EINVAL; | |
70ba6d71 | 1939 | goto return_error; |
a919e511 PG |
1940 | #endif |
1941 | ||
1942 | case OMAP_ECC_BCH8_CODE_HW: | |
1943 | #ifdef CONFIG_MTD_NAND_OMAP_BCH | |
1944 | pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n"); | |
1945 | nand_chip->ecc.mode = NAND_ECC_HW; | |
1946 | nand_chip->ecc.size = 512; | |
1947 | /* 14th bit is kept reserved for ROM-code compatibility */ | |
1948 | nand_chip->ecc.bytes = 13 + 1; | |
1949 | nand_chip->ecc.strength = 8; | |
1950 | nand_chip->ecc.hwctl = omap3_enable_hwecc_bch; | |
1951 | nand_chip->ecc.correct = omap_elm_correct_data; | |
a4c7ca00 | 1952 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; |
a919e511 PG |
1953 | nand_chip->ecc.read_page = omap_read_page_bch; |
1954 | nand_chip->ecc.write_page = omap_write_page_bch; | |
1955 | /* This ECC scheme requires ELM H/W block */ | |
9211439b WY |
1956 | err = is_elm_present(info, pdata->elm_of_node, BCH8_ECC); |
1957 | if (err < 0) { | |
a919e511 | 1958 | pr_err("nand: error: could not initialize ELM\n"); |
70ba6d71 | 1959 | goto return_error; |
a919e511 | 1960 | } |
b491da72 PG |
1961 | /* define ECC layout */ |
1962 | ecclayout->eccbytes = nand_chip->ecc.bytes * | |
1963 | (mtd->writesize / | |
1964 | nand_chip->ecc.size); | |
eae39cb4 PG |
1965 | oob_index = BADBLOCK_MARKER_LENGTH; |
1966 | for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) | |
1967 | ecclayout->eccpos[i] = oob_index; | |
aa6092f9 PG |
1968 | /* reserved marker already included in ecclayout->eccbytes */ |
1969 | ecclayout->oobfree->offset = | |
1970 | ecclayout->eccpos[ecclayout->eccbytes - 1] + 1; | |
a919e511 PG |
1971 | break; |
1972 | #else | |
1973 | pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n"); | |
1974 | err = -EINVAL; | |
70ba6d71 | 1975 | goto return_error; |
a919e511 PG |
1976 | #endif |
1977 | ||
1978 | default: | |
1979 | pr_err("nand: error: invalid or unsupported ECC scheme\n"); | |
1980 | err = -EINVAL; | |
70ba6d71 | 1981 | goto return_error; |
f3d73f36 | 1982 | } |
67ce04bf | 1983 | |
bb38eefb PG |
1984 | /* all OOB bytes from oobfree->offset till end off OOB are free */ |
1985 | ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset; | |
b491da72 PG |
1986 | /* check if NAND device's OOB is enough to store ECC signatures */ |
1987 | if (mtd->oobsize < (ecclayout->eccbytes + BADBLOCK_MARKER_LENGTH)) { | |
1988 | pr_err("not enough OOB bytes required = %d, available=%d\n", | |
1989 | ecclayout->eccbytes, mtd->oobsize); | |
1990 | err = -EINVAL; | |
70ba6d71 | 1991 | goto return_error; |
f040d332 | 1992 | } |
1b0b323c | 1993 | |
a80f1c1f | 1994 | /* second phase scan */ |
633deb58 | 1995 | if (nand_scan_tail(mtd)) { |
a80f1c1f | 1996 | err = -ENXIO; |
70ba6d71 | 1997 | goto return_error; |
a80f1c1f JW |
1998 | } |
1999 | ||
ccf04c51 | 2000 | ppdata.of_node = pdata->of_node; |
633deb58 | 2001 | mtd_device_parse_register(mtd, NULL, &ppdata, pdata->parts, |
42d7fbe2 | 2002 | pdata->nr_parts); |
67ce04bf | 2003 | |
633deb58 | 2004 | platform_set_drvdata(pdev, mtd); |
67ce04bf VS |
2005 | |
2006 | return 0; | |
2007 | ||
70ba6d71 | 2008 | return_error: |
763e7359 RK |
2009 | if (info->dma) |
2010 | dma_release_channel(info->dma); | |
32d42a85 PG |
2011 | if (nand_chip->ecc.priv) { |
2012 | nand_bch_free(nand_chip->ecc.priv); | |
2013 | nand_chip->ecc.priv = NULL; | |
2014 | } | |
67ce04bf VS |
2015 | return err; |
2016 | } | |
2017 | ||
2018 | static int omap_nand_remove(struct platform_device *pdev) | |
2019 | { | |
2020 | struct mtd_info *mtd = platform_get_drvdata(pdev); | |
633deb58 | 2021 | struct nand_chip *nand_chip = mtd->priv; |
f35b6eda VS |
2022 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
2023 | mtd); | |
32d42a85 PG |
2024 | if (nand_chip->ecc.priv) { |
2025 | nand_bch_free(nand_chip->ecc.priv); | |
2026 | nand_chip->ecc.priv = NULL; | |
2027 | } | |
763e7359 RK |
2028 | if (info->dma) |
2029 | dma_release_channel(info->dma); | |
633deb58 | 2030 | nand_release(mtd); |
67ce04bf VS |
2031 | return 0; |
2032 | } | |
2033 | ||
2034 | static struct platform_driver omap_nand_driver = { | |
2035 | .probe = omap_nand_probe, | |
2036 | .remove = omap_nand_remove, | |
2037 | .driver = { | |
2038 | .name = DRIVER_NAME, | |
2039 | .owner = THIS_MODULE, | |
2040 | }, | |
2041 | }; | |
2042 | ||
f99640de | 2043 | module_platform_driver(omap_nand_driver); |
67ce04bf | 2044 | |
c804c733 | 2045 | MODULE_ALIAS("platform:" DRIVER_NAME); |
67ce04bf VS |
2046 | MODULE_LICENSE("GPL"); |
2047 | MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards"); |