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67ce04bf VS |
1 | /* |
2 | * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com> | |
3 | * Copyright © 2004 Micron Technology Inc. | |
4 | * Copyright © 2004 David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/platform_device.h> | |
763e7359 | 12 | #include <linux/dmaengine.h> |
67ce04bf VS |
13 | #include <linux/dma-mapping.h> |
14 | #include <linux/delay.h> | |
a0e5cc58 | 15 | #include <linux/module.h> |
4e070376 | 16 | #include <linux/interrupt.h> |
c276aca4 | 17 | #include <linux/jiffies.h> |
18 | #include <linux/sched.h> | |
67ce04bf VS |
19 | #include <linux/mtd/mtd.h> |
20 | #include <linux/mtd/nand.h> | |
21 | #include <linux/mtd/partitions.h> | |
763e7359 | 22 | #include <linux/omap-dma.h> |
67ce04bf | 23 | #include <linux/io.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
62116e51 PA |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
67ce04bf | 27 | |
0e618ef0 | 28 | #include <linux/bch.h> |
62116e51 | 29 | #include <linux/platform_data/elm.h> |
0e618ef0 | 30 | |
2203747c | 31 | #include <linux/platform_data/mtd-nand-omap2.h> |
67ce04bf | 32 | |
67ce04bf | 33 | #define DRIVER_NAME "omap2-nand" |
4e070376 | 34 | #define OMAP_NAND_TIMEOUT_MS 5000 |
67ce04bf | 35 | |
67ce04bf VS |
36 | #define NAND_Ecc_P1e (1 << 0) |
37 | #define NAND_Ecc_P2e (1 << 1) | |
38 | #define NAND_Ecc_P4e (1 << 2) | |
39 | #define NAND_Ecc_P8e (1 << 3) | |
40 | #define NAND_Ecc_P16e (1 << 4) | |
41 | #define NAND_Ecc_P32e (1 << 5) | |
42 | #define NAND_Ecc_P64e (1 << 6) | |
43 | #define NAND_Ecc_P128e (1 << 7) | |
44 | #define NAND_Ecc_P256e (1 << 8) | |
45 | #define NAND_Ecc_P512e (1 << 9) | |
46 | #define NAND_Ecc_P1024e (1 << 10) | |
47 | #define NAND_Ecc_P2048e (1 << 11) | |
48 | ||
49 | #define NAND_Ecc_P1o (1 << 16) | |
50 | #define NAND_Ecc_P2o (1 << 17) | |
51 | #define NAND_Ecc_P4o (1 << 18) | |
52 | #define NAND_Ecc_P8o (1 << 19) | |
53 | #define NAND_Ecc_P16o (1 << 20) | |
54 | #define NAND_Ecc_P32o (1 << 21) | |
55 | #define NAND_Ecc_P64o (1 << 22) | |
56 | #define NAND_Ecc_P128o (1 << 23) | |
57 | #define NAND_Ecc_P256o (1 << 24) | |
58 | #define NAND_Ecc_P512o (1 << 25) | |
59 | #define NAND_Ecc_P1024o (1 << 26) | |
60 | #define NAND_Ecc_P2048o (1 << 27) | |
61 | ||
62 | #define TF(value) (value ? 1 : 0) | |
63 | ||
64 | #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0) | |
65 | #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1) | |
66 | #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2) | |
67 | #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3) | |
68 | #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4) | |
69 | #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5) | |
70 | #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6) | |
71 | #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7) | |
72 | ||
73 | #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0) | |
74 | #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1) | |
75 | #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2) | |
76 | #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3) | |
77 | #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4) | |
78 | #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5) | |
79 | #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6) | |
80 | #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7) | |
81 | ||
82 | #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0) | |
83 | #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1) | |
84 | #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2) | |
85 | #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3) | |
86 | #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4) | |
87 | #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5) | |
88 | #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6) | |
89 | #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7) | |
90 | ||
91 | #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0) | |
92 | #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1) | |
93 | #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2) | |
94 | #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3) | |
95 | #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4) | |
96 | #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5) | |
97 | #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6) | |
98 | #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7) | |
99 | ||
100 | #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) | |
101 | #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) | |
102 | ||
65b97cf6 AM |
103 | #define PREFETCH_CONFIG1_CS_SHIFT 24 |
104 | #define ECC_CONFIG_CS_SHIFT 1 | |
105 | #define CS_MASK 0x7 | |
106 | #define ENABLE_PREFETCH (0x1 << 7) | |
107 | #define DMA_MPU_MODE_SHIFT 2 | |
2ef9f3dd | 108 | #define ECCSIZE0_SHIFT 12 |
65b97cf6 AM |
109 | #define ECCSIZE1_SHIFT 22 |
110 | #define ECC1RESULTSIZE 0x1 | |
111 | #define ECCCLEAR 0x100 | |
112 | #define ECC1 0x1 | |
47f88af4 AM |
113 | #define PREFETCH_FIFOTHRESHOLD_MAX 0x40 |
114 | #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) | |
115 | #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) | |
116 | #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) | |
117 | #define STATUS_BUFF_EMPTY 0x00000001 | |
65b97cf6 | 118 | |
d5e7c864 LV |
119 | #define OMAP24XX_DMA_GPMC 4 |
120 | ||
c3e4b995 PA |
121 | #define BCH8_MAX_ERROR 8 /* upto 8 bit correctable */ |
122 | #define BCH4_MAX_ERROR 4 /* upto 4 bit correctable */ | |
123 | ||
62116e51 PA |
124 | #define SECTOR_BYTES 512 |
125 | /* 4 bit padding to make byte aligned, 56 = 52 + 4 */ | |
126 | #define BCH4_BIT_PAD 4 | |
127 | #define BCH8_ECC_MAX ((SECTOR_BYTES + BCH8_ECC_OOB_BYTES) * 8) | |
128 | #define BCH4_ECC_MAX ((SECTOR_BYTES + BCH4_ECC_OOB_BYTES) * 8) | |
129 | ||
130 | /* GPMC ecc engine settings for read */ | |
131 | #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */ | |
132 | #define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */ | |
133 | #define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */ | |
134 | #define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */ | |
135 | #define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */ | |
136 | ||
137 | /* GPMC ecc engine settings for write */ | |
138 | #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */ | |
139 | #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */ | |
140 | #define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */ | |
141 | ||
a919e511 PG |
142 | #define OMAP_ECC_BCH8_POLYNOMIAL 0x201b |
143 | ||
62116e51 PA |
144 | #ifdef CONFIG_MTD_NAND_OMAP_BCH |
145 | static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc, | |
146 | 0xac, 0x6b, 0xff, 0x99, 0x7b}; | |
147 | static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10}; | |
148 | #endif | |
149 | ||
f040d332 SG |
150 | /* oob info generated runtime depending on ecc algorithm and layout selected */ |
151 | static struct nand_ecclayout omap_oobinfo; | |
152 | /* Define some generic bad / good block scan pattern which are used | |
153 | * while scanning a device for factory marked good / bad blocks | |
154 | */ | |
155 | static uint8_t scan_ff_pattern[] = { 0xff }; | |
156 | static struct nand_bbt_descr bb_descrip_flashbased = { | |
dad22562 | 157 | .options = NAND_BBT_SCANALLPAGES, |
f040d332 SG |
158 | .offs = 0, |
159 | .len = 1, | |
160 | .pattern = scan_ff_pattern, | |
161 | }; | |
dfe32893 | 162 | |
59e9c5ae | 163 | |
67ce04bf VS |
164 | struct omap_nand_info { |
165 | struct nand_hw_control controller; | |
166 | struct omap_nand_platform_data *pdata; | |
167 | struct mtd_info mtd; | |
67ce04bf VS |
168 | struct nand_chip nand; |
169 | struct platform_device *pdev; | |
170 | ||
171 | int gpmc_cs; | |
172 | unsigned long phys_base; | |
9c4c2f8b | 173 | unsigned long mem_size; |
dfe32893 | 174 | struct completion comp; |
763e7359 | 175 | struct dma_chan *dma; |
5c468455 AM |
176 | int gpmc_irq_fifo; |
177 | int gpmc_irq_count; | |
4e070376 SG |
178 | enum { |
179 | OMAP_NAND_IO_READ = 0, /* read */ | |
180 | OMAP_NAND_IO_WRITE, /* write */ | |
181 | } iomode; | |
182 | u_char *buf; | |
183 | int buf_len; | |
65b97cf6 | 184 | struct gpmc_nand_regs reg; |
a919e511 | 185 | /* fields specific for BCHx_HW ECC scheme */ |
0e618ef0 ID |
186 | struct bch_control *bch; |
187 | struct nand_ecclayout ecclayout; | |
62116e51 PA |
188 | bool is_elm_used; |
189 | struct device *elm_dev; | |
190 | struct device_node *of_node; | |
67ce04bf VS |
191 | }; |
192 | ||
65b97cf6 AM |
193 | /** |
194 | * omap_prefetch_enable - configures and starts prefetch transfer | |
195 | * @cs: cs (chip select) number | |
196 | * @fifo_th: fifo threshold to be used for read/ write | |
197 | * @dma_mode: dma mode enable (1) or disable (0) | |
198 | * @u32_count: number of bytes to be transferred | |
199 | * @is_write: prefetch read(0) or write post(1) mode | |
200 | */ | |
201 | static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode, | |
202 | unsigned int u32_count, int is_write, struct omap_nand_info *info) | |
203 | { | |
204 | u32 val; | |
205 | ||
206 | if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) | |
207 | return -1; | |
208 | ||
209 | if (readl(info->reg.gpmc_prefetch_control)) | |
210 | return -EBUSY; | |
211 | ||
212 | /* Set the amount of bytes to be prefetched */ | |
213 | writel(u32_count, info->reg.gpmc_prefetch_config2); | |
214 | ||
215 | /* Set dma/mpu mode, the prefetch read / post write and | |
216 | * enable the engine. Set which cs is has requested for. | |
217 | */ | |
218 | val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) | | |
219 | PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH | | |
220 | (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write)); | |
221 | writel(val, info->reg.gpmc_prefetch_config1); | |
222 | ||
223 | /* Start the prefetch engine */ | |
224 | writel(0x1, info->reg.gpmc_prefetch_control); | |
225 | ||
226 | return 0; | |
227 | } | |
228 | ||
229 | /** | |
230 | * omap_prefetch_reset - disables and stops the prefetch engine | |
231 | */ | |
232 | static int omap_prefetch_reset(int cs, struct omap_nand_info *info) | |
233 | { | |
234 | u32 config1; | |
235 | ||
236 | /* check if the same module/cs is trying to reset */ | |
237 | config1 = readl(info->reg.gpmc_prefetch_config1); | |
238 | if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs) | |
239 | return -EINVAL; | |
240 | ||
241 | /* Stop the PFPW engine */ | |
242 | writel(0x0, info->reg.gpmc_prefetch_control); | |
243 | ||
244 | /* Reset/disable the PFPW engine */ | |
245 | writel(0x0, info->reg.gpmc_prefetch_config1); | |
246 | ||
247 | return 0; | |
248 | } | |
249 | ||
67ce04bf VS |
250 | /** |
251 | * omap_hwcontrol - hardware specific access to control-lines | |
252 | * @mtd: MTD device structure | |
253 | * @cmd: command to device | |
254 | * @ctrl: | |
255 | * NAND_NCE: bit 0 -> don't care | |
256 | * NAND_CLE: bit 1 -> Command Latch | |
257 | * NAND_ALE: bit 2 -> Address Latch | |
258 | * | |
259 | * NOTE: boards may use different bits for these!! | |
260 | */ | |
261 | static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
262 | { | |
263 | struct omap_nand_info *info = container_of(mtd, | |
264 | struct omap_nand_info, mtd); | |
67ce04bf | 265 | |
2c01946c SG |
266 | if (cmd != NAND_CMD_NONE) { |
267 | if (ctrl & NAND_CLE) | |
65b97cf6 | 268 | writeb(cmd, info->reg.gpmc_nand_command); |
2c01946c SG |
269 | |
270 | else if (ctrl & NAND_ALE) | |
65b97cf6 | 271 | writeb(cmd, info->reg.gpmc_nand_address); |
2c01946c SG |
272 | |
273 | else /* NAND_NCE */ | |
65b97cf6 | 274 | writeb(cmd, info->reg.gpmc_nand_data); |
2c01946c | 275 | } |
67ce04bf VS |
276 | } |
277 | ||
59e9c5ae | 278 | /** |
279 | * omap_read_buf8 - read data from NAND controller into buffer | |
280 | * @mtd: MTD device structure | |
281 | * @buf: buffer to store date | |
282 | * @len: number of bytes to read | |
283 | */ | |
284 | static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len) | |
285 | { | |
286 | struct nand_chip *nand = mtd->priv; | |
287 | ||
288 | ioread8_rep(nand->IO_ADDR_R, buf, len); | |
289 | } | |
290 | ||
291 | /** | |
292 | * omap_write_buf8 - write buffer to NAND controller | |
293 | * @mtd: MTD device structure | |
294 | * @buf: data buffer | |
295 | * @len: number of bytes to write | |
296 | */ | |
297 | static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len) | |
298 | { | |
299 | struct omap_nand_info *info = container_of(mtd, | |
300 | struct omap_nand_info, mtd); | |
301 | u_char *p = (u_char *)buf; | |
2c01946c | 302 | u32 status = 0; |
59e9c5ae | 303 | |
304 | while (len--) { | |
305 | iowrite8(*p++, info->nand.IO_ADDR_W); | |
2c01946c SG |
306 | /* wait until buffer is available for write */ |
307 | do { | |
65b97cf6 | 308 | status = readl(info->reg.gpmc_status) & |
47f88af4 | 309 | STATUS_BUFF_EMPTY; |
2c01946c | 310 | } while (!status); |
59e9c5ae | 311 | } |
312 | } | |
313 | ||
67ce04bf VS |
314 | /** |
315 | * omap_read_buf16 - read data from NAND controller into buffer | |
316 | * @mtd: MTD device structure | |
317 | * @buf: buffer to store date | |
318 | * @len: number of bytes to read | |
319 | */ | |
320 | static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len) | |
321 | { | |
322 | struct nand_chip *nand = mtd->priv; | |
323 | ||
59e9c5ae | 324 | ioread16_rep(nand->IO_ADDR_R, buf, len / 2); |
67ce04bf VS |
325 | } |
326 | ||
327 | /** | |
328 | * omap_write_buf16 - write buffer to NAND controller | |
329 | * @mtd: MTD device structure | |
330 | * @buf: data buffer | |
331 | * @len: number of bytes to write | |
332 | */ | |
333 | static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len) | |
334 | { | |
335 | struct omap_nand_info *info = container_of(mtd, | |
336 | struct omap_nand_info, mtd); | |
337 | u16 *p = (u16 *) buf; | |
2c01946c | 338 | u32 status = 0; |
67ce04bf VS |
339 | /* FIXME try bursts of writesw() or DMA ... */ |
340 | len >>= 1; | |
341 | ||
342 | while (len--) { | |
59e9c5ae | 343 | iowrite16(*p++, info->nand.IO_ADDR_W); |
2c01946c SG |
344 | /* wait until buffer is available for write */ |
345 | do { | |
65b97cf6 | 346 | status = readl(info->reg.gpmc_status) & |
47f88af4 | 347 | STATUS_BUFF_EMPTY; |
2c01946c | 348 | } while (!status); |
67ce04bf VS |
349 | } |
350 | } | |
59e9c5ae | 351 | |
352 | /** | |
353 | * omap_read_buf_pref - read data from NAND controller into buffer | |
354 | * @mtd: MTD device structure | |
355 | * @buf: buffer to store date | |
356 | * @len: number of bytes to read | |
357 | */ | |
358 | static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) | |
359 | { | |
360 | struct omap_nand_info *info = container_of(mtd, | |
361 | struct omap_nand_info, mtd); | |
2c01946c | 362 | uint32_t r_count = 0; |
59e9c5ae | 363 | int ret = 0; |
364 | u32 *p = (u32 *)buf; | |
365 | ||
366 | /* take care of subpage reads */ | |
c3341d0c VS |
367 | if (len % 4) { |
368 | if (info->nand.options & NAND_BUSWIDTH_16) | |
369 | omap_read_buf16(mtd, buf, len % 4); | |
370 | else | |
371 | omap_read_buf8(mtd, buf, len % 4); | |
372 | p = (u32 *) (buf + len % 4); | |
373 | len -= len % 4; | |
59e9c5ae | 374 | } |
59e9c5ae | 375 | |
376 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
377 | ret = omap_prefetch_enable(info->gpmc_cs, |
378 | PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info); | |
59e9c5ae | 379 | if (ret) { |
380 | /* PFPW engine is busy, use cpu copy method */ | |
381 | if (info->nand.options & NAND_BUSWIDTH_16) | |
c5d8c0ca | 382 | omap_read_buf16(mtd, (u_char *)p, len); |
59e9c5ae | 383 | else |
c5d8c0ca | 384 | omap_read_buf8(mtd, (u_char *)p, len); |
59e9c5ae | 385 | } else { |
386 | do { | |
65b97cf6 | 387 | r_count = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 388 | r_count = PREFETCH_STATUS_FIFO_CNT(r_count); |
2c01946c SG |
389 | r_count = r_count >> 2; |
390 | ioread32_rep(info->nand.IO_ADDR_R, p, r_count); | |
59e9c5ae | 391 | p += r_count; |
392 | len -= r_count << 2; | |
393 | } while (len); | |
59e9c5ae | 394 | /* disable and stop the PFPW engine */ |
65b97cf6 | 395 | omap_prefetch_reset(info->gpmc_cs, info); |
59e9c5ae | 396 | } |
397 | } | |
398 | ||
399 | /** | |
400 | * omap_write_buf_pref - write buffer to NAND controller | |
401 | * @mtd: MTD device structure | |
402 | * @buf: data buffer | |
403 | * @len: number of bytes to write | |
404 | */ | |
405 | static void omap_write_buf_pref(struct mtd_info *mtd, | |
406 | const u_char *buf, int len) | |
407 | { | |
408 | struct omap_nand_info *info = container_of(mtd, | |
409 | struct omap_nand_info, mtd); | |
4e070376 | 410 | uint32_t w_count = 0; |
59e9c5ae | 411 | int i = 0, ret = 0; |
c5d8c0ca | 412 | u16 *p = (u16 *)buf; |
4e070376 | 413 | unsigned long tim, limit; |
65b97cf6 | 414 | u32 val; |
59e9c5ae | 415 | |
416 | /* take care of subpage writes */ | |
417 | if (len % 2 != 0) { | |
2c01946c | 418 | writeb(*buf, info->nand.IO_ADDR_W); |
59e9c5ae | 419 | p = (u16 *)(buf + 1); |
420 | len--; | |
421 | } | |
422 | ||
423 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
424 | ret = omap_prefetch_enable(info->gpmc_cs, |
425 | PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info); | |
59e9c5ae | 426 | if (ret) { |
427 | /* PFPW engine is busy, use cpu copy method */ | |
428 | if (info->nand.options & NAND_BUSWIDTH_16) | |
c5d8c0ca | 429 | omap_write_buf16(mtd, (u_char *)p, len); |
59e9c5ae | 430 | else |
c5d8c0ca | 431 | omap_write_buf8(mtd, (u_char *)p, len); |
59e9c5ae | 432 | } else { |
2c01946c | 433 | while (len) { |
65b97cf6 | 434 | w_count = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 435 | w_count = PREFETCH_STATUS_FIFO_CNT(w_count); |
2c01946c | 436 | w_count = w_count >> 1; |
59e9c5ae | 437 | for (i = 0; (i < w_count) && len; i++, len -= 2) |
2c01946c | 438 | iowrite16(*p++, info->nand.IO_ADDR_W); |
59e9c5ae | 439 | } |
2c01946c | 440 | /* wait for data to flushed-out before reset the prefetch */ |
4e070376 SG |
441 | tim = 0; |
442 | limit = (loops_per_jiffy * | |
443 | msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 | 444 | do { |
4e070376 | 445 | cpu_relax(); |
65b97cf6 | 446 | val = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 447 | val = PREFETCH_STATUS_COUNT(val); |
65b97cf6 | 448 | } while (val && (tim++ < limit)); |
4e070376 | 449 | |
59e9c5ae | 450 | /* disable and stop the PFPW engine */ |
65b97cf6 | 451 | omap_prefetch_reset(info->gpmc_cs, info); |
59e9c5ae | 452 | } |
453 | } | |
454 | ||
dfe32893 | 455 | /* |
2df41d05 | 456 | * omap_nand_dma_callback: callback on the completion of dma transfer |
dfe32893 | 457 | * @data: pointer to completion data structure |
458 | */ | |
763e7359 RK |
459 | static void omap_nand_dma_callback(void *data) |
460 | { | |
461 | complete((struct completion *) data); | |
462 | } | |
dfe32893 | 463 | |
464 | /* | |
4cacbe22 | 465 | * omap_nand_dma_transfer: configure and start dma transfer |
dfe32893 | 466 | * @mtd: MTD device structure |
467 | * @addr: virtual address in RAM of source/destination | |
468 | * @len: number of data bytes to be transferred | |
469 | * @is_write: flag for read/write operation | |
470 | */ | |
471 | static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, | |
472 | unsigned int len, int is_write) | |
473 | { | |
474 | struct omap_nand_info *info = container_of(mtd, | |
475 | struct omap_nand_info, mtd); | |
2df41d05 | 476 | struct dma_async_tx_descriptor *tx; |
dfe32893 | 477 | enum dma_data_direction dir = is_write ? DMA_TO_DEVICE : |
478 | DMA_FROM_DEVICE; | |
2df41d05 | 479 | struct scatterlist sg; |
4e070376 | 480 | unsigned long tim, limit; |
2df41d05 RK |
481 | unsigned n; |
482 | int ret; | |
65b97cf6 | 483 | u32 val; |
dfe32893 | 484 | |
485 | if (addr >= high_memory) { | |
486 | struct page *p1; | |
487 | ||
488 | if (((size_t)addr & PAGE_MASK) != | |
489 | ((size_t)(addr + len - 1) & PAGE_MASK)) | |
490 | goto out_copy; | |
491 | p1 = vmalloc_to_page(addr); | |
492 | if (!p1) | |
493 | goto out_copy; | |
494 | addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK); | |
495 | } | |
496 | ||
2df41d05 RK |
497 | sg_init_one(&sg, addr, len); |
498 | n = dma_map_sg(info->dma->device->dev, &sg, 1, dir); | |
499 | if (n == 0) { | |
dfe32893 | 500 | dev_err(&info->pdev->dev, |
501 | "Couldn't DMA map a %d byte buffer\n", len); | |
502 | goto out_copy; | |
503 | } | |
504 | ||
2df41d05 RK |
505 | tx = dmaengine_prep_slave_sg(info->dma, &sg, n, |
506 | is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, | |
507 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
508 | if (!tx) | |
509 | goto out_copy_unmap; | |
510 | ||
511 | tx->callback = omap_nand_dma_callback; | |
512 | tx->callback_param = &info->comp; | |
513 | dmaengine_submit(tx); | |
514 | ||
65b97cf6 AM |
515 | /* configure and start prefetch transfer */ |
516 | ret = omap_prefetch_enable(info->gpmc_cs, | |
517 | PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info); | |
dfe32893 | 518 | if (ret) |
4e070376 | 519 | /* PFPW engine is busy, use cpu copy method */ |
d7efe228 | 520 | goto out_copy_unmap; |
dfe32893 | 521 | |
522 | init_completion(&info->comp); | |
2df41d05 | 523 | dma_async_issue_pending(info->dma); |
dfe32893 | 524 | |
525 | /* setup and start DMA using dma_addr */ | |
526 | wait_for_completion(&info->comp); | |
4e070376 SG |
527 | tim = 0; |
528 | limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 AM |
529 | |
530 | do { | |
4e070376 | 531 | cpu_relax(); |
65b97cf6 | 532 | val = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 533 | val = PREFETCH_STATUS_COUNT(val); |
65b97cf6 | 534 | } while (val && (tim++ < limit)); |
dfe32893 | 535 | |
dfe32893 | 536 | /* disable and stop the PFPW engine */ |
65b97cf6 | 537 | omap_prefetch_reset(info->gpmc_cs, info); |
dfe32893 | 538 | |
2df41d05 | 539 | dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); |
dfe32893 | 540 | return 0; |
541 | ||
d7efe228 | 542 | out_copy_unmap: |
2df41d05 | 543 | dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); |
dfe32893 | 544 | out_copy: |
545 | if (info->nand.options & NAND_BUSWIDTH_16) | |
546 | is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len) | |
547 | : omap_write_buf16(mtd, (u_char *) addr, len); | |
548 | else | |
549 | is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len) | |
550 | : omap_write_buf8(mtd, (u_char *) addr, len); | |
551 | return 0; | |
552 | } | |
dfe32893 | 553 | |
554 | /** | |
555 | * omap_read_buf_dma_pref - read data from NAND controller into buffer | |
556 | * @mtd: MTD device structure | |
557 | * @buf: buffer to store date | |
558 | * @len: number of bytes to read | |
559 | */ | |
560 | static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len) | |
561 | { | |
562 | if (len <= mtd->oobsize) | |
563 | omap_read_buf_pref(mtd, buf, len); | |
564 | else | |
565 | /* start transfer in DMA mode */ | |
566 | omap_nand_dma_transfer(mtd, buf, len, 0x0); | |
567 | } | |
568 | ||
569 | /** | |
570 | * omap_write_buf_dma_pref - write buffer to NAND controller | |
571 | * @mtd: MTD device structure | |
572 | * @buf: data buffer | |
573 | * @len: number of bytes to write | |
574 | */ | |
575 | static void omap_write_buf_dma_pref(struct mtd_info *mtd, | |
576 | const u_char *buf, int len) | |
577 | { | |
578 | if (len <= mtd->oobsize) | |
579 | omap_write_buf_pref(mtd, buf, len); | |
580 | else | |
581 | /* start transfer in DMA mode */ | |
bdaefc41 | 582 | omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1); |
dfe32893 | 583 | } |
584 | ||
4e070376 | 585 | /* |
4cacbe22 | 586 | * omap_nand_irq - GPMC irq handler |
4e070376 SG |
587 | * @this_irq: gpmc irq number |
588 | * @dev: omap_nand_info structure pointer is passed here | |
589 | */ | |
590 | static irqreturn_t omap_nand_irq(int this_irq, void *dev) | |
591 | { | |
592 | struct omap_nand_info *info = (struct omap_nand_info *) dev; | |
593 | u32 bytes; | |
4e070376 | 594 | |
65b97cf6 | 595 | bytes = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 596 | bytes = PREFETCH_STATUS_FIFO_CNT(bytes); |
4e070376 SG |
597 | bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ |
598 | if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ | |
5c468455 | 599 | if (this_irq == info->gpmc_irq_count) |
4e070376 SG |
600 | goto done; |
601 | ||
602 | if (info->buf_len && (info->buf_len < bytes)) | |
603 | bytes = info->buf_len; | |
604 | else if (!info->buf_len) | |
605 | bytes = 0; | |
606 | iowrite32_rep(info->nand.IO_ADDR_W, | |
607 | (u32 *)info->buf, bytes >> 2); | |
608 | info->buf = info->buf + bytes; | |
609 | info->buf_len -= bytes; | |
610 | ||
611 | } else { | |
612 | ioread32_rep(info->nand.IO_ADDR_R, | |
613 | (u32 *)info->buf, bytes >> 2); | |
614 | info->buf = info->buf + bytes; | |
615 | ||
5c468455 | 616 | if (this_irq == info->gpmc_irq_count) |
4e070376 SG |
617 | goto done; |
618 | } | |
4e070376 SG |
619 | |
620 | return IRQ_HANDLED; | |
621 | ||
622 | done: | |
623 | complete(&info->comp); | |
4e070376 | 624 | |
5c468455 AM |
625 | disable_irq_nosync(info->gpmc_irq_fifo); |
626 | disable_irq_nosync(info->gpmc_irq_count); | |
4e070376 SG |
627 | |
628 | return IRQ_HANDLED; | |
629 | } | |
630 | ||
631 | /* | |
632 | * omap_read_buf_irq_pref - read data from NAND controller into buffer | |
633 | * @mtd: MTD device structure | |
634 | * @buf: buffer to store date | |
635 | * @len: number of bytes to read | |
636 | */ | |
637 | static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) | |
638 | { | |
639 | struct omap_nand_info *info = container_of(mtd, | |
640 | struct omap_nand_info, mtd); | |
641 | int ret = 0; | |
642 | ||
643 | if (len <= mtd->oobsize) { | |
644 | omap_read_buf_pref(mtd, buf, len); | |
645 | return; | |
646 | } | |
647 | ||
648 | info->iomode = OMAP_NAND_IO_READ; | |
649 | info->buf = buf; | |
650 | init_completion(&info->comp); | |
651 | ||
652 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
653 | ret = omap_prefetch_enable(info->gpmc_cs, |
654 | PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info); | |
4e070376 SG |
655 | if (ret) |
656 | /* PFPW engine is busy, use cpu copy method */ | |
657 | goto out_copy; | |
658 | ||
659 | info->buf_len = len; | |
5c468455 AM |
660 | |
661 | enable_irq(info->gpmc_irq_count); | |
662 | enable_irq(info->gpmc_irq_fifo); | |
4e070376 SG |
663 | |
664 | /* waiting for read to complete */ | |
665 | wait_for_completion(&info->comp); | |
666 | ||
667 | /* disable and stop the PFPW engine */ | |
65b97cf6 | 668 | omap_prefetch_reset(info->gpmc_cs, info); |
4e070376 SG |
669 | return; |
670 | ||
671 | out_copy: | |
672 | if (info->nand.options & NAND_BUSWIDTH_16) | |
673 | omap_read_buf16(mtd, buf, len); | |
674 | else | |
675 | omap_read_buf8(mtd, buf, len); | |
676 | } | |
677 | ||
678 | /* | |
679 | * omap_write_buf_irq_pref - write buffer to NAND controller | |
680 | * @mtd: MTD device structure | |
681 | * @buf: data buffer | |
682 | * @len: number of bytes to write | |
683 | */ | |
684 | static void omap_write_buf_irq_pref(struct mtd_info *mtd, | |
685 | const u_char *buf, int len) | |
686 | { | |
687 | struct omap_nand_info *info = container_of(mtd, | |
688 | struct omap_nand_info, mtd); | |
689 | int ret = 0; | |
690 | unsigned long tim, limit; | |
65b97cf6 | 691 | u32 val; |
4e070376 SG |
692 | |
693 | if (len <= mtd->oobsize) { | |
694 | omap_write_buf_pref(mtd, buf, len); | |
695 | return; | |
696 | } | |
697 | ||
698 | info->iomode = OMAP_NAND_IO_WRITE; | |
699 | info->buf = (u_char *) buf; | |
700 | init_completion(&info->comp); | |
701 | ||
317379a9 | 702 | /* configure and start prefetch transfer : size=24 */ |
65b97cf6 AM |
703 | ret = omap_prefetch_enable(info->gpmc_cs, |
704 | (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info); | |
4e070376 SG |
705 | if (ret) |
706 | /* PFPW engine is busy, use cpu copy method */ | |
707 | goto out_copy; | |
708 | ||
709 | info->buf_len = len; | |
5c468455 AM |
710 | |
711 | enable_irq(info->gpmc_irq_count); | |
712 | enable_irq(info->gpmc_irq_fifo); | |
4e070376 SG |
713 | |
714 | /* waiting for write to complete */ | |
715 | wait_for_completion(&info->comp); | |
5c468455 | 716 | |
4e070376 SG |
717 | /* wait for data to flushed-out before reset the prefetch */ |
718 | tim = 0; | |
719 | limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 AM |
720 | do { |
721 | val = readl(info->reg.gpmc_prefetch_status); | |
47f88af4 | 722 | val = PREFETCH_STATUS_COUNT(val); |
4e070376 | 723 | cpu_relax(); |
65b97cf6 | 724 | } while (val && (tim++ < limit)); |
4e070376 SG |
725 | |
726 | /* disable and stop the PFPW engine */ | |
65b97cf6 | 727 | omap_prefetch_reset(info->gpmc_cs, info); |
4e070376 SG |
728 | return; |
729 | ||
730 | out_copy: | |
731 | if (info->nand.options & NAND_BUSWIDTH_16) | |
732 | omap_write_buf16(mtd, buf, len); | |
733 | else | |
734 | omap_write_buf8(mtd, buf, len); | |
735 | } | |
736 | ||
67ce04bf VS |
737 | /** |
738 | * gen_true_ecc - This function will generate true ECC value | |
739 | * @ecc_buf: buffer to store ecc code | |
740 | * | |
741 | * This generated true ECC value can be used when correcting | |
742 | * data read from NAND flash memory core | |
743 | */ | |
744 | static void gen_true_ecc(u8 *ecc_buf) | |
745 | { | |
746 | u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) | | |
747 | ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8); | |
748 | ||
749 | ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | | |
750 | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp)); | |
751 | ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | | |
752 | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp)); | |
753 | ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | | |
754 | P1e(tmp) | P2048o(tmp) | P2048e(tmp)); | |
755 | } | |
756 | ||
757 | /** | |
758 | * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data | |
759 | * @ecc_data1: ecc code from nand spare area | |
760 | * @ecc_data2: ecc code from hardware register obtained from hardware ecc | |
761 | * @page_data: page data | |
762 | * | |
763 | * This function compares two ECC's and indicates if there is an error. | |
764 | * If the error can be corrected it will be corrected to the buffer. | |
74f1b724 JO |
765 | * If there is no error, %0 is returned. If there is an error but it |
766 | * was corrected, %1 is returned. Otherwise, %-1 is returned. | |
67ce04bf VS |
767 | */ |
768 | static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */ | |
769 | u8 *ecc_data2, /* read from register */ | |
770 | u8 *page_data) | |
771 | { | |
772 | uint i; | |
773 | u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8]; | |
774 | u8 comp0_bit[8], comp1_bit[8], comp2_bit[8]; | |
775 | u8 ecc_bit[24]; | |
776 | u8 ecc_sum = 0; | |
777 | u8 find_bit = 0; | |
778 | uint find_byte = 0; | |
779 | int isEccFF; | |
780 | ||
781 | isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF); | |
782 | ||
783 | gen_true_ecc(ecc_data1); | |
784 | gen_true_ecc(ecc_data2); | |
785 | ||
786 | for (i = 0; i <= 2; i++) { | |
787 | *(ecc_data1 + i) = ~(*(ecc_data1 + i)); | |
788 | *(ecc_data2 + i) = ~(*(ecc_data2 + i)); | |
789 | } | |
790 | ||
791 | for (i = 0; i < 8; i++) { | |
792 | tmp0_bit[i] = *ecc_data1 % 2; | |
793 | *ecc_data1 = *ecc_data1 / 2; | |
794 | } | |
795 | ||
796 | for (i = 0; i < 8; i++) { | |
797 | tmp1_bit[i] = *(ecc_data1 + 1) % 2; | |
798 | *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2; | |
799 | } | |
800 | ||
801 | for (i = 0; i < 8; i++) { | |
802 | tmp2_bit[i] = *(ecc_data1 + 2) % 2; | |
803 | *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2; | |
804 | } | |
805 | ||
806 | for (i = 0; i < 8; i++) { | |
807 | comp0_bit[i] = *ecc_data2 % 2; | |
808 | *ecc_data2 = *ecc_data2 / 2; | |
809 | } | |
810 | ||
811 | for (i = 0; i < 8; i++) { | |
812 | comp1_bit[i] = *(ecc_data2 + 1) % 2; | |
813 | *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2; | |
814 | } | |
815 | ||
816 | for (i = 0; i < 8; i++) { | |
817 | comp2_bit[i] = *(ecc_data2 + 2) % 2; | |
818 | *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2; | |
819 | } | |
820 | ||
821 | for (i = 0; i < 6; i++) | |
822 | ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2]; | |
823 | ||
824 | for (i = 0; i < 8; i++) | |
825 | ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i]; | |
826 | ||
827 | for (i = 0; i < 8; i++) | |
828 | ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i]; | |
829 | ||
830 | ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0]; | |
831 | ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1]; | |
832 | ||
833 | for (i = 0; i < 24; i++) | |
834 | ecc_sum += ecc_bit[i]; | |
835 | ||
836 | switch (ecc_sum) { | |
837 | case 0: | |
838 | /* Not reached because this function is not called if | |
839 | * ECC values are equal | |
840 | */ | |
841 | return 0; | |
842 | ||
843 | case 1: | |
844 | /* Uncorrectable error */ | |
289c0522 | 845 | pr_debug("ECC UNCORRECTED_ERROR 1\n"); |
67ce04bf VS |
846 | return -1; |
847 | ||
848 | case 11: | |
849 | /* UN-Correctable error */ | |
289c0522 | 850 | pr_debug("ECC UNCORRECTED_ERROR B\n"); |
67ce04bf VS |
851 | return -1; |
852 | ||
853 | case 12: | |
854 | /* Correctable error */ | |
855 | find_byte = (ecc_bit[23] << 8) + | |
856 | (ecc_bit[21] << 7) + | |
857 | (ecc_bit[19] << 6) + | |
858 | (ecc_bit[17] << 5) + | |
859 | (ecc_bit[15] << 4) + | |
860 | (ecc_bit[13] << 3) + | |
861 | (ecc_bit[11] << 2) + | |
862 | (ecc_bit[9] << 1) + | |
863 | ecc_bit[7]; | |
864 | ||
865 | find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; | |
866 | ||
0a32a102 BN |
867 | pr_debug("Correcting single bit ECC error at offset: " |
868 | "%d, bit: %d\n", find_byte, find_bit); | |
67ce04bf VS |
869 | |
870 | page_data[find_byte] ^= (1 << find_bit); | |
871 | ||
74f1b724 | 872 | return 1; |
67ce04bf VS |
873 | default: |
874 | if (isEccFF) { | |
875 | if (ecc_data2[0] == 0 && | |
876 | ecc_data2[1] == 0 && | |
877 | ecc_data2[2] == 0) | |
878 | return 0; | |
879 | } | |
289c0522 | 880 | pr_debug("UNCORRECTED_ERROR default\n"); |
67ce04bf VS |
881 | return -1; |
882 | } | |
883 | } | |
884 | ||
885 | /** | |
886 | * omap_correct_data - Compares the ECC read with HW generated ECC | |
887 | * @mtd: MTD device structure | |
888 | * @dat: page data | |
889 | * @read_ecc: ecc read from nand flash | |
890 | * @calc_ecc: ecc read from HW ECC registers | |
891 | * | |
892 | * Compares the ecc read from nand spare area with ECC registers values | |
74f1b724 JO |
893 | * and if ECC's mismatched, it will call 'omap_compare_ecc' for error |
894 | * detection and correction. If there are no errors, %0 is returned. If | |
895 | * there were errors and all of the errors were corrected, the number of | |
896 | * corrected errors is returned. If uncorrectable errors exist, %-1 is | |
897 | * returned. | |
67ce04bf VS |
898 | */ |
899 | static int omap_correct_data(struct mtd_info *mtd, u_char *dat, | |
900 | u_char *read_ecc, u_char *calc_ecc) | |
901 | { | |
902 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
903 | mtd); | |
904 | int blockCnt = 0, i = 0, ret = 0; | |
74f1b724 | 905 | int stat = 0; |
67ce04bf VS |
906 | |
907 | /* Ex NAND_ECC_HW12_2048 */ | |
908 | if ((info->nand.ecc.mode == NAND_ECC_HW) && | |
909 | (info->nand.ecc.size == 2048)) | |
910 | blockCnt = 4; | |
911 | else | |
912 | blockCnt = 1; | |
913 | ||
914 | for (i = 0; i < blockCnt; i++) { | |
915 | if (memcmp(read_ecc, calc_ecc, 3) != 0) { | |
916 | ret = omap_compare_ecc(read_ecc, calc_ecc, dat); | |
917 | if (ret < 0) | |
918 | return ret; | |
74f1b724 JO |
919 | /* keep track of the number of corrected errors */ |
920 | stat += ret; | |
67ce04bf VS |
921 | } |
922 | read_ecc += 3; | |
923 | calc_ecc += 3; | |
924 | dat += 512; | |
925 | } | |
74f1b724 | 926 | return stat; |
67ce04bf VS |
927 | } |
928 | ||
929 | /** | |
930 | * omap_calcuate_ecc - Generate non-inverted ECC bytes. | |
931 | * @mtd: MTD device structure | |
932 | * @dat: The pointer to data on which ecc is computed | |
933 | * @ecc_code: The ecc_code buffer | |
934 | * | |
935 | * Using noninverted ECC can be considered ugly since writing a blank | |
936 | * page ie. padding will clear the ECC bytes. This is no problem as long | |
937 | * nobody is trying to write data on the seemingly unused page. Reading | |
938 | * an erased page will produce an ECC mismatch between generated and read | |
939 | * ECC bytes that has to be dealt with separately. | |
940 | */ | |
941 | static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat, | |
942 | u_char *ecc_code) | |
943 | { | |
944 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
945 | mtd); | |
65b97cf6 AM |
946 | u32 val; |
947 | ||
948 | val = readl(info->reg.gpmc_ecc_config); | |
949 | if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs) | |
950 | return -EINVAL; | |
951 | ||
952 | /* read ecc result */ | |
953 | val = readl(info->reg.gpmc_ecc1_result); | |
954 | *ecc_code++ = val; /* P128e, ..., P1e */ | |
955 | *ecc_code++ = val >> 16; /* P128o, ..., P1o */ | |
956 | /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ | |
957 | *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); | |
958 | ||
959 | return 0; | |
67ce04bf VS |
960 | } |
961 | ||
962 | /** | |
963 | * omap_enable_hwecc - This function enables the hardware ecc functionality | |
964 | * @mtd: MTD device structure | |
965 | * @mode: Read/Write mode | |
966 | */ | |
967 | static void omap_enable_hwecc(struct mtd_info *mtd, int mode) | |
968 | { | |
969 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
970 | mtd); | |
971 | struct nand_chip *chip = mtd->priv; | |
972 | unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; | |
65b97cf6 AM |
973 | u32 val; |
974 | ||
975 | /* clear ecc and enable bits */ | |
976 | val = ECCCLEAR | ECC1; | |
977 | writel(val, info->reg.gpmc_ecc_control); | |
67ce04bf | 978 | |
65b97cf6 AM |
979 | /* program ecc and result sizes */ |
980 | val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) | | |
981 | ECC1RESULTSIZE); | |
982 | writel(val, info->reg.gpmc_ecc_size_config); | |
983 | ||
984 | switch (mode) { | |
985 | case NAND_ECC_READ: | |
986 | case NAND_ECC_WRITE: | |
987 | writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); | |
988 | break; | |
989 | case NAND_ECC_READSYN: | |
990 | writel(ECCCLEAR, info->reg.gpmc_ecc_control); | |
991 | break; | |
992 | default: | |
993 | dev_info(&info->pdev->dev, | |
994 | "error: unrecognized Mode[%d]!\n", mode); | |
995 | break; | |
996 | } | |
67ce04bf | 997 | |
65b97cf6 AM |
998 | /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ |
999 | val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); | |
1000 | writel(val, info->reg.gpmc_ecc_config); | |
67ce04bf | 1001 | } |
2c01946c | 1002 | |
67ce04bf VS |
1003 | /** |
1004 | * omap_wait - wait until the command is done | |
1005 | * @mtd: MTD device structure | |
1006 | * @chip: NAND Chip structure | |
1007 | * | |
1008 | * Wait function is called during Program and erase operations and | |
1009 | * the way it is called from MTD layer, we should wait till the NAND | |
1010 | * chip is ready after the programming/erase operation has completed. | |
1011 | * | |
1012 | * Erase can take up to 400ms and program up to 20ms according to | |
1013 | * general NAND and SmartMedia specs | |
1014 | */ | |
1015 | static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
1016 | { | |
1017 | struct nand_chip *this = mtd->priv; | |
1018 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1019 | mtd); | |
1020 | unsigned long timeo = jiffies; | |
a9c465f0 | 1021 | int status, state = this->state; |
67ce04bf VS |
1022 | |
1023 | if (state == FL_ERASING) | |
4ff6772b | 1024 | timeo += msecs_to_jiffies(400); |
67ce04bf | 1025 | else |
4ff6772b | 1026 | timeo += msecs_to_jiffies(20); |
67ce04bf | 1027 | |
65b97cf6 | 1028 | writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command); |
67ce04bf | 1029 | while (time_before(jiffies, timeo)) { |
65b97cf6 | 1030 | status = readb(info->reg.gpmc_nand_data); |
c276aca4 | 1031 | if (status & NAND_STATUS_READY) |
67ce04bf | 1032 | break; |
c276aca4 | 1033 | cond_resched(); |
67ce04bf | 1034 | } |
a9c465f0 | 1035 | |
4ea1e4ba | 1036 | status = readb(info->reg.gpmc_nand_data); |
67ce04bf VS |
1037 | return status; |
1038 | } | |
1039 | ||
1040 | /** | |
1041 | * omap_dev_ready - calls the platform specific dev_ready function | |
1042 | * @mtd: MTD device structure | |
1043 | */ | |
1044 | static int omap_dev_ready(struct mtd_info *mtd) | |
1045 | { | |
2c01946c | 1046 | unsigned int val = 0; |
67ce04bf VS |
1047 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
1048 | mtd); | |
67ce04bf | 1049 | |
65b97cf6 AM |
1050 | val = readl(info->reg.gpmc_status); |
1051 | ||
67ce04bf | 1052 | if ((val & 0x100) == 0x100) { |
65b97cf6 | 1053 | return 1; |
67ce04bf | 1054 | } else { |
65b97cf6 | 1055 | return 0; |
67ce04bf | 1056 | } |
67ce04bf VS |
1057 | } |
1058 | ||
a919e511 | 1059 | #if defined(CONFIG_MTD_NAND_ECC_BCH) || defined(CONFIG_MTD_NAND_OMAP_BCH) |
0e618ef0 ID |
1060 | /** |
1061 | * omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction | |
1062 | * @mtd: MTD device structure | |
1063 | * @mode: Read/Write mode | |
62116e51 PA |
1064 | * |
1065 | * When using BCH, sector size is hardcoded to 512 bytes. | |
1066 | * Using wrapping mode 6 both for reading and writing if ELM module not uses | |
1067 | * for error correction. | |
1068 | * On writing, | |
1069 | * eccsize0 = 0 (no additional protected byte in spare area) | |
1070 | * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area) | |
0e618ef0 ID |
1071 | */ |
1072 | static void omap3_enable_hwecc_bch(struct mtd_info *mtd, int mode) | |
1073 | { | |
1074 | int nerrors; | |
2ef9f3dd | 1075 | unsigned int dev_width, nsectors; |
0e618ef0 ID |
1076 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
1077 | mtd); | |
1078 | struct nand_chip *chip = mtd->priv; | |
62116e51 PA |
1079 | u32 val, wr_mode; |
1080 | unsigned int ecc_size1, ecc_size0; | |
1081 | ||
1082 | /* Using wrapping mode 6 for writing */ | |
1083 | wr_mode = BCH_WRAPMODE_6; | |
0e618ef0 | 1084 | |
0e618ef0 | 1085 | /* |
62116e51 PA |
1086 | * ECC engine enabled for valid ecc_size0 nibbles |
1087 | * and disabled for ecc_size1 nibbles. | |
0e618ef0 | 1088 | */ |
62116e51 PA |
1089 | ecc_size0 = BCH_ECC_SIZE0; |
1090 | ecc_size1 = BCH_ECC_SIZE1; | |
1091 | ||
1092 | /* Perform ecc calculation on 512-byte sector */ | |
1093 | nsectors = 1; | |
1094 | ||
1095 | /* Update number of error correction */ | |
1096 | nerrors = info->nand.ecc.strength; | |
1097 | ||
1098 | /* Multi sector reading/writing for NAND flash with page size < 4096 */ | |
1099 | if (info->is_elm_used && (mtd->writesize <= 4096)) { | |
1100 | if (mode == NAND_ECC_READ) { | |
1101 | /* Using wrapping mode 1 for reading */ | |
1102 | wr_mode = BCH_WRAPMODE_1; | |
1103 | ||
1104 | /* | |
1105 | * ECC engine enabled for ecc_size0 nibbles | |
1106 | * and disabled for ecc_size1 nibbles. | |
1107 | */ | |
1108 | ecc_size0 = (nerrors == 8) ? | |
1109 | BCH8R_ECC_SIZE0 : BCH4R_ECC_SIZE0; | |
1110 | ecc_size1 = (nerrors == 8) ? | |
1111 | BCH8R_ECC_SIZE1 : BCH4R_ECC_SIZE1; | |
1112 | } | |
1113 | ||
1114 | /* Perform ecc calculation for one page (< 4096) */ | |
1115 | nsectors = info->nand.ecc.steps; | |
1116 | } | |
2ef9f3dd AM |
1117 | |
1118 | writel(ECC1, info->reg.gpmc_ecc_control); | |
1119 | ||
62116e51 PA |
1120 | /* Configure ecc size for BCH */ |
1121 | val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT); | |
2ef9f3dd AM |
1122 | writel(val, info->reg.gpmc_ecc_size_config); |
1123 | ||
62116e51 PA |
1124 | dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; |
1125 | ||
2ef9f3dd AM |
1126 | /* BCH configuration */ |
1127 | val = ((1 << 16) | /* enable BCH */ | |
1128 | (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */ | |
62116e51 | 1129 | (wr_mode << 8) | /* wrap mode */ |
2ef9f3dd AM |
1130 | (dev_width << 7) | /* bus width */ |
1131 | (((nsectors-1) & 0x7) << 4) | /* number of sectors */ | |
1132 | (info->gpmc_cs << 1) | /* ECC CS */ | |
1133 | (0x1)); /* enable ECC */ | |
1134 | ||
1135 | writel(val, info->reg.gpmc_ecc_config); | |
1136 | ||
62116e51 | 1137 | /* Clear ecc and enable bits */ |
2ef9f3dd | 1138 | writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); |
0e618ef0 | 1139 | } |
a919e511 | 1140 | #endif |
0e618ef0 | 1141 | |
a919e511 | 1142 | #ifdef CONFIG_MTD_NAND_ECC_BCH |
0e618ef0 ID |
1143 | /** |
1144 | * omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC bytes | |
1145 | * @mtd: MTD device structure | |
1146 | * @dat: The pointer to data on which ecc is computed | |
1147 | * @ecc_code: The ecc_code buffer | |
1148 | */ | |
1149 | static int omap3_calculate_ecc_bch4(struct mtd_info *mtd, const u_char *dat, | |
1150 | u_char *ecc_code) | |
1151 | { | |
1152 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1153 | mtd); | |
2ef9f3dd AM |
1154 | unsigned long nsectors, val1, val2; |
1155 | int i; | |
1156 | ||
1157 | nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1; | |
1158 | ||
1159 | for (i = 0; i < nsectors; i++) { | |
1160 | ||
1161 | /* Read hw-computed remainder */ | |
1162 | val1 = readl(info->reg.gpmc_bch_result0[i]); | |
1163 | val2 = readl(info->reg.gpmc_bch_result1[i]); | |
1164 | ||
1165 | /* | |
1166 | * Add constant polynomial to remainder, in order to get an ecc | |
1167 | * sequence of 0xFFs for a buffer filled with 0xFFs; and | |
1168 | * left-justify the resulting polynomial. | |
1169 | */ | |
1170 | *ecc_code++ = 0x28 ^ ((val2 >> 12) & 0xFF); | |
1171 | *ecc_code++ = 0x13 ^ ((val2 >> 4) & 0xFF); | |
1172 | *ecc_code++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF)); | |
1173 | *ecc_code++ = 0x39 ^ ((val1 >> 20) & 0xFF); | |
1174 | *ecc_code++ = 0x96 ^ ((val1 >> 12) & 0xFF); | |
1175 | *ecc_code++ = 0xac ^ ((val1 >> 4) & 0xFF); | |
1176 | *ecc_code++ = 0x7f ^ ((val1 & 0xF) << 4); | |
1177 | } | |
1178 | ||
1179 | return 0; | |
0e618ef0 ID |
1180 | } |
1181 | ||
1182 | /** | |
1183 | * omap3_calculate_ecc_bch8 - Generate 13 bytes of ECC bytes | |
1184 | * @mtd: MTD device structure | |
1185 | * @dat: The pointer to data on which ecc is computed | |
1186 | * @ecc_code: The ecc_code buffer | |
1187 | */ | |
1188 | static int omap3_calculate_ecc_bch8(struct mtd_info *mtd, const u_char *dat, | |
1189 | u_char *ecc_code) | |
1190 | { | |
1191 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1192 | mtd); | |
2ef9f3dd AM |
1193 | unsigned long nsectors, val1, val2, val3, val4; |
1194 | int i; | |
1195 | ||
1196 | nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1; | |
1197 | ||
1198 | for (i = 0; i < nsectors; i++) { | |
1199 | ||
1200 | /* Read hw-computed remainder */ | |
1201 | val1 = readl(info->reg.gpmc_bch_result0[i]); | |
1202 | val2 = readl(info->reg.gpmc_bch_result1[i]); | |
1203 | val3 = readl(info->reg.gpmc_bch_result2[i]); | |
1204 | val4 = readl(info->reg.gpmc_bch_result3[i]); | |
1205 | ||
1206 | /* | |
1207 | * Add constant polynomial to remainder, in order to get an ecc | |
1208 | * sequence of 0xFFs for a buffer filled with 0xFFs. | |
1209 | */ | |
1210 | *ecc_code++ = 0xef ^ (val4 & 0xFF); | |
1211 | *ecc_code++ = 0x51 ^ ((val3 >> 24) & 0xFF); | |
1212 | *ecc_code++ = 0x2e ^ ((val3 >> 16) & 0xFF); | |
1213 | *ecc_code++ = 0x09 ^ ((val3 >> 8) & 0xFF); | |
1214 | *ecc_code++ = 0xed ^ (val3 & 0xFF); | |
1215 | *ecc_code++ = 0x93 ^ ((val2 >> 24) & 0xFF); | |
1216 | *ecc_code++ = 0x9a ^ ((val2 >> 16) & 0xFF); | |
1217 | *ecc_code++ = 0xc2 ^ ((val2 >> 8) & 0xFF); | |
1218 | *ecc_code++ = 0x97 ^ (val2 & 0xFF); | |
1219 | *ecc_code++ = 0x79 ^ ((val1 >> 24) & 0xFF); | |
1220 | *ecc_code++ = 0xe5 ^ ((val1 >> 16) & 0xFF); | |
1221 | *ecc_code++ = 0x24 ^ ((val1 >> 8) & 0xFF); | |
1222 | *ecc_code++ = 0xb5 ^ (val1 & 0xFF); | |
1223 | } | |
1224 | ||
1225 | return 0; | |
0e618ef0 | 1226 | } |
a919e511 | 1227 | #endif /* CONFIG_MTD_NAND_ECC_BCH */ |
0e618ef0 | 1228 | |
a919e511 | 1229 | #ifdef CONFIG_MTD_NAND_OMAP_BCH |
62116e51 PA |
1230 | /** |
1231 | * omap3_calculate_ecc_bch - Generate bytes of ECC bytes | |
1232 | * @mtd: MTD device structure | |
1233 | * @dat: The pointer to data on which ecc is computed | |
1234 | * @ecc_code: The ecc_code buffer | |
1235 | * | |
1236 | * Support calculating of BCH4/8 ecc vectors for the page | |
1237 | */ | |
1238 | static int omap3_calculate_ecc_bch(struct mtd_info *mtd, const u_char *dat, | |
1239 | u_char *ecc_code) | |
1240 | { | |
1241 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1242 | mtd); | |
1243 | unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4; | |
1244 | int i, eccbchtsel; | |
1245 | ||
1246 | nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1; | |
1247 | /* | |
1248 | * find BCH scheme used | |
1249 | * 0 -> BCH4 | |
1250 | * 1 -> BCH8 | |
1251 | */ | |
1252 | eccbchtsel = ((readl(info->reg.gpmc_ecc_config) >> 12) & 0x3); | |
1253 | ||
1254 | for (i = 0; i < nsectors; i++) { | |
1255 | ||
1256 | /* Read hw-computed remainder */ | |
1257 | bch_val1 = readl(info->reg.gpmc_bch_result0[i]); | |
1258 | bch_val2 = readl(info->reg.gpmc_bch_result1[i]); | |
1259 | if (eccbchtsel) { | |
1260 | bch_val3 = readl(info->reg.gpmc_bch_result2[i]); | |
1261 | bch_val4 = readl(info->reg.gpmc_bch_result3[i]); | |
1262 | } | |
1263 | ||
1264 | if (eccbchtsel) { | |
1265 | /* BCH8 ecc scheme */ | |
1266 | *ecc_code++ = (bch_val4 & 0xFF); | |
1267 | *ecc_code++ = ((bch_val3 >> 24) & 0xFF); | |
1268 | *ecc_code++ = ((bch_val3 >> 16) & 0xFF); | |
1269 | *ecc_code++ = ((bch_val3 >> 8) & 0xFF); | |
1270 | *ecc_code++ = (bch_val3 & 0xFF); | |
1271 | *ecc_code++ = ((bch_val2 >> 24) & 0xFF); | |
1272 | *ecc_code++ = ((bch_val2 >> 16) & 0xFF); | |
1273 | *ecc_code++ = ((bch_val2 >> 8) & 0xFF); | |
1274 | *ecc_code++ = (bch_val2 & 0xFF); | |
1275 | *ecc_code++ = ((bch_val1 >> 24) & 0xFF); | |
1276 | *ecc_code++ = ((bch_val1 >> 16) & 0xFF); | |
1277 | *ecc_code++ = ((bch_val1 >> 8) & 0xFF); | |
1278 | *ecc_code++ = (bch_val1 & 0xFF); | |
1279 | /* | |
1280 | * Setting 14th byte to zero to handle | |
1281 | * erased page & maintain compatibility | |
1282 | * with RBL | |
1283 | */ | |
1284 | *ecc_code++ = 0x0; | |
1285 | } else { | |
1286 | /* BCH4 ecc scheme */ | |
1287 | *ecc_code++ = ((bch_val2 >> 12) & 0xFF); | |
1288 | *ecc_code++ = ((bch_val2 >> 4) & 0xFF); | |
1289 | *ecc_code++ = ((bch_val2 & 0xF) << 4) | | |
1290 | ((bch_val1 >> 28) & 0xF); | |
1291 | *ecc_code++ = ((bch_val1 >> 20) & 0xFF); | |
1292 | *ecc_code++ = ((bch_val1 >> 12) & 0xFF); | |
1293 | *ecc_code++ = ((bch_val1 >> 4) & 0xFF); | |
1294 | *ecc_code++ = ((bch_val1 & 0xF) << 4); | |
1295 | /* | |
1296 | * Setting 8th byte to zero to handle | |
1297 | * erased page | |
1298 | */ | |
1299 | *ecc_code++ = 0x0; | |
1300 | } | |
1301 | } | |
1302 | ||
1303 | return 0; | |
1304 | } | |
1305 | ||
1306 | /** | |
1307 | * erased_sector_bitflips - count bit flips | |
1308 | * @data: data sector buffer | |
1309 | * @oob: oob buffer | |
1310 | * @info: omap_nand_info | |
1311 | * | |
1312 | * Check the bit flips in erased page falls below correctable level. | |
1313 | * If falls below, report the page as erased with correctable bit | |
1314 | * flip, else report as uncorrectable page. | |
1315 | */ | |
1316 | static int erased_sector_bitflips(u_char *data, u_char *oob, | |
1317 | struct omap_nand_info *info) | |
1318 | { | |
1319 | int flip_bits = 0, i; | |
1320 | ||
1321 | for (i = 0; i < info->nand.ecc.size; i++) { | |
1322 | flip_bits += hweight8(~data[i]); | |
1323 | if (flip_bits > info->nand.ecc.strength) | |
1324 | return 0; | |
1325 | } | |
1326 | ||
1327 | for (i = 0; i < info->nand.ecc.bytes - 1; i++) { | |
1328 | flip_bits += hweight8(~oob[i]); | |
1329 | if (flip_bits > info->nand.ecc.strength) | |
1330 | return 0; | |
1331 | } | |
1332 | ||
1333 | /* | |
1334 | * Bit flips falls in correctable level. | |
1335 | * Fill data area with 0xFF | |
1336 | */ | |
1337 | if (flip_bits) { | |
1338 | memset(data, 0xFF, info->nand.ecc.size); | |
1339 | memset(oob, 0xFF, info->nand.ecc.bytes); | |
1340 | } | |
1341 | ||
1342 | return flip_bits; | |
1343 | } | |
1344 | ||
1345 | /** | |
1346 | * omap_elm_correct_data - corrects page data area in case error reported | |
1347 | * @mtd: MTD device structure | |
1348 | * @data: page data | |
1349 | * @read_ecc: ecc read from nand flash | |
1350 | * @calc_ecc: ecc read from HW ECC registers | |
1351 | * | |
1352 | * Calculated ecc vector reported as zero in case of non-error pages. | |
1353 | * In case of error/erased pages non-zero error vector is reported. | |
1354 | * In case of non-zero ecc vector, check read_ecc at fixed offset | |
1355 | * (x = 13/7 in case of BCH8/4 == 0) to find page programmed or not. | |
1356 | * To handle bit flips in this data, count the number of 0's in | |
1357 | * read_ecc[x] and check if it greater than 4. If it is less, it is | |
1358 | * programmed page, else erased page. | |
1359 | * | |
1360 | * 1. If page is erased, check with standard ecc vector (ecc vector | |
1361 | * for erased page to find any bit flip). If check fails, bit flip | |
1362 | * is present in erased page. Count the bit flips in erased page and | |
1363 | * if it falls under correctable level, report page with 0xFF and | |
1364 | * update the correctable bit information. | |
1365 | * 2. If error is reported on programmed page, update elm error | |
1366 | * vector and correct the page with ELM error correction routine. | |
1367 | * | |
1368 | */ | |
1369 | static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data, | |
1370 | u_char *read_ecc, u_char *calc_ecc) | |
1371 | { | |
1372 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1373 | mtd); | |
1374 | int eccsteps = info->nand.ecc.steps; | |
1375 | int i , j, stat = 0; | |
1376 | int eccsize, eccflag, ecc_vector_size; | |
1377 | struct elm_errorvec err_vec[ERROR_VECTOR_MAX]; | |
1378 | u_char *ecc_vec = calc_ecc; | |
1379 | u_char *spare_ecc = read_ecc; | |
1380 | u_char *erased_ecc_vec; | |
1381 | enum bch_ecc type; | |
1382 | bool is_error_reported = false; | |
1383 | ||
1384 | /* Initialize elm error vector to zero */ | |
1385 | memset(err_vec, 0, sizeof(err_vec)); | |
1386 | ||
1387 | if (info->nand.ecc.strength == BCH8_MAX_ERROR) { | |
1388 | type = BCH8_ECC; | |
1389 | erased_ecc_vec = bch8_vector; | |
1390 | } else { | |
1391 | type = BCH4_ECC; | |
1392 | erased_ecc_vec = bch4_vector; | |
1393 | } | |
1394 | ||
1395 | ecc_vector_size = info->nand.ecc.bytes; | |
1396 | ||
1397 | /* | |
1398 | * Remove extra byte padding for BCH8 RBL | |
1399 | * compatibility and erased page handling | |
1400 | */ | |
1401 | eccsize = ecc_vector_size - 1; | |
1402 | ||
1403 | for (i = 0; i < eccsteps ; i++) { | |
1404 | eccflag = 0; /* initialize eccflag */ | |
1405 | ||
1406 | /* | |
1407 | * Check any error reported, | |
1408 | * In case of error, non zero ecc reported. | |
1409 | */ | |
1410 | ||
1411 | for (j = 0; (j < eccsize); j++) { | |
1412 | if (calc_ecc[j] != 0) { | |
1413 | eccflag = 1; /* non zero ecc, error present */ | |
1414 | break; | |
1415 | } | |
1416 | } | |
1417 | ||
1418 | if (eccflag == 1) { | |
1419 | /* | |
1420 | * Set threshold to minimum of 4, half of ecc.strength/2 | |
1421 | * to allow max bit flip in byte to 4 | |
1422 | */ | |
1423 | unsigned int threshold = min_t(unsigned int, 4, | |
1424 | info->nand.ecc.strength / 2); | |
1425 | ||
1426 | /* | |
1427 | * Check data area is programmed by counting | |
1428 | * number of 0's at fixed offset in spare area. | |
1429 | * Checking count of 0's against threshold. | |
1430 | * In case programmed page expects at least threshold | |
1431 | * zeros in byte. | |
1432 | * If zeros are less than threshold for programmed page/ | |
1433 | * zeros are more than threshold erased page, either | |
1434 | * case page reported as uncorrectable. | |
1435 | */ | |
1436 | if (hweight8(~read_ecc[eccsize]) >= threshold) { | |
1437 | /* | |
1438 | * Update elm error vector as | |
1439 | * data area is programmed | |
1440 | */ | |
1441 | err_vec[i].error_reported = true; | |
1442 | is_error_reported = true; | |
1443 | } else { | |
1444 | /* Error reported in erased page */ | |
1445 | int bitflip_count; | |
1446 | u_char *buf = &data[info->nand.ecc.size * i]; | |
1447 | ||
1448 | if (memcmp(calc_ecc, erased_ecc_vec, eccsize)) { | |
1449 | bitflip_count = erased_sector_bitflips( | |
1450 | buf, read_ecc, info); | |
1451 | ||
1452 | if (bitflip_count) | |
1453 | stat += bitflip_count; | |
1454 | else | |
1455 | return -EINVAL; | |
1456 | } | |
1457 | } | |
1458 | } | |
1459 | ||
1460 | /* Update the ecc vector */ | |
1461 | calc_ecc += ecc_vector_size; | |
1462 | read_ecc += ecc_vector_size; | |
1463 | } | |
1464 | ||
1465 | /* Check if any error reported */ | |
1466 | if (!is_error_reported) | |
1467 | return 0; | |
1468 | ||
1469 | /* Decode BCH error using ELM module */ | |
1470 | elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec); | |
1471 | ||
1472 | for (i = 0; i < eccsteps; i++) { | |
1473 | if (err_vec[i].error_reported) { | |
1474 | for (j = 0; j < err_vec[i].error_count; j++) { | |
1475 | u32 bit_pos, byte_pos, error_max, pos; | |
1476 | ||
1477 | if (type == BCH8_ECC) | |
1478 | error_max = BCH8_ECC_MAX; | |
1479 | else | |
1480 | error_max = BCH4_ECC_MAX; | |
1481 | ||
1482 | if (info->nand.ecc.strength == BCH8_MAX_ERROR) | |
1483 | pos = err_vec[i].error_loc[j]; | |
1484 | else | |
1485 | /* Add 4 to take care 4 bit padding */ | |
1486 | pos = err_vec[i].error_loc[j] + | |
1487 | BCH4_BIT_PAD; | |
1488 | ||
1489 | /* Calculate bit position of error */ | |
1490 | bit_pos = pos % 8; | |
1491 | ||
1492 | /* Calculate byte position of error */ | |
1493 | byte_pos = (error_max - pos - 1) / 8; | |
1494 | ||
1495 | if (pos < error_max) { | |
1496 | if (byte_pos < 512) | |
1497 | data[byte_pos] ^= 1 << bit_pos; | |
1498 | else | |
1499 | spare_ecc[byte_pos - 512] ^= | |
1500 | 1 << bit_pos; | |
1501 | } | |
1502 | /* else, not interested to correct ecc */ | |
1503 | } | |
1504 | } | |
1505 | ||
1506 | /* Update number of correctable errors */ | |
1507 | stat += err_vec[i].error_count; | |
1508 | ||
1509 | /* Update page data with sector size */ | |
1510 | data += info->nand.ecc.size; | |
1511 | spare_ecc += ecc_vector_size; | |
1512 | } | |
1513 | ||
1514 | for (i = 0; i < eccsteps; i++) | |
1515 | /* Return error if uncorrectable error present */ | |
1516 | if (err_vec[i].error_uncorrectable) | |
1517 | return -EINVAL; | |
1518 | ||
1519 | return stat; | |
1520 | } | |
a919e511 | 1521 | #endif /* CONFIG_MTD_NAND_OMAP_BCH */ |
62116e51 | 1522 | |
a919e511 | 1523 | #ifdef CONFIG_MTD_NAND_ECC_BCH |
0e618ef0 ID |
1524 | /** |
1525 | * omap3_correct_data_bch - Decode received data and correct errors | |
1526 | * @mtd: MTD device structure | |
1527 | * @data: page data | |
1528 | * @read_ecc: ecc read from nand flash | |
1529 | * @calc_ecc: ecc read from HW ECC registers | |
1530 | */ | |
1531 | static int omap3_correct_data_bch(struct mtd_info *mtd, u_char *data, | |
1532 | u_char *read_ecc, u_char *calc_ecc) | |
1533 | { | |
1534 | int i, count; | |
1535 | /* cannot correct more than 8 errors */ | |
1536 | unsigned int errloc[8]; | |
1537 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1538 | mtd); | |
1539 | ||
1540 | count = decode_bch(info->bch, NULL, 512, read_ecc, calc_ecc, NULL, | |
1541 | errloc); | |
1542 | if (count > 0) { | |
1543 | /* correct errors */ | |
1544 | for (i = 0; i < count; i++) { | |
1545 | /* correct data only, not ecc bytes */ | |
1546 | if (errloc[i] < 8*512) | |
1547 | data[errloc[i]/8] ^= 1 << (errloc[i] & 7); | |
1548 | pr_debug("corrected bitflip %u\n", errloc[i]); | |
1549 | } | |
1550 | } else if (count < 0) { | |
1551 | pr_err("ecc unrecoverable error\n"); | |
1552 | } | |
1553 | return count; | |
1554 | } | |
a919e511 | 1555 | #endif /* CONFIG_MTD_NAND_ECC_BCH */ |
0e618ef0 | 1556 | |
a919e511 | 1557 | #ifdef CONFIG_MTD_NAND_OMAP_BCH |
62116e51 PA |
1558 | /** |
1559 | * omap_write_page_bch - BCH ecc based write page function for entire page | |
1560 | * @mtd: mtd info structure | |
1561 | * @chip: nand chip info structure | |
1562 | * @buf: data buffer | |
1563 | * @oob_required: must write chip->oob_poi to OOB | |
1564 | * | |
1565 | * Custom write page method evolved to support multi sector writing in one shot | |
1566 | */ | |
1567 | static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip, | |
1568 | const uint8_t *buf, int oob_required) | |
1569 | { | |
1570 | int i; | |
1571 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
1572 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1573 | ||
1574 | /* Enable GPMC ecc engine */ | |
1575 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
1576 | ||
1577 | /* Write data */ | |
1578 | chip->write_buf(mtd, buf, mtd->writesize); | |
1579 | ||
1580 | /* Update ecc vector from GPMC result registers */ | |
1581 | chip->ecc.calculate(mtd, buf, &ecc_calc[0]); | |
1582 | ||
1583 | for (i = 0; i < chip->ecc.total; i++) | |
1584 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
1585 | ||
1586 | /* Write ecc vector to OOB area */ | |
1587 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1588 | return 0; | |
1589 | } | |
1590 | ||
1591 | /** | |
1592 | * omap_read_page_bch - BCH ecc based page read function for entire page | |
1593 | * @mtd: mtd info structure | |
1594 | * @chip: nand chip info structure | |
1595 | * @buf: buffer to store read data | |
1596 | * @oob_required: caller requires OOB data read to chip->oob_poi | |
1597 | * @page: page number to read | |
1598 | * | |
1599 | * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module | |
1600 | * used for error correction. | |
1601 | * Custom method evolved to support ELM error correction & multi sector | |
1602 | * reading. On reading page data area is read along with OOB data with | |
1603 | * ecc engine enabled. ecc vector updated after read of OOB data. | |
1604 | * For non error pages ecc vector reported as zero. | |
1605 | */ | |
1606 | static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, | |
1607 | uint8_t *buf, int oob_required, int page) | |
1608 | { | |
1609 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
1610 | uint8_t *ecc_code = chip->buffers->ecccode; | |
1611 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1612 | uint8_t *oob = &chip->oob_poi[eccpos[0]]; | |
1613 | uint32_t oob_pos = mtd->writesize + chip->ecc.layout->eccpos[0]; | |
1614 | int stat; | |
1615 | unsigned int max_bitflips = 0; | |
1616 | ||
1617 | /* Enable GPMC ecc engine */ | |
1618 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1619 | ||
1620 | /* Read data */ | |
1621 | chip->read_buf(mtd, buf, mtd->writesize); | |
1622 | ||
1623 | /* Read oob bytes */ | |
1624 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1); | |
1625 | chip->read_buf(mtd, oob, chip->ecc.total); | |
1626 | ||
1627 | /* Calculate ecc bytes */ | |
1628 | chip->ecc.calculate(mtd, buf, ecc_calc); | |
1629 | ||
1630 | memcpy(ecc_code, &chip->oob_poi[eccpos[0]], chip->ecc.total); | |
1631 | ||
1632 | stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc); | |
1633 | ||
1634 | if (stat < 0) { | |
1635 | mtd->ecc_stats.failed++; | |
1636 | } else { | |
1637 | mtd->ecc_stats.corrected += stat; | |
1638 | max_bitflips = max_t(unsigned int, max_bitflips, stat); | |
1639 | } | |
1640 | ||
1641 | return max_bitflips; | |
1642 | } | |
1643 | ||
0e618ef0 | 1644 | /** |
a919e511 PG |
1645 | * is_elm_present - checks for presence of ELM module by scanning DT nodes |
1646 | * @omap_nand_info: NAND device structure containing platform data | |
1647 | * @bch_type: 0x0=BCH4, 0x1=BCH8, 0x2=BCH16 | |
0e618ef0 | 1648 | */ |
a919e511 PG |
1649 | static int is_elm_present(struct omap_nand_info *info, |
1650 | struct device_node *elm_node, enum bch_ecc bch_type) | |
0e618ef0 | 1651 | { |
a919e511 PG |
1652 | struct platform_device *pdev; |
1653 | info->is_elm_used = false; | |
1654 | /* check whether elm-id is passed via DT */ | |
1655 | if (!elm_node) { | |
1656 | pr_err("nand: error: ELM DT node not found\n"); | |
1657 | return -ENODEV; | |
1658 | } | |
1659 | pdev = of_find_device_by_node(elm_node); | |
1660 | /* check whether ELM device is registered */ | |
1661 | if (!pdev) { | |
1662 | pr_err("nand: error: ELM device not found\n"); | |
1663 | return -ENODEV; | |
0e618ef0 | 1664 | } |
a919e511 PG |
1665 | /* ELM module available, now configure it */ |
1666 | info->elm_dev = &pdev->dev; | |
1667 | if (elm_config(info->elm_dev, bch_type)) | |
1668 | return -ENODEV; | |
1669 | info->is_elm_used = true; | |
1670 | return 0; | |
0e618ef0 | 1671 | } |
a919e511 | 1672 | #endif /* CONFIG_MTD_NAND_ECC_BCH */ |
0e618ef0 | 1673 | |
a919e511 | 1674 | #ifdef CONFIG_MTD_NAND_ECC_BCH |
0e618ef0 | 1675 | /** |
a919e511 | 1676 | * omap3_free_bch - Release BCH ecc resources |
0e618ef0 | 1677 | * @mtd: MTD device structure |
0e618ef0 | 1678 | */ |
a919e511 | 1679 | static void omap3_free_bch(struct mtd_info *mtd) |
0e618ef0 | 1680 | { |
0e618ef0 ID |
1681 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
1682 | mtd); | |
a919e511 PG |
1683 | if (info->bch) { |
1684 | free_bch(info->bch); | |
1685 | info->bch = NULL; | |
0e618ef0 | 1686 | } |
0e618ef0 ID |
1687 | } |
1688 | ||
1689 | /** | |
1690 | * omap3_init_bch_tail - Build an oob layout for BCH ECC correction. | |
1691 | * @mtd: MTD device structure | |
1692 | */ | |
1693 | static int omap3_init_bch_tail(struct mtd_info *mtd) | |
1694 | { | |
62116e51 | 1695 | int i, steps, offset; |
0e618ef0 ID |
1696 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
1697 | mtd); | |
1698 | struct nand_ecclayout *layout = &info->ecclayout; | |
1699 | ||
1700 | /* build oob layout */ | |
1701 | steps = mtd->writesize/info->nand.ecc.size; | |
1702 | layout->eccbytes = steps*info->nand.ecc.bytes; | |
1703 | ||
1704 | /* do not bother creating special oob layouts for small page devices */ | |
1705 | if (mtd->oobsize < 64) { | |
1706 | pr_err("BCH ecc is not supported on small page devices\n"); | |
1707 | goto fail; | |
1708 | } | |
1709 | ||
1710 | /* reserve 2 bytes for bad block marker */ | |
1711 | if (layout->eccbytes+2 > mtd->oobsize) { | |
1712 | pr_err("no oob layout available for oobsize %d eccbytes %u\n", | |
1713 | mtd->oobsize, layout->eccbytes); | |
1714 | goto fail; | |
1715 | } | |
1716 | ||
62116e51 PA |
1717 | /* ECC layout compatible with RBL for BCH8 */ |
1718 | if (info->is_elm_used && (info->nand.ecc.bytes == BCH8_SIZE)) | |
1719 | offset = 2; | |
1720 | else | |
1721 | offset = mtd->oobsize - layout->eccbytes; | |
1722 | ||
0e618ef0 ID |
1723 | /* put ecc bytes at oob tail */ |
1724 | for (i = 0; i < layout->eccbytes; i++) | |
62116e51 PA |
1725 | layout->eccpos[i] = offset + i; |
1726 | ||
1727 | if (info->is_elm_used && (info->nand.ecc.bytes == BCH8_SIZE)) | |
1728 | layout->oobfree[0].offset = 2 + layout->eccbytes * steps; | |
1729 | else | |
1730 | layout->oobfree[0].offset = 2; | |
0e618ef0 | 1731 | |
0e618ef0 ID |
1732 | layout->oobfree[0].length = mtd->oobsize-2-layout->eccbytes; |
1733 | info->nand.ecc.layout = layout; | |
1734 | ||
1735 | if (!(info->nand.options & NAND_BUSWIDTH_16)) | |
1736 | info->nand.badblock_pattern = &bb_descrip_flashbased; | |
1737 | return 0; | |
1738 | fail: | |
1739 | omap3_free_bch(mtd); | |
1740 | return -1; | |
1741 | } | |
1742 | ||
1743 | #else | |
0e618ef0 ID |
1744 | static int omap3_init_bch_tail(struct mtd_info *mtd) |
1745 | { | |
1746 | return -1; | |
1747 | } | |
1748 | static void omap3_free_bch(struct mtd_info *mtd) | |
1749 | { | |
1750 | } | |
a919e511 | 1751 | #endif /* CONFIG_MTD_NAND_ECC_BCH */ |
0e618ef0 | 1752 | |
06f25510 | 1753 | static int omap_nand_probe(struct platform_device *pdev) |
67ce04bf VS |
1754 | { |
1755 | struct omap_nand_info *info; | |
1756 | struct omap_nand_platform_data *pdata; | |
633deb58 PG |
1757 | struct mtd_info *mtd; |
1758 | struct nand_chip *nand_chip; | |
67ce04bf | 1759 | int err; |
f040d332 | 1760 | int i, offset; |
633deb58 PG |
1761 | dma_cap_mask_t mask; |
1762 | unsigned sig; | |
9c4c2f8b | 1763 | struct resource *res; |
ccf04c51 | 1764 | struct mtd_part_parser_data ppdata = {}; |
67ce04bf | 1765 | |
453810b7 | 1766 | pdata = dev_get_platdata(&pdev->dev); |
67ce04bf VS |
1767 | if (pdata == NULL) { |
1768 | dev_err(&pdev->dev, "platform data missing\n"); | |
1769 | return -ENODEV; | |
1770 | } | |
1771 | ||
1772 | info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL); | |
1773 | if (!info) | |
1774 | return -ENOMEM; | |
1775 | ||
1776 | platform_set_drvdata(pdev, info); | |
1777 | ||
1778 | spin_lock_init(&info->controller.lock); | |
1779 | init_waitqueue_head(&info->controller.wq); | |
1780 | ||
633deb58 | 1781 | info->pdev = pdev; |
67ce04bf | 1782 | info->gpmc_cs = pdata->cs; |
65b97cf6 | 1783 | info->reg = pdata->reg; |
a919e511 PG |
1784 | info->bch = NULL; |
1785 | info->of_node = pdata->of_node; | |
633deb58 PG |
1786 | mtd = &info->mtd; |
1787 | mtd->priv = &info->nand; | |
1788 | mtd->name = dev_name(&pdev->dev); | |
1789 | mtd->owner = THIS_MODULE; | |
1790 | nand_chip = &info->nand; | |
633deb58 | 1791 | nand_chip->options |= NAND_SKIP_BBTSCAN; |
67ce04bf | 1792 | |
9c4c2f8b AM |
1793 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1794 | if (res == NULL) { | |
1795 | err = -EINVAL; | |
1796 | dev_err(&pdev->dev, "error getting memory resource\n"); | |
1797 | goto out_free_info; | |
1798 | } | |
67ce04bf | 1799 | |
9c4c2f8b AM |
1800 | info->phys_base = res->start; |
1801 | info->mem_size = resource_size(res); | |
1802 | ||
1803 | if (!request_mem_region(info->phys_base, info->mem_size, | |
67ce04bf VS |
1804 | pdev->dev.driver->name)) { |
1805 | err = -EBUSY; | |
2f70a1e9 | 1806 | goto out_free_info; |
67ce04bf VS |
1807 | } |
1808 | ||
633deb58 PG |
1809 | nand_chip->IO_ADDR_R = ioremap(info->phys_base, info->mem_size); |
1810 | if (!nand_chip->IO_ADDR_R) { | |
67ce04bf VS |
1811 | err = -ENOMEM; |
1812 | goto out_release_mem_region; | |
1813 | } | |
59e9c5ae | 1814 | |
633deb58 | 1815 | nand_chip->controller = &info->controller; |
67ce04bf | 1816 | |
633deb58 PG |
1817 | nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R; |
1818 | nand_chip->cmd_ctrl = omap_hwcontrol; | |
67ce04bf | 1819 | |
67ce04bf VS |
1820 | /* |
1821 | * If RDY/BSY line is connected to OMAP then use the omap ready | |
4cacbe22 PM |
1822 | * function and the generic nand_wait function which reads the status |
1823 | * register after monitoring the RDY/BSY line. Otherwise use a standard | |
67ce04bf VS |
1824 | * chip delay which is slightly more than tR (AC Timing) of the NAND |
1825 | * device and read status register until you get a failure or success | |
1826 | */ | |
1827 | if (pdata->dev_ready) { | |
633deb58 PG |
1828 | nand_chip->dev_ready = omap_dev_ready; |
1829 | nand_chip->chip_delay = 0; | |
67ce04bf | 1830 | } else { |
633deb58 PG |
1831 | nand_chip->waitfunc = omap_wait; |
1832 | nand_chip->chip_delay = 50; | |
67ce04bf VS |
1833 | } |
1834 | ||
f18befb5 PG |
1835 | /* scan NAND device connected to chip controller */ |
1836 | nand_chip->options |= pdata->devsize & NAND_BUSWIDTH_16; | |
1837 | if (nand_scan_ident(mtd, 1, NULL)) { | |
1838 | pr_err("nand device scan failed, may be bus-width mismatch\n"); | |
1839 | err = -ENXIO; | |
1840 | goto out_release_mem_region; | |
1841 | } | |
1842 | ||
1843 | /* re-populate low-level callbacks based on xfer modes */ | |
1b0b323c SG |
1844 | switch (pdata->xfer_type) { |
1845 | case NAND_OMAP_PREFETCH_POLLED: | |
633deb58 PG |
1846 | nand_chip->read_buf = omap_read_buf_pref; |
1847 | nand_chip->write_buf = omap_write_buf_pref; | |
1b0b323c SG |
1848 | break; |
1849 | ||
1850 | case NAND_OMAP_POLLED: | |
633deb58 PG |
1851 | if (nand_chip->options & NAND_BUSWIDTH_16) { |
1852 | nand_chip->read_buf = omap_read_buf16; | |
1853 | nand_chip->write_buf = omap_write_buf16; | |
59e9c5ae | 1854 | } else { |
633deb58 PG |
1855 | nand_chip->read_buf = omap_read_buf8; |
1856 | nand_chip->write_buf = omap_write_buf8; | |
59e9c5ae | 1857 | } |
1b0b323c SG |
1858 | break; |
1859 | ||
1860 | case NAND_OMAP_PREFETCH_DMA: | |
763e7359 RK |
1861 | dma_cap_zero(mask); |
1862 | dma_cap_set(DMA_SLAVE, mask); | |
1863 | sig = OMAP24XX_DMA_GPMC; | |
1864 | info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig); | |
1865 | if (!info->dma) { | |
2df41d05 RK |
1866 | dev_err(&pdev->dev, "DMA engine request failed\n"); |
1867 | err = -ENXIO; | |
1868 | goto out_release_mem_region; | |
763e7359 RK |
1869 | } else { |
1870 | struct dma_slave_config cfg; | |
763e7359 RK |
1871 | |
1872 | memset(&cfg, 0, sizeof(cfg)); | |
1873 | cfg.src_addr = info->phys_base; | |
1874 | cfg.dst_addr = info->phys_base; | |
1875 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1876 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1877 | cfg.src_maxburst = 16; | |
1878 | cfg.dst_maxburst = 16; | |
d680e2c1 AB |
1879 | err = dmaengine_slave_config(info->dma, &cfg); |
1880 | if (err) { | |
763e7359 | 1881 | dev_err(&pdev->dev, "DMA engine slave config failed: %d\n", |
d680e2c1 | 1882 | err); |
763e7359 RK |
1883 | goto out_release_mem_region; |
1884 | } | |
633deb58 PG |
1885 | nand_chip->read_buf = omap_read_buf_dma_pref; |
1886 | nand_chip->write_buf = omap_write_buf_dma_pref; | |
1b0b323c SG |
1887 | } |
1888 | break; | |
1889 | ||
4e070376 | 1890 | case NAND_OMAP_PREFETCH_IRQ: |
5c468455 AM |
1891 | info->gpmc_irq_fifo = platform_get_irq(pdev, 0); |
1892 | if (info->gpmc_irq_fifo <= 0) { | |
1893 | dev_err(&pdev->dev, "error getting fifo irq\n"); | |
1894 | err = -ENODEV; | |
1895 | goto out_release_mem_region; | |
1896 | } | |
1897 | err = request_irq(info->gpmc_irq_fifo, omap_nand_irq, | |
1898 | IRQF_SHARED, "gpmc-nand-fifo", info); | |
4e070376 SG |
1899 | if (err) { |
1900 | dev_err(&pdev->dev, "requesting irq(%d) error:%d", | |
5c468455 AM |
1901 | info->gpmc_irq_fifo, err); |
1902 | info->gpmc_irq_fifo = 0; | |
1903 | goto out_release_mem_region; | |
1904 | } | |
1905 | ||
1906 | info->gpmc_irq_count = platform_get_irq(pdev, 1); | |
1907 | if (info->gpmc_irq_count <= 0) { | |
1908 | dev_err(&pdev->dev, "error getting count irq\n"); | |
1909 | err = -ENODEV; | |
1910 | goto out_release_mem_region; | |
1911 | } | |
1912 | err = request_irq(info->gpmc_irq_count, omap_nand_irq, | |
1913 | IRQF_SHARED, "gpmc-nand-count", info); | |
1914 | if (err) { | |
1915 | dev_err(&pdev->dev, "requesting irq(%d) error:%d", | |
1916 | info->gpmc_irq_count, err); | |
1917 | info->gpmc_irq_count = 0; | |
4e070376 | 1918 | goto out_release_mem_region; |
4e070376 | 1919 | } |
5c468455 | 1920 | |
633deb58 PG |
1921 | nand_chip->read_buf = omap_read_buf_irq_pref; |
1922 | nand_chip->write_buf = omap_write_buf_irq_pref; | |
5c468455 | 1923 | |
4e070376 SG |
1924 | break; |
1925 | ||
1b0b323c SG |
1926 | default: |
1927 | dev_err(&pdev->dev, | |
1928 | "xfer_type(%d) not supported!\n", pdata->xfer_type); | |
1929 | err = -EINVAL; | |
1930 | goto out_release_mem_region; | |
59e9c5ae | 1931 | } |
59e9c5ae | 1932 | |
a919e511 PG |
1933 | /* populate MTD interface based on ECC scheme */ |
1934 | switch (pdata->ecc_opt) { | |
1935 | case OMAP_ECC_HAM1_CODE_HW: | |
1936 | pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n"); | |
1937 | nand_chip->ecc.mode = NAND_ECC_HW; | |
633deb58 PG |
1938 | nand_chip->ecc.bytes = 3; |
1939 | nand_chip->ecc.size = 512; | |
1940 | nand_chip->ecc.strength = 1; | |
1941 | nand_chip->ecc.calculate = omap_calculate_ecc; | |
1942 | nand_chip->ecc.hwctl = omap_enable_hwecc; | |
1943 | nand_chip->ecc.correct = omap_correct_data; | |
a919e511 PG |
1944 | break; |
1945 | ||
1946 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: | |
1947 | #ifdef CONFIG_MTD_NAND_ECC_BCH | |
1948 | pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n"); | |
1949 | nand_chip->ecc.mode = NAND_ECC_HW; | |
1950 | nand_chip->ecc.size = 512; | |
1951 | nand_chip->ecc.bytes = 7; | |
1952 | nand_chip->ecc.strength = 4; | |
1953 | nand_chip->ecc.hwctl = omap3_enable_hwecc_bch; | |
1954 | nand_chip->ecc.correct = omap3_correct_data_bch; | |
1955 | nand_chip->ecc.calculate = omap3_calculate_ecc_bch4; | |
1956 | /* software bch library is used for locating errors */ | |
1957 | info->bch = init_bch(nand_chip->ecc.bytes, | |
1958 | nand_chip->ecc.strength, | |
1959 | OMAP_ECC_BCH8_POLYNOMIAL); | |
1960 | if (!info->bch) { | |
1961 | pr_err("nand: error: unable to use s/w BCH library\n"); | |
0e618ef0 | 1962 | err = -EINVAL; |
a919e511 PG |
1963 | } |
1964 | break; | |
1965 | #else | |
1966 | pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n"); | |
1967 | err = -EINVAL; | |
1968 | goto out_release_mem_region; | |
1969 | #endif | |
1970 | ||
1971 | case OMAP_ECC_BCH4_CODE_HW: | |
1972 | #ifdef CONFIG_MTD_NAND_OMAP_BCH | |
1973 | pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n"); | |
1974 | nand_chip->ecc.mode = NAND_ECC_HW; | |
1975 | nand_chip->ecc.size = 512; | |
1976 | /* 14th bit is kept reserved for ROM-code compatibility */ | |
1977 | nand_chip->ecc.bytes = 7 + 1; | |
1978 | nand_chip->ecc.strength = 4; | |
1979 | nand_chip->ecc.hwctl = omap3_enable_hwecc_bch; | |
1980 | nand_chip->ecc.correct = omap_elm_correct_data; | |
1981 | nand_chip->ecc.calculate = omap3_calculate_ecc_bch; | |
1982 | nand_chip->ecc.read_page = omap_read_page_bch; | |
1983 | nand_chip->ecc.write_page = omap_write_page_bch; | |
1984 | /* This ECC scheme requires ELM H/W block */ | |
1985 | if (is_elm_present(info, pdata->elm_of_node, BCH4_ECC) < 0) { | |
1986 | pr_err("nand: error: could not initialize ELM\n"); | |
1987 | err = -ENODEV; | |
0e618ef0 ID |
1988 | goto out_release_mem_region; |
1989 | } | |
a919e511 PG |
1990 | break; |
1991 | #else | |
1992 | pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n"); | |
1993 | err = -EINVAL; | |
1994 | goto out_release_mem_region; | |
1995 | #endif | |
1996 | ||
1997 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | |
1998 | #ifdef CONFIG_MTD_NAND_ECC_BCH | |
1999 | pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n"); | |
2000 | nand_chip->ecc.mode = NAND_ECC_HW; | |
2001 | nand_chip->ecc.size = 512; | |
2002 | nand_chip->ecc.bytes = 13; | |
2003 | nand_chip->ecc.strength = 8; | |
2004 | nand_chip->ecc.hwctl = omap3_enable_hwecc_bch; | |
2005 | nand_chip->ecc.correct = omap3_correct_data_bch; | |
2006 | nand_chip->ecc.calculate = omap3_calculate_ecc_bch8; | |
2007 | /* software bch library is used for locating errors */ | |
2008 | info->bch = init_bch(nand_chip->ecc.bytes, | |
2009 | nand_chip->ecc.strength, | |
2010 | OMAP_ECC_BCH8_POLYNOMIAL); | |
2011 | if (!info->bch) { | |
2012 | pr_err("nand: error: unable to use s/w BCH library\n"); | |
2013 | err = -EINVAL; | |
2014 | goto out_release_mem_region; | |
2015 | } | |
2016 | break; | |
2017 | #else | |
2018 | pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n"); | |
2019 | err = -EINVAL; | |
2020 | goto out_release_mem_region; | |
2021 | #endif | |
2022 | ||
2023 | case OMAP_ECC_BCH8_CODE_HW: | |
2024 | #ifdef CONFIG_MTD_NAND_OMAP_BCH | |
2025 | pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n"); | |
2026 | nand_chip->ecc.mode = NAND_ECC_HW; | |
2027 | nand_chip->ecc.size = 512; | |
2028 | /* 14th bit is kept reserved for ROM-code compatibility */ | |
2029 | nand_chip->ecc.bytes = 13 + 1; | |
2030 | nand_chip->ecc.strength = 8; | |
2031 | nand_chip->ecc.hwctl = omap3_enable_hwecc_bch; | |
2032 | nand_chip->ecc.correct = omap_elm_correct_data; | |
2033 | nand_chip->ecc.calculate = omap3_calculate_ecc_bch; | |
2034 | nand_chip->ecc.read_page = omap_read_page_bch; | |
2035 | nand_chip->ecc.write_page = omap_write_page_bch; | |
2036 | /* This ECC scheme requires ELM H/W block */ | |
2037 | if (is_elm_present(info, pdata->elm_of_node, BCH8_ECC) < 0) { | |
2038 | pr_err("nand: error: could not initialize ELM\n"); | |
2039 | goto out_release_mem_region; | |
2040 | } | |
2041 | break; | |
2042 | #else | |
2043 | pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n"); | |
2044 | err = -EINVAL; | |
2045 | goto out_release_mem_region; | |
2046 | #endif | |
2047 | ||
2048 | default: | |
2049 | pr_err("nand: error: invalid or unsupported ECC scheme\n"); | |
2050 | err = -EINVAL; | |
2051 | goto out_release_mem_region; | |
f3d73f36 | 2052 | } |
67ce04bf | 2053 | |
f040d332 | 2054 | /* rom code layout */ |
c66d0391 | 2055 | if (pdata->ecc_opt == OMAP_ECC_HAM1_CODE_HW) { |
f040d332 | 2056 | |
633deb58 | 2057 | if (nand_chip->options & NAND_BUSWIDTH_16) { |
f040d332 | 2058 | offset = 2; |
633deb58 | 2059 | } else { |
f040d332 | 2060 | offset = 1; |
633deb58 | 2061 | nand_chip->badblock_pattern = &bb_descrip_flashbased; |
f040d332 | 2062 | } |
633deb58 | 2063 | omap_oobinfo.eccbytes = 3 * (mtd->writesize / 512); |
f040d332 SG |
2064 | for (i = 0; i < omap_oobinfo.eccbytes; i++) |
2065 | omap_oobinfo.eccpos[i] = i+offset; | |
2066 | ||
2067 | omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes; | |
633deb58 | 2068 | omap_oobinfo.oobfree->length = mtd->oobsize - |
f040d332 SG |
2069 | (offset + omap_oobinfo.eccbytes); |
2070 | ||
633deb58 | 2071 | nand_chip->ecc.layout = &omap_oobinfo; |
0e618ef0 | 2072 | } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) || |
a919e511 PG |
2073 | (pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW) || |
2074 | (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW_DETECTION_SW) || | |
0e618ef0 ID |
2075 | (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) { |
2076 | /* build OOB layout for BCH ECC correction */ | |
633deb58 | 2077 | err = omap3_init_bch_tail(mtd); |
0e618ef0 ID |
2078 | if (err) { |
2079 | err = -EINVAL; | |
2080 | goto out_release_mem_region; | |
2081 | } | |
f040d332 | 2082 | } |
1b0b323c | 2083 | |
a80f1c1f | 2084 | /* second phase scan */ |
633deb58 | 2085 | if (nand_scan_tail(mtd)) { |
a80f1c1f JW |
2086 | err = -ENXIO; |
2087 | goto out_release_mem_region; | |
2088 | } | |
2089 | ||
ccf04c51 | 2090 | ppdata.of_node = pdata->of_node; |
633deb58 | 2091 | mtd_device_parse_register(mtd, NULL, &ppdata, pdata->parts, |
42d7fbe2 | 2092 | pdata->nr_parts); |
67ce04bf | 2093 | |
633deb58 | 2094 | platform_set_drvdata(pdev, mtd); |
67ce04bf VS |
2095 | |
2096 | return 0; | |
2097 | ||
2098 | out_release_mem_region: | |
763e7359 RK |
2099 | if (info->dma) |
2100 | dma_release_channel(info->dma); | |
5c468455 AM |
2101 | if (info->gpmc_irq_count > 0) |
2102 | free_irq(info->gpmc_irq_count, info); | |
2103 | if (info->gpmc_irq_fifo > 0) | |
2104 | free_irq(info->gpmc_irq_fifo, info); | |
9c4c2f8b | 2105 | release_mem_region(info->phys_base, info->mem_size); |
67ce04bf | 2106 | out_free_info: |
a919e511 | 2107 | omap3_free_bch(mtd); |
67ce04bf VS |
2108 | kfree(info); |
2109 | ||
2110 | return err; | |
2111 | } | |
2112 | ||
2113 | static int omap_nand_remove(struct platform_device *pdev) | |
2114 | { | |
2115 | struct mtd_info *mtd = platform_get_drvdata(pdev); | |
633deb58 | 2116 | struct nand_chip *nand_chip = mtd->priv; |
f35b6eda VS |
2117 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
2118 | mtd); | |
633deb58 | 2119 | omap3_free_bch(mtd); |
67ce04bf | 2120 | |
763e7359 RK |
2121 | if (info->dma) |
2122 | dma_release_channel(info->dma); | |
2123 | ||
5c468455 AM |
2124 | if (info->gpmc_irq_count > 0) |
2125 | free_irq(info->gpmc_irq_count, info); | |
2126 | if (info->gpmc_irq_fifo > 0) | |
2127 | free_irq(info->gpmc_irq_fifo, info); | |
4e070376 | 2128 | |
67ce04bf | 2129 | /* Release NAND device, its internal structures and partitions */ |
633deb58 PG |
2130 | nand_release(mtd); |
2131 | iounmap(nand_chip->IO_ADDR_R); | |
48b51d4d | 2132 | release_mem_region(info->phys_base, info->mem_size); |
7d9b1102 | 2133 | kfree(info); |
67ce04bf VS |
2134 | return 0; |
2135 | } | |
2136 | ||
2137 | static struct platform_driver omap_nand_driver = { | |
2138 | .probe = omap_nand_probe, | |
2139 | .remove = omap_nand_remove, | |
2140 | .driver = { | |
2141 | .name = DRIVER_NAME, | |
2142 | .owner = THIS_MODULE, | |
2143 | }, | |
2144 | }; | |
2145 | ||
f99640de | 2146 | module_platform_driver(omap_nand_driver); |
67ce04bf | 2147 | |
c804c733 | 2148 | MODULE_ALIAS("platform:" DRIVER_NAME); |
67ce04bf VS |
2149 | MODULE_LICENSE("GPL"); |
2150 | MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards"); |