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1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand/ppchameleonevb.c | |
3 | * | |
4 | * Copyright (C) 2003 DAVE Srl (info@wawnet.biz) | |
5 | * | |
6 | * Derived from drivers/mtd/nand/edb7312.c | |
7 | * | |
8 | * | |
1da177e4 LT |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * Overview: | |
14 | * This is a device driver for the NAND flash devices found on the | |
15 | * PPChameleon/PPChameleonEVB system. | |
16 | * PPChameleon options (autodetected): | |
17 | * - BA model: no NAND | |
18 | * - ME model: 32MB (Samsung K9F5608U0B) | |
19 | * - HI model: 128MB (Samsung K9F1G08UOM) | |
20 | * PPChameleonEVB options: | |
21 | * - 32MB (Samsung K9F5608U0B) | |
22 | */ | |
23 | ||
24 | #include <linux/init.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/mtd/mtd.h> | |
28 | #include <linux/mtd/nand.h> | |
29 | #include <linux/mtd/partitions.h> | |
30 | #include <asm/io.h> | |
31 | #include <platforms/PPChameleonEVB.h> | |
32 | ||
33 | #undef USE_READY_BUSY_PIN | |
34 | #define USE_READY_BUSY_PIN | |
35 | /* see datasheets (tR) */ | |
36 | #define NAND_BIG_DELAY_US 25 | |
37 | #define NAND_SMALL_DELAY_US 10 | |
38 | ||
39 | /* handy sizes */ | |
40 | #define SZ_4M 0x00400000 | |
41 | #define NAND_SMALL_SIZE 0x02000000 | |
42 | #define NAND_MTD_NAME "ppchameleon-nand" | |
43 | #define NAND_EVB_MTD_NAME "ppchameleonevb-nand" | |
44 | ||
45 | /* GPIO pins used to drive NAND chip mounted on processor module */ | |
46 | #define NAND_nCE_GPIO_PIN (0x80000000 >> 1) | |
47 | #define NAND_CLE_GPIO_PIN (0x80000000 >> 2) | |
48 | #define NAND_ALE_GPIO_PIN (0x80000000 >> 3) | |
49 | #define NAND_RB_GPIO_PIN (0x80000000 >> 4) | |
50 | /* GPIO pins used to drive NAND chip mounted on EVB */ | |
51 | #define NAND_EVB_nCE_GPIO_PIN (0x80000000 >> 14) | |
52 | #define NAND_EVB_CLE_GPIO_PIN (0x80000000 >> 15) | |
53 | #define NAND_EVB_ALE_GPIO_PIN (0x80000000 >> 16) | |
54 | #define NAND_EVB_RB_GPIO_PIN (0x80000000 >> 31) | |
55 | ||
56 | /* | |
57 | * MTD structure for PPChameleonEVB board | |
58 | */ | |
e0c7d767 | 59 | static struct mtd_info *ppchameleon_mtd = NULL; |
1da177e4 LT |
60 | static struct mtd_info *ppchameleonevb_mtd = NULL; |
61 | ||
62 | /* | |
63 | * Module stuff | |
64 | */ | |
e0c7d767 | 65 | static unsigned long ppchameleon_fio_pbase = CFG_NAND0_PADDR; |
1da177e4 LT |
66 | static unsigned long ppchameleonevb_fio_pbase = CFG_NAND1_PADDR; |
67 | ||
68 | #ifdef MODULE | |
69 | module_param(ppchameleon_fio_pbase, ulong, 0); | |
70 | module_param(ppchameleonevb_fio_pbase, ulong, 0); | |
71 | #else | |
e0c7d767 DW |
72 | __setup("ppchameleon_fio_pbase=", ppchameleon_fio_pbase); |
73 | __setup("ppchameleonevb_fio_pbase=", ppchameleonevb_fio_pbase); | |
1da177e4 LT |
74 | #endif |
75 | ||
1da177e4 LT |
76 | /* |
77 | * Define static partitions for flash devices | |
78 | */ | |
79 | static struct mtd_partition partition_info_hi[] = { | |
e0c7d767 | 80 | { .name = "PPChameleon HI Nand Flash", |
632155e6 | 81 | .offset = 0, |
e0c7d767 DW |
82 | .size = 128 * 1024 * 1024 |
83 | } | |
1da177e4 LT |
84 | }; |
85 | ||
86 | static struct mtd_partition partition_info_me[] = { | |
e0c7d767 DW |
87 | { .name = "PPChameleon ME Nand Flash", |
88 | .offset = 0, | |
89 | .size = 32 * 1024 * 1024 | |
90 | } | |
1da177e4 LT |
91 | }; |
92 | ||
93 | static struct mtd_partition partition_info_evb[] = { | |
e0c7d767 DW |
94 | { .name = "PPChameleonEVB Nand Flash", |
95 | .offset = 0, | |
96 | .size = 32 * 1024 * 1024 | |
97 | } | |
1da177e4 LT |
98 | }; |
99 | ||
100 | #define NUM_PARTITIONS 1 | |
101 | ||
1da177e4 LT |
102 | /* |
103 | * hardware specific access to control-lines | |
104 | */ | |
7abd3ef9 TG |
105 | static void ppchameleon_hwcontrol(struct mtd_info *mtdinfo, int cmd, |
106 | unsigned int ctrl) | |
1da177e4 | 107 | { |
7abd3ef9 TG |
108 | struct nand_chip *chip = mtd->priv; |
109 | ||
110 | if (ctrl & NAND_CTRL_CHANGE) { | |
111 | #error Missing headerfiles. No way to fix this. -tglx | |
112 | switch (cmd) { | |
113 | case NAND_CTL_SETCLE: | |
114 | MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND0_PADDR); | |
115 | break; | |
116 | case NAND_CTL_CLRCLE: | |
117 | MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND0_PADDR); | |
118 | break; | |
119 | case NAND_CTL_SETALE: | |
120 | MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND0_PADDR); | |
121 | break; | |
122 | case NAND_CTL_CLRALE: | |
123 | MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND0_PADDR); | |
124 | break; | |
125 | case NAND_CTL_SETNCE: | |
126 | MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND0_PADDR); | |
127 | break; | |
128 | case NAND_CTL_CLRNCE: | |
129 | MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND0_PADDR); | |
130 | break; | |
131 | } | |
1da177e4 | 132 | } |
7abd3ef9 TG |
133 | if (cmd != NAND_CMD_NONE) |
134 | writeb(cmd, chip->IO_ADDR_W); | |
1da177e4 LT |
135 | } |
136 | ||
7abd3ef9 TG |
137 | static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd, |
138 | unsigned int ctrl) | |
1da177e4 | 139 | { |
7abd3ef9 TG |
140 | struct nand_chip *chip = mtd->priv; |
141 | ||
142 | if (ctrl & NAND_CTRL_CHANGE) { | |
143 | #error Missing headerfiles. No way to fix this. -tglx | |
144 | switch (cmd) { | |
145 | case NAND_CTL_SETCLE: | |
146 | MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND1_PADDR); | |
147 | break; | |
148 | case NAND_CTL_CLRCLE: | |
149 | MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND1_PADDR); | |
150 | break; | |
151 | case NAND_CTL_SETALE: | |
152 | MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND1_PADDR); | |
153 | break; | |
154 | case NAND_CTL_CLRALE: | |
155 | MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND1_PADDR); | |
156 | break; | |
157 | case NAND_CTL_SETNCE: | |
158 | MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND1_PADDR); | |
159 | break; | |
160 | case NAND_CTL_CLRNCE: | |
161 | MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND1_PADDR); | |
162 | break; | |
163 | } | |
1da177e4 | 164 | } |
7abd3ef9 TG |
165 | if (cmd != NAND_CMD_NONE) |
166 | writeb(cmd, chip->IO_ADDR_W); | |
1da177e4 LT |
167 | } |
168 | ||
169 | #ifdef USE_READY_BUSY_PIN | |
170 | /* | |
171 | * read device ready pin | |
172 | */ | |
173 | static int ppchameleon_device_ready(struct mtd_info *minfo) | |
174 | { | |
e0c7d767 | 175 | if (in_be32((volatile unsigned *)GPIO0_IR) & NAND_RB_GPIO_PIN) |
1da177e4 LT |
176 | return 1; |
177 | return 0; | |
178 | } | |
179 | ||
180 | static int ppchameleonevb_device_ready(struct mtd_info *minfo) | |
181 | { | |
e0c7d767 DW |
182 | if (in_be32((volatile unsigned *)GPIO0_IR) & NAND_EVB_RB_GPIO_PIN) |
183 | return 1; | |
1da177e4 LT |
184 | return 0; |
185 | } | |
186 | #endif | |
187 | ||
1da177e4 LT |
188 | /* |
189 | * Main initialization routine | |
190 | */ | |
e0c7d767 | 191 | static int __init ppchameleonevb_init(void) |
1da177e4 LT |
192 | { |
193 | struct nand_chip *this; | |
1da177e4 LT |
194 | void __iomem *ppchameleon_fio_base; |
195 | void __iomem *ppchameleonevb_fio_base; | |
196 | ||
1da177e4 LT |
197 | /********************************* |
198 | * Processor module NAND (if any) * | |
199 | *********************************/ | |
200 | /* Allocate memory for MTD device structure and private data */ | |
e0c7d767 | 201 | ppchameleon_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL); |
1da177e4 LT |
202 | if (!ppchameleon_mtd) { |
203 | printk("Unable to allocate PPChameleon NAND MTD device structure.\n"); | |
204 | return -ENOMEM; | |
205 | } | |
206 | ||
207 | /* map physical address */ | |
208 | ppchameleon_fio_base = ioremap(ppchameleon_fio_pbase, SZ_4M); | |
e0c7d767 | 209 | if (!ppchameleon_fio_base) { |
1da177e4 LT |
210 | printk("ioremap PPChameleon NAND flash failed\n"); |
211 | kfree(ppchameleon_mtd); | |
212 | return -EIO; | |
213 | } | |
214 | ||
215 | /* Get pointer to private data */ | |
e0c7d767 | 216 | this = (struct nand_chip *)(&ppchameleon_mtd[1]); |
1da177e4 LT |
217 | |
218 | /* Initialize structures */ | |
e0c7d767 DW |
219 | memset(ppchameleon_mtd, 0, sizeof(struct mtd_info)); |
220 | memset(this, 0, sizeof(struct nand_chip)); | |
1da177e4 LT |
221 | |
222 | /* Link the private data with the MTD structure */ | |
223 | ppchameleon_mtd->priv = this; | |
552d9205 | 224 | ppchameleon_mtd->owner = THIS_MODULE; |
1da177e4 | 225 | |
e0c7d767 | 226 | /* Initialize GPIOs */ |
1da177e4 LT |
227 | /* Pin mapping for NAND chip */ |
228 | /* | |
e0c7d767 DW |
229 | CE GPIO_01 |
230 | CLE GPIO_02 | |
231 | ALE GPIO_03 | |
232 | R/B GPIO_04 | |
233 | */ | |
1da177e4 | 234 | /* output select */ |
e0c7d767 | 235 | out_be32((volatile unsigned *)GPIO0_OSRH, in_be32((volatile unsigned *)GPIO0_OSRH) & 0xC0FFFFFF); |
1da177e4 | 236 | /* three-state select */ |
e0c7d767 | 237 | out_be32((volatile unsigned *)GPIO0_TSRH, in_be32((volatile unsigned *)GPIO0_TSRH) & 0xC0FFFFFF); |
1da177e4 | 238 | /* enable output driver */ |
e0c7d767 DW |
239 | out_be32((volatile unsigned *)GPIO0_TCR, |
240 | in_be32((volatile unsigned *)GPIO0_TCR) | NAND_nCE_GPIO_PIN | NAND_CLE_GPIO_PIN | NAND_ALE_GPIO_PIN); | |
1da177e4 LT |
241 | #ifdef USE_READY_BUSY_PIN |
242 | /* three-state select */ | |
e0c7d767 | 243 | out_be32((volatile unsigned *)GPIO0_TSRH, in_be32((volatile unsigned *)GPIO0_TSRH) & 0xFF3FFFFF); |
1da177e4 | 244 | /* high-impedecence */ |
e0c7d767 | 245 | out_be32((volatile unsigned *)GPIO0_TCR, in_be32((volatile unsigned *)GPIO0_TCR) & (~NAND_RB_GPIO_PIN)); |
1da177e4 | 246 | /* input select */ |
e0c7d767 DW |
247 | out_be32((volatile unsigned *)GPIO0_ISR1H, |
248 | (in_be32((volatile unsigned *)GPIO0_ISR1H) & 0xFF3FFFFF) | 0x00400000); | |
1da177e4 LT |
249 | #endif |
250 | ||
251 | /* insert callbacks */ | |
252 | this->IO_ADDR_R = ppchameleon_fio_base; | |
253 | this->IO_ADDR_W = ppchameleon_fio_base; | |
7abd3ef9 | 254 | this->cmd_ctrl = ppchameleon_hwcontrol; |
1da177e4 LT |
255 | #ifdef USE_READY_BUSY_PIN |
256 | this->dev_ready = ppchameleon_device_ready; | |
257 | #endif | |
258 | this->chip_delay = NAND_BIG_DELAY_US; | |
259 | /* ECC mode */ | |
6dfc6d25 | 260 | this->ecc.mode = NAND_ECC_SOFT; |
1da177e4 LT |
261 | |
262 | /* Scan to find existence of the device (it could not be mounted) */ | |
e0c7d767 | 263 | if (nand_scan(ppchameleon_mtd, 1)) { |
1da177e4 | 264 | iounmap((void *)ppchameleon_fio_base); |
25f0c659 | 265 | ppchameleon_fio_base = NULL; |
e0c7d767 | 266 | kfree(ppchameleon_mtd); |
1da177e4 LT |
267 | goto nand_evb_init; |
268 | } | |
1da177e4 LT |
269 | #ifndef USE_READY_BUSY_PIN |
270 | /* Adjust delay if necessary */ | |
271 | if (ppchameleon_mtd->size == NAND_SMALL_SIZE) | |
272 | this->chip_delay = NAND_SMALL_DELAY_US; | |
273 | #endif | |
274 | ||
1da177e4 | 275 | ppchameleon_mtd->name = "ppchameleon-nand"; |
1da177e4 LT |
276 | |
277 | /* Register the partitions */ | |
42d7fbe2 AB |
278 | mtd_device_parse_register(ppchameleon_mtd, NULL, NULL, |
279 | ppchameleon_mtd->size == NAND_SMALL_SIZE ? | |
280 | partition_info_me : partition_info_hi, | |
281 | NUM_PARTITIONS); | |
1da177e4 | 282 | |
e0c7d767 | 283 | nand_evb_init: |
1da177e4 LT |
284 | /**************************** |
285 | * EVB NAND (always present) * | |
286 | ****************************/ | |
287 | /* Allocate memory for MTD device structure and private data */ | |
e0c7d767 | 288 | ppchameleonevb_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL); |
1da177e4 LT |
289 | if (!ppchameleonevb_mtd) { |
290 | printk("Unable to allocate PPChameleonEVB NAND MTD device structure.\n"); | |
25f0c659 AL |
291 | if (ppchameleon_fio_base) |
292 | iounmap(ppchameleon_fio_base); | |
1da177e4 LT |
293 | return -ENOMEM; |
294 | } | |
295 | ||
296 | /* map physical address */ | |
297 | ppchameleonevb_fio_base = ioremap(ppchameleonevb_fio_pbase, SZ_4M); | |
e0c7d767 | 298 | if (!ppchameleonevb_fio_base) { |
1da177e4 LT |
299 | printk("ioremap PPChameleonEVB NAND flash failed\n"); |
300 | kfree(ppchameleonevb_mtd); | |
25f0c659 AL |
301 | if (ppchameleon_fio_base) |
302 | iounmap(ppchameleon_fio_base); | |
1da177e4 LT |
303 | return -EIO; |
304 | } | |
305 | ||
306 | /* Get pointer to private data */ | |
e0c7d767 | 307 | this = (struct nand_chip *)(&ppchameleonevb_mtd[1]); |
1da177e4 LT |
308 | |
309 | /* Initialize structures */ | |
e0c7d767 DW |
310 | memset(ppchameleonevb_mtd, 0, sizeof(struct mtd_info)); |
311 | memset(this, 0, sizeof(struct nand_chip)); | |
1da177e4 LT |
312 | |
313 | /* Link the private data with the MTD structure */ | |
314 | ppchameleonevb_mtd->priv = this; | |
315 | ||
e0c7d767 | 316 | /* Initialize GPIOs */ |
1da177e4 LT |
317 | /* Pin mapping for NAND chip */ |
318 | /* | |
e0c7d767 DW |
319 | CE GPIO_14 |
320 | CLE GPIO_15 | |
321 | ALE GPIO_16 | |
322 | R/B GPIO_31 | |
323 | */ | |
1da177e4 | 324 | /* output select */ |
e0c7d767 DW |
325 | out_be32((volatile unsigned *)GPIO0_OSRH, in_be32((volatile unsigned *)GPIO0_OSRH) & 0xFFFFFFF0); |
326 | out_be32((volatile unsigned *)GPIO0_OSRL, in_be32((volatile unsigned *)GPIO0_OSRL) & 0x3FFFFFFF); | |
1da177e4 | 327 | /* three-state select */ |
e0c7d767 DW |
328 | out_be32((volatile unsigned *)GPIO0_TSRH, in_be32((volatile unsigned *)GPIO0_TSRH) & 0xFFFFFFF0); |
329 | out_be32((volatile unsigned *)GPIO0_TSRL, in_be32((volatile unsigned *)GPIO0_TSRL) & 0x3FFFFFFF); | |
1da177e4 | 330 | /* enable output driver */ |
e0c7d767 | 331 | out_be32((volatile unsigned *)GPIO0_TCR, in_be32((volatile unsigned *)GPIO0_TCR) | NAND_EVB_nCE_GPIO_PIN | |
1da177e4 LT |
332 | NAND_EVB_CLE_GPIO_PIN | NAND_EVB_ALE_GPIO_PIN); |
333 | #ifdef USE_READY_BUSY_PIN | |
334 | /* three-state select */ | |
e0c7d767 | 335 | out_be32((volatile unsigned *)GPIO0_TSRL, in_be32((volatile unsigned *)GPIO0_TSRL) & 0xFFFFFFFC); |
1da177e4 | 336 | /* high-impedecence */ |
e0c7d767 | 337 | out_be32((volatile unsigned *)GPIO0_TCR, in_be32((volatile unsigned *)GPIO0_TCR) & (~NAND_EVB_RB_GPIO_PIN)); |
1da177e4 | 338 | /* input select */ |
e0c7d767 DW |
339 | out_be32((volatile unsigned *)GPIO0_ISR1L, |
340 | (in_be32((volatile unsigned *)GPIO0_ISR1L) & 0xFFFFFFFC) | 0x00000001); | |
1da177e4 LT |
341 | #endif |
342 | ||
343 | /* insert callbacks */ | |
344 | this->IO_ADDR_R = ppchameleonevb_fio_base; | |
345 | this->IO_ADDR_W = ppchameleonevb_fio_base; | |
7abd3ef9 | 346 | this->cmd_ctrl = ppchameleonevb_hwcontrol; |
1da177e4 LT |
347 | #ifdef USE_READY_BUSY_PIN |
348 | this->dev_ready = ppchameleonevb_device_ready; | |
349 | #endif | |
350 | this->chip_delay = NAND_SMALL_DELAY_US; | |
351 | ||
352 | /* ECC mode */ | |
6dfc6d25 | 353 | this->ecc.mode = NAND_ECC_SOFT; |
1da177e4 LT |
354 | |
355 | /* Scan to find existence of the device */ | |
e0c7d767 | 356 | if (nand_scan(ppchameleonevb_mtd, 1)) { |
1da177e4 | 357 | iounmap((void *)ppchameleonevb_fio_base); |
e0c7d767 | 358 | kfree(ppchameleonevb_mtd); |
25f0c659 AL |
359 | if (ppchameleon_fio_base) |
360 | iounmap(ppchameleon_fio_base); | |
1da177e4 LT |
361 | return -ENXIO; |
362 | } | |
acd4134a | 363 | |
1da177e4 | 364 | ppchameleonevb_mtd->name = NAND_EVB_MTD_NAME; |
1da177e4 LT |
365 | |
366 | /* Register the partitions */ | |
42d7fbe2 AB |
367 | mtd_device_parse_register(ppchameleonevb_mtd, NULL, NULL, |
368 | ppchameleon_mtd->size == NAND_SMALL_SIZE ? | |
369 | partition_info_me : partition_info_hi, | |
370 | NUM_PARTITIONS); | |
1da177e4 LT |
371 | |
372 | /* Return happy */ | |
373 | return 0; | |
374 | } | |
e0c7d767 | 375 | |
1da177e4 LT |
376 | module_init(ppchameleonevb_init); |
377 | ||
378 | /* | |
379 | * Clean up routine | |
380 | */ | |
e0c7d767 | 381 | static void __exit ppchameleonevb_cleanup(void) |
1da177e4 LT |
382 | { |
383 | struct nand_chip *this; | |
384 | ||
385 | /* Release resources, unregister device(s) */ | |
e0c7d767 DW |
386 | nand_release(ppchameleon_mtd); |
387 | nand_release(ppchameleonevb_mtd); | |
61b03bd7 | 388 | |
1da177e4 LT |
389 | /* Release iomaps */ |
390 | this = (struct nand_chip *) &ppchameleon_mtd[1]; | |
f8343685 | 391 | iounmap((void *) this->IO_ADDR_R); |
1da177e4 | 392 | this = (struct nand_chip *) &ppchameleonevb_mtd[1]; |
f8343685 | 393 | iounmap((void *) this->IO_ADDR_R); |
1da177e4 LT |
394 | |
395 | /* Free the MTD device structure */ | |
396 | kfree (ppchameleon_mtd); | |
397 | kfree (ppchameleonevb_mtd); | |
398 | } | |
399 | module_exit(ppchameleonevb_cleanup); | |
400 | ||
401 | MODULE_LICENSE("GPL"); | |
402 | MODULE_AUTHOR("DAVE Srl <support-ppchameleon@dave-tech.it>"); | |
403 | MODULE_DESCRIPTION("MTD map driver for DAVE Srl PPChameleonEVB board"); |