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mtd: pxa3xx_nand: convert all printk into dev_*
[deliverable/linux.git] / drivers / mtd / nand / pxa3xx_nand.c
CommitLineData
fe69af00 1/*
2 * drivers/mtd/nand/pxa3xx_nand.c
3 *
4 * Copyright © 2005 Intel Corporation
5 * Copyright © 2006 Marvell International Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
a88bdbb5 12#include <linux/kernel.h>
fe69af00 13#include <linux/module.h>
14#include <linux/interrupt.h>
15#include <linux/platform_device.h>
16#include <linux/dma-mapping.h>
17#include <linux/delay.h>
18#include <linux/clk.h>
19#include <linux/mtd/mtd.h>
20#include <linux/mtd/nand.h>
21#include <linux/mtd/partitions.h>
a1c06ee1
DW		 22#include <linux/io.h>
23#include <linux/irq.h>
5a0e3ad6 24#include <linux/slab.h>
fe69af00 25
afb5b5c9 26#include <mach/dma.h>
82b95ecb 27#include <plat/pxa3xx_nand.h>
fe69af00 28
29#define CHIP_DELAY_TIMEOUT (2 * HZ/10)
f8155a40 30#define NAND_STOP_DELAY (2 * HZ/50)
4eb2da89 31#define PAGE_CHUNK_SIZE (2048)
fe69af00 32
33/* registers and bit definitions */
34#define NDCR (0x00) /* Control register */
35#define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
36#define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
37#define NDSR (0x14) /* Status Register */
38#define NDPCR (0x18) /* Page Count Register */
39#define NDBDR0 (0x1C) /* Bad Block Register 0 */
40#define NDBDR1 (0x20) /* Bad Block Register 1 */
41#define NDDB (0x40) /* Data Buffer */
42#define NDCB0 (0x48) /* Command Buffer0 */
43#define NDCB1 (0x4C) /* Command Buffer1 */
44#define NDCB2 (0x50) /* Command Buffer2 */
45
46#define NDCR_SPARE_EN (0x1 << 31)
47#define NDCR_ECC_EN (0x1 << 30)
48#define NDCR_DMA_EN (0x1 << 29)
49#define NDCR_ND_RUN (0x1 << 28)
50#define NDCR_DWIDTH_C (0x1 << 27)
51#define NDCR_DWIDTH_M (0x1 << 26)
52#define NDCR_PAGE_SZ (0x1 << 24)
53#define NDCR_NCSX (0x1 << 23)
54#define NDCR_ND_MODE (0x3 << 21)
55#define NDCR_NAND_MODE (0x0)
56#define NDCR_CLR_PG_CNT (0x1 << 20)
f8155a40 57#define NDCR_STOP_ON_UNCOR (0x1 << 19)
fe69af00 58#define NDCR_RD_ID_CNT_MASK (0x7 << 16)
59#define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
60
61#define NDCR_RA_START (0x1 << 15)
62#define NDCR_PG_PER_BLK (0x1 << 14)
63#define NDCR_ND_ARB_EN (0x1 << 12)
f8155a40 64#define NDCR_INT_MASK (0xFFF)
fe69af00 65
66#define NDSR_MASK (0xfff)
f8155a40
LW		 67#define NDSR_RDY (0x1 << 12)
68#define NDSR_FLASH_RDY (0x1 << 11)
fe69af00 69#define NDSR_CS0_PAGED (0x1 << 10)
70#define NDSR_CS1_PAGED (0x1 << 9)
71#define NDSR_CS0_CMDD (0x1 << 8)
72#define NDSR_CS1_CMDD (0x1 << 7)
73#define NDSR_CS0_BBD (0x1 << 6)
74#define NDSR_CS1_BBD (0x1 << 5)
75#define NDSR_DBERR (0x1 << 4)
76#define NDSR_SBERR (0x1 << 3)
77#define NDSR_WRDREQ (0x1 << 2)
78#define NDSR_RDDREQ (0x1 << 1)
79#define NDSR_WRCMDREQ (0x1)
80
4eb2da89 81#define NDCB0_ST_ROW_EN (0x1 << 26)
fe69af00 82#define NDCB0_AUTO_RS (0x1 << 25)
83#define NDCB0_CSEL (0x1 << 24)
84#define NDCB0_CMD_TYPE_MASK (0x7 << 21)
85#define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
86#define NDCB0_NC (0x1 << 20)
87#define NDCB0_DBC (0x1 << 19)
88#define NDCB0_ADDR_CYC_MASK (0x7 << 16)
89#define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
90#define NDCB0_CMD2_MASK (0xff << 8)
91#define NDCB0_CMD1_MASK (0xff)
92#define NDCB0_ADDR_CYC_SHIFT (16)
93
fe69af00 94/* macros for registers read/write */
95#define nand_writel(info, off, val) \
96 __raw_writel((val), (info)->mmio_base + (off))
97
98#define nand_readl(info, off) \
99 __raw_readl((info)->mmio_base + (off))
100
101/* error code and state */
102enum {
103 ERR_NONE = 0,
104 ERR_DMABUSERR = -1,
105 ERR_SENDCMD = -2,
106 ERR_DBERR = -3,
107 ERR_BBERR = -4,
223cf6c3 108 ERR_SBERR = -5,
fe69af00 109};
110
111enum {
f8155a40 112 STATE_IDLE = 0,
fe69af00 113 STATE_CMD_HANDLE,
114 STATE_DMA_READING,
115 STATE_DMA_WRITING,
116 STATE_DMA_DONE,
117 STATE_PIO_READING,
118 STATE_PIO_WRITING,
f8155a40
LW		 119 STATE_CMD_DONE,
120 STATE_READY,
fe69af00 121};
122
fe69af00 123struct pxa3xx_nand_info {
124 struct nand_chip nand_chip;
125
401e67e2 126 struct nand_hw_control controller;
fe69af00 127 struct platform_device *pdev;
18c81b18 128 struct pxa3xx_nand_cmdset *cmdset;
fe69af00 129
130 struct clk *clk;
131 void __iomem *mmio_base;
8638fac8 132 unsigned long mmio_phys;
fe69af00 133
134 unsigned int buf_start;
135 unsigned int buf_count;
136
e353a20a 137 struct mtd_info *mtd;
fe69af00 138 /* DMA information */
139 int drcmr_dat;
140 int drcmr_cmd;
141
142 unsigned char *data_buff;
18c81b18 143 unsigned char *oob_buff;
fe69af00 144 dma_addr_t data_buff_phys;
145 size_t data_buff_size;
146 int data_dma_ch;
147 struct pxa_dma_desc *data_desc;
148 dma_addr_t data_desc_addr;
149
150 uint32_t reg_ndcr;
151
152 /* saved column/page_addr during CMD_SEQIN */
153 int seqin_column;
154 int seqin_page_addr;
155
156 /* relate to the command */
157 unsigned int state;
158
159 int use_ecc; /* use HW ECC ? */
160 int use_dma; /* use DMA ? */
401e67e2 161 int is_ready;
fe69af00 162
18c81b18
LW		 163 unsigned int page_size; /* page size of attached chip */
164 unsigned int data_size; /* data size in FIFO */
fe69af00 165 int retcode;
166 struct completion cmd_complete;
167
168 /* generated NDCBx register values */
169 uint32_t ndcb0;
170 uint32_t ndcb1;
171 uint32_t ndcb2;
c8c17c88 172
18c81b18
LW		 173 /* timing calcuted from setting */
174 uint32_t ndtr0cs0;
175 uint32_t ndtr1cs0;
176
c8c17c88
ES		 177 /* calculated from pxa3xx_nand_flash data */
178 size_t oob_size;
179 size_t read_id_bytes;
180
181 unsigned int col_addr_cycles;
182 unsigned int row_addr_cycles;
fe69af00 183};
184
185static int use_dma = 1;
186module_param(use_dma, bool, 0444);
25985edc 187MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW");
fe69af00 188
f271049e
MR		 189/*
190 * Default NAND flash controller configuration setup by the
191 * bootloader. This configuration is used only when pdata->keep_config is set
192 */
c1f82478 193static struct pxa3xx_nand_cmdset default_cmdset = {
fe69af00 194 .read1 = 0x3000,
195 .read2 = 0x0050,
196 .program = 0x1080,
197 .read_status = 0x0070,
198 .read_id = 0x0090,
199 .erase = 0xD060,
200 .reset = 0x00FF,
201 .lock = 0x002A,
202 .unlock = 0x2423,
203 .lock_status = 0x007A,
204};
205
c1f82478 206static struct pxa3xx_nand_timing timing[] = {
227a886c
LW		 207 { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
208 { 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
209 { 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
210 { 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
d3490dfd
HZ		 211};
212
c1f82478 213static struct pxa3xx_nand_flash builtin_flash_types[] = {
4332c116
LW		 214{ "DEFAULT FLASH", 0, 0, 2048, 8, 8, 0, &timing[0] },
215{ "64MiB 16-bit", 0x46ec, 32, 512, 16, 16, 4096, &timing[1] },
216{ "256MiB 8-bit", 0xdaec, 64, 2048, 8, 8, 2048, &timing[1] },
217{ "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, 8192, &timing[1] },
218{ "128MiB 8-bit", 0xa12c, 64, 2048, 8, 8, 1024, &timing[2] },
219{ "128MiB 16-bit", 0xb12c, 64, 2048, 16, 16, 1024, &timing[2] },
220{ "512MiB 8-bit", 0xdc2c, 64, 2048, 8, 8, 4096, &timing[2] },
221{ "512MiB 16-bit", 0xcc2c, 64, 2048, 16, 16, 4096, &timing[2] },
222{ "256MiB 16-bit", 0xba20, 64, 2048, 16, 16, 2048, &timing[3] },
d3490dfd
HZ		 223};
224
227a886c
LW		 225/* Define a default flash type setting serve as flash detecting only */
226#define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
227
401e67e2
LW		 228const char *mtd_names[] = {"pxa3xx_nand-0", NULL};
229
fe69af00 230#define NDTR0_tCH(c) (min((c), 7) << 19)
231#define NDTR0_tCS(c) (min((c), 7) << 16)
232#define NDTR0_tWH(c) (min((c), 7) << 11)
233#define NDTR0_tWP(c) (min((c), 7) << 8)
234#define NDTR0_tRH(c) (min((c), 7) << 3)
235#define NDTR0_tRP(c) (min((c), 7) << 0)
236
237#define NDTR1_tR(c) (min((c), 65535) << 16)
238#define NDTR1_tWHR(c) (min((c), 15) << 4)
239#define NDTR1_tAR(c) (min((c), 15) << 0)
240
241/* convert nano-seconds to nand flash controller clock cycles */
93b352fc 242#define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
fe69af00 243
244static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
7dad482e 245 const struct pxa3xx_nand_timing *t)
fe69af00 246{
247 unsigned long nand_clk = clk_get_rate(info->clk);
248 uint32_t ndtr0, ndtr1;
249
250 ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
251 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
252 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
253 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
254 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
255 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
256
257 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
258 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
259 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
260
18c81b18
LW		 261 info->ndtr0cs0 = ndtr0;
262 info->ndtr1cs0 = ndtr1;
fe69af00 263 nand_writel(info, NDTR0CS0, ndtr0);
264 nand_writel(info, NDTR1CS0, ndtr1);
265}
266
18c81b18 267static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
fe69af00 268{
9d8b1043
LW		 269 int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
270
271 info->data_size = info->page_size;
272 if (!oob_enable) {
273 info->oob_size = 0;
274 return;
275 }
276
18c81b18 277 switch (info->page_size) {
fe69af00 278 case 2048:
9d8b1043 279 info->oob_size = (info->use_ecc) ? 40 : 64;
fe69af00 280 break;
281 case 512:
9d8b1043 282 info->oob_size = (info->use_ecc) ? 8 : 16;
fe69af00 283 break;
fe69af00 284 }
18c81b18
LW		 285}
286
f8155a40
LW		 287/**
288 * NOTE: it is a must to set ND_RUN firstly, then write
289 * command buffer, otherwise, it does not work.
290 * We enable all the interrupt at the same time, and
291 * let pxa3xx_nand_irq to handle all logic.
292 */
293static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
294{
295 uint32_t ndcr;
296
297 ndcr = info->reg_ndcr;
298 ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
299 ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
300 ndcr |= NDCR_ND_RUN;
301
302 /* clear status bits and run */
303 nand_writel(info, NDCR, 0);
304 nand_writel(info, NDSR, NDSR_MASK);
305 nand_writel(info, NDCR, ndcr);
306}
307
308static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
309{
310 uint32_t ndcr;
311 int timeout = NAND_STOP_DELAY;
312
313 /* wait RUN bit in NDCR become 0 */
314 ndcr = nand_readl(info, NDCR);
315 while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) {
316 ndcr = nand_readl(info, NDCR);
317 udelay(1);
318 }
319
320 if (timeout <= 0) {
321 ndcr &= ~NDCR_ND_RUN;
322 nand_writel(info, NDCR, ndcr);
323 }
324 /* clear status bits */
325 nand_writel(info, NDSR, NDSR_MASK);
326}
327
fe69af00 328static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
329{
330 uint32_t ndcr;
331
332 ndcr = nand_readl(info, NDCR);
333 nand_writel(info, NDCR, ndcr & ~int_mask);
334}
335
336static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
337{
338 uint32_t ndcr;
339
340 ndcr = nand_readl(info, NDCR);
341 nand_writel(info, NDCR, ndcr | int_mask);
342}
343
f8155a40 344static void handle_data_pio(struct pxa3xx_nand_info *info)
fe69af00 345{
fe69af00 346 switch (info->state) {
347 case STATE_PIO_WRITING:
348 __raw_writesl(info->mmio_base + NDDB, info->data_buff,
a88bdbb5 349 DIV_ROUND_UP(info->data_size, 4));
9d8b1043
LW		 350 if (info->oob_size > 0)
351 __raw_writesl(info->mmio_base + NDDB, info->oob_buff,
352 DIV_ROUND_UP(info->oob_size, 4));
fe69af00 353 break;
354 case STATE_PIO_READING:
355 __raw_readsl(info->mmio_base + NDDB, info->data_buff,
a88bdbb5 356 DIV_ROUND_UP(info->data_size, 4));
9d8b1043
LW		 357 if (info->oob_size > 0)
358 __raw_readsl(info->mmio_base + NDDB, info->oob_buff,
359 DIV_ROUND_UP(info->oob_size, 4));
fe69af00 360 break;
361 default:
da675b4e 362 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
fe69af00 363 info->state);
f8155a40 364 BUG();
fe69af00 365 }
fe69af00 366}
367
f8155a40 368static void start_data_dma(struct pxa3xx_nand_info *info)
fe69af00 369{
370 struct pxa_dma_desc *desc = info->data_desc;
9d8b1043 371 int dma_len = ALIGN(info->data_size + info->oob_size, 32);
fe69af00 372
373 desc->ddadr = DDADR_STOP;
374 desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
375
f8155a40
LW		 376 switch (info->state) {
377 case STATE_DMA_WRITING:
fe69af00 378 desc->dsadr = info->data_buff_phys;
8638fac8 379 desc->dtadr = info->mmio_phys + NDDB;
fe69af00 380 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
f8155a40
LW		 381 break;
382 case STATE_DMA_READING:
fe69af00 383 desc->dtadr = info->data_buff_phys;
8638fac8 384 desc->dsadr = info->mmio_phys + NDDB;
fe69af00 385 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
f8155a40
LW		 386 break;
387 default:
da675b4e 388 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
f8155a40
LW		 389 info->state);
390 BUG();
fe69af00 391 }
392
393 DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
394 DDADR(info->data_dma_ch) = info->data_desc_addr;
395 DCSR(info->data_dma_ch) |= DCSR_RUN;
396}
397
398static void pxa3xx_nand_data_dma_irq(int channel, void *data)
399{
400 struct pxa3xx_nand_info *info = data;
401 uint32_t dcsr;
402
403 dcsr = DCSR(channel);
404 DCSR(channel) = dcsr;
405
406 if (dcsr & DCSR_BUSERR) {
407 info->retcode = ERR_DMABUSERR;
fe69af00 408 }
409
f8155a40
LW		 410 info->state = STATE_DMA_DONE;
411 enable_int(info, NDCR_INT_MASK);
412 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
fe69af00 413}
414
415static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
416{
417 struct pxa3xx_nand_info *info = devid;
f8155a40 418 unsigned int status, is_completed = 0;
fe69af00 419
420 status = nand_readl(info, NDSR);
421
f8155a40
LW		 422 if (status & NDSR_DBERR)
423 info->retcode = ERR_DBERR;
424 if (status & NDSR_SBERR)
425 info->retcode = ERR_SBERR;
426 if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
427 /* whether use dma to transfer data */
fe69af00 428 if (info->use_dma) {
f8155a40
LW		 429 disable_int(info, NDCR_INT_MASK);
430 info->state = (status & NDSR_RDDREQ) ?
431 STATE_DMA_READING : STATE_DMA_WRITING;
432 start_data_dma(info);
433 goto NORMAL_IRQ_EXIT;
fe69af00 434 } else {
f8155a40
LW		 435 info->state = (status & NDSR_RDDREQ) ?
436 STATE_PIO_READING : STATE_PIO_WRITING;
437 handle_data_pio(info);
fe69af00 438 }
fe69af00 439 }
f8155a40
LW		 440 if (status & NDSR_CS0_CMDD) {
441 info->state = STATE_CMD_DONE;
442 is_completed = 1;
fe69af00 443 }
401e67e2
LW		 444 if (status & NDSR_FLASH_RDY) {
445 info->is_ready = 1;
f8155a40 446 info->state = STATE_READY;
401e67e2 447 }
fe69af00 448
f8155a40
LW		 449 if (status & NDSR_WRCMDREQ) {
450 nand_writel(info, NDSR, NDSR_WRCMDREQ);
451 status &= ~NDSR_WRCMDREQ;
452 info->state = STATE_CMD_HANDLE;
453 nand_writel(info, NDCB0, info->ndcb0);
454 nand_writel(info, NDCB0, info->ndcb1);
455 nand_writel(info, NDCB0, info->ndcb2);
fe69af00 456 }
457
f8155a40
LW		 458 /* clear NDSR to let the controller exit the IRQ */
459 nand_writel(info, NDSR, status);
460 if (is_completed)
461 complete(&info->cmd_complete);
462NORMAL_IRQ_EXIT:
463 return IRQ_HANDLED;
fe69af00 464}
465
466static int pxa3xx_nand_dev_ready(struct mtd_info *mtd)
467{
468 struct pxa3xx_nand_info *info = mtd->priv;
469 return (nand_readl(info, NDSR) & NDSR_RDY) ? 1 : 0;
470}
471
472static inline int is_buf_blank(uint8_t *buf, size_t len)
473{
474 for (; len > 0; len--)
475 if (*buf++ != 0xff)
476 return 0;
477 return 1;
478}
479
4eb2da89
LW		 480static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
481 uint16_t column, int page_addr)
fe69af00 482{
4eb2da89
LW		 483 uint16_t cmd;
484 int addr_cycle, exec_cmd, ndcb0;
485 struct mtd_info *mtd = info->mtd;
fe69af00 486
4eb2da89
LW		 487 ndcb0 = 0;
488 addr_cycle = 0;
489 exec_cmd = 1;
490
491 /* reset data and oob column point to handle data */
401e67e2
LW		 492 info->buf_start = 0;
493 info->buf_count = 0;
4eb2da89
LW		 494 info->oob_size = 0;
495 info->use_ecc = 0;
401e67e2 496 info->is_ready = 0;
4eb2da89 497 info->retcode = ERR_NONE;
fe69af00 498
499 switch (command) {
4eb2da89
LW		 500 case NAND_CMD_READ0:
501 case NAND_CMD_PAGEPROG:
502 info->use_ecc = 1;
fe69af00 503 case NAND_CMD_READOOB:
4eb2da89 504 pxa3xx_set_datasize(info);
fe69af00 505 break;
4eb2da89
LW		 506 case NAND_CMD_SEQIN:
507 exec_cmd = 0;
508 break;
509 default:
510 info->ndcb1 = 0;
511 info->ndcb2 = 0;
512 break;
513 }
514
515 info->ndcb0 = ndcb0;
516 addr_cycle = NDCB0_ADDR_CYC(info->row_addr_cycles
517 + info->col_addr_cycles);
fe69af00 518
4eb2da89
LW		 519 switch (command) {
520 case NAND_CMD_READOOB:
fe69af00 521 case NAND_CMD_READ0:
4eb2da89
LW		 522 cmd = info->cmdset->read1;
523 if (command == NAND_CMD_READOOB)
524 info->buf_start = mtd->writesize + column;
525 else
526 info->buf_start = column;
527
528 if (unlikely(info->page_size < PAGE_CHUNK_SIZE))
529 info->ndcb0 |= NDCB0_CMD_TYPE(0)
530 | addr_cycle
531 | (cmd & NDCB0_CMD1_MASK);
532 else
533 info->ndcb0 |= NDCB0_CMD_TYPE(0)
534 | NDCB0_DBC
535 | addr_cycle
536 | cmd;
fe69af00 537
fe69af00 538 case NAND_CMD_SEQIN:
4eb2da89
LW		 539 /* small page addr setting */
540 if (unlikely(info->page_size < PAGE_CHUNK_SIZE)) {
541 info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
542 | (column & 0xFF);
543
544 info->ndcb2 = 0;
545 } else {
546 info->ndcb1 = ((page_addr & 0xFFFF) << 16)
547 | (column & 0xFFFF);
548
549 if (page_addr & 0xFF0000)
550 info->ndcb2 = (page_addr & 0xFF0000) >> 16;
551 else
552 info->ndcb2 = 0;
553 }
554
fe69af00 555 info->buf_count = mtd->writesize + mtd->oobsize;
4eb2da89 556 memset(info->data_buff, 0xFF, info->buf_count);
fe69af00 557
fe69af00 558 break;
4eb2da89 559
fe69af00 560 case NAND_CMD_PAGEPROG:
4eb2da89
LW		 561 if (is_buf_blank(info->data_buff,
562 (mtd->writesize + mtd->oobsize))) {
563 exec_cmd = 0;
564 break;
565 }
fe69af00 566
4eb2da89
LW		 567 cmd = info->cmdset->program;
568 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
569 | NDCB0_AUTO_RS
570 | NDCB0_ST_ROW_EN
571 | NDCB0_DBC
572 | cmd
573 | addr_cycle;
fe69af00 574 break;
4eb2da89 575
fe69af00 576 case NAND_CMD_READID:
4eb2da89
LW		 577 cmd = info->cmdset->read_id;
578 info->buf_count = info->read_id_bytes;
579 info->ndcb0 |= NDCB0_CMD_TYPE(3)
580 | NDCB0_ADDR_CYC(1)
581 | cmd;
582
583 info->data_size = 8;
584 break;
fe69af00 585 case NAND_CMD_STATUS:
4eb2da89
LW		 586 cmd = info->cmdset->read_status;
587 info->buf_count = 1;
588 info->ndcb0 |= NDCB0_CMD_TYPE(4)
589 | NDCB0_ADDR_CYC(1)
590 | cmd;
591
592 info->data_size = 8;
593 break;
594
595 case NAND_CMD_ERASE1:
596 cmd = info->cmdset->erase;
597 info->ndcb0 |= NDCB0_CMD_TYPE(2)
598 | NDCB0_AUTO_RS
599 | NDCB0_ADDR_CYC(3)
600 | NDCB0_DBC
601 | cmd;
602 info->ndcb1 = page_addr;
603 info->ndcb2 = 0;
604
fe69af00 605 break;
606 case NAND_CMD_RESET:
4eb2da89
LW		 607 cmd = info->cmdset->reset;
608 info->ndcb0 |= NDCB0_CMD_TYPE(5)
609 | cmd;
610
611 break;
612
613 case NAND_CMD_ERASE2:
614 exec_cmd = 0;
fe69af00 615 break;
4eb2da89 616
fe69af00 617 default:
4eb2da89 618 exec_cmd = 0;
da675b4e
LW		 619 dev_err(&info->pdev->dev, "non-supported command %x\n",
620 command);
fe69af00 621 break;
622 }
623
4eb2da89
LW		 624 return exec_cmd;
625}
626
627static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
628 int column, int page_addr)
629{
630 struct pxa3xx_nand_info *info = mtd->priv;
631 int ret, exec_cmd;
632
633 /*
634 * if this is a x16 device ,then convert the input
635 * "byte" address into a "word" address appropriate
636 * for indexing a word-oriented device
637 */
638 if (info->reg_ndcr & NDCR_DWIDTH_M)
639 column /= 2;
640
641 exec_cmd = prepare_command_pool(info, command, column, page_addr);
f8155a40
LW		 642 if (exec_cmd) {
643 init_completion(&info->cmd_complete);
644 pxa3xx_nand_start(info);
645
646 ret = wait_for_completion_timeout(&info->cmd_complete,
647 CHIP_DELAY_TIMEOUT);
648 if (!ret) {
da675b4e 649 dev_err(&info->pdev->dev, "Wait time out!!!\n");
f8155a40
LW		 650 /* Stop State Machine for next command cycle */
651 pxa3xx_nand_stop(info);
652 }
653 info->state = STATE_IDLE;
654 }
655}
656
657static void pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
658 struct nand_chip *chip, const uint8_t *buf)
659{
660 chip->write_buf(mtd, buf, mtd->writesize);
661 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
662}
663
664static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
665 struct nand_chip *chip, uint8_t *buf, int page)
666{
667 struct pxa3xx_nand_info *info = mtd->priv;
668
669 chip->read_buf(mtd, buf, mtd->writesize);
670 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
671
672 if (info->retcode == ERR_SBERR) {
673 switch (info->use_ecc) {
674 case 1:
675 mtd->ecc_stats.corrected++;
676 break;
677 case 0:
678 default:
679 break;
680 }
681 } else if (info->retcode == ERR_DBERR) {
682 /*
683 * for blank page (all 0xff), HW will calculate its ECC as
684 * 0, which is different from the ECC information within
685 * OOB, ignore such double bit errors
686 */
687 if (is_buf_blank(buf, mtd->writesize))
543e32d5
DM		 688 info->retcode = ERR_NONE;
689 else
f8155a40 690 mtd->ecc_stats.failed++;
fe69af00 691 }
f8155a40
LW		 692
693 return 0;
fe69af00 694}
695
696static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
697{
698 struct pxa3xx_nand_info *info = mtd->priv;
699 char retval = 0xFF;
700
701 if (info->buf_start < info->buf_count)
702 /* Has just send a new command? */
703 retval = info->data_buff[info->buf_start++];
704
705 return retval;
706}
707
708static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
709{
710 struct pxa3xx_nand_info *info = mtd->priv;
711 u16 retval = 0xFFFF;
712
713 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
714 retval = *((u16 *)(info->data_buff+info->buf_start));
715 info->buf_start += 2;
716 }
717 return retval;
718}
719
720static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
721{
722 struct pxa3xx_nand_info *info = mtd->priv;
723 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
724
725 memcpy(buf, info->data_buff + info->buf_start, real_len);
726 info->buf_start += real_len;
727}
728
729static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
730 const uint8_t *buf, int len)
731{
732 struct pxa3xx_nand_info *info = mtd->priv;
733 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
734
735 memcpy(info->data_buff + info->buf_start, buf, real_len);
736 info->buf_start += real_len;
737}
738
739static int pxa3xx_nand_verify_buf(struct mtd_info *mtd,
740 const uint8_t *buf, int len)
741{
742 return 0;
743}
744
745static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
746{
747 return;
748}
749
750static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
751{
752 struct pxa3xx_nand_info *info = mtd->priv;
753
754 /* pxa3xx_nand_send_command has waited for command complete */
755 if (this->state == FL_WRITING || this->state == FL_ERASING) {
756 if (info->retcode == ERR_NONE)
757 return 0;
758 else {
759 /*
760 * any error make it return 0x01 which will tell
761 * the caller the erase and write fail
762 */
763 return 0x01;
764 }
765 }
766
767 return 0;
768}
769
fe69af00 770static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
c8c17c88 771 const struct pxa3xx_nand_flash *f)
fe69af00 772{
773 struct platform_device *pdev = info->pdev;
774 struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
f8155a40 775 uint32_t ndcr = 0x0; /* enable all interrupts */
fe69af00 776
da675b4e
LW		 777 if (f->page_size != 2048 && f->page_size != 512) {
778 dev_err(&pdev->dev, "Current only support 2048 and 512 size\n");
fe69af00 779 return -EINVAL;
da675b4e 780 }
fe69af00 781
da675b4e
LW		 782 if (f->flash_width != 16 && f->flash_width != 8) {
783 dev_err(&pdev->dev, "Only support 8bit and 16 bit!\n");
fe69af00 784 return -EINVAL;
da675b4e 785 }
fe69af00 786
787 /* calculate flash information */
4332c116 788 info->cmdset = &default_cmdset;
18c81b18 789 info->page_size = f->page_size;
c8c17c88 790 info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
fe69af00 791
792 /* calculate addressing information */
c8c17c88 793 info->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
fe69af00 794
795 if (f->num_blocks * f->page_per_block > 65536)
c8c17c88 796 info->row_addr_cycles = 3;
fe69af00 797 else
c8c17c88 798 info->row_addr_cycles = 2;
fe69af00 799
800 ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
c8c17c88 801 ndcr |= (info->col_addr_cycles == 2) ? NDCR_RA_START : 0;
fe69af00 802 ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
803 ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
804 ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
805 ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
806
c8c17c88 807 ndcr |= NDCR_RD_ID_CNT(info->read_id_bytes);
fe69af00 808 ndcr |= NDCR_SPARE_EN; /* enable spare by default */
809
810 info->reg_ndcr = ndcr;
811
812 pxa3xx_nand_set_timing(info, f->timing);
fe69af00 813 return 0;
814}
815
f271049e
MR		 816static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
817{
818 uint32_t ndcr = nand_readl(info, NDCR);
18c81b18 819 info->page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
38caf7f6 820 /* set info fields needed to read id */
18c81b18 821 info->read_id_bytes = (info->page_size == 2048) ? 4 : 2;
0fab028b 822 info->reg_ndcr = ndcr & ~NDCR_INT_MASK;
52d039fd 823 info->cmdset = &default_cmdset;
f271049e 824
18c81b18
LW		 825 info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
826 info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
f271049e
MR		 827
828 return 0;
829}
830
fe69af00 831/* the maximum possible buffer size for large page with OOB data
832 * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
833 * data buffer and the DMA descriptor
834 */
835#define MAX_BUFF_SIZE PAGE_SIZE
836
837static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
838{
839 struct platform_device *pdev = info->pdev;
840 int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
841
842 if (use_dma == 0) {
843 info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
844 if (info->data_buff == NULL)
845 return -ENOMEM;
846 return 0;
847 }
848
849 info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
850 &info->data_buff_phys, GFP_KERNEL);
851 if (info->data_buff == NULL) {
852 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
853 return -ENOMEM;
854 }
855
856 info->data_buff_size = MAX_BUFF_SIZE;
857 info->data_desc = (void *)info->data_buff + data_desc_offset;
858 info->data_desc_addr = info->data_buff_phys + data_desc_offset;
859
860 info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
861 pxa3xx_nand_data_dma_irq, info);
862 if (info->data_dma_ch < 0) {
863 dev_err(&pdev->dev, "failed to request data dma\n");
864 dma_free_coherent(&pdev->dev, info->data_buff_size,
865 info->data_buff, info->data_buff_phys);
866 return info->data_dma_ch;
867 }
868
869 return 0;
870}
871
401e67e2
LW		 872static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
873{
874 struct mtd_info *mtd = info->mtd;
875 struct nand_chip *chip = mtd->priv;
fe69af00 876
401e67e2
LW		 877 /* use the common timing to make a try */
878 pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
879 chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
880 if (info->is_ready)
881 return 1;
882 else
883 return 0;
884}
fe69af00 885
401e67e2 886static int pxa3xx_nand_scan(struct mtd_info *mtd)
fe69af00 887{
401e67e2
LW		 888 struct pxa3xx_nand_info *info = mtd->priv;
889 struct platform_device *pdev = info->pdev;
890 struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
0fab028b 891 struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL;
401e67e2
LW		 892 const struct pxa3xx_nand_flash *f = NULL;
893 struct nand_chip *chip = mtd->priv;
894 uint32_t id = -1;
4332c116 895 uint64_t chipsize;
401e67e2
LW		 896 int i, ret, num;
897
898 if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
4332c116 899 goto KEEP_CONFIG;
401e67e2
LW		 900
901 ret = pxa3xx_nand_sensing(info);
902 if (!ret) {
903 kfree(mtd);
904 info->mtd = NULL;
da675b4e 905 dev_info(&info->pdev->dev, "There is no nand chip on cs 0!\n");
401e67e2
LW		 906
907 return -EINVAL;
908 }
909
910 chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
911 id = *((uint16_t *)(info->data_buff));
912 if (id != 0)
da675b4e 913 dev_info(&info->pdev->dev, "Detect a flash id %x\n", id);
401e67e2
LW		 914 else {
915 kfree(mtd);
916 info->mtd = NULL;
da675b4e
LW		 917 dev_warn(&info->pdev->dev,
918 "Read out ID 0, potential timing set wrong!!\n");
401e67e2
LW		 919
920 return -EINVAL;
921 }
922
923 num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1;
924 for (i = 0; i < num; i++) {
925 if (i < pdata->num_flash)
926 f = pdata->flash + i;
927 else
928 f = &builtin_flash_types[i - pdata->num_flash + 1];
929
930 /* find the chip in default list */
4332c116 931 if (f->chip_id == id)
401e67e2 932 break;
401e67e2
LW		 933 }
934
4332c116 935 if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) {
401e67e2
LW		 936 kfree(mtd);
937 info->mtd = NULL;
da675b4e 938 dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n");
401e67e2
LW		 939
940 return -EINVAL;
941 }
942
4332c116
LW		 943 pxa3xx_nand_config_flash(info, f);
944 pxa3xx_flash_ids[0].name = f->name;
945 pxa3xx_flash_ids[0].id = (f->chip_id >> 8) & 0xffff;
946 pxa3xx_flash_ids[0].pagesize = f->page_size;
947 chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size;
948 pxa3xx_flash_ids[0].chipsize = chipsize >> 20;
949 pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block;
950 if (f->flash_width == 16)
951 pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16;
0fab028b
LW		 952 pxa3xx_flash_ids[1].name = NULL;
953 def = pxa3xx_flash_ids;
4332c116 954KEEP_CONFIG:
0fab028b 955 if (nand_scan_ident(mtd, 1, def))
4332c116
LW		 956 return -ENODEV;
957 /* calculate addressing information */
958 info->col_addr_cycles = (mtd->writesize >= 2048) ? 2 : 1;
959 info->oob_buff = info->data_buff + mtd->writesize;
960 if ((mtd->size >> chip->page_shift) > 65536)
961 info->row_addr_cycles = 3;
962 else
963 info->row_addr_cycles = 2;
964 mtd->name = mtd_names[0];
401e67e2 965 chip->ecc.mode = NAND_ECC_HW;
0fab028b 966 chip->ecc.size = info->page_size;
401e67e2 967
0fab028b 968 chip->options = (info->reg_ndcr & NDCR_DWIDTH_M) ? NAND_BUSWIDTH_16 : 0;
401e67e2
LW		 969 chip->options |= NAND_NO_AUTOINCR;
970 chip->options |= NAND_NO_READRDY;
fe69af00 971
401e67e2 972 return nand_scan_tail(mtd);
fe69af00 973}
974
e353a20a
LW		 975static
976struct pxa3xx_nand_info *alloc_nand_resource(struct platform_device *pdev)
fe69af00 977{
fe69af00 978 struct pxa3xx_nand_info *info;
401e67e2 979 struct nand_chip *chip;
fe69af00 980 struct mtd_info *mtd;
981 struct resource *r;
e353a20a 982 int ret, irq;
fe69af00 983
984 mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct pxa3xx_nand_info),
985 GFP_KERNEL);
a1c06ee1 986 if (!mtd) {
fe69af00 987 dev_err(&pdev->dev, "failed to allocate memory\n");
e353a20a 988 return NULL;
a1c06ee1 989 }
fe69af00 990
991 info = (struct pxa3xx_nand_info *)(&mtd[1]);
401e67e2 992 chip = (struct nand_chip *)(&mtd[1]);
fe69af00 993 info->pdev = pdev;
e353a20a 994 info->mtd = mtd;
401e67e2 995 mtd->priv = info;
82a72d10 996 mtd->owner = THIS_MODULE;
fe69af00 997
401e67e2
LW		 998 chip->ecc.read_page = pxa3xx_nand_read_page_hwecc;
999 chip->ecc.write_page = pxa3xx_nand_write_page_hwecc;
1000 chip->controller = &info->controller;
1001 chip->waitfunc = pxa3xx_nand_waitfunc;
1002 chip->select_chip = pxa3xx_nand_select_chip;
1003 chip->dev_ready = pxa3xx_nand_dev_ready;
1004 chip->cmdfunc = pxa3xx_nand_cmdfunc;
1005 chip->read_word = pxa3xx_nand_read_word;
1006 chip->read_byte = pxa3xx_nand_read_byte;
1007 chip->read_buf = pxa3xx_nand_read_buf;
1008 chip->write_buf = pxa3xx_nand_write_buf;
1009 chip->verify_buf = pxa3xx_nand_verify_buf;
1010
1011 spin_lock_init(&chip->controller->lock);
1012 init_waitqueue_head(&chip->controller->wq);
e0d8b13a 1013 info->clk = clk_get(&pdev->dev, NULL);
fe69af00 1014 if (IS_ERR(info->clk)) {
1015 dev_err(&pdev->dev, "failed to get nand clock\n");
1016 ret = PTR_ERR(info->clk);
1017 goto fail_free_mtd;
1018 }
1019 clk_enable(info->clk);
1020
1021 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1022 if (r == NULL) {
1023 dev_err(&pdev->dev, "no resource defined for data DMA\n");
1024 ret = -ENXIO;
1025 goto fail_put_clk;
1026 }
1027 info->drcmr_dat = r->start;
1028
1029 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1030 if (r == NULL) {
1031 dev_err(&pdev->dev, "no resource defined for command DMA\n");
1032 ret = -ENXIO;
1033 goto fail_put_clk;
1034 }
1035 info->drcmr_cmd = r->start;
1036
1037 irq = platform_get_irq(pdev, 0);
1038 if (irq < 0) {
1039 dev_err(&pdev->dev, "no IRQ resource defined\n");
1040 ret = -ENXIO;
1041 goto fail_put_clk;
1042 }
1043
1044 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1045 if (r == NULL) {
1046 dev_err(&pdev->dev, "no IO memory resource defined\n");
1047 ret = -ENODEV;
1048 goto fail_put_clk;
1049 }
1050
b2ed3680 1051 r = request_mem_region(r->start, resource_size(r), pdev->name);
fe69af00 1052 if (r == NULL) {
1053 dev_err(&pdev->dev, "failed to request memory resource\n");
1054 ret = -EBUSY;
1055 goto fail_put_clk;
1056 }
1057
b2ed3680 1058 info->mmio_base = ioremap(r->start, resource_size(r));
fe69af00 1059 if (info->mmio_base == NULL) {
1060 dev_err(&pdev->dev, "ioremap() failed\n");
1061 ret = -ENODEV;
1062 goto fail_free_res;
1063 }
8638fac8 1064 info->mmio_phys = r->start;
fe69af00 1065
1066 ret = pxa3xx_nand_init_buff(info);
1067 if (ret)
1068 goto fail_free_io;
1069
346e1259
HZ		 1070 /* initialize all interrupts to be disabled */
1071 disable_int(info, NDSR_MASK);
1072
dbf5986a
HZ		 1073 ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED,
1074 pdev->name, info);
fe69af00 1075 if (ret < 0) {
1076 dev_err(&pdev->dev, "failed to request IRQ\n");
1077 goto fail_free_buf;
1078 }
1079
e353a20a 1080 platform_set_drvdata(pdev, info);
fe69af00 1081
e353a20a 1082 return info;
fe69af00 1083
fe69af00 1084fail_free_buf:
401e67e2 1085 free_irq(irq, info);
fe69af00 1086 if (use_dma) {
1087 pxa_free_dma(info->data_dma_ch);
1088 dma_free_coherent(&pdev->dev, info->data_buff_size,
1089 info->data_buff, info->data_buff_phys);
1090 } else
1091 kfree(info->data_buff);
1092fail_free_io:
1093 iounmap(info->mmio_base);
1094fail_free_res:
b2ed3680 1095 release_mem_region(r->start, resource_size(r));
fe69af00 1096fail_put_clk:
1097 clk_disable(info->clk);
1098 clk_put(info->clk);
1099fail_free_mtd:
1100 kfree(mtd);
e353a20a 1101 return NULL;
fe69af00 1102}
1103
1104static int pxa3xx_nand_remove(struct platform_device *pdev)
1105{
e353a20a
LW		 1106 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1107 struct mtd_info *mtd = info->mtd;
82a72d10 1108 struct resource *r;
dbf5986a 1109 int irq;
fe69af00 1110
1111 platform_set_drvdata(pdev, NULL);
1112
dbf5986a
HZ		 1113 irq = platform_get_irq(pdev, 0);
1114 if (irq >= 0)
1115 free_irq(irq, info);
fe69af00 1116 if (use_dma) {
1117 pxa_free_dma(info->data_dma_ch);
1118 dma_free_writecombine(&pdev->dev, info->data_buff_size,
1119 info->data_buff, info->data_buff_phys);
1120 } else
1121 kfree(info->data_buff);
82a72d10
MR		 1122
1123 iounmap(info->mmio_base);
1124 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1125 release_mem_region(r->start, resource_size(r));
1126
1127 clk_disable(info->clk);
1128 clk_put(info->clk);
1129
f8155a40 1130 if (mtd) {
1a359192 1131 nand_release(mtd);
f8155a40
LW		 1132 kfree(mtd);
1133 }
fe69af00 1134 return 0;
1135}
1136
e353a20a
LW		 1137static int pxa3xx_nand_probe(struct platform_device *pdev)
1138{
1139 struct pxa3xx_nand_platform_data *pdata;
1140 struct pxa3xx_nand_info *info;
1141
1142 pdata = pdev->dev.platform_data;
1143 if (!pdata) {
1144 dev_err(&pdev->dev, "no platform data defined\n");
1145 return -ENODEV;
1146 }
1147
1148 info = alloc_nand_resource(pdev);
1149 if (info == NULL)
1150 return -ENOMEM;
1151
401e67e2 1152 if (pxa3xx_nand_scan(info->mtd)) {
e353a20a
LW		 1153 dev_err(&pdev->dev, "failed to scan nand\n");
1154 pxa3xx_nand_remove(pdev);
1155 return -ENODEV;
1156 }
1157
ee0f6a15
DES		 1158 return mtd_device_parse_register(info->mtd, NULL, 0,
1159 pdata->parts, pdata->nr_parts);
e353a20a
LW		 1160}
1161
fe69af00 1162#ifdef CONFIG_PM
1163static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1164{
e353a20a 1165 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
051fc41c 1166 struct mtd_info *mtd = info->mtd;
fe69af00 1167
f8155a40 1168 if (info->state) {
fe69af00 1169 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1170 return -EAGAIN;
1171 }
1172
051fc41c 1173 mtd->suspend(mtd);
fe69af00 1174 return 0;
1175}
1176
1177static int pxa3xx_nand_resume(struct platform_device *pdev)
1178{
e353a20a 1179 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
051fc41c
LW		 1180 struct mtd_info *mtd = info->mtd;
1181
1182 /* We don't want to handle interrupt without calling mtd routine */
1183 disable_int(info, NDCR_INT_MASK);
fe69af00 1184
18c81b18
LW		 1185 nand_writel(info, NDTR0CS0, info->ndtr0cs0);
1186 nand_writel(info, NDTR1CS0, info->ndtr1cs0);
fe69af00 1187
051fc41c
LW		 1188 /*
1189 * As the spec says, the NDSR would be updated to 0x1800 when
1190 * doing the nand_clk disable/enable.
1191 * To prevent it damaging state machine of the driver, clear
1192 * all status before resume
1193 */
1194 nand_writel(info, NDSR, NDSR_MASK);
1195 mtd->resume(mtd);
18c81b18 1196 return 0;
fe69af00 1197}
1198#else
1199#define pxa3xx_nand_suspend NULL
1200#define pxa3xx_nand_resume NULL
1201#endif
1202
1203static struct platform_driver pxa3xx_nand_driver = {
1204 .driver = {
1205 .name = "pxa3xx-nand",
1206 },
1207 .probe = pxa3xx_nand_probe,
1208 .remove = pxa3xx_nand_remove,
1209 .suspend = pxa3xx_nand_suspend,
1210 .resume = pxa3xx_nand_resume,
1211};
1212
1213static int __init pxa3xx_nand_init(void)
1214{
1215 return platform_driver_register(&pxa3xx_nand_driver);
1216}
1217module_init(pxa3xx_nand_init);
1218
1219static void __exit pxa3xx_nand_exit(void)
1220{
1221 platform_driver_unregister(&pxa3xx_nand_driver);
1222}
1223module_exit(pxa3xx_nand_exit);
1224
1225MODULE_LICENSE("GPL");
1226MODULE_DESCRIPTION("PXA3xx NAND controller driver");
Linux kernel - Deliverables
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