Commit | Line | Data |
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fe69af00 | 1 | /* |
2 | * drivers/mtd/nand/pxa3xx_nand.c | |
3 | * | |
4 | * Copyright © 2005 Intel Corporation | |
5 | * Copyright © 2006 Marvell International Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
a88bdbb5 | 12 | #include <linux/kernel.h> |
fe69af00 | 13 | #include <linux/module.h> |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/mtd/mtd.h> | |
20 | #include <linux/mtd/nand.h> | |
21 | #include <linux/mtd/partitions.h> | |
a1c06ee1 DW |
22 | #include <linux/io.h> |
23 | #include <linux/irq.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
fe69af00 | 25 | |
afb5b5c9 | 26 | #include <mach/dma.h> |
82b95ecb | 27 | #include <plat/pxa3xx_nand.h> |
fe69af00 | 28 | |
29 | #define CHIP_DELAY_TIMEOUT (2 * HZ/10) | |
f8155a40 | 30 | #define NAND_STOP_DELAY (2 * HZ/50) |
4eb2da89 | 31 | #define PAGE_CHUNK_SIZE (2048) |
fe69af00 | 32 | |
33 | /* registers and bit definitions */ | |
34 | #define NDCR (0x00) /* Control register */ | |
35 | #define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */ | |
36 | #define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */ | |
37 | #define NDSR (0x14) /* Status Register */ | |
38 | #define NDPCR (0x18) /* Page Count Register */ | |
39 | #define NDBDR0 (0x1C) /* Bad Block Register 0 */ | |
40 | #define NDBDR1 (0x20) /* Bad Block Register 1 */ | |
41 | #define NDDB (0x40) /* Data Buffer */ | |
42 | #define NDCB0 (0x48) /* Command Buffer0 */ | |
43 | #define NDCB1 (0x4C) /* Command Buffer1 */ | |
44 | #define NDCB2 (0x50) /* Command Buffer2 */ | |
45 | ||
46 | #define NDCR_SPARE_EN (0x1 << 31) | |
47 | #define NDCR_ECC_EN (0x1 << 30) | |
48 | #define NDCR_DMA_EN (0x1 << 29) | |
49 | #define NDCR_ND_RUN (0x1 << 28) | |
50 | #define NDCR_DWIDTH_C (0x1 << 27) | |
51 | #define NDCR_DWIDTH_M (0x1 << 26) | |
52 | #define NDCR_PAGE_SZ (0x1 << 24) | |
53 | #define NDCR_NCSX (0x1 << 23) | |
54 | #define NDCR_ND_MODE (0x3 << 21) | |
55 | #define NDCR_NAND_MODE (0x0) | |
56 | #define NDCR_CLR_PG_CNT (0x1 << 20) | |
f8155a40 | 57 | #define NDCR_STOP_ON_UNCOR (0x1 << 19) |
fe69af00 | 58 | #define NDCR_RD_ID_CNT_MASK (0x7 << 16) |
59 | #define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK) | |
60 | ||
61 | #define NDCR_RA_START (0x1 << 15) | |
62 | #define NDCR_PG_PER_BLK (0x1 << 14) | |
63 | #define NDCR_ND_ARB_EN (0x1 << 12) | |
f8155a40 | 64 | #define NDCR_INT_MASK (0xFFF) |
fe69af00 | 65 | |
66 | #define NDSR_MASK (0xfff) | |
f8155a40 LW |
67 | #define NDSR_RDY (0x1 << 12) |
68 | #define NDSR_FLASH_RDY (0x1 << 11) | |
fe69af00 | 69 | #define NDSR_CS0_PAGED (0x1 << 10) |
70 | #define NDSR_CS1_PAGED (0x1 << 9) | |
71 | #define NDSR_CS0_CMDD (0x1 << 8) | |
72 | #define NDSR_CS1_CMDD (0x1 << 7) | |
73 | #define NDSR_CS0_BBD (0x1 << 6) | |
74 | #define NDSR_CS1_BBD (0x1 << 5) | |
75 | #define NDSR_DBERR (0x1 << 4) | |
76 | #define NDSR_SBERR (0x1 << 3) | |
77 | #define NDSR_WRDREQ (0x1 << 2) | |
78 | #define NDSR_RDDREQ (0x1 << 1) | |
79 | #define NDSR_WRCMDREQ (0x1) | |
80 | ||
4eb2da89 | 81 | #define NDCB0_ST_ROW_EN (0x1 << 26) |
fe69af00 | 82 | #define NDCB0_AUTO_RS (0x1 << 25) |
83 | #define NDCB0_CSEL (0x1 << 24) | |
84 | #define NDCB0_CMD_TYPE_MASK (0x7 << 21) | |
85 | #define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK) | |
86 | #define NDCB0_NC (0x1 << 20) | |
87 | #define NDCB0_DBC (0x1 << 19) | |
88 | #define NDCB0_ADDR_CYC_MASK (0x7 << 16) | |
89 | #define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK) | |
90 | #define NDCB0_CMD2_MASK (0xff << 8) | |
91 | #define NDCB0_CMD1_MASK (0xff) | |
92 | #define NDCB0_ADDR_CYC_SHIFT (16) | |
93 | ||
fe69af00 | 94 | /* macros for registers read/write */ |
95 | #define nand_writel(info, off, val) \ | |
96 | __raw_writel((val), (info)->mmio_base + (off)) | |
97 | ||
98 | #define nand_readl(info, off) \ | |
99 | __raw_readl((info)->mmio_base + (off)) | |
100 | ||
101 | /* error code and state */ | |
102 | enum { | |
103 | ERR_NONE = 0, | |
104 | ERR_DMABUSERR = -1, | |
105 | ERR_SENDCMD = -2, | |
106 | ERR_DBERR = -3, | |
107 | ERR_BBERR = -4, | |
223cf6c3 | 108 | ERR_SBERR = -5, |
fe69af00 | 109 | }; |
110 | ||
111 | enum { | |
f8155a40 | 112 | STATE_IDLE = 0, |
d456882b | 113 | STATE_PREPARED, |
fe69af00 | 114 | STATE_CMD_HANDLE, |
115 | STATE_DMA_READING, | |
116 | STATE_DMA_WRITING, | |
117 | STATE_DMA_DONE, | |
118 | STATE_PIO_READING, | |
119 | STATE_PIO_WRITING, | |
f8155a40 LW |
120 | STATE_CMD_DONE, |
121 | STATE_READY, | |
fe69af00 | 122 | }; |
123 | ||
d456882b LW |
124 | struct pxa3xx_nand_host { |
125 | struct nand_chip chip; | |
126 | struct pxa3xx_nand_cmdset *cmdset; | |
127 | struct mtd_info *mtd; | |
128 | void *info_data; | |
129 | ||
130 | /* page size of attached chip */ | |
131 | unsigned int page_size; | |
132 | int use_ecc; | |
f3c8cfc2 | 133 | int cs; |
fe69af00 | 134 | |
d456882b LW |
135 | /* calculated from pxa3xx_nand_flash data */ |
136 | unsigned int col_addr_cycles; | |
137 | unsigned int row_addr_cycles; | |
138 | size_t read_id_bytes; | |
139 | ||
140 | /* cached register value */ | |
141 | uint32_t reg_ndcr; | |
142 | uint32_t ndtr0cs0; | |
143 | uint32_t ndtr1cs0; | |
144 | }; | |
145 | ||
146 | struct pxa3xx_nand_info { | |
401e67e2 | 147 | struct nand_hw_control controller; |
fe69af00 | 148 | struct platform_device *pdev; |
fe69af00 | 149 | |
150 | struct clk *clk; | |
151 | void __iomem *mmio_base; | |
8638fac8 | 152 | unsigned long mmio_phys; |
d456882b | 153 | struct completion cmd_complete; |
fe69af00 | 154 | |
155 | unsigned int buf_start; | |
156 | unsigned int buf_count; | |
157 | ||
158 | /* DMA information */ | |
159 | int drcmr_dat; | |
160 | int drcmr_cmd; | |
161 | ||
162 | unsigned char *data_buff; | |
18c81b18 | 163 | unsigned char *oob_buff; |
fe69af00 | 164 | dma_addr_t data_buff_phys; |
fe69af00 | 165 | int data_dma_ch; |
166 | struct pxa_dma_desc *data_desc; | |
167 | dma_addr_t data_desc_addr; | |
168 | ||
f3c8cfc2 | 169 | struct pxa3xx_nand_host *host[NUM_CHIP_SELECT]; |
fe69af00 | 170 | unsigned int state; |
171 | ||
f3c8cfc2 | 172 | int cs; |
fe69af00 | 173 | int use_ecc; /* use HW ECC ? */ |
174 | int use_dma; /* use DMA ? */ | |
401e67e2 | 175 | int is_ready; |
fe69af00 | 176 | |
18c81b18 LW |
177 | unsigned int page_size; /* page size of attached chip */ |
178 | unsigned int data_size; /* data size in FIFO */ | |
d456882b | 179 | unsigned int oob_size; |
fe69af00 | 180 | int retcode; |
fe69af00 | 181 | |
182 | /* generated NDCBx register values */ | |
183 | uint32_t ndcb0; | |
184 | uint32_t ndcb1; | |
185 | uint32_t ndcb2; | |
186 | }; | |
187 | ||
188 | static int use_dma = 1; | |
189 | module_param(use_dma, bool, 0444); | |
25985edc | 190 | MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW"); |
fe69af00 | 191 | |
f271049e MR |
192 | /* |
193 | * Default NAND flash controller configuration setup by the | |
194 | * bootloader. This configuration is used only when pdata->keep_config is set | |
195 | */ | |
c1f82478 | 196 | static struct pxa3xx_nand_cmdset default_cmdset = { |
fe69af00 | 197 | .read1 = 0x3000, |
198 | .read2 = 0x0050, | |
199 | .program = 0x1080, | |
200 | .read_status = 0x0070, | |
201 | .read_id = 0x0090, | |
202 | .erase = 0xD060, | |
203 | .reset = 0x00FF, | |
204 | .lock = 0x002A, | |
205 | .unlock = 0x2423, | |
206 | .lock_status = 0x007A, | |
207 | }; | |
208 | ||
c1f82478 | 209 | static struct pxa3xx_nand_timing timing[] = { |
227a886c LW |
210 | { 40, 80, 60, 100, 80, 100, 90000, 400, 40, }, |
211 | { 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, | |
212 | { 10, 25, 15, 25, 15, 30, 25000, 60, 10, }, | |
213 | { 10, 35, 15, 25, 15, 25, 25000, 60, 10, }, | |
d3490dfd HZ |
214 | }; |
215 | ||
c1f82478 | 216 | static struct pxa3xx_nand_flash builtin_flash_types[] = { |
4332c116 LW |
217 | { "DEFAULT FLASH", 0, 0, 2048, 8, 8, 0, &timing[0] }, |
218 | { "64MiB 16-bit", 0x46ec, 32, 512, 16, 16, 4096, &timing[1] }, | |
219 | { "256MiB 8-bit", 0xdaec, 64, 2048, 8, 8, 2048, &timing[1] }, | |
220 | { "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, 8192, &timing[1] }, | |
221 | { "128MiB 8-bit", 0xa12c, 64, 2048, 8, 8, 1024, &timing[2] }, | |
222 | { "128MiB 16-bit", 0xb12c, 64, 2048, 16, 16, 1024, &timing[2] }, | |
223 | { "512MiB 8-bit", 0xdc2c, 64, 2048, 8, 8, 4096, &timing[2] }, | |
224 | { "512MiB 16-bit", 0xcc2c, 64, 2048, 16, 16, 4096, &timing[2] }, | |
225 | { "256MiB 16-bit", 0xba20, 64, 2048, 16, 16, 2048, &timing[3] }, | |
d3490dfd HZ |
226 | }; |
227 | ||
227a886c LW |
228 | /* Define a default flash type setting serve as flash detecting only */ |
229 | #define DEFAULT_FLASH_TYPE (&builtin_flash_types[0]) | |
230 | ||
f3c8cfc2 | 231 | const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL}; |
401e67e2 | 232 | |
fe69af00 | 233 | #define NDTR0_tCH(c) (min((c), 7) << 19) |
234 | #define NDTR0_tCS(c) (min((c), 7) << 16) | |
235 | #define NDTR0_tWH(c) (min((c), 7) << 11) | |
236 | #define NDTR0_tWP(c) (min((c), 7) << 8) | |
237 | #define NDTR0_tRH(c) (min((c), 7) << 3) | |
238 | #define NDTR0_tRP(c) (min((c), 7) << 0) | |
239 | ||
240 | #define NDTR1_tR(c) (min((c), 65535) << 16) | |
241 | #define NDTR1_tWHR(c) (min((c), 15) << 4) | |
242 | #define NDTR1_tAR(c) (min((c), 15) << 0) | |
243 | ||
244 | /* convert nano-seconds to nand flash controller clock cycles */ | |
93b352fc | 245 | #define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000) |
fe69af00 | 246 | |
d456882b | 247 | static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host, |
7dad482e | 248 | const struct pxa3xx_nand_timing *t) |
fe69af00 | 249 | { |
d456882b | 250 | struct pxa3xx_nand_info *info = host->info_data; |
fe69af00 | 251 | unsigned long nand_clk = clk_get_rate(info->clk); |
252 | uint32_t ndtr0, ndtr1; | |
253 | ||
254 | ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) | | |
255 | NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) | | |
256 | NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) | | |
257 | NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) | | |
258 | NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) | | |
259 | NDTR0_tRP(ns2cycle(t->tRP, nand_clk)); | |
260 | ||
261 | ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | | |
262 | NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) | | |
263 | NDTR1_tAR(ns2cycle(t->tAR, nand_clk)); | |
264 | ||
d456882b LW |
265 | host->ndtr0cs0 = ndtr0; |
266 | host->ndtr1cs0 = ndtr1; | |
fe69af00 | 267 | nand_writel(info, NDTR0CS0, ndtr0); |
268 | nand_writel(info, NDTR1CS0, ndtr1); | |
269 | } | |
270 | ||
18c81b18 | 271 | static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info) |
fe69af00 | 272 | { |
f3c8cfc2 | 273 | struct pxa3xx_nand_host *host = info->host[info->cs]; |
d456882b | 274 | int oob_enable = host->reg_ndcr & NDCR_SPARE_EN; |
9d8b1043 | 275 | |
d456882b | 276 | info->data_size = host->page_size; |
9d8b1043 LW |
277 | if (!oob_enable) { |
278 | info->oob_size = 0; | |
279 | return; | |
280 | } | |
281 | ||
d456882b | 282 | switch (host->page_size) { |
fe69af00 | 283 | case 2048: |
9d8b1043 | 284 | info->oob_size = (info->use_ecc) ? 40 : 64; |
fe69af00 | 285 | break; |
286 | case 512: | |
9d8b1043 | 287 | info->oob_size = (info->use_ecc) ? 8 : 16; |
fe69af00 | 288 | break; |
fe69af00 | 289 | } |
18c81b18 LW |
290 | } |
291 | ||
f8155a40 LW |
292 | /** |
293 | * NOTE: it is a must to set ND_RUN firstly, then write | |
294 | * command buffer, otherwise, it does not work. | |
295 | * We enable all the interrupt at the same time, and | |
296 | * let pxa3xx_nand_irq to handle all logic. | |
297 | */ | |
298 | static void pxa3xx_nand_start(struct pxa3xx_nand_info *info) | |
299 | { | |
f3c8cfc2 | 300 | struct pxa3xx_nand_host *host = info->host[info->cs]; |
f8155a40 LW |
301 | uint32_t ndcr; |
302 | ||
d456882b | 303 | ndcr = host->reg_ndcr; |
f8155a40 LW |
304 | ndcr |= info->use_ecc ? NDCR_ECC_EN : 0; |
305 | ndcr |= info->use_dma ? NDCR_DMA_EN : 0; | |
306 | ndcr |= NDCR_ND_RUN; | |
307 | ||
308 | /* clear status bits and run */ | |
309 | nand_writel(info, NDCR, 0); | |
310 | nand_writel(info, NDSR, NDSR_MASK); | |
311 | nand_writel(info, NDCR, ndcr); | |
312 | } | |
313 | ||
314 | static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info) | |
315 | { | |
316 | uint32_t ndcr; | |
317 | int timeout = NAND_STOP_DELAY; | |
318 | ||
319 | /* wait RUN bit in NDCR become 0 */ | |
320 | ndcr = nand_readl(info, NDCR); | |
321 | while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) { | |
322 | ndcr = nand_readl(info, NDCR); | |
323 | udelay(1); | |
324 | } | |
325 | ||
326 | if (timeout <= 0) { | |
327 | ndcr &= ~NDCR_ND_RUN; | |
328 | nand_writel(info, NDCR, ndcr); | |
329 | } | |
330 | /* clear status bits */ | |
331 | nand_writel(info, NDSR, NDSR_MASK); | |
332 | } | |
333 | ||
fe69af00 | 334 | static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) |
335 | { | |
336 | uint32_t ndcr; | |
337 | ||
338 | ndcr = nand_readl(info, NDCR); | |
339 | nand_writel(info, NDCR, ndcr & ~int_mask); | |
340 | } | |
341 | ||
342 | static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) | |
343 | { | |
344 | uint32_t ndcr; | |
345 | ||
346 | ndcr = nand_readl(info, NDCR); | |
347 | nand_writel(info, NDCR, ndcr | int_mask); | |
348 | } | |
349 | ||
f8155a40 | 350 | static void handle_data_pio(struct pxa3xx_nand_info *info) |
fe69af00 | 351 | { |
fe69af00 | 352 | switch (info->state) { |
353 | case STATE_PIO_WRITING: | |
354 | __raw_writesl(info->mmio_base + NDDB, info->data_buff, | |
a88bdbb5 | 355 | DIV_ROUND_UP(info->data_size, 4)); |
9d8b1043 LW |
356 | if (info->oob_size > 0) |
357 | __raw_writesl(info->mmio_base + NDDB, info->oob_buff, | |
358 | DIV_ROUND_UP(info->oob_size, 4)); | |
fe69af00 | 359 | break; |
360 | case STATE_PIO_READING: | |
361 | __raw_readsl(info->mmio_base + NDDB, info->data_buff, | |
a88bdbb5 | 362 | DIV_ROUND_UP(info->data_size, 4)); |
9d8b1043 LW |
363 | if (info->oob_size > 0) |
364 | __raw_readsl(info->mmio_base + NDDB, info->oob_buff, | |
365 | DIV_ROUND_UP(info->oob_size, 4)); | |
fe69af00 | 366 | break; |
367 | default: | |
da675b4e | 368 | dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, |
fe69af00 | 369 | info->state); |
f8155a40 | 370 | BUG(); |
fe69af00 | 371 | } |
fe69af00 | 372 | } |
373 | ||
f8155a40 | 374 | static void start_data_dma(struct pxa3xx_nand_info *info) |
fe69af00 | 375 | { |
376 | struct pxa_dma_desc *desc = info->data_desc; | |
9d8b1043 | 377 | int dma_len = ALIGN(info->data_size + info->oob_size, 32); |
fe69af00 | 378 | |
379 | desc->ddadr = DDADR_STOP; | |
380 | desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len; | |
381 | ||
f8155a40 LW |
382 | switch (info->state) { |
383 | case STATE_DMA_WRITING: | |
fe69af00 | 384 | desc->dsadr = info->data_buff_phys; |
8638fac8 | 385 | desc->dtadr = info->mmio_phys + NDDB; |
fe69af00 | 386 | desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG; |
f8155a40 LW |
387 | break; |
388 | case STATE_DMA_READING: | |
fe69af00 | 389 | desc->dtadr = info->data_buff_phys; |
8638fac8 | 390 | desc->dsadr = info->mmio_phys + NDDB; |
fe69af00 | 391 | desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC; |
f8155a40 LW |
392 | break; |
393 | default: | |
da675b4e | 394 | dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, |
f8155a40 LW |
395 | info->state); |
396 | BUG(); | |
fe69af00 | 397 | } |
398 | ||
399 | DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch; | |
400 | DDADR(info->data_dma_ch) = info->data_desc_addr; | |
401 | DCSR(info->data_dma_ch) |= DCSR_RUN; | |
402 | } | |
403 | ||
404 | static void pxa3xx_nand_data_dma_irq(int channel, void *data) | |
405 | { | |
406 | struct pxa3xx_nand_info *info = data; | |
407 | uint32_t dcsr; | |
408 | ||
409 | dcsr = DCSR(channel); | |
410 | DCSR(channel) = dcsr; | |
411 | ||
412 | if (dcsr & DCSR_BUSERR) { | |
413 | info->retcode = ERR_DMABUSERR; | |
fe69af00 | 414 | } |
415 | ||
f8155a40 LW |
416 | info->state = STATE_DMA_DONE; |
417 | enable_int(info, NDCR_INT_MASK); | |
418 | nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ); | |
fe69af00 | 419 | } |
420 | ||
421 | static irqreturn_t pxa3xx_nand_irq(int irq, void *devid) | |
422 | { | |
423 | struct pxa3xx_nand_info *info = devid; | |
f8155a40 | 424 | unsigned int status, is_completed = 0; |
f3c8cfc2 LW |
425 | unsigned int ready, cmd_done; |
426 | ||
427 | if (info->cs == 0) { | |
428 | ready = NDSR_FLASH_RDY; | |
429 | cmd_done = NDSR_CS0_CMDD; | |
430 | } else { | |
431 | ready = NDSR_RDY; | |
432 | cmd_done = NDSR_CS1_CMDD; | |
433 | } | |
fe69af00 | 434 | |
435 | status = nand_readl(info, NDSR); | |
436 | ||
f8155a40 LW |
437 | if (status & NDSR_DBERR) |
438 | info->retcode = ERR_DBERR; | |
439 | if (status & NDSR_SBERR) | |
440 | info->retcode = ERR_SBERR; | |
441 | if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) { | |
442 | /* whether use dma to transfer data */ | |
fe69af00 | 443 | if (info->use_dma) { |
f8155a40 LW |
444 | disable_int(info, NDCR_INT_MASK); |
445 | info->state = (status & NDSR_RDDREQ) ? | |
446 | STATE_DMA_READING : STATE_DMA_WRITING; | |
447 | start_data_dma(info); | |
448 | goto NORMAL_IRQ_EXIT; | |
fe69af00 | 449 | } else { |
f8155a40 LW |
450 | info->state = (status & NDSR_RDDREQ) ? |
451 | STATE_PIO_READING : STATE_PIO_WRITING; | |
452 | handle_data_pio(info); | |
fe69af00 | 453 | } |
fe69af00 | 454 | } |
f3c8cfc2 | 455 | if (status & cmd_done) { |
f8155a40 LW |
456 | info->state = STATE_CMD_DONE; |
457 | is_completed = 1; | |
fe69af00 | 458 | } |
f3c8cfc2 | 459 | if (status & ready) { |
401e67e2 | 460 | info->is_ready = 1; |
f8155a40 | 461 | info->state = STATE_READY; |
401e67e2 | 462 | } |
fe69af00 | 463 | |
f8155a40 LW |
464 | if (status & NDSR_WRCMDREQ) { |
465 | nand_writel(info, NDSR, NDSR_WRCMDREQ); | |
466 | status &= ~NDSR_WRCMDREQ; | |
467 | info->state = STATE_CMD_HANDLE; | |
468 | nand_writel(info, NDCB0, info->ndcb0); | |
469 | nand_writel(info, NDCB0, info->ndcb1); | |
470 | nand_writel(info, NDCB0, info->ndcb2); | |
fe69af00 | 471 | } |
472 | ||
f8155a40 LW |
473 | /* clear NDSR to let the controller exit the IRQ */ |
474 | nand_writel(info, NDSR, status); | |
475 | if (is_completed) | |
476 | complete(&info->cmd_complete); | |
477 | NORMAL_IRQ_EXIT: | |
478 | return IRQ_HANDLED; | |
fe69af00 | 479 | } |
480 | ||
fe69af00 | 481 | static inline int is_buf_blank(uint8_t *buf, size_t len) |
482 | { | |
483 | for (; len > 0; len--) | |
484 | if (*buf++ != 0xff) | |
485 | return 0; | |
486 | return 1; | |
487 | } | |
488 | ||
4eb2da89 LW |
489 | static int prepare_command_pool(struct pxa3xx_nand_info *info, int command, |
490 | uint16_t column, int page_addr) | |
fe69af00 | 491 | { |
4eb2da89 | 492 | uint16_t cmd; |
d456882b | 493 | int addr_cycle, exec_cmd; |
f3c8cfc2 LW |
494 | struct pxa3xx_nand_host *host; |
495 | struct mtd_info *mtd; | |
fe69af00 | 496 | |
f3c8cfc2 LW |
497 | host = info->host[info->cs]; |
498 | mtd = host->mtd; | |
4eb2da89 LW |
499 | addr_cycle = 0; |
500 | exec_cmd = 1; | |
501 | ||
502 | /* reset data and oob column point to handle data */ | |
401e67e2 LW |
503 | info->buf_start = 0; |
504 | info->buf_count = 0; | |
4eb2da89 LW |
505 | info->oob_size = 0; |
506 | info->use_ecc = 0; | |
401e67e2 | 507 | info->is_ready = 0; |
4eb2da89 | 508 | info->retcode = ERR_NONE; |
f3c8cfc2 LW |
509 | if (info->cs != 0) |
510 | info->ndcb0 = NDCB0_CSEL; | |
511 | else | |
512 | info->ndcb0 = 0; | |
fe69af00 | 513 | |
514 | switch (command) { | |
4eb2da89 LW |
515 | case NAND_CMD_READ0: |
516 | case NAND_CMD_PAGEPROG: | |
517 | info->use_ecc = 1; | |
fe69af00 | 518 | case NAND_CMD_READOOB: |
4eb2da89 | 519 | pxa3xx_set_datasize(info); |
fe69af00 | 520 | break; |
4eb2da89 LW |
521 | case NAND_CMD_SEQIN: |
522 | exec_cmd = 0; | |
523 | break; | |
524 | default: | |
525 | info->ndcb1 = 0; | |
526 | info->ndcb2 = 0; | |
527 | break; | |
528 | } | |
529 | ||
d456882b LW |
530 | addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles |
531 | + host->col_addr_cycles); | |
fe69af00 | 532 | |
4eb2da89 LW |
533 | switch (command) { |
534 | case NAND_CMD_READOOB: | |
fe69af00 | 535 | case NAND_CMD_READ0: |
d456882b | 536 | cmd = host->cmdset->read1; |
4eb2da89 LW |
537 | if (command == NAND_CMD_READOOB) |
538 | info->buf_start = mtd->writesize + column; | |
539 | else | |
540 | info->buf_start = column; | |
541 | ||
d456882b | 542 | if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) |
4eb2da89 LW |
543 | info->ndcb0 |= NDCB0_CMD_TYPE(0) |
544 | | addr_cycle | |
545 | | (cmd & NDCB0_CMD1_MASK); | |
546 | else | |
547 | info->ndcb0 |= NDCB0_CMD_TYPE(0) | |
548 | | NDCB0_DBC | |
549 | | addr_cycle | |
550 | | cmd; | |
fe69af00 | 551 | |
fe69af00 | 552 | case NAND_CMD_SEQIN: |
4eb2da89 | 553 | /* small page addr setting */ |
d456882b | 554 | if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) { |
4eb2da89 LW |
555 | info->ndcb1 = ((page_addr & 0xFFFFFF) << 8) |
556 | | (column & 0xFF); | |
557 | ||
558 | info->ndcb2 = 0; | |
559 | } else { | |
560 | info->ndcb1 = ((page_addr & 0xFFFF) << 16) | |
561 | | (column & 0xFFFF); | |
562 | ||
563 | if (page_addr & 0xFF0000) | |
564 | info->ndcb2 = (page_addr & 0xFF0000) >> 16; | |
565 | else | |
566 | info->ndcb2 = 0; | |
567 | } | |
568 | ||
fe69af00 | 569 | info->buf_count = mtd->writesize + mtd->oobsize; |
4eb2da89 | 570 | memset(info->data_buff, 0xFF, info->buf_count); |
fe69af00 | 571 | |
fe69af00 | 572 | break; |
4eb2da89 | 573 | |
fe69af00 | 574 | case NAND_CMD_PAGEPROG: |
4eb2da89 LW |
575 | if (is_buf_blank(info->data_buff, |
576 | (mtd->writesize + mtd->oobsize))) { | |
577 | exec_cmd = 0; | |
578 | break; | |
579 | } | |
fe69af00 | 580 | |
d456882b | 581 | cmd = host->cmdset->program; |
4eb2da89 LW |
582 | info->ndcb0 |= NDCB0_CMD_TYPE(0x1) |
583 | | NDCB0_AUTO_RS | |
584 | | NDCB0_ST_ROW_EN | |
585 | | NDCB0_DBC | |
586 | | cmd | |
587 | | addr_cycle; | |
fe69af00 | 588 | break; |
4eb2da89 | 589 | |
fe69af00 | 590 | case NAND_CMD_READID: |
d456882b LW |
591 | cmd = host->cmdset->read_id; |
592 | info->buf_count = host->read_id_bytes; | |
4eb2da89 LW |
593 | info->ndcb0 |= NDCB0_CMD_TYPE(3) |
594 | | NDCB0_ADDR_CYC(1) | |
595 | | cmd; | |
596 | ||
597 | info->data_size = 8; | |
598 | break; | |
fe69af00 | 599 | case NAND_CMD_STATUS: |
d456882b | 600 | cmd = host->cmdset->read_status; |
4eb2da89 LW |
601 | info->buf_count = 1; |
602 | info->ndcb0 |= NDCB0_CMD_TYPE(4) | |
603 | | NDCB0_ADDR_CYC(1) | |
604 | | cmd; | |
605 | ||
606 | info->data_size = 8; | |
607 | break; | |
608 | ||
609 | case NAND_CMD_ERASE1: | |
d456882b | 610 | cmd = host->cmdset->erase; |
4eb2da89 LW |
611 | info->ndcb0 |= NDCB0_CMD_TYPE(2) |
612 | | NDCB0_AUTO_RS | |
613 | | NDCB0_ADDR_CYC(3) | |
614 | | NDCB0_DBC | |
615 | | cmd; | |
616 | info->ndcb1 = page_addr; | |
617 | info->ndcb2 = 0; | |
618 | ||
fe69af00 | 619 | break; |
620 | case NAND_CMD_RESET: | |
d456882b | 621 | cmd = host->cmdset->reset; |
4eb2da89 LW |
622 | info->ndcb0 |= NDCB0_CMD_TYPE(5) |
623 | | cmd; | |
624 | ||
625 | break; | |
626 | ||
627 | case NAND_CMD_ERASE2: | |
628 | exec_cmd = 0; | |
fe69af00 | 629 | break; |
4eb2da89 | 630 | |
fe69af00 | 631 | default: |
4eb2da89 | 632 | exec_cmd = 0; |
da675b4e LW |
633 | dev_err(&info->pdev->dev, "non-supported command %x\n", |
634 | command); | |
fe69af00 | 635 | break; |
636 | } | |
637 | ||
4eb2da89 LW |
638 | return exec_cmd; |
639 | } | |
640 | ||
641 | static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command, | |
642 | int column, int page_addr) | |
643 | { | |
d456882b LW |
644 | struct pxa3xx_nand_host *host = mtd->priv; |
645 | struct pxa3xx_nand_info *info = host->info_data; | |
4eb2da89 LW |
646 | int ret, exec_cmd; |
647 | ||
648 | /* | |
649 | * if this is a x16 device ,then convert the input | |
650 | * "byte" address into a "word" address appropriate | |
651 | * for indexing a word-oriented device | |
652 | */ | |
d456882b | 653 | if (host->reg_ndcr & NDCR_DWIDTH_M) |
4eb2da89 LW |
654 | column /= 2; |
655 | ||
f3c8cfc2 LW |
656 | /* |
657 | * There may be different NAND chip hooked to | |
658 | * different chip select, so check whether | |
659 | * chip select has been changed, if yes, reset the timing | |
660 | */ | |
661 | if (info->cs != host->cs) { | |
662 | info->cs = host->cs; | |
663 | nand_writel(info, NDTR0CS0, host->ndtr0cs0); | |
664 | nand_writel(info, NDTR1CS0, host->ndtr1cs0); | |
665 | } | |
666 | ||
d456882b | 667 | info->state = STATE_PREPARED; |
4eb2da89 | 668 | exec_cmd = prepare_command_pool(info, command, column, page_addr); |
f8155a40 LW |
669 | if (exec_cmd) { |
670 | init_completion(&info->cmd_complete); | |
671 | pxa3xx_nand_start(info); | |
672 | ||
673 | ret = wait_for_completion_timeout(&info->cmd_complete, | |
674 | CHIP_DELAY_TIMEOUT); | |
675 | if (!ret) { | |
da675b4e | 676 | dev_err(&info->pdev->dev, "Wait time out!!!\n"); |
f8155a40 LW |
677 | /* Stop State Machine for next command cycle */ |
678 | pxa3xx_nand_stop(info); | |
679 | } | |
f8155a40 | 680 | } |
d456882b | 681 | info->state = STATE_IDLE; |
f8155a40 LW |
682 | } |
683 | ||
684 | static void pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd, | |
685 | struct nand_chip *chip, const uint8_t *buf) | |
686 | { | |
687 | chip->write_buf(mtd, buf, mtd->writesize); | |
688 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
689 | } | |
690 | ||
691 | static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd, | |
692 | struct nand_chip *chip, uint8_t *buf, int page) | |
693 | { | |
d456882b LW |
694 | struct pxa3xx_nand_host *host = mtd->priv; |
695 | struct pxa3xx_nand_info *info = host->info_data; | |
f8155a40 LW |
696 | |
697 | chip->read_buf(mtd, buf, mtd->writesize); | |
698 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
699 | ||
700 | if (info->retcode == ERR_SBERR) { | |
701 | switch (info->use_ecc) { | |
702 | case 1: | |
703 | mtd->ecc_stats.corrected++; | |
704 | break; | |
705 | case 0: | |
706 | default: | |
707 | break; | |
708 | } | |
709 | } else if (info->retcode == ERR_DBERR) { | |
710 | /* | |
711 | * for blank page (all 0xff), HW will calculate its ECC as | |
712 | * 0, which is different from the ECC information within | |
713 | * OOB, ignore such double bit errors | |
714 | */ | |
715 | if (is_buf_blank(buf, mtd->writesize)) | |
543e32d5 DM |
716 | info->retcode = ERR_NONE; |
717 | else | |
f8155a40 | 718 | mtd->ecc_stats.failed++; |
fe69af00 | 719 | } |
f8155a40 LW |
720 | |
721 | return 0; | |
fe69af00 | 722 | } |
723 | ||
724 | static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd) | |
725 | { | |
d456882b LW |
726 | struct pxa3xx_nand_host *host = mtd->priv; |
727 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 728 | char retval = 0xFF; |
729 | ||
730 | if (info->buf_start < info->buf_count) | |
731 | /* Has just send a new command? */ | |
732 | retval = info->data_buff[info->buf_start++]; | |
733 | ||
734 | return retval; | |
735 | } | |
736 | ||
737 | static u16 pxa3xx_nand_read_word(struct mtd_info *mtd) | |
738 | { | |
d456882b LW |
739 | struct pxa3xx_nand_host *host = mtd->priv; |
740 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 741 | u16 retval = 0xFFFF; |
742 | ||
743 | if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) { | |
744 | retval = *((u16 *)(info->data_buff+info->buf_start)); | |
745 | info->buf_start += 2; | |
746 | } | |
747 | return retval; | |
748 | } | |
749 | ||
750 | static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
751 | { | |
d456882b LW |
752 | struct pxa3xx_nand_host *host = mtd->priv; |
753 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 754 | int real_len = min_t(size_t, len, info->buf_count - info->buf_start); |
755 | ||
756 | memcpy(buf, info->data_buff + info->buf_start, real_len); | |
757 | info->buf_start += real_len; | |
758 | } | |
759 | ||
760 | static void pxa3xx_nand_write_buf(struct mtd_info *mtd, | |
761 | const uint8_t *buf, int len) | |
762 | { | |
d456882b LW |
763 | struct pxa3xx_nand_host *host = mtd->priv; |
764 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 765 | int real_len = min_t(size_t, len, info->buf_count - info->buf_start); |
766 | ||
767 | memcpy(info->data_buff + info->buf_start, buf, real_len); | |
768 | info->buf_start += real_len; | |
769 | } | |
770 | ||
771 | static int pxa3xx_nand_verify_buf(struct mtd_info *mtd, | |
772 | const uint8_t *buf, int len) | |
773 | { | |
774 | return 0; | |
775 | } | |
776 | ||
777 | static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip) | |
778 | { | |
779 | return; | |
780 | } | |
781 | ||
782 | static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this) | |
783 | { | |
d456882b LW |
784 | struct pxa3xx_nand_host *host = mtd->priv; |
785 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 786 | |
787 | /* pxa3xx_nand_send_command has waited for command complete */ | |
788 | if (this->state == FL_WRITING || this->state == FL_ERASING) { | |
789 | if (info->retcode == ERR_NONE) | |
790 | return 0; | |
791 | else { | |
792 | /* | |
793 | * any error make it return 0x01 which will tell | |
794 | * the caller the erase and write fail | |
795 | */ | |
796 | return 0x01; | |
797 | } | |
798 | } | |
799 | ||
800 | return 0; | |
801 | } | |
802 | ||
fe69af00 | 803 | static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info, |
c8c17c88 | 804 | const struct pxa3xx_nand_flash *f) |
fe69af00 | 805 | { |
806 | struct platform_device *pdev = info->pdev; | |
807 | struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data; | |
f3c8cfc2 | 808 | struct pxa3xx_nand_host *host = info->host[info->cs]; |
f8155a40 | 809 | uint32_t ndcr = 0x0; /* enable all interrupts */ |
fe69af00 | 810 | |
da675b4e LW |
811 | if (f->page_size != 2048 && f->page_size != 512) { |
812 | dev_err(&pdev->dev, "Current only support 2048 and 512 size\n"); | |
fe69af00 | 813 | return -EINVAL; |
da675b4e | 814 | } |
fe69af00 | 815 | |
da675b4e LW |
816 | if (f->flash_width != 16 && f->flash_width != 8) { |
817 | dev_err(&pdev->dev, "Only support 8bit and 16 bit!\n"); | |
fe69af00 | 818 | return -EINVAL; |
da675b4e | 819 | } |
fe69af00 | 820 | |
821 | /* calculate flash information */ | |
d456882b LW |
822 | host->cmdset = &default_cmdset; |
823 | host->page_size = f->page_size; | |
824 | host->read_id_bytes = (f->page_size == 2048) ? 4 : 2; | |
fe69af00 | 825 | |
826 | /* calculate addressing information */ | |
d456882b | 827 | host->col_addr_cycles = (f->page_size == 2048) ? 2 : 1; |
fe69af00 | 828 | |
829 | if (f->num_blocks * f->page_per_block > 65536) | |
d456882b | 830 | host->row_addr_cycles = 3; |
fe69af00 | 831 | else |
d456882b | 832 | host->row_addr_cycles = 2; |
fe69af00 | 833 | |
834 | ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; | |
d456882b | 835 | ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0; |
fe69af00 | 836 | ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0; |
837 | ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0; | |
838 | ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0; | |
839 | ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0; | |
840 | ||
d456882b | 841 | ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes); |
fe69af00 | 842 | ndcr |= NDCR_SPARE_EN; /* enable spare by default */ |
843 | ||
d456882b | 844 | host->reg_ndcr = ndcr; |
fe69af00 | 845 | |
d456882b | 846 | pxa3xx_nand_set_timing(host, f->timing); |
fe69af00 | 847 | return 0; |
848 | } | |
849 | ||
f271049e MR |
850 | static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info) |
851 | { | |
f3c8cfc2 LW |
852 | /* |
853 | * We set 0 by hard coding here, for we don't support keep_config | |
854 | * when there is more than one chip attached to the controller | |
855 | */ | |
856 | struct pxa3xx_nand_host *host = info->host[0]; | |
f271049e | 857 | uint32_t ndcr = nand_readl(info, NDCR); |
f271049e | 858 | |
d456882b LW |
859 | if (ndcr & NDCR_PAGE_SZ) { |
860 | host->page_size = 2048; | |
861 | host->read_id_bytes = 4; | |
862 | } else { | |
863 | host->page_size = 512; | |
864 | host->read_id_bytes = 2; | |
865 | } | |
866 | ||
867 | host->reg_ndcr = ndcr & ~NDCR_INT_MASK; | |
868 | host->cmdset = &default_cmdset; | |
869 | ||
870 | host->ndtr0cs0 = nand_readl(info, NDTR0CS0); | |
871 | host->ndtr1cs0 = nand_readl(info, NDTR1CS0); | |
f271049e MR |
872 | |
873 | return 0; | |
874 | } | |
875 | ||
fe69af00 | 876 | /* the maximum possible buffer size for large page with OOB data |
877 | * is: 2048 + 64 = 2112 bytes, allocate a page here for both the | |
878 | * data buffer and the DMA descriptor | |
879 | */ | |
880 | #define MAX_BUFF_SIZE PAGE_SIZE | |
881 | ||
882 | static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info) | |
883 | { | |
884 | struct platform_device *pdev = info->pdev; | |
885 | int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc); | |
886 | ||
887 | if (use_dma == 0) { | |
888 | info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL); | |
889 | if (info->data_buff == NULL) | |
890 | return -ENOMEM; | |
891 | return 0; | |
892 | } | |
893 | ||
894 | info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE, | |
895 | &info->data_buff_phys, GFP_KERNEL); | |
896 | if (info->data_buff == NULL) { | |
897 | dev_err(&pdev->dev, "failed to allocate dma buffer\n"); | |
898 | return -ENOMEM; | |
899 | } | |
900 | ||
fe69af00 | 901 | info->data_desc = (void *)info->data_buff + data_desc_offset; |
902 | info->data_desc_addr = info->data_buff_phys + data_desc_offset; | |
903 | ||
904 | info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW, | |
905 | pxa3xx_nand_data_dma_irq, info); | |
906 | if (info->data_dma_ch < 0) { | |
907 | dev_err(&pdev->dev, "failed to request data dma\n"); | |
d456882b | 908 | dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE, |
fe69af00 | 909 | info->data_buff, info->data_buff_phys); |
910 | return info->data_dma_ch; | |
911 | } | |
912 | ||
913 | return 0; | |
914 | } | |
915 | ||
401e67e2 LW |
916 | static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info) |
917 | { | |
f3c8cfc2 | 918 | struct mtd_info *mtd; |
d456882b | 919 | int ret; |
f3c8cfc2 | 920 | mtd = info->host[info->cs]->mtd; |
401e67e2 | 921 | /* use the common timing to make a try */ |
d456882b LW |
922 | ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]); |
923 | if (ret) | |
924 | return ret; | |
925 | ||
926 | pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RESET, 0, 0); | |
401e67e2 | 927 | if (info->is_ready) |
401e67e2 | 928 | return 0; |
d456882b LW |
929 | |
930 | return -ENODEV; | |
401e67e2 | 931 | } |
fe69af00 | 932 | |
401e67e2 | 933 | static int pxa3xx_nand_scan(struct mtd_info *mtd) |
fe69af00 | 934 | { |
d456882b LW |
935 | struct pxa3xx_nand_host *host = mtd->priv; |
936 | struct pxa3xx_nand_info *info = host->info_data; | |
401e67e2 LW |
937 | struct platform_device *pdev = info->pdev; |
938 | struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data; | |
0fab028b | 939 | struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL; |
401e67e2 LW |
940 | const struct pxa3xx_nand_flash *f = NULL; |
941 | struct nand_chip *chip = mtd->priv; | |
942 | uint32_t id = -1; | |
4332c116 | 943 | uint64_t chipsize; |
401e67e2 LW |
944 | int i, ret, num; |
945 | ||
946 | if (pdata->keep_config && !pxa3xx_nand_detect_config(info)) | |
4332c116 | 947 | goto KEEP_CONFIG; |
401e67e2 LW |
948 | |
949 | ret = pxa3xx_nand_sensing(info); | |
d456882b | 950 | if (ret) { |
f3c8cfc2 LW |
951 | dev_info(&info->pdev->dev, "There is no chip on cs %d!\n", |
952 | info->cs); | |
401e67e2 | 953 | |
d456882b | 954 | return ret; |
401e67e2 LW |
955 | } |
956 | ||
957 | chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0); | |
958 | id = *((uint16_t *)(info->data_buff)); | |
959 | if (id != 0) | |
da675b4e | 960 | dev_info(&info->pdev->dev, "Detect a flash id %x\n", id); |
401e67e2 | 961 | else { |
da675b4e LW |
962 | dev_warn(&info->pdev->dev, |
963 | "Read out ID 0, potential timing set wrong!!\n"); | |
401e67e2 LW |
964 | |
965 | return -EINVAL; | |
966 | } | |
967 | ||
968 | num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; | |
969 | for (i = 0; i < num; i++) { | |
970 | if (i < pdata->num_flash) | |
971 | f = pdata->flash + i; | |
972 | else | |
973 | f = &builtin_flash_types[i - pdata->num_flash + 1]; | |
974 | ||
975 | /* find the chip in default list */ | |
4332c116 | 976 | if (f->chip_id == id) |
401e67e2 | 977 | break; |
401e67e2 LW |
978 | } |
979 | ||
4332c116 | 980 | if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) { |
da675b4e | 981 | dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n"); |
401e67e2 LW |
982 | |
983 | return -EINVAL; | |
984 | } | |
985 | ||
d456882b LW |
986 | ret = pxa3xx_nand_config_flash(info, f); |
987 | if (ret) { | |
988 | dev_err(&info->pdev->dev, "ERROR! Configure failed\n"); | |
989 | return ret; | |
990 | } | |
991 | ||
4332c116 LW |
992 | pxa3xx_flash_ids[0].name = f->name; |
993 | pxa3xx_flash_ids[0].id = (f->chip_id >> 8) & 0xffff; | |
994 | pxa3xx_flash_ids[0].pagesize = f->page_size; | |
995 | chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size; | |
996 | pxa3xx_flash_ids[0].chipsize = chipsize >> 20; | |
997 | pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block; | |
998 | if (f->flash_width == 16) | |
999 | pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16; | |
0fab028b LW |
1000 | pxa3xx_flash_ids[1].name = NULL; |
1001 | def = pxa3xx_flash_ids; | |
4332c116 | 1002 | KEEP_CONFIG: |
d456882b LW |
1003 | chip->ecc.mode = NAND_ECC_HW; |
1004 | chip->ecc.size = host->page_size; | |
1005 | ||
1006 | chip->options = NAND_NO_AUTOINCR; | |
1007 | chip->options |= NAND_NO_READRDY; | |
1008 | if (host->reg_ndcr & NDCR_DWIDTH_M) | |
1009 | chip->options |= NAND_BUSWIDTH_16; | |
1010 | ||
0fab028b | 1011 | if (nand_scan_ident(mtd, 1, def)) |
4332c116 LW |
1012 | return -ENODEV; |
1013 | /* calculate addressing information */ | |
d456882b LW |
1014 | if (mtd->writesize >= 2048) |
1015 | host->col_addr_cycles = 2; | |
1016 | else | |
1017 | host->col_addr_cycles = 1; | |
1018 | ||
4332c116 LW |
1019 | info->oob_buff = info->data_buff + mtd->writesize; |
1020 | if ((mtd->size >> chip->page_shift) > 65536) | |
d456882b | 1021 | host->row_addr_cycles = 3; |
4332c116 | 1022 | else |
d456882b | 1023 | host->row_addr_cycles = 2; |
fe69af00 | 1024 | |
d456882b | 1025 | mtd->name = mtd_names[0]; |
401e67e2 | 1026 | return nand_scan_tail(mtd); |
fe69af00 | 1027 | } |
1028 | ||
d456882b | 1029 | static int alloc_nand_resource(struct platform_device *pdev) |
fe69af00 | 1030 | { |
f3c8cfc2 | 1031 | struct pxa3xx_nand_platform_data *pdata; |
fe69af00 | 1032 | struct pxa3xx_nand_info *info; |
d456882b | 1033 | struct pxa3xx_nand_host *host; |
401e67e2 | 1034 | struct nand_chip *chip; |
fe69af00 | 1035 | struct mtd_info *mtd; |
1036 | struct resource *r; | |
f3c8cfc2 | 1037 | int ret, irq, cs; |
fe69af00 | 1038 | |
f3c8cfc2 LW |
1039 | pdata = pdev->dev.platform_data; |
1040 | info = kzalloc(sizeof(*info) + (sizeof(*mtd) + | |
1041 | sizeof(*host)) * pdata->num_cs, GFP_KERNEL); | |
d456882b | 1042 | if (!info) { |
fe69af00 | 1043 | dev_err(&pdev->dev, "failed to allocate memory\n"); |
d456882b | 1044 | return -ENOMEM; |
a1c06ee1 | 1045 | } |
fe69af00 | 1046 | |
fe69af00 | 1047 | info->pdev = pdev; |
f3c8cfc2 LW |
1048 | for (cs = 0; cs < pdata->num_cs; cs++) { |
1049 | mtd = (struct mtd_info *)((unsigned int)&info[1] + | |
1050 | (sizeof(*mtd) + sizeof(*host)) * cs); | |
1051 | chip = (struct nand_chip *)(&mtd[1]); | |
1052 | host = (struct pxa3xx_nand_host *)chip; | |
1053 | info->host[cs] = host; | |
1054 | host->mtd = mtd; | |
1055 | host->cs = cs; | |
1056 | host->info_data = info; | |
1057 | mtd->priv = host; | |
1058 | mtd->owner = THIS_MODULE; | |
1059 | ||
1060 | chip->ecc.read_page = pxa3xx_nand_read_page_hwecc; | |
1061 | chip->ecc.write_page = pxa3xx_nand_write_page_hwecc; | |
1062 | chip->controller = &info->controller; | |
1063 | chip->waitfunc = pxa3xx_nand_waitfunc; | |
1064 | chip->select_chip = pxa3xx_nand_select_chip; | |
1065 | chip->cmdfunc = pxa3xx_nand_cmdfunc; | |
1066 | chip->read_word = pxa3xx_nand_read_word; | |
1067 | chip->read_byte = pxa3xx_nand_read_byte; | |
1068 | chip->read_buf = pxa3xx_nand_read_buf; | |
1069 | chip->write_buf = pxa3xx_nand_write_buf; | |
1070 | chip->verify_buf = pxa3xx_nand_verify_buf; | |
1071 | } | |
401e67e2 LW |
1072 | |
1073 | spin_lock_init(&chip->controller->lock); | |
1074 | init_waitqueue_head(&chip->controller->wq); | |
e0d8b13a | 1075 | info->clk = clk_get(&pdev->dev, NULL); |
fe69af00 | 1076 | if (IS_ERR(info->clk)) { |
1077 | dev_err(&pdev->dev, "failed to get nand clock\n"); | |
1078 | ret = PTR_ERR(info->clk); | |
1079 | goto fail_free_mtd; | |
1080 | } | |
1081 | clk_enable(info->clk); | |
1082 | ||
1083 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
1084 | if (r == NULL) { | |
1085 | dev_err(&pdev->dev, "no resource defined for data DMA\n"); | |
1086 | ret = -ENXIO; | |
1087 | goto fail_put_clk; | |
1088 | } | |
1089 | info->drcmr_dat = r->start; | |
1090 | ||
1091 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
1092 | if (r == NULL) { | |
1093 | dev_err(&pdev->dev, "no resource defined for command DMA\n"); | |
1094 | ret = -ENXIO; | |
1095 | goto fail_put_clk; | |
1096 | } | |
1097 | info->drcmr_cmd = r->start; | |
1098 | ||
1099 | irq = platform_get_irq(pdev, 0); | |
1100 | if (irq < 0) { | |
1101 | dev_err(&pdev->dev, "no IRQ resource defined\n"); | |
1102 | ret = -ENXIO; | |
1103 | goto fail_put_clk; | |
1104 | } | |
1105 | ||
1106 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1107 | if (r == NULL) { | |
1108 | dev_err(&pdev->dev, "no IO memory resource defined\n"); | |
1109 | ret = -ENODEV; | |
1110 | goto fail_put_clk; | |
1111 | } | |
1112 | ||
b2ed3680 | 1113 | r = request_mem_region(r->start, resource_size(r), pdev->name); |
fe69af00 | 1114 | if (r == NULL) { |
1115 | dev_err(&pdev->dev, "failed to request memory resource\n"); | |
1116 | ret = -EBUSY; | |
1117 | goto fail_put_clk; | |
1118 | } | |
1119 | ||
b2ed3680 | 1120 | info->mmio_base = ioremap(r->start, resource_size(r)); |
fe69af00 | 1121 | if (info->mmio_base == NULL) { |
1122 | dev_err(&pdev->dev, "ioremap() failed\n"); | |
1123 | ret = -ENODEV; | |
1124 | goto fail_free_res; | |
1125 | } | |
8638fac8 | 1126 | info->mmio_phys = r->start; |
fe69af00 | 1127 | |
1128 | ret = pxa3xx_nand_init_buff(info); | |
1129 | if (ret) | |
1130 | goto fail_free_io; | |
1131 | ||
346e1259 HZ |
1132 | /* initialize all interrupts to be disabled */ |
1133 | disable_int(info, NDSR_MASK); | |
1134 | ||
dbf5986a HZ |
1135 | ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED, |
1136 | pdev->name, info); | |
fe69af00 | 1137 | if (ret < 0) { |
1138 | dev_err(&pdev->dev, "failed to request IRQ\n"); | |
1139 | goto fail_free_buf; | |
1140 | } | |
1141 | ||
e353a20a | 1142 | platform_set_drvdata(pdev, info); |
fe69af00 | 1143 | |
d456882b | 1144 | return 0; |
fe69af00 | 1145 | |
fe69af00 | 1146 | fail_free_buf: |
401e67e2 | 1147 | free_irq(irq, info); |
fe69af00 | 1148 | if (use_dma) { |
1149 | pxa_free_dma(info->data_dma_ch); | |
d456882b | 1150 | dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE, |
fe69af00 | 1151 | info->data_buff, info->data_buff_phys); |
1152 | } else | |
1153 | kfree(info->data_buff); | |
1154 | fail_free_io: | |
1155 | iounmap(info->mmio_base); | |
1156 | fail_free_res: | |
b2ed3680 | 1157 | release_mem_region(r->start, resource_size(r)); |
fe69af00 | 1158 | fail_put_clk: |
1159 | clk_disable(info->clk); | |
1160 | clk_put(info->clk); | |
1161 | fail_free_mtd: | |
d456882b LW |
1162 | kfree(info); |
1163 | return ret; | |
fe69af00 | 1164 | } |
1165 | ||
1166 | static int pxa3xx_nand_remove(struct platform_device *pdev) | |
1167 | { | |
e353a20a | 1168 | struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); |
f3c8cfc2 | 1169 | struct pxa3xx_nand_platform_data *pdata; |
82a72d10 | 1170 | struct resource *r; |
f3c8cfc2 | 1171 | int irq, cs; |
fe69af00 | 1172 | |
d456882b LW |
1173 | if (!info) |
1174 | return 0; | |
1175 | ||
f3c8cfc2 | 1176 | pdata = pdev->dev.platform_data; |
fe69af00 | 1177 | platform_set_drvdata(pdev, NULL); |
1178 | ||
dbf5986a HZ |
1179 | irq = platform_get_irq(pdev, 0); |
1180 | if (irq >= 0) | |
1181 | free_irq(irq, info); | |
fe69af00 | 1182 | if (use_dma) { |
1183 | pxa_free_dma(info->data_dma_ch); | |
d456882b | 1184 | dma_free_writecombine(&pdev->dev, MAX_BUFF_SIZE, |
fe69af00 | 1185 | info->data_buff, info->data_buff_phys); |
1186 | } else | |
1187 | kfree(info->data_buff); | |
82a72d10 MR |
1188 | |
1189 | iounmap(info->mmio_base); | |
1190 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1191 | release_mem_region(r->start, resource_size(r)); | |
1192 | ||
1193 | clk_disable(info->clk); | |
1194 | clk_put(info->clk); | |
1195 | ||
f3c8cfc2 LW |
1196 | for (cs = 0; cs < pdata->num_cs; cs++) |
1197 | nand_release(info->host[cs]->mtd); | |
d456882b | 1198 | kfree(info); |
fe69af00 | 1199 | return 0; |
1200 | } | |
1201 | ||
e353a20a LW |
1202 | static int pxa3xx_nand_probe(struct platform_device *pdev) |
1203 | { | |
1204 | struct pxa3xx_nand_platform_data *pdata; | |
1205 | struct pxa3xx_nand_info *info; | |
f3c8cfc2 | 1206 | int ret, cs, probe_success; |
e353a20a LW |
1207 | |
1208 | pdata = pdev->dev.platform_data; | |
1209 | if (!pdata) { | |
1210 | dev_err(&pdev->dev, "no platform data defined\n"); | |
1211 | return -ENODEV; | |
1212 | } | |
1213 | ||
d456882b LW |
1214 | ret = alloc_nand_resource(pdev); |
1215 | if (ret) { | |
1216 | dev_err(&pdev->dev, "alloc nand resource failed\n"); | |
1217 | return ret; | |
1218 | } | |
e353a20a | 1219 | |
d456882b | 1220 | info = platform_get_drvdata(pdev); |
f3c8cfc2 LW |
1221 | probe_success = 0; |
1222 | for (cs = 0; cs < pdata->num_cs; cs++) { | |
1223 | info->cs = cs; | |
1224 | ret = pxa3xx_nand_scan(info->host[cs]->mtd); | |
1225 | if (ret) { | |
1226 | dev_warn(&pdev->dev, "failed to scan nand at cs %d\n", | |
1227 | cs); | |
1228 | continue; | |
1229 | } | |
1230 | ||
1231 | ret = mtd_device_parse_register(info->host[cs]->mtd, NULL, 0, | |
1232 | pdata->parts[cs], pdata->nr_parts[cs]); | |
1233 | if (!ret) | |
1234 | probe_success = 1; | |
1235 | } | |
1236 | ||
1237 | if (!probe_success) { | |
e353a20a LW |
1238 | pxa3xx_nand_remove(pdev); |
1239 | return -ENODEV; | |
1240 | } | |
1241 | ||
f3c8cfc2 | 1242 | return 0; |
e353a20a LW |
1243 | } |
1244 | ||
fe69af00 | 1245 | #ifdef CONFIG_PM |
1246 | static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state) | |
1247 | { | |
e353a20a | 1248 | struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); |
f3c8cfc2 LW |
1249 | struct pxa3xx_nand_platform_data *pdata; |
1250 | struct mtd_info *mtd; | |
1251 | int cs; | |
fe69af00 | 1252 | |
f3c8cfc2 | 1253 | pdata = pdev->dev.platform_data; |
f8155a40 | 1254 | if (info->state) { |
fe69af00 | 1255 | dev_err(&pdev->dev, "driver busy, state = %d\n", info->state); |
1256 | return -EAGAIN; | |
1257 | } | |
1258 | ||
f3c8cfc2 LW |
1259 | for (cs = 0; cs < pdata->num_cs; cs++) { |
1260 | mtd = info->host[cs]->mtd; | |
1261 | mtd->suspend(mtd); | |
1262 | } | |
1263 | ||
fe69af00 | 1264 | return 0; |
1265 | } | |
1266 | ||
1267 | static int pxa3xx_nand_resume(struct platform_device *pdev) | |
1268 | { | |
e353a20a | 1269 | struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); |
f3c8cfc2 LW |
1270 | struct pxa3xx_nand_platform_data *pdata; |
1271 | struct mtd_info *mtd; | |
1272 | int cs; | |
051fc41c | 1273 | |
f3c8cfc2 | 1274 | pdata = pdev->dev.platform_data; |
051fc41c LW |
1275 | /* We don't want to handle interrupt without calling mtd routine */ |
1276 | disable_int(info, NDCR_INT_MASK); | |
fe69af00 | 1277 | |
f3c8cfc2 LW |
1278 | /* |
1279 | * Directly set the chip select to a invalid value, | |
1280 | * then the driver would reset the timing according | |
1281 | * to current chip select at the beginning of cmdfunc | |
1282 | */ | |
1283 | info->cs = 0xff; | |
fe69af00 | 1284 | |
051fc41c LW |
1285 | /* |
1286 | * As the spec says, the NDSR would be updated to 0x1800 when | |
1287 | * doing the nand_clk disable/enable. | |
1288 | * To prevent it damaging state machine of the driver, clear | |
1289 | * all status before resume | |
1290 | */ | |
1291 | nand_writel(info, NDSR, NDSR_MASK); | |
f3c8cfc2 LW |
1292 | for (cs = 0; cs < pdata->num_cs; cs++) { |
1293 | mtd = info->host[cs]->mtd; | |
1294 | mtd->resume(mtd); | |
1295 | } | |
1296 | ||
18c81b18 | 1297 | return 0; |
fe69af00 | 1298 | } |
1299 | #else | |
1300 | #define pxa3xx_nand_suspend NULL | |
1301 | #define pxa3xx_nand_resume NULL | |
1302 | #endif | |
1303 | ||
1304 | static struct platform_driver pxa3xx_nand_driver = { | |
1305 | .driver = { | |
1306 | .name = "pxa3xx-nand", | |
1307 | }, | |
1308 | .probe = pxa3xx_nand_probe, | |
1309 | .remove = pxa3xx_nand_remove, | |
1310 | .suspend = pxa3xx_nand_suspend, | |
1311 | .resume = pxa3xx_nand_resume, | |
1312 | }; | |
1313 | ||
f99640de | 1314 | module_platform_driver(pxa3xx_nand_driver); |
fe69af00 | 1315 | |
1316 | MODULE_LICENSE("GPL"); | |
1317 | MODULE_DESCRIPTION("PXA3xx NAND controller driver"); |