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1da177e4 LT |
1 | /* linux/drivers/mtd/nand/s3c2410.c |
2 | * | |
7e74a507 BD |
3 | * Copyright © 2004-2008 Simtec Electronics |
4 | * http://armlinux.simtec.co.uk/ | |
fdf2fd52 | 5 | * Ben Dooks <ben@simtec.co.uk> |
1da177e4 | 6 | * |
7e74a507 | 7 | * Samsung S3C2410/S3C2440/S3C2412 NAND driver |
1da177e4 | 8 | * |
1da177e4 LT |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | */ | |
23 | ||
92aeb5d2 SK |
24 | #define pr_fmt(fmt) "nand-s3c2410: " fmt |
25 | ||
1da177e4 LT |
26 | #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG |
27 | #define DEBUG | |
28 | #endif | |
29 | ||
30 | #include <linux/module.h> | |
31 | #include <linux/types.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/string.h> | |
d2a89be8 | 35 | #include <linux/io.h> |
1da177e4 | 36 | #include <linux/ioport.h> |
d052d1be | 37 | #include <linux/platform_device.h> |
1da177e4 LT |
38 | #include <linux/delay.h> |
39 | #include <linux/err.h> | |
4e57b681 | 40 | #include <linux/slab.h> |
f8ce2547 | 41 | #include <linux/clk.h> |
30821fee | 42 | #include <linux/cpufreq.h> |
1da177e4 LT |
43 | |
44 | #include <linux/mtd/mtd.h> | |
45 | #include <linux/mtd/nand.h> | |
46 | #include <linux/mtd/nand_ecc.h> | |
47 | #include <linux/mtd/partitions.h> | |
48 | ||
7926b5a3 | 49 | #include <plat/regs-nand.h> |
436d42c6 | 50 | #include <linux/platform_data/mtd-nand-s3c2410.h> |
1da177e4 | 51 | |
1da177e4 LT |
52 | /* new oob placement block for use with hardware ecc generation |
53 | */ | |
54 | ||
5bd34c09 | 55 | static struct nand_ecclayout nand_hw_eccoob = { |
e0c7d767 DW |
56 | .eccbytes = 3, |
57 | .eccpos = {0, 1, 2}, | |
58 | .oobfree = {{8, 8}} | |
1da177e4 LT |
59 | }; |
60 | ||
61 | /* controller and mtd information */ | |
62 | ||
63 | struct s3c2410_nand_info; | |
64 | ||
3db72151 BD |
65 | /** |
66 | * struct s3c2410_nand_mtd - driver MTD structure | |
67 | * @mtd: The MTD instance to pass to the MTD layer. | |
68 | * @chip: The NAND chip information. | |
69 | * @set: The platform information supplied for this set of NAND chips. | |
70 | * @info: Link back to the hardware information. | |
71 | * @scan_res: The result from calling nand_scan_ident(). | |
72 | */ | |
1da177e4 LT |
73 | struct s3c2410_nand_mtd { |
74 | struct mtd_info mtd; | |
75 | struct nand_chip chip; | |
76 | struct s3c2410_nand_set *set; | |
77 | struct s3c2410_nand_info *info; | |
78 | int scan_res; | |
79 | }; | |
80 | ||
2c06a082 BD |
81 | enum s3c_cpu_type { |
82 | TYPE_S3C2410, | |
83 | TYPE_S3C2412, | |
84 | TYPE_S3C2440, | |
85 | }; | |
86 | ||
ac497c16 JP |
87 | enum s3c_nand_clk_state { |
88 | CLOCK_DISABLE = 0, | |
89 | CLOCK_ENABLE, | |
90 | CLOCK_SUSPEND, | |
91 | }; | |
92 | ||
1da177e4 LT |
93 | /* overview of the s3c2410 nand state */ |
94 | ||
3db72151 BD |
95 | /** |
96 | * struct s3c2410_nand_info - NAND controller state. | |
97 | * @mtds: An array of MTD instances on this controoler. | |
98 | * @platform: The platform data for this board. | |
99 | * @device: The platform device we bound to. | |
3db72151 | 100 | * @clk: The clock resource for this controller. |
6f32a3e2 | 101 | * @regs: The area mapped for the hardware registers. |
3db72151 BD |
102 | * @sel_reg: Pointer to the register controlling the NAND selection. |
103 | * @sel_bit: The bit in @sel_reg to select the NAND chip. | |
104 | * @mtd_count: The number of MTDs created from this controller. | |
105 | * @save_sel: The contents of @sel_reg to be saved over suspend. | |
106 | * @clk_rate: The clock rate from @clk. | |
ac497c16 | 107 | * @clk_state: The current clock state. |
3db72151 BD |
108 | * @cpu_type: The exact type of this controller. |
109 | */ | |
1da177e4 LT |
110 | struct s3c2410_nand_info { |
111 | /* mtd info */ | |
112 | struct nand_hw_control controller; | |
113 | struct s3c2410_nand_mtd *mtds; | |
114 | struct s3c2410_platform_nand *platform; | |
115 | ||
116 | /* device info */ | |
117 | struct device *device; | |
1da177e4 | 118 | struct clk *clk; |
fdf2fd52 | 119 | void __iomem *regs; |
2c06a082 BD |
120 | void __iomem *sel_reg; |
121 | int sel_bit; | |
1da177e4 | 122 | int mtd_count; |
09160832 | 123 | unsigned long save_sel; |
30821fee | 124 | unsigned long clk_rate; |
ac497c16 | 125 | enum s3c_nand_clk_state clk_state; |
03680b1e | 126 | |
2c06a082 | 127 | enum s3c_cpu_type cpu_type; |
30821fee BD |
128 | |
129 | #ifdef CONFIG_CPU_FREQ | |
130 | struct notifier_block freq_transition; | |
131 | #endif | |
1da177e4 LT |
132 | }; |
133 | ||
134 | /* conversion functions */ | |
135 | ||
136 | static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd) | |
137 | { | |
138 | return container_of(mtd, struct s3c2410_nand_mtd, mtd); | |
139 | } | |
140 | ||
141 | static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd) | |
142 | { | |
143 | return s3c2410_nand_mtd_toours(mtd)->info; | |
144 | } | |
145 | ||
3ae5eaec | 146 | static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev) |
1da177e4 | 147 | { |
3ae5eaec | 148 | return platform_get_drvdata(dev); |
1da177e4 LT |
149 | } |
150 | ||
3ae5eaec | 151 | static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev) |
1da177e4 | 152 | { |
3ae5eaec | 153 | return dev->dev.platform_data; |
1da177e4 LT |
154 | } |
155 | ||
ac497c16 | 156 | static inline int allow_clk_suspend(struct s3c2410_nand_info *info) |
d1fef3c5 | 157 | { |
a68c5ec8 SK |
158 | #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP |
159 | return 1; | |
160 | #else | |
161 | return 0; | |
162 | #endif | |
d1fef3c5 BD |
163 | } |
164 | ||
ac497c16 JP |
165 | /** |
166 | * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock. | |
167 | * @info: The controller instance. | |
168 | * @new_state: State to which clock should be set. | |
169 | */ | |
170 | static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info, | |
171 | enum s3c_nand_clk_state new_state) | |
172 | { | |
173 | if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND) | |
174 | return; | |
175 | ||
176 | if (info->clk_state == CLOCK_ENABLE) { | |
177 | if (new_state != CLOCK_ENABLE) | |
178 | clk_disable(info->clk); | |
179 | } else { | |
180 | if (new_state == CLOCK_ENABLE) | |
181 | clk_enable(info->clk); | |
182 | } | |
183 | ||
184 | info->clk_state = new_state; | |
185 | } | |
186 | ||
1da177e4 LT |
187 | /* timing calculations */ |
188 | ||
cfd320fb | 189 | #define NS_IN_KHZ 1000000 |
1da177e4 | 190 | |
3db72151 BD |
191 | /** |
192 | * s3c_nand_calc_rate - calculate timing data. | |
193 | * @wanted: The cycle time in nanoseconds. | |
194 | * @clk: The clock rate in kHz. | |
195 | * @max: The maximum divider value. | |
196 | * | |
197 | * Calculate the timing value from the given parameters. | |
198 | */ | |
2c06a082 | 199 | static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max) |
1da177e4 LT |
200 | { |
201 | int result; | |
202 | ||
947391cf | 203 | result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ); |
1da177e4 LT |
204 | |
205 | pr_debug("result %d from %ld, %d\n", result, clk, wanted); | |
206 | ||
207 | if (result > max) { | |
92aeb5d2 SK |
208 | pr_err("%d ns is too big for current clock rate %ld\n", |
209 | wanted, clk); | |
1da177e4 LT |
210 | return -1; |
211 | } | |
212 | ||
213 | if (result < 1) | |
214 | result = 1; | |
215 | ||
216 | return result; | |
217 | } | |
218 | ||
54cd0208 | 219 | #define to_ns(ticks, clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk)) |
1da177e4 LT |
220 | |
221 | /* controller setup */ | |
222 | ||
3db72151 BD |
223 | /** |
224 | * s3c2410_nand_setrate - setup controller timing information. | |
225 | * @info: The controller instance. | |
226 | * | |
227 | * Given the information supplied by the platform, calculate and set | |
228 | * the necessary timing registers in the hardware to generate the | |
229 | * necessary timing cycles to the hardware. | |
230 | */ | |
30821fee | 231 | static int s3c2410_nand_setrate(struct s3c2410_nand_info *info) |
1da177e4 | 232 | { |
30821fee | 233 | struct s3c2410_platform_nand *plat = info->platform; |
2c06a082 | 234 | int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4; |
cfd320fb | 235 | int tacls, twrph0, twrph1; |
30821fee | 236 | unsigned long clkrate = clk_get_rate(info->clk); |
2612e523 | 237 | unsigned long uninitialized_var(set), cfg, uninitialized_var(mask); |
30821fee | 238 | unsigned long flags; |
1da177e4 LT |
239 | |
240 | /* calculate the timing information for the controller */ | |
241 | ||
30821fee | 242 | info->clk_rate = clkrate; |
cfd320fb BD |
243 | clkrate /= 1000; /* turn clock into kHz for ease of use */ |
244 | ||
1da177e4 | 245 | if (plat != NULL) { |
2c06a082 BD |
246 | tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max); |
247 | twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8); | |
248 | twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8); | |
1da177e4 LT |
249 | } else { |
250 | /* default timings */ | |
2c06a082 | 251 | tacls = tacls_max; |
1da177e4 LT |
252 | twrph0 = 8; |
253 | twrph1 = 8; | |
254 | } | |
61b03bd7 | 255 | |
1da177e4 | 256 | if (tacls < 0 || twrph0 < 0 || twrph1 < 0) { |
99974c62 | 257 | dev_err(info->device, "cannot get suitable timings\n"); |
1da177e4 LT |
258 | return -EINVAL; |
259 | } | |
260 | ||
99974c62 | 261 | dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n", |
54cd0208 SK |
262 | tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), |
263 | twrph1, to_ns(twrph1, clkrate)); | |
1da177e4 | 264 | |
30821fee BD |
265 | switch (info->cpu_type) { |
266 | case TYPE_S3C2410: | |
267 | mask = (S3C2410_NFCONF_TACLS(3) | | |
268 | S3C2410_NFCONF_TWRPH0(7) | | |
269 | S3C2410_NFCONF_TWRPH1(7)); | |
270 | set = S3C2410_NFCONF_EN; | |
271 | set |= S3C2410_NFCONF_TACLS(tacls - 1); | |
272 | set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); | |
273 | set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); | |
274 | break; | |
275 | ||
276 | case TYPE_S3C2440: | |
277 | case TYPE_S3C2412: | |
a755a385 PK |
278 | mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) | |
279 | S3C2440_NFCONF_TWRPH0(7) | | |
280 | S3C2440_NFCONF_TWRPH1(7)); | |
30821fee BD |
281 | |
282 | set = S3C2440_NFCONF_TACLS(tacls - 1); | |
283 | set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1); | |
284 | set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1); | |
285 | break; | |
286 | ||
287 | default: | |
30821fee BD |
288 | BUG(); |
289 | } | |
290 | ||
30821fee BD |
291 | local_irq_save(flags); |
292 | ||
293 | cfg = readl(info->regs + S3C2410_NFCONF); | |
294 | cfg &= ~mask; | |
295 | cfg |= set; | |
296 | writel(cfg, info->regs + S3C2410_NFCONF); | |
297 | ||
298 | local_irq_restore(flags); | |
299 | ||
ae7304e5 AG |
300 | dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg); |
301 | ||
30821fee BD |
302 | return 0; |
303 | } | |
304 | ||
3db72151 BD |
305 | /** |
306 | * s3c2410_nand_inithw - basic hardware initialisation | |
307 | * @info: The hardware state. | |
308 | * | |
309 | * Do the basic initialisation of the hardware, using s3c2410_nand_setrate() | |
310 | * to setup the hardware access speeds and set the controller to be enabled. | |
311 | */ | |
30821fee BD |
312 | static int s3c2410_nand_inithw(struct s3c2410_nand_info *info) |
313 | { | |
314 | int ret; | |
315 | ||
316 | ret = s3c2410_nand_setrate(info); | |
317 | if (ret < 0) | |
318 | return ret; | |
319 | ||
54cd0208 SK |
320 | switch (info->cpu_type) { |
321 | case TYPE_S3C2410: | |
30821fee | 322 | default: |
2c06a082 BD |
323 | break; |
324 | ||
54cd0208 SK |
325 | case TYPE_S3C2440: |
326 | case TYPE_S3C2412: | |
d1fef3c5 BD |
327 | /* enable the controller and de-assert nFCE */ |
328 | ||
2c06a082 | 329 | writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT); |
a4f957f1 | 330 | } |
1da177e4 | 331 | |
1da177e4 LT |
332 | return 0; |
333 | } | |
334 | ||
3db72151 BD |
335 | /** |
336 | * s3c2410_nand_select_chip - select the given nand chip | |
337 | * @mtd: The MTD instance for this chip. | |
338 | * @chip: The chip number. | |
339 | * | |
340 | * This is called by the MTD layer to either select a given chip for the | |
341 | * @mtd instance, or to indicate that the access has finished and the | |
342 | * chip can be de-selected. | |
343 | * | |
344 | * The routine ensures that the nFCE line is correctly setup, and any | |
345 | * platform specific selection code is called to route nFCE to the specific | |
346 | * chip. | |
347 | */ | |
1da177e4 LT |
348 | static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip) |
349 | { | |
350 | struct s3c2410_nand_info *info; | |
61b03bd7 | 351 | struct s3c2410_nand_mtd *nmtd; |
1da177e4 LT |
352 | struct nand_chip *this = mtd->priv; |
353 | unsigned long cur; | |
354 | ||
355 | nmtd = this->priv; | |
356 | info = nmtd->info; | |
357 | ||
ac497c16 JP |
358 | if (chip != -1) |
359 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); | |
d1fef3c5 | 360 | |
2c06a082 | 361 | cur = readl(info->sel_reg); |
1da177e4 LT |
362 | |
363 | if (chip == -1) { | |
2c06a082 | 364 | cur |= info->sel_bit; |
1da177e4 | 365 | } else { |
fb8d82a8 | 366 | if (nmtd->set != NULL && chip > nmtd->set->nr_chips) { |
99974c62 | 367 | dev_err(info->device, "invalid chip %d\n", chip); |
1da177e4 LT |
368 | return; |
369 | } | |
370 | ||
371 | if (info->platform != NULL) { | |
372 | if (info->platform->select_chip != NULL) | |
e0c7d767 | 373 | (info->platform->select_chip) (nmtd->set, chip); |
1da177e4 LT |
374 | } |
375 | ||
2c06a082 | 376 | cur &= ~info->sel_bit; |
1da177e4 LT |
377 | } |
378 | ||
2c06a082 | 379 | writel(cur, info->sel_reg); |
d1fef3c5 | 380 | |
ac497c16 JP |
381 | if (chip == -1) |
382 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); | |
1da177e4 LT |
383 | } |
384 | ||
ad3b5fb7 | 385 | /* s3c2410_nand_hwcontrol |
a4f957f1 | 386 | * |
ad3b5fb7 | 387 | * Issue command and address cycles to the chip |
a4f957f1 | 388 | */ |
1da177e4 | 389 | |
7abd3ef9 | 390 | static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
f9068876 | 391 | unsigned int ctrl) |
1da177e4 LT |
392 | { |
393 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
c9ac5977 | 394 | |
7abd3ef9 TG |
395 | if (cmd == NAND_CMD_NONE) |
396 | return; | |
397 | ||
f9068876 | 398 | if (ctrl & NAND_CLE) |
7abd3ef9 TG |
399 | writeb(cmd, info->regs + S3C2410_NFCMD); |
400 | else | |
401 | writeb(cmd, info->regs + S3C2410_NFADDR); | |
a4f957f1 BD |
402 | } |
403 | ||
404 | /* command and control functions */ | |
405 | ||
f9068876 DW |
406 | static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
407 | unsigned int ctrl) | |
a4f957f1 BD |
408 | { |
409 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
1da177e4 | 410 | |
7abd3ef9 TG |
411 | if (cmd == NAND_CMD_NONE) |
412 | return; | |
413 | ||
f9068876 | 414 | if (ctrl & NAND_CLE) |
7abd3ef9 TG |
415 | writeb(cmd, info->regs + S3C2440_NFCMD); |
416 | else | |
417 | writeb(cmd, info->regs + S3C2440_NFADDR); | |
1da177e4 LT |
418 | } |
419 | ||
1da177e4 LT |
420 | /* s3c2410_nand_devready() |
421 | * | |
422 | * returns 0 if the nand is busy, 1 if it is ready | |
423 | */ | |
424 | ||
425 | static int s3c2410_nand_devready(struct mtd_info *mtd) | |
426 | { | |
427 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
1da177e4 LT |
428 | return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY; |
429 | } | |
430 | ||
2c06a082 BD |
431 | static int s3c2440_nand_devready(struct mtd_info *mtd) |
432 | { | |
433 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
434 | return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY; | |
435 | } | |
436 | ||
437 | static int s3c2412_nand_devready(struct mtd_info *mtd) | |
438 | { | |
439 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
440 | return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY; | |
441 | } | |
442 | ||
1da177e4 LT |
443 | /* ECC handling functions */ |
444 | ||
19da4158 | 445 | #ifdef CONFIG_MTD_NAND_S3C2410_HWECC |
2c06a082 BD |
446 | static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, |
447 | u_char *read_ecc, u_char *calc_ecc) | |
1da177e4 | 448 | { |
a2593247 BD |
449 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
450 | unsigned int diff0, diff1, diff2; | |
451 | unsigned int bit, byte; | |
452 | ||
453 | pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc); | |
454 | ||
455 | diff0 = read_ecc[0] ^ calc_ecc[0]; | |
456 | diff1 = read_ecc[1] ^ calc_ecc[1]; | |
457 | diff2 = read_ecc[2] ^ calc_ecc[2]; | |
458 | ||
13e85974 AS |
459 | pr_debug("%s: rd %*phN calc %*phN diff %02x%02x%02x\n", |
460 | __func__, 3, read_ecc, 3, calc_ecc, | |
a2593247 BD |
461 | diff0, diff1, diff2); |
462 | ||
463 | if (diff0 == 0 && diff1 == 0 && diff2 == 0) | |
464 | return 0; /* ECC is ok */ | |
465 | ||
c45c6c68 BD |
466 | /* sometimes people do not think about using the ECC, so check |
467 | * to see if we have an 0xff,0xff,0xff read ECC and then ignore | |
468 | * the error, on the assumption that this is an un-eccd page. | |
469 | */ | |
470 | if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff | |
471 | && info->platform->ignore_unset_ecc) | |
472 | return 0; | |
473 | ||
a2593247 BD |
474 | /* Can we correct this ECC (ie, one row and column change). |
475 | * Note, this is similar to the 256 error code on smartmedia */ | |
476 | ||
477 | if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 && | |
478 | ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 && | |
479 | ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) { | |
480 | /* calculate the bit position of the error */ | |
481 | ||
d0bf3793 MR |
482 | bit = ((diff2 >> 3) & 1) | |
483 | ((diff2 >> 4) & 2) | | |
484 | ((diff2 >> 5) & 4); | |
1da177e4 | 485 | |
a2593247 | 486 | /* calculate the byte position of the error */ |
1da177e4 | 487 | |
d0bf3793 MR |
488 | byte = ((diff2 << 7) & 0x100) | |
489 | ((diff1 << 0) & 0x80) | | |
490 | ((diff1 << 1) & 0x40) | | |
491 | ((diff1 << 2) & 0x20) | | |
492 | ((diff1 << 3) & 0x10) | | |
493 | ((diff0 >> 4) & 0x08) | | |
494 | ((diff0 >> 3) & 0x04) | | |
495 | ((diff0 >> 2) & 0x02) | | |
496 | ((diff0 >> 1) & 0x01); | |
a2593247 BD |
497 | |
498 | dev_dbg(info->device, "correcting error bit %d, byte %d\n", | |
499 | bit, byte); | |
500 | ||
501 | dat[byte] ^= (1 << bit); | |
502 | return 1; | |
503 | } | |
504 | ||
505 | /* if there is only one bit difference in the ECC, then | |
506 | * one of only a row or column parity has changed, which | |
507 | * means the error is most probably in the ECC itself */ | |
508 | ||
509 | diff0 |= (diff1 << 8); | |
510 | diff0 |= (diff2 << 16); | |
511 | ||
512 | if ((diff0 & ~(1<<fls(diff0))) == 0) | |
513 | return 1; | |
514 | ||
4fac9f69 | 515 | return -1; |
1da177e4 LT |
516 | } |
517 | ||
a4f957f1 BD |
518 | /* ECC functions |
519 | * | |
520 | * These allow the s3c2410 and s3c2440 to use the controller's ECC | |
521 | * generator block to ECC the data as it passes through] | |
522 | */ | |
523 | ||
1da177e4 LT |
524 | static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
525 | { | |
526 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
527 | unsigned long ctrl; | |
528 | ||
529 | ctrl = readl(info->regs + S3C2410_NFCONF); | |
530 | ctrl |= S3C2410_NFCONF_INITECC; | |
531 | writel(ctrl, info->regs + S3C2410_NFCONF); | |
532 | } | |
533 | ||
4f659923 MC |
534 | static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
535 | { | |
536 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
537 | unsigned long ctrl; | |
538 | ||
539 | ctrl = readl(info->regs + S3C2440_NFCONT); | |
f938bc56 SK |
540 | writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, |
541 | info->regs + S3C2440_NFCONT); | |
4f659923 MC |
542 | } |
543 | ||
a4f957f1 BD |
544 | static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
545 | { | |
546 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
547 | unsigned long ctrl; | |
548 | ||
549 | ctrl = readl(info->regs + S3C2440_NFCONT); | |
550 | writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT); | |
551 | } | |
552 | ||
f938bc56 SK |
553 | static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
554 | u_char *ecc_code) | |
1da177e4 LT |
555 | { |
556 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
557 | ||
558 | ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0); | |
559 | ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1); | |
560 | ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2); | |
561 | ||
13e85974 | 562 | pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code); |
1da177e4 LT |
563 | |
564 | return 0; | |
565 | } | |
566 | ||
f938bc56 SK |
567 | static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
568 | u_char *ecc_code) | |
4f659923 MC |
569 | { |
570 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
571 | unsigned long ecc = readl(info->regs + S3C2412_NFMECC0); | |
572 | ||
573 | ecc_code[0] = ecc; | |
574 | ecc_code[1] = ecc >> 8; | |
575 | ecc_code[2] = ecc >> 16; | |
576 | ||
13e85974 | 577 | pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code); |
4f659923 MC |
578 | |
579 | return 0; | |
580 | } | |
581 | ||
f938bc56 SK |
582 | static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
583 | u_char *ecc_code) | |
a4f957f1 BD |
584 | { |
585 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
586 | unsigned long ecc = readl(info->regs + S3C2440_NFMECC0); | |
587 | ||
588 | ecc_code[0] = ecc; | |
589 | ecc_code[1] = ecc >> 8; | |
590 | ecc_code[2] = ecc >> 16; | |
591 | ||
71d54f38 | 592 | pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff); |
a4f957f1 BD |
593 | |
594 | return 0; | |
595 | } | |
19da4158 | 596 | #endif |
a4f957f1 | 597 | |
a4f957f1 BD |
598 | /* over-ride the standard functions for a little more speed. We can |
599 | * use read/write block to move the data buffers to/from the controller | |
600 | */ | |
1da177e4 LT |
601 | |
602 | static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
603 | { | |
604 | struct nand_chip *this = mtd->priv; | |
605 | readsb(this->IO_ADDR_R, buf, len); | |
606 | } | |
607 | ||
b773bb2e MR |
608 | static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
609 | { | |
610 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
dea2aa6f BD |
611 | |
612 | readsl(info->regs + S3C2440_NFDATA, buf, len >> 2); | |
613 | ||
614 | /* cleanup if we've got less than a word to do */ | |
615 | if (len & 3) { | |
616 | buf += len & ~3; | |
617 | ||
618 | for (; len & 3; len--) | |
619 | *buf++ = readb(info->regs + S3C2440_NFDATA); | |
620 | } | |
b773bb2e MR |
621 | } |
622 | ||
f938bc56 SK |
623 | static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, |
624 | int len) | |
1da177e4 LT |
625 | { |
626 | struct nand_chip *this = mtd->priv; | |
627 | writesb(this->IO_ADDR_W, buf, len); | |
628 | } | |
629 | ||
f938bc56 SK |
630 | static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, |
631 | int len) | |
b773bb2e MR |
632 | { |
633 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
dea2aa6f BD |
634 | |
635 | writesl(info->regs + S3C2440_NFDATA, buf, len >> 2); | |
636 | ||
637 | /* cleanup any fractional write */ | |
638 | if (len & 3) { | |
639 | buf += len & ~3; | |
640 | ||
641 | for (; len & 3; len--, buf++) | |
642 | writeb(*buf, info->regs + S3C2440_NFDATA); | |
643 | } | |
b773bb2e MR |
644 | } |
645 | ||
30821fee BD |
646 | /* cpufreq driver support */ |
647 | ||
648 | #ifdef CONFIG_CPU_FREQ | |
649 | ||
650 | static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb, | |
651 | unsigned long val, void *data) | |
652 | { | |
653 | struct s3c2410_nand_info *info; | |
654 | unsigned long newclk; | |
655 | ||
656 | info = container_of(nb, struct s3c2410_nand_info, freq_transition); | |
657 | newclk = clk_get_rate(info->clk); | |
658 | ||
659 | if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) || | |
660 | (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) { | |
661 | s3c2410_nand_setrate(info); | |
662 | } | |
663 | ||
664 | return 0; | |
665 | } | |
666 | ||
667 | static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) | |
668 | { | |
669 | info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition; | |
670 | ||
671 | return cpufreq_register_notifier(&info->freq_transition, | |
672 | CPUFREQ_TRANSITION_NOTIFIER); | |
673 | } | |
674 | ||
f938bc56 SK |
675 | static inline void |
676 | s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) | |
30821fee BD |
677 | { |
678 | cpufreq_unregister_notifier(&info->freq_transition, | |
679 | CPUFREQ_TRANSITION_NOTIFIER); | |
680 | } | |
681 | ||
682 | #else | |
683 | static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) | |
684 | { | |
685 | return 0; | |
686 | } | |
687 | ||
f938bc56 SK |
688 | static inline void |
689 | s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) | |
30821fee BD |
690 | { |
691 | } | |
692 | #endif | |
693 | ||
1da177e4 LT |
694 | /* device management functions */ |
695 | ||
ec0482e6 | 696 | static int s3c24xx_nand_remove(struct platform_device *pdev) |
1da177e4 | 697 | { |
3ae5eaec | 698 | struct s3c2410_nand_info *info = to_nand_info(pdev); |
1da177e4 | 699 | |
3ae5eaec | 700 | platform_set_drvdata(pdev, NULL); |
1da177e4 | 701 | |
61b03bd7 | 702 | if (info == NULL) |
1da177e4 LT |
703 | return 0; |
704 | ||
30821fee BD |
705 | s3c2410_nand_cpufreq_deregister(info); |
706 | ||
707 | /* Release all our mtds and their partitions, then go through | |
708 | * freeing the resources used | |
1da177e4 | 709 | */ |
61b03bd7 | 710 | |
1da177e4 LT |
711 | if (info->mtds != NULL) { |
712 | struct s3c2410_nand_mtd *ptr = info->mtds; | |
713 | int mtdno; | |
714 | ||
715 | for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) { | |
716 | pr_debug("releasing mtd %d (%p)\n", mtdno, ptr); | |
717 | nand_release(&ptr->mtd); | |
718 | } | |
1da177e4 LT |
719 | } |
720 | ||
721 | /* free the common resources */ | |
722 | ||
6f32a3e2 | 723 | if (!IS_ERR(info->clk)) |
ac497c16 | 724 | s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); |
1da177e4 LT |
725 | |
726 | return 0; | |
727 | } | |
728 | ||
1da177e4 LT |
729 | static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, |
730 | struct s3c2410_nand_mtd *mtd, | |
731 | struct s3c2410_nand_set *set) | |
732 | { | |
599501a7 DES |
733 | if (set) |
734 | mtd->mtd.name = set->name; | |
ed27f028 | 735 | |
42d7fbe2 AB |
736 | return mtd_device_parse_register(&mtd->mtd, NULL, NULL, |
737 | set->partitions, set->nr_partitions); | |
1da177e4 | 738 | } |
1da177e4 | 739 | |
3db72151 BD |
740 | /** |
741 | * s3c2410_nand_init_chip - initialise a single instance of an chip | |
742 | * @info: The base NAND controller the chip is on. | |
743 | * @nmtd: The new controller MTD instance to fill in. | |
744 | * @set: The information passed from the board specific platform data. | |
1da177e4 | 745 | * |
3db72151 BD |
746 | * Initialise the given @nmtd from the information in @info and @set. This |
747 | * readies the structure for use with the MTD layer functions by ensuring | |
748 | * all pointers are setup and the necessary control routines selected. | |
749 | */ | |
1da177e4 LT |
750 | static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, |
751 | struct s3c2410_nand_mtd *nmtd, | |
752 | struct s3c2410_nand_set *set) | |
753 | { | |
754 | struct nand_chip *chip = &nmtd->chip; | |
2c06a082 | 755 | void __iomem *regs = info->regs; |
1da177e4 | 756 | |
1da177e4 LT |
757 | chip->write_buf = s3c2410_nand_write_buf; |
758 | chip->read_buf = s3c2410_nand_read_buf; | |
759 | chip->select_chip = s3c2410_nand_select_chip; | |
760 | chip->chip_delay = 50; | |
761 | chip->priv = nmtd; | |
74218fed | 762 | chip->options = set->options; |
1da177e4 LT |
763 | chip->controller = &info->controller; |
764 | ||
2c06a082 BD |
765 | switch (info->cpu_type) { |
766 | case TYPE_S3C2410: | |
767 | chip->IO_ADDR_W = regs + S3C2410_NFDATA; | |
768 | info->sel_reg = regs + S3C2410_NFCONF; | |
769 | info->sel_bit = S3C2410_NFCONF_nFCE; | |
770 | chip->cmd_ctrl = s3c2410_nand_hwcontrol; | |
771 | chip->dev_ready = s3c2410_nand_devready; | |
772 | break; | |
773 | ||
774 | case TYPE_S3C2440: | |
775 | chip->IO_ADDR_W = regs + S3C2440_NFDATA; | |
776 | info->sel_reg = regs + S3C2440_NFCONT; | |
777 | info->sel_bit = S3C2440_NFCONT_nFCE; | |
778 | chip->cmd_ctrl = s3c2440_nand_hwcontrol; | |
779 | chip->dev_ready = s3c2440_nand_devready; | |
b773bb2e MR |
780 | chip->read_buf = s3c2440_nand_read_buf; |
781 | chip->write_buf = s3c2440_nand_write_buf; | |
2c06a082 BD |
782 | break; |
783 | ||
784 | case TYPE_S3C2412: | |
785 | chip->IO_ADDR_W = regs + S3C2440_NFDATA; | |
786 | info->sel_reg = regs + S3C2440_NFCONT; | |
787 | info->sel_bit = S3C2412_NFCONT_nFCE0; | |
788 | chip->cmd_ctrl = s3c2440_nand_hwcontrol; | |
789 | chip->dev_ready = s3c2412_nand_devready; | |
790 | ||
791 | if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT) | |
792 | dev_info(info->device, "System booted from NAND\n"); | |
793 | ||
794 | break; | |
54cd0208 | 795 | } |
2c06a082 BD |
796 | |
797 | chip->IO_ADDR_R = chip->IO_ADDR_W; | |
a4f957f1 | 798 | |
1da177e4 LT |
799 | nmtd->info = info; |
800 | nmtd->mtd.priv = chip; | |
552d9205 | 801 | nmtd->mtd.owner = THIS_MODULE; |
1da177e4 LT |
802 | nmtd->set = set; |
803 | ||
a68c5ec8 SK |
804 | #ifdef CONFIG_MTD_NAND_S3C2410_HWECC |
805 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; | |
806 | chip->ecc.correct = s3c2410_nand_correct_data; | |
807 | chip->ecc.mode = NAND_ECC_HW; | |
808 | chip->ecc.strength = 1; | |
809 | ||
810 | switch (info->cpu_type) { | |
811 | case TYPE_S3C2410: | |
812 | chip->ecc.hwctl = s3c2410_nand_enable_hwecc; | |
6dfc6d25 | 813 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; |
a68c5ec8 | 814 | break; |
2c06a082 | 815 | |
a68c5ec8 SK |
816 | case TYPE_S3C2412: |
817 | chip->ecc.hwctl = s3c2412_nand_enable_hwecc; | |
818 | chip->ecc.calculate = s3c2412_nand_calculate_ecc; | |
819 | break; | |
820 | ||
821 | case TYPE_S3C2440: | |
822 | chip->ecc.hwctl = s3c2440_nand_enable_hwecc; | |
823 | chip->ecc.calculate = s3c2440_nand_calculate_ecc; | |
824 | break; | |
1da177e4 | 825 | } |
a68c5ec8 SK |
826 | #else |
827 | chip->ecc.mode = NAND_ECC_SOFT; | |
828 | #endif | |
1c21ab67 BD |
829 | |
830 | if (set->ecc_layout != NULL) | |
831 | chip->ecc.layout = set->ecc_layout; | |
37e5ffa3 BD |
832 | |
833 | if (set->disable_ecc) | |
834 | chip->ecc.mode = NAND_ECC_NONE; | |
8c3e843d AG |
835 | |
836 | switch (chip->ecc.mode) { | |
837 | case NAND_ECC_NONE: | |
838 | dev_info(info->device, "NAND ECC disabled\n"); | |
839 | break; | |
840 | case NAND_ECC_SOFT: | |
841 | dev_info(info->device, "NAND soft ECC\n"); | |
842 | break; | |
843 | case NAND_ECC_HW: | |
844 | dev_info(info->device, "NAND hardware ECC\n"); | |
845 | break; | |
846 | default: | |
847 | dev_info(info->device, "NAND ECC UNKNOWN\n"); | |
848 | break; | |
849 | } | |
9db41f9e MP |
850 | |
851 | /* If you use u-boot BBT creation code, specifying this flag will | |
852 | * let the kernel fish out the BBT from the NAND, and also skip the | |
853 | * full NAND scan that can take 1/2s or so. Little things... */ | |
a40f7341 | 854 | if (set->flash_bbt) { |
bb9ebd4e | 855 | chip->bbt_options |= NAND_BBT_USE_FLASH; |
a40f7341 BN |
856 | chip->options |= NAND_SKIP_BBTSCAN; |
857 | } | |
1da177e4 LT |
858 | } |
859 | ||
3db72151 BD |
860 | /** |
861 | * s3c2410_nand_update_chip - post probe update | |
862 | * @info: The controller instance. | |
863 | * @nmtd: The driver version of the MTD instance. | |
71d54f38 | 864 | * |
af901ca1 | 865 | * This routine is called after the chip probe has successfully completed |
3db72151 BD |
866 | * and the relevant per-chip information updated. This call ensure that |
867 | * we update the internal state accordingly. | |
868 | * | |
869 | * The internal state is currently limited to the ECC state information. | |
870 | */ | |
71d54f38 BD |
871 | static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info, |
872 | struct s3c2410_nand_mtd *nmtd) | |
873 | { | |
874 | struct nand_chip *chip = &nmtd->chip; | |
875 | ||
451d3399 BD |
876 | dev_dbg(info->device, "chip %p => page shift %d\n", |
877 | chip, chip->page_shift); | |
71d54f38 | 878 | |
8c3e843d AG |
879 | if (chip->ecc.mode != NAND_ECC_HW) |
880 | return; | |
881 | ||
71d54f38 BD |
882 | /* change the behaviour depending on wether we are using |
883 | * the large or small page nand device */ | |
884 | ||
8c3e843d AG |
885 | if (chip->page_shift > 10) { |
886 | chip->ecc.size = 256; | |
887 | chip->ecc.bytes = 3; | |
888 | } else { | |
889 | chip->ecc.size = 512; | |
890 | chip->ecc.bytes = 3; | |
891 | chip->ecc.layout = &nand_hw_eccoob; | |
71d54f38 BD |
892 | } |
893 | } | |
894 | ||
ec0482e6 | 895 | /* s3c24xx_nand_probe |
1da177e4 LT |
896 | * |
897 | * called by device layer when it finds a device matching | |
898 | * one our driver can handled. This code checks to see if | |
899 | * it can allocate all necessary resources then calls the | |
900 | * nand layer to look for devices | |
901 | */ | |
ec0482e6 | 902 | static int s3c24xx_nand_probe(struct platform_device *pdev) |
1da177e4 | 903 | { |
3ae5eaec | 904 | struct s3c2410_platform_nand *plat = to_nand_plat(pdev); |
54cd0208 | 905 | enum s3c_cpu_type cpu_type; |
1da177e4 LT |
906 | struct s3c2410_nand_info *info; |
907 | struct s3c2410_nand_mtd *nmtd; | |
908 | struct s3c2410_nand_set *sets; | |
909 | struct resource *res; | |
910 | int err = 0; | |
911 | int size; | |
912 | int nr_sets; | |
913 | int setno; | |
914 | ||
ec0482e6 BD |
915 | cpu_type = platform_get_device_id(pdev)->driver_data; |
916 | ||
3ae5eaec | 917 | pr_debug("s3c2410_nand_probe(%p)\n", pdev); |
1da177e4 | 918 | |
6f32a3e2 | 919 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); |
1da177e4 | 920 | if (info == NULL) { |
3ae5eaec | 921 | dev_err(&pdev->dev, "no memory for flash info\n"); |
1da177e4 LT |
922 | err = -ENOMEM; |
923 | goto exit_error; | |
924 | } | |
925 | ||
3ae5eaec | 926 | platform_set_drvdata(pdev, info); |
1da177e4 LT |
927 | |
928 | spin_lock_init(&info->controller.lock); | |
a4f957f1 | 929 | init_waitqueue_head(&info->controller.wq); |
1da177e4 LT |
930 | |
931 | /* get the clock source and enable it */ | |
932 | ||
6f32a3e2 | 933 | info->clk = devm_clk_get(&pdev->dev, "nand"); |
1da177e4 | 934 | if (IS_ERR(info->clk)) { |
898eb71c | 935 | dev_err(&pdev->dev, "failed to get clock\n"); |
1da177e4 LT |
936 | err = -ENOENT; |
937 | goto exit_error; | |
938 | } | |
939 | ||
ac497c16 | 940 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); |
1da177e4 LT |
941 | |
942 | /* allocate and map the resource */ | |
943 | ||
a4f957f1 | 944 | /* currently we assume we have the one resource */ |
6f32a3e2 | 945 | res = pdev->resource; |
fc161c4e | 946 | size = resource_size(res); |
1da177e4 | 947 | |
6f32a3e2 SK |
948 | info->device = &pdev->dev; |
949 | info->platform = plat; | |
950 | info->cpu_type = cpu_type; | |
1da177e4 | 951 | |
6f32a3e2 | 952 | info->regs = devm_request_and_ioremap(&pdev->dev, res); |
1da177e4 | 953 | if (info->regs == NULL) { |
3ae5eaec | 954 | dev_err(&pdev->dev, "cannot reserve register region\n"); |
1da177e4 LT |
955 | err = -EIO; |
956 | goto exit_error; | |
61b03bd7 | 957 | } |
1da177e4 | 958 | |
3ae5eaec | 959 | dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs); |
1da177e4 LT |
960 | |
961 | /* initialise the hardware */ | |
962 | ||
30821fee | 963 | err = s3c2410_nand_inithw(info); |
1da177e4 LT |
964 | if (err != 0) |
965 | goto exit_error; | |
966 | ||
967 | sets = (plat != NULL) ? plat->sets : NULL; | |
968 | nr_sets = (plat != NULL) ? plat->nr_sets : 1; | |
969 | ||
970 | info->mtd_count = nr_sets; | |
971 | ||
972 | /* allocate our information */ | |
973 | ||
974 | size = nr_sets * sizeof(*info->mtds); | |
6f32a3e2 | 975 | info->mtds = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); |
1da177e4 | 976 | if (info->mtds == NULL) { |
3ae5eaec | 977 | dev_err(&pdev->dev, "failed to allocate mtd storage\n"); |
1da177e4 LT |
978 | err = -ENOMEM; |
979 | goto exit_error; | |
980 | } | |
981 | ||
1da177e4 LT |
982 | /* initialise all possible chips */ |
983 | ||
984 | nmtd = info->mtds; | |
985 | ||
986 | for (setno = 0; setno < nr_sets; setno++, nmtd++) { | |
f938bc56 SK |
987 | pr_debug("initialising set %d (%p, info %p)\n", |
988 | setno, nmtd, info); | |
61b03bd7 | 989 | |
1da177e4 LT |
990 | s3c2410_nand_init_chip(info, nmtd, sets); |
991 | ||
71d54f38 | 992 | nmtd->scan_res = nand_scan_ident(&nmtd->mtd, |
5e81e88a DW |
993 | (sets) ? sets->nr_chips : 1, |
994 | NULL); | |
1da177e4 LT |
995 | |
996 | if (nmtd->scan_res == 0) { | |
71d54f38 BD |
997 | s3c2410_nand_update_chip(info, nmtd); |
998 | nand_scan_tail(&nmtd->mtd); | |
1da177e4 LT |
999 | s3c2410_nand_add_partition(info, nmtd, sets); |
1000 | } | |
1001 | ||
1002 | if (sets != NULL) | |
1003 | sets++; | |
1004 | } | |
61b03bd7 | 1005 | |
30821fee BD |
1006 | err = s3c2410_nand_cpufreq_register(info); |
1007 | if (err < 0) { | |
1008 | dev_err(&pdev->dev, "failed to init cpufreq support\n"); | |
1009 | goto exit_error; | |
1010 | } | |
1011 | ||
ac497c16 | 1012 | if (allow_clk_suspend(info)) { |
d1fef3c5 | 1013 | dev_info(&pdev->dev, "clock idle support enabled\n"); |
ac497c16 | 1014 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); |
d1fef3c5 BD |
1015 | } |
1016 | ||
1da177e4 LT |
1017 | pr_debug("initialised ok\n"); |
1018 | return 0; | |
1019 | ||
1020 | exit_error: | |
ec0482e6 | 1021 | s3c24xx_nand_remove(pdev); |
1da177e4 LT |
1022 | |
1023 | if (err == 0) | |
1024 | err = -EINVAL; | |
1025 | return err; | |
1026 | } | |
1027 | ||
d1fef3c5 BD |
1028 | /* PM Support */ |
1029 | #ifdef CONFIG_PM | |
1030 | ||
1031 | static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm) | |
1032 | { | |
1033 | struct s3c2410_nand_info *info = platform_get_drvdata(dev); | |
1034 | ||
1035 | if (info) { | |
09160832 | 1036 | info->save_sel = readl(info->sel_reg); |
03680b1e BD |
1037 | |
1038 | /* For the moment, we must ensure nFCE is high during | |
1039 | * the time we are suspended. This really should be | |
1040 | * handled by suspending the MTDs we are using, but | |
1041 | * that is currently not the case. */ | |
1042 | ||
09160832 | 1043 | writel(info->save_sel | info->sel_bit, info->sel_reg); |
03680b1e | 1044 | |
ac497c16 | 1045 | s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); |
d1fef3c5 BD |
1046 | } |
1047 | ||
1048 | return 0; | |
1049 | } | |
1050 | ||
1051 | static int s3c24xx_nand_resume(struct platform_device *dev) | |
1052 | { | |
1053 | struct s3c2410_nand_info *info = platform_get_drvdata(dev); | |
09160832 | 1054 | unsigned long sel; |
d1fef3c5 BD |
1055 | |
1056 | if (info) { | |
ac497c16 | 1057 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); |
30821fee | 1058 | s3c2410_nand_inithw(info); |
d1fef3c5 | 1059 | |
03680b1e BD |
1060 | /* Restore the state of the nFCE line. */ |
1061 | ||
09160832 BD |
1062 | sel = readl(info->sel_reg); |
1063 | sel &= ~info->sel_bit; | |
1064 | sel |= info->save_sel & info->sel_bit; | |
1065 | writel(sel, info->sel_reg); | |
03680b1e | 1066 | |
ac497c16 | 1067 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); |
d1fef3c5 BD |
1068 | } |
1069 | ||
1070 | return 0; | |
1071 | } | |
1072 | ||
1073 | #else | |
1074 | #define s3c24xx_nand_suspend NULL | |
1075 | #define s3c24xx_nand_resume NULL | |
1076 | #endif | |
1077 | ||
a4f957f1 BD |
1078 | /* driver device registration */ |
1079 | ||
ec0482e6 BD |
1080 | static struct platform_device_id s3c24xx_driver_ids[] = { |
1081 | { | |
1082 | .name = "s3c2410-nand", | |
1083 | .driver_data = TYPE_S3C2410, | |
1084 | }, { | |
1085 | .name = "s3c2440-nand", | |
1086 | .driver_data = TYPE_S3C2440, | |
1087 | }, { | |
1088 | .name = "s3c2412-nand", | |
1089 | .driver_data = TYPE_S3C2412, | |
9dbc0902 PK |
1090 | }, { |
1091 | .name = "s3c6400-nand", | |
1092 | .driver_data = TYPE_S3C2412, /* compatible with 2412 */ | |
3ae5eaec | 1093 | }, |
ec0482e6 | 1094 | { } |
1da177e4 LT |
1095 | }; |
1096 | ||
ec0482e6 | 1097 | MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); |
a4f957f1 | 1098 | |
ec0482e6 BD |
1099 | static struct platform_driver s3c24xx_nand_driver = { |
1100 | .probe = s3c24xx_nand_probe, | |
1101 | .remove = s3c24xx_nand_remove, | |
2c06a082 BD |
1102 | .suspend = s3c24xx_nand_suspend, |
1103 | .resume = s3c24xx_nand_resume, | |
ec0482e6 | 1104 | .id_table = s3c24xx_driver_ids, |
2c06a082 | 1105 | .driver = { |
ec0482e6 | 1106 | .name = "s3c24xx-nand", |
2c06a082 BD |
1107 | .owner = THIS_MODULE, |
1108 | }, | |
1109 | }; | |
1110 | ||
056fcab5 | 1111 | module_platform_driver(s3c24xx_nand_driver); |
1da177e4 LT |
1112 | |
1113 | MODULE_LICENSE("GPL"); | |
1114 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
a4f957f1 | 1115 | MODULE_DESCRIPTION("S3C24XX MTD NAND driver"); |