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mtd: trivial sh_flctl changes
[deliverable/linux.git] / drivers / mtd / nand / sh_flctl.c
CommitLineData
6028aa01
YS		 1/*
2 * SuperH FLCTL nand controller
3 *
b79c7adf
MD		 4 * Copyright (c) 2008 Renesas Solutions Corp.
5 * Copyright (c) 2008 Atom Create Engineering Co., Ltd.
6028aa01 6 *
b79c7adf 7 * Based on fsl_elbc_nand.c, Copyright (c) 2006-2007 Freescale Semiconductor
6028aa01
YS		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28#include <linux/platform_device.h>
29
30#include <linux/mtd/mtd.h>
31#include <linux/mtd/nand.h>
32#include <linux/mtd/partitions.h>
33#include <linux/mtd/sh_flctl.h>
34
35static struct nand_ecclayout flctl_4secc_oob_16 = {
36 .eccbytes = 10,
37 .eccpos = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
38 .oobfree = {
39 {.offset = 12,
40 . length = 4} },
41};
42
43static struct nand_ecclayout flctl_4secc_oob_64 = {
44 .eccbytes = 10,
45 .eccpos = {48, 49, 50, 51, 52, 53, 54, 55, 56, 57},
46 .oobfree = {
47 {.offset = 60,
48 . length = 4} },
49};
50
51static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
52
53static struct nand_bbt_descr flctl_4secc_smallpage = {
54 .options = NAND_BBT_SCAN2NDPAGE,
55 .offs = 11,
56 .len = 1,
57 .pattern = scan_ff_pattern,
58};
59
60static struct nand_bbt_descr flctl_4secc_largepage = {
c0e6616a 61 .options = NAND_BBT_SCAN2NDPAGE,
6028aa01
YS		 62 .offs = 58,
63 .len = 2,
64 .pattern = scan_ff_pattern,
65};
66
67static void empty_fifo(struct sh_flctl *flctl)
68{
69 writel(0x000c0000, FLINTDMACR(flctl)); /* FIFO Clear */
70 writel(0x00000000, FLINTDMACR(flctl)); /* Clear Error flags */
71}
72
73static void start_translation(struct sh_flctl *flctl)
74{
75 writeb(TRSTRT, FLTRCR(flctl));
76}
77
b79c7adf
MD		 78static void timeout_error(struct sh_flctl *flctl, const char *str)
79{
80 dev_err(&flctl->pdev->dev, "Timeout occured in %s\n", str);
81}
82
6028aa01
YS		 83static void wait_completion(struct sh_flctl *flctl)
84{
85 uint32_t timeout = LOOP_TIMEOUT_MAX;
86
87 while (timeout--) {
88 if (readb(FLTRCR(flctl)) & TREND) {
89 writeb(0x0, FLTRCR(flctl));
90 return;
91 }
92 udelay(1);
93 }
94
b79c7adf 95 timeout_error(flctl, __func__);
6028aa01
YS		 96 writeb(0x0, FLTRCR(flctl));
97}
98
99static void set_addr(struct mtd_info *mtd, int column, int page_addr)
100{
101 struct sh_flctl *flctl = mtd_to_flctl(mtd);
102 uint32_t addr = 0;
103
104 if (column == -1) {
105 addr = page_addr; /* ERASE1 */
106 } else if (page_addr != -1) {
107 /* SEQIN, READ0, etc.. */
108 if (flctl->page_size) {
109 addr = column & 0x0FFF;
110 addr |= (page_addr & 0xff) << 16;
111 addr |= ((page_addr >> 8) & 0xff) << 24;
112 /* big than 128MB */
113 if (flctl->rw_ADRCNT == ADRCNT2_E) {
114 uint32_t addr2;
115 addr2 = (page_addr >> 16) & 0xff;
116 writel(addr2, FLADR2(flctl));
117 }
118 } else {
119 addr = column;
120 addr |= (page_addr & 0xff) << 8;
121 addr |= ((page_addr >> 8) & 0xff) << 16;
122 addr |= ((page_addr >> 16) & 0xff) << 24;
123 }
124 }
125 writel(addr, FLADR(flctl));
126}
127
128static void wait_rfifo_ready(struct sh_flctl *flctl)
129{
130 uint32_t timeout = LOOP_TIMEOUT_MAX;
131
132 while (timeout--) {
133 uint32_t val;
134 /* check FIFO */
135 val = readl(FLDTCNTR(flctl)) >> 16;
136 if (val & 0xFF)
137 return;
138 udelay(1);
139 }
b79c7adf 140 timeout_error(flctl, __func__);
6028aa01
YS		 141}
142
143static void wait_wfifo_ready(struct sh_flctl *flctl)
144{
145 uint32_t len, timeout = LOOP_TIMEOUT_MAX;
146
147 while (timeout--) {
148 /* check FIFO */
149 len = (readl(FLDTCNTR(flctl)) >> 16) & 0xFF;
150 if (len >= 4)
151 return;
152 udelay(1);
153 }
b79c7adf 154 timeout_error(flctl, __func__);
6028aa01
YS		 155}
156
c0e6616a 157static int wait_recfifo_ready(struct sh_flctl *flctl, int sector_number)
6028aa01
YS		 158{
159 uint32_t timeout = LOOP_TIMEOUT_MAX;
160 int checked[4];
161 void __iomem *ecc_reg[4];
162 int i;
163 uint32_t data, size;
164
165 memset(checked, 0, sizeof(checked));
166
167 while (timeout--) {
168 size = readl(FLDTCNTR(flctl)) >> 24;
169 if (size & 0xFF)
170 return 0; /* success */
171
172 if (readl(FL4ECCCR(flctl)) & _4ECCFA)
173 return 1; /* can't correct */
174
175 udelay(1);
176 if (!(readl(FL4ECCCR(flctl)) & _4ECCEND))
177 continue;
178
179 /* start error correction */
180 ecc_reg[0] = FL4ECCRESULT0(flctl);
181 ecc_reg[1] = FL4ECCRESULT1(flctl);
182 ecc_reg[2] = FL4ECCRESULT2(flctl);
183 ecc_reg[3] = FL4ECCRESULT3(flctl);
184
185 for (i = 0; i < 3; i++) {
186 data = readl(ecc_reg[i]);
187 if (data != INIT_FL4ECCRESULT_VAL && !checked[i]) {
188 uint8_t org;
189 int index;
190
c0e6616a
YS		 191 if (flctl->page_size)
192 index = (512 * sector_number) +
193 (data >> 16);
194 else
195 index = data >> 16;
196
6028aa01
YS		 197 org = flctl->done_buff[index];
198 flctl->done_buff[index] = org ^ (data & 0xFF);
199 checked[i] = 1;
200 }
201 }
202
203 writel(0, FL4ECCCR(flctl));
204 }
205
b79c7adf 206 timeout_error(flctl, __func__);
6028aa01
YS		 207 return 1; /* timeout */
208}
209
210static void wait_wecfifo_ready(struct sh_flctl *flctl)
211{
212 uint32_t timeout = LOOP_TIMEOUT_MAX;
213 uint32_t len;
214
215 while (timeout--) {
216 /* check FLECFIFO */
217 len = (readl(FLDTCNTR(flctl)) >> 24) & 0xFF;
218 if (len >= 4)
219 return;
220 udelay(1);
221 }
b79c7adf 222 timeout_error(flctl, __func__);
6028aa01
YS		 223}
224
225static void read_datareg(struct sh_flctl *flctl, int offset)
226{
227 unsigned long data;
228 unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
229
230 wait_completion(flctl);
231
232 data = readl(FLDATAR(flctl));
233 *buf = le32_to_cpu(data);
234}
235
236static void read_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
237{
238 int i, len_4align;
239 unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
240 void *fifo_addr = (void *)FLDTFIFO(flctl);
241
242 len_4align = (rlen + 3) / 4;
243
244 for (i = 0; i < len_4align; i++) {
245 wait_rfifo_ready(flctl);
246 buf[i] = readl(fifo_addr);
247 buf[i] = be32_to_cpu(buf[i]);
248 }
249}
250
c0e6616a 251static int read_ecfiforeg(struct sh_flctl *flctl, uint8_t *buff, int sector)
6028aa01
YS		 252{
253 int i;
254 unsigned long *ecc_buf = (unsigned long *)buff;
255 void *fifo_addr = (void *)FLECFIFO(flctl);
256
257 for (i = 0; i < 4; i++) {
c0e6616a 258 if (wait_recfifo_ready(flctl , sector))
6028aa01
YS		 259 return 1;
260 ecc_buf[i] = readl(fifo_addr);
261 ecc_buf[i] = be32_to_cpu(ecc_buf[i]);
262 }
263
264 return 0;
265}
266
267static void write_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
268{
269 int i, len_4align;
270 unsigned long *data = (unsigned long *)&flctl->done_buff[offset];
271 void *fifo_addr = (void *)FLDTFIFO(flctl);
272
273 len_4align = (rlen + 3) / 4;
274 for (i = 0; i < len_4align; i++) {
275 wait_wfifo_ready(flctl);
276 writel(cpu_to_be32(data[i]), fifo_addr);
277 }
278}
279
280static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_val)
281{
282 struct sh_flctl *flctl = mtd_to_flctl(mtd);
283 uint32_t flcmncr_val = readl(FLCMNCR(flctl));
284 uint32_t flcmdcr_val, addr_len_bytes = 0;
285
286 /* Set SNAND bit if page size is 2048byte */
287 if (flctl->page_size)
288 flcmncr_val |= SNAND_E;
289 else
290 flcmncr_val &= ~SNAND_E;
291
292 /* default FLCMDCR val */
293 flcmdcr_val = DOCMD1_E | DOADR_E;
294
295 /* Set for FLCMDCR */
296 switch (cmd) {
297 case NAND_CMD_ERASE1:
298 addr_len_bytes = flctl->erase_ADRCNT;
299 flcmdcr_val |= DOCMD2_E;
300 break;
301 case NAND_CMD_READ0:
302 case NAND_CMD_READOOB:
303 addr_len_bytes = flctl->rw_ADRCNT;
304 flcmdcr_val |= CDSRC_E;
305 break;
306 case NAND_CMD_SEQIN:
307 /* This case is that cmd is READ0 or READ1 or READ00 */
308 flcmdcr_val &= ~DOADR_E; /* ONLY execute 1st cmd */
309 break;
310 case NAND_CMD_PAGEPROG:
311 addr_len_bytes = flctl->rw_ADRCNT;
35a34799
YS		 312 flcmdcr_val |= DOCMD2_E | CDSRC_E | SELRW;
313 break;
314 case NAND_CMD_READID:
315 flcmncr_val &= ~SNAND_E;
316 addr_len_bytes = ADRCNT_1;
317 break;
318 case NAND_CMD_STATUS:
319 case NAND_CMD_RESET:
320 flcmncr_val &= ~SNAND_E;
321 flcmdcr_val &= ~(DOADR_E | DOSR_E);
322 break;
323 default:
324 break;
325 }
326
327 /* Set address bytes parameter */
328 flcmdcr_val |= addr_len_bytes;
329
330 /* Now actually write */
331 writel(flcmncr_val, FLCMNCR(flctl));
332 writel(flcmdcr_val, FLCMDCR(flctl));
333 writel(flcmcdr_val, FLCMCDR(flctl));
334}
335
336static int flctl_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 337 uint8_t *buf, int page)
35a34799
YS		 338{
339 int i, eccsize = chip->ecc.size;
340 int eccbytes = chip->ecc.bytes;
341 int eccsteps = chip->ecc.steps;
342 uint8_t *p = buf;
343 struct sh_flctl *flctl = mtd_to_flctl(mtd);
344
345 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
346 chip->read_buf(mtd, p, eccsize);
347
348 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
349 if (flctl->hwecc_cant_correct[i])
350 mtd->ecc_stats.failed++;
351 else
352 mtd->ecc_stats.corrected += 0;
353 }
354
355 return 0;
356}
357
358static void flctl_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
359 const uint8_t *buf)
360{
361 int i, eccsize = chip->ecc.size;
362 int eccbytes = chip->ecc.bytes;
363 int eccsteps = chip->ecc.steps;
364 const uint8_t *p = buf;
365
366 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
367 chip->write_buf(mtd, p, eccsize);
368}
369
370static void execmd_read_page_sector(struct mtd_info *mtd, int page_addr)
371{
372 struct sh_flctl *flctl = mtd_to_flctl(mtd);
373 int sector, page_sectors;
374
375 if (flctl->page_size)
376 page_sectors = 4;
377 else
378 page_sectors = 1;
379
380 writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE | _4ECCCORRECT,
381 FLCMNCR(flctl));
382
383 set_cmd_regs(mtd, NAND_CMD_READ0,
384 (NAND_CMD_READSTART << 8) | NAND_CMD_READ0);
385
386 for (sector = 0; sector < page_sectors; sector++) {
387 int ret;
388
389 empty_fifo(flctl);
390 writel(readl(FLCMDCR(flctl)) | 1, FLCMDCR(flctl));
391 writel(page_addr << 2 | sector, FLADR(flctl));
392
393 start_translation(flctl);
394 read_fiforeg(flctl, 512, 512 * sector);
395
396 ret = read_ecfiforeg(flctl,
c0e6616a
YS		 397 &flctl->done_buff[mtd->writesize + 16 * sector],
398 sector);
35a34799
YS		 399
400 if (ret)
401 flctl->hwecc_cant_correct[sector] = 1;
402
403 writel(0x0, FL4ECCCR(flctl));
404 wait_completion(flctl);
405 }
406 writel(readl(FLCMNCR(flctl)) & ~(ACM_SACCES_MODE | _4ECCCORRECT),
407 FLCMNCR(flctl));
408}
409
410static void execmd_read_oob(struct mtd_info *mtd, int page_addr)
411{
412 struct sh_flctl *flctl = mtd_to_flctl(mtd);
413
414 set_cmd_regs(mtd, NAND_CMD_READ0,
415 (NAND_CMD_READSTART << 8) | NAND_CMD_READ0);
416
417 empty_fifo(flctl);
418 if (flctl->page_size) {
419 int i;
420 /* In case that the page size is 2k */
421 for (i = 0; i < 16 * 3; i++)
422 flctl->done_buff[i] = 0xFF;
423
424 set_addr(mtd, 3 * 528 + 512, page_addr);
425 writel(16, FLDTCNTR(flctl));
426
427 start_translation(flctl);
428 read_fiforeg(flctl, 16, 16 * 3);
429 wait_completion(flctl);
430 } else {
431 /* In case that the page size is 512b */
432 set_addr(mtd, 512, page_addr);
433 writel(16, FLDTCNTR(flctl));
434
435 start_translation(flctl);
436 read_fiforeg(flctl, 16, 0);
437 wait_completion(flctl);
438 }
439}
440
441static void execmd_write_page_sector(struct mtd_info *mtd)
442{
443 struct sh_flctl *flctl = mtd_to_flctl(mtd);
444 int i, page_addr = flctl->seqin_page_addr;
445 int sector, page_sectors;
446
447 if (flctl->page_size)
448 page_sectors = 4;
449 else
450 page_sectors = 1;
451
452 writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE, FLCMNCR(flctl));
453
454 set_cmd_regs(mtd, NAND_CMD_PAGEPROG,
455 (NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN);
456
457 for (sector = 0; sector < page_sectors; sector++) {
458 empty_fifo(flctl);
459 writel(readl(FLCMDCR(flctl)) | 1, FLCMDCR(flctl));
460 writel(page_addr << 2 | sector, FLADR(flctl));
461
462 start_translation(flctl);
463 write_fiforeg(flctl, 512, 512 * sector);
464
465 for (i = 0; i < 4; i++) {
466 wait_wecfifo_ready(flctl); /* wait for write ready */
467 writel(0xFFFFFFFF, FLECFIFO(flctl));
468 }
469 wait_completion(flctl);
470 }
471
472 writel(readl(FLCMNCR(flctl)) & ~ACM_SACCES_MODE, FLCMNCR(flctl));
473}
474
475static void execmd_write_oob(struct mtd_info *mtd)
476{
477 struct sh_flctl *flctl = mtd_to_flctl(mtd);
478 int page_addr = flctl->seqin_page_addr;
479 int sector, page_sectors;
480
481 if (flctl->page_size) {
482 sector = 3;
483 page_sectors = 4;
484 } else {
485 sector = 0;
486 page_sectors = 1;
487 }
488
489 set_cmd_regs(mtd, NAND_CMD_PAGEPROG,
490 (NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN);
491
492 for (; sector < page_sectors; sector++) {
493 empty_fifo(flctl);
494 set_addr(mtd, sector * 528 + 512, page_addr);
495 writel(16, FLDTCNTR(flctl)); /* set read size */
496
497 start_translation(flctl);
498 write_fiforeg(flctl, 16, 16 * sector);
499 wait_completion(flctl);
500 }
501}
502
503static void flctl_cmdfunc(struct mtd_info *mtd, unsigned int command,
504 int column, int page_addr)
505{
506 struct sh_flctl *flctl = mtd_to_flctl(mtd);
507 uint32_t read_cmd = 0;
508
509 flctl->read_bytes = 0;
510 if (command != NAND_CMD_PAGEPROG)
511 flctl->index = 0;
512
513 switch (command) {
514 case NAND_CMD_READ1:
515 case NAND_CMD_READ0:
516 if (flctl->hwecc) {
517 /* read page with hwecc */
518 execmd_read_page_sector(mtd, page_addr);
519 break;
520 }
521 empty_fifo(flctl);
522 if (flctl->page_size)
523 set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8)
524 | command);
525 else
526 set_cmd_regs(mtd, command, command);
527
528 set_addr(mtd, 0, page_addr);
529
530 flctl->read_bytes = mtd->writesize + mtd->oobsize;
531 flctl->index += column;
532 goto read_normal_exit;
533
534 case NAND_CMD_READOOB:
535 if (flctl->hwecc) {
536 /* read page with hwecc */
537 execmd_read_oob(mtd, page_addr);
538 break;
539 }
540
541 empty_fifo(flctl);
542 if (flctl->page_size) {
543 set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8)
544 | NAND_CMD_READ0);
545 set_addr(mtd, mtd->writesize, page_addr);
546 } else {
547 set_cmd_regs(mtd, command, command);
548 set_addr(mtd, 0, page_addr);
549 }
550 flctl->read_bytes = mtd->oobsize;
551 goto read_normal_exit;
552
553 case NAND_CMD_READID:
554 empty_fifo(flctl);
555 set_cmd_regs(mtd, command, command);
556 set_addr(mtd, 0, 0);
557
558 flctl->read_bytes = 4;
559 writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
560 start_translation(flctl);
561 read_datareg(flctl, 0); /* read and end */
562 break;
563
564 case NAND_CMD_ERASE1:
565 flctl->erase1_page_addr = page_addr;
566 break;
567
568 case NAND_CMD_ERASE2:
569 set_cmd_regs(mtd, NAND_CMD_ERASE1,
570 (command << 8) | NAND_CMD_ERASE1);
571 set_addr(mtd, -1, flctl->erase1_page_addr);
572 start_translation(flctl);
573 wait_completion(flctl);
574 break;
575
576 case NAND_CMD_SEQIN:
577 if (!flctl->page_size) {
578 /* output read command */
579 if (column >= mtd->writesize) {
580 column -= mtd->writesize;
581 read_cmd = NAND_CMD_READOOB;
582 } else if (column < 256) {
583 read_cmd = NAND_CMD_READ0;
584 } else {
585 column -= 256;
586 read_cmd = NAND_CMD_READ1;
587 }
588 }
589 flctl->seqin_column = column;
590 flctl->seqin_page_addr = page_addr;
591 flctl->seqin_read_cmd = read_cmd;
592 break;
593
594 case NAND_CMD_PAGEPROG:
595 empty_fifo(flctl);
596 if (!flctl->page_size) {
597 set_cmd_regs(mtd, NAND_CMD_SEQIN,
598 flctl->seqin_read_cmd);
599 set_addr(mtd, -1, -1);
600 writel(0, FLDTCNTR(flctl)); /* set 0 size */
601 start_translation(flctl);
602 wait_completion(flctl);
603 }
604 if (flctl->hwecc) {
605 /* write page with hwecc */
606 if (flctl->seqin_column == mtd->writesize)
607 execmd_write_oob(mtd);
608 else if (!flctl->seqin_column)
609 execmd_write_page_sector(mtd);
610 else
611 printk(KERN_ERR "Invalid address !?\n");
612 break;
613 }
614 set_cmd_regs(mtd, command, (command << 8) | NAND_CMD_SEQIN);
615 set_addr(mtd, flctl->seqin_column, flctl->seqin_page_addr);
616 writel(flctl->index, FLDTCNTR(flctl)); /* set write size */
617 start_translation(flctl);
618 write_fiforeg(flctl, flctl->index, 0);
619 wait_completion(flctl);
620 break;
621
622 case NAND_CMD_STATUS:
623 set_cmd_regs(mtd, command, command);
624 set_addr(mtd, -1, -1);
625
626 flctl->read_bytes = 1;
627 writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
628 start_translation(flctl);
629 read_datareg(flctl, 0); /* read and end */
630 break;
631
632 case NAND_CMD_RESET:
633 set_cmd_regs(mtd, command, command);
634 set_addr(mtd, -1, -1);
635
636 writel(0, FLDTCNTR(flctl)); /* set 0 size */
637 start_translation(flctl);
638 wait_completion(flctl);
639 break;
640
641 default:
642 break;
643 }
644 return;
645
646read_normal_exit:
647 writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
648 start_translation(flctl);
649 read_fiforeg(flctl, flctl->read_bytes, 0);
650 wait_completion(flctl);
651 return;
652}
653
654static void flctl_select_chip(struct mtd_info *mtd, int chipnr)
655{
656 struct sh_flctl *flctl = mtd_to_flctl(mtd);
657 uint32_t flcmncr_val = readl(FLCMNCR(flctl));
658
659 switch (chipnr) {
660 case -1:
661 flcmncr_val &= ~CE0_ENABLE;
662 writel(flcmncr_val, FLCMNCR(flctl));
663 break;
664 case 0:
665 flcmncr_val |= CE0_ENABLE;
666 writel(flcmncr_val, FLCMNCR(flctl));
667 break;
668 default:
669 BUG();
670 }
671}
672
673static void flctl_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
674{
675 struct sh_flctl *flctl = mtd_to_flctl(mtd);
676 int i, index = flctl->index;
677
678 for (i = 0; i < len; i++)
679 flctl->done_buff[index + i] = buf[i];
680 flctl->index += len;
681}
682
683static uint8_t flctl_read_byte(struct mtd_info *mtd)
684{
685 struct sh_flctl *flctl = mtd_to_flctl(mtd);
686 int index = flctl->index;
687 uint8_t data;
688
689 data = flctl->done_buff[index];
690 flctl->index++;
691 return data;
692}
693
694static void flctl_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
695{
696 int i;
697
698 for (i = 0; i < len; i++)
699 buf[i] = flctl_read_byte(mtd);
700}
701
702static int flctl_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
703{
704 int i;
705
706 for (i = 0; i < len; i++)
707 if (buf[i] != flctl_read_byte(mtd))
708 return -EFAULT;
709 return 0;
710}
711
712static void flctl_register_init(struct sh_flctl *flctl, unsigned long val)
713{
714 writel(val, FLCMNCR(flctl));
715}
716
717static int flctl_chip_init_tail(struct mtd_info *mtd)
718{
719 struct sh_flctl *flctl = mtd_to_flctl(mtd);
720 struct nand_chip *chip = &flctl->chip;
721
722 if (mtd->writesize == 512) {
723 flctl->page_size = 0;
724 if (chip->chipsize > (32 << 20)) {
725 /* big than 32MB */
726 flctl->rw_ADRCNT = ADRCNT_4;
727 flctl->erase_ADRCNT = ADRCNT_3;
728 } else if (chip->chipsize > (2 << 16)) {
729 /* big than 128KB */
730 flctl->rw_ADRCNT = ADRCNT_3;
731 flctl->erase_ADRCNT = ADRCNT_2;
732 } else {
733 flctl->rw_ADRCNT = ADRCNT_2;
734 flctl->erase_ADRCNT = ADRCNT_1;
735 }
736 } else {
737 flctl->page_size = 1;
738 if (chip->chipsize > (128 << 20)) {
739 /* big than 128MB */
740 flctl->rw_ADRCNT = ADRCNT2_E;
741 flctl->erase_ADRCNT = ADRCNT_3;
742 } else if (chip->chipsize > (8 << 16)) {
743 /* big than 512KB */
744 flctl->rw_ADRCNT = ADRCNT_4;
745 flctl->erase_ADRCNT = ADRCNT_2;
746 } else {
747 flctl->rw_ADRCNT = ADRCNT_3;
748 flctl->erase_ADRCNT = ADRCNT_1;
749 }
750 }
751
752 if (flctl->hwecc) {
753 if (mtd->writesize == 512) {
754 chip->ecc.layout = &flctl_4secc_oob_16;
755 chip->badblock_pattern = &flctl_4secc_smallpage;
756 } else {
757 chip->ecc.layout = &flctl_4secc_oob_64;
758 chip->badblock_pattern = &flctl_4secc_largepage;
759 }
760
761 chip->ecc.size = 512;
762 chip->ecc.bytes = 10;
763 chip->ecc.read_page = flctl_read_page_hwecc;
764 chip->ecc.write_page = flctl_write_page_hwecc;
765 chip->ecc.mode = NAND_ECC_HW;
766
767 /* 4 symbols ECC enabled */
768 writel(readl(FLCMNCR(flctl)) | _4ECCEN | ECCPOS2 | ECCPOS_02,
769 FLCMNCR(flctl));
770 } else {
771 chip->ecc.mode = NAND_ECC_SOFT;
772 }
773
774 return 0;
775}
776
b79c7adf 777static int __devinit flctl_probe(struct platform_device *pdev)
35a34799
YS		 778{
779 struct resource *res;
780 struct sh_flctl *flctl;
781 struct mtd_info *flctl_mtd;
782 struct nand_chip *nand;
783 struct sh_flctl_platform_data *pdata;
b79c7adf 784 int ret = -ENXIO;
35a34799
YS		 785
786 pdata = pdev->dev.platform_data;
787 if (pdata == NULL) {
b79c7adf
MD		 788 dev_err(&pdev->dev, "no platform data defined\n");
789 return -EINVAL;
35a34799
YS		 790 }
791
792 flctl = kzalloc(sizeof(struct sh_flctl), GFP_KERNEL);
793 if (!flctl) {
b79c7adf 794 dev_err(&pdev->dev, "failed to allocate driver data\n");
35a34799
YS		 795 return -ENOMEM;
796 }
797
798 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
799 if (!res) {
b79c7adf 800 dev_err(&pdev->dev, "failed to get I/O memory\n");
35a34799
YS		 801 goto err;
802 }
803
b79c7adf 804 flctl->reg = ioremap(res->start, resource_size(res));
35a34799 805 if (flctl->reg == NULL) {
b79c7adf 806 dev_err(&pdev->dev, "failed to remap I/O memory\n");
35a34799
YS		 807 goto err;
808 }
809
810 platform_set_drvdata(pdev, flctl);
811 flctl_mtd = &flctl->mtd;
812 nand = &flctl->chip;
813 flctl_mtd->priv = nand;
b79c7adf 814 flctl->pdev = pdev;
35a34799
YS		 815 flctl->hwecc = pdata->has_hwecc;
816
817 flctl_register_init(flctl, pdata->flcmncr_val);
818
819 nand->options = NAND_NO_AUTOINCR;
820
821 /* Set address of hardware control function */
822 /* 20 us command delay time */
823 nand->chip_delay = 20;
824
825 nand->read_byte = flctl_read_byte;
826 nand->write_buf = flctl_write_buf;
827 nand->read_buf = flctl_read_buf;
828 nand->verify_buf = flctl_verify_buf;
829 nand->select_chip = flctl_select_chip;
830 nand->cmdfunc = flctl_cmdfunc;
831
832 ret = nand_scan_ident(flctl_mtd, 1);
833 if (ret)
834 goto err;
835
836 ret = flctl_chip_init_tail(flctl_mtd);
837 if (ret)
838 goto err;
839
840 ret = nand_scan_tail(flctl_mtd);
841 if (ret)
842 goto err;
843
844 add_mtd_partitions(flctl_mtd, pdata->parts, pdata->nr_parts);
845
846 return 0;
847
848err:
849 kfree(flctl);
850 return ret;
851}
852
b79c7adf 853static int __devexit flctl_remove(struct platform_device *pdev)
35a34799
YS		 854{
855 struct sh_flctl *flctl = platform_get_drvdata(pdev);
856
857 nand_release(&flctl->mtd);
858 kfree(flctl);
859
860 return 0;
861}
862
863static struct platform_driver flctl_driver = {
35a34799
YS		 864 .remove = flctl_remove,
865 .driver = {
866 .name = "sh_flctl",
867 .owner = THIS_MODULE,
868 },
869};
870
871static int __init flctl_nand_init(void)
872{
894572a3 873 return platform_driver_probe(&flctl_driver, flctl_probe);
35a34799
YS		 874}
875
876static void __exit flctl_nand_cleanup(void)
877{
878 platform_driver_unregister(&flctl_driver);
879}
880
881module_init(flctl_nand_init);
882module_exit(flctl_nand_cleanup);
883
884MODULE_LICENSE("GPL");
885MODULE_AUTHOR("Yoshihiro Shimoda");
886MODULE_DESCRIPTION("SuperH FLCTL driver");
887MODULE_ALIAS("platform:sh_flctl");
Linux kernel - Deliverables
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