Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand/sharpsl.c | |
3 | * | |
4 | * Copyright (C) 2004 Richard Purdie | |
c176d0ca | 5 | * Copyright (C) 2008 Dmitry Baryshkov |
1da177e4 | 6 | * |
1da177e4 LT |
7 | * Based on Sharp's NAND driver sharp_sl.c |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <linux/genhd.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/mtd/mtd.h> | |
20 | #include <linux/mtd/nand.h> | |
21 | #include <linux/mtd/nand_ecc.h> | |
22 | #include <linux/mtd/partitions.h> | |
a20c7ab5 | 23 | #include <linux/mtd/sharpsl.h> |
1da177e4 | 24 | #include <linux/interrupt.h> |
26615249 DB |
25 | #include <linux/platform_device.h> |
26 | ||
1da177e4 | 27 | #include <asm/io.h> |
a09e64fb | 28 | #include <mach/hardware.h> |
1da177e4 LT |
29 | #include <asm/mach-types.h> |
30 | ||
2206ef1c DB |
31 | struct sharpsl_nand { |
32 | struct mtd_info mtd; | |
33 | struct nand_chip chip; | |
a4e4f29c DB |
34 | |
35 | void __iomem *io; | |
2206ef1c DB |
36 | }; |
37 | ||
a4e4f29c | 38 | #define mtd_to_sharpsl(_mtd) container_of(_mtd, struct sharpsl_nand, mtd) |
1da177e4 LT |
39 | |
40 | /* register offset */ | |
a4e4f29c DB |
41 | #define ECCLPLB 0x00 /* line parity 7 - 0 bit */ |
42 | #define ECCLPUB 0x04 /* line parity 15 - 8 bit */ | |
43 | #define ECCCP 0x08 /* column parity 5 - 0 bit */ | |
44 | #define ECCCNTR 0x0C /* ECC byte counter */ | |
45 | #define ECCCLRR 0x10 /* cleare ECC */ | |
46 | #define FLASHIO 0x14 /* Flash I/O */ | |
47 | #define FLASHCTL 0x18 /* Flash Control */ | |
1da177e4 LT |
48 | |
49 | /* Flash control bit */ | |
50 | #define FLRYBY (1 << 5) | |
51 | #define FLCE1 (1 << 4) | |
52 | #define FLWP (1 << 3) | |
53 | #define FLALE (1 << 2) | |
54 | #define FLCLE (1 << 1) | |
55 | #define FLCE0 (1 << 0) | |
56 | ||
61b03bd7 | 57 | /* |
1da177e4 | 58 | * hardware specific access to control-lines |
7abd3ef9 | 59 | * ctrl: |
6a5a297c | 60 | * NAND_CNE: bit 0 -> ! bit 0 & 4 |
7abd3ef9 TG |
61 | * NAND_CLE: bit 1 -> bit 1 |
62 | * NAND_ALE: bit 2 -> bit 2 | |
63 | * | |
1da177e4 | 64 | */ |
7abd3ef9 TG |
65 | static void sharpsl_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
66 | unsigned int ctrl) | |
1da177e4 | 67 | { |
a4e4f29c | 68 | struct sharpsl_nand *sharpsl = mtd_to_sharpsl(mtd); |
7abd3ef9 TG |
69 | struct nand_chip *chip = mtd->priv; |
70 | ||
71 | if (ctrl & NAND_CTRL_CHANGE) { | |
72 | unsigned char bits = ctrl & 0x07; | |
73 | ||
74 | bits |= (ctrl & 0x01) << 4; | |
6a5a297c RP |
75 | |
76 | bits ^= 0x11; | |
77 | ||
a4e4f29c | 78 | writeb((readb(sharpsl->io + FLASHCTL) & ~0x17) | bits, sharpsl->io + FLASHCTL); |
1da177e4 | 79 | } |
7abd3ef9 TG |
80 | |
81 | if (cmd != NAND_CMD_NONE) | |
82 | writeb(cmd, chip->IO_ADDR_W); | |
1da177e4 LT |
83 | } |
84 | ||
e0c7d767 | 85 | static int sharpsl_nand_dev_ready(struct mtd_info *mtd) |
1da177e4 | 86 | { |
a4e4f29c DB |
87 | struct sharpsl_nand *sharpsl = mtd_to_sharpsl(mtd); |
88 | return !((readb(sharpsl->io + FLASHCTL) & FLRYBY) == 0); | |
1da177e4 LT |
89 | } |
90 | ||
e0c7d767 | 91 | static void sharpsl_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
1da177e4 | 92 | { |
a4e4f29c DB |
93 | struct sharpsl_nand *sharpsl = mtd_to_sharpsl(mtd); |
94 | writeb(0, sharpsl->io + ECCCLRR); | |
1da177e4 LT |
95 | } |
96 | ||
e0c7d767 | 97 | static int sharpsl_nand_calculate_ecc(struct mtd_info *mtd, const u_char * dat, u_char * ecc_code) |
1da177e4 | 98 | { |
a4e4f29c DB |
99 | struct sharpsl_nand *sharpsl = mtd_to_sharpsl(mtd); |
100 | ecc_code[0] = ~readb(sharpsl->io + ECCLPUB); | |
101 | ecc_code[1] = ~readb(sharpsl->io + ECCLPLB); | |
102 | ecc_code[2] = (~readb(sharpsl->io + ECCCP) << 2) | 0x03; | |
103 | return readb(sharpsl->io + ECCCNTR) != 0; | |
1da177e4 LT |
104 | } |
105 | ||
c176d0ca | 106 | static const char *part_probes[] = { "cmdlinepart", NULL }; |
1da177e4 | 107 | |
1da177e4 LT |
108 | /* |
109 | * Main initialization routine | |
110 | */ | |
26615249 | 111 | static int __devinit sharpsl_nand_probe(struct platform_device *pdev) |
1da177e4 LT |
112 | { |
113 | struct nand_chip *this; | |
e0c7d767 | 114 | struct mtd_partition *sharpsl_partition_info; |
c176d0ca | 115 | int nr_partitions; |
26615249 | 116 | struct resource *r; |
1da177e4 | 117 | int err = 0; |
2206ef1c | 118 | struct sharpsl_nand *sharpsl; |
a20c7ab5 DB |
119 | struct sharpsl_nand_platform_data *data = pdev->dev.platform_data; |
120 | ||
121 | if (!data) { | |
122 | dev_err(&pdev->dev, "no platform data!\n"); | |
123 | return -EINVAL; | |
124 | } | |
1da177e4 LT |
125 | |
126 | /* Allocate memory for MTD device structure and private data */ | |
2206ef1c DB |
127 | sharpsl = kzalloc(sizeof(struct sharpsl_nand), GFP_KERNEL); |
128 | if (!sharpsl) { | |
e0c7d767 | 129 | printk("Unable to allocate SharpSL NAND MTD device structure.\n"); |
1da177e4 LT |
130 | return -ENOMEM; |
131 | } | |
61b03bd7 | 132 | |
26615249 DB |
133 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
134 | if (!r) { | |
135 | dev_err(&pdev->dev, "no io memory resource defined!\n"); | |
136 | err = -ENODEV; | |
137 | goto err_get_res; | |
138 | } | |
139 | ||
8e87d782 | 140 | /* map physical address */ |
a4e4f29c DB |
141 | sharpsl->io = ioremap(r->start, resource_size(r)); |
142 | if (!sharpsl->io) { | |
1da177e4 | 143 | printk("ioremap to access Sharp SL NAND chip failed\n"); |
2206ef1c DB |
144 | err = -EIO; |
145 | goto err_ioremap; | |
1da177e4 | 146 | } |
61b03bd7 | 147 | |
1da177e4 | 148 | /* Get pointer to private data */ |
2206ef1c | 149 | this = (struct nand_chip *)(&sharpsl->chip); |
1da177e4 LT |
150 | |
151 | /* Link the private data with the MTD structure */ | |
2206ef1c DB |
152 | sharpsl->mtd.priv = this; |
153 | sharpsl->mtd.owner = THIS_MODULE; | |
154 | ||
155 | platform_set_drvdata(pdev, sharpsl); | |
1da177e4 LT |
156 | |
157 | /* | |
158 | * PXA initialize | |
159 | */ | |
a4e4f29c | 160 | writeb(readb(sharpsl->io + FLASHCTL) | FLWP, sharpsl->io + FLASHCTL); |
1da177e4 LT |
161 | |
162 | /* Set address of NAND IO lines */ | |
a4e4f29c DB |
163 | this->IO_ADDR_R = sharpsl->io + FLASHIO; |
164 | this->IO_ADDR_W = sharpsl->io + FLASHIO; | |
1da177e4 | 165 | /* Set address of hardware control function */ |
7abd3ef9 | 166 | this->cmd_ctrl = sharpsl_nand_hwcontrol; |
1da177e4 LT |
167 | this->dev_ready = sharpsl_nand_dev_ready; |
168 | /* 15 us command delay time */ | |
169 | this->chip_delay = 15; | |
170 | /* set eccmode using hardware ECC */ | |
6dfc6d25 TG |
171 | this->ecc.mode = NAND_ECC_HW; |
172 | this->ecc.size = 256; | |
173 | this->ecc.bytes = 3; | |
a20c7ab5 DB |
174 | this->badblock_pattern = data->badblock_pattern; |
175 | this->ecc.layout = data->ecc_layout; | |
6dfc6d25 TG |
176 | this->ecc.hwctl = sharpsl_nand_enable_hwecc; |
177 | this->ecc.calculate = sharpsl_nand_calculate_ecc; | |
178 | this->ecc.correct = nand_correct_data; | |
1da177e4 LT |
179 | |
180 | /* Scan to find existence of the device */ | |
2206ef1c | 181 | err = nand_scan(&sharpsl->mtd, 1); |
a4e4f29c DB |
182 | if (err) |
183 | goto err_scan; | |
1da177e4 LT |
184 | |
185 | /* Register the partitions */ | |
2206ef1c DB |
186 | sharpsl->mtd.name = "sharpsl-nand"; |
187 | nr_partitions = parse_mtd_partitions(&sharpsl->mtd, part_probes, &sharpsl_partition_info, 0); | |
1da177e4 | 188 | if (nr_partitions <= 0) { |
a20c7ab5 DB |
189 | nr_partitions = data->nr_partitions; |
190 | sharpsl_partition_info = data->partitions; | |
1da177e4 LT |
191 | } |
192 | ||
6baed700 JI |
193 | err = mtd_device_register(&sharpsl->mtd, sharpsl_partition_info, |
194 | nr_partitions); | |
c176d0ca DB |
195 | if (err) |
196 | goto err_add; | |
1da177e4 LT |
197 | |
198 | /* Return happy */ | |
199 | return 0; | |
e0c7d767 | 200 | |
c176d0ca DB |
201 | err_add: |
202 | nand_release(&sharpsl->mtd); | |
203 | ||
a4e4f29c DB |
204 | err_scan: |
205 | platform_set_drvdata(pdev, NULL); | |
206 | iounmap(sharpsl->io); | |
2206ef1c | 207 | err_ioremap: |
26615249 | 208 | err_get_res: |
2206ef1c | 209 | kfree(sharpsl); |
26615249 DB |
210 | return err; |
211 | } | |
1da177e4 LT |
212 | |
213 | /* | |
214 | * Clean up routine | |
215 | */ | |
26615249 | 216 | static int __devexit sharpsl_nand_remove(struct platform_device *pdev) |
1da177e4 | 217 | { |
2206ef1c DB |
218 | struct sharpsl_nand *sharpsl = platform_get_drvdata(pdev); |
219 | ||
1da177e4 | 220 | /* Release resources, unregister device */ |
2206ef1c DB |
221 | nand_release(&sharpsl->mtd); |
222 | ||
223 | platform_set_drvdata(pdev, NULL); | |
1da177e4 | 224 | |
a4e4f29c | 225 | iounmap(sharpsl->io); |
1da177e4 LT |
226 | |
227 | /* Free the MTD device structure */ | |
2206ef1c | 228 | kfree(sharpsl); |
26615249 DB |
229 | |
230 | return 0; | |
231 | } | |
232 | ||
233 | static struct platform_driver sharpsl_nand_driver = { | |
234 | .driver = { | |
235 | .name = "sharpsl-nand", | |
236 | .owner = THIS_MODULE, | |
237 | }, | |
238 | .probe = sharpsl_nand_probe, | |
239 | .remove = __devexit_p(sharpsl_nand_remove), | |
240 | }; | |
241 | ||
26615249 DB |
242 | static int __init sharpsl_nand_init(void) |
243 | { | |
26615249 | 244 | return platform_driver_register(&sharpsl_nand_driver); |
1da177e4 | 245 | } |
26615249 | 246 | module_init(sharpsl_nand_init); |
e0c7d767 | 247 | |
26615249 DB |
248 | static void __exit sharpsl_nand_exit(void) |
249 | { | |
250 | platform_driver_unregister(&sharpsl_nand_driver); | |
26615249 DB |
251 | } |
252 | module_exit(sharpsl_nand_exit); | |
1da177e4 LT |
253 | |
254 | MODULE_LICENSE("GPL"); | |
255 | MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>"); | |
256 | MODULE_DESCRIPTION("Device specific logic for NAND flash on Sharp SL-C7xx Series"); |