[deliverable/linux.git] / drivers / mtd / nand / tmio_nand.c

/*
 * Toshiba TMIO NAND flash controller driver
 *
 * Slightly murky pre-git history of the driver:
 *
 * Copyright (c) Ian Molton 2004, 2005, 2008
 *    Original work, independent of sharps code. Included hardware ECC support.
 *    Hard ECC did not work for writes in the early revisions.
 * Copyright (c) Dirk Opfer 2005.
 *    Modifications developed from sharps code but
 *    NOT containing any, ported onto Ians base.
 * Copyright (c) Chris Humbert 2005
 * Copyright (c) Dmitry Baryshkov 2008
 *    Minor fixes
 *
 * Parts copyright Sebastian Carlier
 *
 * This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 */


#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include <linux/mfd/tmio.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
#include <linux/slab.h>

/*--------------------------------------------------------------------------*/

/*
 * NAND Flash Host Controller Configuration Register
 */
#define CCR_COMMAND	0x04	/* w Command				*/
#define CCR_BASE	0x10	/* l NAND Flash Control Reg Base Addr	*/
#define CCR_INTP	0x3d	/* b Interrupt Pin			*/
#define CCR_INTE	0x48	/* b Interrupt Enable			*/
#define CCR_EC		0x4a	/* b Event Control			*/
#define CCR_ICC		0x4c	/* b Internal Clock Control		*/
#define CCR_ECCC	0x5b	/* b ECC Control			*/
#define CCR_NFTC	0x60	/* b NAND Flash Transaction Control	*/
#define CCR_NFM		0x61	/* b NAND Flash Monitor			*/
#define CCR_NFPSC	0x62	/* b NAND Flash Power Supply Control	*/
#define CCR_NFDC	0x63	/* b NAND Flash Detect Control		*/

/*
 * NAND Flash Control Register
 */
#define FCR_DATA	0x00	/* bwl Data Register			*/
#define FCR_MODE	0x04	/* b Mode Register			*/
#define FCR_STATUS	0x05	/* b Status Register			*/
#define FCR_ISR		0x06	/* b Interrupt Status Register		*/
#define FCR_IMR		0x07	/* b Interrupt Mask Register		*/

/* FCR_MODE Register Command List */
#define FCR_MODE_DATA	0x94	/* Data Data_Mode */
#define FCR_MODE_COMMAND 0x95	/* Data Command_Mode */
#define FCR_MODE_ADDRESS 0x96	/* Data Address_Mode */

#define FCR_MODE_HWECC_CALC	0xB4	/* HW-ECC Data */
#define FCR_MODE_HWECC_RESULT	0xD4	/* HW-ECC Calc result Read_Mode */
#define FCR_MODE_HWECC_RESET	0xF4	/* HW-ECC Reset */

#define FCR_MODE_POWER_ON	0x0C	/* Power Supply ON  to SSFDC card */
#define FCR_MODE_POWER_OFF	0x08	/* Power Supply OFF to SSFDC card */

#define FCR_MODE_LED_OFF	0x00	/* LED OFF */
#define FCR_MODE_LED_ON		0x04	/* LED ON */

#define FCR_MODE_EJECT_ON	0x68	/* Ejection events active  */
#define FCR_MODE_EJECT_OFF	0x08	/* Ejection events ignored */

#define FCR_MODE_LOCK		0x6C	/* Lock_Mode. Eject Switch Invalid */
#define FCR_MODE_UNLOCK		0x0C	/* UnLock_Mode. Eject Switch is valid */

#define FCR_MODE_CONTROLLER_ID	0x40	/* Controller ID Read */
#define FCR_MODE_STANDBY	0x00	/* SSFDC card Changes Standby State */

#define FCR_MODE_WE		0x80
#define FCR_MODE_ECC1		0x40
#define FCR_MODE_ECC0		0x20
#define FCR_MODE_CE		0x10
#define FCR_MODE_PCNT1		0x08
#define FCR_MODE_PCNT0		0x04
#define FCR_MODE_ALE		0x02
#define FCR_MODE_CLE		0x01

#define FCR_STATUS_BUSY		0x80

/*--------------------------------------------------------------------------*/

struct tmio_nand {
	struct nand_chip chip;

	struct platform_device *dev;

	void __iomem *ccr;
	void __iomem *fcr;
	unsigned long fcr_base;

	unsigned int irq;

	/* for tmio_nand_read_byte */
	u8			read;
	unsigned read_good:1;
};

static inline struct tmio_nand *mtd_to_tmio(struct mtd_info *mtd)
{
	return container_of(mtd_to_nand(mtd), struct tmio_nand, chip);
}


/*--------------------------------------------------------------------------*/

static void tmio_nand_hwcontrol(struct mtd_info *mtd, int cmd,
				   unsigned int ctrl)
{
	struct tmio_nand *tmio = mtd_to_tmio(mtd);
	struct nand_chip *chip = mtd_to_nand(mtd);

	if (ctrl & NAND_CTRL_CHANGE) {
		u8 mode;

		if (ctrl & NAND_NCE) {
			mode = FCR_MODE_DATA;

			if (ctrl & NAND_CLE)
				mode |=  FCR_MODE_CLE;
			else
				mode &= ~FCR_MODE_CLE;

			if (ctrl & NAND_ALE)
				mode |=  FCR_MODE_ALE;
			else
				mode &= ~FCR_MODE_ALE;
		} else {
			mode = FCR_MODE_STANDBY;
		}

		tmio_iowrite8(mode, tmio->fcr + FCR_MODE);
		tmio->read_good = 0;
	}

	if (cmd != NAND_CMD_NONE)
		tmio_iowrite8(cmd, chip->IO_ADDR_W);
}

static int tmio_nand_dev_ready(struct mtd_info *mtd)
{
	struct tmio_nand *tmio = mtd_to_tmio(mtd);

	return !(tmio_ioread8(tmio->fcr + FCR_STATUS) & FCR_STATUS_BUSY);
}

static irqreturn_t tmio_irq(int irq, void *__tmio)
{
	struct tmio_nand *tmio = __tmio;
	struct nand_chip *nand_chip = &tmio->chip;

	/* disable RDYREQ interrupt */
	tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);

	if (unlikely(!waitqueue_active(&nand_chip->controller->wq)))
		dev_warn(&tmio->dev->dev, "spurious interrupt\n");

	wake_up(&nand_chip->controller->wq);
	return IRQ_HANDLED;
}

/*
  *The TMIO core has a RDYREQ interrupt on the posedge of #SMRB.
  *This interrupt is normally disabled, but for long operations like
  *erase and write, we enable it to wake us up.  The irq handler
  *disables the interrupt.
 */
static int
tmio_nand_wait(struct mtd_info *mtd, struct nand_chip *nand_chip)
{
	struct tmio_nand *tmio = mtd_to_tmio(mtd);
	long timeout;

	/* enable RDYREQ interrupt */
	tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR);
	tmio_iowrite8(0x81, tmio->fcr + FCR_IMR);

	timeout = wait_event_timeout(nand_chip->controller->wq,
		tmio_nand_dev_ready(mtd),
		msecs_to_jiffies(nand_chip->state == FL_ERASING ? 400 : 20));

	if (unlikely(!tmio_nand_dev_ready(mtd))) {
		tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
		dev_warn(&tmio->dev->dev, "still busy with %s after %d ms\n",
			nand_chip->state == FL_ERASING ? "erase" : "program",
			nand_chip->state == FL_ERASING ? 400 : 20);

	} else if (unlikely(!timeout)) {
		tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
		dev_warn(&tmio->dev->dev, "timeout waiting for interrupt\n");
	}

	nand_chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
	return nand_chip->read_byte(mtd);
}

/*
  *The TMIO controller combines two 8-bit data bytes into one 16-bit
  *word. This function separates them so nand_base.c works as expected,
  *especially its NAND_CMD_READID routines.
 *
  *To prevent stale data from being read, tmio_nand_hwcontrol() clears
  *tmio->read_good.
 */
static u_char tmio_nand_read_byte(struct mtd_info *mtd)
{
	struct tmio_nand *tmio = mtd_to_tmio(mtd);
	unsigned int data;

	if (tmio->read_good--)
		return tmio->read;

	data = tmio_ioread16(tmio->fcr + FCR_DATA);
	tmio->read = data >> 8;
	return data;
}

/*
  *The TMIO controller converts an 8-bit NAND interface to a 16-bit
  *bus interface, so all data reads and writes must be 16-bit wide.
  *Thus, we implement 16-bit versions of the read, write, and verify
  *buffer functions.
 */
static void
tmio_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
{
	struct tmio_nand *tmio = mtd_to_tmio(mtd);

	tmio_iowrite16_rep(tmio->fcr + FCR_DATA, buf, len >> 1);
}

static void tmio_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
{
	struct tmio_nand *tmio = mtd_to_tmio(mtd);

	tmio_ioread16_rep(tmio->fcr + FCR_DATA, buf, len >> 1);
}

static void tmio_nand_enable_hwecc(struct mtd_info *mtd, int mode)
{
	struct tmio_nand *tmio = mtd_to_tmio(mtd);

	tmio_iowrite8(FCR_MODE_HWECC_RESET, tmio->fcr + FCR_MODE);
	tmio_ioread8(tmio->fcr + FCR_DATA);	/* dummy read */
	tmio_iowrite8(FCR_MODE_HWECC_CALC, tmio->fcr + FCR_MODE);
}

static int tmio_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
							u_char *ecc_code)
{
	struct tmio_nand *tmio = mtd_to_tmio(mtd);
	unsigned int ecc;

	tmio_iowrite8(FCR_MODE_HWECC_RESULT, tmio->fcr + FCR_MODE);

	ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
	ecc_code[1] = ecc;	/* 000-255 LP7-0 */
	ecc_code[0] = ecc >> 8;	/* 000-255 LP15-8 */
	ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
	ecc_code[2] = ecc;	/* 000-255 CP5-0,11b */
	ecc_code[4] = ecc >> 8;	/* 256-511 LP7-0 */
	ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
	ecc_code[3] = ecc;	/* 256-511 LP15-8 */
	ecc_code[5] = ecc >> 8;	/* 256-511 CP5-0,11b */

	tmio_iowrite8(FCR_MODE_DATA, tmio->fcr + FCR_MODE);
	return 0;
}

static int tmio_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
		unsigned char *read_ecc, unsigned char *calc_ecc)
{
	int r0, r1;

	/* assume ecc.size = 512 and ecc.bytes = 6 */
	r0 = __nand_correct_data(buf, read_ecc, calc_ecc, 256);
	if (r0 < 0)
		return r0;
	r1 = __nand_correct_data(buf + 256, read_ecc + 3, calc_ecc + 3, 256);
	if (r1 < 0)
		return r1;
	return r0 + r1;
}

static int tmio_hw_init(struct platform_device *dev, struct tmio_nand *tmio)
{
	const struct mfd_cell *cell = mfd_get_cell(dev);
	int ret;

	if (cell->enable) {
		ret = cell->enable(dev);
		if (ret)
			return ret;
	}

	/* (4Ch) CLKRUN Enable    1st spcrunc */
	tmio_iowrite8(0x81, tmio->ccr + CCR_ICC);

	/* (10h)BaseAddress    0x1000 spba.spba2 */
	tmio_iowrite16(tmio->fcr_base, tmio->ccr + CCR_BASE);
	tmio_iowrite16(tmio->fcr_base >> 16, tmio->ccr + CCR_BASE + 2);

	/* (04h)Command Register I/O spcmd */
	tmio_iowrite8(0x02, tmio->ccr + CCR_COMMAND);

	/* (62h) Power Supply Control ssmpwc */
	/* HardPowerOFF - SuspendOFF - PowerSupplyWait_4MS */
	tmio_iowrite8(0x02, tmio->ccr + CCR_NFPSC);

	/* (63h) Detect Control ssmdtc */
	tmio_iowrite8(0x02, tmio->ccr + CCR_NFDC);

	/* Interrupt status register clear sintst */
	tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR);

	/* After power supply, Media are reset smode */
	tmio_iowrite8(FCR_MODE_POWER_ON, tmio->fcr + FCR_MODE);
	tmio_iowrite8(FCR_MODE_COMMAND, tmio->fcr + FCR_MODE);
	tmio_iowrite8(NAND_CMD_RESET, tmio->fcr + FCR_DATA);

	/* Standby Mode smode */
	tmio_iowrite8(FCR_MODE_STANDBY, tmio->fcr + FCR_MODE);

	mdelay(5);

	return 0;
}

static void tmio_hw_stop(struct platform_device *dev, struct tmio_nand *tmio)
{
	const struct mfd_cell *cell = mfd_get_cell(dev);

	tmio_iowrite8(FCR_MODE_POWER_OFF, tmio->fcr + FCR_MODE);
	if (cell->disable)
		cell->disable(dev);
}

static int tmio_probe(struct platform_device *dev)
{
	struct tmio_nand_data *data = dev_get_platdata(&dev->dev);
	struct resource *fcr = platform_get_resource(dev,
			IORESOURCE_MEM, 0);
	struct resource *ccr = platform_get_resource(dev,
			IORESOURCE_MEM, 1);
	int irq = platform_get_irq(dev, 0);
	struct tmio_nand *tmio;
	struct mtd_info *mtd;
	struct nand_chip *nand_chip;
	int retval;

	if (data == NULL)
		dev_warn(&dev->dev, "NULL platform data!\n");

	tmio = devm_kzalloc(&dev->dev, sizeof(*tmio), GFP_KERNEL);
	if (!tmio)
		return -ENOMEM;

	tmio->dev = dev;

	platform_set_drvdata(dev, tmio);
	nand_chip = &tmio->chip;
	mtd = nand_to_mtd(nand_chip);
	mtd->name = "tmio-nand";
	mtd->dev.parent = &dev->dev;

	tmio->ccr = devm_ioremap(&dev->dev, ccr->start, resource_size(ccr));
	if (!tmio->ccr)
		return -EIO;

	tmio->fcr_base = fcr->start & 0xfffff;
	tmio->fcr = devm_ioremap(&dev->dev, fcr->start, resource_size(fcr));
	if (!tmio->fcr)
		return -EIO;

	retval = tmio_hw_init(dev, tmio);
	if (retval)
		return retval;

	/* Set address of NAND IO lines */
	nand_chip->IO_ADDR_R = tmio->fcr;
	nand_chip->IO_ADDR_W = tmio->fcr;

	/* Set address of hardware control function */
	nand_chip->cmd_ctrl = tmio_nand_hwcontrol;
	nand_chip->dev_ready = tmio_nand_dev_ready;
	nand_chip->read_byte = tmio_nand_read_byte;
	nand_chip->write_buf = tmio_nand_write_buf;
	nand_chip->read_buf = tmio_nand_read_buf;

	/* set eccmode using hardware ECC */
	nand_chip->ecc.mode = NAND_ECC_HW;
	nand_chip->ecc.size = 512;
	nand_chip->ecc.bytes = 6;
	nand_chip->ecc.strength = 2;
	nand_chip->ecc.hwctl = tmio_nand_enable_hwecc;
	nand_chip->ecc.calculate = tmio_nand_calculate_ecc;
	nand_chip->ecc.correct = tmio_nand_correct_data;

	if (data)
		nand_chip->badblock_pattern = data->badblock_pattern;

	/* 15 us command delay time */
	nand_chip->chip_delay = 15;

	retval = devm_request_irq(&dev->dev, irq, &tmio_irq, 0,
				  dev_name(&dev->dev), tmio);
	if (retval) {
		dev_err(&dev->dev, "request_irq error %d\n", retval);
		goto err_irq;
	}

	tmio->irq = irq;
	nand_chip->waitfunc = tmio_nand_wait;

	/* Scan to find existence of the device */
	if (nand_scan(mtd, 1)) {
		retval = -ENODEV;
		goto err_irq;
	}
	/* Register the partitions */
	retval = mtd_device_parse_register(mtd, NULL, NULL,
					   data ? data->partition : NULL,
					   data ? data->num_partitions : 0);
	if (!retval)
		return retval;

	nand_release(mtd);

err_irq:
	tmio_hw_stop(dev, tmio);
	return retval;
}

static int tmio_remove(struct platform_device *dev)
{
	struct tmio_nand *tmio = platform_get_drvdata(dev);

	nand_release(nand_to_mtd(&tmio->chip));
	tmio_hw_stop(dev, tmio);
	return 0;
}

#ifdef CONFIG_PM
static int tmio_suspend(struct platform_device *dev, pm_message_t state)
{
	const struct mfd_cell *cell = mfd_get_cell(dev);

	if (cell->suspend)
		cell->suspend(dev);

	tmio_hw_stop(dev, platform_get_drvdata(dev));
	return 0;
}

static int tmio_resume(struct platform_device *dev)
{
	const struct mfd_cell *cell = mfd_get_cell(dev);

	/* FIXME - is this required or merely another attack of the broken
	 * SHARP platform? Looks suspicious.
	 */
	tmio_hw_init(dev, platform_get_drvdata(dev));

	if (cell->resume)
		cell->resume(dev);

	return 0;
}
#else
#define tmio_suspend NULL
#define tmio_resume NULL
#endif

static struct platform_driver tmio_driver = {
	.driver.name	= "tmio-nand",
	.driver.owner	= THIS_MODULE,
	.probe		= tmio_probe,
	.remove		= tmio_remove,
	.suspend	= tmio_suspend,
	.resume		= tmio_resume,
};

module_platform_driver(tmio_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Ian Molton, Dirk Opfer, Chris Humbert, Dmitry Baryshkov");
MODULE_DESCRIPTION("NAND flash driver on Toshiba Mobile IO controller");
MODULE_ALIAS("platform:tmio-nand");
Commit	Line	Data
ec43b816 IM	1	/*
	2	* Toshiba TMIO NAND flash controller driver
	3	*
	4	* Slightly murky pre-git history of the driver:
	5	*
	6	* Copyright (c) Ian Molton 2004, 2005, 2008
25985edc	7	* Original work, independent of sharps code. Included hardware ECC support.
ec43b816 IM	8	* Hard ECC did not work for writes in the early revisions.
	9	* Copyright (c) Dirk Opfer 2005.
	10	* Modifications developed from sharps code but
	11	* NOT containing any, ported onto Ians base.
	12	* Copyright (c) Chris Humbert 2005
	13	* Copyright (c) Dmitry Baryshkov 2008
	14	* Minor fixes
	15	*
	16	* Parts copyright Sebastian Carlier
	17	*
	18	* This file is licensed under
	19	* the terms of the GNU General Public License version 2. This program
	20	* is licensed "as is" without any warranty of any kind, whether express
	21	* or implied.
	22	*
	23	*/
	24
	25
	26	#include <linux/kernel.h>
	27	#include <linux/module.h>
	28	#include <linux/platform_device.h>
	29	#include <linux/mfd/core.h>
	30	#include <linux/mfd/tmio.h>
	31	#include <linux/delay.h>
	32	#include <linux/io.h>
	33	#include <linux/irq.h>
	34	#include <linux/interrupt.h>
	35	#include <linux/ioport.h>
	36	#include <linux/mtd/mtd.h>
	37	#include <linux/mtd/nand.h>
	38	#include <linux/mtd/nand_ecc.h>
	39	#include <linux/mtd/partitions.h>
5a0e3ad6	40	#include <linux/slab.h>
ec43b816 IM	41
	42	/--------------------------------------------------------------------------/
	43
	44	/*
	45	* NAND Flash Host Controller Configuration Register
	46	*/
	47	#define CCR_COMMAND 0x04 /* w Command */
	48	#define CCR_BASE 0x10 /* l NAND Flash Control Reg Base Addr */
	49	#define CCR_INTP 0x3d /* b Interrupt Pin */
	50	#define CCR_INTE 0x48 /* b Interrupt Enable */
	51	#define CCR_EC 0x4a /* b Event Control */
	52	#define CCR_ICC 0x4c /* b Internal Clock Control */
	53	#define CCR_ECCC 0x5b /* b ECC Control */
	54	#define CCR_NFTC 0x60 /* b NAND Flash Transaction Control */
	55	#define CCR_NFM 0x61 /* b NAND Flash Monitor */
	56	#define CCR_NFPSC 0x62 /* b NAND Flash Power Supply Control */
	57	#define CCR_NFDC 0x63 /* b NAND Flash Detect Control */
	58
	59	/*
	60	* NAND Flash Control Register
	61	*/
	62	#define FCR_DATA 0x00 /* bwl Data Register */
	63	#define FCR_MODE 0x04 /* b Mode Register */
	64	#define FCR_STATUS 0x05 /* b Status Register */
	65	#define FCR_ISR 0x06 /* b Interrupt Status Register */
	66	#define FCR_IMR 0x07 /* b Interrupt Mask Register */
	67
	68	/* FCR_MODE Register Command List */
	69	#define FCR_MODE_DATA 0x94 /* Data Data_Mode */
	70	#define FCR_MODE_COMMAND 0x95 /* Data Command_Mode */
	71	#define FCR_MODE_ADDRESS 0x96 /* Data Address_Mode */
	72
	73	#define FCR_MODE_HWECC_CALC 0xB4 /* HW-ECC Data */
	74	#define FCR_MODE_HWECC_RESULT 0xD4 /* HW-ECC Calc result Read_Mode */
	75	#define FCR_MODE_HWECC_RESET 0xF4 /* HW-ECC Reset */
	76
	77	#define FCR_MODE_POWER_ON 0x0C /* Power Supply ON to SSFDC card */
	78	#define FCR_MODE_POWER_OFF 0x08 /* Power Supply OFF to SSFDC card */
	79
	80	#define FCR_MODE_LED_OFF 0x00 /* LED OFF */
	81	#define FCR_MODE_LED_ON 0x04 /* LED ON */
	82
	83	#define FCR_MODE_EJECT_ON 0x68 /* Ejection events active */
	84	#define FCR_MODE_EJECT_OFF 0x08 /* Ejection events ignored */
	85
	86	#define FCR_MODE_LOCK 0x6C /* Lock_Mode. Eject Switch Invalid */
	87	#define FCR_MODE_UNLOCK 0x0C /* UnLock_Mode. Eject Switch is valid */
	88
	89	#define FCR_MODE_CONTROLLER_ID 0x40 /* Controller ID Read */
	90	#define FCR_MODE_STANDBY 0x00 /* SSFDC card Changes Standby State */
	91
	92	#define FCR_MODE_WE 0x80
	93	#define FCR_MODE_ECC1 0x40
	94	#define FCR_MODE_ECC0 0x20
	95	#define FCR_MODE_CE 0x10
	96	#define FCR_MODE_PCNT1 0x08
	97	#define FCR_MODE_PCNT0 0x04
	98	#define FCR_MODE_ALE 0x02
	99	#define FCR_MODE_CLE 0x01
	100
	101	#define FCR_STATUS_BUSY 0x80
	102
	103	/--------------------------------------------------------------------------/
	104
105	struct tmio_nand {
ec43b816 IM	106	struct nand_chip chip;
	107
	108	struct platform_device *dev;
	109
	110	void __iomem *ccr;
	111	void __iomem *fcr;
076c7f4c	112	unsigned long fcr_base;
ec43b816 IM	113
	114	unsigned int irq;
	115
	116	/* for tmio_nand_read_byte */
	117	u8 read;
	118	unsigned read_good:1;
	119	};
	120
66c9595d BB	121	static inline struct tmio_nand mtd_to_tmio(struct mtd_info mtd)
	122	{
	123	return container_of(mtd_to_nand(mtd), struct tmio_nand, chip);
	124	}
ec43b816	125
ec43b816 IM	126
	127	/--------------------------------------------------------------------------/
	128
	129	static void tmio_nand_hwcontrol(struct mtd_info *mtd, int cmd,
	130	unsigned int ctrl)
	131	{
	132	struct tmio_nand *tmio = mtd_to_tmio(mtd);
4bd4ebcc	133	struct nand_chip *chip = mtd_to_nand(mtd);
ec43b816 IM	134
	135	if (ctrl & NAND_CTRL_CHANGE) {
	136	u8 mode;
	137
	138	if (ctrl & NAND_NCE) {
	139	mode = FCR_MODE_DATA;
	140
	141	if (ctrl & NAND_CLE)
	142	mode \|= FCR_MODE_CLE;
	143	else
	144	mode &= ~FCR_MODE_CLE;
	145
	146	if (ctrl & NAND_ALE)
	147	mode \|= FCR_MODE_ALE;
	148	else
	149	mode &= ~FCR_MODE_ALE;
	150	} else {
	151	mode = FCR_MODE_STANDBY;
	152	}
	153
	154	tmio_iowrite8(mode, tmio->fcr + FCR_MODE);
	155	tmio->read_good = 0;
	156	}
	157
	158	if (cmd != NAND_CMD_NONE)
	159	tmio_iowrite8(cmd, chip->IO_ADDR_W);
	160	}
	161
	162	static int tmio_nand_dev_ready(struct mtd_info *mtd)
	163	{
	164	struct tmio_nand *tmio = mtd_to_tmio(mtd);
	165
	166	return !(tmio_ioread8(tmio->fcr + FCR_STATUS) & FCR_STATUS_BUSY);
	167	}
	168
	169	static irqreturn_t tmio_irq(int irq, void *__tmio)
	170	{
	171	struct tmio_nand *tmio = __tmio;
	172	struct nand_chip *nand_chip = &tmio->chip;
	173
	174	/* disable RDYREQ interrupt */
	175	tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
	176
	177	if (unlikely(!waitqueue_active(&nand_chip->controller->wq)))
	178	dev_warn(&tmio->dev->dev, "spurious interrupt\n");
	179
	180	wake_up(&nand_chip->controller->wq);
	181	return IRQ_HANDLED;
	182	}
	183
	184	/*
	185	*The TMIO core has a RDYREQ interrupt on the posedge of #SMRB.
	186	*This interrupt is normally disabled, but for long operations like
	187	*erase and write, we enable it to wake us up. The irq handler
	188	*disables the interrupt.
	189	*/
	190	static int
	191	tmio_nand_wait(struct mtd_info mtd, struct nand_chip nand_chip)
	192	{
	193	struct tmio_nand *tmio = mtd_to_tmio(mtd);
	194	long timeout;
	195
	196	/* enable RDYREQ interrupt */
	197	tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR);
198	tmio_iowrite8(0x81, tmio->fcr + FCR_IMR);
199
200	timeout = wait_event_timeout(nand_chip->controller->wq,
201	tmio_nand_dev_ready(mtd),
202	msecs_to_jiffies(nand_chip->state == FL_ERASING ? 400 : 20));
203
204	if (unlikely(!tmio_nand_dev_ready(mtd))) {
205	tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
206	dev_warn(&tmio->dev->dev, "still busy with %s after %d ms\n",
207	nand_chip->state == FL_ERASING ? "erase" : "program",
208	nand_chip->state == FL_ERASING ? 400 : 20);
209
210	} else if (unlikely(!timeout)) {
211	tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
212	dev_warn(&tmio->dev->dev, "timeout waiting for interrupt\n");
213	}
214
215	nand_chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
216	return nand_chip->read_byte(mtd);
217	}
218
219	/*
220	*The TMIO controller combines two 8-bit data bytes into one 16-bit
221	*word. This function separates them so nand_base.c works as expected,
222	*especially its NAND_CMD_READID routines.
223	*
224	*To prevent stale data from being read, tmio_nand_hwcontrol() clears
225	*tmio->read_good.
226	*/
227	static u_char tmio_nand_read_byte(struct mtd_info *mtd)
228	{
229	struct tmio_nand *tmio = mtd_to_tmio(mtd);
230	unsigned int data;
231
232	if (tmio->read_good--)
233	return tmio->read;
234
235	data = tmio_ioread16(tmio->fcr + FCR_DATA);
236	tmio->read = data >> 8;
237	return data;
238	}
239
240	/*
241	*The TMIO controller converts an 8-bit NAND interface to a 16-bit
242	*bus interface, so all data reads and writes must be 16-bit wide.
243	*Thus, we implement 16-bit versions of the read, write, and verify
244	*buffer functions.
245	*/
246	static void
247	tmio_nand_write_buf(struct mtd_info mtd, const u_char buf, int len)
248	{
249	struct tmio_nand *tmio = mtd_to_tmio(mtd);
250
251	tmio_iowrite16_rep(tmio->fcr + FCR_DATA, buf, len >> 1);
252	}
253
254	static void tmio_nand_read_buf(struct mtd_info mtd, u_char buf, int len)
255	{
256	struct tmio_nand *tmio = mtd_to_tmio(mtd);
257
258	tmio_ioread16_rep(tmio->fcr + FCR_DATA, buf, len >> 1);
259	}
260
ec43b816 IM	261	static void tmio_nand_enable_hwecc(struct mtd_info *mtd, int mode)
	262	{
	263	struct tmio_nand *tmio = mtd_to_tmio(mtd);
	264
	265	tmio_iowrite8(FCR_MODE_HWECC_RESET, tmio->fcr + FCR_MODE);
	266	tmio_ioread8(tmio->fcr + FCR_DATA); /* dummy read */
	267	tmio_iowrite8(FCR_MODE_HWECC_CALC, tmio->fcr + FCR_MODE);
	268	}
	269
	270	static int tmio_nand_calculate_ecc(struct mtd_info mtd, const u_char dat,
	271	u_char *ecc_code)
	272	{
	273	struct tmio_nand *tmio = mtd_to_tmio(mtd);
	274	unsigned int ecc;
	275
	276	tmio_iowrite8(FCR_MODE_HWECC_RESULT, tmio->fcr + FCR_MODE);
	277
	278	ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
	279	ecc_code[1] = ecc; /* 000-255 LP7-0 */
	280	ecc_code[0] = ecc >> 8; /* 000-255 LP15-8 */
	281	ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
	282	ecc_code[2] = ecc; /* 000-255 CP5-0,11b */
	283	ecc_code[4] = ecc >> 8; /* 256-511 LP7-0 */
	284	ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
	285	ecc_code[3] = ecc; /* 256-511 LP15-8 */
	286	ecc_code[5] = ecc >> 8; /* 256-511 CP5-0,11b */
	287
	288	tmio_iowrite8(FCR_MODE_DATA, tmio->fcr + FCR_MODE);
	289	return 0;
	290	}
	291
0f777fb9 AN	292	static int tmio_nand_correct_data(struct mtd_info mtd, unsigned char buf,
	293	unsigned char read_ecc, unsigned char calc_ecc)
	294	{
	295	int r0, r1;
	296
	297	/* assume ecc.size = 512 and ecc.bytes = 6 */
	298	r0 = __nand_correct_data(buf, read_ecc, calc_ecc, 256);
	299	if (r0 < 0)
	300	return r0;
	301	r1 = __nand_correct_data(buf + 256, read_ecc + 3, calc_ecc + 3, 256);
	302	if (r1 < 0)
	303	return r1;
	304	return r0 + r1;
	305	}
	306
ec43b816 IM	307	static int tmio_hw_init(struct platform_device dev, struct tmio_nand tmio)
ec43b816 IM	308	{
944dc035	309	const struct mfd_cell *cell = mfd_get_cell(dev);
ec43b816 IM	310	int ret;
	311
	312	if (cell->enable) {
	313	ret = cell->enable(dev);
	314	if (ret)
	315	return ret;
	316	}
	317
	318	/* (4Ch) CLKRUN Enable 1st spcrunc */
	319	tmio_iowrite8(0x81, tmio->ccr + CCR_ICC);
	320
	321	/* (10h)BaseAddress 0x1000 spba.spba2 */
076c7f4c DB	322	tmio_iowrite16(tmio->fcr_base, tmio->ccr + CCR_BASE);
076c7f4c DB	323	tmio_iowrite16(tmio->fcr_base >> 16, tmio->ccr + CCR_BASE + 2);
ec43b816 IM	324
	325	/* (04h)Command Register I/O spcmd */
	326	tmio_iowrite8(0x02, tmio->ccr + CCR_COMMAND);
	327
	328	/* (62h) Power Supply Control ssmpwc */
	329	/* HardPowerOFF - SuspendOFF - PowerSupplyWait_4MS */
	330	tmio_iowrite8(0x02, tmio->ccr + CCR_NFPSC);
	331
	332	/* (63h) Detect Control ssmdtc */
	333	tmio_iowrite8(0x02, tmio->ccr + CCR_NFDC);
	334
	335	/* Interrupt status register clear sintst */
	336	tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR);
	337
	338	/* After power supply, Media are reset smode */
	339	tmio_iowrite8(FCR_MODE_POWER_ON, tmio->fcr + FCR_MODE);
	340	tmio_iowrite8(FCR_MODE_COMMAND, tmio->fcr + FCR_MODE);
	341	tmio_iowrite8(NAND_CMD_RESET, tmio->fcr + FCR_DATA);
	342
	343	/* Standby Mode smode */
	344	tmio_iowrite8(FCR_MODE_STANDBY, tmio->fcr + FCR_MODE);
	345
	346	mdelay(5);
	347
	348	return 0;
	349	}
	350
	351	static void tmio_hw_stop(struct platform_device dev, struct tmio_nand tmio)
	352	{
944dc035	353	const struct mfd_cell *cell = mfd_get_cell(dev);
ec43b816 IM	354
	355	tmio_iowrite8(FCR_MODE_POWER_OFF, tmio->fcr + FCR_MODE);
	356	if (cell->disable)
	357	cell->disable(dev);
	358	}
	359
	360	static int tmio_probe(struct platform_device *dev)
	361	{
453810b7	362	struct tmio_nand_data *data = dev_get_platdata(&dev->dev);
ec43b816 IM	363	struct resource *fcr = platform_get_resource(dev,
	364	IORESOURCE_MEM, 0);
	365	struct resource *ccr = platform_get_resource(dev,
	366	IORESOURCE_MEM, 1);
	367	int irq = platform_get_irq(dev, 0);
	368	struct tmio_nand *tmio;
	369	struct mtd_info *mtd;
	370	struct nand_chip *nand_chip;
ec43b816 IM	371	int retval;
	372
	373	if (data == NULL)
	374	dev_warn(&dev->dev, "NULL platform data!\n");
	375
8f91fb68 JH	376	tmio = devm_kzalloc(&dev->dev, sizeof(*tmio), GFP_KERNEL);
	377	if (!tmio)
	378	return -ENOMEM;
ec43b816 IM	379
	380	tmio->dev = dev;
	381
	382	platform_set_drvdata(dev, tmio);
ec43b816	383	nand_chip = &tmio->chip;
66c9595d	384	mtd = nand_to_mtd(nand_chip);
ec43b816	385	mtd->name = "tmio-nand";
7b679053	386	mtd->dev.parent = &dev->dev;
ec43b816	387
8f91fb68 JH	388	tmio->ccr = devm_ioremap(&dev->dev, ccr->start, resource_size(ccr));
	389	if (!tmio->ccr)
	390	return -EIO;
ec43b816	391
076c7f4c	392	tmio->fcr_base = fcr->start & 0xfffff;
8f91fb68 JH	393	tmio->fcr = devm_ioremap(&dev->dev, fcr->start, resource_size(fcr));
	394	if (!tmio->fcr)
	395	return -EIO;
ec43b816 IM	396
	397	retval = tmio_hw_init(dev, tmio);
	398	if (retval)
8f91fb68	399	return retval;
ec43b816 IM	400
	401	/* Set address of NAND IO lines */
	402	nand_chip->IO_ADDR_R = tmio->fcr;
	403	nand_chip->IO_ADDR_W = tmio->fcr;
	404
	405	/* Set address of hardware control function */
	406	nand_chip->cmd_ctrl = tmio_nand_hwcontrol;
	407	nand_chip->dev_ready = tmio_nand_dev_ready;
	408	nand_chip->read_byte = tmio_nand_read_byte;
	409	nand_chip->write_buf = tmio_nand_write_buf;
	410	nand_chip->read_buf = tmio_nand_read_buf;
ec43b816 IM	411
	412	/* set eccmode using hardware ECC */
	413	nand_chip->ecc.mode = NAND_ECC_HW;
	414	nand_chip->ecc.size = 512;
	415	nand_chip->ecc.bytes = 6;
6a918bad	416	nand_chip->ecc.strength = 2;
ec43b816 IM	417	nand_chip->ecc.hwctl = tmio_nand_enable_hwecc;
ec43b816 IM	418	nand_chip->ecc.calculate = tmio_nand_calculate_ecc;
0f777fb9	419	nand_chip->ecc.correct = tmio_nand_correct_data;
ec43b816 IM	420
	421	if (data)
	422	nand_chip->badblock_pattern = data->badblock_pattern;
	423
	424	/* 15 us command delay time */
	425	nand_chip->chip_delay = 15;
	426
8f91fb68 JH	427	retval = devm_request_irq(&dev->dev, irq, &tmio_irq, 0,
8f91fb68 JH	428	dev_name(&dev->dev), tmio);
ec43b816 IM	429	if (retval) {
	430	dev_err(&dev->dev, "request_irq error %d\n", retval);
	431	goto err_irq;
	432	}
	433
	434	tmio->irq = irq;
	435	nand_chip->waitfunc = tmio_nand_wait;
	436
	437	/* Scan to find existence of the device */
	438	if (nand_scan(mtd, 1)) {
	439	retval = -ENODEV;
8f91fb68	440	goto err_irq;
ec43b816 IM	441	}
ec43b816 IM	442	/* Register the partitions */
42d7fbe2 AB	443	retval = mtd_device_parse_register(mtd, NULL, NULL,
	444	data ? data->partition : NULL,
	445	data ? data->num_partitions : 0);
ec43b816 IM	446	if (!retval)
	447	return retval;
	448
	449	nand_release(mtd);
	450
ec43b816 IM	451	err_irq:
ec43b816 IM	452	tmio_hw_stop(dev, tmio);
ec43b816 IM	453	return retval;
	454	}
	455
	456	static int tmio_remove(struct platform_device *dev)
	457	{
	458	struct tmio_nand *tmio = platform_get_drvdata(dev);
	459
66c9595d	460	nand_release(nand_to_mtd(&tmio->chip));
ec43b816	461	tmio_hw_stop(dev, tmio);
ec43b816 IM	462	return 0;
	463	}
	464
	465	#ifdef CONFIG_PM
	466	static int tmio_suspend(struct platform_device *dev, pm_message_t state)
	467	{
944dc035	468	const struct mfd_cell *cell = mfd_get_cell(dev);
ec43b816 IM	469
	470	if (cell->suspend)
	471	cell->suspend(dev);
	472
	473	tmio_hw_stop(dev, platform_get_drvdata(dev));
	474	return 0;
	475	}
	476
	477	static int tmio_resume(struct platform_device *dev)
	478	{
944dc035	479	const struct mfd_cell *cell = mfd_get_cell(dev);
ec43b816 IM	480
	481	/* FIXME - is this required or merely another attack of the broken
	482	* SHARP platform? Looks suspicious.
	483	*/
	484	tmio_hw_init(dev, platform_get_drvdata(dev));
	485
	486	if (cell->resume)
	487	cell->resume(dev);
	488
	489	return 0;
	490	}
	491	#else
	492	#define tmio_suspend NULL
	493	#define tmio_resume NULL
	494	#endif
	495
	496	static struct platform_driver tmio_driver = {
	497	.driver.name = "tmio-nand",
	498	.driver.owner = THIS_MODULE,
	499	.probe = tmio_probe,
	500	.remove = tmio_remove,
	501	.suspend = tmio_suspend,
	502	.resume = tmio_resume,
	503	};
	504
f99640de	505	module_platform_driver(tmio_driver);
ec43b816 IM	506
	507	MODULE_LICENSE("GPL v2");
	508	MODULE_AUTHOR("Ian Molton, Dirk Opfer, Chris Humbert, Dmitry Baryshkov");
	509	MODULE_DESCRIPTION("NAND flash driver on Toshiba Mobile IO controller");
	510	MODULE_ALIAS("platform:tmio-nand");