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mtd: physmap_of: assign parent for the concatenated MTD
[deliverable/linux.git] / drivers / mtd / nand / vf610_nfc.c
CommitLineData
456930d8
SA		 1/*
2 * Copyright 2009-2015 Freescale Semiconductor, Inc. and others
3 *
4 * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
5 * Jason ported to M54418TWR and MVFA5 (VF610).
6 * Authors: Stefan Agner <stefan.agner@toradex.com>
7 * Bill Pringlemeir <bpringlemeir@nbsps.com>
8 * Shaohui Xie <b21989@freescale.com>
9 * Jason Jin <Jason.jin@freescale.com>
10 *
11 * Based on original driver mpc5121_nfc.c.
12 *
13 * This is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * Limitations:
19 * - Untested on MPC5125 and M54418.
20 * - DMA and pipelining not used.
21 * - 2K pages or less.
049f4250
SA		 22 * - HW ECC: Only 2K page with 64+ OOB.
23 * - HW ECC: Only 24 and 32-bit error correction implemented.
456930d8
SA		 24 */
25
26#include <linux/module.h>
27#include <linux/bitops.h>
28#include <linux/clk.h>
29#include <linux/delay.h>
30#include <linux/init.h>
31#include <linux/interrupt.h>
32#include <linux/io.h>
33#include <linux/mtd/mtd.h>
34#include <linux/mtd/nand.h>
35#include <linux/mtd/partitions.h>
36#include <linux/of_mtd.h>
37#include <linux/of_device.h>
039353c8 38#include <linux/pinctrl/consumer.h>
456930d8
SA		 39#include <linux/platform_device.h>
40#include <linux/slab.h>
41
42#define DRV_NAME "vf610_nfc"
43
44/* Register Offsets */
45#define NFC_FLASH_CMD1 0x3F00
46#define NFC_FLASH_CMD2 0x3F04
47#define NFC_COL_ADDR 0x3F08
48#define NFC_ROW_ADDR 0x3F0c
49#define NFC_ROW_ADDR_INC 0x3F14
50#define NFC_FLASH_STATUS1 0x3F18
51#define NFC_FLASH_STATUS2 0x3F1c
52#define NFC_CACHE_SWAP 0x3F28
53#define NFC_SECTOR_SIZE 0x3F2c
54#define NFC_FLASH_CONFIG 0x3F30
55#define NFC_IRQ_STATUS 0x3F38
56
57/* Addresses for NFC MAIN RAM BUFFER areas */
58#define NFC_MAIN_AREA(n) ((n) * 0x1000)
59
60#define PAGE_2K 0x0800
61#define OOB_64 0x0040
62#define OOB_MAX 0x0100
63
64/*
65 * NFC_CMD2[CODE] values. See section:
66 * - 31.4.7 Flash Command Code Description, Vybrid manual
67 * - 23.8.6 Flash Command Sequencer, MPC5125 manual
68 *
69 * Briefly these are bitmasks of controller cycles.
70 */
71#define READ_PAGE_CMD_CODE 0x7EE0
72#define READ_ONFI_PARAM_CMD_CODE 0x4860
73#define PROGRAM_PAGE_CMD_CODE 0x7FC0
74#define ERASE_CMD_CODE 0x4EC0
75#define READ_ID_CMD_CODE 0x4804
76#define RESET_CMD_CODE 0x4040
77#define STATUS_READ_CMD_CODE 0x4068
78
79/* NFC ECC mode define */
80#define ECC_BYPASS 0
049f4250
SA		 81#define ECC_45_BYTE 6
82#define ECC_60_BYTE 7
456930d8
SA		 83
84/*** Register Mask and bit definitions */
85
86/* NFC_FLASH_CMD1 Field */
87#define CMD_BYTE2_MASK 0xFF000000
88#define CMD_BYTE2_SHIFT 24
89
90/* NFC_FLASH_CM2 Field */
91#define CMD_BYTE1_MASK 0xFF000000
92#define CMD_BYTE1_SHIFT 24
93#define CMD_CODE_MASK 0x00FFFF00
94#define CMD_CODE_SHIFT 8
95#define BUFNO_MASK 0x00000006
96#define BUFNO_SHIFT 1
97#define START_BIT BIT(0)
98
99/* NFC_COL_ADDR Field */
100#define COL_ADDR_MASK 0x0000FFFF
101#define COL_ADDR_SHIFT 0
102
103/* NFC_ROW_ADDR Field */
104#define ROW_ADDR_MASK 0x00FFFFFF
105#define ROW_ADDR_SHIFT 0
106#define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000
107#define ROW_ADDR_CHIP_SEL_RB_SHIFT 28
108#define ROW_ADDR_CHIP_SEL_MASK 0x0F000000
109#define ROW_ADDR_CHIP_SEL_SHIFT 24
110
111/* NFC_FLASH_STATUS2 Field */
112#define STATUS_BYTE1_MASK 0x000000FF
113
114/* NFC_FLASH_CONFIG Field */
115#define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000
116#define CONFIG_ECC_SRAM_ADDR_SHIFT 22
117#define CONFIG_ECC_SRAM_REQ_BIT BIT(21)
118#define CONFIG_DMA_REQ_BIT BIT(20)
119#define CONFIG_ECC_MODE_MASK 0x000E0000
120#define CONFIG_ECC_MODE_SHIFT 17
121#define CONFIG_FAST_FLASH_BIT BIT(16)
122#define CONFIG_16BIT BIT(7)
123#define CONFIG_BOOT_MODE_BIT BIT(6)
124#define CONFIG_ADDR_AUTO_INCR_BIT BIT(5)
125#define CONFIG_BUFNO_AUTO_INCR_BIT BIT(4)
126#define CONFIG_PAGE_CNT_MASK 0xF
127#define CONFIG_PAGE_CNT_SHIFT 0
128
129/* NFC_IRQ_STATUS Field */
130#define IDLE_IRQ_BIT BIT(29)
131#define IDLE_EN_BIT BIT(20)
132#define CMD_DONE_CLEAR_BIT BIT(18)
133#define IDLE_CLEAR_BIT BIT(17)
134
049f4250
SA		 135/*
136 * ECC status - seems to consume 8 bytes (double word). The documented
137 * status byte is located in the lowest byte of the second word (which is
138 * the 4th or 7th byte depending on endianness).
139 * Calculate an offset to store the ECC status at the end of the buffer.
140 */
141#define ECC_SRAM_ADDR (PAGE_2K + OOB_MAX - 8)
142
143#define ECC_STATUS 0x4
144#define ECC_STATUS_MASK 0x80
145#define ECC_STATUS_ERR_COUNT 0x3F
146
456930d8
SA		 147enum vf610_nfc_alt_buf {
148 ALT_BUF_DATA = 0,
149 ALT_BUF_ID = 1,
150 ALT_BUF_STAT = 2,
151 ALT_BUF_ONFI = 3,
152};
153
154enum vf610_nfc_variant {
155 NFC_VFC610 = 1,
156};
157
158struct vf610_nfc {
159 struct mtd_info mtd;
160 struct nand_chip chip;
161 struct device *dev;
162 void __iomem *regs;
163 struct completion cmd_done;
164 uint buf_offset;
165 int write_sz;
166 /* Status and ID are in alternate locations. */
167 enum vf610_nfc_alt_buf alt_buf;
168 enum vf610_nfc_variant variant;
169 struct clk *clk;
049f4250
SA		 170 bool use_hw_ecc;
171 u32 ecc_mode;
456930d8
SA		 172};
173
174#define mtd_to_nfc(_mtd) container_of(_mtd, struct vf610_nfc, mtd)
175
049f4250
SA		 176static struct nand_ecclayout vf610_nfc_ecc45 = {
177 .eccbytes = 45,
178 .eccpos = {19, 20, 21, 22, 23,
179 24, 25, 26, 27, 28, 29, 30, 31,
180 32, 33, 34, 35, 36, 37, 38, 39,
181 40, 41, 42, 43, 44, 45, 46, 47,
182 48, 49, 50, 51, 52, 53, 54, 55,
183 56, 57, 58, 59, 60, 61, 62, 63},
184 .oobfree = {
185 {.offset = 2,
186 .length = 17} }
187};
188
189static struct nand_ecclayout vf610_nfc_ecc60 = {
190 .eccbytes = 60,
191 .eccpos = { 4, 5, 6, 7, 8, 9, 10, 11,
192 12, 13, 14, 15, 16, 17, 18, 19,
193 20, 21, 22, 23, 24, 25, 26, 27,
194 28, 29, 30, 31, 32, 33, 34, 35,
195 36, 37, 38, 39, 40, 41, 42, 43,
196 44, 45, 46, 47, 48, 49, 50, 51,
197 52, 53, 54, 55, 56, 57, 58, 59,
198 60, 61, 62, 63 },
199 .oobfree = {
200 {.offset = 2,
201 .length = 2} }
202};
203
456930d8
SA		 204static inline u32 vf610_nfc_read(struct vf610_nfc *nfc, uint reg)
205{
206 return readl(nfc->regs + reg);
207}
208
209static inline void vf610_nfc_write(struct vf610_nfc *nfc, uint reg, u32 val)
210{
211 writel(val, nfc->regs + reg);
212}
213
214static inline void vf610_nfc_set(struct vf610_nfc *nfc, uint reg, u32 bits)
215{
216 vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) | bits);
217}
218
219static inline void vf610_nfc_clear(struct vf610_nfc *nfc, uint reg, u32 bits)
220{
221 vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) & ~bits);
222}
223
224static inline void vf610_nfc_set_field(struct vf610_nfc *nfc, u32 reg,
225 u32 mask, u32 shift, u32 val)
226{
227 vf610_nfc_write(nfc, reg,
228 (vf610_nfc_read(nfc, reg) & (~mask)) | val << shift);
229}
230
231static inline void vf610_nfc_memcpy(void *dst, const void __iomem *src,
232 size_t n)
233{
234 /*
235 * Use this accessor for the internal SRAM buffers. On the ARM
236 * Freescale Vybrid SoC it's known that the driver can treat
237 * the SRAM buffer as if it's memory. Other platform might need
238 * to treat the buffers differently.
239 *
240 * For the time being, use memcpy
241 */
242 memcpy(dst, src, n);
243}
244
245/* Clear flags for upcoming command */
246static inline void vf610_nfc_clear_status(struct vf610_nfc *nfc)
247{
248 u32 tmp = vf610_nfc_read(nfc, NFC_IRQ_STATUS);
249
250 tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT;
251 vf610_nfc_write(nfc, NFC_IRQ_STATUS, tmp);
252}
253
254static void vf610_nfc_done(struct vf610_nfc *nfc)
255{
256 unsigned long timeout = msecs_to_jiffies(100);
257
258 /*
259 * Barrier is needed after this write. This write need
260 * to be done before reading the next register the first
261 * time.
262 * vf610_nfc_set implicates such a barrier by using writel
263 * to write to the register.
264 */
265 vf610_nfc_set(nfc, NFC_IRQ_STATUS, IDLE_EN_BIT);
266 vf610_nfc_set(nfc, NFC_FLASH_CMD2, START_BIT);
267
268 if (!wait_for_completion_timeout(&nfc->cmd_done, timeout))
269 dev_warn(nfc->dev, "Timeout while waiting for BUSY.\n");
270
271 vf610_nfc_clear_status(nfc);
272}
273
274static u8 vf610_nfc_get_id(struct vf610_nfc *nfc, int col)
275{
276 u32 flash_id;
277
278 if (col < 4) {
279 flash_id = vf610_nfc_read(nfc, NFC_FLASH_STATUS1);
280 flash_id >>= (3 - col) * 8;
281 } else {
282 flash_id = vf610_nfc_read(nfc, NFC_FLASH_STATUS2);
283 flash_id >>= 24;
284 }
285
286 return flash_id & 0xff;
287}
288
289static u8 vf610_nfc_get_status(struct vf610_nfc *nfc)
290{
291 return vf610_nfc_read(nfc, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK;
292}
293
294static void vf610_nfc_send_command(struct vf610_nfc *nfc, u32 cmd_byte1,
295 u32 cmd_code)
296{
297 u32 tmp;
298
299 vf610_nfc_clear_status(nfc);
300
301 tmp = vf610_nfc_read(nfc, NFC_FLASH_CMD2);
302 tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK);
303 tmp |= cmd_byte1 << CMD_BYTE1_SHIFT;
304 tmp |= cmd_code << CMD_CODE_SHIFT;
305 vf610_nfc_write(nfc, NFC_FLASH_CMD2, tmp);
306}
307
308static void vf610_nfc_send_commands(struct vf610_nfc *nfc, u32 cmd_byte1,
309 u32 cmd_byte2, u32 cmd_code)
310{
311 u32 tmp;
312
313 vf610_nfc_send_command(nfc, cmd_byte1, cmd_code);
314
315 tmp = vf610_nfc_read(nfc, NFC_FLASH_CMD1);
316 tmp &= ~CMD_BYTE2_MASK;
317 tmp |= cmd_byte2 << CMD_BYTE2_SHIFT;
318 vf610_nfc_write(nfc, NFC_FLASH_CMD1, tmp);
319}
320
321static irqreturn_t vf610_nfc_irq(int irq, void *data)
322{
323 struct mtd_info *mtd = data;
324 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
325
326 vf610_nfc_clear(nfc, NFC_IRQ_STATUS, IDLE_EN_BIT);
327 complete(&nfc->cmd_done);
328
329 return IRQ_HANDLED;
330}
331
332static void vf610_nfc_addr_cycle(struct vf610_nfc *nfc, int column, int page)
333{
334 if (column != -1) {
335 if (nfc->chip.options & NAND_BUSWIDTH_16)
336 column = column / 2;
337 vf610_nfc_set_field(nfc, NFC_COL_ADDR, COL_ADDR_MASK,
338 COL_ADDR_SHIFT, column);
339 }
340 if (page != -1)
341 vf610_nfc_set_field(nfc, NFC_ROW_ADDR, ROW_ADDR_MASK,
342 ROW_ADDR_SHIFT, page);
343}
344
049f4250
SA		 345static inline void vf610_nfc_ecc_mode(struct vf610_nfc *nfc, int ecc_mode)
346{
347 vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG,
348 CONFIG_ECC_MODE_MASK,
349 CONFIG_ECC_MODE_SHIFT, ecc_mode);
350}
351
456930d8
SA		 352static inline void vf610_nfc_transfer_size(struct vf610_nfc *nfc, int size)
353{
354 vf610_nfc_write(nfc, NFC_SECTOR_SIZE, size);
355}
356
357static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
358 int column, int page)
359{
360 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
361 int trfr_sz = nfc->chip.options & NAND_BUSWIDTH_16 ? 1 : 0;
362
363 nfc->buf_offset = max(column, 0);
364 nfc->alt_buf = ALT_BUF_DATA;
365
366 switch (command) {
367 case NAND_CMD_SEQIN:
368 /* Use valid column/page from preread... */
369 vf610_nfc_addr_cycle(nfc, column, page);
049f4250
SA		 370 nfc->buf_offset = 0;
371
456930d8
SA		 372 /*
373 * SEQIN => data => PAGEPROG sequence is done by the controller
374 * hence we do not need to issue the command here...
375 */
376 return;
377 case NAND_CMD_PAGEPROG:
378 trfr_sz += nfc->write_sz;
379 vf610_nfc_transfer_size(nfc, trfr_sz);
380 vf610_nfc_send_commands(nfc, NAND_CMD_SEQIN,
381 command, PROGRAM_PAGE_CMD_CODE);
049f4250
SA		 382 if (nfc->use_hw_ecc)
383 vf610_nfc_ecc_mode(nfc, nfc->ecc_mode);
384 else
385 vf610_nfc_ecc_mode(nfc, ECC_BYPASS);
456930d8
SA		 386 break;
387
388 case NAND_CMD_RESET:
389 vf610_nfc_transfer_size(nfc, 0);
390 vf610_nfc_send_command(nfc, command, RESET_CMD_CODE);
391 break;
392
393 case NAND_CMD_READOOB:
394 trfr_sz += mtd->oobsize;
395 column = mtd->writesize;
396 vf610_nfc_transfer_size(nfc, trfr_sz);
397 vf610_nfc_send_commands(nfc, NAND_CMD_READ0,
398 NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
399 vf610_nfc_addr_cycle(nfc, column, page);
049f4250 400 vf610_nfc_ecc_mode(nfc, ECC_BYPASS);
456930d8
SA		 401 break;
402
403 case NAND_CMD_READ0:
404 trfr_sz += mtd->writesize + mtd->oobsize;
405 vf610_nfc_transfer_size(nfc, trfr_sz);
406 vf610_nfc_send_commands(nfc, NAND_CMD_READ0,
407 NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
408 vf610_nfc_addr_cycle(nfc, column, page);
049f4250 409 vf610_nfc_ecc_mode(nfc, nfc->ecc_mode);
456930d8
SA		 410 break;
411
412 case NAND_CMD_PARAM:
413 nfc->alt_buf = ALT_BUF_ONFI;
414 trfr_sz = 3 * sizeof(struct nand_onfi_params);
415 vf610_nfc_transfer_size(nfc, trfr_sz);
416 vf610_nfc_send_command(nfc, command, READ_ONFI_PARAM_CMD_CODE);
417 vf610_nfc_addr_cycle(nfc, -1, column);
049f4250 418 vf610_nfc_ecc_mode(nfc, ECC_BYPASS);
456930d8
SA		 419 break;
420
421 case NAND_CMD_ERASE1:
422 vf610_nfc_transfer_size(nfc, 0);
423 vf610_nfc_send_commands(nfc, command,
424 NAND_CMD_ERASE2, ERASE_CMD_CODE);
425 vf610_nfc_addr_cycle(nfc, column, page);
426 break;
427
428 case NAND_CMD_READID:
429 nfc->alt_buf = ALT_BUF_ID;
430 nfc->buf_offset = 0;
431 vf610_nfc_transfer_size(nfc, 0);
432 vf610_nfc_send_command(nfc, command, READ_ID_CMD_CODE);
433 vf610_nfc_addr_cycle(nfc, -1, column);
434 break;
435
436 case NAND_CMD_STATUS:
437 nfc->alt_buf = ALT_BUF_STAT;
438 vf610_nfc_transfer_size(nfc, 0);
439 vf610_nfc_send_command(nfc, command, STATUS_READ_CMD_CODE);
440 break;
441 default:
442 return;
443 }
444
445 vf610_nfc_done(nfc);
446
049f4250 447 nfc->use_hw_ecc = false;
456930d8
SA		 448 nfc->write_sz = 0;
449}
450
451static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
452{
453 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
454 uint c = nfc->buf_offset;
455
456 /* Alternate buffers are only supported through read_byte */
457 WARN_ON(nfc->alt_buf);
458
459 vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, len);
460
461 nfc->buf_offset += len;
462}
463
464static void vf610_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
465 int len)
466{
467 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
468 uint c = nfc->buf_offset;
469 uint l;
470
471 l = min_t(uint, len, mtd->writesize + mtd->oobsize - c);
472 vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l);
473
474 nfc->write_sz += l;
475 nfc->buf_offset += l;
476}
477
478static uint8_t vf610_nfc_read_byte(struct mtd_info *mtd)
479{
480 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
481 u8 tmp;
482 uint c = nfc->buf_offset;
483
484 switch (nfc->alt_buf) {
485 case ALT_BUF_ID:
486 tmp = vf610_nfc_get_id(nfc, c);
487 break;
488 case ALT_BUF_STAT:
489 tmp = vf610_nfc_get_status(nfc);
490 break;
491#ifdef __LITTLE_ENDIAN
492 case ALT_BUF_ONFI:
493 /* Reverse byte since the controller uses big endianness */
494 c = nfc->buf_offset ^ 0x3;
495 /* fall-through */
496#endif
497 default:
498 tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c));
499 break;
500 }
501 nfc->buf_offset++;
502 return tmp;
503}
504
505static u16 vf610_nfc_read_word(struct mtd_info *mtd)
506{
507 u16 tmp;
508
509 vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
510 return tmp;
511}
512
513/* If not provided, upper layers apply a fixed delay. */
514static int vf610_nfc_dev_ready(struct mtd_info *mtd)
515{
516 /* NFC handles R/B internally; always ready. */
517 return 1;
518}
519
520/*
521 * This function supports Vybrid only (MPC5125 would have full RB and four CS)
522 */
523static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip)
524{
525 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
526 u32 tmp = vf610_nfc_read(nfc, NFC_ROW_ADDR);
527
528 /* Vybrid only (MPC5125 would have full RB and four CS) */
529 if (nfc->variant != NFC_VFC610)
530 return;
531
532 tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK);
533
534 if (chip >= 0) {
535 tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT;
536 tmp |= BIT(chip) << ROW_ADDR_CHIP_SEL_SHIFT;
537 }
538
539 vf610_nfc_write(nfc, NFC_ROW_ADDR, tmp);
540}
541
049f4250
SA		 542/* Count the number of 0's in buff up to max_bits */
543static inline int count_written_bits(uint8_t *buff, int size, int max_bits)
544{
545 uint32_t *buff32 = (uint32_t *)buff;
546 int k, written_bits = 0;
547
548 for (k = 0; k < (size / 4); k++) {
549 written_bits += hweight32(~buff32[k]);
550 if (unlikely(written_bits > max_bits))
551 break;
552 }
553
554 return written_bits;
555}
556
557static inline int vf610_nfc_correct_data(struct mtd_info *mtd, uint8_t *dat,
558 uint8_t *oob, int page)
559{
560 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
561 u32 ecc_status_off = NFC_MAIN_AREA(0) + ECC_SRAM_ADDR + ECC_STATUS;
562 u8 ecc_status;
563 u8 ecc_count;
049f4250
SA		 564 int flips_threshold = nfc->chip.ecc.strength / 2;
565
566 ecc_status = vf610_nfc_read(nfc, ecc_status_off) & 0xff;
567 ecc_count = ecc_status & ECC_STATUS_ERR_COUNT;
568
569 if (!(ecc_status & ECC_STATUS_MASK))
570 return ecc_count;
571
572 /* Read OOB without ECC unit enabled */
573 vf610_nfc_command(mtd, NAND_CMD_READOOB, 0, page);
574 vf610_nfc_read_buf(mtd, oob, mtd->oobsize);
575
576 /*
577 * On an erased page, bit count (including OOB) should be zero or
578 * at least less then half of the ECC strength.
579 */
48c25cf4
BN		 580 return nand_check_erased_ecc_chunk(dat, nfc->chip.ecc.size, oob,
581 mtd->oobsize, NULL, 0,
582 flips_threshold);
049f4250
SA		 583}
584
585static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
586 uint8_t *buf, int oob_required, int page)
587{
588 int eccsize = chip->ecc.size;
589 int stat;
590
591 vf610_nfc_read_buf(mtd, buf, eccsize);
592 if (oob_required)
593 vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
594
595 stat = vf610_nfc_correct_data(mtd, buf, chip->oob_poi, page);
596
597 if (stat < 0) {
598 mtd->ecc_stats.failed++;
599 return 0;
600 } else {
601 mtd->ecc_stats.corrected += stat;
602 return stat;
603 }
604}
605
606static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
45aaeff9 607 const uint8_t *buf, int oob_required, int page)
049f4250
SA		 608{
609 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
610
611 vf610_nfc_write_buf(mtd, buf, mtd->writesize);
612 if (oob_required)
613 vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
614
615 /* Always write whole page including OOB due to HW ECC */
616 nfc->use_hw_ecc = true;
617 nfc->write_sz = mtd->writesize + mtd->oobsize;
618
619 return 0;
620}
621
456930d8
SA		 622static const struct of_device_id vf610_nfc_dt_ids[] = {
623 { .compatible = "fsl,vf610-nfc", .data = (void *)NFC_VFC610 },
624 { /* sentinel */ }
625};
626MODULE_DEVICE_TABLE(of, vf610_nfc_dt_ids);
627
628static void vf610_nfc_preinit_controller(struct vf610_nfc *nfc)
629{
630 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
631 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
632 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
633 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
634 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
635 vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
636
637 /* Disable virtual pages, only one elementary transfer unit */
638 vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
639 CONFIG_PAGE_CNT_SHIFT, 1);
640}
641
642static void vf610_nfc_init_controller(struct vf610_nfc *nfc)
643{
644 if (nfc->chip.options & NAND_BUSWIDTH_16)
645 vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
646 else
647 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
049f4250
SA		 648
649 if (nfc->chip.ecc.mode == NAND_ECC_HW) {
650 /* Set ECC status offset in SRAM */
651 vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG,
652 CONFIG_ECC_SRAM_ADDR_MASK,
653 CONFIG_ECC_SRAM_ADDR_SHIFT,
654 ECC_SRAM_ADDR >> 3);
655
656 /* Enable ECC status in SRAM */
657 vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
658 }
456930d8
SA		 659}
660
661static int vf610_nfc_probe(struct platform_device *pdev)
662{
663 struct vf610_nfc *nfc;
664 struct resource *res;
665 struct mtd_info *mtd;
666 struct nand_chip *chip;
667 struct device_node *child;
668 const struct of_device_id *of_id;
669 int err;
670 int irq;
671
672 nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL);
673 if (!nfc)
674 return -ENOMEM;
675
676 nfc->dev = &pdev->dev;
677 mtd = &nfc->mtd;
678 chip = &nfc->chip;
679
680 mtd->priv = chip;
681 mtd->owner = THIS_MODULE;
682 mtd->dev.parent = nfc->dev;
683 mtd->name = DRV_NAME;
684
685 irq = platform_get_irq(pdev, 0);
686 if (irq <= 0)
687 return -EINVAL;
688
689 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
690 nfc->regs = devm_ioremap_resource(nfc->dev, res);
691 if (IS_ERR(nfc->regs))
692 return PTR_ERR(nfc->regs);
693
694 nfc->clk = devm_clk_get(&pdev->dev, NULL);
695 if (IS_ERR(nfc->clk))
696 return PTR_ERR(nfc->clk);
697
698 err = clk_prepare_enable(nfc->clk);
699 if (err) {
700 dev_err(nfc->dev, "Unable to enable clock!\n");
701 return err;
702 }
703
704 of_id = of_match_device(vf610_nfc_dt_ids, &pdev->dev);
705 nfc->variant = (enum vf610_nfc_variant)of_id->data;
706
707 for_each_available_child_of_node(nfc->dev->of_node, child) {
708 if (of_device_is_compatible(child, "fsl,vf610-nfc-nandcs")) {
709
710 if (chip->flash_node) {
711 dev_err(nfc->dev,
712 "Only one NAND chip supported!\n");
713 err = -EINVAL;
714 goto error;
715 }
716
63752199 717 nand_set_flash_node(chip, child);
456930d8
SA		 718 }
719 }
720
721 if (!chip->flash_node) {
722 dev_err(nfc->dev, "NAND chip sub-node missing!\n");
723 err = -ENODEV;
724 goto err_clk;
725 }
726
727 chip->dev_ready = vf610_nfc_dev_ready;
728 chip->cmdfunc = vf610_nfc_command;
729 chip->read_byte = vf610_nfc_read_byte;
730 chip->read_word = vf610_nfc_read_word;
731 chip->read_buf = vf610_nfc_read_buf;
732 chip->write_buf = vf610_nfc_write_buf;
733 chip->select_chip = vf610_nfc_select_chip;
734
735 chip->options |= NAND_NO_SUBPAGE_WRITE;
736
737 init_completion(&nfc->cmd_done);
738
739 err = devm_request_irq(nfc->dev, irq, vf610_nfc_irq, 0, DRV_NAME, mtd);
740 if (err) {
741 dev_err(nfc->dev, "Error requesting IRQ!\n");
742 goto error;
743 }
744
745 vf610_nfc_preinit_controller(nfc);
746
747 /* first scan to find the device and get the page size */
748 if (nand_scan_ident(mtd, 1, NULL)) {
749 err = -ENXIO;
750 goto error;
751 }
752
753 vf610_nfc_init_controller(nfc);
754
755 /* Bad block options. */
756 if (chip->bbt_options & NAND_BBT_USE_FLASH)
757 chip->bbt_options |= NAND_BBT_NO_OOB;
758
759 /* Single buffer only, max 256 OOB minus ECC status */
760 if (mtd->writesize + mtd->oobsize > PAGE_2K + OOB_MAX - 8) {
761 dev_err(nfc->dev, "Unsupported flash page size\n");
762 err = -ENXIO;
763 goto error;
764 }
765
049f4250
SA		 766 if (chip->ecc.mode == NAND_ECC_HW) {
767 if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
768 dev_err(nfc->dev, "Unsupported flash with hwecc\n");
769 err = -ENXIO;
770 goto error;
771 }
772
773 if (chip->ecc.size != mtd->writesize) {
774 dev_err(nfc->dev, "Step size needs to be page size\n");
775 err = -ENXIO;
776 goto error;
777 }
778
779 /* Only 64 byte ECC layouts known */
780 if (mtd->oobsize > 64)
781 mtd->oobsize = 64;
782
783 if (chip->ecc.strength == 32) {
784 nfc->ecc_mode = ECC_60_BYTE;
785 chip->ecc.bytes = 60;
786 chip->ecc.layout = &vf610_nfc_ecc60;
787 } else if (chip->ecc.strength == 24) {
788 nfc->ecc_mode = ECC_45_BYTE;
789 chip->ecc.bytes = 45;
790 chip->ecc.layout = &vf610_nfc_ecc45;
791 } else {
792 dev_err(nfc->dev, "Unsupported ECC strength\n");
793 err = -ENXIO;
794 goto error;
795 }
796
797 /* propagate ecc.layout to mtd_info */
798 mtd->ecclayout = chip->ecc.layout;
799 chip->ecc.read_page = vf610_nfc_read_page;
800 chip->ecc.write_page = vf610_nfc_write_page;
801
802 chip->ecc.size = PAGE_2K;
803 }
804
456930d8
SA		 805 /* second phase scan */
806 if (nand_scan_tail(mtd)) {
807 err = -ENXIO;
808 goto error;
809 }
810
811 platform_set_drvdata(pdev, mtd);
812
813 /* Register device in MTD */
a61ae81a 814 return mtd_device_register(mtd, NULL, 0);
456930d8
SA		 815
816error:
817 of_node_put(chip->flash_node);
818err_clk:
819 clk_disable_unprepare(nfc->clk);
820 return err;
821}
822
823static int vf610_nfc_remove(struct platform_device *pdev)
824{
825 struct mtd_info *mtd = platform_get_drvdata(pdev);
826 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
827
828 nand_release(mtd);
829 clk_disable_unprepare(nfc->clk);
830 return 0;
831}
832
833#ifdef CONFIG_PM_SLEEP
834static int vf610_nfc_suspend(struct device *dev)
835{
836 struct mtd_info *mtd = dev_get_drvdata(dev);
837 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
838
839 clk_disable_unprepare(nfc->clk);
840 return 0;
841}
842
843static int vf610_nfc_resume(struct device *dev)
844{
845 struct mtd_info *mtd = dev_get_drvdata(dev);
846 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
847
848 pinctrl_pm_select_default_state(dev);
849
850 clk_prepare_enable(nfc->clk);
851
852 vf610_nfc_preinit_controller(nfc);
853 vf610_nfc_init_controller(nfc);
854 return 0;
855}
856#endif
857
858static SIMPLE_DEV_PM_OPS(vf610_nfc_pm_ops, vf610_nfc_suspend, vf610_nfc_resume);
859
860static struct platform_driver vf610_nfc_driver = {
861 .driver = {
862 .name = DRV_NAME,
863 .of_match_table = vf610_nfc_dt_ids,
864 .pm = &vf610_nfc_pm_ops,
865 },
866 .probe = vf610_nfc_probe,
867 .remove = vf610_nfc_remove,
868};
869
870module_platform_driver(vf610_nfc_driver);
871
872MODULE_AUTHOR("Stefan Agner <stefan.agner@toradex.com>");
873MODULE_DESCRIPTION("Freescale VF610/MPC5125 NFC MTD NAND driver");
874MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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