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ARM: omap: move platform_data definitions
[deliverable/linux.git] / drivers / mtd / onenand / omap2.c
CommitLineData
36cd4fb5
AH		 1/*
2 * linux/drivers/mtd/onenand/omap2.c
3 *
4 * OneNAND driver for OMAP2 / OMAP3
5 *
6 * Copyright © 2005-2006 Nokia Corporation
7 *
8 * Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjölä
9 * IRQ and DMA support written by Timo Teras
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published by
13 * the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along with
21 * this program; see the file COPYING. If not, write to the Free Software
22 * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 *
24 */
25
26#include <linux/device.h>
27#include <linux/module.h>
28#include <linux/init.h>
29#include <linux/mtd/mtd.h>
30#include <linux/mtd/onenand.h>
31#include <linux/mtd/partitions.h>
32#include <linux/platform_device.h>
33#include <linux/interrupt.h>
34#include <linux/delay.h>
cbbd6956
AH		 35#include <linux/dma-mapping.h>
36#include <linux/io.h>
5a0e3ad6 37#include <linux/slab.h>
9ac4e613 38#include <linux/regulator/consumer.h>
36cd4fb5 39
36cd4fb5 40#include <asm/mach/flash.h>
ce491cf8 41#include <plat/gpmc.h>
2203747c 42#include <linux/platform_data/mtd-onenand-omap2.h>
1bc857f7 43#include <asm/gpio.h>
36cd4fb5 44
ce491cf8 45#include <plat/dma.h>
7d7e1eba 46#include <plat/cpu.h>
36cd4fb5 47
36cd4fb5
AH		 48#define DRIVER_NAME "omap2-onenand"
49
36cd4fb5
AH		 50#define ONENAND_BUFRAM_SIZE (1024 * 5)
51
52struct omap2_onenand {
53 struct platform_device *pdev;
54 int gpmc_cs;
55 unsigned long phys_base;
d65ccb6d 56 unsigned int mem_size;
36cd4fb5
AH		 57 int gpio_irq;
58 struct mtd_info mtd;
36cd4fb5
AH		 59 struct onenand_chip onenand;
60 struct completion irq_done;
61 struct completion dma_done;
62 int dma_channel;
63 int freq;
3ad2d861 64 int (*setup)(void __iomem *base, int *freq_ptr);
9ac4e613 65 struct regulator *regulator;
36cd4fb5
AH		 66};
67
68static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data)
69{
70 struct omap2_onenand *c = data;
71
72 complete(&c->dma_done);
73}
74
75static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
76{
77 struct omap2_onenand *c = dev_id;
78
79 complete(&c->irq_done);
80
81 return IRQ_HANDLED;
82}
83
84static inline unsigned short read_reg(struct omap2_onenand *c, int reg)
85{
86 return readw(c->onenand.base + reg);
87}
88
89static inline void write_reg(struct omap2_onenand *c, unsigned short value,
90 int reg)
91{
92 writew(value, c->onenand.base + reg);
93}
94
95static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr)
96{
97 printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
98 msg, state, ctrl, intr);
99}
100
101static void wait_warn(char *msg, int state, unsigned int ctrl,
102 unsigned int intr)
103{
104 printk(KERN_WARNING "onenand_wait: %s! state %d ctrl 0x%04x "
105 "intr 0x%04x\n", msg, state, ctrl, intr);
106}
107
108static int omap2_onenand_wait(struct mtd_info *mtd, int state)
109{
110 struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
d19d7b46 111 struct onenand_chip *this = mtd->priv;
36cd4fb5 112 unsigned int intr = 0;
d19d7b46 113 unsigned int ctrl, ctrl_mask;
36cd4fb5
AH		 114 unsigned long timeout;
115 u32 syscfg;
116
72073027
MK		 117 if (state == FL_RESETING || state == FL_PREPARING_ERASE ||
118 state == FL_VERIFYING_ERASE) {
119 int i = 21;
120 unsigned int intr_flags = ONENAND_INT_MASTER;
121
122 switch (state) {
123 case FL_RESETING:
124 intr_flags |= ONENAND_INT_RESET;
125 break;
126 case FL_PREPARING_ERASE:
127 intr_flags |= ONENAND_INT_ERASE;
128 break;
129 case FL_VERIFYING_ERASE:
130 i = 101;
131 break;
132 }
36cd4fb5 133
72073027 134 while (--i) {
36cd4fb5
AH		 135 udelay(1);
136 intr = read_reg(c, ONENAND_REG_INTERRUPT);
137 if (intr & ONENAND_INT_MASTER)
138 break;
139 }
140 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
141 if (ctrl & ONENAND_CTRL_ERROR) {
142 wait_err("controller error", state, ctrl, intr);
143 return -EIO;
144 }
c497dd55
RT		 145 if ((intr & intr_flags) == intr_flags)
146 return 0;
147 /* Continue in wait for interrupt branch */
36cd4fb5
AH		 148 }
149
150 if (state != FL_READING) {
151 int result;
152
153 /* Turn interrupts on */
154 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
782b7a36
AH		 155 if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) {
156 syscfg |= ONENAND_SYS_CFG1_IOBE;
157 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
158 if (cpu_is_omap34xx())
159 /* Add a delay to let GPIO settle */
160 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
161 }
36cd4fb5
AH		 162
163 INIT_COMPLETION(c->irq_done);
164 if (c->gpio_irq) {
0b84b5ca 165 result = gpio_get_value(c->gpio_irq);
36cd4fb5
AH		 166 if (result == -1) {
167 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
168 intr = read_reg(c, ONENAND_REG_INTERRUPT);
169 wait_err("gpio error", state, ctrl, intr);
170 return -EIO;
171 }
172 } else
173 result = 0;
174 if (result == 0) {
175 int retry_cnt = 0;
176retry:
177 result = wait_for_completion_timeout(&c->irq_done,
178 msecs_to_jiffies(20));
179 if (result == 0) {
180 /* Timeout after 20ms */
181 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
d19d7b46
RT		 182 if (ctrl & ONENAND_CTRL_ONGO &&
183 !this->ongoing) {
36cd4fb5
AH		 184 /*
185 * The operation seems to be still going
186 * so give it some more time.
187 */
188 retry_cnt += 1;
189 if (retry_cnt < 3)
190 goto retry;
191 intr = read_reg(c,
192 ONENAND_REG_INTERRUPT);
193 wait_err("timeout", state, ctrl, intr);
194 return -EIO;
195 }
196 intr = read_reg(c, ONENAND_REG_INTERRUPT);
197 if ((intr & ONENAND_INT_MASTER) == 0)
198 wait_warn("timeout", state, ctrl, intr);
199 }
200 }
201 } else {
8afbc114
AH		 202 int retry_cnt = 0;
203
36cd4fb5
AH		 204 /* Turn interrupts off */
205 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
206 syscfg &= ~ONENAND_SYS_CFG1_IOBE;
207 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
208
209 timeout = jiffies + msecs_to_jiffies(20);
8afbc114
AH		 210 while (1) {
211 if (time_before(jiffies, timeout)) {
212 intr = read_reg(c, ONENAND_REG_INTERRUPT);
213 if (intr & ONENAND_INT_MASTER)
214 break;
215 } else {
216 /* Timeout after 20ms */
217 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
218 if (ctrl & ONENAND_CTRL_ONGO) {
219 /*
220 * The operation seems to be still going
221 * so give it some more time.
222 */
223 retry_cnt += 1;
224 if (retry_cnt < 3) {
225 timeout = jiffies +
226 msecs_to_jiffies(20);
227 continue;
228 }
229 }
36cd4fb5 230 break;
8afbc114 231 }
36cd4fb5
AH		 232 }
233 }
234
235 intr = read_reg(c, ONENAND_REG_INTERRUPT);
236 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
237
238 if (intr & ONENAND_INT_READ) {
239 int ecc = read_reg(c, ONENAND_REG_ECC_STATUS);
240
241 if (ecc) {
242 unsigned int addr1, addr8;
243
244 addr1 = read_reg(c, ONENAND_REG_START_ADDRESS1);
245 addr8 = read_reg(c, ONENAND_REG_START_ADDRESS8);
246 if (ecc & ONENAND_ECC_2BIT_ALL) {
247 printk(KERN_ERR "onenand_wait: ECC error = "
248 "0x%04x, addr1 %#x, addr8 %#x\n",
249 ecc, addr1, addr8);
250 mtd->ecc_stats.failed++;
251 return -EBADMSG;
252 } else if (ecc & ONENAND_ECC_1BIT_ALL) {
253 printk(KERN_NOTICE "onenand_wait: correctable "
254 "ECC error = 0x%04x, addr1 %#x, "
255 "addr8 %#x\n", ecc, addr1, addr8);
256 mtd->ecc_stats.corrected++;
257 }
258 }
259 } else if (state == FL_READING) {
260 wait_err("timeout", state, ctrl, intr);
261 return -EIO;
262 }
263
264 if (ctrl & ONENAND_CTRL_ERROR) {
265 wait_err("controller error", state, ctrl, intr);
266 if (ctrl & ONENAND_CTRL_LOCK)
267 printk(KERN_ERR "onenand_wait: "
268 "Device is write protected!!!\n");
269 return -EIO;
270 }
271
d19d7b46
RT		 272 ctrl_mask = 0xFE9F;
273 if (this->ongoing)
274 ctrl_mask &= ~0x8000;
275
276 if (ctrl & ctrl_mask)
36cd4fb5
AH		 277 wait_warn("unexpected controller status", state, ctrl, intr);
278
279 return 0;
280}
281
282static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
283{
284 struct onenand_chip *this = mtd->priv;
285
286 if (ONENAND_CURRENT_BUFFERRAM(this)) {
287 if (area == ONENAND_DATARAM)
00acf4a8 288 return this->writesize;
36cd4fb5
AH		 289 if (area == ONENAND_SPARERAM)
290 return mtd->oobsize;
291 }
292
293 return 0;
294}
295
296#if defined(CONFIG_ARCH_OMAP3) || defined(MULTI_OMAP2)
297
298static int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
299 unsigned char *buffer, int offset,
300 size_t count)
301{
302 struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
303 struct onenand_chip *this = mtd->priv;
304 dma_addr_t dma_src, dma_dst;
305 int bram_offset;
306 unsigned long timeout;
307 void *buf = (void *)buffer;
308 size_t xtra;
309 volatile unsigned *done;
310
311 bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
312 if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
313 goto out_copy;
314
a29f280b 315 /* panic_write() may be in an interrupt context */
932f5d21 316 if (in_interrupt() || oops_in_progress)
a29f280b
AH		 317 goto out_copy;
318
36cd4fb5
AH		 319 if (buf >= high_memory) {
320 struct page *p1;
321
322 if (((size_t)buf & PAGE_MASK) !=
323 ((size_t)(buf + count - 1) & PAGE_MASK))
324 goto out_copy;
325 p1 = vmalloc_to_page(buf);
326 if (!p1)
327 goto out_copy;
328 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
329 }
330
331 xtra = count & 3;
332 if (xtra) {
333 count -= xtra;
334 memcpy(buf + count, this->base + bram_offset + count, xtra);
335 }
336
337 dma_src = c->phys_base + bram_offset;
338 dma_dst = dma_map_single(&c->pdev->dev, buf, count, DMA_FROM_DEVICE);
339 if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
340 dev_err(&c->pdev->dev,
341 "Couldn't DMA map a %d byte buffer\n",
342 count);
343 goto out_copy;
344 }
345
346 omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
347 count >> 2, 1, 0, 0, 0);
348 omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
349 dma_src, 0, 0);
350 omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
351 dma_dst, 0, 0);
352
353 INIT_COMPLETION(c->dma_done);
354 omap_start_dma(c->dma_channel);
355
356 timeout = jiffies + msecs_to_jiffies(20);
357 done = &c->dma_done.done;
358 while (time_before(jiffies, timeout))
359 if (*done)
360 break;
361
362 dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
363
364 if (!*done) {
365 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
366 goto out_copy;
367 }
368
369 return 0;
370
371out_copy:
372 memcpy(buf, this->base + bram_offset, count);
373 return 0;
374}
375
376static int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
377 const unsigned char *buffer,
378 int offset, size_t count)
379{
380 struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
381 struct onenand_chip *this = mtd->priv;
382 dma_addr_t dma_src, dma_dst;
383 int bram_offset;
384 unsigned long timeout;
385 void *buf = (void *)buffer;
386 volatile unsigned *done;
387
388 bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
389 if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
390 goto out_copy;
391
392 /* panic_write() may be in an interrupt context */
932f5d21 393 if (in_interrupt() || oops_in_progress)
36cd4fb5
AH		 394 goto out_copy;
395
396 if (buf >= high_memory) {
397 struct page *p1;
398
399 if (((size_t)buf & PAGE_MASK) !=
400 ((size_t)(buf + count - 1) & PAGE_MASK))
401 goto out_copy;
402 p1 = vmalloc_to_page(buf);
403 if (!p1)
404 goto out_copy;
405 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
406 }
407
408 dma_src = dma_map_single(&c->pdev->dev, buf, count, DMA_TO_DEVICE);
409 dma_dst = c->phys_base + bram_offset;
4a70b7d3 410 if (dma_mapping_error(&c->pdev->dev, dma_src)) {
36cd4fb5
AH		 411 dev_err(&c->pdev->dev,
412 "Couldn't DMA map a %d byte buffer\n",
413 count);
414 return -1;
415 }
416
417 omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
418 count >> 2, 1, 0, 0, 0);
419 omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
420 dma_src, 0, 0);
421 omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
422 dma_dst, 0, 0);
423
424 INIT_COMPLETION(c->dma_done);
425 omap_start_dma(c->dma_channel);
426
427 timeout = jiffies + msecs_to_jiffies(20);
428 done = &c->dma_done.done;
429 while (time_before(jiffies, timeout))
430 if (*done)
431 break;
432
4a70b7d3 433 dma_unmap_single(&c->pdev->dev, dma_src, count, DMA_TO_DEVICE);
36cd4fb5
AH		 434
435 if (!*done) {
436 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
437 goto out_copy;
438 }
439
440 return 0;
441
442out_copy:
443 memcpy(this->base + bram_offset, buf, count);
444 return 0;
445}
446
447#else
448
449int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
450 unsigned char *buffer, int offset,
451 size_t count);
452
453int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
454 const unsigned char *buffer,
455 int offset, size_t count);
456
457#endif
458
459#if defined(CONFIG_ARCH_OMAP2) || defined(MULTI_OMAP2)
460
461static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
462 unsigned char *buffer, int offset,
463 size_t count)
464{
465 struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
466 struct onenand_chip *this = mtd->priv;
467 dma_addr_t dma_src, dma_dst;
468 int bram_offset;
469
470 bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
471 /* DMA is not used. Revisit PM requirements before enabling it. */
472 if (1 || (c->dma_channel < 0) ||
473 ((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
474 (((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
475 memcpy(buffer, (__force void *)(this->base + bram_offset),
476 count);
477 return 0;
478 }
479
480 dma_src = c->phys_base + bram_offset;
481 dma_dst = dma_map_single(&c->pdev->dev, buffer, count,
482 DMA_FROM_DEVICE);
483 if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
484 dev_err(&c->pdev->dev,
485 "Couldn't DMA map a %d byte buffer\n",
486 count);
487 return -1;
488 }
489
490 omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
491 count / 4, 1, 0, 0, 0);
492 omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
493 dma_src, 0, 0);
494 omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
495 dma_dst, 0, 0);
496
497 INIT_COMPLETION(c->dma_done);
498 omap_start_dma(c->dma_channel);
499 wait_for_completion(&c->dma_done);
500
501 dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
502
503 return 0;
504}
505
506static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
507 const unsigned char *buffer,
508 int offset, size_t count)
509{
510 struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
511 struct onenand_chip *this = mtd->priv;
512 dma_addr_t dma_src, dma_dst;
513 int bram_offset;
514
515 bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
516 /* DMA is not used. Revisit PM requirements before enabling it. */
517 if (1 || (c->dma_channel < 0) ||
518 ((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
519 (((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
520 memcpy((__force void *)(this->base + bram_offset), buffer,
521 count);
522 return 0;
523 }
524
525 dma_src = dma_map_single(&c->pdev->dev, (void *) buffer, count,
526 DMA_TO_DEVICE);
527 dma_dst = c->phys_base + bram_offset;
4a70b7d3 528 if (dma_mapping_error(&c->pdev->dev, dma_src)) {
36cd4fb5
AH		 529 dev_err(&c->pdev->dev,
530 "Couldn't DMA map a %d byte buffer\n",
531 count);
532 return -1;
533 }
534
535 omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S16,
536 count / 2, 1, 0, 0, 0);
537 omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
538 dma_src, 0, 0);
539 omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
540 dma_dst, 0, 0);
541
542 INIT_COMPLETION(c->dma_done);
543 omap_start_dma(c->dma_channel);
544 wait_for_completion(&c->dma_done);
545
4a70b7d3 546 dma_unmap_single(&c->pdev->dev, dma_src, count, DMA_TO_DEVICE);
36cd4fb5
AH		 547
548 return 0;
549}
550
551#else
552
553int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
554 unsigned char *buffer, int offset,
555 size_t count);
556
557int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
558 const unsigned char *buffer,
559 int offset, size_t count);
560
561#endif
562
563static struct platform_driver omap2_onenand_driver;
564
565static int __adjust_timing(struct device *dev, void *data)
566{
567 int ret = 0;
568 struct omap2_onenand *c;
569
570 c = dev_get_drvdata(dev);
571
572 BUG_ON(c->setup == NULL);
573
574 /* DMA is not in use so this is all that is needed */
575 /* Revisit for OMAP3! */
3ad2d861 576 ret = c->setup(c->onenand.base, &c->freq);
36cd4fb5
AH		 577
578 return ret;
579}
580
581int omap2_onenand_rephase(void)
582{
583 return driver_for_each_device(&omap2_onenand_driver.driver, NULL,
584 NULL, __adjust_timing);
585}
586
d3412dbd 587static void omap2_onenand_shutdown(struct platform_device *pdev)
36cd4fb5
AH		 588{
589 struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
590
591 /* With certain content in the buffer RAM, the OMAP boot ROM code
592 * can recognize the flash chip incorrectly. Zero it out before
593 * soft reset.
594 */
595 memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE);
596}
597
9ac4e613
AH		 598static int omap2_onenand_enable(struct mtd_info *mtd)
599{
600 int ret;
601 struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
602
603 ret = regulator_enable(c->regulator);
604 if (ret != 0)
25985edc 605 dev_err(&c->pdev->dev, "can't enable regulator\n");
9ac4e613
AH		 606
607 return ret;
608}
609
610static int omap2_onenand_disable(struct mtd_info *mtd)
611{
612 int ret;
613 struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
614
615 ret = regulator_disable(c->regulator);
616 if (ret != 0)
25985edc 617 dev_err(&c->pdev->dev, "can't disable regulator\n");
9ac4e613
AH		 618
619 return ret;
620}
621
36cd4fb5
AH		 622static int __devinit omap2_onenand_probe(struct platform_device *pdev)
623{
624 struct omap_onenand_platform_data *pdata;
625 struct omap2_onenand *c;
c93ff6bf 626 struct onenand_chip *this;
36cd4fb5 627 int r;
d65ccb6d 628 struct resource *res;
36cd4fb5
AH		 629
630 pdata = pdev->dev.platform_data;
631 if (pdata == NULL) {
632 dev_err(&pdev->dev, "platform data missing\n");
633 return -ENODEV;
634 }
635
636 c = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
637 if (!c)
638 return -ENOMEM;
639
640 init_completion(&c->irq_done);
641 init_completion(&c->dma_done);
642 c->gpmc_cs = pdata->cs;
643 c->gpio_irq = pdata->gpio_irq;
644 c->dma_channel = pdata->dma_channel;
645 if (c->dma_channel < 0) {
646 /* if -1, don't use DMA */
647 c->gpio_irq = 0;
648 }
649
d65ccb6d
AM		 650 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
651 if (res == NULL) {
652 r = -EINVAL;
653 dev_err(&pdev->dev, "error getting memory resource\n");
36cd4fb5
AH		 654 goto err_kfree;
655 }
656
d65ccb6d
AM		 657 c->phys_base = res->start;
658 c->mem_size = resource_size(res);
659
660 if (request_mem_region(c->phys_base, c->mem_size,
36cd4fb5 661 pdev->dev.driver->name) == NULL) {
d65ccb6d
AM		 662 dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, size: 0x%x\n",
663 c->phys_base, c->mem_size);
36cd4fb5 664 r = -EBUSY;
d65ccb6d 665 goto err_kfree;
36cd4fb5 666 }
d65ccb6d 667 c->onenand.base = ioremap(c->phys_base, c->mem_size);
36cd4fb5
AH		 668 if (c->onenand.base == NULL) {
669 r = -ENOMEM;
670 goto err_release_mem_region;
671 }
672
673 if (pdata->onenand_setup != NULL) {
3ad2d861 674 r = pdata->onenand_setup(c->onenand.base, &c->freq);
36cd4fb5
AH		 675 if (r < 0) {
676 dev_err(&pdev->dev, "Onenand platform setup failed: "
677 "%d\n", r);
678 goto err_iounmap;
679 }
680 c->setup = pdata->onenand_setup;
681 }
682
683 if (c->gpio_irq) {
73069e38 684 if ((r = gpio_request(c->gpio_irq, "OneNAND irq")) < 0) {
36cd4fb5
AH		 685 dev_err(&pdev->dev, "Failed to request GPIO%d for "
686 "OneNAND\n", c->gpio_irq);
687 goto err_iounmap;
688 }
40e3925b 689 gpio_direction_input(c->gpio_irq);
36cd4fb5 690
15f74b03 691 if ((r = request_irq(gpio_to_irq(c->gpio_irq),
36cd4fb5
AH		 692 omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
693 pdev->dev.driver->name, c)) < 0)
694 goto err_release_gpio;
695 }
696
697 if (c->dma_channel >= 0) {
698 r = omap_request_dma(0, pdev->dev.driver->name,
699 omap2_onenand_dma_cb, (void *) c,
700 &c->dma_channel);
701 if (r == 0) {
702 omap_set_dma_write_mode(c->dma_channel,
703 OMAP_DMA_WRITE_NON_POSTED);
704 omap_set_dma_src_data_pack(c->dma_channel, 1);
705 omap_set_dma_src_burst_mode(c->dma_channel,
706 OMAP_DMA_DATA_BURST_8);
707 omap_set_dma_dest_data_pack(c->dma_channel, 1);
708 omap_set_dma_dest_burst_mode(c->dma_channel,
709 OMAP_DMA_DATA_BURST_8);
710 } else {
711 dev_info(&pdev->dev,
712 "failed to allocate DMA for OneNAND, "
713 "using PIO instead\n");
714 c->dma_channel = -1;
715 }
716 }
717
718 dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
3ad2d861
AH		 719 "base %p, freq %d MHz\n", c->gpmc_cs, c->phys_base,
720 c->onenand.base, c->freq);
36cd4fb5
AH		 721
722 c->pdev = pdev;
475b44c1 723 c->mtd.name = dev_name(&pdev->dev);
36cd4fb5
AH		 724 c->mtd.priv = &c->onenand;
725 c->mtd.owner = THIS_MODULE;
726
87f39f04
DB		 727 c->mtd.dev.parent = &pdev->dev;
728
c93ff6bf 729 this = &c->onenand;
36cd4fb5 730 if (c->dma_channel >= 0) {
36cd4fb5
AH		 731 this->wait = omap2_onenand_wait;
732 if (cpu_is_omap34xx()) {
733 this->read_bufferram = omap3_onenand_read_bufferram;
734 this->write_bufferram = omap3_onenand_write_bufferram;
735 } else {
736 this->read_bufferram = omap2_onenand_read_bufferram;
737 this->write_bufferram = omap2_onenand_write_bufferram;
738 }
739 }
740
9ac4e613
AH		 741 if (pdata->regulator_can_sleep) {
742 c->regulator = regulator_get(&pdev->dev, "vonenand");
743 if (IS_ERR(c->regulator)) {
744 dev_err(&pdev->dev, "Failed to get regulator\n");
1c3bd14b 745 r = PTR_ERR(c->regulator);
9ac4e613
AH		 746 goto err_release_dma;
747 }
748 c->onenand.enable = omap2_onenand_enable;
749 c->onenand.disable = omap2_onenand_disable;
750 }
751
c93ff6bf
RT		 752 if (pdata->skip_initial_unlocking)
753 this->options |= ONENAND_SKIP_INITIAL_UNLOCKING;
754
36cd4fb5 755 if ((r = onenand_scan(&c->mtd, 1)) < 0)
9ac4e613 756 goto err_release_regulator;
36cd4fb5 757
42d7fbe2
AB		 758 r = mtd_device_parse_register(&c->mtd, NULL, NULL,
759 pdata ? pdata->parts : NULL,
760 pdata ? pdata->nr_parts : 0);
263a8c86 761 if (r)
36cd4fb5
AH		 762 goto err_release_onenand;
763
764 platform_set_drvdata(pdev, c);
765
766 return 0;
767
768err_release_onenand:
769 onenand_release(&c->mtd);
9ac4e613
AH		 770err_release_regulator:
771 regulator_put(c->regulator);
36cd4fb5
AH		 772err_release_dma:
773 if (c->dma_channel != -1)
774 omap_free_dma(c->dma_channel);
775 if (c->gpio_irq)
15f74b03 776 free_irq(gpio_to_irq(c->gpio_irq), c);
36cd4fb5
AH		 777err_release_gpio:
778 if (c->gpio_irq)
73069e38 779 gpio_free(c->gpio_irq);
36cd4fb5
AH		 780err_iounmap:
781 iounmap(c->onenand.base);
782err_release_mem_region:
d65ccb6d 783 release_mem_region(c->phys_base, c->mem_size);
36cd4fb5
AH		 784err_kfree:
785 kfree(c);
786
787 return r;
788}
789
790static int __devexit omap2_onenand_remove(struct platform_device *pdev)
791{
792 struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
793
36cd4fb5 794 onenand_release(&c->mtd);
9ac4e613 795 regulator_put(c->regulator);
36cd4fb5
AH		 796 if (c->dma_channel != -1)
797 omap_free_dma(c->dma_channel);
798 omap2_onenand_shutdown(pdev);
799 platform_set_drvdata(pdev, NULL);
800 if (c->gpio_irq) {
15f74b03 801 free_irq(gpio_to_irq(c->gpio_irq), c);
73069e38 802 gpio_free(c->gpio_irq);
36cd4fb5
AH		 803 }
804 iounmap(c->onenand.base);
d65ccb6d 805 release_mem_region(c->phys_base, c->mem_size);
3cae1cc1 806 gpmc_cs_free(c->gpmc_cs);
36cd4fb5
AH		 807 kfree(c);
808
809 return 0;
810}
811
812static struct platform_driver omap2_onenand_driver = {
813 .probe = omap2_onenand_probe,
d3412dbd 814 .remove = __devexit_p(omap2_onenand_remove),
36cd4fb5
AH		 815 .shutdown = omap2_onenand_shutdown,
816 .driver = {
817 .name = DRIVER_NAME,
818 .owner = THIS_MODULE,
819 },
820};
821
822static int __init omap2_onenand_init(void)
823{
824 printk(KERN_INFO "OneNAND driver initializing\n");
825 return platform_driver_register(&omap2_onenand_driver);
826}
827
828static void __exit omap2_onenand_exit(void)
829{
830 platform_driver_unregister(&omap2_onenand_driver);
831}
832
833module_init(omap2_onenand_init);
834module_exit(omap2_onenand_exit);
835
c804c733 836MODULE_ALIAS("platform:" DRIVER_NAME);
36cd4fb5
AH		 837MODULE_LICENSE("GPL");
838MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
839MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2 / OMAP3");
Linux kernel - Deliverables
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