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cd5f6346 KP |
1 | /* |
2 | * linux/drivers/mtd/onenand/onenand_base.c | |
3 | * | |
75384b0d | 4 | * Copyright (C) 2005-2007 Samsung Electronics |
cd5f6346 KP |
5 | * Kyungmin Park <kyungmin.park@samsung.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/init.h> | |
015953d7 | 15 | #include <linux/sched.h> |
2c22120f | 16 | #include <linux/interrupt.h> |
015953d7 | 17 | #include <linux/jiffies.h> |
cd5f6346 KP |
18 | #include <linux/mtd/mtd.h> |
19 | #include <linux/mtd/onenand.h> | |
20 | #include <linux/mtd/partitions.h> | |
21 | ||
22 | #include <asm/io.h> | |
23 | ||
24 | /** | |
25 | * onenand_oob_64 - oob info for large (2KB) page | |
26 | */ | |
5bd34c09 | 27 | static struct nand_ecclayout onenand_oob_64 = { |
cd5f6346 KP |
28 | .eccbytes = 20, |
29 | .eccpos = { | |
30 | 8, 9, 10, 11, 12, | |
31 | 24, 25, 26, 27, 28, | |
32 | 40, 41, 42, 43, 44, | |
33 | 56, 57, 58, 59, 60, | |
34 | }, | |
35 | .oobfree = { | |
36 | {2, 3}, {14, 2}, {18, 3}, {30, 2}, | |
d9777f1c JL |
37 | {34, 3}, {46, 2}, {50, 3}, {62, 2} |
38 | } | |
cd5f6346 KP |
39 | }; |
40 | ||
41 | /** | |
42 | * onenand_oob_32 - oob info for middle (1KB) page | |
43 | */ | |
5bd34c09 | 44 | static struct nand_ecclayout onenand_oob_32 = { |
cd5f6346 KP |
45 | .eccbytes = 10, |
46 | .eccpos = { | |
47 | 8, 9, 10, 11, 12, | |
48 | 24, 25, 26, 27, 28, | |
49 | }, | |
50 | .oobfree = { {2, 3}, {14, 2}, {18, 3}, {30, 2} } | |
51 | }; | |
52 | ||
53 | static const unsigned char ffchars[] = { | |
54 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
55 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 16 */ | |
56 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
57 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 32 */ | |
58 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
59 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 48 */ | |
60 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
61 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 64 */ | |
62 | }; | |
63 | ||
64 | /** | |
65 | * onenand_readw - [OneNAND Interface] Read OneNAND register | |
66 | * @param addr address to read | |
67 | * | |
68 | * Read OneNAND register | |
69 | */ | |
70 | static unsigned short onenand_readw(void __iomem *addr) | |
71 | { | |
72 | return readw(addr); | |
73 | } | |
74 | ||
75 | /** | |
76 | * onenand_writew - [OneNAND Interface] Write OneNAND register with value | |
77 | * @param value value to write | |
78 | * @param addr address to write | |
79 | * | |
80 | * Write OneNAND register with value | |
81 | */ | |
82 | static void onenand_writew(unsigned short value, void __iomem *addr) | |
83 | { | |
84 | writew(value, addr); | |
85 | } | |
86 | ||
87 | /** | |
88 | * onenand_block_address - [DEFAULT] Get block address | |
83a36838 | 89 | * @param this onenand chip data structure |
cd5f6346 KP |
90 | * @param block the block |
91 | * @return translated block address if DDP, otherwise same | |
92 | * | |
93 | * Setup Start Address 1 Register (F100h) | |
94 | */ | |
83a36838 | 95 | static int onenand_block_address(struct onenand_chip *this, int block) |
cd5f6346 | 96 | { |
738d61f5 KP |
97 | /* Device Flash Core select, NAND Flash Block Address */ |
98 | if (block & this->density_mask) | |
99 | return ONENAND_DDP_CHIP1 | (block ^ this->density_mask); | |
cd5f6346 KP |
100 | |
101 | return block; | |
102 | } | |
103 | ||
104 | /** | |
105 | * onenand_bufferram_address - [DEFAULT] Get bufferram address | |
83a36838 | 106 | * @param this onenand chip data structure |
cd5f6346 KP |
107 | * @param block the block |
108 | * @return set DBS value if DDP, otherwise 0 | |
109 | * | |
110 | * Setup Start Address 2 Register (F101h) for DDP | |
111 | */ | |
83a36838 | 112 | static int onenand_bufferram_address(struct onenand_chip *this, int block) |
cd5f6346 | 113 | { |
738d61f5 KP |
114 | /* Device BufferRAM Select */ |
115 | if (block & this->density_mask) | |
116 | return ONENAND_DDP_CHIP1; | |
cd5f6346 | 117 | |
738d61f5 | 118 | return ONENAND_DDP_CHIP0; |
cd5f6346 KP |
119 | } |
120 | ||
121 | /** | |
122 | * onenand_page_address - [DEFAULT] Get page address | |
123 | * @param page the page address | |
124 | * @param sector the sector address | |
125 | * @return combined page and sector address | |
126 | * | |
127 | * Setup Start Address 8 Register (F107h) | |
128 | */ | |
129 | static int onenand_page_address(int page, int sector) | |
130 | { | |
131 | /* Flash Page Address, Flash Sector Address */ | |
132 | int fpa, fsa; | |
133 | ||
134 | fpa = page & ONENAND_FPA_MASK; | |
135 | fsa = sector & ONENAND_FSA_MASK; | |
136 | ||
137 | return ((fpa << ONENAND_FPA_SHIFT) | fsa); | |
138 | } | |
139 | ||
140 | /** | |
141 | * onenand_buffer_address - [DEFAULT] Get buffer address | |
142 | * @param dataram1 DataRAM index | |
143 | * @param sectors the sector address | |
144 | * @param count the number of sectors | |
145 | * @return the start buffer value | |
146 | * | |
147 | * Setup Start Buffer Register (F200h) | |
148 | */ | |
149 | static int onenand_buffer_address(int dataram1, int sectors, int count) | |
150 | { | |
151 | int bsa, bsc; | |
152 | ||
153 | /* BufferRAM Sector Address */ | |
154 | bsa = sectors & ONENAND_BSA_MASK; | |
155 | ||
156 | if (dataram1) | |
157 | bsa |= ONENAND_BSA_DATARAM1; /* DataRAM1 */ | |
158 | else | |
159 | bsa |= ONENAND_BSA_DATARAM0; /* DataRAM0 */ | |
160 | ||
161 | /* BufferRAM Sector Count */ | |
162 | bsc = count & ONENAND_BSC_MASK; | |
163 | ||
164 | return ((bsa << ONENAND_BSA_SHIFT) | bsc); | |
165 | } | |
166 | ||
167 | /** | |
168 | * onenand_command - [DEFAULT] Send command to OneNAND device | |
169 | * @param mtd MTD device structure | |
170 | * @param cmd the command to be sent | |
171 | * @param addr offset to read from or write to | |
172 | * @param len number of bytes to read or write | |
173 | * | |
174 | * Send command to OneNAND device. This function is used for middle/large page | |
175 | * devices (1KB/2KB Bytes per page) | |
176 | */ | |
177 | static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t len) | |
178 | { | |
179 | struct onenand_chip *this = mtd->priv; | |
493c6460 | 180 | int value, readcmd = 0, block_cmd = 0; |
cd5f6346 | 181 | int block, page; |
cd5f6346 KP |
182 | |
183 | /* Address translation */ | |
184 | switch (cmd) { | |
185 | case ONENAND_CMD_UNLOCK: | |
186 | case ONENAND_CMD_LOCK: | |
187 | case ONENAND_CMD_LOCK_TIGHT: | |
28b79ff9 | 188 | case ONENAND_CMD_UNLOCK_ALL: |
cd5f6346 KP |
189 | block = -1; |
190 | page = -1; | |
191 | break; | |
192 | ||
193 | case ONENAND_CMD_ERASE: | |
194 | case ONENAND_CMD_BUFFERRAM: | |
493c6460 KP |
195 | case ONENAND_CMD_OTP_ACCESS: |
196 | block_cmd = 1; | |
cd5f6346 KP |
197 | block = (int) (addr >> this->erase_shift); |
198 | page = -1; | |
199 | break; | |
200 | ||
201 | default: | |
202 | block = (int) (addr >> this->erase_shift); | |
203 | page = (int) (addr >> this->page_shift); | |
204 | page &= this->page_mask; | |
205 | break; | |
206 | } | |
207 | ||
208 | /* NOTE: The setting order of the registers is very important! */ | |
209 | if (cmd == ONENAND_CMD_BUFFERRAM) { | |
210 | /* Select DataRAM for DDP */ | |
83a36838 | 211 | value = onenand_bufferram_address(this, block); |
cd5f6346 KP |
212 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); |
213 | ||
214 | /* Switch to the next data buffer */ | |
215 | ONENAND_SET_NEXT_BUFFERRAM(this); | |
216 | ||
217 | return 0; | |
218 | } | |
219 | ||
220 | if (block != -1) { | |
221 | /* Write 'DFS, FBA' of Flash */ | |
83a36838 | 222 | value = onenand_block_address(this, block); |
cd5f6346 | 223 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); |
3cecf69e | 224 | |
75287070 | 225 | if (block_cmd) { |
3cecf69e KP |
226 | /* Select DataRAM for DDP */ |
227 | value = onenand_bufferram_address(this, block); | |
228 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); | |
229 | } | |
cd5f6346 KP |
230 | } |
231 | ||
232 | if (page != -1) { | |
60d84f97 KP |
233 | /* Now we use page size operation */ |
234 | int sectors = 4, count = 4; | |
cd5f6346 KP |
235 | int dataram; |
236 | ||
237 | switch (cmd) { | |
238 | case ONENAND_CMD_READ: | |
239 | case ONENAND_CMD_READOOB: | |
240 | dataram = ONENAND_SET_NEXT_BUFFERRAM(this); | |
241 | readcmd = 1; | |
242 | break; | |
243 | ||
244 | default: | |
245 | dataram = ONENAND_CURRENT_BUFFERRAM(this); | |
246 | break; | |
247 | } | |
248 | ||
249 | /* Write 'FPA, FSA' of Flash */ | |
250 | value = onenand_page_address(page, sectors); | |
251 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS8); | |
252 | ||
253 | /* Write 'BSA, BSC' of DataRAM */ | |
254 | value = onenand_buffer_address(dataram, sectors, count); | |
255 | this->write_word(value, this->base + ONENAND_REG_START_BUFFER); | |
d5c5e78a | 256 | |
cd5f6346 KP |
257 | if (readcmd) { |
258 | /* Select DataRAM for DDP */ | |
83a36838 | 259 | value = onenand_bufferram_address(this, block); |
cd5f6346 KP |
260 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); |
261 | } | |
262 | } | |
263 | ||
264 | /* Interrupt clear */ | |
265 | this->write_word(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT); | |
266 | ||
267 | /* Write command */ | |
268 | this->write_word(cmd, this->base + ONENAND_REG_COMMAND); | |
269 | ||
270 | return 0; | |
271 | } | |
272 | ||
273 | /** | |
274 | * onenand_wait - [DEFAULT] wait until the command is done | |
275 | * @param mtd MTD device structure | |
276 | * @param state state to select the max. timeout value | |
277 | * | |
278 | * Wait for command done. This applies to all OneNAND command | |
279 | * Read can take up to 30us, erase up to 2ms and program up to 350us | |
280 | * according to general OneNAND specs | |
281 | */ | |
282 | static int onenand_wait(struct mtd_info *mtd, int state) | |
283 | { | |
284 | struct onenand_chip * this = mtd->priv; | |
285 | unsigned long timeout; | |
286 | unsigned int flags = ONENAND_INT_MASTER; | |
287 | unsigned int interrupt = 0; | |
2fd32d4a | 288 | unsigned int ctrl; |
cd5f6346 KP |
289 | |
290 | /* The 20 msec is enough */ | |
291 | timeout = jiffies + msecs_to_jiffies(20); | |
292 | while (time_before(jiffies, timeout)) { | |
293 | interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); | |
294 | ||
295 | if (interrupt & flags) | |
296 | break; | |
297 | ||
298 | if (state != FL_READING) | |
299 | cond_resched(); | |
300 | } | |
301 | /* To get correct interrupt status in timeout case */ | |
302 | interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); | |
303 | ||
304 | ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); | |
305 | ||
306 | if (ctrl & ONENAND_CTRL_ERROR) { | |
211ac75f | 307 | printk(KERN_ERR "onenand_wait: controller error = 0x%04x\n", ctrl); |
f6272487 | 308 | if (ctrl & ONENAND_CTRL_LOCK) |
211ac75f | 309 | printk(KERN_ERR "onenand_wait: it's locked error.\n"); |
f6272487 | 310 | return ctrl; |
cd5f6346 KP |
311 | } |
312 | ||
313 | if (interrupt & ONENAND_INT_READ) { | |
2fd32d4a | 314 | int ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS); |
f4f91ac3 | 315 | if (ecc) { |
211ac75f | 316 | printk(KERN_ERR "onenand_wait: ECC error = 0x%04x\n", ecc); |
b3c9f8bf | 317 | if (ecc & ONENAND_ECC_2BIT_ALL) { |
f4f91ac3 | 318 | mtd->ecc_stats.failed++; |
b3c9f8bf KP |
319 | return ecc; |
320 | } else if (ecc & ONENAND_ECC_1BIT_ALL) | |
f4f91ac3 | 321 | mtd->ecc_stats.corrected++; |
cd5f6346 | 322 | } |
9d032801 AH |
323 | } else if (state == FL_READING) { |
324 | printk(KERN_ERR "onenand_wait: read timeout! ctrl=0x%04x intr=0x%04x\n", ctrl, interrupt); | |
325 | return -EIO; | |
cd5f6346 KP |
326 | } |
327 | ||
328 | return 0; | |
329 | } | |
330 | ||
2c22120f KP |
331 | /* |
332 | * onenand_interrupt - [DEFAULT] onenand interrupt handler | |
333 | * @param irq onenand interrupt number | |
334 | * @param dev_id interrupt data | |
335 | * | |
336 | * complete the work | |
337 | */ | |
338 | static irqreturn_t onenand_interrupt(int irq, void *data) | |
339 | { | |
340 | struct onenand_chip *this = (struct onenand_chip *) data; | |
341 | ||
342 | /* To handle shared interrupt */ | |
343 | if (!this->complete.done) | |
344 | complete(&this->complete); | |
345 | ||
346 | return IRQ_HANDLED; | |
347 | } | |
348 | ||
349 | /* | |
350 | * onenand_interrupt_wait - [DEFAULT] wait until the command is done | |
351 | * @param mtd MTD device structure | |
352 | * @param state state to select the max. timeout value | |
353 | * | |
354 | * Wait for command done. | |
355 | */ | |
356 | static int onenand_interrupt_wait(struct mtd_info *mtd, int state) | |
357 | { | |
358 | struct onenand_chip *this = mtd->priv; | |
359 | ||
2c22120f KP |
360 | wait_for_completion(&this->complete); |
361 | ||
362 | return onenand_wait(mtd, state); | |
363 | } | |
364 | ||
365 | /* | |
366 | * onenand_try_interrupt_wait - [DEFAULT] try interrupt wait | |
367 | * @param mtd MTD device structure | |
368 | * @param state state to select the max. timeout value | |
369 | * | |
370 | * Try interrupt based wait (It is used one-time) | |
371 | */ | |
372 | static int onenand_try_interrupt_wait(struct mtd_info *mtd, int state) | |
373 | { | |
374 | struct onenand_chip *this = mtd->priv; | |
375 | unsigned long remain, timeout; | |
376 | ||
377 | /* We use interrupt wait first */ | |
378 | this->wait = onenand_interrupt_wait; | |
379 | ||
2c22120f KP |
380 | timeout = msecs_to_jiffies(100); |
381 | remain = wait_for_completion_timeout(&this->complete, timeout); | |
382 | if (!remain) { | |
383 | printk(KERN_INFO "OneNAND: There's no interrupt. " | |
384 | "We use the normal wait\n"); | |
385 | ||
386 | /* Release the irq */ | |
387 | free_irq(this->irq, this); | |
c9ac5977 | 388 | |
2c22120f KP |
389 | this->wait = onenand_wait; |
390 | } | |
391 | ||
392 | return onenand_wait(mtd, state); | |
393 | } | |
394 | ||
395 | /* | |
396 | * onenand_setup_wait - [OneNAND Interface] setup onenand wait method | |
397 | * @param mtd MTD device structure | |
398 | * | |
399 | * There's two method to wait onenand work | |
400 | * 1. polling - read interrupt status register | |
401 | * 2. interrupt - use the kernel interrupt method | |
402 | */ | |
403 | static void onenand_setup_wait(struct mtd_info *mtd) | |
404 | { | |
405 | struct onenand_chip *this = mtd->priv; | |
406 | int syscfg; | |
407 | ||
408 | init_completion(&this->complete); | |
409 | ||
410 | if (this->irq <= 0) { | |
411 | this->wait = onenand_wait; | |
412 | return; | |
413 | } | |
414 | ||
415 | if (request_irq(this->irq, &onenand_interrupt, | |
416 | IRQF_SHARED, "onenand", this)) { | |
417 | /* If we can't get irq, use the normal wait */ | |
418 | this->wait = onenand_wait; | |
419 | return; | |
420 | } | |
421 | ||
422 | /* Enable interrupt */ | |
423 | syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1); | |
424 | syscfg |= ONENAND_SYS_CFG1_IOBE; | |
425 | this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1); | |
426 | ||
427 | this->wait = onenand_try_interrupt_wait; | |
428 | } | |
429 | ||
cd5f6346 KP |
430 | /** |
431 | * onenand_bufferram_offset - [DEFAULT] BufferRAM offset | |
432 | * @param mtd MTD data structure | |
433 | * @param area BufferRAM area | |
434 | * @return offset given area | |
435 | * | |
436 | * Return BufferRAM offset given area | |
437 | */ | |
438 | static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area) | |
439 | { | |
440 | struct onenand_chip *this = mtd->priv; | |
441 | ||
442 | if (ONENAND_CURRENT_BUFFERRAM(this)) { | |
443 | if (area == ONENAND_DATARAM) | |
28318776 | 444 | return mtd->writesize; |
cd5f6346 KP |
445 | if (area == ONENAND_SPARERAM) |
446 | return mtd->oobsize; | |
447 | } | |
448 | ||
449 | return 0; | |
450 | } | |
451 | ||
452 | /** | |
453 | * onenand_read_bufferram - [OneNAND Interface] Read the bufferram area | |
454 | * @param mtd MTD data structure | |
455 | * @param area BufferRAM area | |
456 | * @param buffer the databuffer to put/get data | |
457 | * @param offset offset to read from or write to | |
458 | * @param count number of bytes to read/write | |
459 | * | |
460 | * Read the BufferRAM area | |
461 | */ | |
462 | static int onenand_read_bufferram(struct mtd_info *mtd, int area, | |
463 | unsigned char *buffer, int offset, size_t count) | |
464 | { | |
465 | struct onenand_chip *this = mtd->priv; | |
466 | void __iomem *bufferram; | |
467 | ||
468 | bufferram = this->base + area; | |
469 | ||
470 | bufferram += onenand_bufferram_offset(mtd, area); | |
471 | ||
9c01f87d KP |
472 | if (ONENAND_CHECK_BYTE_ACCESS(count)) { |
473 | unsigned short word; | |
474 | ||
475 | /* Align with word(16-bit) size */ | |
476 | count--; | |
477 | ||
478 | /* Read word and save byte */ | |
479 | word = this->read_word(bufferram + offset + count); | |
480 | buffer[count] = (word & 0xff); | |
481 | } | |
482 | ||
cd5f6346 KP |
483 | memcpy(buffer, bufferram + offset, count); |
484 | ||
485 | return 0; | |
486 | } | |
487 | ||
52b0eea7 KP |
488 | /** |
489 | * onenand_sync_read_bufferram - [OneNAND Interface] Read the bufferram area with Sync. Burst mode | |
490 | * @param mtd MTD data structure | |
491 | * @param area BufferRAM area | |
492 | * @param buffer the databuffer to put/get data | |
493 | * @param offset offset to read from or write to | |
494 | * @param count number of bytes to read/write | |
495 | * | |
496 | * Read the BufferRAM area with Sync. Burst Mode | |
497 | */ | |
498 | static int onenand_sync_read_bufferram(struct mtd_info *mtd, int area, | |
499 | unsigned char *buffer, int offset, size_t count) | |
500 | { | |
501 | struct onenand_chip *this = mtd->priv; | |
502 | void __iomem *bufferram; | |
503 | ||
504 | bufferram = this->base + area; | |
505 | ||
506 | bufferram += onenand_bufferram_offset(mtd, area); | |
507 | ||
508 | this->mmcontrol(mtd, ONENAND_SYS_CFG1_SYNC_READ); | |
509 | ||
9c01f87d KP |
510 | if (ONENAND_CHECK_BYTE_ACCESS(count)) { |
511 | unsigned short word; | |
512 | ||
513 | /* Align with word(16-bit) size */ | |
514 | count--; | |
515 | ||
516 | /* Read word and save byte */ | |
517 | word = this->read_word(bufferram + offset + count); | |
518 | buffer[count] = (word & 0xff); | |
519 | } | |
520 | ||
52b0eea7 KP |
521 | memcpy(buffer, bufferram + offset, count); |
522 | ||
523 | this->mmcontrol(mtd, 0); | |
524 | ||
525 | return 0; | |
526 | } | |
527 | ||
cd5f6346 KP |
528 | /** |
529 | * onenand_write_bufferram - [OneNAND Interface] Write the bufferram area | |
530 | * @param mtd MTD data structure | |
531 | * @param area BufferRAM area | |
532 | * @param buffer the databuffer to put/get data | |
533 | * @param offset offset to read from or write to | |
534 | * @param count number of bytes to read/write | |
535 | * | |
536 | * Write the BufferRAM area | |
537 | */ | |
538 | static int onenand_write_bufferram(struct mtd_info *mtd, int area, | |
539 | const unsigned char *buffer, int offset, size_t count) | |
540 | { | |
541 | struct onenand_chip *this = mtd->priv; | |
542 | void __iomem *bufferram; | |
543 | ||
544 | bufferram = this->base + area; | |
545 | ||
546 | bufferram += onenand_bufferram_offset(mtd, area); | |
547 | ||
9c01f87d KP |
548 | if (ONENAND_CHECK_BYTE_ACCESS(count)) { |
549 | unsigned short word; | |
550 | int byte_offset; | |
551 | ||
552 | /* Align with word(16-bit) size */ | |
553 | count--; | |
554 | ||
555 | /* Calculate byte access offset */ | |
556 | byte_offset = offset + count; | |
557 | ||
558 | /* Read word and save byte */ | |
559 | word = this->read_word(bufferram + byte_offset); | |
560 | word = (word & ~0xff) | buffer[count]; | |
561 | this->write_word(word, bufferram + byte_offset); | |
562 | } | |
563 | ||
cd5f6346 KP |
564 | memcpy(bufferram + offset, buffer, count); |
565 | ||
566 | return 0; | |
567 | } | |
568 | ||
569 | /** | |
570 | * onenand_check_bufferram - [GENERIC] Check BufferRAM information | |
571 | * @param mtd MTD data structure | |
572 | * @param addr address to check | |
d5c5e78a | 573 | * @return 1 if there are valid data, otherwise 0 |
cd5f6346 KP |
574 | * |
575 | * Check bufferram if there is data we required | |
576 | */ | |
577 | static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr) | |
578 | { | |
579 | struct onenand_chip *this = mtd->priv; | |
cde36b37 | 580 | int blockpage, found = 0; |
abf3c0f2 | 581 | unsigned int i; |
d5c5e78a | 582 | |
abf3c0f2 | 583 | blockpage = (int) (addr >> this->page_shift); |
cd5f6346 | 584 | |
abf3c0f2 | 585 | /* Is there valid data? */ |
cd5f6346 | 586 | i = ONENAND_CURRENT_BUFFERRAM(this); |
abf3c0f2 | 587 | if (this->bufferram[i].blockpage == blockpage) |
cde36b37 AH |
588 | found = 1; |
589 | else { | |
590 | /* Check another BufferRAM */ | |
591 | i = ONENAND_NEXT_BUFFERRAM(this); | |
592 | if (this->bufferram[i].blockpage == blockpage) { | |
593 | ONENAND_SET_NEXT_BUFFERRAM(this); | |
594 | found = 1; | |
595 | } | |
596 | } | |
cd5f6346 | 597 | |
cde36b37 AH |
598 | if (found && ONENAND_IS_DDP(this)) { |
599 | /* Select DataRAM for DDP */ | |
600 | int block = (int) (addr >> this->erase_shift); | |
601 | int value = onenand_bufferram_address(this, block); | |
602 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); | |
abf3c0f2 | 603 | } |
cd5f6346 | 604 | |
cde36b37 | 605 | return found; |
cd5f6346 KP |
606 | } |
607 | ||
608 | /** | |
609 | * onenand_update_bufferram - [GENERIC] Update BufferRAM information | |
610 | * @param mtd MTD data structure | |
611 | * @param addr address to update | |
612 | * @param valid valid flag | |
613 | * | |
614 | * Update BufferRAM information | |
615 | */ | |
abf3c0f2 | 616 | static void onenand_update_bufferram(struct mtd_info *mtd, loff_t addr, |
cd5f6346 KP |
617 | int valid) |
618 | { | |
619 | struct onenand_chip *this = mtd->priv; | |
abf3c0f2 KP |
620 | int blockpage; |
621 | unsigned int i; | |
d5c5e78a | 622 | |
abf3c0f2 | 623 | blockpage = (int) (addr >> this->page_shift); |
cd5f6346 | 624 | |
abf3c0f2 KP |
625 | /* Invalidate another BufferRAM */ |
626 | i = ONENAND_NEXT_BUFFERRAM(this); | |
5b4246f1 | 627 | if (this->bufferram[i].blockpage == blockpage) |
abf3c0f2 | 628 | this->bufferram[i].blockpage = -1; |
cd5f6346 KP |
629 | |
630 | /* Update BufferRAM */ | |
631 | i = ONENAND_CURRENT_BUFFERRAM(this); | |
abf3c0f2 KP |
632 | if (valid) |
633 | this->bufferram[i].blockpage = blockpage; | |
634 | else | |
635 | this->bufferram[i].blockpage = -1; | |
cd5f6346 KP |
636 | } |
637 | ||
480b9dfb AH |
638 | /** |
639 | * onenand_invalidate_bufferram - [GENERIC] Invalidate BufferRAM information | |
640 | * @param mtd MTD data structure | |
641 | * @param addr start address to invalidate | |
642 | * @param len length to invalidate | |
643 | * | |
644 | * Invalidate BufferRAM information | |
645 | */ | |
646 | static void onenand_invalidate_bufferram(struct mtd_info *mtd, loff_t addr, | |
647 | unsigned int len) | |
648 | { | |
649 | struct onenand_chip *this = mtd->priv; | |
650 | int i; | |
651 | loff_t end_addr = addr + len; | |
652 | ||
653 | /* Invalidate BufferRAM */ | |
654 | for (i = 0; i < MAX_BUFFERRAM; i++) { | |
655 | loff_t buf_addr = this->bufferram[i].blockpage << this->page_shift; | |
656 | if (buf_addr >= addr && buf_addr < end_addr) | |
657 | this->bufferram[i].blockpage = -1; | |
658 | } | |
659 | } | |
660 | ||
cd5f6346 KP |
661 | /** |
662 | * onenand_get_device - [GENERIC] Get chip for selected access | |
663 | * @param mtd MTD device structure | |
664 | * @param new_state the state which is requested | |
665 | * | |
666 | * Get the device and lock it for exclusive access | |
667 | */ | |
a41371eb | 668 | static int onenand_get_device(struct mtd_info *mtd, int new_state) |
cd5f6346 KP |
669 | { |
670 | struct onenand_chip *this = mtd->priv; | |
671 | DECLARE_WAITQUEUE(wait, current); | |
672 | ||
673 | /* | |
674 | * Grab the lock and see if the device is available | |
675 | */ | |
676 | while (1) { | |
677 | spin_lock(&this->chip_lock); | |
678 | if (this->state == FL_READY) { | |
679 | this->state = new_state; | |
680 | spin_unlock(&this->chip_lock); | |
681 | break; | |
682 | } | |
a41371eb KP |
683 | if (new_state == FL_PM_SUSPENDED) { |
684 | spin_unlock(&this->chip_lock); | |
685 | return (this->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN; | |
686 | } | |
cd5f6346 KP |
687 | set_current_state(TASK_UNINTERRUPTIBLE); |
688 | add_wait_queue(&this->wq, &wait); | |
689 | spin_unlock(&this->chip_lock); | |
690 | schedule(); | |
691 | remove_wait_queue(&this->wq, &wait); | |
692 | } | |
a41371eb KP |
693 | |
694 | return 0; | |
cd5f6346 KP |
695 | } |
696 | ||
697 | /** | |
698 | * onenand_release_device - [GENERIC] release chip | |
699 | * @param mtd MTD device structure | |
700 | * | |
701 | * Deselect, release chip lock and wake up anyone waiting on the device | |
702 | */ | |
703 | static void onenand_release_device(struct mtd_info *mtd) | |
704 | { | |
705 | struct onenand_chip *this = mtd->priv; | |
706 | ||
707 | /* Release the chip */ | |
708 | spin_lock(&this->chip_lock); | |
709 | this->state = FL_READY; | |
710 | wake_up(&this->wq); | |
711 | spin_unlock(&this->chip_lock); | |
712 | } | |
713 | ||
714 | /** | |
9223a456 | 715 | * onenand_read - [MTD Interface] Read data from flash |
cd5f6346 KP |
716 | * @param mtd MTD device structure |
717 | * @param from offset to read from | |
718 | * @param len number of bytes to read | |
719 | * @param retlen pointer to variable to store the number of read bytes | |
720 | * @param buf the databuffer to put data | |
cd5f6346 | 721 | * |
9223a456 TG |
722 | * Read with ecc |
723 | */ | |
724 | static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
725 | size_t *retlen, u_char *buf) | |
cd5f6346 KP |
726 | { |
727 | struct onenand_chip *this = mtd->priv; | |
f4f91ac3 | 728 | struct mtd_ecc_stats stats; |
cd5f6346 KP |
729 | int read = 0, column; |
730 | int thislen; | |
0fc2ccea | 731 | int ret = 0, boundary = 0; |
cd5f6346 | 732 | |
9223a456 | 733 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_read: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); |
cd5f6346 KP |
734 | |
735 | /* Do not allow reads past end of device */ | |
736 | if ((from + len) > mtd->size) { | |
211ac75f | 737 | printk(KERN_ERR "onenand_read: Attempt read beyond end of device\n"); |
cd5f6346 KP |
738 | *retlen = 0; |
739 | return -EINVAL; | |
740 | } | |
741 | ||
742 | /* Grab the lock and see if the device is available */ | |
743 | onenand_get_device(mtd, FL_READING); | |
744 | ||
f4f91ac3 | 745 | stats = mtd->ecc_stats; |
61a7e198 | 746 | |
a8de85d5 AH |
747 | /* Read-while-load method */ |
748 | ||
749 | /* Do first load to bufferRAM */ | |
750 | if (read < len) { | |
751 | if (!onenand_check_bufferram(mtd, from)) { | |
752 | this->command(mtd, ONENAND_CMD_READ, from, mtd->writesize); | |
753 | ret = this->wait(mtd, FL_READING); | |
754 | onenand_update_bufferram(mtd, from, !ret); | |
755 | } | |
756 | } | |
757 | ||
758 | thislen = min_t(int, mtd->writesize, len - read); | |
759 | column = from & (mtd->writesize - 1); | |
760 | if (column + thislen > mtd->writesize) | |
761 | thislen = mtd->writesize - column; | |
762 | ||
763 | while (!ret) { | |
764 | /* If there is more to load then start next load */ | |
765 | from += thislen; | |
766 | if (read + thislen < len) { | |
767 | this->command(mtd, ONENAND_CMD_READ, from, mtd->writesize); | |
0fc2ccea AH |
768 | /* |
769 | * Chip boundary handling in DDP | |
770 | * Now we issued chip 1 read and pointed chip 1 | |
771 | * bufferam so we have to point chip 0 bufferam. | |
772 | */ | |
738d61f5 KP |
773 | if (ONENAND_IS_DDP(this) && |
774 | unlikely(from == (this->chipsize >> 1))) { | |
775 | this->write_word(ONENAND_DDP_CHIP0, this->base + ONENAND_REG_START_ADDRESS2); | |
0fc2ccea AH |
776 | boundary = 1; |
777 | } else | |
778 | boundary = 0; | |
a8de85d5 AH |
779 | ONENAND_SET_PREV_BUFFERRAM(this); |
780 | } | |
781 | /* While load is going, read from last bufferRAM */ | |
782 | this->read_bufferram(mtd, ONENAND_DATARAM, buf, column, thislen); | |
783 | /* See if we are done */ | |
784 | read += thislen; | |
785 | if (read == len) | |
786 | break; | |
787 | /* Set up for next read from bufferRAM */ | |
0fc2ccea | 788 | if (unlikely(boundary)) |
738d61f5 | 789 | this->write_word(ONENAND_DDP_CHIP1, this->base + ONENAND_REG_START_ADDRESS2); |
a8de85d5 AH |
790 | ONENAND_SET_NEXT_BUFFERRAM(this); |
791 | buf += thislen; | |
792 | thislen = min_t(int, mtd->writesize, len - read); | |
793 | column = 0; | |
794 | cond_resched(); | |
795 | /* Now wait for load */ | |
796 | ret = this->wait(mtd, FL_READING); | |
797 | onenand_update_bufferram(mtd, from, !ret); | |
798 | } | |
cd5f6346 | 799 | |
cd5f6346 KP |
800 | /* Deselect and wake up anyone waiting on the device */ |
801 | onenand_release_device(mtd); | |
802 | ||
803 | /* | |
804 | * Return success, if no ECC failures, else -EBADMSG | |
805 | * fs driver will take care of that, because | |
806 | * retlen == desired len and result == -EBADMSG | |
807 | */ | |
808 | *retlen = read; | |
f4f91ac3 KP |
809 | |
810 | if (mtd->ecc_stats.failed - stats.failed) | |
811 | return -EBADMSG; | |
812 | ||
a8de85d5 AH |
813 | if (ret) |
814 | return ret; | |
815 | ||
f4f91ac3 | 816 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; |
cd5f6346 KP |
817 | } |
818 | ||
a5e7c7b4 AH |
819 | /** |
820 | * onenand_transfer_auto_oob - [Internal] oob auto-placement transfer | |
821 | * @param mtd MTD device structure | |
822 | * @param buf destination address | |
823 | * @param column oob offset to read from | |
824 | * @param thislen oob length to read | |
825 | */ | |
826 | static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf, int column, | |
827 | int thislen) | |
828 | { | |
829 | struct onenand_chip *this = mtd->priv; | |
830 | struct nand_oobfree *free; | |
831 | int readcol = column; | |
832 | int readend = column + thislen; | |
833 | int lastgap = 0; | |
834 | uint8_t *oob_buf = this->page_buf + mtd->writesize; | |
835 | ||
836 | for (free = this->ecclayout->oobfree; free->length; ++free) { | |
837 | if (readcol >= lastgap) | |
838 | readcol += free->offset - lastgap; | |
839 | if (readend >= lastgap) | |
840 | readend += free->offset - lastgap; | |
841 | lastgap = free->offset + free->length; | |
842 | } | |
4f4fad27 | 843 | this->read_bufferram(mtd, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize); |
a5e7c7b4 AH |
844 | for (free = this->ecclayout->oobfree; free->length; ++free) { |
845 | int free_end = free->offset + free->length; | |
846 | if (free->offset < readend && free_end > readcol) { | |
847 | int st = max_t(int,free->offset,readcol); | |
848 | int ed = min_t(int,free_end,readend); | |
849 | int n = ed - st; | |
850 | memcpy(buf, oob_buf + st, n); | |
851 | buf += n; | |
852 | } | |
853 | } | |
854 | return 0; | |
855 | } | |
856 | ||
cd5f6346 | 857 | /** |
8593fbc6 | 858 | * onenand_do_read_oob - [MTD Interface] OneNAND read out-of-band |
cd5f6346 KP |
859 | * @param mtd MTD device structure |
860 | * @param from offset to read from | |
861 | * @param len number of bytes to read | |
862 | * @param retlen pointer to variable to store the number of read bytes | |
863 | * @param buf the databuffer to put data | |
a5e7c7b4 | 864 | * @param mode operation mode |
cd5f6346 KP |
865 | * |
866 | * OneNAND read out-of-band data from the spare area | |
867 | */ | |
211ac75f | 868 | static int onenand_do_read_oob(struct mtd_info *mtd, loff_t from, size_t len, |
a5e7c7b4 | 869 | size_t *retlen, u_char *buf, mtd_oob_mode_t mode) |
cd5f6346 KP |
870 | { |
871 | struct onenand_chip *this = mtd->priv; | |
a5e7c7b4 | 872 | int read = 0, thislen, column, oobsize; |
cd5f6346 KP |
873 | int ret = 0; |
874 | ||
875 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_oob: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); | |
876 | ||
877 | /* Initialize return length value */ | |
878 | *retlen = 0; | |
879 | ||
a5e7c7b4 AH |
880 | if (mode == MTD_OOB_AUTO) |
881 | oobsize = this->ecclayout->oobavail; | |
882 | else | |
883 | oobsize = mtd->oobsize; | |
884 | ||
885 | column = from & (mtd->oobsize - 1); | |
886 | ||
887 | if (unlikely(column >= oobsize)) { | |
211ac75f | 888 | printk(KERN_ERR "onenand_read_oob: Attempted to start read outside oob\n"); |
a5e7c7b4 AH |
889 | return -EINVAL; |
890 | } | |
891 | ||
cd5f6346 | 892 | /* Do not allow reads past end of device */ |
a5e7c7b4 AH |
893 | if (unlikely(from >= mtd->size || |
894 | column + len > ((mtd->size >> this->page_shift) - | |
895 | (from >> this->page_shift)) * oobsize)) { | |
211ac75f | 896 | printk(KERN_ERR "onenand_read_oob: Attempted to read beyond end of device\n"); |
cd5f6346 KP |
897 | return -EINVAL; |
898 | } | |
899 | ||
900 | /* Grab the lock and see if the device is available */ | |
901 | onenand_get_device(mtd, FL_READING); | |
902 | ||
cd5f6346 | 903 | while (read < len) { |
61a7e198 AB |
904 | cond_resched(); |
905 | ||
a5e7c7b4 | 906 | thislen = oobsize - column; |
cd5f6346 KP |
907 | thislen = min_t(int, thislen, len); |
908 | ||
909 | this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize); | |
910 | ||
911 | onenand_update_bufferram(mtd, from, 0); | |
912 | ||
913 | ret = this->wait(mtd, FL_READING); | |
914 | /* First copy data and check return value for ECC handling */ | |
915 | ||
a5e7c7b4 AH |
916 | if (mode == MTD_OOB_AUTO) |
917 | onenand_transfer_auto_oob(mtd, buf, column, thislen); | |
918 | else | |
919 | this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen); | |
cd5f6346 | 920 | |
f6272487 | 921 | if (ret) { |
211ac75f | 922 | printk(KERN_ERR "onenand_read_oob: read failed = 0x%x\n", ret); |
5b4246f1 | 923 | break; |
f6272487 KP |
924 | } |
925 | ||
cd5f6346 KP |
926 | read += thislen; |
927 | ||
928 | if (read == len) | |
929 | break; | |
930 | ||
cd5f6346 KP |
931 | buf += thislen; |
932 | ||
933 | /* Read more? */ | |
934 | if (read < len) { | |
935 | /* Page size */ | |
28318776 | 936 | from += mtd->writesize; |
cd5f6346 KP |
937 | column = 0; |
938 | } | |
939 | } | |
940 | ||
cd5f6346 KP |
941 | /* Deselect and wake up anyone waiting on the device */ |
942 | onenand_release_device(mtd); | |
943 | ||
944 | *retlen = read; | |
945 | return ret; | |
946 | } | |
947 | ||
8593fbc6 TG |
948 | /** |
949 | * onenand_read_oob - [MTD Interface] NAND write data and/or out-of-band | |
950 | * @mtd: MTD device structure | |
951 | * @from: offset to read from | |
952 | * @ops: oob operation description structure | |
953 | */ | |
954 | static int onenand_read_oob(struct mtd_info *mtd, loff_t from, | |
955 | struct mtd_oob_ops *ops) | |
956 | { | |
4f4fad27 | 957 | switch (ops->mode) { |
a5e7c7b4 AH |
958 | case MTD_OOB_PLACE: |
959 | case MTD_OOB_AUTO: | |
960 | break; | |
961 | case MTD_OOB_RAW: | |
4f4fad27 | 962 | /* Not implemented yet */ |
a5e7c7b4 AH |
963 | default: |
964 | return -EINVAL; | |
965 | } | |
66a1e421 | 966 | return onenand_do_read_oob(mtd, from + ops->ooboffs, ops->ooblen, |
a5e7c7b4 | 967 | &ops->oobretlen, ops->oobbuf, ops->mode); |
8593fbc6 TG |
968 | } |
969 | ||
211ac75f KP |
970 | /** |
971 | * onenand_bbt_wait - [DEFAULT] wait until the command is done | |
972 | * @param mtd MTD device structure | |
973 | * @param state state to select the max. timeout value | |
974 | * | |
975 | * Wait for command done. | |
976 | */ | |
977 | static int onenand_bbt_wait(struct mtd_info *mtd, int state) | |
978 | { | |
979 | struct onenand_chip *this = mtd->priv; | |
980 | unsigned long timeout; | |
981 | unsigned int interrupt; | |
982 | unsigned int ctrl; | |
983 | ||
984 | /* The 20 msec is enough */ | |
985 | timeout = jiffies + msecs_to_jiffies(20); | |
986 | while (time_before(jiffies, timeout)) { | |
987 | interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); | |
988 | if (interrupt & ONENAND_INT_MASTER) | |
989 | break; | |
990 | } | |
991 | /* To get correct interrupt status in timeout case */ | |
992 | interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); | |
993 | ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); | |
994 | ||
995 | if (ctrl & ONENAND_CTRL_ERROR) { | |
996 | printk(KERN_DEBUG "onenand_bbt_wait: controller error = 0x%04x\n", ctrl); | |
997 | /* Initial bad block case */ | |
998 | if (ctrl & ONENAND_CTRL_LOAD) | |
999 | return ONENAND_BBT_READ_ERROR; | |
1000 | return ONENAND_BBT_READ_FATAL_ERROR; | |
1001 | } | |
1002 | ||
1003 | if (interrupt & ONENAND_INT_READ) { | |
1004 | int ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS); | |
1005 | if (ecc & ONENAND_ECC_2BIT_ALL) | |
1006 | return ONENAND_BBT_READ_ERROR; | |
1007 | } else { | |
1008 | printk(KERN_ERR "onenand_bbt_wait: read timeout!" | |
1009 | "ctrl=0x%04x intr=0x%04x\n", ctrl, interrupt); | |
1010 | return ONENAND_BBT_READ_FATAL_ERROR; | |
1011 | } | |
1012 | ||
1013 | return 0; | |
1014 | } | |
1015 | ||
1016 | /** | |
1017 | * onenand_bbt_read_oob - [MTD Interface] OneNAND read out-of-band for bbt scan | |
1018 | * @param mtd MTD device structure | |
1019 | * @param from offset to read from | |
1020 | * @param @ops oob operation description structure | |
1021 | * | |
1022 | * OneNAND read out-of-band data from the spare area for bbt scan | |
1023 | */ | |
1024 | int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from, | |
1025 | struct mtd_oob_ops *ops) | |
1026 | { | |
1027 | struct onenand_chip *this = mtd->priv; | |
1028 | int read = 0, thislen, column; | |
1029 | int ret = 0; | |
1030 | size_t len = ops->ooblen; | |
1031 | u_char *buf = ops->oobbuf; | |
1032 | ||
5785bdd6 | 1033 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_bbt_read_oob: from = 0x%08x, len = %zi\n", (unsigned int) from, len); |
211ac75f KP |
1034 | |
1035 | /* Initialize return value */ | |
1036 | ops->oobretlen = 0; | |
1037 | ||
1038 | /* Do not allow reads past end of device */ | |
1039 | if (unlikely((from + len) > mtd->size)) { | |
1040 | printk(KERN_ERR "onenand_bbt_read_oob: Attempt read beyond end of device\n"); | |
1041 | return ONENAND_BBT_READ_FATAL_ERROR; | |
1042 | } | |
1043 | ||
1044 | /* Grab the lock and see if the device is available */ | |
1045 | onenand_get_device(mtd, FL_READING); | |
1046 | ||
1047 | column = from & (mtd->oobsize - 1); | |
1048 | ||
1049 | while (read < len) { | |
1050 | cond_resched(); | |
1051 | ||
1052 | thislen = mtd->oobsize - column; | |
1053 | thislen = min_t(int, thislen, len); | |
1054 | ||
1055 | this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize); | |
1056 | ||
1057 | onenand_update_bufferram(mtd, from, 0); | |
1058 | ||
1059 | ret = onenand_bbt_wait(mtd, FL_READING); | |
1060 | if (ret) | |
1061 | break; | |
1062 | ||
1063 | this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen); | |
1064 | read += thislen; | |
1065 | if (read == len) | |
1066 | break; | |
1067 | ||
1068 | buf += thislen; | |
1069 | ||
1070 | /* Read more? */ | |
1071 | if (read < len) { | |
1072 | /* Update Page size */ | |
1073 | from += mtd->writesize; | |
1074 | column = 0; | |
1075 | } | |
1076 | } | |
1077 | ||
1078 | /* Deselect and wake up anyone waiting on the device */ | |
1079 | onenand_release_device(mtd); | |
1080 | ||
1081 | ops->oobretlen = read; | |
1082 | return ret; | |
1083 | } | |
1084 | ||
cd5f6346 | 1085 | #ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE |
8e6ec690 KP |
1086 | /** |
1087 | * onenand_verify_oob - [GENERIC] verify the oob contents after a write | |
1088 | * @param mtd MTD device structure | |
1089 | * @param buf the databuffer to verify | |
1090 | * @param to offset to read from | |
8e6ec690 KP |
1091 | * |
1092 | */ | |
a5e7c7b4 | 1093 | static int onenand_verify_oob(struct mtd_info *mtd, const u_char *buf, loff_t to) |
8e6ec690 KP |
1094 | { |
1095 | struct onenand_chip *this = mtd->priv; | |
91014e9b | 1096 | char oobbuf[64]; |
8e6ec690 KP |
1097 | int status, i; |
1098 | ||
1099 | this->command(mtd, ONENAND_CMD_READOOB, to, mtd->oobsize); | |
1100 | onenand_update_bufferram(mtd, to, 0); | |
1101 | status = this->wait(mtd, FL_READING); | |
1102 | if (status) | |
1103 | return status; | |
1104 | ||
91014e9b KP |
1105 | this->read_bufferram(mtd, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize); |
1106 | for (i = 0; i < mtd->oobsize; i++) | |
1107 | if (buf[i] != 0xFF && buf[i] != oobbuf[i]) | |
8e6ec690 KP |
1108 | return -EBADMSG; |
1109 | ||
1110 | return 0; | |
1111 | } | |
1112 | ||
cd5f6346 | 1113 | /** |
8b29c0b6 AH |
1114 | * onenand_verify - [GENERIC] verify the chip contents after a write |
1115 | * @param mtd MTD device structure | |
1116 | * @param buf the databuffer to verify | |
1117 | * @param addr offset to read from | |
1118 | * @param len number of bytes to read and compare | |
cd5f6346 | 1119 | * |
cd5f6346 | 1120 | */ |
8b29c0b6 | 1121 | static int onenand_verify(struct mtd_info *mtd, const u_char *buf, loff_t addr, size_t len) |
cd5f6346 KP |
1122 | { |
1123 | struct onenand_chip *this = mtd->priv; | |
8b29c0b6 | 1124 | void __iomem *dataram; |
cd5f6346 | 1125 | int ret = 0; |
8b29c0b6 | 1126 | int thislen, column; |
cd5f6346 | 1127 | |
8b29c0b6 AH |
1128 | while (len != 0) { |
1129 | thislen = min_t(int, mtd->writesize, len); | |
1130 | column = addr & (mtd->writesize - 1); | |
1131 | if (column + thislen > mtd->writesize) | |
1132 | thislen = mtd->writesize - column; | |
60d84f97 | 1133 | |
8b29c0b6 | 1134 | this->command(mtd, ONENAND_CMD_READ, addr, mtd->writesize); |
cd5f6346 | 1135 | |
8b29c0b6 AH |
1136 | onenand_update_bufferram(mtd, addr, 0); |
1137 | ||
1138 | ret = this->wait(mtd, FL_READING); | |
1139 | if (ret) | |
1140 | return ret; | |
cd5f6346 | 1141 | |
8b29c0b6 | 1142 | onenand_update_bufferram(mtd, addr, 1); |
cd5f6346 | 1143 | |
8b29c0b6 AH |
1144 | dataram = this->base + ONENAND_DATARAM; |
1145 | dataram += onenand_bufferram_offset(mtd, ONENAND_DATARAM); | |
cd5f6346 | 1146 | |
8b29c0b6 AH |
1147 | if (memcmp(buf, dataram + column, thislen)) |
1148 | return -EBADMSG; | |
1149 | ||
1150 | len -= thislen; | |
1151 | buf += thislen; | |
1152 | addr += thislen; | |
1153 | } | |
d5c5e78a | 1154 | |
cd5f6346 KP |
1155 | return 0; |
1156 | } | |
1157 | #else | |
8b29c0b6 | 1158 | #define onenand_verify(...) (0) |
8e6ec690 | 1159 | #define onenand_verify_oob(...) (0) |
cd5f6346 KP |
1160 | #endif |
1161 | ||
60d84f97 | 1162 | #define NOTALIGNED(x) ((x & (this->subpagesize - 1)) != 0) |
cd5f6346 KP |
1163 | |
1164 | /** | |
9223a456 | 1165 | * onenand_write - [MTD Interface] write buffer to FLASH |
cd5f6346 KP |
1166 | * @param mtd MTD device structure |
1167 | * @param to offset to write to | |
1168 | * @param len number of bytes to write | |
1169 | * @param retlen pointer to variable to store the number of written bytes | |
1170 | * @param buf the data to write | |
cd5f6346 | 1171 | * |
9223a456 | 1172 | * Write with ECC |
cd5f6346 | 1173 | */ |
9223a456 TG |
1174 | static int onenand_write(struct mtd_info *mtd, loff_t to, size_t len, |
1175 | size_t *retlen, const u_char *buf) | |
cd5f6346 KP |
1176 | { |
1177 | struct onenand_chip *this = mtd->priv; | |
1178 | int written = 0; | |
1179 | int ret = 0; | |
60d84f97 | 1180 | int column, subpage; |
cd5f6346 | 1181 | |
9223a456 | 1182 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_write: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); |
cd5f6346 KP |
1183 | |
1184 | /* Initialize retlen, in case of early exit */ | |
1185 | *retlen = 0; | |
1186 | ||
1187 | /* Do not allow writes past end of device */ | |
1188 | if (unlikely((to + len) > mtd->size)) { | |
211ac75f | 1189 | printk(KERN_ERR "onenand_write: Attempt write to past end of device\n"); |
cd5f6346 KP |
1190 | return -EINVAL; |
1191 | } | |
1192 | ||
1193 | /* Reject writes, which are not page aligned */ | |
1194 | if (unlikely(NOTALIGNED(to)) || unlikely(NOTALIGNED(len))) { | |
211ac75f | 1195 | printk(KERN_ERR "onenand_write: Attempt to write not page aligned data\n"); |
cd5f6346 KP |
1196 | return -EINVAL; |
1197 | } | |
1198 | ||
60d84f97 | 1199 | column = to & (mtd->writesize - 1); |
60d84f97 | 1200 | |
cd5f6346 KP |
1201 | /* Grab the lock and see if the device is available */ |
1202 | onenand_get_device(mtd, FL_WRITING); | |
1203 | ||
1204 | /* Loop until all data write */ | |
1205 | while (written < len) { | |
81f38e11 | 1206 | int thislen = min_t(int, mtd->writesize - column, len - written); |
60d84f97 KP |
1207 | u_char *wbuf = (u_char *) buf; |
1208 | ||
61a7e198 AB |
1209 | cond_resched(); |
1210 | ||
81f38e11 | 1211 | this->command(mtd, ONENAND_CMD_BUFFERRAM, to, thislen); |
60d84f97 KP |
1212 | |
1213 | /* Partial page write */ | |
81f38e11 | 1214 | subpage = thislen < mtd->writesize; |
60d84f97 | 1215 | if (subpage) { |
60d84f97 | 1216 | memset(this->page_buf, 0xff, mtd->writesize); |
81f38e11 | 1217 | memcpy(this->page_buf + column, buf, thislen); |
60d84f97 | 1218 | wbuf = this->page_buf; |
60d84f97 | 1219 | } |
cd5f6346 | 1220 | |
81f38e11 | 1221 | this->write_bufferram(mtd, ONENAND_DATARAM, wbuf, 0, mtd->writesize); |
cd5f6346 KP |
1222 | this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0, mtd->oobsize); |
1223 | ||
28318776 | 1224 | this->command(mtd, ONENAND_CMD_PROG, to, mtd->writesize); |
cd5f6346 | 1225 | |
81f38e11 AH |
1226 | ret = this->wait(mtd, FL_WRITING); |
1227 | ||
60d84f97 | 1228 | /* In partial page write we don't update bufferram */ |
81f38e11 | 1229 | onenand_update_bufferram(mtd, to, !ret && !subpage); |
cd5f6346 | 1230 | |
cd5f6346 | 1231 | if (ret) { |
211ac75f | 1232 | printk(KERN_ERR "onenand_write: write filaed %d\n", ret); |
60d84f97 | 1233 | break; |
cd5f6346 KP |
1234 | } |
1235 | ||
cd5f6346 | 1236 | /* Only check verify write turn on */ |
8b29c0b6 | 1237 | ret = onenand_verify(mtd, (u_char *) wbuf, to, thislen); |
cd5f6346 | 1238 | if (ret) { |
211ac75f | 1239 | printk(KERN_ERR "onenand_write: verify failed %d\n", ret); |
60d84f97 | 1240 | break; |
cd5f6346 KP |
1241 | } |
1242 | ||
60d84f97 | 1243 | written += thislen; |
81f38e11 | 1244 | |
cd5f6346 KP |
1245 | if (written == len) |
1246 | break; | |
1247 | ||
60d84f97 | 1248 | column = 0; |
cd5f6346 KP |
1249 | to += thislen; |
1250 | buf += thislen; | |
1251 | } | |
1252 | ||
cd5f6346 KP |
1253 | /* Deselect and wake up anyone waiting on the device */ |
1254 | onenand_release_device(mtd); | |
1255 | ||
1256 | *retlen = written; | |
d5c5e78a | 1257 | |
cd5f6346 KP |
1258 | return ret; |
1259 | } | |
1260 | ||
a5e7c7b4 AH |
1261 | /** |
1262 | * onenand_fill_auto_oob - [Internal] oob auto-placement transfer | |
1263 | * @param mtd MTD device structure | |
1264 | * @param oob_buf oob buffer | |
1265 | * @param buf source address | |
1266 | * @param column oob offset to write to | |
1267 | * @param thislen oob length to write | |
1268 | */ | |
1269 | static int onenand_fill_auto_oob(struct mtd_info *mtd, u_char *oob_buf, | |
1270 | const u_char *buf, int column, int thislen) | |
1271 | { | |
1272 | struct onenand_chip *this = mtd->priv; | |
1273 | struct nand_oobfree *free; | |
1274 | int writecol = column; | |
1275 | int writeend = column + thislen; | |
1276 | int lastgap = 0; | |
1277 | ||
1278 | for (free = this->ecclayout->oobfree; free->length; ++free) { | |
1279 | if (writecol >= lastgap) | |
1280 | writecol += free->offset - lastgap; | |
1281 | if (writeend >= lastgap) | |
1282 | writeend += free->offset - lastgap; | |
1283 | lastgap = free->offset + free->length; | |
1284 | } | |
a5e7c7b4 AH |
1285 | for (free = this->ecclayout->oobfree; free->length; ++free) { |
1286 | int free_end = free->offset + free->length; | |
1287 | if (free->offset < writeend && free_end > writecol) { | |
1288 | int st = max_t(int,free->offset,writecol); | |
1289 | int ed = min_t(int,free_end,writeend); | |
1290 | int n = ed - st; | |
1291 | memcpy(oob_buf + st, buf, n); | |
1292 | buf += n; | |
1293 | } | |
1294 | } | |
1295 | return 0; | |
1296 | } | |
1297 | ||
cd5f6346 | 1298 | /** |
8593fbc6 | 1299 | * onenand_do_write_oob - [Internal] OneNAND write out-of-band |
cd5f6346 KP |
1300 | * @param mtd MTD device structure |
1301 | * @param to offset to write to | |
1302 | * @param len number of bytes to write | |
1303 | * @param retlen pointer to variable to store the number of written bytes | |
1304 | * @param buf the data to write | |
a5e7c7b4 | 1305 | * @param mode operation mode |
cd5f6346 KP |
1306 | * |
1307 | * OneNAND write out-of-band | |
1308 | */ | |
8593fbc6 | 1309 | static int onenand_do_write_oob(struct mtd_info *mtd, loff_t to, size_t len, |
a5e7c7b4 | 1310 | size_t *retlen, const u_char *buf, mtd_oob_mode_t mode) |
cd5f6346 KP |
1311 | { |
1312 | struct onenand_chip *this = mtd->priv; | |
a5e7c7b4 | 1313 | int column, ret = 0, oobsize; |
cd5f6346 | 1314 | int written = 0; |
91014e9b | 1315 | u_char *oobbuf; |
cd5f6346 KP |
1316 | |
1317 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_oob: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); | |
1318 | ||
1319 | /* Initialize retlen, in case of early exit */ | |
1320 | *retlen = 0; | |
1321 | ||
a5e7c7b4 AH |
1322 | if (mode == MTD_OOB_AUTO) |
1323 | oobsize = this->ecclayout->oobavail; | |
1324 | else | |
1325 | oobsize = mtd->oobsize; | |
1326 | ||
1327 | column = to & (mtd->oobsize - 1); | |
1328 | ||
1329 | if (unlikely(column >= oobsize)) { | |
211ac75f | 1330 | printk(KERN_ERR "onenand_write_oob: Attempted to start write outside oob\n"); |
a5e7c7b4 AH |
1331 | return -EINVAL; |
1332 | } | |
1333 | ||
52e4200a | 1334 | /* For compatibility with NAND: Do not allow write past end of page */ |
91014e9b | 1335 | if (unlikely(column + len > oobsize)) { |
211ac75f | 1336 | printk(KERN_ERR "onenand_write_oob: " |
52e4200a AH |
1337 | "Attempt to write past end of page\n"); |
1338 | return -EINVAL; | |
1339 | } | |
1340 | ||
a5e7c7b4 AH |
1341 | /* Do not allow reads past end of device */ |
1342 | if (unlikely(to >= mtd->size || | |
1343 | column + len > ((mtd->size >> this->page_shift) - | |
1344 | (to >> this->page_shift)) * oobsize)) { | |
211ac75f | 1345 | printk(KERN_ERR "onenand_write_oob: Attempted to write past end of device\n"); |
cd5f6346 KP |
1346 | return -EINVAL; |
1347 | } | |
1348 | ||
1349 | /* Grab the lock and see if the device is available */ | |
1350 | onenand_get_device(mtd, FL_WRITING); | |
1351 | ||
91014e9b KP |
1352 | oobbuf = this->page_buf + mtd->writesize; |
1353 | ||
cd5f6346 KP |
1354 | /* Loop until all data write */ |
1355 | while (written < len) { | |
a5e7c7b4 | 1356 | int thislen = min_t(int, oobsize, len - written); |
cd5f6346 | 1357 | |
61a7e198 AB |
1358 | cond_resched(); |
1359 | ||
cd5f6346 KP |
1360 | this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobsize); |
1361 | ||
34c10609 KP |
1362 | /* We send data to spare ram with oobsize |
1363 | * to prevent byte access */ | |
91014e9b | 1364 | memset(oobbuf, 0xff, mtd->oobsize); |
a5e7c7b4 | 1365 | if (mode == MTD_OOB_AUTO) |
91014e9b | 1366 | onenand_fill_auto_oob(mtd, oobbuf, buf, column, thislen); |
a5e7c7b4 | 1367 | else |
91014e9b KP |
1368 | memcpy(oobbuf + column, buf, thislen); |
1369 | this->write_bufferram(mtd, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize); | |
cd5f6346 KP |
1370 | |
1371 | this->command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize); | |
1372 | ||
1373 | onenand_update_bufferram(mtd, to, 0); | |
1374 | ||
8e6ec690 KP |
1375 | ret = this->wait(mtd, FL_WRITING); |
1376 | if (ret) { | |
211ac75f | 1377 | printk(KERN_ERR "onenand_write_oob: write failed %d\n", ret); |
5b4246f1 | 1378 | break; |
8e6ec690 KP |
1379 | } |
1380 | ||
91014e9b | 1381 | ret = onenand_verify_oob(mtd, oobbuf, to); |
8e6ec690 | 1382 | if (ret) { |
211ac75f | 1383 | printk(KERN_ERR "onenand_write_oob: verify failed %d\n", ret); |
5b4246f1 | 1384 | break; |
8e6ec690 | 1385 | } |
cd5f6346 KP |
1386 | |
1387 | written += thislen; | |
cd5f6346 KP |
1388 | if (written == len) |
1389 | break; | |
1390 | ||
a5e7c7b4 | 1391 | to += mtd->writesize; |
cd5f6346 | 1392 | buf += thislen; |
a5e7c7b4 | 1393 | column = 0; |
cd5f6346 KP |
1394 | } |
1395 | ||
cd5f6346 KP |
1396 | /* Deselect and wake up anyone waiting on the device */ |
1397 | onenand_release_device(mtd); | |
1398 | ||
1399 | *retlen = written; | |
d5c5e78a | 1400 | |
8e6ec690 | 1401 | return ret; |
cd5f6346 KP |
1402 | } |
1403 | ||
8593fbc6 TG |
1404 | /** |
1405 | * onenand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
1406 | * @mtd: MTD device structure | |
1407 | * @from: offset to read from | |
1408 | * @ops: oob operation description structure | |
1409 | */ | |
1410 | static int onenand_write_oob(struct mtd_info *mtd, loff_t to, | |
1411 | struct mtd_oob_ops *ops) | |
1412 | { | |
4f4fad27 | 1413 | switch (ops->mode) { |
a5e7c7b4 AH |
1414 | case MTD_OOB_PLACE: |
1415 | case MTD_OOB_AUTO: | |
1416 | break; | |
1417 | case MTD_OOB_RAW: | |
4f4fad27 | 1418 | /* Not implemented yet */ |
a5e7c7b4 AH |
1419 | default: |
1420 | return -EINVAL; | |
1421 | } | |
66a1e421 | 1422 | return onenand_do_write_oob(mtd, to + ops->ooboffs, ops->ooblen, |
a5e7c7b4 | 1423 | &ops->oobretlen, ops->oobbuf, ops->mode); |
8593fbc6 TG |
1424 | } |
1425 | ||
cdc00130 KP |
1426 | /** |
1427 | * onenand_block_checkbad - [GENERIC] Check if a block is marked bad | |
1428 | * @param mtd MTD device structure | |
1429 | * @param ofs offset from device start | |
1430 | * @param getchip 0, if the chip is already selected | |
1431 | * @param allowbbt 1, if its allowed to access the bbt area | |
1432 | * | |
1433 | * Check, if the block is bad. Either by reading the bad block table or | |
1434 | * calling of the scan function. | |
1435 | */ | |
1436 | static int onenand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, int allowbbt) | |
1437 | { | |
1438 | struct onenand_chip *this = mtd->priv; | |
1439 | struct bbm_info *bbm = this->bbm; | |
1440 | ||
1441 | /* Return info from the table */ | |
1442 | return bbm->isbad_bbt(mtd, ofs, allowbbt); | |
1443 | } | |
1444 | ||
cd5f6346 KP |
1445 | /** |
1446 | * onenand_erase - [MTD Interface] erase block(s) | |
1447 | * @param mtd MTD device structure | |
1448 | * @param instr erase instruction | |
1449 | * | |
1450 | * Erase one ore more blocks | |
1451 | */ | |
1452 | static int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) | |
1453 | { | |
1454 | struct onenand_chip *this = mtd->priv; | |
1455 | unsigned int block_size; | |
1456 | loff_t addr; | |
1457 | int len; | |
1458 | int ret = 0; | |
1459 | ||
1460 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len); | |
1461 | ||
1462 | block_size = (1 << this->erase_shift); | |
1463 | ||
1464 | /* Start address must align on block boundary */ | |
1465 | if (unlikely(instr->addr & (block_size - 1))) { | |
211ac75f | 1466 | printk(KERN_ERR "onenand_erase: Unaligned address\n"); |
cd5f6346 KP |
1467 | return -EINVAL; |
1468 | } | |
1469 | ||
1470 | /* Length must align on block boundary */ | |
1471 | if (unlikely(instr->len & (block_size - 1))) { | |
211ac75f | 1472 | printk(KERN_ERR "onenand_erase: Length not block aligned\n"); |
cd5f6346 KP |
1473 | return -EINVAL; |
1474 | } | |
1475 | ||
1476 | /* Do not allow erase past end of device */ | |
1477 | if (unlikely((instr->len + instr->addr) > mtd->size)) { | |
211ac75f | 1478 | printk(KERN_ERR "onenand_erase: Erase past end of device\n"); |
cd5f6346 KP |
1479 | return -EINVAL; |
1480 | } | |
1481 | ||
1482 | instr->fail_addr = 0xffffffff; | |
1483 | ||
1484 | /* Grab the lock and see if the device is available */ | |
1485 | onenand_get_device(mtd, FL_ERASING); | |
1486 | ||
1487 | /* Loop throught the pages */ | |
1488 | len = instr->len; | |
1489 | addr = instr->addr; | |
1490 | ||
1491 | instr->state = MTD_ERASING; | |
1492 | ||
1493 | while (len) { | |
61a7e198 | 1494 | cond_resched(); |
cd5f6346 | 1495 | |
cdc00130 KP |
1496 | /* Check if we have a bad block, we do not erase bad blocks */ |
1497 | if (onenand_block_checkbad(mtd, addr, 0, 0)) { | |
1498 | printk (KERN_WARNING "onenand_erase: attempt to erase a bad block at addr 0x%08x\n", (unsigned int) addr); | |
1499 | instr->state = MTD_ERASE_FAILED; | |
1500 | goto erase_exit; | |
1501 | } | |
cd5f6346 KP |
1502 | |
1503 | this->command(mtd, ONENAND_CMD_ERASE, addr, block_size); | |
1504 | ||
480b9dfb AH |
1505 | onenand_invalidate_bufferram(mtd, addr, block_size); |
1506 | ||
cd5f6346 KP |
1507 | ret = this->wait(mtd, FL_ERASING); |
1508 | /* Check, if it is write protected */ | |
1509 | if (ret) { | |
211ac75f | 1510 | printk(KERN_ERR "onenand_erase: Failed erase, block %d\n", (unsigned) (addr >> this->erase_shift)); |
cd5f6346 KP |
1511 | instr->state = MTD_ERASE_FAILED; |
1512 | instr->fail_addr = addr; | |
1513 | goto erase_exit; | |
1514 | } | |
1515 | ||
1516 | len -= block_size; | |
1517 | addr += block_size; | |
1518 | } | |
1519 | ||
1520 | instr->state = MTD_ERASE_DONE; | |
1521 | ||
1522 | erase_exit: | |
1523 | ||
1524 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1525 | /* Do call back function */ | |
1526 | if (!ret) | |
1527 | mtd_erase_callback(instr); | |
1528 | ||
1529 | /* Deselect and wake up anyone waiting on the device */ | |
1530 | onenand_release_device(mtd); | |
1531 | ||
1532 | return ret; | |
1533 | } | |
1534 | ||
1535 | /** | |
1536 | * onenand_sync - [MTD Interface] sync | |
1537 | * @param mtd MTD device structure | |
1538 | * | |
1539 | * Sync is actually a wait for chip ready function | |
1540 | */ | |
1541 | static void onenand_sync(struct mtd_info *mtd) | |
1542 | { | |
1543 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_sync: called\n"); | |
1544 | ||
1545 | /* Grab the lock and see if the device is available */ | |
1546 | onenand_get_device(mtd, FL_SYNCING); | |
1547 | ||
1548 | /* Release it and go back */ | |
1549 | onenand_release_device(mtd); | |
1550 | } | |
1551 | ||
1552 | /** | |
1553 | * onenand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad | |
1554 | * @param mtd MTD device structure | |
1555 | * @param ofs offset relative to mtd start | |
cdc00130 KP |
1556 | * |
1557 | * Check whether the block is bad | |
cd5f6346 KP |
1558 | */ |
1559 | static int onenand_block_isbad(struct mtd_info *mtd, loff_t ofs) | |
1560 | { | |
cdc00130 KP |
1561 | /* Check for invalid offset */ |
1562 | if (ofs > mtd->size) | |
1563 | return -EINVAL; | |
1564 | ||
1565 | return onenand_block_checkbad(mtd, ofs, 1, 0); | |
1566 | } | |
1567 | ||
1568 | /** | |
1569 | * onenand_default_block_markbad - [DEFAULT] mark a block bad | |
1570 | * @param mtd MTD device structure | |
1571 | * @param ofs offset from device start | |
1572 | * | |
1573 | * This is the default implementation, which can be overridden by | |
1574 | * a hardware specific driver. | |
1575 | */ | |
1576 | static int onenand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
1577 | { | |
1578 | struct onenand_chip *this = mtd->priv; | |
1579 | struct bbm_info *bbm = this->bbm; | |
1580 | u_char buf[2] = {0, 0}; | |
1581 | size_t retlen; | |
1582 | int block; | |
1583 | ||
1584 | /* Get block number */ | |
1585 | block = ((int) ofs) >> bbm->bbt_erase_shift; | |
1586 | if (bbm->bbt) | |
1587 | bbm->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); | |
1588 | ||
1589 | /* We write two bytes, so we dont have to mess with 16 bit access */ | |
1590 | ofs += mtd->oobsize + (bbm->badblockpos & ~0x01); | |
a5e7c7b4 | 1591 | return onenand_do_write_oob(mtd, ofs , 2, &retlen, buf, MTD_OOB_PLACE); |
cd5f6346 KP |
1592 | } |
1593 | ||
1594 | /** | |
1595 | * onenand_block_markbad - [MTD Interface] Mark the block at the given offset as bad | |
1596 | * @param mtd MTD device structure | |
1597 | * @param ofs offset relative to mtd start | |
cdc00130 KP |
1598 | * |
1599 | * Mark the block as bad | |
cd5f6346 KP |
1600 | */ |
1601 | static int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
1602 | { | |
cdc00130 KP |
1603 | struct onenand_chip *this = mtd->priv; |
1604 | int ret; | |
1605 | ||
1606 | ret = onenand_block_isbad(mtd, ofs); | |
1607 | if (ret) { | |
1608 | /* If it was bad already, return success and do nothing */ | |
1609 | if (ret > 0) | |
1610 | return 0; | |
1611 | return ret; | |
1612 | } | |
1613 | ||
1614 | return this->block_markbad(mtd, ofs); | |
cd5f6346 KP |
1615 | } |
1616 | ||
1617 | /** | |
08f782b6 | 1618 | * onenand_do_lock_cmd - [OneNAND Interface] Lock or unlock block(s) |
cd5f6346 KP |
1619 | * @param mtd MTD device structure |
1620 | * @param ofs offset relative to mtd start | |
08f782b6 | 1621 | * @param len number of bytes to lock or unlock |
cd5f6346 | 1622 | * |
08f782b6 | 1623 | * Lock or unlock one or more blocks |
cd5f6346 | 1624 | */ |
08f782b6 | 1625 | static int onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs, size_t len, int cmd) |
cd5f6346 KP |
1626 | { |
1627 | struct onenand_chip *this = mtd->priv; | |
1628 | int start, end, block, value, status; | |
08f782b6 | 1629 | int wp_status_mask; |
cd5f6346 KP |
1630 | |
1631 | start = ofs >> this->erase_shift; | |
1632 | end = len >> this->erase_shift; | |
1633 | ||
08f782b6 KP |
1634 | if (cmd == ONENAND_CMD_LOCK) |
1635 | wp_status_mask = ONENAND_WP_LS; | |
1636 | else | |
1637 | wp_status_mask = ONENAND_WP_US; | |
1638 | ||
cd5f6346 | 1639 | /* Continuous lock scheme */ |
28b79ff9 | 1640 | if (this->options & ONENAND_HAS_CONT_LOCK) { |
cd5f6346 KP |
1641 | /* Set start block address */ |
1642 | this->write_word(start, this->base + ONENAND_REG_START_BLOCK_ADDRESS); | |
1643 | /* Set end block address */ | |
28b79ff9 | 1644 | this->write_word(start + end - 1, this->base + ONENAND_REG_END_BLOCK_ADDRESS); |
08f782b6 KP |
1645 | /* Write lock command */ |
1646 | this->command(mtd, cmd, 0, 0); | |
cd5f6346 KP |
1647 | |
1648 | /* There's no return value */ | |
08f782b6 | 1649 | this->wait(mtd, FL_LOCKING); |
cd5f6346 KP |
1650 | |
1651 | /* Sanity check */ | |
1652 | while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) | |
1653 | & ONENAND_CTRL_ONGO) | |
1654 | continue; | |
1655 | ||
1656 | /* Check lock status */ | |
1657 | status = this->read_word(this->base + ONENAND_REG_WP_STATUS); | |
08f782b6 | 1658 | if (!(status & wp_status_mask)) |
cd5f6346 KP |
1659 | printk(KERN_ERR "wp status = 0x%x\n", status); |
1660 | ||
1661 | return 0; | |
1662 | } | |
1663 | ||
1664 | /* Block lock scheme */ | |
28b79ff9 | 1665 | for (block = start; block < start + end; block++) { |
20ba89a3 KP |
1666 | /* Set block address */ |
1667 | value = onenand_block_address(this, block); | |
1668 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); | |
1669 | /* Select DataRAM for DDP */ | |
1670 | value = onenand_bufferram_address(this, block); | |
1671 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); | |
cd5f6346 KP |
1672 | /* Set start block address */ |
1673 | this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS); | |
08f782b6 KP |
1674 | /* Write lock command */ |
1675 | this->command(mtd, cmd, 0, 0); | |
cd5f6346 KP |
1676 | |
1677 | /* There's no return value */ | |
08f782b6 | 1678 | this->wait(mtd, FL_LOCKING); |
cd5f6346 KP |
1679 | |
1680 | /* Sanity check */ | |
1681 | while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) | |
1682 | & ONENAND_CTRL_ONGO) | |
1683 | continue; | |
1684 | ||
cd5f6346 KP |
1685 | /* Check lock status */ |
1686 | status = this->read_word(this->base + ONENAND_REG_WP_STATUS); | |
08f782b6 | 1687 | if (!(status & wp_status_mask)) |
cd5f6346 KP |
1688 | printk(KERN_ERR "block = %d, wp status = 0x%x\n", block, status); |
1689 | } | |
d5c5e78a | 1690 | |
cd5f6346 KP |
1691 | return 0; |
1692 | } | |
1693 | ||
08f782b6 KP |
1694 | /** |
1695 | * onenand_lock - [MTD Interface] Lock block(s) | |
1696 | * @param mtd MTD device structure | |
1697 | * @param ofs offset relative to mtd start | |
1698 | * @param len number of bytes to unlock | |
1699 | * | |
1700 | * Lock one or more blocks | |
1701 | */ | |
1702 | static int onenand_lock(struct mtd_info *mtd, loff_t ofs, size_t len) | |
1703 | { | |
1704 | return onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_LOCK); | |
1705 | } | |
1706 | ||
08f782b6 KP |
1707 | /** |
1708 | * onenand_unlock - [MTD Interface] Unlock block(s) | |
1709 | * @param mtd MTD device structure | |
1710 | * @param ofs offset relative to mtd start | |
1711 | * @param len number of bytes to unlock | |
1712 | * | |
1713 | * Unlock one or more blocks | |
1714 | */ | |
1715 | static int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len) | |
1716 | { | |
1717 | return onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK); | |
1718 | } | |
1719 | ||
28b79ff9 KP |
1720 | /** |
1721 | * onenand_check_lock_status - [OneNAND Interface] Check lock status | |
1722 | * @param this onenand chip data structure | |
1723 | * | |
1724 | * Check lock status | |
1725 | */ | |
1726 | static void onenand_check_lock_status(struct onenand_chip *this) | |
1727 | { | |
1728 | unsigned int value, block, status; | |
1729 | unsigned int end; | |
1730 | ||
1731 | end = this->chipsize >> this->erase_shift; | |
1732 | for (block = 0; block < end; block++) { | |
1733 | /* Set block address */ | |
1734 | value = onenand_block_address(this, block); | |
1735 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); | |
1736 | /* Select DataRAM for DDP */ | |
1737 | value = onenand_bufferram_address(this, block); | |
1738 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); | |
1739 | /* Set start block address */ | |
1740 | this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS); | |
1741 | ||
1742 | /* Check lock status */ | |
1743 | status = this->read_word(this->base + ONENAND_REG_WP_STATUS); | |
1744 | if (!(status & ONENAND_WP_US)) | |
1745 | printk(KERN_ERR "block = %d, wp status = 0x%x\n", block, status); | |
1746 | } | |
1747 | } | |
1748 | ||
1749 | /** | |
1750 | * onenand_unlock_all - [OneNAND Interface] unlock all blocks | |
1751 | * @param mtd MTD device structure | |
1752 | * | |
1753 | * Unlock all blocks | |
1754 | */ | |
1755 | static int onenand_unlock_all(struct mtd_info *mtd) | |
1756 | { | |
1757 | struct onenand_chip *this = mtd->priv; | |
1758 | ||
1759 | if (this->options & ONENAND_HAS_UNLOCK_ALL) { | |
10b7a2bd KP |
1760 | /* Set start block address */ |
1761 | this->write_word(0, this->base + ONENAND_REG_START_BLOCK_ADDRESS); | |
28b79ff9 KP |
1762 | /* Write unlock command */ |
1763 | this->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0, 0); | |
1764 | ||
1765 | /* There's no return value */ | |
08f782b6 | 1766 | this->wait(mtd, FL_LOCKING); |
28b79ff9 KP |
1767 | |
1768 | /* Sanity check */ | |
1769 | while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) | |
1770 | & ONENAND_CTRL_ONGO) | |
1771 | continue; | |
1772 | ||
1773 | /* Workaround for all block unlock in DDP */ | |
738d61f5 | 1774 | if (ONENAND_IS_DDP(this)) { |
28b79ff9 | 1775 | /* 1st block on another chip */ |
10b7a2bd KP |
1776 | loff_t ofs = this->chipsize >> 1; |
1777 | size_t len = mtd->erasesize; | |
28b79ff9 KP |
1778 | |
1779 | onenand_unlock(mtd, ofs, len); | |
1780 | } | |
1781 | ||
1782 | onenand_check_lock_status(this); | |
1783 | ||
1784 | return 0; | |
1785 | } | |
1786 | ||
08f782b6 | 1787 | onenand_unlock(mtd, 0x0, this->chipsize); |
28b79ff9 KP |
1788 | |
1789 | return 0; | |
1790 | } | |
1791 | ||
493c6460 KP |
1792 | #ifdef CONFIG_MTD_ONENAND_OTP |
1793 | ||
1794 | /* Interal OTP operation */ | |
1795 | typedef int (*otp_op_t)(struct mtd_info *mtd, loff_t form, size_t len, | |
1796 | size_t *retlen, u_char *buf); | |
1797 | ||
1798 | /** | |
1799 | * do_otp_read - [DEFAULT] Read OTP block area | |
1800 | * @param mtd MTD device structure | |
1801 | * @param from The offset to read | |
1802 | * @param len number of bytes to read | |
1803 | * @param retlen pointer to variable to store the number of readbytes | |
1804 | * @param buf the databuffer to put/get data | |
1805 | * | |
1806 | * Read OTP block area. | |
1807 | */ | |
1808 | static int do_otp_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1809 | size_t *retlen, u_char *buf) | |
1810 | { | |
1811 | struct onenand_chip *this = mtd->priv; | |
1812 | int ret; | |
1813 | ||
1814 | /* Enter OTP access mode */ | |
1815 | this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0); | |
1816 | this->wait(mtd, FL_OTPING); | |
1817 | ||
1818 | ret = mtd->read(mtd, from, len, retlen, buf); | |
1819 | ||
1820 | /* Exit OTP access mode */ | |
1821 | this->command(mtd, ONENAND_CMD_RESET, 0, 0); | |
1822 | this->wait(mtd, FL_RESETING); | |
1823 | ||
1824 | return ret; | |
1825 | } | |
1826 | ||
1827 | /** | |
1828 | * do_otp_write - [DEFAULT] Write OTP block area | |
1829 | * @param mtd MTD device structure | |
1830 | * @param from The offset to write | |
1831 | * @param len number of bytes to write | |
1832 | * @param retlen pointer to variable to store the number of write bytes | |
1833 | * @param buf the databuffer to put/get data | |
1834 | * | |
1835 | * Write OTP block area. | |
1836 | */ | |
1837 | static int do_otp_write(struct mtd_info *mtd, loff_t from, size_t len, | |
1838 | size_t *retlen, u_char *buf) | |
1839 | { | |
1840 | struct onenand_chip *this = mtd->priv; | |
1841 | unsigned char *pbuf = buf; | |
1842 | int ret; | |
1843 | ||
1844 | /* Force buffer page aligned */ | |
28318776 | 1845 | if (len < mtd->writesize) { |
493c6460 | 1846 | memcpy(this->page_buf, buf, len); |
28318776 | 1847 | memset(this->page_buf + len, 0xff, mtd->writesize - len); |
493c6460 | 1848 | pbuf = this->page_buf; |
28318776 | 1849 | len = mtd->writesize; |
493c6460 KP |
1850 | } |
1851 | ||
1852 | /* Enter OTP access mode */ | |
1853 | this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0); | |
1854 | this->wait(mtd, FL_OTPING); | |
1855 | ||
1856 | ret = mtd->write(mtd, from, len, retlen, pbuf); | |
1857 | ||
1858 | /* Exit OTP access mode */ | |
1859 | this->command(mtd, ONENAND_CMD_RESET, 0, 0); | |
1860 | this->wait(mtd, FL_RESETING); | |
1861 | ||
1862 | return ret; | |
1863 | } | |
1864 | ||
1865 | /** | |
1866 | * do_otp_lock - [DEFAULT] Lock OTP block area | |
1867 | * @param mtd MTD device structure | |
1868 | * @param from The offset to lock | |
1869 | * @param len number of bytes to lock | |
1870 | * @param retlen pointer to variable to store the number of lock bytes | |
1871 | * @param buf the databuffer to put/get data | |
1872 | * | |
1873 | * Lock OTP block area. | |
1874 | */ | |
1875 | static int do_otp_lock(struct mtd_info *mtd, loff_t from, size_t len, | |
1876 | size_t *retlen, u_char *buf) | |
1877 | { | |
1878 | struct onenand_chip *this = mtd->priv; | |
1879 | int ret; | |
1880 | ||
1881 | /* Enter OTP access mode */ | |
1882 | this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0); | |
1883 | this->wait(mtd, FL_OTPING); | |
1884 | ||
a5e7c7b4 | 1885 | ret = onenand_do_write_oob(mtd, from, len, retlen, buf, MTD_OOB_PLACE); |
493c6460 KP |
1886 | |
1887 | /* Exit OTP access mode */ | |
1888 | this->command(mtd, ONENAND_CMD_RESET, 0, 0); | |
1889 | this->wait(mtd, FL_RESETING); | |
1890 | ||
1891 | return ret; | |
1892 | } | |
1893 | ||
1894 | /** | |
1895 | * onenand_otp_walk - [DEFAULT] Handle OTP operation | |
1896 | * @param mtd MTD device structure | |
1897 | * @param from The offset to read/write | |
1898 | * @param len number of bytes to read/write | |
1899 | * @param retlen pointer to variable to store the number of read bytes | |
1900 | * @param buf the databuffer to put/get data | |
1901 | * @param action do given action | |
1902 | * @param mode specify user and factory | |
1903 | * | |
1904 | * Handle OTP operation. | |
1905 | */ | |
1906 | static int onenand_otp_walk(struct mtd_info *mtd, loff_t from, size_t len, | |
1907 | size_t *retlen, u_char *buf, | |
1908 | otp_op_t action, int mode) | |
1909 | { | |
1910 | struct onenand_chip *this = mtd->priv; | |
1911 | int otp_pages; | |
1912 | int density; | |
1913 | int ret = 0; | |
1914 | ||
1915 | *retlen = 0; | |
1916 | ||
1917 | density = this->device_id >> ONENAND_DEVICE_DENSITY_SHIFT; | |
1918 | if (density < ONENAND_DEVICE_DENSITY_512Mb) | |
1919 | otp_pages = 20; | |
1920 | else | |
1921 | otp_pages = 10; | |
1922 | ||
1923 | if (mode == MTD_OTP_FACTORY) { | |
28318776 | 1924 | from += mtd->writesize * otp_pages; |
493c6460 KP |
1925 | otp_pages = 64 - otp_pages; |
1926 | } | |
1927 | ||
1928 | /* Check User/Factory boundary */ | |
28318776 | 1929 | if (((mtd->writesize * otp_pages) - (from + len)) < 0) |
493c6460 KP |
1930 | return 0; |
1931 | ||
1932 | while (len > 0 && otp_pages > 0) { | |
1933 | if (!action) { /* OTP Info functions */ | |
1934 | struct otp_info *otpinfo; | |
1935 | ||
1936 | len -= sizeof(struct otp_info); | |
1937 | if (len <= 0) | |
1938 | return -ENOSPC; | |
1939 | ||
1940 | otpinfo = (struct otp_info *) buf; | |
1941 | otpinfo->start = from; | |
28318776 | 1942 | otpinfo->length = mtd->writesize; |
493c6460 KP |
1943 | otpinfo->locked = 0; |
1944 | ||
28318776 | 1945 | from += mtd->writesize; |
493c6460 KP |
1946 | buf += sizeof(struct otp_info); |
1947 | *retlen += sizeof(struct otp_info); | |
1948 | } else { | |
1949 | size_t tmp_retlen; | |
1950 | int size = len; | |
1951 | ||
1952 | ret = action(mtd, from, len, &tmp_retlen, buf); | |
1953 | ||
1954 | buf += size; | |
1955 | len -= size; | |
1956 | *retlen += size; | |
1957 | ||
1958 | if (ret < 0) | |
1959 | return ret; | |
1960 | } | |
1961 | otp_pages--; | |
1962 | } | |
1963 | ||
1964 | return 0; | |
1965 | } | |
1966 | ||
1967 | /** | |
1968 | * onenand_get_fact_prot_info - [MTD Interface] Read factory OTP info | |
1969 | * @param mtd MTD device structure | |
1970 | * @param buf the databuffer to put/get data | |
1971 | * @param len number of bytes to read | |
1972 | * | |
1973 | * Read factory OTP info. | |
1974 | */ | |
1975 | static int onenand_get_fact_prot_info(struct mtd_info *mtd, | |
1976 | struct otp_info *buf, size_t len) | |
1977 | { | |
1978 | size_t retlen; | |
1979 | int ret; | |
1980 | ||
1981 | ret = onenand_otp_walk(mtd, 0, len, &retlen, (u_char *) buf, NULL, MTD_OTP_FACTORY); | |
1982 | ||
1983 | return ret ? : retlen; | |
1984 | } | |
1985 | ||
1986 | /** | |
1987 | * onenand_read_fact_prot_reg - [MTD Interface] Read factory OTP area | |
1988 | * @param mtd MTD device structure | |
1989 | * @param from The offset to read | |
1990 | * @param len number of bytes to read | |
1991 | * @param retlen pointer to variable to store the number of read bytes | |
1992 | * @param buf the databuffer to put/get data | |
1993 | * | |
1994 | * Read factory OTP area. | |
1995 | */ | |
1996 | static int onenand_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, | |
1997 | size_t len, size_t *retlen, u_char *buf) | |
1998 | { | |
1999 | return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_read, MTD_OTP_FACTORY); | |
2000 | } | |
2001 | ||
2002 | /** | |
2003 | * onenand_get_user_prot_info - [MTD Interface] Read user OTP info | |
2004 | * @param mtd MTD device structure | |
2005 | * @param buf the databuffer to put/get data | |
2006 | * @param len number of bytes to read | |
2007 | * | |
2008 | * Read user OTP info. | |
2009 | */ | |
2010 | static int onenand_get_user_prot_info(struct mtd_info *mtd, | |
2011 | struct otp_info *buf, size_t len) | |
2012 | { | |
2013 | size_t retlen; | |
2014 | int ret; | |
2015 | ||
2016 | ret = onenand_otp_walk(mtd, 0, len, &retlen, (u_char *) buf, NULL, MTD_OTP_USER); | |
2017 | ||
2018 | return ret ? : retlen; | |
2019 | } | |
2020 | ||
2021 | /** | |
2022 | * onenand_read_user_prot_reg - [MTD Interface] Read user OTP area | |
2023 | * @param mtd MTD device structure | |
2024 | * @param from The offset to read | |
2025 | * @param len number of bytes to read | |
2026 | * @param retlen pointer to variable to store the number of read bytes | |
2027 | * @param buf the databuffer to put/get data | |
2028 | * | |
2029 | * Read user OTP area. | |
2030 | */ | |
2031 | static int onenand_read_user_prot_reg(struct mtd_info *mtd, loff_t from, | |
2032 | size_t len, size_t *retlen, u_char *buf) | |
2033 | { | |
2034 | return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_read, MTD_OTP_USER); | |
2035 | } | |
2036 | ||
2037 | /** | |
2038 | * onenand_write_user_prot_reg - [MTD Interface] Write user OTP area | |
2039 | * @param mtd MTD device structure | |
2040 | * @param from The offset to write | |
2041 | * @param len number of bytes to write | |
2042 | * @param retlen pointer to variable to store the number of write bytes | |
2043 | * @param buf the databuffer to put/get data | |
2044 | * | |
2045 | * Write user OTP area. | |
2046 | */ | |
2047 | static int onenand_write_user_prot_reg(struct mtd_info *mtd, loff_t from, | |
2048 | size_t len, size_t *retlen, u_char *buf) | |
2049 | { | |
2050 | return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_write, MTD_OTP_USER); | |
2051 | } | |
2052 | ||
2053 | /** | |
2054 | * onenand_lock_user_prot_reg - [MTD Interface] Lock user OTP area | |
2055 | * @param mtd MTD device structure | |
2056 | * @param from The offset to lock | |
2057 | * @param len number of bytes to unlock | |
2058 | * | |
2059 | * Write lock mark on spare area in page 0 in OTP block | |
2060 | */ | |
2061 | static int onenand_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, | |
2062 | size_t len) | |
2063 | { | |
2064 | unsigned char oob_buf[64]; | |
2065 | size_t retlen; | |
2066 | int ret; | |
2067 | ||
2068 | memset(oob_buf, 0xff, mtd->oobsize); | |
2069 | /* | |
2070 | * Note: OTP lock operation | |
2071 | * OTP block : 0xXXFC | |
2072 | * 1st block : 0xXXF3 (If chip support) | |
2073 | * Both : 0xXXF0 (If chip support) | |
2074 | */ | |
2075 | oob_buf[ONENAND_OTP_LOCK_OFFSET] = 0xFC; | |
2076 | ||
2077 | /* | |
2078 | * Write lock mark to 8th word of sector0 of page0 of the spare0. | |
2079 | * We write 16 bytes spare area instead of 2 bytes. | |
2080 | */ | |
2081 | from = 0; | |
2082 | len = 16; | |
2083 | ||
2084 | ret = onenand_otp_walk(mtd, from, len, &retlen, oob_buf, do_otp_lock, MTD_OTP_USER); | |
2085 | ||
2086 | return ret ? : retlen; | |
2087 | } | |
2088 | #endif /* CONFIG_MTD_ONENAND_OTP */ | |
2089 | ||
28b79ff9 | 2090 | /** |
75384b0d | 2091 | * onenand_check_features - Check and set OneNAND features |
28b79ff9 KP |
2092 | * @param mtd MTD data structure |
2093 | * | |
75384b0d KP |
2094 | * Check and set OneNAND features |
2095 | * - lock scheme | |
28b79ff9 | 2096 | */ |
75384b0d | 2097 | static void onenand_check_features(struct mtd_info *mtd) |
28b79ff9 KP |
2098 | { |
2099 | struct onenand_chip *this = mtd->priv; | |
2100 | unsigned int density, process; | |
2101 | ||
2102 | /* Lock scheme depends on density and process */ | |
2103 | density = this->device_id >> ONENAND_DEVICE_DENSITY_SHIFT; | |
2104 | process = this->version_id >> ONENAND_VERSION_PROCESS_SHIFT; | |
2105 | ||
2106 | /* Lock scheme */ | |
2107 | if (density >= ONENAND_DEVICE_DENSITY_1Gb) { | |
2108 | /* A-Die has all block unlock */ | |
2109 | if (process) { | |
2110 | printk(KERN_DEBUG "Chip support all block unlock\n"); | |
2111 | this->options |= ONENAND_HAS_UNLOCK_ALL; | |
2112 | } | |
2113 | } else { | |
2114 | /* Some OneNAND has continues lock scheme */ | |
2115 | if (!process) { | |
2116 | printk(KERN_DEBUG "Lock scheme is Continues Lock\n"); | |
2117 | this->options |= ONENAND_HAS_CONT_LOCK; | |
2118 | } | |
2119 | } | |
2120 | } | |
2121 | ||
cd5f6346 KP |
2122 | /** |
2123 | * onenand_print_device_info - Print device ID | |
2124 | * @param device device ID | |
2125 | * | |
2126 | * Print device ID | |
2127 | */ | |
28b79ff9 | 2128 | static void onenand_print_device_info(int device, int version) |
cd5f6346 KP |
2129 | { |
2130 | int vcc, demuxed, ddp, density; | |
2131 | ||
2132 | vcc = device & ONENAND_DEVICE_VCC_MASK; | |
2133 | demuxed = device & ONENAND_DEVICE_IS_DEMUX; | |
2134 | ddp = device & ONENAND_DEVICE_IS_DDP; | |
2135 | density = device >> ONENAND_DEVICE_DENSITY_SHIFT; | |
2136 | printk(KERN_INFO "%sOneNAND%s %dMB %sV 16-bit (0x%02x)\n", | |
2137 | demuxed ? "" : "Muxed ", | |
2138 | ddp ? "(DDP)" : "", | |
2139 | (16 << density), | |
2140 | vcc ? "2.65/3.3" : "1.8", | |
2141 | device); | |
28b79ff9 | 2142 | printk(KERN_DEBUG "OneNAND version = 0x%04x\n", version); |
cd5f6346 KP |
2143 | } |
2144 | ||
2145 | static const struct onenand_manufacturers onenand_manuf_ids[] = { | |
2146 | {ONENAND_MFR_SAMSUNG, "Samsung"}, | |
cd5f6346 KP |
2147 | }; |
2148 | ||
2149 | /** | |
2150 | * onenand_check_maf - Check manufacturer ID | |
2151 | * @param manuf manufacturer ID | |
2152 | * | |
2153 | * Check manufacturer ID | |
2154 | */ | |
2155 | static int onenand_check_maf(int manuf) | |
2156 | { | |
37b1cc39 KP |
2157 | int size = ARRAY_SIZE(onenand_manuf_ids); |
2158 | char *name; | |
cd5f6346 KP |
2159 | int i; |
2160 | ||
37b1cc39 | 2161 | for (i = 0; i < size; i++) |
cd5f6346 KP |
2162 | if (manuf == onenand_manuf_ids[i].id) |
2163 | break; | |
cd5f6346 | 2164 | |
37b1cc39 KP |
2165 | if (i < size) |
2166 | name = onenand_manuf_ids[i].name; | |
2167 | else | |
2168 | name = "Unknown"; | |
2169 | ||
2170 | printk(KERN_DEBUG "OneNAND Manufacturer: %s (0x%0x)\n", name, manuf); | |
cd5f6346 | 2171 | |
37b1cc39 | 2172 | return (i == size); |
cd5f6346 KP |
2173 | } |
2174 | ||
2175 | /** | |
2176 | * onenand_probe - [OneNAND Interface] Probe the OneNAND device | |
2177 | * @param mtd MTD device structure | |
2178 | * | |
2179 | * OneNAND detection method: | |
2180 | * Compare the the values from command with ones from register | |
2181 | */ | |
2182 | static int onenand_probe(struct mtd_info *mtd) | |
2183 | { | |
2184 | struct onenand_chip *this = mtd->priv; | |
28b79ff9 | 2185 | int bram_maf_id, bram_dev_id, maf_id, dev_id, ver_id; |
cd5f6346 | 2186 | int density; |
47e777e0 KP |
2187 | int syscfg; |
2188 | ||
2189 | /* Save system configuration 1 */ | |
2190 | syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1); | |
2191 | /* Clear Sync. Burst Read mode to read BootRAM */ | |
2192 | this->write_word((syscfg & ~ONENAND_SYS_CFG1_SYNC_READ), this->base + ONENAND_REG_SYS_CFG1); | |
cd5f6346 KP |
2193 | |
2194 | /* Send the command for reading device ID from BootRAM */ | |
2195 | this->write_word(ONENAND_CMD_READID, this->base + ONENAND_BOOTRAM); | |
2196 | ||
2197 | /* Read manufacturer and device IDs from BootRAM */ | |
2198 | bram_maf_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x0); | |
2199 | bram_dev_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x2); | |
2200 | ||
47e777e0 KP |
2201 | /* Reset OneNAND to read default register values */ |
2202 | this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM); | |
2203 | /* Wait reset */ | |
2204 | this->wait(mtd, FL_RESETING); | |
2205 | ||
2206 | /* Restore system configuration 1 */ | |
2207 | this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1); | |
2208 | ||
cd5f6346 KP |
2209 | /* Check manufacturer ID */ |
2210 | if (onenand_check_maf(bram_maf_id)) | |
2211 | return -ENXIO; | |
2212 | ||
cd5f6346 KP |
2213 | /* Read manufacturer and device IDs from Register */ |
2214 | maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID); | |
2215 | dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID); | |
f4f91ac3 | 2216 | ver_id = this->read_word(this->base + ONENAND_REG_VERSION_ID); |
cd5f6346 KP |
2217 | |
2218 | /* Check OneNAND device */ | |
2219 | if (maf_id != bram_maf_id || dev_id != bram_dev_id) | |
2220 | return -ENXIO; | |
2221 | ||
2222 | /* Flash device information */ | |
28b79ff9 | 2223 | onenand_print_device_info(dev_id, ver_id); |
cd5f6346 | 2224 | this->device_id = dev_id; |
28b79ff9 | 2225 | this->version_id = ver_id; |
cd5f6346 KP |
2226 | |
2227 | density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT; | |
2228 | this->chipsize = (16 << density) << 20; | |
83a36838 | 2229 | /* Set density mask. it is used for DDP */ |
738d61f5 KP |
2230 | if (ONENAND_IS_DDP(this)) |
2231 | this->density_mask = (1 << (density + 6)); | |
2232 | else | |
2233 | this->density_mask = 0; | |
cd5f6346 KP |
2234 | |
2235 | /* OneNAND page size & block size */ | |
2236 | /* The data buffer size is equal to page size */ | |
28318776 JE |
2237 | mtd->writesize = this->read_word(this->base + ONENAND_REG_DATA_BUFFER_SIZE); |
2238 | mtd->oobsize = mtd->writesize >> 5; | |
9bfbc9b2 | 2239 | /* Pages per a block are always 64 in OneNAND */ |
28318776 | 2240 | mtd->erasesize = mtd->writesize << 6; |
cd5f6346 KP |
2241 | |
2242 | this->erase_shift = ffs(mtd->erasesize) - 1; | |
28318776 | 2243 | this->page_shift = ffs(mtd->writesize) - 1; |
9bfbc9b2 | 2244 | this->page_mask = (1 << (this->erase_shift - this->page_shift)) - 1; |
cd5f6346 KP |
2245 | |
2246 | /* REVIST: Multichip handling */ | |
2247 | ||
2248 | mtd->size = this->chipsize; | |
2249 | ||
75384b0d KP |
2250 | /* Check OneNAND features */ |
2251 | onenand_check_features(mtd); | |
d5c5e78a | 2252 | |
cd5f6346 KP |
2253 | return 0; |
2254 | } | |
2255 | ||
a41371eb KP |
2256 | /** |
2257 | * onenand_suspend - [MTD Interface] Suspend the OneNAND flash | |
2258 | * @param mtd MTD device structure | |
2259 | */ | |
2260 | static int onenand_suspend(struct mtd_info *mtd) | |
2261 | { | |
2262 | return onenand_get_device(mtd, FL_PM_SUSPENDED); | |
2263 | } | |
2264 | ||
2265 | /** | |
2266 | * onenand_resume - [MTD Interface] Resume the OneNAND flash | |
2267 | * @param mtd MTD device structure | |
2268 | */ | |
2269 | static void onenand_resume(struct mtd_info *mtd) | |
2270 | { | |
2271 | struct onenand_chip *this = mtd->priv; | |
2272 | ||
2273 | if (this->state == FL_PM_SUSPENDED) | |
2274 | onenand_release_device(mtd); | |
2275 | else | |
2276 | printk(KERN_ERR "resume() called for the chip which is not" | |
2277 | "in suspended state\n"); | |
2278 | } | |
2279 | ||
cd5f6346 KP |
2280 | /** |
2281 | * onenand_scan - [OneNAND Interface] Scan for the OneNAND device | |
2282 | * @param mtd MTD device structure | |
2283 | * @param maxchips Number of chips to scan for | |
2284 | * | |
2285 | * This fills out all the not initialized function pointers | |
2286 | * with the defaults. | |
2287 | * The flash ID is read and the mtd/chip structures are | |
2288 | * filled with the appropriate values. | |
2289 | */ | |
2290 | int onenand_scan(struct mtd_info *mtd, int maxchips) | |
2291 | { | |
a5e7c7b4 | 2292 | int i; |
cd5f6346 KP |
2293 | struct onenand_chip *this = mtd->priv; |
2294 | ||
2295 | if (!this->read_word) | |
2296 | this->read_word = onenand_readw; | |
2297 | if (!this->write_word) | |
2298 | this->write_word = onenand_writew; | |
2299 | ||
2300 | if (!this->command) | |
2301 | this->command = onenand_command; | |
2302 | if (!this->wait) | |
2c22120f | 2303 | onenand_setup_wait(mtd); |
cd5f6346 KP |
2304 | |
2305 | if (!this->read_bufferram) | |
2306 | this->read_bufferram = onenand_read_bufferram; | |
2307 | if (!this->write_bufferram) | |
2308 | this->write_bufferram = onenand_write_bufferram; | |
2309 | ||
cdc00130 KP |
2310 | if (!this->block_markbad) |
2311 | this->block_markbad = onenand_default_block_markbad; | |
2312 | if (!this->scan_bbt) | |
2313 | this->scan_bbt = onenand_default_bbt; | |
2314 | ||
cd5f6346 KP |
2315 | if (onenand_probe(mtd)) |
2316 | return -ENXIO; | |
2317 | ||
52b0eea7 KP |
2318 | /* Set Sync. Burst Read after probing */ |
2319 | if (this->mmcontrol) { | |
2320 | printk(KERN_INFO "OneNAND Sync. Burst Read support\n"); | |
2321 | this->read_bufferram = onenand_sync_read_bufferram; | |
2322 | } | |
2323 | ||
532a37cf KP |
2324 | /* Allocate buffers, if necessary */ |
2325 | if (!this->page_buf) { | |
2326 | size_t len; | |
28318776 | 2327 | len = mtd->writesize + mtd->oobsize; |
532a37cf KP |
2328 | this->page_buf = kmalloc(len, GFP_KERNEL); |
2329 | if (!this->page_buf) { | |
2330 | printk(KERN_ERR "onenand_scan(): Can't allocate page_buf\n"); | |
2331 | return -ENOMEM; | |
2332 | } | |
2333 | this->options |= ONENAND_PAGEBUF_ALLOC; | |
2334 | } | |
2335 | ||
cd5f6346 KP |
2336 | this->state = FL_READY; |
2337 | init_waitqueue_head(&this->wq); | |
2338 | spin_lock_init(&this->chip_lock); | |
2339 | ||
60d84f97 KP |
2340 | /* |
2341 | * Allow subpage writes up to oobsize. | |
2342 | */ | |
cd5f6346 KP |
2343 | switch (mtd->oobsize) { |
2344 | case 64: | |
5bd34c09 | 2345 | this->ecclayout = &onenand_oob_64; |
60d84f97 | 2346 | mtd->subpage_sft = 2; |
cd5f6346 KP |
2347 | break; |
2348 | ||
2349 | case 32: | |
5bd34c09 | 2350 | this->ecclayout = &onenand_oob_32; |
60d84f97 | 2351 | mtd->subpage_sft = 1; |
cd5f6346 KP |
2352 | break; |
2353 | ||
2354 | default: | |
2355 | printk(KERN_WARNING "No OOB scheme defined for oobsize %d\n", | |
2356 | mtd->oobsize); | |
60d84f97 | 2357 | mtd->subpage_sft = 0; |
cd5f6346 | 2358 | /* To prevent kernel oops */ |
5bd34c09 | 2359 | this->ecclayout = &onenand_oob_32; |
cd5f6346 KP |
2360 | break; |
2361 | } | |
2362 | ||
60d84f97 | 2363 | this->subpagesize = mtd->writesize >> mtd->subpage_sft; |
a5e7c7b4 AH |
2364 | |
2365 | /* | |
2366 | * The number of bytes available for a client to place data into | |
2367 | * the out of band area | |
2368 | */ | |
2369 | this->ecclayout->oobavail = 0; | |
2370 | for (i = 0; this->ecclayout->oobfree[i].length; i++) | |
2371 | this->ecclayout->oobavail += | |
2372 | this->ecclayout->oobfree[i].length; | |
1f92267c | 2373 | mtd->oobavail = this->ecclayout->oobavail; |
a5e7c7b4 | 2374 | |
5bd34c09 | 2375 | mtd->ecclayout = this->ecclayout; |
d5c5e78a | 2376 | |
cd5f6346 KP |
2377 | /* Fill in remaining MTD driver data */ |
2378 | mtd->type = MTD_NANDFLASH; | |
5fa43394 | 2379 | mtd->flags = MTD_CAP_NANDFLASH; |
cd5f6346 KP |
2380 | mtd->erase = onenand_erase; |
2381 | mtd->point = NULL; | |
2382 | mtd->unpoint = NULL; | |
2383 | mtd->read = onenand_read; | |
2384 | mtd->write = onenand_write; | |
cd5f6346 KP |
2385 | mtd->read_oob = onenand_read_oob; |
2386 | mtd->write_oob = onenand_write_oob; | |
493c6460 KP |
2387 | #ifdef CONFIG_MTD_ONENAND_OTP |
2388 | mtd->get_fact_prot_info = onenand_get_fact_prot_info; | |
2389 | mtd->read_fact_prot_reg = onenand_read_fact_prot_reg; | |
2390 | mtd->get_user_prot_info = onenand_get_user_prot_info; | |
2391 | mtd->read_user_prot_reg = onenand_read_user_prot_reg; | |
2392 | mtd->write_user_prot_reg = onenand_write_user_prot_reg; | |
2393 | mtd->lock_user_prot_reg = onenand_lock_user_prot_reg; | |
2394 | #endif | |
cd5f6346 | 2395 | mtd->sync = onenand_sync; |
08f782b6 | 2396 | mtd->lock = onenand_lock; |
cd5f6346 | 2397 | mtd->unlock = onenand_unlock; |
a41371eb KP |
2398 | mtd->suspend = onenand_suspend; |
2399 | mtd->resume = onenand_resume; | |
cd5f6346 KP |
2400 | mtd->block_isbad = onenand_block_isbad; |
2401 | mtd->block_markbad = onenand_block_markbad; | |
2402 | mtd->owner = THIS_MODULE; | |
2403 | ||
2404 | /* Unlock whole block */ | |
28b79ff9 | 2405 | onenand_unlock_all(mtd); |
cd5f6346 | 2406 | |
cdc00130 | 2407 | return this->scan_bbt(mtd); |
cd5f6346 KP |
2408 | } |
2409 | ||
2410 | /** | |
2411 | * onenand_release - [OneNAND Interface] Free resources held by the OneNAND device | |
2412 | * @param mtd MTD device structure | |
2413 | */ | |
2414 | void onenand_release(struct mtd_info *mtd) | |
2415 | { | |
532a37cf KP |
2416 | struct onenand_chip *this = mtd->priv; |
2417 | ||
cd5f6346 KP |
2418 | #ifdef CONFIG_MTD_PARTITIONS |
2419 | /* Deregister partitions */ | |
2420 | del_mtd_partitions (mtd); | |
2421 | #endif | |
2422 | /* Deregister the device */ | |
2423 | del_mtd_device (mtd); | |
532a37cf KP |
2424 | |
2425 | /* Free bad block table memory, if allocated */ | |
f00b0046 AH |
2426 | if (this->bbm) { |
2427 | struct bbm_info *bbm = this->bbm; | |
2428 | kfree(bbm->bbt); | |
532a37cf | 2429 | kfree(this->bbm); |
f00b0046 | 2430 | } |
532a37cf KP |
2431 | /* Buffer allocated by onenand_scan */ |
2432 | if (this->options & ONENAND_PAGEBUF_ALLOC) | |
2433 | kfree(this->page_buf); | |
cd5f6346 KP |
2434 | } |
2435 | ||
2436 | EXPORT_SYMBOL_GPL(onenand_scan); | |
2437 | EXPORT_SYMBOL_GPL(onenand_release); | |
2438 | ||
2439 | MODULE_LICENSE("GPL"); | |
2440 | MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>"); | |
2441 | MODULE_DESCRIPTION("Generic OneNAND flash driver code"); |