jffs2: leaking jffs2_summary in function jffs2_scan_medium
[deliverable/linux.git] / drivers / mtd / onenand / onenand_base.c
CommitLineData
cd5f6346
KP
1/*
2 * linux/drivers/mtd/onenand/onenand_base.c
3 *
75384b0d 4 * Copyright (C) 2005-2007 Samsung Electronics
cd5f6346
KP
5 * Kyungmin Park <kyungmin.park@samsung.com>
6 *
81280d58
AH
7 * Credits:
8 * Adrian Hunter <ext-adrian.hunter@nokia.com>:
9 * auto-placement support, read-while load support, various fixes
10 * Copyright (C) Nokia Corporation, 2007
11 *
5988af23
RH
12 * Vishak G <vishak.g at samsung.com>, Rohit Hagargundgi <h.rohit at samsung.com>
13 * Flex-OneNAND support
14 * Copyright (C) Samsung Electronics, 2008
15 *
cd5f6346
KP
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/init.h>
015953d7 24#include <linux/sched.h>
6c77fd64 25#include <linux/delay.h>
2c22120f 26#include <linux/interrupt.h>
015953d7 27#include <linux/jiffies.h>
cd5f6346
KP
28#include <linux/mtd/mtd.h>
29#include <linux/mtd/onenand.h>
30#include <linux/mtd/partitions.h>
31
32#include <asm/io.h>
33
5988af23
RH
34/* Default Flex-OneNAND boundary and lock respectively */
35static int flex_bdry[MAX_DIES * 2] = { -1, 0, -1, 0 };
36
37/**
38 * onenand_oob_128 - oob info for Flex-Onenand with 4KB page
39 * For now, we expose only 64 out of 80 ecc bytes
40 */
41static struct nand_ecclayout onenand_oob_128 = {
42 .eccbytes = 64,
43 .eccpos = {
44 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
45 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
46 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
47 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
48 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
49 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
50 102, 103, 104, 105
51 },
52 .oobfree = {
53 {2, 4}, {18, 4}, {34, 4}, {50, 4},
54 {66, 4}, {82, 4}, {98, 4}, {114, 4}
55 }
56};
57
cd5f6346
KP
58/**
59 * onenand_oob_64 - oob info for large (2KB) page
60 */
5bd34c09 61static struct nand_ecclayout onenand_oob_64 = {
cd5f6346
KP
62 .eccbytes = 20,
63 .eccpos = {
64 8, 9, 10, 11, 12,
65 24, 25, 26, 27, 28,
66 40, 41, 42, 43, 44,
67 56, 57, 58, 59, 60,
68 },
69 .oobfree = {
70 {2, 3}, {14, 2}, {18, 3}, {30, 2},
d9777f1c
JL
71 {34, 3}, {46, 2}, {50, 3}, {62, 2}
72 }
cd5f6346
KP
73};
74
75/**
76 * onenand_oob_32 - oob info for middle (1KB) page
77 */
5bd34c09 78static struct nand_ecclayout onenand_oob_32 = {
cd5f6346
KP
79 .eccbytes = 10,
80 .eccpos = {
81 8, 9, 10, 11, 12,
82 24, 25, 26, 27, 28,
83 },
84 .oobfree = { {2, 3}, {14, 2}, {18, 3}, {30, 2} }
85};
86
87static const unsigned char ffchars[] = {
88 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
89 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 16 */
90 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
91 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 32 */
92 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
93 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 48 */
94 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
95 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 64 */
5988af23
RH
96 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
97 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 80 */
98 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
99 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 96 */
100 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
101 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 112 */
102 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
103 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 128 */
cd5f6346
KP
104};
105
106/**
107 * onenand_readw - [OneNAND Interface] Read OneNAND register
108 * @param addr address to read
109 *
110 * Read OneNAND register
111 */
112static unsigned short onenand_readw(void __iomem *addr)
113{
114 return readw(addr);
115}
116
117/**
118 * onenand_writew - [OneNAND Interface] Write OneNAND register with value
119 * @param value value to write
120 * @param addr address to write
121 *
122 * Write OneNAND register with value
123 */
124static void onenand_writew(unsigned short value, void __iomem *addr)
125{
126 writew(value, addr);
127}
128
129/**
130 * onenand_block_address - [DEFAULT] Get block address
83a36838 131 * @param this onenand chip data structure
cd5f6346
KP
132 * @param block the block
133 * @return translated block address if DDP, otherwise same
134 *
135 * Setup Start Address 1 Register (F100h)
136 */
83a36838 137static int onenand_block_address(struct onenand_chip *this, int block)
cd5f6346 138{
738d61f5
KP
139 /* Device Flash Core select, NAND Flash Block Address */
140 if (block & this->density_mask)
141 return ONENAND_DDP_CHIP1 | (block ^ this->density_mask);
cd5f6346
KP
142
143 return block;
144}
145
146/**
147 * onenand_bufferram_address - [DEFAULT] Get bufferram address
83a36838 148 * @param this onenand chip data structure
cd5f6346
KP
149 * @param block the block
150 * @return set DBS value if DDP, otherwise 0
151 *
152 * Setup Start Address 2 Register (F101h) for DDP
153 */
83a36838 154static int onenand_bufferram_address(struct onenand_chip *this, int block)
cd5f6346 155{
738d61f5
KP
156 /* Device BufferRAM Select */
157 if (block & this->density_mask)
158 return ONENAND_DDP_CHIP1;
cd5f6346 159
738d61f5 160 return ONENAND_DDP_CHIP0;
cd5f6346
KP
161}
162
163/**
164 * onenand_page_address - [DEFAULT] Get page address
165 * @param page the page address
166 * @param sector the sector address
167 * @return combined page and sector address
168 *
169 * Setup Start Address 8 Register (F107h)
170 */
171static int onenand_page_address(int page, int sector)
172{
173 /* Flash Page Address, Flash Sector Address */
174 int fpa, fsa;
175
176 fpa = page & ONENAND_FPA_MASK;
177 fsa = sector & ONENAND_FSA_MASK;
178
179 return ((fpa << ONENAND_FPA_SHIFT) | fsa);
180}
181
182/**
183 * onenand_buffer_address - [DEFAULT] Get buffer address
184 * @param dataram1 DataRAM index
185 * @param sectors the sector address
186 * @param count the number of sectors
187 * @return the start buffer value
188 *
189 * Setup Start Buffer Register (F200h)
190 */
191static int onenand_buffer_address(int dataram1, int sectors, int count)
192{
193 int bsa, bsc;
194
195 /* BufferRAM Sector Address */
196 bsa = sectors & ONENAND_BSA_MASK;
197
198 if (dataram1)
199 bsa |= ONENAND_BSA_DATARAM1; /* DataRAM1 */
200 else
201 bsa |= ONENAND_BSA_DATARAM0; /* DataRAM0 */
202
203 /* BufferRAM Sector Count */
204 bsc = count & ONENAND_BSC_MASK;
205
206 return ((bsa << ONENAND_BSA_SHIFT) | bsc);
207}
208
5988af23
RH
209/**
210 * flexonenand_block- For given address return block number
211 * @param this - OneNAND device structure
212 * @param addr - Address for which block number is needed
213 */
214static unsigned flexonenand_block(struct onenand_chip *this, loff_t addr)
215{
216 unsigned boundary, blk, die = 0;
217
218 if (ONENAND_IS_DDP(this) && addr >= this->diesize[0]) {
219 die = 1;
220 addr -= this->diesize[0];
221 }
222
223 boundary = this->boundary[die];
224
225 blk = addr >> (this->erase_shift - 1);
226 if (blk > boundary)
227 blk = (blk + boundary + 1) >> 1;
228
229 blk += die ? this->density_mask : 0;
230 return blk;
231}
232
233inline unsigned onenand_block(struct onenand_chip *this, loff_t addr)
234{
235 if (!FLEXONENAND(this))
236 return addr >> this->erase_shift;
237 return flexonenand_block(this, addr);
238}
239
240/**
241 * flexonenand_addr - Return address of the block
242 * @this: OneNAND device structure
243 * @block: Block number on Flex-OneNAND
244 *
245 * Return address of the block
246 */
247static loff_t flexonenand_addr(struct onenand_chip *this, int block)
248{
249 loff_t ofs = 0;
250 int die = 0, boundary;
251
252 if (ONENAND_IS_DDP(this) && block >= this->density_mask) {
253 block -= this->density_mask;
254 die = 1;
255 ofs = this->diesize[0];
256 }
257
258 boundary = this->boundary[die];
259 ofs += (loff_t)block << (this->erase_shift - 1);
260 if (block > (boundary + 1))
261 ofs += (loff_t)(block - boundary - 1) << (this->erase_shift - 1);
262 return ofs;
263}
264
265loff_t onenand_addr(struct onenand_chip *this, int block)
266{
267 if (!FLEXONENAND(this))
268 return (loff_t)block << this->erase_shift;
269 return flexonenand_addr(this, block);
270}
271EXPORT_SYMBOL(onenand_addr);
272
e71f04fc
KP
273/**
274 * onenand_get_density - [DEFAULT] Get OneNAND density
275 * @param dev_id OneNAND device ID
276 *
277 * Get OneNAND density from device ID
278 */
279static inline int onenand_get_density(int dev_id)
280{
281 int density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT;
282 return (density & ONENAND_DEVICE_DENSITY_MASK);
283}
284
5988af23
RH
285/**
286 * flexonenand_region - [Flex-OneNAND] Return erase region of addr
287 * @param mtd MTD device structure
288 * @param addr address whose erase region needs to be identified
289 */
290int flexonenand_region(struct mtd_info *mtd, loff_t addr)
291{
292 int i;
293
294 for (i = 0; i < mtd->numeraseregions; i++)
295 if (addr < mtd->eraseregions[i].offset)
296 break;
297 return i - 1;
298}
299EXPORT_SYMBOL(flexonenand_region);
300
cd5f6346
KP
301/**
302 * onenand_command - [DEFAULT] Send command to OneNAND device
303 * @param mtd MTD device structure
304 * @param cmd the command to be sent
305 * @param addr offset to read from or write to
306 * @param len number of bytes to read or write
307 *
308 * Send command to OneNAND device. This function is used for middle/large page
309 * devices (1KB/2KB Bytes per page)
310 */
311static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t len)
312{
313 struct onenand_chip *this = mtd->priv;
b21b72cf 314 int value, block, page;
cd5f6346
KP
315
316 /* Address translation */
317 switch (cmd) {
318 case ONENAND_CMD_UNLOCK:
319 case ONENAND_CMD_LOCK:
320 case ONENAND_CMD_LOCK_TIGHT:
28b79ff9 321 case ONENAND_CMD_UNLOCK_ALL:
cd5f6346
KP
322 block = -1;
323 page = -1;
324 break;
325
5988af23
RH
326 case FLEXONENAND_CMD_PI_ACCESS:
327 /* addr contains die index */
328 block = addr * this->density_mask;
329 page = -1;
330 break;
331
cd5f6346
KP
332 case ONENAND_CMD_ERASE:
333 case ONENAND_CMD_BUFFERRAM:
493c6460 334 case ONENAND_CMD_OTP_ACCESS:
5988af23 335 block = onenand_block(this, addr);
cd5f6346
KP
336 page = -1;
337 break;
338
5988af23
RH
339 case FLEXONENAND_CMD_READ_PI:
340 cmd = ONENAND_CMD_READ;
341 block = addr * this->density_mask;
342 page = 0;
343 break;
344
cd5f6346 345 default:
5988af23
RH
346 block = onenand_block(this, addr);
347 page = (int) (addr - onenand_addr(this, block)) >> this->page_shift;
ee9745fc
KP
348
349 if (ONENAND_IS_2PLANE(this)) {
350 /* Make the even block number */
351 block &= ~1;
352 /* Is it the odd plane? */
353 if (addr & this->writesize)
354 block++;
355 page >>= 1;
356 }
cd5f6346
KP
357 page &= this->page_mask;
358 break;
359 }
360
361 /* NOTE: The setting order of the registers is very important! */
362 if (cmd == ONENAND_CMD_BUFFERRAM) {
363 /* Select DataRAM for DDP */
83a36838 364 value = onenand_bufferram_address(this, block);
cd5f6346
KP
365 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
366
5988af23 367 if (ONENAND_IS_MLC(this) || ONENAND_IS_2PLANE(this))
ee9745fc
KP
368 /* It is always BufferRAM0 */
369 ONENAND_SET_BUFFERRAM0(this);
370 else
371 /* Switch to the next data buffer */
372 ONENAND_SET_NEXT_BUFFERRAM(this);
cd5f6346
KP
373
374 return 0;
375 }
376
377 if (block != -1) {
378 /* Write 'DFS, FBA' of Flash */
83a36838 379 value = onenand_block_address(this, block);
cd5f6346 380 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1);
3cecf69e 381
b21b72cf
KP
382 /* Select DataRAM for DDP */
383 value = onenand_bufferram_address(this, block);
384 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
cd5f6346
KP
385 }
386
387 if (page != -1) {
60d84f97 388 /* Now we use page size operation */
5988af23 389 int sectors = 0, count = 0;
cd5f6346
KP
390 int dataram;
391
392 switch (cmd) {
5988af23 393 case FLEXONENAND_CMD_RECOVER_LSB:
cd5f6346
KP
394 case ONENAND_CMD_READ:
395 case ONENAND_CMD_READOOB:
5988af23
RH
396 if (ONENAND_IS_MLC(this))
397 /* It is always BufferRAM0 */
398 dataram = ONENAND_SET_BUFFERRAM0(this);
399 else
400 dataram = ONENAND_SET_NEXT_BUFFERRAM(this);
cd5f6346
KP
401 break;
402
403 default:
ee9745fc
KP
404 if (ONENAND_IS_2PLANE(this) && cmd == ONENAND_CMD_PROG)
405 cmd = ONENAND_CMD_2X_PROG;
cd5f6346
KP
406 dataram = ONENAND_CURRENT_BUFFERRAM(this);
407 break;
408 }
409
410 /* Write 'FPA, FSA' of Flash */
411 value = onenand_page_address(page, sectors);
412 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS8);
413
414 /* Write 'BSA, BSC' of DataRAM */
415 value = onenand_buffer_address(dataram, sectors, count);
416 this->write_word(value, this->base + ONENAND_REG_START_BUFFER);
cd5f6346
KP
417 }
418
419 /* Interrupt clear */
420 this->write_word(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT);
421
422 /* Write command */
423 this->write_word(cmd, this->base + ONENAND_REG_COMMAND);
424
425 return 0;
426}
427
5988af23
RH
428/**
429 * onenand_read_ecc - return ecc status
430 * @param this onenand chip structure
431 */
432static inline int onenand_read_ecc(struct onenand_chip *this)
433{
434 int ecc, i, result = 0;
435
436 if (!FLEXONENAND(this))
437 return this->read_word(this->base + ONENAND_REG_ECC_STATUS);
438
439 for (i = 0; i < 4; i++) {
440 ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS + i);
441 if (likely(!ecc))
442 continue;
443 if (ecc & FLEXONENAND_UNCORRECTABLE_ERROR)
444 return ONENAND_ECC_2BIT_ALL;
445 else
446 result = ONENAND_ECC_1BIT_ALL;
447 }
448
449 return result;
450}
451
cd5f6346
KP
452/**
453 * onenand_wait - [DEFAULT] wait until the command is done
454 * @param mtd MTD device structure
455 * @param state state to select the max. timeout value
456 *
457 * Wait for command done. This applies to all OneNAND command
458 * Read can take up to 30us, erase up to 2ms and program up to 350us
459 * according to general OneNAND specs
460 */
461static int onenand_wait(struct mtd_info *mtd, int state)
462{
463 struct onenand_chip * this = mtd->priv;
464 unsigned long timeout;
465 unsigned int flags = ONENAND_INT_MASTER;
466 unsigned int interrupt = 0;
2fd32d4a 467 unsigned int ctrl;
cd5f6346
KP
468
469 /* The 20 msec is enough */
470 timeout = jiffies + msecs_to_jiffies(20);
471 while (time_before(jiffies, timeout)) {
472 interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
473
474 if (interrupt & flags)
475 break;
476
477 if (state != FL_READING)
478 cond_resched();
479 }
480 /* To get correct interrupt status in timeout case */
481 interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
482
483 ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
484
83973b87
KP
485 /*
486 * In the Spec. it checks the controller status first
487 * However if you get the correct information in case of
488 * power off recovery (POR) test, it should read ECC status first
489 */
cd5f6346 490 if (interrupt & ONENAND_INT_READ) {
5988af23 491 int ecc = onenand_read_ecc(this);
f4f91ac3 492 if (ecc) {
b3c9f8bf 493 if (ecc & ONENAND_ECC_2BIT_ALL) {
49dc08ee 494 printk(KERN_ERR "onenand_wait: ECC error = 0x%04x\n", ecc);
f4f91ac3 495 mtd->ecc_stats.failed++;
30a7eb29 496 return -EBADMSG;
49dc08ee 497 } else if (ecc & ONENAND_ECC_1BIT_ALL) {
5988af23 498 printk(KERN_DEBUG "onenand_wait: correctable ECC error = 0x%04x\n", ecc);
f4f91ac3 499 mtd->ecc_stats.corrected++;
49dc08ee 500 }
cd5f6346 501 }
9d032801
AH
502 } else if (state == FL_READING) {
503 printk(KERN_ERR "onenand_wait: read timeout! ctrl=0x%04x intr=0x%04x\n", ctrl, interrupt);
504 return -EIO;
cd5f6346
KP
505 }
506
83973b87
KP
507 /* If there's controller error, it's a real error */
508 if (ctrl & ONENAND_CTRL_ERROR) {
509 printk(KERN_ERR "onenand_wait: controller error = 0x%04x\n",
510 ctrl);
511 if (ctrl & ONENAND_CTRL_LOCK)
512 printk(KERN_ERR "onenand_wait: it's locked error.\n");
513 return -EIO;
514 }
515
cd5f6346
KP
516 return 0;
517}
518
2c22120f
KP
519/*
520 * onenand_interrupt - [DEFAULT] onenand interrupt handler
521 * @param irq onenand interrupt number
522 * @param dev_id interrupt data
523 *
524 * complete the work
525 */
526static irqreturn_t onenand_interrupt(int irq, void *data)
527{
06efcad0 528 struct onenand_chip *this = data;
2c22120f
KP
529
530 /* To handle shared interrupt */
531 if (!this->complete.done)
532 complete(&this->complete);
533
534 return IRQ_HANDLED;
535}
536
537/*
538 * onenand_interrupt_wait - [DEFAULT] wait until the command is done
539 * @param mtd MTD device structure
540 * @param state state to select the max. timeout value
541 *
542 * Wait for command done.
543 */
544static int onenand_interrupt_wait(struct mtd_info *mtd, int state)
545{
546 struct onenand_chip *this = mtd->priv;
547
2c22120f
KP
548 wait_for_completion(&this->complete);
549
550 return onenand_wait(mtd, state);
551}
552
553/*
554 * onenand_try_interrupt_wait - [DEFAULT] try interrupt wait
555 * @param mtd MTD device structure
556 * @param state state to select the max. timeout value
557 *
558 * Try interrupt based wait (It is used one-time)
559 */
560static int onenand_try_interrupt_wait(struct mtd_info *mtd, int state)
561{
562 struct onenand_chip *this = mtd->priv;
563 unsigned long remain, timeout;
564
565 /* We use interrupt wait first */
566 this->wait = onenand_interrupt_wait;
567
2c22120f
KP
568 timeout = msecs_to_jiffies(100);
569 remain = wait_for_completion_timeout(&this->complete, timeout);
570 if (!remain) {
571 printk(KERN_INFO "OneNAND: There's no interrupt. "
572 "We use the normal wait\n");
573
574 /* Release the irq */
575 free_irq(this->irq, this);
c9ac5977 576
2c22120f
KP
577 this->wait = onenand_wait;
578 }
579
580 return onenand_wait(mtd, state);
581}
582
583/*
584 * onenand_setup_wait - [OneNAND Interface] setup onenand wait method
585 * @param mtd MTD device structure
586 *
587 * There's two method to wait onenand work
588 * 1. polling - read interrupt status register
589 * 2. interrupt - use the kernel interrupt method
590 */
591static void onenand_setup_wait(struct mtd_info *mtd)
592{
593 struct onenand_chip *this = mtd->priv;
594 int syscfg;
595
596 init_completion(&this->complete);
597
598 if (this->irq <= 0) {
599 this->wait = onenand_wait;
600 return;
601 }
602
603 if (request_irq(this->irq, &onenand_interrupt,
604 IRQF_SHARED, "onenand", this)) {
605 /* If we can't get irq, use the normal wait */
606 this->wait = onenand_wait;
607 return;
608 }
609
610 /* Enable interrupt */
611 syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1);
612 syscfg |= ONENAND_SYS_CFG1_IOBE;
613 this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);
614
615 this->wait = onenand_try_interrupt_wait;
616}
617
cd5f6346
KP
618/**
619 * onenand_bufferram_offset - [DEFAULT] BufferRAM offset
620 * @param mtd MTD data structure
621 * @param area BufferRAM area
622 * @return offset given area
623 *
624 * Return BufferRAM offset given area
625 */
626static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area)
627{
628 struct onenand_chip *this = mtd->priv;
629
630 if (ONENAND_CURRENT_BUFFERRAM(this)) {
ee9745fc 631 /* Note: the 'this->writesize' is a real page size */
cd5f6346 632 if (area == ONENAND_DATARAM)
ee9745fc 633 return this->writesize;
cd5f6346
KP
634 if (area == ONENAND_SPARERAM)
635 return mtd->oobsize;
636 }
637
638 return 0;
639}
640
641/**
642 * onenand_read_bufferram - [OneNAND Interface] Read the bufferram area
643 * @param mtd MTD data structure
644 * @param area BufferRAM area
645 * @param buffer the databuffer to put/get data
646 * @param offset offset to read from or write to
647 * @param count number of bytes to read/write
648 *
649 * Read the BufferRAM area
650 */
651static int onenand_read_bufferram(struct mtd_info *mtd, int area,
652 unsigned char *buffer, int offset, size_t count)
653{
654 struct onenand_chip *this = mtd->priv;
655 void __iomem *bufferram;
656
657 bufferram = this->base + area;
658
659 bufferram += onenand_bufferram_offset(mtd, area);
660
9c01f87d
KP
661 if (ONENAND_CHECK_BYTE_ACCESS(count)) {
662 unsigned short word;
663
664 /* Align with word(16-bit) size */
665 count--;
666
667 /* Read word and save byte */
668 word = this->read_word(bufferram + offset + count);
669 buffer[count] = (word & 0xff);
670 }
671
cd5f6346
KP
672 memcpy(buffer, bufferram + offset, count);
673
674 return 0;
675}
676
52b0eea7
KP
677/**
678 * onenand_sync_read_bufferram - [OneNAND Interface] Read the bufferram area with Sync. Burst mode
679 * @param mtd MTD data structure
680 * @param area BufferRAM area
681 * @param buffer the databuffer to put/get data
682 * @param offset offset to read from or write to
683 * @param count number of bytes to read/write
684 *
685 * Read the BufferRAM area with Sync. Burst Mode
686 */
687static int onenand_sync_read_bufferram(struct mtd_info *mtd, int area,
688 unsigned char *buffer, int offset, size_t count)
689{
690 struct onenand_chip *this = mtd->priv;
691 void __iomem *bufferram;
692
693 bufferram = this->base + area;
694
695 bufferram += onenand_bufferram_offset(mtd, area);
696
697 this->mmcontrol(mtd, ONENAND_SYS_CFG1_SYNC_READ);
698
9c01f87d
KP
699 if (ONENAND_CHECK_BYTE_ACCESS(count)) {
700 unsigned short word;
701
702 /* Align with word(16-bit) size */
703 count--;
704
705 /* Read word and save byte */
706 word = this->read_word(bufferram + offset + count);
707 buffer[count] = (word & 0xff);
708 }
709
52b0eea7
KP
710 memcpy(buffer, bufferram + offset, count);
711
712 this->mmcontrol(mtd, 0);
713
714 return 0;
715}
716
cd5f6346
KP
717/**
718 * onenand_write_bufferram - [OneNAND Interface] Write the bufferram area
719 * @param mtd MTD data structure
720 * @param area BufferRAM area
721 * @param buffer the databuffer to put/get data
722 * @param offset offset to read from or write to
723 * @param count number of bytes to read/write
724 *
725 * Write the BufferRAM area
726 */
727static int onenand_write_bufferram(struct mtd_info *mtd, int area,
728 const unsigned char *buffer, int offset, size_t count)
729{
730 struct onenand_chip *this = mtd->priv;
731 void __iomem *bufferram;
732
733 bufferram = this->base + area;
734
735 bufferram += onenand_bufferram_offset(mtd, area);
736
9c01f87d
KP
737 if (ONENAND_CHECK_BYTE_ACCESS(count)) {
738 unsigned short word;
739 int byte_offset;
740
741 /* Align with word(16-bit) size */
742 count--;
743
744 /* Calculate byte access offset */
745 byte_offset = offset + count;
746
747 /* Read word and save byte */
748 word = this->read_word(bufferram + byte_offset);
749 word = (word & ~0xff) | buffer[count];
750 this->write_word(word, bufferram + byte_offset);
751 }
752
cd5f6346
KP
753 memcpy(bufferram + offset, buffer, count);
754
755 return 0;
756}
757
ee9745fc
KP
758/**
759 * onenand_get_2x_blockpage - [GENERIC] Get blockpage at 2x program mode
760 * @param mtd MTD data structure
761 * @param addr address to check
762 * @return blockpage address
763 *
764 * Get blockpage address at 2x program mode
765 */
766static int onenand_get_2x_blockpage(struct mtd_info *mtd, loff_t addr)
767{
768 struct onenand_chip *this = mtd->priv;
769 int blockpage, block, page;
770
771 /* Calculate the even block number */
772 block = (int) (addr >> this->erase_shift) & ~1;
773 /* Is it the odd plane? */
774 if (addr & this->writesize)
775 block++;
776 page = (int) (addr >> (this->page_shift + 1)) & this->page_mask;
777 blockpage = (block << 7) | page;
778
779 return blockpage;
780}
781
cd5f6346
KP
782/**
783 * onenand_check_bufferram - [GENERIC] Check BufferRAM information
784 * @param mtd MTD data structure
785 * @param addr address to check
d5c5e78a 786 * @return 1 if there are valid data, otherwise 0
cd5f6346
KP
787 *
788 * Check bufferram if there is data we required
789 */
790static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr)
791{
792 struct onenand_chip *this = mtd->priv;
cde36b37 793 int blockpage, found = 0;
abf3c0f2 794 unsigned int i;
d5c5e78a 795
ee9745fc
KP
796 if (ONENAND_IS_2PLANE(this))
797 blockpage = onenand_get_2x_blockpage(mtd, addr);
798 else
799 blockpage = (int) (addr >> this->page_shift);
cd5f6346 800
abf3c0f2 801 /* Is there valid data? */
cd5f6346 802 i = ONENAND_CURRENT_BUFFERRAM(this);
abf3c0f2 803 if (this->bufferram[i].blockpage == blockpage)
cde36b37
AH
804 found = 1;
805 else {
806 /* Check another BufferRAM */
807 i = ONENAND_NEXT_BUFFERRAM(this);
808 if (this->bufferram[i].blockpage == blockpage) {
809 ONENAND_SET_NEXT_BUFFERRAM(this);
810 found = 1;
811 }
812 }
cd5f6346 813
cde36b37
AH
814 if (found && ONENAND_IS_DDP(this)) {
815 /* Select DataRAM for DDP */
5988af23 816 int block = onenand_block(this, addr);
cde36b37
AH
817 int value = onenand_bufferram_address(this, block);
818 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
abf3c0f2 819 }
cd5f6346 820
cde36b37 821 return found;
cd5f6346
KP
822}
823
824/**
825 * onenand_update_bufferram - [GENERIC] Update BufferRAM information
826 * @param mtd MTD data structure
827 * @param addr address to update
828 * @param valid valid flag
829 *
830 * Update BufferRAM information
831 */
abf3c0f2 832static void onenand_update_bufferram(struct mtd_info *mtd, loff_t addr,
cd5f6346
KP
833 int valid)
834{
835 struct onenand_chip *this = mtd->priv;
abf3c0f2
KP
836 int blockpage;
837 unsigned int i;
d5c5e78a 838
ee9745fc
KP
839 if (ONENAND_IS_2PLANE(this))
840 blockpage = onenand_get_2x_blockpage(mtd, addr);
841 else
842 blockpage = (int) (addr >> this->page_shift);
cd5f6346 843
abf3c0f2
KP
844 /* Invalidate another BufferRAM */
845 i = ONENAND_NEXT_BUFFERRAM(this);
5b4246f1 846 if (this->bufferram[i].blockpage == blockpage)
abf3c0f2 847 this->bufferram[i].blockpage = -1;
cd5f6346
KP
848
849 /* Update BufferRAM */
850 i = ONENAND_CURRENT_BUFFERRAM(this);
abf3c0f2
KP
851 if (valid)
852 this->bufferram[i].blockpage = blockpage;
853 else
854 this->bufferram[i].blockpage = -1;
cd5f6346
KP
855}
856
480b9dfb
AH
857/**
858 * onenand_invalidate_bufferram - [GENERIC] Invalidate BufferRAM information
859 * @param mtd MTD data structure
860 * @param addr start address to invalidate
861 * @param len length to invalidate
862 *
863 * Invalidate BufferRAM information
864 */
865static void onenand_invalidate_bufferram(struct mtd_info *mtd, loff_t addr,
866 unsigned int len)
867{
868 struct onenand_chip *this = mtd->priv;
869 int i;
870 loff_t end_addr = addr + len;
871
872 /* Invalidate BufferRAM */
873 for (i = 0; i < MAX_BUFFERRAM; i++) {
874 loff_t buf_addr = this->bufferram[i].blockpage << this->page_shift;
875 if (buf_addr >= addr && buf_addr < end_addr)
876 this->bufferram[i].blockpage = -1;
877 }
878}
879
cd5f6346
KP
880/**
881 * onenand_get_device - [GENERIC] Get chip for selected access
882 * @param mtd MTD device structure
883 * @param new_state the state which is requested
884 *
885 * Get the device and lock it for exclusive access
886 */
a41371eb 887static int onenand_get_device(struct mtd_info *mtd, int new_state)
cd5f6346
KP
888{
889 struct onenand_chip *this = mtd->priv;
890 DECLARE_WAITQUEUE(wait, current);
891
892 /*
893 * Grab the lock and see if the device is available
894 */
895 while (1) {
896 spin_lock(&this->chip_lock);
897 if (this->state == FL_READY) {
898 this->state = new_state;
899 spin_unlock(&this->chip_lock);
900 break;
901 }
a41371eb
KP
902 if (new_state == FL_PM_SUSPENDED) {
903 spin_unlock(&this->chip_lock);
904 return (this->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
905 }
cd5f6346
KP
906 set_current_state(TASK_UNINTERRUPTIBLE);
907 add_wait_queue(&this->wq, &wait);
908 spin_unlock(&this->chip_lock);
909 schedule();
910 remove_wait_queue(&this->wq, &wait);
911 }
a41371eb
KP
912
913 return 0;
cd5f6346
KP
914}
915
916/**
917 * onenand_release_device - [GENERIC] release chip
918 * @param mtd MTD device structure
919 *
920 * Deselect, release chip lock and wake up anyone waiting on the device
921 */
922static void onenand_release_device(struct mtd_info *mtd)
923{
924 struct onenand_chip *this = mtd->priv;
925
926 /* Release the chip */
927 spin_lock(&this->chip_lock);
928 this->state = FL_READY;
929 wake_up(&this->wq);
930 spin_unlock(&this->chip_lock);
931}
932
933/**
d15057b7
KP
934 * onenand_transfer_auto_oob - [Internal] oob auto-placement transfer
935 * @param mtd MTD device structure
936 * @param buf destination address
937 * @param column oob offset to read from
938 * @param thislen oob length to read
939 */
940static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf, int column,
941 int thislen)
942{
943 struct onenand_chip *this = mtd->priv;
944 struct nand_oobfree *free;
945 int readcol = column;
946 int readend = column + thislen;
947 int lastgap = 0;
948 unsigned int i;
949 uint8_t *oob_buf = this->oob_buf;
950
951 free = this->ecclayout->oobfree;
952 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
953 if (readcol >= lastgap)
954 readcol += free->offset - lastgap;
955 if (readend >= lastgap)
956 readend += free->offset - lastgap;
957 lastgap = free->offset + free->length;
958 }
959 this->read_bufferram(mtd, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize);
960 free = this->ecclayout->oobfree;
961 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
962 int free_end = free->offset + free->length;
963 if (free->offset < readend && free_end > readcol) {
964 int st = max_t(int,free->offset,readcol);
965 int ed = min_t(int,free_end,readend);
966 int n = ed - st;
967 memcpy(buf, oob_buf + st, n);
968 buf += n;
969 } else if (column == 0)
970 break;
971 }
972 return 0;
973}
974
5988af23
RH
975/**
976 * onenand_recover_lsb - [Flex-OneNAND] Recover LSB page data
977 * @param mtd MTD device structure
978 * @param addr address to recover
979 * @param status return value from onenand_wait / onenand_bbt_wait
980 *
981 * MLC NAND Flash cell has paired pages - LSB page and MSB page. LSB page has
982 * lower page address and MSB page has higher page address in paired pages.
983 * If power off occurs during MSB page program, the paired LSB page data can
984 * become corrupt. LSB page recovery read is a way to read LSB page though page
985 * data are corrupted. When uncorrectable error occurs as a result of LSB page
986 * read after power up, issue LSB page recovery read.
987 */
988static int onenand_recover_lsb(struct mtd_info *mtd, loff_t addr, int status)
989{
990 struct onenand_chip *this = mtd->priv;
991 int i;
992
993 /* Recovery is only for Flex-OneNAND */
994 if (!FLEXONENAND(this))
995 return status;
996
997 /* check if we failed due to uncorrectable error */
998 if (status != -EBADMSG && status != ONENAND_BBT_READ_ECC_ERROR)
999 return status;
1000
1001 /* check if address lies in MLC region */
1002 i = flexonenand_region(mtd, addr);
1003 if (mtd->eraseregions[i].erasesize < (1 << this->erase_shift))
1004 return status;
1005
1006 /* We are attempting to reread, so decrement stats.failed
1007 * which was incremented by onenand_wait due to read failure
1008 */
1009 printk(KERN_INFO "onenand_recover_lsb: Attempting to recover from uncorrectable read\n");
1010 mtd->ecc_stats.failed--;
1011
1012 /* Issue the LSB page recovery command */
1013 this->command(mtd, FLEXONENAND_CMD_RECOVER_LSB, addr, this->writesize);
1014 return this->wait(mtd, FL_READING);
1015}
1016
1017/**
1018 * onenand_mlc_read_ops_nolock - MLC OneNAND read main and/or out-of-band
1019 * @param mtd MTD device structure
1020 * @param from offset to read from
1021 * @param ops: oob operation description structure
1022 *
1023 * MLC OneNAND / Flex-OneNAND has 4KB page size and 4KB dataram.
1024 * So, read-while-load is not present.
1025 */
1026static int onenand_mlc_read_ops_nolock(struct mtd_info *mtd, loff_t from,
1027 struct mtd_oob_ops *ops)
1028{
1029 struct onenand_chip *this = mtd->priv;
1030 struct mtd_ecc_stats stats;
1031 size_t len = ops->len;
1032 size_t ooblen = ops->ooblen;
1033 u_char *buf = ops->datbuf;
1034 u_char *oobbuf = ops->oobbuf;
1035 int read = 0, column, thislen;
1036 int oobread = 0, oobcolumn, thisooblen, oobsize;
1037 int ret = 0;
1038 int writesize = this->writesize;
1039
1040 DEBUG(MTD_DEBUG_LEVEL3, "onenand_mlc_read_ops_nolock: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
1041
1042 if (ops->mode == MTD_OOB_AUTO)
1043 oobsize = this->ecclayout->oobavail;
1044 else
1045 oobsize = mtd->oobsize;
1046
1047 oobcolumn = from & (mtd->oobsize - 1);
1048
1049 /* Do not allow reads past end of device */
1050 if (from + len > mtd->size) {
1051 printk(KERN_ERR "onenand_mlc_read_ops_nolock: Attempt read beyond end of device\n");
1052 ops->retlen = 0;
1053 ops->oobretlen = 0;
1054 return -EINVAL;
1055 }
1056
1057 stats = mtd->ecc_stats;
1058
1059 while (read < len) {
1060 cond_resched();
1061
1062 thislen = min_t(int, writesize, len - read);
1063
1064 column = from & (writesize - 1);
1065 if (column + thislen > writesize)
1066 thislen = writesize - column;
1067
1068 if (!onenand_check_bufferram(mtd, from)) {
1069 this->command(mtd, ONENAND_CMD_READ, from, writesize);
1070
1071 ret = this->wait(mtd, FL_READING);
1072 if (unlikely(ret))
1073 ret = onenand_recover_lsb(mtd, from, ret);
1074 onenand_update_bufferram(mtd, from, !ret);
1075 if (ret == -EBADMSG)
1076 ret = 0;
1077 }
1078
1079 this->read_bufferram(mtd, ONENAND_DATARAM, buf, column, thislen);
1080 if (oobbuf) {
1081 thisooblen = oobsize - oobcolumn;
1082 thisooblen = min_t(int, thisooblen, ooblen - oobread);
1083
1084 if (ops->mode == MTD_OOB_AUTO)
1085 onenand_transfer_auto_oob(mtd, oobbuf, oobcolumn, thisooblen);
1086 else
1087 this->read_bufferram(mtd, ONENAND_SPARERAM, oobbuf, oobcolumn, thisooblen);
1088 oobread += thisooblen;
1089 oobbuf += thisooblen;
1090 oobcolumn = 0;
1091 }
1092
1093 read += thislen;
1094 if (read == len)
1095 break;
1096
1097 from += thislen;
1098 buf += thislen;
1099 }
1100
1101 /*
1102 * Return success, if no ECC failures, else -EBADMSG
1103 * fs driver will take care of that, because
1104 * retlen == desired len and result == -EBADMSG
1105 */
1106 ops->retlen = read;
1107 ops->oobretlen = oobread;
1108
1109 if (ret)
1110 return ret;
1111
1112 if (mtd->ecc_stats.failed - stats.failed)
1113 return -EBADMSG;
1114
1115 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1116}
1117
d15057b7 1118/**
49dc08ee 1119 * onenand_read_ops_nolock - [OneNAND Interface] OneNAND read main and/or out-of-band
cd5f6346
KP
1120 * @param mtd MTD device structure
1121 * @param from offset to read from
d15057b7 1122 * @param ops: oob operation description structure
cd5f6346 1123 *
d15057b7
KP
1124 * OneNAND read main and/or out-of-band data
1125 */
49dc08ee 1126static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from,
d15057b7 1127 struct mtd_oob_ops *ops)
cd5f6346
KP
1128{
1129 struct onenand_chip *this = mtd->priv;
f4f91ac3 1130 struct mtd_ecc_stats stats;
d15057b7
KP
1131 size_t len = ops->len;
1132 size_t ooblen = ops->ooblen;
1133 u_char *buf = ops->datbuf;
1134 u_char *oobbuf = ops->oobbuf;
1135 int read = 0, column, thislen;
1136 int oobread = 0, oobcolumn, thisooblen, oobsize;
0fc2ccea 1137 int ret = 0, boundary = 0;
ee9745fc 1138 int writesize = this->writesize;
cd5f6346 1139
49dc08ee 1140 DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_ops_nolock: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
d15057b7
KP
1141
1142 if (ops->mode == MTD_OOB_AUTO)
1143 oobsize = this->ecclayout->oobavail;
1144 else
1145 oobsize = mtd->oobsize;
1146
1147 oobcolumn = from & (mtd->oobsize - 1);
cd5f6346
KP
1148
1149 /* Do not allow reads past end of device */
1150 if ((from + len) > mtd->size) {
49dc08ee 1151 printk(KERN_ERR "onenand_read_ops_nolock: Attempt read beyond end of device\n");
d15057b7
KP
1152 ops->retlen = 0;
1153 ops->oobretlen = 0;
cd5f6346
KP
1154 return -EINVAL;
1155 }
1156
f4f91ac3 1157 stats = mtd->ecc_stats;
61a7e198 1158
a8de85d5
AH
1159 /* Read-while-load method */
1160
1161 /* Do first load to bufferRAM */
1162 if (read < len) {
1163 if (!onenand_check_bufferram(mtd, from)) {
ee9745fc 1164 this->command(mtd, ONENAND_CMD_READ, from, writesize);
a8de85d5
AH
1165 ret = this->wait(mtd, FL_READING);
1166 onenand_update_bufferram(mtd, from, !ret);
5f4d47d5
AH
1167 if (ret == -EBADMSG)
1168 ret = 0;
a8de85d5
AH
1169 }
1170 }
1171
ee9745fc
KP
1172 thislen = min_t(int, writesize, len - read);
1173 column = from & (writesize - 1);
1174 if (column + thislen > writesize)
1175 thislen = writesize - column;
a8de85d5
AH
1176
1177 while (!ret) {
1178 /* If there is more to load then start next load */
1179 from += thislen;
1180 if (read + thislen < len) {
ee9745fc 1181 this->command(mtd, ONENAND_CMD_READ, from, writesize);
0fc2ccea
AH
1182 /*
1183 * Chip boundary handling in DDP
1184 * Now we issued chip 1 read and pointed chip 1
1185 * bufferam so we have to point chip 0 bufferam.
1186 */
738d61f5
KP
1187 if (ONENAND_IS_DDP(this) &&
1188 unlikely(from == (this->chipsize >> 1))) {
1189 this->write_word(ONENAND_DDP_CHIP0, this->base + ONENAND_REG_START_ADDRESS2);
0fc2ccea
AH
1190 boundary = 1;
1191 } else
1192 boundary = 0;
a8de85d5
AH
1193 ONENAND_SET_PREV_BUFFERRAM(this);
1194 }
1195 /* While load is going, read from last bufferRAM */
1196 this->read_bufferram(mtd, ONENAND_DATARAM, buf, column, thislen);
d15057b7
KP
1197
1198 /* Read oob area if needed */
1199 if (oobbuf) {
1200 thisooblen = oobsize - oobcolumn;
1201 thisooblen = min_t(int, thisooblen, ooblen - oobread);
1202
1203 if (ops->mode == MTD_OOB_AUTO)
1204 onenand_transfer_auto_oob(mtd, oobbuf, oobcolumn, thisooblen);
1205 else
1206 this->read_bufferram(mtd, ONENAND_SPARERAM, oobbuf, oobcolumn, thisooblen);
1207 oobread += thisooblen;
1208 oobbuf += thisooblen;
1209 oobcolumn = 0;
1210 }
1211
a8de85d5
AH
1212 /* See if we are done */
1213 read += thislen;
1214 if (read == len)
1215 break;
1216 /* Set up for next read from bufferRAM */
0fc2ccea 1217 if (unlikely(boundary))
738d61f5 1218 this->write_word(ONENAND_DDP_CHIP1, this->base + ONENAND_REG_START_ADDRESS2);
a8de85d5
AH
1219 ONENAND_SET_NEXT_BUFFERRAM(this);
1220 buf += thislen;
ee9745fc 1221 thislen = min_t(int, writesize, len - read);
a8de85d5
AH
1222 column = 0;
1223 cond_resched();
1224 /* Now wait for load */
1225 ret = this->wait(mtd, FL_READING);
1226 onenand_update_bufferram(mtd, from, !ret);
5f4d47d5
AH
1227 if (ret == -EBADMSG)
1228 ret = 0;
a8de85d5 1229 }
cd5f6346 1230
cd5f6346
KP
1231 /*
1232 * Return success, if no ECC failures, else -EBADMSG
1233 * fs driver will take care of that, because
1234 * retlen == desired len and result == -EBADMSG
1235 */
d15057b7
KP
1236 ops->retlen = read;
1237 ops->oobretlen = oobread;
f4f91ac3 1238
a8de85d5
AH
1239 if (ret)
1240 return ret;
1241
5f4d47d5
AH
1242 if (mtd->ecc_stats.failed - stats.failed)
1243 return -EBADMSG;
1244
f4f91ac3 1245 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
cd5f6346
KP
1246}
1247
cd5f6346 1248/**
49dc08ee 1249 * onenand_read_oob_nolock - [MTD Interface] OneNAND read out-of-band
cd5f6346
KP
1250 * @param mtd MTD device structure
1251 * @param from offset to read from
d15057b7 1252 * @param ops: oob operation description structure
cd5f6346
KP
1253 *
1254 * OneNAND read out-of-band data from the spare area
1255 */
49dc08ee 1256static int onenand_read_oob_nolock(struct mtd_info *mtd, loff_t from,
12f77c9e 1257 struct mtd_oob_ops *ops)
cd5f6346
KP
1258{
1259 struct onenand_chip *this = mtd->priv;
5f4d47d5 1260 struct mtd_ecc_stats stats;
a5e7c7b4 1261 int read = 0, thislen, column, oobsize;
12f77c9e
KP
1262 size_t len = ops->ooblen;
1263 mtd_oob_mode_t mode = ops->mode;
1264 u_char *buf = ops->oobbuf;
5988af23 1265 int ret = 0, readcmd;
cd5f6346 1266
12f77c9e
KP
1267 from += ops->ooboffs;
1268
49dc08ee 1269 DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_oob_nolock: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
cd5f6346
KP
1270
1271 /* Initialize return length value */
12f77c9e 1272 ops->oobretlen = 0;
cd5f6346 1273
a5e7c7b4
AH
1274 if (mode == MTD_OOB_AUTO)
1275 oobsize = this->ecclayout->oobavail;
1276 else
1277 oobsize = mtd->oobsize;
1278
1279 column = from & (mtd->oobsize - 1);
1280
1281 if (unlikely(column >= oobsize)) {
49dc08ee 1282 printk(KERN_ERR "onenand_read_oob_nolock: Attempted to start read outside oob\n");
a5e7c7b4
AH
1283 return -EINVAL;
1284 }
1285
cd5f6346 1286 /* Do not allow reads past end of device */
a5e7c7b4
AH
1287 if (unlikely(from >= mtd->size ||
1288 column + len > ((mtd->size >> this->page_shift) -
1289 (from >> this->page_shift)) * oobsize)) {
49dc08ee 1290 printk(KERN_ERR "onenand_read_oob_nolock: Attempted to read beyond end of device\n");
cd5f6346
KP
1291 return -EINVAL;
1292 }
1293
5f4d47d5
AH
1294 stats = mtd->ecc_stats;
1295
5988af23
RH
1296 readcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_READ : ONENAND_CMD_READOOB;
1297
cd5f6346 1298 while (read < len) {
61a7e198
AB
1299 cond_resched();
1300
a5e7c7b4 1301 thislen = oobsize - column;
cd5f6346
KP
1302 thislen = min_t(int, thislen, len);
1303
5988af23 1304 this->command(mtd, readcmd, from, mtd->oobsize);
cd5f6346
KP
1305
1306 onenand_update_bufferram(mtd, from, 0);
1307
1308 ret = this->wait(mtd, FL_READING);
5988af23
RH
1309 if (unlikely(ret))
1310 ret = onenand_recover_lsb(mtd, from, ret);
1311
5f4d47d5
AH
1312 if (ret && ret != -EBADMSG) {
1313 printk(KERN_ERR "onenand_read_oob_nolock: read failed = 0x%x\n", ret);
1314 break;
1315 }
cd5f6346 1316
a5e7c7b4
AH
1317 if (mode == MTD_OOB_AUTO)
1318 onenand_transfer_auto_oob(mtd, buf, column, thislen);
1319 else
1320 this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen);
cd5f6346
KP
1321
1322 read += thislen;
1323
1324 if (read == len)
1325 break;
1326
cd5f6346
KP
1327 buf += thislen;
1328
1329 /* Read more? */
1330 if (read < len) {
1331 /* Page size */
28318776 1332 from += mtd->writesize;
cd5f6346
KP
1333 column = 0;
1334 }
1335 }
1336
12f77c9e 1337 ops->oobretlen = read;
5f4d47d5
AH
1338
1339 if (ret)
1340 return ret;
1341
1342 if (mtd->ecc_stats.failed - stats.failed)
1343 return -EBADMSG;
1344
1345 return 0;
cd5f6346
KP
1346}
1347
8593fbc6 1348/**
d15057b7
KP
1349 * onenand_read - [MTD Interface] Read data from flash
1350 * @param mtd MTD device structure
1351 * @param from offset to read from
1352 * @param len number of bytes to read
1353 * @param retlen pointer to variable to store the number of read bytes
1354 * @param buf the databuffer to put data
1355 *
1356 * Read with ecc
1357*/
1358static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
1359 size_t *retlen, u_char *buf)
1360{
5988af23 1361 struct onenand_chip *this = mtd->priv;
d15057b7
KP
1362 struct mtd_oob_ops ops = {
1363 .len = len,
1364 .ooblen = 0,
1365 .datbuf = buf,
1366 .oobbuf = NULL,
1367 };
1368 int ret;
1369
49dc08ee 1370 onenand_get_device(mtd, FL_READING);
5988af23
RH
1371 ret = ONENAND_IS_MLC(this) ?
1372 onenand_mlc_read_ops_nolock(mtd, from, &ops) :
1373 onenand_read_ops_nolock(mtd, from, &ops);
49dc08ee 1374 onenand_release_device(mtd);
d15057b7 1375
49dc08ee 1376 *retlen = ops.retlen;
d15057b7
KP
1377 return ret;
1378}
1379
1380/**
1381 * onenand_read_oob - [MTD Interface] Read main and/or out-of-band
e3da8067
KP
1382 * @param mtd: MTD device structure
1383 * @param from: offset to read from
1384 * @param ops: oob operation description structure
d15057b7
KP
1385
1386 * Read main and/or out-of-band
8593fbc6
TG
1387 */
1388static int onenand_read_oob(struct mtd_info *mtd, loff_t from,
1389 struct mtd_oob_ops *ops)
1390{
5988af23 1391 struct onenand_chip *this = mtd->priv;
49dc08ee
AB
1392 int ret;
1393
4f4fad27 1394 switch (ops->mode) {
a5e7c7b4
AH
1395 case MTD_OOB_PLACE:
1396 case MTD_OOB_AUTO:
1397 break;
1398 case MTD_OOB_RAW:
4f4fad27 1399 /* Not implemented yet */
a5e7c7b4
AH
1400 default:
1401 return -EINVAL;
1402 }
d15057b7 1403
49dc08ee 1404 onenand_get_device(mtd, FL_READING);
d15057b7 1405 if (ops->datbuf)
5988af23
RH
1406 ret = ONENAND_IS_MLC(this) ?
1407 onenand_mlc_read_ops_nolock(mtd, from, ops) :
1408 onenand_read_ops_nolock(mtd, from, ops);
49dc08ee
AB
1409 else
1410 ret = onenand_read_oob_nolock(mtd, from, ops);
1411 onenand_release_device(mtd);
d15057b7 1412
49dc08ee 1413 return ret;
8593fbc6
TG
1414}
1415
211ac75f
KP
1416/**
1417 * onenand_bbt_wait - [DEFAULT] wait until the command is done
1418 * @param mtd MTD device structure
1419 * @param state state to select the max. timeout value
1420 *
1421 * Wait for command done.
1422 */
1423static int onenand_bbt_wait(struct mtd_info *mtd, int state)
1424{
1425 struct onenand_chip *this = mtd->priv;
1426 unsigned long timeout;
1427 unsigned int interrupt;
1428 unsigned int ctrl;
1429
1430 /* The 20 msec is enough */
1431 timeout = jiffies + msecs_to_jiffies(20);
1432 while (time_before(jiffies, timeout)) {
1433 interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
1434 if (interrupt & ONENAND_INT_MASTER)
1435 break;
1436 }
1437 /* To get correct interrupt status in timeout case */
1438 interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
1439 ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
1440
211ac75f 1441 if (interrupt & ONENAND_INT_READ) {
5988af23 1442 int ecc = onenand_read_ecc(this);
83973b87
KP
1443 if (ecc & ONENAND_ECC_2BIT_ALL) {
1444 printk(KERN_INFO "onenand_bbt_wait: ecc error = 0x%04x"
1445 ", controller error 0x%04x\n", ecc, ctrl);
5988af23 1446 return ONENAND_BBT_READ_ECC_ERROR;
83973b87 1447 }
211ac75f
KP
1448 } else {
1449 printk(KERN_ERR "onenand_bbt_wait: read timeout!"
1450 "ctrl=0x%04x intr=0x%04x\n", ctrl, interrupt);
1451 return ONENAND_BBT_READ_FATAL_ERROR;
1452 }
1453
83973b87
KP
1454 /* Initial bad block case: 0x2400 or 0x0400 */
1455 if (ctrl & ONENAND_CTRL_ERROR) {
1456 printk(KERN_DEBUG "onenand_bbt_wait: "
1457 "controller error = 0x%04x\n", ctrl);
1458 return ONENAND_BBT_READ_ERROR;
1459 }
1460
211ac75f
KP
1461 return 0;
1462}
1463
1464/**
1465 * onenand_bbt_read_oob - [MTD Interface] OneNAND read out-of-band for bbt scan
1466 * @param mtd MTD device structure
1467 * @param from offset to read from
e3da8067 1468 * @param ops oob operation description structure
211ac75f
KP
1469 *
1470 * OneNAND read out-of-band data from the spare area for bbt scan
1471 */
1472int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from,
1473 struct mtd_oob_ops *ops)
1474{
1475 struct onenand_chip *this = mtd->priv;
1476 int read = 0, thislen, column;
5988af23 1477 int ret = 0, readcmd;
211ac75f
KP
1478 size_t len = ops->ooblen;
1479 u_char *buf = ops->oobbuf;
1480
5785bdd6 1481 DEBUG(MTD_DEBUG_LEVEL3, "onenand_bbt_read_oob: from = 0x%08x, len = %zi\n", (unsigned int) from, len);
211ac75f
KP
1482
1483 /* Initialize return value */
1484 ops->oobretlen = 0;
1485
1486 /* Do not allow reads past end of device */
1487 if (unlikely((from + len) > mtd->size)) {
1488 printk(KERN_ERR "onenand_bbt_read_oob: Attempt read beyond end of device\n");
1489 return ONENAND_BBT_READ_FATAL_ERROR;
1490 }
1491
1492 /* Grab the lock and see if the device is available */
1493 onenand_get_device(mtd, FL_READING);
1494
1495 column = from & (mtd->oobsize - 1);
1496
5988af23
RH
1497 readcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_READ : ONENAND_CMD_READOOB;
1498
211ac75f
KP
1499 while (read < len) {
1500 cond_resched();
1501
1502 thislen = mtd->oobsize - column;
1503 thislen = min_t(int, thislen, len);
1504
5988af23 1505 this->command(mtd, readcmd, from, mtd->oobsize);
211ac75f
KP
1506
1507 onenand_update_bufferram(mtd, from, 0);
1508
31bb999e 1509 ret = this->bbt_wait(mtd, FL_READING);
5988af23
RH
1510 if (unlikely(ret))
1511 ret = onenand_recover_lsb(mtd, from, ret);
1512
211ac75f
KP
1513 if (ret)
1514 break;
1515
1516 this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen);
1517 read += thislen;
1518 if (read == len)
1519 break;
1520
1521 buf += thislen;
1522
1523 /* Read more? */
1524 if (read < len) {
1525 /* Update Page size */
ee9745fc 1526 from += this->writesize;
211ac75f
KP
1527 column = 0;
1528 }
1529 }
1530
1531 /* Deselect and wake up anyone waiting on the device */
1532 onenand_release_device(mtd);
1533
1534 ops->oobretlen = read;
1535 return ret;
1536}
1537
cd5f6346 1538#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
8e6ec690
KP
1539/**
1540 * onenand_verify_oob - [GENERIC] verify the oob contents after a write
1541 * @param mtd MTD device structure
1542 * @param buf the databuffer to verify
1543 * @param to offset to read from
8e6ec690 1544 */
a5e7c7b4 1545static int onenand_verify_oob(struct mtd_info *mtd, const u_char *buf, loff_t to)
8e6ec690
KP
1546{
1547 struct onenand_chip *this = mtd->priv;
69d79186 1548 u_char *oob_buf = this->oob_buf;
5988af23
RH
1549 int status, i, readcmd;
1550
1551 readcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_READ : ONENAND_CMD_READOOB;
8e6ec690 1552
5988af23 1553 this->command(mtd, readcmd, to, mtd->oobsize);
8e6ec690
KP
1554 onenand_update_bufferram(mtd, to, 0);
1555 status = this->wait(mtd, FL_READING);
1556 if (status)
1557 return status;
1558
69d79186 1559 this->read_bufferram(mtd, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize);
91014e9b 1560 for (i = 0; i < mtd->oobsize; i++)
69d79186 1561 if (buf[i] != 0xFF && buf[i] != oob_buf[i])
8e6ec690
KP
1562 return -EBADMSG;
1563
1564 return 0;
1565}
1566
cd5f6346 1567/**
8b29c0b6
AH
1568 * onenand_verify - [GENERIC] verify the chip contents after a write
1569 * @param mtd MTD device structure
1570 * @param buf the databuffer to verify
1571 * @param addr offset to read from
1572 * @param len number of bytes to read and compare
cd5f6346 1573 */
8b29c0b6 1574static int onenand_verify(struct mtd_info *mtd, const u_char *buf, loff_t addr, size_t len)
cd5f6346
KP
1575{
1576 struct onenand_chip *this = mtd->priv;
8b29c0b6 1577 void __iomem *dataram;
cd5f6346 1578 int ret = 0;
8b29c0b6 1579 int thislen, column;
cd5f6346 1580
8b29c0b6 1581 while (len != 0) {
ee9745fc
KP
1582 thislen = min_t(int, this->writesize, len);
1583 column = addr & (this->writesize - 1);
1584 if (column + thislen > this->writesize)
1585 thislen = this->writesize - column;
60d84f97 1586
ee9745fc 1587 this->command(mtd, ONENAND_CMD_READ, addr, this->writesize);
cd5f6346 1588
8b29c0b6
AH
1589 onenand_update_bufferram(mtd, addr, 0);
1590
1591 ret = this->wait(mtd, FL_READING);
1592 if (ret)
1593 return ret;
cd5f6346 1594
8b29c0b6 1595 onenand_update_bufferram(mtd, addr, 1);
cd5f6346 1596
8b29c0b6
AH
1597 dataram = this->base + ONENAND_DATARAM;
1598 dataram += onenand_bufferram_offset(mtd, ONENAND_DATARAM);
cd5f6346 1599
8b29c0b6
AH
1600 if (memcmp(buf, dataram + column, thislen))
1601 return -EBADMSG;
1602
1603 len -= thislen;
1604 buf += thislen;
1605 addr += thislen;
1606 }
d5c5e78a 1607
cd5f6346
KP
1608 return 0;
1609}
1610#else
8b29c0b6 1611#define onenand_verify(...) (0)
8e6ec690 1612#define onenand_verify_oob(...) (0)
cd5f6346
KP
1613#endif
1614
60d84f97 1615#define NOTALIGNED(x) ((x & (this->subpagesize - 1)) != 0)
cd5f6346 1616
6c77fd64
RP
1617static void onenand_panic_wait(struct mtd_info *mtd)
1618{
1619 struct onenand_chip *this = mtd->priv;
1620 unsigned int interrupt;
1621 int i;
1622
1623 for (i = 0; i < 2000; i++) {
1624 interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
1625 if (interrupt & ONENAND_INT_MASTER)
1626 break;
1627 udelay(10);
1628 }
1629}
1630
1631/**
1632 * onenand_panic_write - [MTD Interface] write buffer to FLASH in a panic context
1633 * @param mtd MTD device structure
1634 * @param to offset to write to
1635 * @param len number of bytes to write
1636 * @param retlen pointer to variable to store the number of written bytes
1637 * @param buf the data to write
1638 *
1639 * Write with ECC
1640 */
1641static int onenand_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
1642 size_t *retlen, const u_char *buf)
1643{
1644 struct onenand_chip *this = mtd->priv;
1645 int column, subpage;
1646 int written = 0;
1647 int ret = 0;
1648
1649 if (this->state == FL_PM_SUSPENDED)
1650 return -EBUSY;
1651
1652 /* Wait for any existing operation to clear */
1653 onenand_panic_wait(mtd);
1654
1655 DEBUG(MTD_DEBUG_LEVEL3, "onenand_panic_write: to = 0x%08x, len = %i\n",
1656 (unsigned int) to, (int) len);
1657
1658 /* Initialize retlen, in case of early exit */
1659 *retlen = 0;
1660
1661 /* Do not allow writes past end of device */
1662 if (unlikely((to + len) > mtd->size)) {
1663 printk(KERN_ERR "onenand_panic_write: Attempt write to past end of device\n");
1664 return -EINVAL;
1665 }
1666
1667 /* Reject writes, which are not page aligned */
b73d7e43 1668 if (unlikely(NOTALIGNED(to) || NOTALIGNED(len))) {
6c77fd64
RP
1669 printk(KERN_ERR "onenand_panic_write: Attempt to write not page aligned data\n");
1670 return -EINVAL;
1671 }
1672
1673 column = to & (mtd->writesize - 1);
1674
1675 /* Loop until all data write */
1676 while (written < len) {
1677 int thislen = min_t(int, mtd->writesize - column, len - written);
1678 u_char *wbuf = (u_char *) buf;
1679
1680 this->command(mtd, ONENAND_CMD_BUFFERRAM, to, thislen);
1681
1682 /* Partial page write */
1683 subpage = thislen < mtd->writesize;
1684 if (subpage) {
1685 memset(this->page_buf, 0xff, mtd->writesize);
1686 memcpy(this->page_buf + column, buf, thislen);
1687 wbuf = this->page_buf;
1688 }
1689
1690 this->write_bufferram(mtd, ONENAND_DATARAM, wbuf, 0, mtd->writesize);
1691 this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0, mtd->oobsize);
1692
1693 this->command(mtd, ONENAND_CMD_PROG, to, mtd->writesize);
1694
1695 onenand_panic_wait(mtd);
1696
1697 /* In partial page write we don't update bufferram */
1698 onenand_update_bufferram(mtd, to, !ret && !subpage);
1699 if (ONENAND_IS_2PLANE(this)) {
1700 ONENAND_SET_BUFFERRAM1(this);
1701 onenand_update_bufferram(mtd, to + this->writesize, !ret && !subpage);
1702 }
1703
1704 if (ret) {
1705 printk(KERN_ERR "onenand_panic_write: write failed %d\n", ret);
1706 break;
1707 }
1708
1709 written += thislen;
1710
1711 if (written == len)
1712 break;
1713
1714 column = 0;
1715 to += thislen;
1716 buf += thislen;
1717 }
1718
1719 *retlen = written;
1720 return ret;
1721}
1722
cd5f6346 1723/**
d15057b7
KP
1724 * onenand_fill_auto_oob - [Internal] oob auto-placement transfer
1725 * @param mtd MTD device structure
1726 * @param oob_buf oob buffer
1727 * @param buf source address
1728 * @param column oob offset to write to
1729 * @param thislen oob length to write
1730 */
1731static int onenand_fill_auto_oob(struct mtd_info *mtd, u_char *oob_buf,
1732 const u_char *buf, int column, int thislen)
1733{
1734 struct onenand_chip *this = mtd->priv;
1735 struct nand_oobfree *free;
1736 int writecol = column;
1737 int writeend = column + thislen;
1738 int lastgap = 0;
1739 unsigned int i;
1740
1741 free = this->ecclayout->oobfree;
1742 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
1743 if (writecol >= lastgap)
1744 writecol += free->offset - lastgap;
1745 if (writeend >= lastgap)
1746 writeend += free->offset - lastgap;
1747 lastgap = free->offset + free->length;
1748 }
1749 free = this->ecclayout->oobfree;
1750 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
1751 int free_end = free->offset + free->length;
1752 if (free->offset < writeend && free_end > writecol) {
1753 int st = max_t(int,free->offset,writecol);
1754 int ed = min_t(int,free_end,writeend);
1755 int n = ed - st;
1756 memcpy(oob_buf + st, buf, n);
1757 buf += n;
1758 } else if (column == 0)
1759 break;
1760 }
1761 return 0;
1762}
1763
1764/**
49dc08ee 1765 * onenand_write_ops_nolock - [OneNAND Interface] write main and/or out-of-band
cd5f6346
KP
1766 * @param mtd MTD device structure
1767 * @param to offset to write to
d15057b7 1768 * @param ops oob operation description structure
cd5f6346 1769 *
d15057b7 1770 * Write main and/or oob with ECC
cd5f6346 1771 */
49dc08ee 1772static int onenand_write_ops_nolock(struct mtd_info *mtd, loff_t to,
d15057b7 1773 struct mtd_oob_ops *ops)
cd5f6346
KP
1774{
1775 struct onenand_chip *this = mtd->priv;
9ce96908
KP
1776 int written = 0, column, thislen = 0, subpage = 0;
1777 int prev = 0, prevlen = 0, prev_subpage = 0, first = 1;
d15057b7
KP
1778 int oobwritten = 0, oobcolumn, thisooblen, oobsize;
1779 size_t len = ops->len;
1780 size_t ooblen = ops->ooblen;
1781 const u_char *buf = ops->datbuf;
1782 const u_char *oob = ops->oobbuf;
1783 u_char *oobbuf;
cd5f6346
KP
1784 int ret = 0;
1785
49dc08ee 1786 DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_ops_nolock: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
cd5f6346
KP
1787
1788 /* Initialize retlen, in case of early exit */
d15057b7
KP
1789 ops->retlen = 0;
1790 ops->oobretlen = 0;
cd5f6346
KP
1791
1792 /* Do not allow writes past end of device */
1793 if (unlikely((to + len) > mtd->size)) {
49dc08ee 1794 printk(KERN_ERR "onenand_write_ops_nolock: Attempt write to past end of device\n");
cd5f6346
KP
1795 return -EINVAL;
1796 }
1797
1798 /* Reject writes, which are not page aligned */
b73d7e43 1799 if (unlikely(NOTALIGNED(to) || NOTALIGNED(len))) {
49dc08ee 1800 printk(KERN_ERR "onenand_write_ops_nolock: Attempt to write not page aligned data\n");
cd5f6346
KP
1801 return -EINVAL;
1802 }
1803
9ce96908
KP
1804 /* Check zero length */
1805 if (!len)
1806 return 0;
1807
d15057b7
KP
1808 if (ops->mode == MTD_OOB_AUTO)
1809 oobsize = this->ecclayout->oobavail;
1810 else
1811 oobsize = mtd->oobsize;
1812
1813 oobcolumn = to & (mtd->oobsize - 1);
1814
60d84f97 1815 column = to & (mtd->writesize - 1);
60d84f97 1816
cd5f6346 1817 /* Loop until all data write */
9ce96908
KP
1818 while (1) {
1819 if (written < len) {
1820 u_char *wbuf = (u_char *) buf;
60d84f97 1821
9ce96908
KP
1822 thislen = min_t(int, mtd->writesize - column, len - written);
1823 thisooblen = min_t(int, oobsize - oobcolumn, ooblen - oobwritten);
d15057b7 1824
9ce96908 1825 cond_resched();
61a7e198 1826
9ce96908 1827 this->command(mtd, ONENAND_CMD_BUFFERRAM, to, thislen);
60d84f97 1828
9ce96908
KP
1829 /* Partial page write */
1830 subpage = thislen < mtd->writesize;
1831 if (subpage) {
1832 memset(this->page_buf, 0xff, mtd->writesize);
1833 memcpy(this->page_buf + column, buf, thislen);
1834 wbuf = this->page_buf;
1835 }
cd5f6346 1836
9ce96908 1837 this->write_bufferram(mtd, ONENAND_DATARAM, wbuf, 0, mtd->writesize);
d15057b7 1838
9ce96908
KP
1839 if (oob) {
1840 oobbuf = this->oob_buf;
d15057b7 1841
9ce96908
KP
1842 /* We send data to spare ram with oobsize
1843 * to prevent byte access */
1844 memset(oobbuf, 0xff, mtd->oobsize);
1845 if (ops->mode == MTD_OOB_AUTO)
1846 onenand_fill_auto_oob(mtd, oobbuf, oob, oobcolumn, thisooblen);
1847 else
1848 memcpy(oobbuf + oobcolumn, oob, thisooblen);
d15057b7 1849
9ce96908
KP
1850 oobwritten += thisooblen;
1851 oob += thisooblen;
1852 oobcolumn = 0;
1853 } else
1854 oobbuf = (u_char *) ffchars;
1855
1856 this->write_bufferram(mtd, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize);
d15057b7 1857 } else
9ce96908 1858 ONENAND_SET_NEXT_BUFFERRAM(this);
d15057b7 1859
9ce96908
KP
1860 /*
1861 * 2 PLANE, MLC, and Flex-OneNAND doesn't support
1862 * write-while-programe feature.
1863 */
1864 if (!ONENAND_IS_2PLANE(this) && !first) {
1865 ONENAND_SET_PREV_BUFFERRAM(this);
1866
1867 ret = this->wait(mtd, FL_WRITING);
1868
1869 /* In partial page write we don't update bufferram */
1870 onenand_update_bufferram(mtd, prev, !ret && !prev_subpage);
1871 if (ret) {
1872 written -= prevlen;
1873 printk(KERN_ERR "onenand_write_ops_nolock: write filaed %d\n", ret);
1874 break;
1875 }
cd5f6346 1876
9ce96908
KP
1877 if (written == len) {
1878 /* Only check verify write turn on */
1879 ret = onenand_verify(mtd, buf - len, to - len, len);
1880 if (ret)
1881 printk(KERN_ERR "onenand_write_ops_nolock: verify failed %d\n", ret);
1882 break;
1883 }
cd5f6346 1884
9ce96908
KP
1885 ONENAND_SET_NEXT_BUFFERRAM(this);
1886 }
81f38e11 1887
9ce96908
KP
1888 this->command(mtd, ONENAND_CMD_PROG, to, mtd->writesize);
1889
1890 /*
1891 * 2 PLANE, MLC, and Flex-OneNAND wait here
1892 */
ee9745fc 1893 if (ONENAND_IS_2PLANE(this)) {
9ce96908 1894 ret = this->wait(mtd, FL_WRITING);
cd5f6346 1895
9ce96908
KP
1896 /* In partial page write we don't update bufferram */
1897 onenand_update_bufferram(mtd, to, !ret && !subpage);
1898 if (ret) {
1899 printk(KERN_ERR "onenand_write_ops_nolock: write filaed %d\n", ret);
1900 break;
1901 }
cd5f6346 1902
9ce96908
KP
1903 /* Only check verify write turn on */
1904 ret = onenand_verify(mtd, buf, to, thislen);
1905 if (ret) {
1906 printk(KERN_ERR "onenand_write_ops_nolock: verify failed %d\n", ret);
1907 break;
1908 }
cd5f6346 1909
9ce96908 1910 written += thislen;
81f38e11 1911
9ce96908
KP
1912 if (written == len)
1913 break;
1914
1915 } else
1916 written += thislen;
cd5f6346 1917
60d84f97 1918 column = 0;
9ce96908
KP
1919 prev_subpage = subpage;
1920 prev = to;
1921 prevlen = thislen;
cd5f6346
KP
1922 to += thislen;
1923 buf += thislen;
9ce96908 1924 first = 0;
cd5f6346
KP
1925 }
1926
9ce96908
KP
1927 /* In error case, clear all bufferrams */
1928 if (written != len)
1929 onenand_invalidate_bufferram(mtd, 0, -1);
1930
d15057b7 1931 ops->retlen = written;
9ce96908 1932 ops->oobretlen = oobwritten;
d5c5e78a 1933
cd5f6346
KP
1934 return ret;
1935}
1936
a5e7c7b4 1937
cd5f6346 1938/**
49dc08ee 1939 * onenand_write_oob_nolock - [Internal] OneNAND write out-of-band
cd5f6346
KP
1940 * @param mtd MTD device structure
1941 * @param to offset to write to
1942 * @param len number of bytes to write
1943 * @param retlen pointer to variable to store the number of written bytes
1944 * @param buf the data to write
a5e7c7b4 1945 * @param mode operation mode
cd5f6346
KP
1946 *
1947 * OneNAND write out-of-band
1948 */
49dc08ee
AB
1949static int onenand_write_oob_nolock(struct mtd_info *mtd, loff_t to,
1950 struct mtd_oob_ops *ops)
cd5f6346
KP
1951{
1952 struct onenand_chip *this = mtd->priv;
a5e7c7b4 1953 int column, ret = 0, oobsize;
5988af23 1954 int written = 0, oobcmd;
91014e9b 1955 u_char *oobbuf;
12f77c9e
KP
1956 size_t len = ops->ooblen;
1957 const u_char *buf = ops->oobbuf;
1958 mtd_oob_mode_t mode = ops->mode;
1959
1960 to += ops->ooboffs;
cd5f6346 1961
49dc08ee 1962 DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_oob_nolock: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
cd5f6346
KP
1963
1964 /* Initialize retlen, in case of early exit */
12f77c9e 1965 ops->oobretlen = 0;
cd5f6346 1966
a5e7c7b4
AH
1967 if (mode == MTD_OOB_AUTO)
1968 oobsize = this->ecclayout->oobavail;
1969 else
1970 oobsize = mtd->oobsize;
1971
1972 column = to & (mtd->oobsize - 1);
1973
1974 if (unlikely(column >= oobsize)) {
49dc08ee 1975 printk(KERN_ERR "onenand_write_oob_nolock: Attempted to start write outside oob\n");
a5e7c7b4
AH
1976 return -EINVAL;
1977 }
1978
52e4200a 1979 /* For compatibility with NAND: Do not allow write past end of page */
91014e9b 1980 if (unlikely(column + len > oobsize)) {
49dc08ee 1981 printk(KERN_ERR "onenand_write_oob_nolock: "
52e4200a
AH
1982 "Attempt to write past end of page\n");
1983 return -EINVAL;
1984 }
1985
a5e7c7b4
AH
1986 /* Do not allow reads past end of device */
1987 if (unlikely(to >= mtd->size ||
1988 column + len > ((mtd->size >> this->page_shift) -
1989 (to >> this->page_shift)) * oobsize)) {
49dc08ee 1990 printk(KERN_ERR "onenand_write_oob_nolock: Attempted to write past end of device\n");
cd5f6346
KP
1991 return -EINVAL;
1992 }
1993
470bc844 1994 oobbuf = this->oob_buf;
91014e9b 1995
5988af23
RH
1996 oobcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_PROG : ONENAND_CMD_PROGOOB;
1997
cd5f6346
KP
1998 /* Loop until all data write */
1999 while (written < len) {
a5e7c7b4 2000 int thislen = min_t(int, oobsize, len - written);
cd5f6346 2001
61a7e198
AB
2002 cond_resched();
2003
cd5f6346
KP
2004 this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobsize);
2005
34c10609
KP
2006 /* We send data to spare ram with oobsize
2007 * to prevent byte access */
91014e9b 2008 memset(oobbuf, 0xff, mtd->oobsize);
a5e7c7b4 2009 if (mode == MTD_OOB_AUTO)
91014e9b 2010 onenand_fill_auto_oob(mtd, oobbuf, buf, column, thislen);
a5e7c7b4 2011 else
91014e9b
KP
2012 memcpy(oobbuf + column, buf, thislen);
2013 this->write_bufferram(mtd, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize);
cd5f6346 2014
5988af23
RH
2015 if (ONENAND_IS_MLC(this)) {
2016 /* Set main area of DataRAM to 0xff*/
2017 memset(this->page_buf, 0xff, mtd->writesize);
2018 this->write_bufferram(mtd, ONENAND_DATARAM,
2019 this->page_buf, 0, mtd->writesize);
2020 }
2021
2022 this->command(mtd, oobcmd, to, mtd->oobsize);
cd5f6346
KP
2023
2024 onenand_update_bufferram(mtd, to, 0);
ee9745fc
KP
2025 if (ONENAND_IS_2PLANE(this)) {
2026 ONENAND_SET_BUFFERRAM1(this);
2027 onenand_update_bufferram(mtd, to + this->writesize, 0);
2028 }
cd5f6346 2029
8e6ec690
KP
2030 ret = this->wait(mtd, FL_WRITING);
2031 if (ret) {
49dc08ee 2032 printk(KERN_ERR "onenand_write_oob_nolock: write failed %d\n", ret);
5b4246f1 2033 break;
8e6ec690
KP
2034 }
2035
91014e9b 2036 ret = onenand_verify_oob(mtd, oobbuf, to);
8e6ec690 2037 if (ret) {
49dc08ee 2038 printk(KERN_ERR "onenand_write_oob_nolock: verify failed %d\n", ret);
5b4246f1 2039 break;
8e6ec690 2040 }
cd5f6346
KP
2041
2042 written += thislen;
cd5f6346
KP
2043 if (written == len)
2044 break;
2045
a5e7c7b4 2046 to += mtd->writesize;
cd5f6346 2047 buf += thislen;
a5e7c7b4 2048 column = 0;
cd5f6346
KP
2049 }
2050
12f77c9e 2051 ops->oobretlen = written;
d5c5e78a 2052
8e6ec690 2053 return ret;
cd5f6346
KP
2054}
2055
d15057b7
KP
2056/**
2057 * onenand_write - [MTD Interface] write buffer to FLASH
2058 * @param mtd MTD device structure
2059 * @param to offset to write to
2060 * @param len number of bytes to write
2061 * @param retlen pointer to variable to store the number of written bytes
2062 * @param buf the data to write
2063 *
2064 * Write with ECC
2065 */
2066static int onenand_write(struct mtd_info *mtd, loff_t to, size_t len,
2067 size_t *retlen, const u_char *buf)
2068{
2069 struct mtd_oob_ops ops = {
2070 .len = len,
2071 .ooblen = 0,
2072 .datbuf = (u_char *) buf,
2073 .oobbuf = NULL,
2074 };
2075 int ret;
2076
49dc08ee
AB
2077 onenand_get_device(mtd, FL_WRITING);
2078 ret = onenand_write_ops_nolock(mtd, to, &ops);
2079 onenand_release_device(mtd);
d15057b7 2080
49dc08ee 2081 *retlen = ops.retlen;
d15057b7
KP
2082 return ret;
2083}
2084
8593fbc6
TG
2085/**
2086 * onenand_write_oob - [MTD Interface] NAND write data and/or out-of-band
e3da8067
KP
2087 * @param mtd: MTD device structure
2088 * @param to: offset to write
2089 * @param ops: oob operation description structure
8593fbc6
TG
2090 */
2091static int onenand_write_oob(struct mtd_info *mtd, loff_t to,
2092 struct mtd_oob_ops *ops)
2093{
49dc08ee
AB
2094 int ret;
2095
4f4fad27 2096 switch (ops->mode) {
a5e7c7b4
AH
2097 case MTD_OOB_PLACE:
2098 case MTD_OOB_AUTO:
2099 break;
2100 case MTD_OOB_RAW:
4f4fad27 2101 /* Not implemented yet */
a5e7c7b4
AH
2102 default:
2103 return -EINVAL;
2104 }
d15057b7 2105
49dc08ee 2106 onenand_get_device(mtd, FL_WRITING);
d15057b7 2107 if (ops->datbuf)
49dc08ee
AB
2108 ret = onenand_write_ops_nolock(mtd, to, ops);
2109 else
2110 ret = onenand_write_oob_nolock(mtd, to, ops);
2111 onenand_release_device(mtd);
d15057b7 2112
49dc08ee 2113 return ret;
8593fbc6
TG
2114}
2115
cdc00130 2116/**
49dc08ee 2117 * onenand_block_isbad_nolock - [GENERIC] Check if a block is marked bad
cdc00130
KP
2118 * @param mtd MTD device structure
2119 * @param ofs offset from device start
cdc00130
KP
2120 * @param allowbbt 1, if its allowed to access the bbt area
2121 *
2122 * Check, if the block is bad. Either by reading the bad block table or
2123 * calling of the scan function.
2124 */
49dc08ee 2125static int onenand_block_isbad_nolock(struct mtd_info *mtd, loff_t ofs, int allowbbt)
cdc00130
KP
2126{
2127 struct onenand_chip *this = mtd->priv;
2128 struct bbm_info *bbm = this->bbm;
2129
2130 /* Return info from the table */
2131 return bbm->isbad_bbt(mtd, ofs, allowbbt);
2132}
2133
cd5f6346
KP
2134/**
2135 * onenand_erase - [MTD Interface] erase block(s)
2136 * @param mtd MTD device structure
2137 * @param instr erase instruction
2138 *
2139 * Erase one ore more blocks
2140 */
2141static int onenand_erase(struct mtd_info *mtd, struct erase_info *instr)
2142{
2143 struct onenand_chip *this = mtd->priv;
2144 unsigned int block_size;
5988af23
RH
2145 loff_t addr = instr->addr;
2146 loff_t len = instr->len;
2147 int ret = 0, i;
2148 struct mtd_erase_region_info *region = NULL;
2149 loff_t region_end = 0;
cd5f6346 2150
69423d99 2151 DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%012llx, len = %llu\n", (unsigned long long) instr->addr, (unsigned long long) instr->len);
cd5f6346 2152
5988af23
RH
2153 /* Do not allow erase past end of device */
2154 if (unlikely((len + addr) > mtd->size)) {
2155 printk(KERN_ERR "onenand_erase: Erase past end of device\n");
cd5f6346
KP
2156 return -EINVAL;
2157 }
2158
5988af23
RH
2159 if (FLEXONENAND(this)) {
2160 /* Find the eraseregion of this address */
2161 i = flexonenand_region(mtd, addr);
2162 region = &mtd->eraseregions[i];
2163
2164 block_size = region->erasesize;
2165 region_end = region->offset + region->erasesize * region->numblocks;
2166
2167 /* Start address within region must align on block boundary.
2168 * Erase region's start offset is always block start address.
2169 */
2170 if (unlikely((addr - region->offset) & (block_size - 1))) {
2171 printk(KERN_ERR "onenand_erase: Unaligned address\n");
2172 return -EINVAL;
2173 }
2174 } else {
2175 block_size = 1 << this->erase_shift;
2176
2177 /* Start address must align on block boundary */
2178 if (unlikely(addr & (block_size - 1))) {
2179 printk(KERN_ERR "onenand_erase: Unaligned address\n");
2180 return -EINVAL;
2181 }
cd5f6346
KP
2182 }
2183
5988af23
RH
2184 /* Length must align on block boundary */
2185 if (unlikely(len & (block_size - 1))) {
2186 printk(KERN_ERR "onenand_erase: Length not block aligned\n");
cd5f6346
KP
2187 return -EINVAL;
2188 }
2189
bb0eb217 2190 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
cd5f6346
KP
2191
2192 /* Grab the lock and see if the device is available */
2193 onenand_get_device(mtd, FL_ERASING);
2194
2195 /* Loop throught the pages */
cd5f6346
KP
2196 instr->state = MTD_ERASING;
2197
2198 while (len) {
61a7e198 2199 cond_resched();
cd5f6346 2200
cdc00130 2201 /* Check if we have a bad block, we do not erase bad blocks */
49dc08ee 2202 if (onenand_block_isbad_nolock(mtd, addr, 0)) {
69423d99 2203 printk (KERN_WARNING "onenand_erase: attempt to erase a bad block at addr 0x%012llx\n", (unsigned long long) addr);
cdc00130
KP
2204 instr->state = MTD_ERASE_FAILED;
2205 goto erase_exit;
2206 }
cd5f6346
KP
2207
2208 this->command(mtd, ONENAND_CMD_ERASE, addr, block_size);
2209
480b9dfb
AH
2210 onenand_invalidate_bufferram(mtd, addr, block_size);
2211
cd5f6346
KP
2212 ret = this->wait(mtd, FL_ERASING);
2213 /* Check, if it is write protected */
2214 if (ret) {
5988af23
RH
2215 printk(KERN_ERR "onenand_erase: Failed erase, block %d\n",
2216 onenand_block(this, addr));
cd5f6346
KP
2217 instr->state = MTD_ERASE_FAILED;
2218 instr->fail_addr = addr;
2219 goto erase_exit;
2220 }
2221
2222 len -= block_size;
2223 addr += block_size;
5988af23
RH
2224
2225 if (addr == region_end) {
2226 if (!len)
2227 break;
2228 region++;
2229
2230 block_size = region->erasesize;
2231 region_end = region->offset + region->erasesize * region->numblocks;
2232
2233 if (len & (block_size - 1)) {
2234 /* FIXME: This should be handled at MTD partitioning level. */
2235 printk(KERN_ERR "onenand_erase: Unaligned address\n");
2236 goto erase_exit;
2237 }
2238 }
2239
cd5f6346
KP
2240 }
2241
2242 instr->state = MTD_ERASE_DONE;
2243
2244erase_exit:
2245
2246 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
cd5f6346
KP
2247
2248 /* Deselect and wake up anyone waiting on the device */
2249 onenand_release_device(mtd);
2250
3cd3a86b
AH
2251 /* Do call back function */
2252 if (!ret)
2253 mtd_erase_callback(instr);
2254
cd5f6346
KP
2255 return ret;
2256}
2257
2258/**
2259 * onenand_sync - [MTD Interface] sync
2260 * @param mtd MTD device structure
2261 *
2262 * Sync is actually a wait for chip ready function
2263 */
2264static void onenand_sync(struct mtd_info *mtd)
2265{
2266 DEBUG(MTD_DEBUG_LEVEL3, "onenand_sync: called\n");
2267
2268 /* Grab the lock and see if the device is available */
2269 onenand_get_device(mtd, FL_SYNCING);
2270
2271 /* Release it and go back */
2272 onenand_release_device(mtd);
2273}
2274
2275/**
2276 * onenand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad
2277 * @param mtd MTD device structure
2278 * @param ofs offset relative to mtd start
cdc00130
KP
2279 *
2280 * Check whether the block is bad
cd5f6346
KP
2281 */
2282static int onenand_block_isbad(struct mtd_info *mtd, loff_t ofs)
2283{
49dc08ee
AB
2284 int ret;
2285
cdc00130
KP
2286 /* Check for invalid offset */
2287 if (ofs > mtd->size)
2288 return -EINVAL;
2289
49dc08ee
AB
2290 onenand_get_device(mtd, FL_READING);
2291 ret = onenand_block_isbad_nolock(mtd, ofs, 0);
2292 onenand_release_device(mtd);
2293 return ret;
cdc00130
KP
2294}
2295
2296/**
2297 * onenand_default_block_markbad - [DEFAULT] mark a block bad
2298 * @param mtd MTD device structure
2299 * @param ofs offset from device start
2300 *
2301 * This is the default implementation, which can be overridden by
2302 * a hardware specific driver.
2303 */
2304static int onenand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
2305{
2306 struct onenand_chip *this = mtd->priv;
2307 struct bbm_info *bbm = this->bbm;
2308 u_char buf[2] = {0, 0};
12f77c9e
KP
2309 struct mtd_oob_ops ops = {
2310 .mode = MTD_OOB_PLACE,
2311 .ooblen = 2,
2312 .oobbuf = buf,
2313 .ooboffs = 0,
2314 };
cdc00130
KP
2315 int block;
2316
2317 /* Get block number */
5988af23 2318 block = onenand_block(this, ofs);
cdc00130
KP
2319 if (bbm->bbt)
2320 bbm->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
2321
2322 /* We write two bytes, so we dont have to mess with 16 bit access */
2323 ofs += mtd->oobsize + (bbm->badblockpos & ~0x01);
5988af23
RH
2324 /* FIXME : What to do when marking SLC block in partition
2325 * with MLC erasesize? For now, it is not advisable to
2326 * create partitions containing both SLC and MLC regions.
2327 */
2328 return onenand_write_oob_nolock(mtd, ofs, &ops);
cd5f6346
KP
2329}
2330
2331/**
2332 * onenand_block_markbad - [MTD Interface] Mark the block at the given offset as bad
2333 * @param mtd MTD device structure
2334 * @param ofs offset relative to mtd start
cdc00130
KP
2335 *
2336 * Mark the block as bad
cd5f6346
KP
2337 */
2338static int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2339{
cdc00130
KP
2340 struct onenand_chip *this = mtd->priv;
2341 int ret;
2342
2343 ret = onenand_block_isbad(mtd, ofs);
2344 if (ret) {
2345 /* If it was bad already, return success and do nothing */
2346 if (ret > 0)
2347 return 0;
2348 return ret;
2349 }
2350
49dc08ee
AB
2351 onenand_get_device(mtd, FL_WRITING);
2352 ret = this->block_markbad(mtd, ofs);
2353 onenand_release_device(mtd);
2354 return ret;
cd5f6346
KP
2355}
2356
2357/**
08f782b6 2358 * onenand_do_lock_cmd - [OneNAND Interface] Lock or unlock block(s)
cd5f6346
KP
2359 * @param mtd MTD device structure
2360 * @param ofs offset relative to mtd start
08f782b6 2361 * @param len number of bytes to lock or unlock
e3da8067 2362 * @param cmd lock or unlock command
cd5f6346 2363 *
08f782b6 2364 * Lock or unlock one or more blocks
cd5f6346 2365 */
08f782b6 2366static int onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs, size_t len, int cmd)
cd5f6346
KP
2367{
2368 struct onenand_chip *this = mtd->priv;
2369 int start, end, block, value, status;
08f782b6 2370 int wp_status_mask;
cd5f6346 2371
5988af23
RH
2372 start = onenand_block(this, ofs);
2373 end = onenand_block(this, ofs + len) - 1;
cd5f6346 2374
08f782b6
KP
2375 if (cmd == ONENAND_CMD_LOCK)
2376 wp_status_mask = ONENAND_WP_LS;
2377 else
2378 wp_status_mask = ONENAND_WP_US;
2379
cd5f6346 2380 /* Continuous lock scheme */
28b79ff9 2381 if (this->options & ONENAND_HAS_CONT_LOCK) {
cd5f6346
KP
2382 /* Set start block address */
2383 this->write_word(start, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
2384 /* Set end block address */
5988af23 2385 this->write_word(end, this->base + ONENAND_REG_END_BLOCK_ADDRESS);
08f782b6
KP
2386 /* Write lock command */
2387 this->command(mtd, cmd, 0, 0);
cd5f6346
KP
2388
2389 /* There's no return value */
08f782b6 2390 this->wait(mtd, FL_LOCKING);
cd5f6346
KP
2391
2392 /* Sanity check */
2393 while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
2394 & ONENAND_CTRL_ONGO)
2395 continue;
2396
2397 /* Check lock status */
2398 status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
08f782b6 2399 if (!(status & wp_status_mask))
cd5f6346
KP
2400 printk(KERN_ERR "wp status = 0x%x\n", status);
2401
2402 return 0;
2403 }
2404
2405 /* Block lock scheme */
5988af23 2406 for (block = start; block < end + 1; block++) {
20ba89a3
KP
2407 /* Set block address */
2408 value = onenand_block_address(this, block);
2409 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1);
2410 /* Select DataRAM for DDP */
2411 value = onenand_bufferram_address(this, block);
2412 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
cd5f6346
KP
2413 /* Set start block address */
2414 this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
08f782b6
KP
2415 /* Write lock command */
2416 this->command(mtd, cmd, 0, 0);
cd5f6346
KP
2417
2418 /* There's no return value */
08f782b6 2419 this->wait(mtd, FL_LOCKING);
cd5f6346
KP
2420
2421 /* Sanity check */
2422 while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
2423 & ONENAND_CTRL_ONGO)
2424 continue;
2425
cd5f6346
KP
2426 /* Check lock status */
2427 status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
08f782b6 2428 if (!(status & wp_status_mask))
cd5f6346
KP
2429 printk(KERN_ERR "block = %d, wp status = 0x%x\n", block, status);
2430 }
d5c5e78a 2431
cd5f6346
KP
2432 return 0;
2433}
2434
08f782b6
KP
2435/**
2436 * onenand_lock - [MTD Interface] Lock block(s)
2437 * @param mtd MTD device structure
2438 * @param ofs offset relative to mtd start
2439 * @param len number of bytes to unlock
2440 *
2441 * Lock one or more blocks
2442 */
69423d99 2443static int onenand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
08f782b6 2444{
34627f0e
AH
2445 int ret;
2446
2447 onenand_get_device(mtd, FL_LOCKING);
2448 ret = onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_LOCK);
2449 onenand_release_device(mtd);
2450 return ret;
08f782b6
KP
2451}
2452
08f782b6
KP
2453/**
2454 * onenand_unlock - [MTD Interface] Unlock block(s)
2455 * @param mtd MTD device structure
2456 * @param ofs offset relative to mtd start
2457 * @param len number of bytes to unlock
2458 *
2459 * Unlock one or more blocks
2460 */
69423d99 2461static int onenand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
08f782b6 2462{
34627f0e
AH
2463 int ret;
2464
2465 onenand_get_device(mtd, FL_LOCKING);
2466 ret = onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK);
2467 onenand_release_device(mtd);
2468 return ret;
08f782b6
KP
2469}
2470
28b79ff9
KP
2471/**
2472 * onenand_check_lock_status - [OneNAND Interface] Check lock status
2473 * @param this onenand chip data structure
2474 *
2475 * Check lock status
2476 */
66a10506 2477static int onenand_check_lock_status(struct onenand_chip *this)
28b79ff9
KP
2478{
2479 unsigned int value, block, status;
2480 unsigned int end;
2481
2482 end = this->chipsize >> this->erase_shift;
2483 for (block = 0; block < end; block++) {
2484 /* Set block address */
2485 value = onenand_block_address(this, block);
2486 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1);
2487 /* Select DataRAM for DDP */
2488 value = onenand_bufferram_address(this, block);
2489 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
2490 /* Set start block address */
2491 this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
2492
2493 /* Check lock status */
2494 status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
66a10506 2495 if (!(status & ONENAND_WP_US)) {
28b79ff9 2496 printk(KERN_ERR "block = %d, wp status = 0x%x\n", block, status);
66a10506
KP
2497 return 0;
2498 }
28b79ff9 2499 }
66a10506
KP
2500
2501 return 1;
28b79ff9
KP
2502}
2503
2504/**
2505 * onenand_unlock_all - [OneNAND Interface] unlock all blocks
2506 * @param mtd MTD device structure
2507 *
2508 * Unlock all blocks
2509 */
66a10506 2510static void onenand_unlock_all(struct mtd_info *mtd)
28b79ff9
KP
2511{
2512 struct onenand_chip *this = mtd->priv;
66a10506 2513 loff_t ofs = 0;
5988af23 2514 loff_t len = mtd->size;
28b79ff9
KP
2515
2516 if (this->options & ONENAND_HAS_UNLOCK_ALL) {
10b7a2bd
KP
2517 /* Set start block address */
2518 this->write_word(0, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
28b79ff9
KP
2519 /* Write unlock command */
2520 this->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0, 0);
2521
2522 /* There's no return value */
08f782b6 2523 this->wait(mtd, FL_LOCKING);
28b79ff9
KP
2524
2525 /* Sanity check */
2526 while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
2527 & ONENAND_CTRL_ONGO)
2528 continue;
2529
31bb999e
KP
2530 /* Don't check lock status */
2531 if (this->options & ONENAND_SKIP_UNLOCK_CHECK)
2532 return;
2533
66a10506
KP
2534 /* Check lock status */
2535 if (onenand_check_lock_status(this))
2536 return;
2537
28b79ff9 2538 /* Workaround for all block unlock in DDP */
5988af23 2539 if (ONENAND_IS_DDP(this) && !FLEXONENAND(this)) {
66a10506
KP
2540 /* All blocks on another chip */
2541 ofs = this->chipsize >> 1;
2542 len = this->chipsize >> 1;
28b79ff9 2543 }
28b79ff9
KP
2544 }
2545
66a10506 2546 onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK);
28b79ff9
KP
2547}
2548
493c6460
KP
2549#ifdef CONFIG_MTD_ONENAND_OTP
2550
2551/* Interal OTP operation */
2552typedef int (*otp_op_t)(struct mtd_info *mtd, loff_t form, size_t len,
2553 size_t *retlen, u_char *buf);
2554
2555/**
2556 * do_otp_read - [DEFAULT] Read OTP block area
2557 * @param mtd MTD device structure
2558 * @param from The offset to read
2559 * @param len number of bytes to read
2560 * @param retlen pointer to variable to store the number of readbytes
2561 * @param buf the databuffer to put/get data
2562 *
2563 * Read OTP block area.
2564 */
2565static int do_otp_read(struct mtd_info *mtd, loff_t from, size_t len,
2566 size_t *retlen, u_char *buf)
2567{
2568 struct onenand_chip *this = mtd->priv;
49dc08ee
AB
2569 struct mtd_oob_ops ops = {
2570 .len = len,
2571 .ooblen = 0,
2572 .datbuf = buf,
2573 .oobbuf = NULL,
2574 };
493c6460
KP
2575 int ret;
2576
2577 /* Enter OTP access mode */
2578 this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0);
2579 this->wait(mtd, FL_OTPING);
2580
5988af23
RH
2581 ret = ONENAND_IS_MLC(this) ?
2582 onenand_mlc_read_ops_nolock(mtd, from, &ops) :
2583 onenand_read_ops_nolock(mtd, from, &ops);
493c6460
KP
2584
2585 /* Exit OTP access mode */
2586 this->command(mtd, ONENAND_CMD_RESET, 0, 0);
2587 this->wait(mtd, FL_RESETING);
2588
2589 return ret;
2590}
2591
2592/**
2593 * do_otp_write - [DEFAULT] Write OTP block area
2594 * @param mtd MTD device structure
49dc08ee 2595 * @param to The offset to write
493c6460
KP
2596 * @param len number of bytes to write
2597 * @param retlen pointer to variable to store the number of write bytes
2598 * @param buf the databuffer to put/get data
2599 *
2600 * Write OTP block area.
2601 */
49dc08ee 2602static int do_otp_write(struct mtd_info *mtd, loff_t to, size_t len,
493c6460
KP
2603 size_t *retlen, u_char *buf)
2604{
2605 struct onenand_chip *this = mtd->priv;
2606 unsigned char *pbuf = buf;
2607 int ret;
49dc08ee 2608 struct mtd_oob_ops ops;
493c6460
KP
2609
2610 /* Force buffer page aligned */
28318776 2611 if (len < mtd->writesize) {
493c6460 2612 memcpy(this->page_buf, buf, len);
28318776 2613 memset(this->page_buf + len, 0xff, mtd->writesize - len);
493c6460 2614 pbuf = this->page_buf;
28318776 2615 len = mtd->writesize;
493c6460
KP
2616 }
2617
2618 /* Enter OTP access mode */
2619 this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0);
2620 this->wait(mtd, FL_OTPING);
2621
49dc08ee
AB
2622 ops.len = len;
2623 ops.ooblen = 0;
1437085c 2624 ops.datbuf = pbuf;
49dc08ee
AB
2625 ops.oobbuf = NULL;
2626 ret = onenand_write_ops_nolock(mtd, to, &ops);
2627 *retlen = ops.retlen;
493c6460
KP
2628
2629 /* Exit OTP access mode */
2630 this->command(mtd, ONENAND_CMD_RESET, 0, 0);
2631 this->wait(mtd, FL_RESETING);
2632
2633 return ret;
2634}
2635
2636/**
2637 * do_otp_lock - [DEFAULT] Lock OTP block area
2638 * @param mtd MTD device structure
2639 * @param from The offset to lock
2640 * @param len number of bytes to lock
2641 * @param retlen pointer to variable to store the number of lock bytes
2642 * @param buf the databuffer to put/get data
2643 *
2644 * Lock OTP block area.
2645 */
2646static int do_otp_lock(struct mtd_info *mtd, loff_t from, size_t len,
2647 size_t *retlen, u_char *buf)
2648{
2649 struct onenand_chip *this = mtd->priv;
5988af23 2650 struct mtd_oob_ops ops;
493c6460
KP
2651 int ret;
2652
2653 /* Enter OTP access mode */
2654 this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0);
2655 this->wait(mtd, FL_OTPING);
2656
5988af23
RH
2657 if (FLEXONENAND(this)) {
2658 /*
2659 * For Flex-OneNAND, we write lock mark to 1st word of sector 4 of
2660 * main area of page 49.
2661 */
2662 ops.len = mtd->writesize;
2663 ops.ooblen = 0;
2664 ops.datbuf = buf;
2665 ops.oobbuf = NULL;
2666 ret = onenand_write_ops_nolock(mtd, mtd->writesize * 49, &ops);
2667 *retlen = ops.retlen;
2668 } else {
2669 ops.mode = MTD_OOB_PLACE;
2670 ops.ooblen = len;
2671 ops.oobbuf = buf;
2672 ops.ooboffs = 0;
2673 ret = onenand_write_oob_nolock(mtd, from, &ops);
2674 *retlen = ops.oobretlen;
2675 }
493c6460
KP
2676
2677 /* Exit OTP access mode */
2678 this->command(mtd, ONENAND_CMD_RESET, 0, 0);
2679 this->wait(mtd, FL_RESETING);
2680
2681 return ret;
2682}
2683
2684/**
2685 * onenand_otp_walk - [DEFAULT] Handle OTP operation
2686 * @param mtd MTD device structure
2687 * @param from The offset to read/write
2688 * @param len number of bytes to read/write
2689 * @param retlen pointer to variable to store the number of read bytes
2690 * @param buf the databuffer to put/get data
2691 * @param action do given action
2692 * @param mode specify user and factory
2693 *
2694 * Handle OTP operation.
2695 */
2696static int onenand_otp_walk(struct mtd_info *mtd, loff_t from, size_t len,
2697 size_t *retlen, u_char *buf,
2698 otp_op_t action, int mode)
2699{
2700 struct onenand_chip *this = mtd->priv;
2701 int otp_pages;
2702 int density;
2703 int ret = 0;
2704
2705 *retlen = 0;
2706
e71f04fc 2707 density = onenand_get_density(this->device_id);
493c6460
KP
2708 if (density < ONENAND_DEVICE_DENSITY_512Mb)
2709 otp_pages = 20;
2710 else
2711 otp_pages = 10;
2712
2713 if (mode == MTD_OTP_FACTORY) {
28318776 2714 from += mtd->writesize * otp_pages;
493c6460
KP
2715 otp_pages = 64 - otp_pages;
2716 }
2717
2718 /* Check User/Factory boundary */
28318776 2719 if (((mtd->writesize * otp_pages) - (from + len)) < 0)
493c6460
KP
2720 return 0;
2721
49dc08ee 2722 onenand_get_device(mtd, FL_OTPING);
493c6460
KP
2723 while (len > 0 && otp_pages > 0) {
2724 if (!action) { /* OTP Info functions */
2725 struct otp_info *otpinfo;
2726
2727 len -= sizeof(struct otp_info);
49dc08ee
AB
2728 if (len <= 0) {
2729 ret = -ENOSPC;
2730 break;
2731 }
493c6460
KP
2732
2733 otpinfo = (struct otp_info *) buf;
2734 otpinfo->start = from;
28318776 2735 otpinfo->length = mtd->writesize;
493c6460
KP
2736 otpinfo->locked = 0;
2737
28318776 2738 from += mtd->writesize;
493c6460
KP
2739 buf += sizeof(struct otp_info);
2740 *retlen += sizeof(struct otp_info);
2741 } else {
2742 size_t tmp_retlen;
2743 int size = len;
2744
2745 ret = action(mtd, from, len, &tmp_retlen, buf);
2746
2747 buf += size;
2748 len -= size;
2749 *retlen += size;
2750
49dc08ee
AB
2751 if (ret)
2752 break;
493c6460
KP
2753 }
2754 otp_pages--;
2755 }
49dc08ee 2756 onenand_release_device(mtd);
493c6460 2757
49dc08ee 2758 return ret;
493c6460
KP
2759}
2760
2761/**
2762 * onenand_get_fact_prot_info - [MTD Interface] Read factory OTP info
2763 * @param mtd MTD device structure
2764 * @param buf the databuffer to put/get data
2765 * @param len number of bytes to read
2766 *
2767 * Read factory OTP info.
2768 */
2769static int onenand_get_fact_prot_info(struct mtd_info *mtd,
2770 struct otp_info *buf, size_t len)
2771{
2772 size_t retlen;
2773 int ret;
2774
2775 ret = onenand_otp_walk(mtd, 0, len, &retlen, (u_char *) buf, NULL, MTD_OTP_FACTORY);
2776
2777 return ret ? : retlen;
2778}
2779
2780/**
2781 * onenand_read_fact_prot_reg - [MTD Interface] Read factory OTP area
2782 * @param mtd MTD device structure
2783 * @param from The offset to read
2784 * @param len number of bytes to read
2785 * @param retlen pointer to variable to store the number of read bytes
2786 * @param buf the databuffer to put/get data
2787 *
2788 * Read factory OTP area.
2789 */
2790static int onenand_read_fact_prot_reg(struct mtd_info *mtd, loff_t from,
2791 size_t len, size_t *retlen, u_char *buf)
2792{
2793 return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_read, MTD_OTP_FACTORY);
2794}
2795
2796/**
2797 * onenand_get_user_prot_info - [MTD Interface] Read user OTP info
2798 * @param mtd MTD device structure
2799 * @param buf the databuffer to put/get data
2800 * @param len number of bytes to read
2801 *
2802 * Read user OTP info.
2803 */
2804static int onenand_get_user_prot_info(struct mtd_info *mtd,
2805 struct otp_info *buf, size_t len)
2806{
2807 size_t retlen;
2808 int ret;
2809
2810 ret = onenand_otp_walk(mtd, 0, len, &retlen, (u_char *) buf, NULL, MTD_OTP_USER);
2811
2812 return ret ? : retlen;
2813}
2814
2815/**
2816 * onenand_read_user_prot_reg - [MTD Interface] Read user OTP area
2817 * @param mtd MTD device structure
2818 * @param from The offset to read
2819 * @param len number of bytes to read
2820 * @param retlen pointer to variable to store the number of read bytes
2821 * @param buf the databuffer to put/get data
2822 *
2823 * Read user OTP area.
2824 */
2825static int onenand_read_user_prot_reg(struct mtd_info *mtd, loff_t from,
2826 size_t len, size_t *retlen, u_char *buf)
2827{
2828 return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_read, MTD_OTP_USER);
2829}
2830
2831/**
2832 * onenand_write_user_prot_reg - [MTD Interface] Write user OTP area
2833 * @param mtd MTD device structure
2834 * @param from The offset to write
2835 * @param len number of bytes to write
2836 * @param retlen pointer to variable to store the number of write bytes
2837 * @param buf the databuffer to put/get data
2838 *
2839 * Write user OTP area.
2840 */
2841static int onenand_write_user_prot_reg(struct mtd_info *mtd, loff_t from,
2842 size_t len, size_t *retlen, u_char *buf)
2843{
2844 return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_write, MTD_OTP_USER);
2845}
2846
2847/**
2848 * onenand_lock_user_prot_reg - [MTD Interface] Lock user OTP area
2849 * @param mtd MTD device structure
2850 * @param from The offset to lock
2851 * @param len number of bytes to unlock
2852 *
2853 * Write lock mark on spare area in page 0 in OTP block
2854 */
2855static int onenand_lock_user_prot_reg(struct mtd_info *mtd, loff_t from,
2856 size_t len)
2857{
69d79186 2858 struct onenand_chip *this = mtd->priv;
5988af23 2859 u_char *buf = FLEXONENAND(this) ? this->page_buf : this->oob_buf;
493c6460
KP
2860 size_t retlen;
2861 int ret;
2862
5988af23
RH
2863 memset(buf, 0xff, FLEXONENAND(this) ? this->writesize
2864 : mtd->oobsize);
493c6460
KP
2865 /*
2866 * Note: OTP lock operation
2867 * OTP block : 0xXXFC
2868 * 1st block : 0xXXF3 (If chip support)
2869 * Both : 0xXXF0 (If chip support)
2870 */
5988af23
RH
2871 if (FLEXONENAND(this))
2872 buf[FLEXONENAND_OTP_LOCK_OFFSET] = 0xFC;
2873 else
2874 buf[ONENAND_OTP_LOCK_OFFSET] = 0xFC;
493c6460
KP
2875
2876 /*
2877 * Write lock mark to 8th word of sector0 of page0 of the spare0.
2878 * We write 16 bytes spare area instead of 2 bytes.
5988af23
RH
2879 * For Flex-OneNAND, we write lock mark to 1st word of sector 4 of
2880 * main area of page 49.
493c6460 2881 */
5988af23 2882
493c6460 2883 from = 0;
5988af23 2884 len = FLEXONENAND(this) ? mtd->writesize : 16;
493c6460 2885
5988af23 2886 ret = onenand_otp_walk(mtd, from, len, &retlen, buf, do_otp_lock, MTD_OTP_USER);
493c6460
KP
2887
2888 return ret ? : retlen;
2889}
2890#endif /* CONFIG_MTD_ONENAND_OTP */
2891
28b79ff9 2892/**
75384b0d 2893 * onenand_check_features - Check and set OneNAND features
28b79ff9
KP
2894 * @param mtd MTD data structure
2895 *
75384b0d
KP
2896 * Check and set OneNAND features
2897 * - lock scheme
ee9745fc 2898 * - two plane
28b79ff9 2899 */
75384b0d 2900static void onenand_check_features(struct mtd_info *mtd)
28b79ff9
KP
2901{
2902 struct onenand_chip *this = mtd->priv;
2903 unsigned int density, process;
2904
2905 /* Lock scheme depends on density and process */
e71f04fc 2906 density = onenand_get_density(this->device_id);
28b79ff9
KP
2907 process = this->version_id >> ONENAND_VERSION_PROCESS_SHIFT;
2908
2909 /* Lock scheme */
ee9745fc
KP
2910 switch (density) {
2911 case ONENAND_DEVICE_DENSITY_4Gb:
2912 this->options |= ONENAND_HAS_2PLANE;
2913
2914 case ONENAND_DEVICE_DENSITY_2Gb:
2915 /* 2Gb DDP don't have 2 plane */
2916 if (!ONENAND_IS_DDP(this))
2917 this->options |= ONENAND_HAS_2PLANE;
2918 this->options |= ONENAND_HAS_UNLOCK_ALL;
2919
2920 case ONENAND_DEVICE_DENSITY_1Gb:
28b79ff9 2921 /* A-Die has all block unlock */
ee9745fc 2922 if (process)
28b79ff9 2923 this->options |= ONENAND_HAS_UNLOCK_ALL;
ee9745fc
KP
2924 break;
2925
2926 default:
2927 /* Some OneNAND has continuous lock scheme */
2928 if (!process)
28b79ff9 2929 this->options |= ONENAND_HAS_CONT_LOCK;
ee9745fc 2930 break;
28b79ff9 2931 }
ee9745fc 2932
5988af23
RH
2933 if (ONENAND_IS_MLC(this))
2934 this->options &= ~ONENAND_HAS_2PLANE;
2935
2936 if (FLEXONENAND(this)) {
2937 this->options &= ~ONENAND_HAS_CONT_LOCK;
2938 this->options |= ONENAND_HAS_UNLOCK_ALL;
2939 }
2940
ee9745fc
KP
2941 if (this->options & ONENAND_HAS_CONT_LOCK)
2942 printk(KERN_DEBUG "Lock scheme is Continuous Lock\n");
2943 if (this->options & ONENAND_HAS_UNLOCK_ALL)
2944 printk(KERN_DEBUG "Chip support all block unlock\n");
2945 if (this->options & ONENAND_HAS_2PLANE)
2946 printk(KERN_DEBUG "Chip has 2 plane\n");
28b79ff9
KP
2947}
2948
cd5f6346 2949/**
e3da8067 2950 * onenand_print_device_info - Print device & version ID
cd5f6346 2951 * @param device device ID
e3da8067 2952 * @param version version ID
cd5f6346 2953 *
e3da8067 2954 * Print device & version ID
cd5f6346 2955 */
28b79ff9 2956static void onenand_print_device_info(int device, int version)
cd5f6346 2957{
5988af23 2958 int vcc, demuxed, ddp, density, flexonenand;
cd5f6346
KP
2959
2960 vcc = device & ONENAND_DEVICE_VCC_MASK;
2961 demuxed = device & ONENAND_DEVICE_IS_DEMUX;
2962 ddp = device & ONENAND_DEVICE_IS_DDP;
e71f04fc 2963 density = onenand_get_density(device);
5988af23
RH
2964 flexonenand = device & DEVICE_IS_FLEXONENAND;
2965 printk(KERN_INFO "%s%sOneNAND%s %dMB %sV 16-bit (0x%02x)\n",
2966 demuxed ? "" : "Muxed ",
2967 flexonenand ? "Flex-" : "",
cd5f6346
KP
2968 ddp ? "(DDP)" : "",
2969 (16 << density),
2970 vcc ? "2.65/3.3" : "1.8",
2971 device);
49dc08ee 2972 printk(KERN_INFO "OneNAND version = 0x%04x\n", version);
cd5f6346
KP
2973}
2974
2975static const struct onenand_manufacturers onenand_manuf_ids[] = {
2976 {ONENAND_MFR_SAMSUNG, "Samsung"},
ee8f3768 2977 {ONENAND_MFR_NUMONYX, "Numonyx"},
cd5f6346
KP
2978};
2979
2980/**
2981 * onenand_check_maf - Check manufacturer ID
2982 * @param manuf manufacturer ID
2983 *
2984 * Check manufacturer ID
2985 */
2986static int onenand_check_maf(int manuf)
2987{
37b1cc39
KP
2988 int size = ARRAY_SIZE(onenand_manuf_ids);
2989 char *name;
cd5f6346
KP
2990 int i;
2991
37b1cc39 2992 for (i = 0; i < size; i++)
cd5f6346
KP
2993 if (manuf == onenand_manuf_ids[i].id)
2994 break;
cd5f6346 2995
37b1cc39
KP
2996 if (i < size)
2997 name = onenand_manuf_ids[i].name;
2998 else
2999 name = "Unknown";
3000
3001 printk(KERN_DEBUG "OneNAND Manufacturer: %s (0x%0x)\n", name, manuf);
cd5f6346 3002
37b1cc39 3003 return (i == size);
cd5f6346
KP
3004}
3005
5988af23
RH
3006/**
3007* flexonenand_get_boundary - Reads the SLC boundary
3008* @param onenand_info - onenand info structure
3009**/
3010static int flexonenand_get_boundary(struct mtd_info *mtd)
3011{
3012 struct onenand_chip *this = mtd->priv;
3013 unsigned die, bdry;
3014 int ret, syscfg, locked;
3015
3016 /* Disable ECC */
3017 syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1);
3018 this->write_word((syscfg | 0x0100), this->base + ONENAND_REG_SYS_CFG1);
3019
3020 for (die = 0; die < this->dies; die++) {
3021 this->command(mtd, FLEXONENAND_CMD_PI_ACCESS, die, 0);
3022 this->wait(mtd, FL_SYNCING);
3023
3024 this->command(mtd, FLEXONENAND_CMD_READ_PI, die, 0);
3025 ret = this->wait(mtd, FL_READING);
3026
3027 bdry = this->read_word(this->base + ONENAND_DATARAM);
3028 if ((bdry >> FLEXONENAND_PI_UNLOCK_SHIFT) == 3)
3029 locked = 0;
3030 else
3031 locked = 1;
3032 this->boundary[die] = bdry & FLEXONENAND_PI_MASK;
3033
3034 this->command(mtd, ONENAND_CMD_RESET, 0, 0);
3035 ret = this->wait(mtd, FL_RESETING);
3036
3037 printk(KERN_INFO "Die %d boundary: %d%s\n", die,
3038 this->boundary[die], locked ? "(Locked)" : "(Unlocked)");
3039 }
3040
3041 /* Enable ECC */
3042 this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);
3043 return 0;
3044}
3045
3046/**
3047 * flexonenand_get_size - Fill up fields in onenand_chip and mtd_info
3048 * boundary[], diesize[], mtd->size, mtd->erasesize
3049 * @param mtd - MTD device structure
3050 */
3051static void flexonenand_get_size(struct mtd_info *mtd)
3052{
3053 struct onenand_chip *this = mtd->priv;
3054 int die, i, eraseshift, density;
3055 int blksperdie, maxbdry;
3056 loff_t ofs;
3057
3058 density = onenand_get_density(this->device_id);
3059 blksperdie = ((loff_t)(16 << density) << 20) >> (this->erase_shift);
3060 blksperdie >>= ONENAND_IS_DDP(this) ? 1 : 0;
3061 maxbdry = blksperdie - 1;
3062 eraseshift = this->erase_shift - 1;
3063
3064 mtd->numeraseregions = this->dies << 1;
3065
3066 /* This fills up the device boundary */
3067 flexonenand_get_boundary(mtd);
3068 die = ofs = 0;
3069 i = -1;
3070 for (; die < this->dies; die++) {
3071 if (!die || this->boundary[die-1] != maxbdry) {
3072 i++;
3073 mtd->eraseregions[i].offset = ofs;
3074 mtd->eraseregions[i].erasesize = 1 << eraseshift;
3075 mtd->eraseregions[i].numblocks =
3076 this->boundary[die] + 1;
3077 ofs += mtd->eraseregions[i].numblocks << eraseshift;
3078 eraseshift++;
3079 } else {
3080 mtd->numeraseregions -= 1;
3081 mtd->eraseregions[i].numblocks +=
3082 this->boundary[die] + 1;
3083 ofs += (this->boundary[die] + 1) << (eraseshift - 1);
3084 }
3085 if (this->boundary[die] != maxbdry) {
3086 i++;
3087 mtd->eraseregions[i].offset = ofs;
3088 mtd->eraseregions[i].erasesize = 1 << eraseshift;
3089 mtd->eraseregions[i].numblocks = maxbdry ^
3090 this->boundary[die];
3091 ofs += mtd->eraseregions[i].numblocks << eraseshift;
3092 eraseshift--;
3093 } else
3094 mtd->numeraseregions -= 1;
3095 }
3096
3097 /* Expose MLC erase size except when all blocks are SLC */
3098 mtd->erasesize = 1 << this->erase_shift;
3099 if (mtd->numeraseregions == 1)
3100 mtd->erasesize >>= 1;
3101
3102 printk(KERN_INFO "Device has %d eraseregions\n", mtd->numeraseregions);
3103 for (i = 0; i < mtd->numeraseregions; i++)
3104 printk(KERN_INFO "[offset: 0x%08x, erasesize: 0x%05x,"
3105 " numblocks: %04u]\n",
3106 (unsigned int) mtd->eraseregions[i].offset,
3107 mtd->eraseregions[i].erasesize,
3108 mtd->eraseregions[i].numblocks);
3109
3110 for (die = 0, mtd->size = 0; die < this->dies; die++) {
3111 this->diesize[die] = (loff_t)blksperdie << this->erase_shift;
3112 this->diesize[die] -= (loff_t)(this->boundary[die] + 1)
3113 << (this->erase_shift - 1);
3114 mtd->size += this->diesize[die];
3115 }
3116}
3117
3118/**
3119 * flexonenand_check_blocks_erased - Check if blocks are erased
3120 * @param mtd_info - mtd info structure
3121 * @param start - first erase block to check
3122 * @param end - last erase block to check
3123 *
3124 * Converting an unerased block from MLC to SLC
3125 * causes byte values to change. Since both data and its ECC
3126 * have changed, reads on the block give uncorrectable error.
3127 * This might lead to the block being detected as bad.
3128 *
3129 * Avoid this by ensuring that the block to be converted is
3130 * erased.
3131 */
3132static int flexonenand_check_blocks_erased(struct mtd_info *mtd, int start, int end)
3133{
3134 struct onenand_chip *this = mtd->priv;
3135 int i, ret;
3136 int block;
3137 struct mtd_oob_ops ops = {
3138 .mode = MTD_OOB_PLACE,
3139 .ooboffs = 0,
3140 .ooblen = mtd->oobsize,
3141 .datbuf = NULL,
3142 .oobbuf = this->oob_buf,
3143 };
3144 loff_t addr;
3145
3146 printk(KERN_DEBUG "Check blocks from %d to %d\n", start, end);
3147
3148 for (block = start; block <= end; block++) {
3149 addr = flexonenand_addr(this, block);
3150 if (onenand_block_isbad_nolock(mtd, addr, 0))
3151 continue;
3152
3153 /*
3154 * Since main area write results in ECC write to spare,
3155 * it is sufficient to check only ECC bytes for change.
3156 */
3157 ret = onenand_read_oob_nolock(mtd, addr, &ops);
3158 if (ret)
3159 return ret;
3160
3161 for (i = 0; i < mtd->oobsize; i++)
3162 if (this->oob_buf[i] != 0xff)
3163 break;
3164
3165 if (i != mtd->oobsize) {
3166 printk(KERN_WARNING "Block %d not erased.\n", block);
3167 return 1;
3168 }
3169 }
3170
3171 return 0;
3172}
3173
3174/**
3175 * flexonenand_set_boundary - Writes the SLC boundary
3176 * @param mtd - mtd info structure
3177 */
3178int flexonenand_set_boundary(struct mtd_info *mtd, int die,
3179 int boundary, int lock)
3180{
3181 struct onenand_chip *this = mtd->priv;
3182 int ret, density, blksperdie, old, new, thisboundary;
3183 loff_t addr;
3184
3185 /* Change only once for SDP Flex-OneNAND */
3186 if (die && (!ONENAND_IS_DDP(this)))
3187 return 0;
3188
3189 /* boundary value of -1 indicates no required change */
3190 if (boundary < 0 || boundary == this->boundary[die])
3191 return 0;
3192
3193 density = onenand_get_density(this->device_id);
3194 blksperdie = ((16 << density) << 20) >> this->erase_shift;
3195 blksperdie >>= ONENAND_IS_DDP(this) ? 1 : 0;
3196
3197 if (boundary >= blksperdie) {
3198 printk(KERN_ERR "flexonenand_set_boundary: Invalid boundary value. "
3199 "Boundary not changed.\n");
3200 return -EINVAL;
3201 }
3202
3203 /* Check if converting blocks are erased */
3204 old = this->boundary[die] + (die * this->density_mask);
3205 new = boundary + (die * this->density_mask);
3206 ret = flexonenand_check_blocks_erased(mtd, min(old, new) + 1, max(old, new));
3207 if (ret) {
3208 printk(KERN_ERR "flexonenand_set_boundary: Please erase blocks before boundary change\n");
3209 return ret;
3210 }
3211
3212 this->command(mtd, FLEXONENAND_CMD_PI_ACCESS, die, 0);
3213 this->wait(mtd, FL_SYNCING);
3214
3215 /* Check is boundary is locked */
3216 this->command(mtd, FLEXONENAND_CMD_READ_PI, die, 0);
3217 ret = this->wait(mtd, FL_READING);
3218
3219 thisboundary = this->read_word(this->base + ONENAND_DATARAM);
3220 if ((thisboundary >> FLEXONENAND_PI_UNLOCK_SHIFT) != 3) {
3221 printk(KERN_ERR "flexonenand_set_boundary: boundary locked\n");
3222 ret = 1;
3223 goto out;
3224 }
3225
3226 printk(KERN_INFO "flexonenand_set_boundary: Changing die %d boundary: %d%s\n",
3227 die, boundary, lock ? "(Locked)" : "(Unlocked)");
3228
3229 addr = die ? this->diesize[0] : 0;
3230
3231 boundary &= FLEXONENAND_PI_MASK;
3232 boundary |= lock ? 0 : (3 << FLEXONENAND_PI_UNLOCK_SHIFT);
3233
3234 this->command(mtd, ONENAND_CMD_ERASE, addr, 0);
3235 ret = this->wait(mtd, FL_ERASING);
3236 if (ret) {
3237 printk(KERN_ERR "flexonenand_set_boundary: Failed PI erase for Die %d\n", die);
3238 goto out;
3239 }
3240
3241 this->write_word(boundary, this->base + ONENAND_DATARAM);
3242 this->command(mtd, ONENAND_CMD_PROG, addr, 0);
3243 ret = this->wait(mtd, FL_WRITING);
3244 if (ret) {
3245 printk(KERN_ERR "flexonenand_set_boundary: Failed PI write for Die %d\n", die);
3246 goto out;
3247 }
3248
3249 this->command(mtd, FLEXONENAND_CMD_PI_UPDATE, die, 0);
3250 ret = this->wait(mtd, FL_WRITING);
3251out:
3252 this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_REG_COMMAND);
3253 this->wait(mtd, FL_RESETING);
3254 if (!ret)
3255 /* Recalculate device size on boundary change*/
3256 flexonenand_get_size(mtd);
3257
3258 return ret;
3259}
3260
3261/**
3262 * flexonenand_setup - capture Flex-OneNAND boundary and lock
3263 * values passed as kernel parameters
3264 * @param s kernel parameter string
3265 */
3266static int flexonenand_setup(char *s)
3267{
3268 int ints[5], i;
3269
3270 s = get_options(s, 5, ints);
3271
3272 for (i = 0; i < ints[0]; i++)
3273 flex_bdry[i] = ints[i + 1];
3274
3275 return 1;
3276}
3277
3278__setup("onenand.bdry=", flexonenand_setup);
3279
cd5f6346
KP
3280/**
3281 * onenand_probe - [OneNAND Interface] Probe the OneNAND device
3282 * @param mtd MTD device structure
3283 *
3284 * OneNAND detection method:
59c51591 3285 * Compare the values from command with ones from register
cd5f6346
KP
3286 */
3287static int onenand_probe(struct mtd_info *mtd)
3288{
3289 struct onenand_chip *this = mtd->priv;
28b79ff9 3290 int bram_maf_id, bram_dev_id, maf_id, dev_id, ver_id;
cd5f6346 3291 int density;
47e777e0
KP
3292 int syscfg;
3293
3294 /* Save system configuration 1 */
3295 syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1);
3296 /* Clear Sync. Burst Read mode to read BootRAM */
ee8f3768 3297 this->write_word((syscfg & ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE), this->base + ONENAND_REG_SYS_CFG1);
cd5f6346
KP
3298
3299 /* Send the command for reading device ID from BootRAM */
3300 this->write_word(ONENAND_CMD_READID, this->base + ONENAND_BOOTRAM);
3301
3302 /* Read manufacturer and device IDs from BootRAM */
3303 bram_maf_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x0);
3304 bram_dev_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x2);
3305
47e777e0
KP
3306 /* Reset OneNAND to read default register values */
3307 this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM);
3308 /* Wait reset */
3309 this->wait(mtd, FL_RESETING);
3310
3311 /* Restore system configuration 1 */
3312 this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);
3313
cd5f6346
KP
3314 /* Check manufacturer ID */
3315 if (onenand_check_maf(bram_maf_id))
3316 return -ENXIO;
3317
cd5f6346
KP
3318 /* Read manufacturer and device IDs from Register */
3319 maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID);
3320 dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID);
f4f91ac3 3321 ver_id = this->read_word(this->base + ONENAND_REG_VERSION_ID);
5988af23 3322 this->technology = this->read_word(this->base + ONENAND_REG_TECHNOLOGY);
cd5f6346
KP
3323
3324 /* Check OneNAND device */
3325 if (maf_id != bram_maf_id || dev_id != bram_dev_id)
3326 return -ENXIO;
3327
3328 /* Flash device information */
28b79ff9 3329 onenand_print_device_info(dev_id, ver_id);
cd5f6346 3330 this->device_id = dev_id;
28b79ff9 3331 this->version_id = ver_id;
cd5f6346 3332
e71f04fc 3333 density = onenand_get_density(dev_id);
5988af23
RH
3334 if (FLEXONENAND(this)) {
3335 this->dies = ONENAND_IS_DDP(this) ? 2 : 1;
3336 /* Maximum possible erase regions */
3337 mtd->numeraseregions = this->dies << 1;
3338 mtd->eraseregions = kzalloc(sizeof(struct mtd_erase_region_info)
3339 * (this->dies << 1), GFP_KERNEL);
3340 if (!mtd->eraseregions)
3341 return -ENOMEM;
3342 }
3343
3344 /*
3345 * For Flex-OneNAND, chipsize represents maximum possible device size.
3346 * mtd->size represents the actual device size.
3347 */
cd5f6346
KP
3348 this->chipsize = (16 << density) << 20;
3349
3350 /* OneNAND page size & block size */
3351 /* The data buffer size is equal to page size */
28318776 3352 mtd->writesize = this->read_word(this->base + ONENAND_REG_DATA_BUFFER_SIZE);
5988af23
RH
3353 /* We use the full BufferRAM */
3354 if (ONENAND_IS_MLC(this))
3355 mtd->writesize <<= 1;
3356
28318776 3357 mtd->oobsize = mtd->writesize >> 5;
9bfbc9b2 3358 /* Pages per a block are always 64 in OneNAND */
28318776 3359 mtd->erasesize = mtd->writesize << 6;
5988af23
RH
3360 /*
3361 * Flex-OneNAND SLC area has 64 pages per block.
3362 * Flex-OneNAND MLC area has 128 pages per block.
3363 * Expose MLC erase size to find erase_shift and page_mask.
3364 */
3365 if (FLEXONENAND(this))
3366 mtd->erasesize <<= 1;
cd5f6346
KP
3367
3368 this->erase_shift = ffs(mtd->erasesize) - 1;
28318776 3369 this->page_shift = ffs(mtd->writesize) - 1;
9bfbc9b2 3370 this->page_mask = (1 << (this->erase_shift - this->page_shift)) - 1;
5988af23
RH
3371 /* Set density mask. it is used for DDP */
3372 if (ONENAND_IS_DDP(this))
3373 this->density_mask = this->chipsize >> (this->erase_shift + 1);
ee9745fc
KP
3374 /* It's real page size */
3375 this->writesize = mtd->writesize;
cd5f6346
KP
3376
3377 /* REVIST: Multichip handling */
3378
5988af23
RH
3379 if (FLEXONENAND(this))
3380 flexonenand_get_size(mtd);
3381 else
3382 mtd->size = this->chipsize;
cd5f6346 3383
75384b0d
KP
3384 /* Check OneNAND features */
3385 onenand_check_features(mtd);
d5c5e78a 3386
ee9745fc
KP
3387 /*
3388 * We emulate the 4KiB page and 256KiB erase block size
3389 * But oobsize is still 64 bytes.
3390 * It is only valid if you turn on 2X program support,
3391 * Otherwise it will be ignored by compiler.
3392 */
3393 if (ONENAND_IS_2PLANE(this)) {
3394 mtd->writesize <<= 1;
3395 mtd->erasesize <<= 1;
3396 }
3397
cd5f6346
KP
3398 return 0;
3399}
3400
a41371eb
KP
3401/**
3402 * onenand_suspend - [MTD Interface] Suspend the OneNAND flash
3403 * @param mtd MTD device structure
3404 */
3405static int onenand_suspend(struct mtd_info *mtd)
3406{
3407 return onenand_get_device(mtd, FL_PM_SUSPENDED);
3408}
3409
3410/**
3411 * onenand_resume - [MTD Interface] Resume the OneNAND flash
3412 * @param mtd MTD device structure
3413 */
3414static void onenand_resume(struct mtd_info *mtd)
3415{
3416 struct onenand_chip *this = mtd->priv;
3417
3418 if (this->state == FL_PM_SUSPENDED)
3419 onenand_release_device(mtd);
3420 else
3421 printk(KERN_ERR "resume() called for the chip which is not"
3422 "in suspended state\n");
3423}
3424
cd5f6346
KP
3425/**
3426 * onenand_scan - [OneNAND Interface] Scan for the OneNAND device
3427 * @param mtd MTD device structure
3428 * @param maxchips Number of chips to scan for
3429 *
3430 * This fills out all the not initialized function pointers
3431 * with the defaults.
3432 * The flash ID is read and the mtd/chip structures are
3433 * filled with the appropriate values.
3434 */
3435int onenand_scan(struct mtd_info *mtd, int maxchips)
3436{
5988af23 3437 int i, ret;
cd5f6346
KP
3438 struct onenand_chip *this = mtd->priv;
3439
3440 if (!this->read_word)
3441 this->read_word = onenand_readw;
3442 if (!this->write_word)
3443 this->write_word = onenand_writew;
3444
3445 if (!this->command)
3446 this->command = onenand_command;
3447 if (!this->wait)
2c22120f 3448 onenand_setup_wait(mtd);
31bb999e
KP
3449 if (!this->bbt_wait)
3450 this->bbt_wait = onenand_bbt_wait;
3451 if (!this->unlock_all)
3452 this->unlock_all = onenand_unlock_all;
cd5f6346
KP
3453
3454 if (!this->read_bufferram)
3455 this->read_bufferram = onenand_read_bufferram;
3456 if (!this->write_bufferram)
3457 this->write_bufferram = onenand_write_bufferram;
3458
cdc00130
KP
3459 if (!this->block_markbad)
3460 this->block_markbad = onenand_default_block_markbad;
3461 if (!this->scan_bbt)
3462 this->scan_bbt = onenand_default_bbt;
3463
cd5f6346
KP
3464 if (onenand_probe(mtd))
3465 return -ENXIO;
3466
52b0eea7
KP
3467 /* Set Sync. Burst Read after probing */
3468 if (this->mmcontrol) {
3469 printk(KERN_INFO "OneNAND Sync. Burst Read support\n");
3470 this->read_bufferram = onenand_sync_read_bufferram;
3471 }
3472
532a37cf
KP
3473 /* Allocate buffers, if necessary */
3474 if (!this->page_buf) {
470bc844 3475 this->page_buf = kzalloc(mtd->writesize, GFP_KERNEL);
532a37cf
KP
3476 if (!this->page_buf) {
3477 printk(KERN_ERR "onenand_scan(): Can't allocate page_buf\n");
3478 return -ENOMEM;
3479 }
3480 this->options |= ONENAND_PAGEBUF_ALLOC;
3481 }
470bc844
KP
3482 if (!this->oob_buf) {
3483 this->oob_buf = kzalloc(mtd->oobsize, GFP_KERNEL);
3484 if (!this->oob_buf) {
3485 printk(KERN_ERR "onenand_scan(): Can't allocate oob_buf\n");
3486 if (this->options & ONENAND_PAGEBUF_ALLOC) {
3487 this->options &= ~ONENAND_PAGEBUF_ALLOC;
3488 kfree(this->page_buf);
3489 }
3490 return -ENOMEM;
3491 }
3492 this->options |= ONENAND_OOBBUF_ALLOC;
3493 }
532a37cf 3494
cd5f6346
KP
3495 this->state = FL_READY;
3496 init_waitqueue_head(&this->wq);
3497 spin_lock_init(&this->chip_lock);
3498
60d84f97
KP
3499 /*
3500 * Allow subpage writes up to oobsize.
3501 */
cd5f6346 3502 switch (mtd->oobsize) {
5988af23
RH
3503 case 128:
3504 this->ecclayout = &onenand_oob_128;
3505 mtd->subpage_sft = 0;
3506 break;
cd5f6346 3507 case 64:
5bd34c09 3508 this->ecclayout = &onenand_oob_64;
60d84f97 3509 mtd->subpage_sft = 2;
cd5f6346
KP
3510 break;
3511
3512 case 32:
5bd34c09 3513 this->ecclayout = &onenand_oob_32;
60d84f97 3514 mtd->subpage_sft = 1;
cd5f6346
KP
3515 break;
3516
3517 default:
3518 printk(KERN_WARNING "No OOB scheme defined for oobsize %d\n",
3519 mtd->oobsize);
60d84f97 3520 mtd->subpage_sft = 0;
cd5f6346 3521 /* To prevent kernel oops */
5bd34c09 3522 this->ecclayout = &onenand_oob_32;
cd5f6346
KP
3523 break;
3524 }
3525
60d84f97 3526 this->subpagesize = mtd->writesize >> mtd->subpage_sft;
a5e7c7b4
AH
3527
3528 /*
3529 * The number of bytes available for a client to place data into
3530 * the out of band area
3531 */
3532 this->ecclayout->oobavail = 0;
ad286343
KP
3533 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES &&
3534 this->ecclayout->oobfree[i].length; i++)
a5e7c7b4
AH
3535 this->ecclayout->oobavail +=
3536 this->ecclayout->oobfree[i].length;
1f92267c 3537 mtd->oobavail = this->ecclayout->oobavail;
a5e7c7b4 3538
5bd34c09 3539 mtd->ecclayout = this->ecclayout;
d5c5e78a 3540
cd5f6346
KP
3541 /* Fill in remaining MTD driver data */
3542 mtd->type = MTD_NANDFLASH;
5fa43394 3543 mtd->flags = MTD_CAP_NANDFLASH;
cd5f6346
KP
3544 mtd->erase = onenand_erase;
3545 mtd->point = NULL;
3546 mtd->unpoint = NULL;
3547 mtd->read = onenand_read;
3548 mtd->write = onenand_write;
cd5f6346
KP
3549 mtd->read_oob = onenand_read_oob;
3550 mtd->write_oob = onenand_write_oob;
6c77fd64 3551 mtd->panic_write = onenand_panic_write;
493c6460
KP
3552#ifdef CONFIG_MTD_ONENAND_OTP
3553 mtd->get_fact_prot_info = onenand_get_fact_prot_info;
3554 mtd->read_fact_prot_reg = onenand_read_fact_prot_reg;
3555 mtd->get_user_prot_info = onenand_get_user_prot_info;
3556 mtd->read_user_prot_reg = onenand_read_user_prot_reg;
3557 mtd->write_user_prot_reg = onenand_write_user_prot_reg;
3558 mtd->lock_user_prot_reg = onenand_lock_user_prot_reg;
3559#endif
cd5f6346 3560 mtd->sync = onenand_sync;
08f782b6 3561 mtd->lock = onenand_lock;
cd5f6346 3562 mtd->unlock = onenand_unlock;
a41371eb
KP
3563 mtd->suspend = onenand_suspend;
3564 mtd->resume = onenand_resume;
cd5f6346
KP
3565 mtd->block_isbad = onenand_block_isbad;
3566 mtd->block_markbad = onenand_block_markbad;
3567 mtd->owner = THIS_MODULE;
3568
3569 /* Unlock whole block */
31bb999e 3570 this->unlock_all(mtd);
cd5f6346 3571
5988af23
RH
3572 ret = this->scan_bbt(mtd);
3573 if ((!FLEXONENAND(this)) || ret)
3574 return ret;
3575
3576 /* Change Flex-OneNAND boundaries if required */
3577 for (i = 0; i < MAX_DIES; i++)
3578 flexonenand_set_boundary(mtd, i, flex_bdry[2 * i],
3579 flex_bdry[(2 * i) + 1]);
3580
3581 return 0;
cd5f6346
KP
3582}
3583
3584/**
3585 * onenand_release - [OneNAND Interface] Free resources held by the OneNAND device
3586 * @param mtd MTD device structure
3587 */
3588void onenand_release(struct mtd_info *mtd)
3589{
532a37cf
KP
3590 struct onenand_chip *this = mtd->priv;
3591
cd5f6346
KP
3592#ifdef CONFIG_MTD_PARTITIONS
3593 /* Deregister partitions */
3594 del_mtd_partitions (mtd);
3595#endif
3596 /* Deregister the device */
3597 del_mtd_device (mtd);
532a37cf
KP
3598
3599 /* Free bad block table memory, if allocated */
f00b0046
AH
3600 if (this->bbm) {
3601 struct bbm_info *bbm = this->bbm;
3602 kfree(bbm->bbt);
532a37cf 3603 kfree(this->bbm);
f00b0046 3604 }
470bc844 3605 /* Buffers allocated by onenand_scan */
532a37cf
KP
3606 if (this->options & ONENAND_PAGEBUF_ALLOC)
3607 kfree(this->page_buf);
470bc844
KP
3608 if (this->options & ONENAND_OOBBUF_ALLOC)
3609 kfree(this->oob_buf);
5988af23 3610 kfree(mtd->eraseregions);
cd5f6346
KP
3611}
3612
3613EXPORT_SYMBOL_GPL(onenand_scan);
3614EXPORT_SYMBOL_GPL(onenand_release);
3615
3616MODULE_LICENSE("GPL");
3617MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
3618MODULE_DESCRIPTION("Generic OneNAND flash driver code");
This page took 0.603926 seconds and 5 git commands to generate.