Commit | Line | Data |
---|---|---|
a50a97d4 WZ |
1 | /* |
2 | * Copyright (c) 2008-2009 Nuvoton technology corporation. | |
3 | * | |
4 | * Wan ZongShun <mcuos.com@gmail.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation;version 2 of the License. | |
9 | * | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/mii.h> | |
15 | #include <linux/netdevice.h> | |
16 | #include <linux/etherdevice.h> | |
17 | #include <linux/skbuff.h> | |
18 | #include <linux/ethtool.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/clk.h> | |
5a0e3ad6 | 21 | #include <linux/gfp.h> |
a50a97d4 WZ |
22 | |
23 | #define DRV_MODULE_NAME "w90p910-emc" | |
24 | #define DRV_MODULE_VERSION "0.1" | |
25 | ||
26 | /* Ethernet MAC Registers */ | |
27 | #define REG_CAMCMR 0x00 | |
28 | #define REG_CAMEN 0x04 | |
29 | #define REG_CAMM_BASE 0x08 | |
30 | #define REG_CAML_BASE 0x0c | |
31 | #define REG_TXDLSA 0x88 | |
32 | #define REG_RXDLSA 0x8C | |
33 | #define REG_MCMDR 0x90 | |
34 | #define REG_MIID 0x94 | |
35 | #define REG_MIIDA 0x98 | |
36 | #define REG_FFTCR 0x9C | |
37 | #define REG_TSDR 0xa0 | |
38 | #define REG_RSDR 0xa4 | |
39 | #define REG_DMARFC 0xa8 | |
40 | #define REG_MIEN 0xac | |
41 | #define REG_MISTA 0xb0 | |
42 | #define REG_CTXDSA 0xcc | |
43 | #define REG_CTXBSA 0xd0 | |
44 | #define REG_CRXDSA 0xd4 | |
45 | #define REG_CRXBSA 0xd8 | |
46 | ||
47 | /* mac controller bit */ | |
48 | #define MCMDR_RXON 0x01 | |
49 | #define MCMDR_ACP (0x01 << 3) | |
50 | #define MCMDR_SPCRC (0x01 << 5) | |
51 | #define MCMDR_TXON (0x01 << 8) | |
52 | #define MCMDR_FDUP (0x01 << 18) | |
53 | #define MCMDR_ENMDC (0x01 << 19) | |
54 | #define MCMDR_OPMOD (0x01 << 20) | |
55 | #define SWR (0x01 << 24) | |
56 | ||
57 | /* cam command regiser */ | |
58 | #define CAMCMR_AUP 0x01 | |
59 | #define CAMCMR_AMP (0x01 << 1) | |
60 | #define CAMCMR_ABP (0x01 << 2) | |
61 | #define CAMCMR_CCAM (0x01 << 3) | |
62 | #define CAMCMR_ECMP (0x01 << 4) | |
63 | #define CAM0EN 0x01 | |
64 | ||
65 | /* mac mii controller bit */ | |
66 | #define MDCCR (0x0a << 20) | |
67 | #define PHYAD (0x01 << 8) | |
68 | #define PHYWR (0x01 << 16) | |
69 | #define PHYBUSY (0x01 << 17) | |
70 | #define PHYPRESP (0x01 << 18) | |
71 | #define CAM_ENTRY_SIZE 0x08 | |
72 | ||
73 | /* rx and tx status */ | |
74 | #define TXDS_TXCP (0x01 << 19) | |
75 | #define RXDS_CRCE (0x01 << 17) | |
76 | #define RXDS_PTLE (0x01 << 19) | |
77 | #define RXDS_RXGD (0x01 << 20) | |
78 | #define RXDS_ALIE (0x01 << 21) | |
79 | #define RXDS_RP (0x01 << 22) | |
80 | ||
81 | /* mac interrupt status*/ | |
82 | #define MISTA_EXDEF (0x01 << 19) | |
83 | #define MISTA_TXBERR (0x01 << 24) | |
84 | #define MISTA_TDU (0x01 << 23) | |
85 | #define MISTA_RDU (0x01 << 10) | |
86 | #define MISTA_RXBERR (0x01 << 11) | |
87 | ||
88 | #define ENSTART 0x01 | |
89 | #define ENRXINTR 0x01 | |
90 | #define ENRXGD (0x01 << 4) | |
91 | #define ENRXBERR (0x01 << 11) | |
92 | #define ENTXINTR (0x01 << 16) | |
93 | #define ENTXCP (0x01 << 18) | |
94 | #define ENTXABT (0x01 << 21) | |
95 | #define ENTXBERR (0x01 << 24) | |
96 | #define ENMDC (0x01 << 19) | |
97 | #define PHYBUSY (0x01 << 17) | |
98 | #define MDCCR_VAL 0xa00000 | |
99 | ||
100 | /* rx and tx owner bit */ | |
101 | #define RX_OWEN_DMA (0x01 << 31) | |
102 | #define RX_OWEN_CPU (~(0x03 << 30)) | |
103 | #define TX_OWEN_DMA (0x01 << 31) | |
104 | #define TX_OWEN_CPU (~(0x01 << 31)) | |
105 | ||
106 | /* tx frame desc controller bit */ | |
107 | #define MACTXINTEN 0x04 | |
108 | #define CRCMODE 0x02 | |
109 | #define PADDINGMODE 0x01 | |
110 | ||
111 | /* fftcr controller bit */ | |
112 | #define TXTHD (0x03 << 8) | |
113 | #define BLENGTH (0x01 << 20) | |
114 | ||
115 | /* global setting for driver */ | |
116 | #define RX_DESC_SIZE 50 | |
117 | #define TX_DESC_SIZE 10 | |
118 | #define MAX_RBUFF_SZ 0x600 | |
119 | #define MAX_TBUFF_SZ 0x600 | |
120 | #define TX_TIMEOUT 50 | |
121 | #define DELAY 1000 | |
122 | #define CAM0 0x0 | |
123 | ||
124 | static int w90p910_mdio_read(struct net_device *dev, int phy_id, int reg); | |
125 | ||
126 | struct w90p910_rxbd { | |
127 | unsigned int sl; | |
128 | unsigned int buffer; | |
129 | unsigned int reserved; | |
130 | unsigned int next; | |
131 | }; | |
132 | ||
133 | struct w90p910_txbd { | |
134 | unsigned int mode; | |
135 | unsigned int buffer; | |
136 | unsigned int sl; | |
137 | unsigned int next; | |
138 | }; | |
139 | ||
140 | struct recv_pdesc { | |
141 | struct w90p910_rxbd desclist[RX_DESC_SIZE]; | |
142 | char recv_buf[RX_DESC_SIZE][MAX_RBUFF_SZ]; | |
143 | }; | |
144 | ||
145 | struct tran_pdesc { | |
146 | struct w90p910_txbd desclist[TX_DESC_SIZE]; | |
1e5053b7 | 147 | char tran_buf[TX_DESC_SIZE][MAX_TBUFF_SZ]; |
a50a97d4 WZ |
148 | }; |
149 | ||
150 | struct w90p910_ether { | |
151 | struct recv_pdesc *rdesc; | |
a50a97d4 | 152 | struct tran_pdesc *tdesc; |
1e5053b7 WZ |
153 | dma_addr_t rdesc_phys; |
154 | dma_addr_t tdesc_phys; | |
a50a97d4 WZ |
155 | struct net_device_stats stats; |
156 | struct platform_device *pdev; | |
1e5053b7 | 157 | struct resource *res; |
a50a97d4 WZ |
158 | struct sk_buff *skb; |
159 | struct clk *clk; | |
160 | struct clk *rmiiclk; | |
161 | struct mii_if_info mii; | |
162 | struct timer_list check_timer; | |
163 | void __iomem *reg; | |
ddb14175 WZ |
164 | int rxirq; |
165 | int txirq; | |
a50a97d4 WZ |
166 | unsigned int cur_tx; |
167 | unsigned int cur_rx; | |
168 | unsigned int finish_tx; | |
169 | unsigned int rx_packets; | |
170 | unsigned int rx_bytes; | |
171 | unsigned int start_tx_ptr; | |
172 | unsigned int start_rx_ptr; | |
173 | unsigned int linkflag; | |
a50a97d4 WZ |
174 | }; |
175 | ||
176 | static void update_linkspeed_register(struct net_device *dev, | |
177 | unsigned int speed, unsigned int duplex) | |
178 | { | |
179 | struct w90p910_ether *ether = netdev_priv(dev); | |
180 | unsigned int val; | |
181 | ||
182 | val = __raw_readl(ether->reg + REG_MCMDR); | |
183 | ||
184 | if (speed == SPEED_100) { | |
185 | /* 100 full/half duplex */ | |
186 | if (duplex == DUPLEX_FULL) { | |
187 | val |= (MCMDR_OPMOD | MCMDR_FDUP); | |
188 | } else { | |
189 | val |= MCMDR_OPMOD; | |
190 | val &= ~MCMDR_FDUP; | |
191 | } | |
192 | } else { | |
193 | /* 10 full/half duplex */ | |
194 | if (duplex == DUPLEX_FULL) { | |
195 | val |= MCMDR_FDUP; | |
196 | val &= ~MCMDR_OPMOD; | |
197 | } else { | |
198 | val &= ~(MCMDR_FDUP | MCMDR_OPMOD); | |
199 | } | |
200 | } | |
201 | ||
202 | __raw_writel(val, ether->reg + REG_MCMDR); | |
203 | } | |
204 | ||
205 | static void update_linkspeed(struct net_device *dev) | |
206 | { | |
207 | struct w90p910_ether *ether = netdev_priv(dev); | |
208 | struct platform_device *pdev; | |
209 | unsigned int bmsr, bmcr, lpa, speed, duplex; | |
210 | ||
211 | pdev = ether->pdev; | |
212 | ||
213 | if (!mii_link_ok(ðer->mii)) { | |
214 | ether->linkflag = 0x0; | |
215 | netif_carrier_off(dev); | |
216 | dev_warn(&pdev->dev, "%s: Link down.\n", dev->name); | |
217 | return; | |
218 | } | |
219 | ||
220 | if (ether->linkflag == 1) | |
221 | return; | |
222 | ||
223 | bmsr = w90p910_mdio_read(dev, ether->mii.phy_id, MII_BMSR); | |
224 | bmcr = w90p910_mdio_read(dev, ether->mii.phy_id, MII_BMCR); | |
225 | ||
226 | if (bmcr & BMCR_ANENABLE) { | |
227 | if (!(bmsr & BMSR_ANEGCOMPLETE)) | |
228 | return; | |
229 | ||
230 | lpa = w90p910_mdio_read(dev, ether->mii.phy_id, MII_LPA); | |
231 | ||
232 | if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) | |
233 | speed = SPEED_100; | |
234 | else | |
235 | speed = SPEED_10; | |
236 | ||
237 | if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) | |
238 | duplex = DUPLEX_FULL; | |
239 | else | |
240 | duplex = DUPLEX_HALF; | |
241 | ||
242 | } else { | |
243 | speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10; | |
244 | duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; | |
245 | } | |
246 | ||
247 | update_linkspeed_register(dev, speed, duplex); | |
248 | ||
249 | dev_info(&pdev->dev, "%s: Link now %i-%s\n", dev->name, speed, | |
250 | (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex"); | |
251 | ether->linkflag = 0x01; | |
252 | ||
253 | netif_carrier_on(dev); | |
254 | } | |
255 | ||
256 | static void w90p910_check_link(unsigned long dev_id) | |
257 | { | |
258 | struct net_device *dev = (struct net_device *) dev_id; | |
259 | struct w90p910_ether *ether = netdev_priv(dev); | |
260 | ||
261 | update_linkspeed(dev); | |
262 | mod_timer(ðer->check_timer, jiffies + msecs_to_jiffies(1000)); | |
263 | } | |
264 | ||
265 | static void w90p910_write_cam(struct net_device *dev, | |
266 | unsigned int x, unsigned char *pval) | |
267 | { | |
268 | struct w90p910_ether *ether = netdev_priv(dev); | |
269 | unsigned int msw, lsw; | |
270 | ||
271 | msw = (pval[0] << 24) | (pval[1] << 16) | (pval[2] << 8) | pval[3]; | |
272 | ||
273 | lsw = (pval[4] << 24) | (pval[5] << 16); | |
274 | ||
275 | __raw_writel(lsw, ether->reg + REG_CAML_BASE + x * CAM_ENTRY_SIZE); | |
276 | __raw_writel(msw, ether->reg + REG_CAMM_BASE + x * CAM_ENTRY_SIZE); | |
277 | } | |
278 | ||
1e5053b7 | 279 | static int w90p910_init_desc(struct net_device *dev) |
a50a97d4 WZ |
280 | { |
281 | struct w90p910_ether *ether; | |
1e5053b7 WZ |
282 | struct w90p910_txbd *tdesc; |
283 | struct w90p910_rxbd *rdesc; | |
284 | struct platform_device *pdev; | |
285 | unsigned int i; | |
a50a97d4 WZ |
286 | |
287 | ether = netdev_priv(dev); | |
1e5053b7 | 288 | pdev = ether->pdev; |
a50a97d4 WZ |
289 | |
290 | ether->tdesc = (struct tran_pdesc *) | |
1e5053b7 WZ |
291 | dma_alloc_coherent(&pdev->dev, sizeof(struct tran_pdesc), |
292 | ðer->tdesc_phys, GFP_KERNEL); | |
293 | ||
294 | if (!ether->tdesc) { | |
295 | dev_err(&pdev->dev, "Failed to allocate memory for tx desc\n"); | |
296 | return -ENOMEM; | |
297 | } | |
a50a97d4 WZ |
298 | |
299 | ether->rdesc = (struct recv_pdesc *) | |
1e5053b7 WZ |
300 | dma_alloc_coherent(&pdev->dev, sizeof(struct recv_pdesc), |
301 | ðer->rdesc_phys, GFP_KERNEL); | |
302 | ||
303 | if (!ether->rdesc) { | |
304 | dev_err(&pdev->dev, "Failed to allocate memory for rx desc\n"); | |
305 | dma_free_coherent(&pdev->dev, sizeof(struct tran_pdesc), | |
306 | ether->tdesc, ether->tdesc_phys); | |
307 | return -ENOMEM; | |
308 | } | |
a50a97d4 WZ |
309 | |
310 | for (i = 0; i < TX_DESC_SIZE; i++) { | |
1e5053b7 | 311 | unsigned int offset; |
a50a97d4 | 312 | |
1e5053b7 | 313 | tdesc = &(ether->tdesc->desclist[i]); |
a50a97d4 | 314 | |
1e5053b7 WZ |
315 | if (i == TX_DESC_SIZE - 1) |
316 | offset = offsetof(struct tran_pdesc, desclist[0]); | |
317 | else | |
318 | offset = offsetof(struct tran_pdesc, desclist[i + 1]); | |
a50a97d4 | 319 | |
1e5053b7 WZ |
320 | tdesc->next = ether->tdesc_phys + offset; |
321 | tdesc->buffer = ether->tdesc_phys + | |
322 | offsetof(struct tran_pdesc, tran_buf[i]); | |
a50a97d4 WZ |
323 | tdesc->sl = 0; |
324 | tdesc->mode = 0; | |
325 | } | |
326 | ||
1e5053b7 WZ |
327 | ether->start_tx_ptr = ether->tdesc_phys; |
328 | ||
a50a97d4 | 329 | for (i = 0; i < RX_DESC_SIZE; i++) { |
1e5053b7 | 330 | unsigned int offset; |
a50a97d4 | 331 | |
1e5053b7 | 332 | rdesc = &(ether->rdesc->desclist[i]); |
a50a97d4 | 333 | |
1e5053b7 WZ |
334 | if (i == RX_DESC_SIZE - 1) |
335 | offset = offsetof(struct recv_pdesc, desclist[0]); | |
336 | else | |
337 | offset = offsetof(struct recv_pdesc, desclist[i + 1]); | |
a50a97d4 | 338 | |
1e5053b7 | 339 | rdesc->next = ether->rdesc_phys + offset; |
a50a97d4 | 340 | rdesc->sl = RX_OWEN_DMA; |
1e5053b7 WZ |
341 | rdesc->buffer = ether->rdesc_phys + |
342 | offsetof(struct recv_pdesc, recv_buf[i]); | |
a50a97d4 | 343 | } |
1e5053b7 WZ |
344 | |
345 | ether->start_rx_ptr = ether->rdesc_phys; | |
346 | ||
347 | return 0; | |
a50a97d4 WZ |
348 | } |
349 | ||
350 | static void w90p910_set_fifo_threshold(struct net_device *dev) | |
351 | { | |
352 | struct w90p910_ether *ether = netdev_priv(dev); | |
353 | unsigned int val; | |
354 | ||
355 | val = TXTHD | BLENGTH; | |
356 | __raw_writel(val, ether->reg + REG_FFTCR); | |
357 | } | |
358 | ||
359 | static void w90p910_return_default_idle(struct net_device *dev) | |
360 | { | |
361 | struct w90p910_ether *ether = netdev_priv(dev); | |
362 | unsigned int val; | |
363 | ||
364 | val = __raw_readl(ether->reg + REG_MCMDR); | |
365 | val |= SWR; | |
366 | __raw_writel(val, ether->reg + REG_MCMDR); | |
367 | } | |
368 | ||
369 | static void w90p910_trigger_rx(struct net_device *dev) | |
370 | { | |
371 | struct w90p910_ether *ether = netdev_priv(dev); | |
372 | ||
373 | __raw_writel(ENSTART, ether->reg + REG_RSDR); | |
374 | } | |
375 | ||
376 | static void w90p910_trigger_tx(struct net_device *dev) | |
377 | { | |
378 | struct w90p910_ether *ether = netdev_priv(dev); | |
379 | ||
380 | __raw_writel(ENSTART, ether->reg + REG_TSDR); | |
381 | } | |
382 | ||
383 | static void w90p910_enable_mac_interrupt(struct net_device *dev) | |
384 | { | |
385 | struct w90p910_ether *ether = netdev_priv(dev); | |
386 | unsigned int val; | |
387 | ||
388 | val = ENTXINTR | ENRXINTR | ENRXGD | ENTXCP; | |
389 | val |= ENTXBERR | ENRXBERR | ENTXABT; | |
390 | ||
391 | __raw_writel(val, ether->reg + REG_MIEN); | |
392 | } | |
393 | ||
394 | static void w90p910_get_and_clear_int(struct net_device *dev, | |
395 | unsigned int *val) | |
396 | { | |
397 | struct w90p910_ether *ether = netdev_priv(dev); | |
398 | ||
399 | *val = __raw_readl(ether->reg + REG_MISTA); | |
400 | __raw_writel(*val, ether->reg + REG_MISTA); | |
401 | } | |
402 | ||
403 | static void w90p910_set_global_maccmd(struct net_device *dev) | |
404 | { | |
405 | struct w90p910_ether *ether = netdev_priv(dev); | |
406 | unsigned int val; | |
407 | ||
408 | val = __raw_readl(ether->reg + REG_MCMDR); | |
409 | val |= MCMDR_SPCRC | MCMDR_ENMDC | MCMDR_ACP | ENMDC; | |
410 | __raw_writel(val, ether->reg + REG_MCMDR); | |
411 | } | |
412 | ||
413 | static void w90p910_enable_cam(struct net_device *dev) | |
414 | { | |
415 | struct w90p910_ether *ether = netdev_priv(dev); | |
416 | unsigned int val; | |
417 | ||
418 | w90p910_write_cam(dev, CAM0, dev->dev_addr); | |
419 | ||
420 | val = __raw_readl(ether->reg + REG_CAMEN); | |
421 | val |= CAM0EN; | |
422 | __raw_writel(val, ether->reg + REG_CAMEN); | |
423 | } | |
424 | ||
425 | static void w90p910_enable_cam_command(struct net_device *dev) | |
426 | { | |
427 | struct w90p910_ether *ether = netdev_priv(dev); | |
428 | unsigned int val; | |
429 | ||
430 | val = CAMCMR_ECMP | CAMCMR_ABP | CAMCMR_AMP; | |
431 | __raw_writel(val, ether->reg + REG_CAMCMR); | |
432 | } | |
433 | ||
434 | static void w90p910_enable_tx(struct net_device *dev, unsigned int enable) | |
435 | { | |
436 | struct w90p910_ether *ether = netdev_priv(dev); | |
437 | unsigned int val; | |
438 | ||
439 | val = __raw_readl(ether->reg + REG_MCMDR); | |
440 | ||
441 | if (enable) | |
442 | val |= MCMDR_TXON; | |
443 | else | |
444 | val &= ~MCMDR_TXON; | |
445 | ||
446 | __raw_writel(val, ether->reg + REG_MCMDR); | |
447 | } | |
448 | ||
449 | static void w90p910_enable_rx(struct net_device *dev, unsigned int enable) | |
450 | { | |
451 | struct w90p910_ether *ether = netdev_priv(dev); | |
452 | unsigned int val; | |
453 | ||
454 | val = __raw_readl(ether->reg + REG_MCMDR); | |
455 | ||
456 | if (enable) | |
457 | val |= MCMDR_RXON; | |
458 | else | |
459 | val &= ~MCMDR_RXON; | |
460 | ||
461 | __raw_writel(val, ether->reg + REG_MCMDR); | |
462 | } | |
463 | ||
464 | static void w90p910_set_curdest(struct net_device *dev) | |
465 | { | |
466 | struct w90p910_ether *ether = netdev_priv(dev); | |
467 | ||
468 | __raw_writel(ether->start_rx_ptr, ether->reg + REG_RXDLSA); | |
469 | __raw_writel(ether->start_tx_ptr, ether->reg + REG_TXDLSA); | |
470 | } | |
471 | ||
472 | static void w90p910_reset_mac(struct net_device *dev) | |
473 | { | |
474 | struct w90p910_ether *ether = netdev_priv(dev); | |
475 | ||
a50a97d4 WZ |
476 | w90p910_enable_tx(dev, 0); |
477 | w90p910_enable_rx(dev, 0); | |
478 | w90p910_set_fifo_threshold(dev); | |
479 | w90p910_return_default_idle(dev); | |
480 | ||
481 | if (!netif_queue_stopped(dev)) | |
482 | netif_stop_queue(dev); | |
483 | ||
484 | w90p910_init_desc(dev); | |
485 | ||
1ae5dc34 | 486 | dev->trans_start = jiffies; /* prevent tx timeout */ |
a50a97d4 WZ |
487 | ether->cur_tx = 0x0; |
488 | ether->finish_tx = 0x0; | |
489 | ether->cur_rx = 0x0; | |
490 | ||
491 | w90p910_set_curdest(dev); | |
492 | w90p910_enable_cam(dev); | |
493 | w90p910_enable_cam_command(dev); | |
494 | w90p910_enable_mac_interrupt(dev); | |
495 | w90p910_enable_tx(dev, 1); | |
496 | w90p910_enable_rx(dev, 1); | |
497 | w90p910_trigger_tx(dev); | |
498 | w90p910_trigger_rx(dev); | |
499 | ||
1ae5dc34 | 500 | dev->trans_start = jiffies; /* prevent tx timeout */ |
a50a97d4 WZ |
501 | |
502 | if (netif_queue_stopped(dev)) | |
503 | netif_wake_queue(dev); | |
a50a97d4 WZ |
504 | } |
505 | ||
506 | static void w90p910_mdio_write(struct net_device *dev, | |
507 | int phy_id, int reg, int data) | |
508 | { | |
509 | struct w90p910_ether *ether = netdev_priv(dev); | |
510 | struct platform_device *pdev; | |
511 | unsigned int val, i; | |
512 | ||
513 | pdev = ether->pdev; | |
514 | ||
515 | __raw_writel(data, ether->reg + REG_MIID); | |
516 | ||
517 | val = (phy_id << 0x08) | reg; | |
518 | val |= PHYBUSY | PHYWR | MDCCR_VAL; | |
519 | __raw_writel(val, ether->reg + REG_MIIDA); | |
520 | ||
521 | for (i = 0; i < DELAY; i++) { | |
522 | if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0) | |
523 | break; | |
524 | } | |
525 | ||
526 | if (i == DELAY) | |
527 | dev_warn(&pdev->dev, "mdio write timed out\n"); | |
528 | } | |
529 | ||
530 | static int w90p910_mdio_read(struct net_device *dev, int phy_id, int reg) | |
531 | { | |
532 | struct w90p910_ether *ether = netdev_priv(dev); | |
533 | struct platform_device *pdev; | |
534 | unsigned int val, i, data; | |
535 | ||
536 | pdev = ether->pdev; | |
537 | ||
538 | val = (phy_id << 0x08) | reg; | |
539 | val |= PHYBUSY | MDCCR_VAL; | |
540 | __raw_writel(val, ether->reg + REG_MIIDA); | |
541 | ||
542 | for (i = 0; i < DELAY; i++) { | |
543 | if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0) | |
544 | break; | |
545 | } | |
546 | ||
547 | if (i == DELAY) { | |
548 | dev_warn(&pdev->dev, "mdio read timed out\n"); | |
549 | data = 0xffff; | |
550 | } else { | |
551 | data = __raw_readl(ether->reg + REG_MIID); | |
552 | } | |
553 | ||
554 | return data; | |
555 | } | |
556 | ||
1e5053b7 | 557 | static int w90p910_set_mac_address(struct net_device *dev, void *addr) |
a50a97d4 WZ |
558 | { |
559 | struct sockaddr *address = addr; | |
560 | ||
561 | if (!is_valid_ether_addr(address->sa_data)) | |
562 | return -EADDRNOTAVAIL; | |
563 | ||
564 | memcpy(dev->dev_addr, address->sa_data, dev->addr_len); | |
565 | w90p910_write_cam(dev, CAM0, dev->dev_addr); | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
570 | static int w90p910_ether_close(struct net_device *dev) | |
571 | { | |
572 | struct w90p910_ether *ether = netdev_priv(dev); | |
1e5053b7 | 573 | struct platform_device *pdev; |
a50a97d4 | 574 | |
1e5053b7 WZ |
575 | pdev = ether->pdev; |
576 | ||
577 | dma_free_coherent(&pdev->dev, sizeof(struct recv_pdesc), | |
578 | ether->rdesc, ether->rdesc_phys); | |
579 | dma_free_coherent(&pdev->dev, sizeof(struct tran_pdesc), | |
580 | ether->tdesc, ether->tdesc_phys); | |
a50a97d4 WZ |
581 | |
582 | netif_stop_queue(dev); | |
583 | ||
584 | del_timer_sync(ðer->check_timer); | |
585 | clk_disable(ether->rmiiclk); | |
586 | clk_disable(ether->clk); | |
587 | ||
588 | free_irq(ether->txirq, dev); | |
589 | free_irq(ether->rxirq, dev); | |
590 | ||
591 | return 0; | |
592 | } | |
593 | ||
594 | static struct net_device_stats *w90p910_ether_stats(struct net_device *dev) | |
595 | { | |
596 | struct w90p910_ether *ether; | |
597 | ||
598 | ether = netdev_priv(dev); | |
599 | ||
600 | return ðer->stats; | |
601 | } | |
602 | ||
603 | static int w90p910_send_frame(struct net_device *dev, | |
604 | unsigned char *data, int length) | |
605 | { | |
606 | struct w90p910_ether *ether; | |
607 | struct w90p910_txbd *txbd; | |
608 | struct platform_device *pdev; | |
609 | unsigned char *buffer; | |
610 | ||
611 | ether = netdev_priv(dev); | |
612 | pdev = ether->pdev; | |
613 | ||
614 | txbd = ðer->tdesc->desclist[ether->cur_tx]; | |
615 | buffer = ether->tdesc->tran_buf[ether->cur_tx]; | |
1e5053b7 | 616 | |
a50a97d4 WZ |
617 | if (length > 1514) { |
618 | dev_err(&pdev->dev, "send data %d bytes, check it\n", length); | |
619 | length = 1514; | |
620 | } | |
621 | ||
622 | txbd->sl = length & 0xFFFF; | |
623 | ||
624 | memcpy(buffer, data, length); | |
625 | ||
626 | txbd->mode = TX_OWEN_DMA | PADDINGMODE | CRCMODE | MACTXINTEN; | |
627 | ||
628 | w90p910_enable_tx(dev, 1); | |
629 | ||
630 | w90p910_trigger_tx(dev); | |
631 | ||
1e5053b7 WZ |
632 | if (++ether->cur_tx >= TX_DESC_SIZE) |
633 | ether->cur_tx = 0; | |
634 | ||
a50a97d4 WZ |
635 | txbd = ðer->tdesc->desclist[ether->cur_tx]; |
636 | ||
a50a97d4 WZ |
637 | if (txbd->mode & TX_OWEN_DMA) |
638 | netif_stop_queue(dev); | |
639 | ||
640 | return 0; | |
641 | } | |
642 | ||
643 | static int w90p910_ether_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
644 | { | |
645 | struct w90p910_ether *ether = netdev_priv(dev); | |
646 | ||
647 | if (!(w90p910_send_frame(dev, skb->data, skb->len))) { | |
648 | ether->skb = skb; | |
649 | dev_kfree_skb_irq(skb); | |
650 | return 0; | |
651 | } | |
1e5053b7 | 652 | return -EAGAIN; |
a50a97d4 WZ |
653 | } |
654 | ||
655 | static irqreturn_t w90p910_tx_interrupt(int irq, void *dev_id) | |
656 | { | |
657 | struct w90p910_ether *ether; | |
658 | struct w90p910_txbd *txbd; | |
659 | struct platform_device *pdev; | |
a50a97d4 WZ |
660 | struct net_device *dev; |
661 | unsigned int cur_entry, entry, status; | |
662 | ||
1e5053b7 | 663 | dev = dev_id; |
a50a97d4 WZ |
664 | ether = netdev_priv(dev); |
665 | pdev = ether->pdev; | |
666 | ||
a50a97d4 WZ |
667 | w90p910_get_and_clear_int(dev, &status); |
668 | ||
669 | cur_entry = __raw_readl(ether->reg + REG_CTXDSA); | |
670 | ||
1e5053b7 WZ |
671 | entry = ether->tdesc_phys + |
672 | offsetof(struct tran_pdesc, desclist[ether->finish_tx]); | |
a50a97d4 WZ |
673 | |
674 | while (entry != cur_entry) { | |
675 | txbd = ðer->tdesc->desclist[ether->finish_tx]; | |
676 | ||
1e5053b7 WZ |
677 | if (++ether->finish_tx >= TX_DESC_SIZE) |
678 | ether->finish_tx = 0; | |
a50a97d4 WZ |
679 | |
680 | if (txbd->sl & TXDS_TXCP) { | |
681 | ether->stats.tx_packets++; | |
682 | ether->stats.tx_bytes += txbd->sl & 0xFFFF; | |
683 | } else { | |
684 | ether->stats.tx_errors++; | |
685 | } | |
686 | ||
687 | txbd->sl = 0x0; | |
688 | txbd->mode = 0x0; | |
689 | ||
690 | if (netif_queue_stopped(dev)) | |
691 | netif_wake_queue(dev); | |
692 | ||
1e5053b7 WZ |
693 | entry = ether->tdesc_phys + |
694 | offsetof(struct tran_pdesc, desclist[ether->finish_tx]); | |
a50a97d4 WZ |
695 | } |
696 | ||
697 | if (status & MISTA_EXDEF) { | |
698 | dev_err(&pdev->dev, "emc defer exceed interrupt\n"); | |
699 | } else if (status & MISTA_TXBERR) { | |
1e5053b7 WZ |
700 | dev_err(&pdev->dev, "emc bus error interrupt\n"); |
701 | w90p910_reset_mac(dev); | |
702 | } else if (status & MISTA_TDU) { | |
703 | if (netif_queue_stopped(dev)) | |
704 | netif_wake_queue(dev); | |
705 | } | |
a50a97d4 WZ |
706 | |
707 | return IRQ_HANDLED; | |
708 | } | |
709 | ||
710 | static void netdev_rx(struct net_device *dev) | |
711 | { | |
712 | struct w90p910_ether *ether; | |
713 | struct w90p910_rxbd *rxbd; | |
714 | struct platform_device *pdev; | |
a50a97d4 WZ |
715 | struct sk_buff *skb; |
716 | unsigned char *data; | |
717 | unsigned int length, status, val, entry; | |
718 | ||
719 | ether = netdev_priv(dev); | |
720 | pdev = ether->pdev; | |
a50a97d4 WZ |
721 | |
722 | rxbd = ðer->rdesc->desclist[ether->cur_rx]; | |
723 | ||
724 | do { | |
725 | val = __raw_readl(ether->reg + REG_CRXDSA); | |
1e5053b7 WZ |
726 | |
727 | entry = ether->rdesc_phys + | |
728 | offsetof(struct recv_pdesc, desclist[ether->cur_rx]); | |
a50a97d4 WZ |
729 | |
730 | if (val == entry) | |
731 | break; | |
732 | ||
733 | status = rxbd->sl; | |
734 | length = status & 0xFFFF; | |
735 | ||
736 | if (status & RXDS_RXGD) { | |
737 | data = ether->rdesc->recv_buf[ether->cur_rx]; | |
738 | skb = dev_alloc_skb(length+2); | |
739 | if (!skb) { | |
740 | dev_err(&pdev->dev, "get skb buffer error\n"); | |
741 | ether->stats.rx_dropped++; | |
742 | return; | |
743 | } | |
744 | ||
a50a97d4 WZ |
745 | skb_reserve(skb, 2); |
746 | skb_put(skb, length); | |
747 | skb_copy_to_linear_data(skb, data, length); | |
748 | skb->protocol = eth_type_trans(skb, dev); | |
749 | ether->stats.rx_packets++; | |
750 | ether->stats.rx_bytes += length; | |
751 | netif_rx(skb); | |
752 | } else { | |
753 | ether->stats.rx_errors++; | |
754 | ||
755 | if (status & RXDS_RP) { | |
756 | dev_err(&pdev->dev, "rx runt err\n"); | |
757 | ether->stats.rx_length_errors++; | |
758 | } else if (status & RXDS_CRCE) { | |
1e5053b7 WZ |
759 | dev_err(&pdev->dev, "rx crc err\n"); |
760 | ether->stats.rx_crc_errors++; | |
761 | } else if (status & RXDS_ALIE) { | |
a50a97d4 WZ |
762 | dev_err(&pdev->dev, "rx aligment err\n"); |
763 | ether->stats.rx_frame_errors++; | |
764 | } else if (status & RXDS_PTLE) { | |
1e5053b7 WZ |
765 | dev_err(&pdev->dev, "rx longer err\n"); |
766 | ether->stats.rx_over_errors++; | |
a50a97d4 | 767 | } |
1e5053b7 | 768 | } |
a50a97d4 WZ |
769 | |
770 | rxbd->sl = RX_OWEN_DMA; | |
771 | rxbd->reserved = 0x0; | |
1e5053b7 WZ |
772 | |
773 | if (++ether->cur_rx >= RX_DESC_SIZE) | |
774 | ether->cur_rx = 0; | |
775 | ||
a50a97d4 WZ |
776 | rxbd = ðer->rdesc->desclist[ether->cur_rx]; |
777 | ||
a50a97d4 WZ |
778 | } while (1); |
779 | } | |
780 | ||
781 | static irqreturn_t w90p910_rx_interrupt(int irq, void *dev_id) | |
782 | { | |
783 | struct net_device *dev; | |
784 | struct w90p910_ether *ether; | |
785 | struct platform_device *pdev; | |
786 | unsigned int status; | |
787 | ||
1e5053b7 | 788 | dev = dev_id; |
a50a97d4 WZ |
789 | ether = netdev_priv(dev); |
790 | pdev = ether->pdev; | |
791 | ||
a50a97d4 WZ |
792 | w90p910_get_and_clear_int(dev, &status); |
793 | ||
794 | if (status & MISTA_RDU) { | |
795 | netdev_rx(dev); | |
a50a97d4 WZ |
796 | w90p910_trigger_rx(dev); |
797 | ||
a50a97d4 WZ |
798 | return IRQ_HANDLED; |
799 | } else if (status & MISTA_RXBERR) { | |
1e5053b7 WZ |
800 | dev_err(&pdev->dev, "emc rx bus error\n"); |
801 | w90p910_reset_mac(dev); | |
802 | } | |
a50a97d4 WZ |
803 | |
804 | netdev_rx(dev); | |
a50a97d4 WZ |
805 | return IRQ_HANDLED; |
806 | } | |
807 | ||
808 | static int w90p910_ether_open(struct net_device *dev) | |
809 | { | |
810 | struct w90p910_ether *ether; | |
811 | struct platform_device *pdev; | |
812 | ||
813 | ether = netdev_priv(dev); | |
814 | pdev = ether->pdev; | |
815 | ||
816 | w90p910_reset_mac(dev); | |
817 | w90p910_set_fifo_threshold(dev); | |
818 | w90p910_set_curdest(dev); | |
819 | w90p910_enable_cam(dev); | |
820 | w90p910_enable_cam_command(dev); | |
821 | w90p910_enable_mac_interrupt(dev); | |
822 | w90p910_set_global_maccmd(dev); | |
823 | w90p910_enable_rx(dev, 1); | |
824 | ||
825 | ether->rx_packets = 0x0; | |
826 | ether->rx_bytes = 0x0; | |
827 | ||
828 | if (request_irq(ether->txirq, w90p910_tx_interrupt, | |
829 | 0x0, pdev->name, dev)) { | |
830 | dev_err(&pdev->dev, "register irq tx failed\n"); | |
831 | return -EAGAIN; | |
832 | } | |
833 | ||
834 | if (request_irq(ether->rxirq, w90p910_rx_interrupt, | |
835 | 0x0, pdev->name, dev)) { | |
836 | dev_err(&pdev->dev, "register irq rx failed\n"); | |
1e5053b7 | 837 | free_irq(ether->txirq, dev); |
a50a97d4 WZ |
838 | return -EAGAIN; |
839 | } | |
840 | ||
841 | mod_timer(ðer->check_timer, jiffies + msecs_to_jiffies(1000)); | |
842 | netif_start_queue(dev); | |
843 | w90p910_trigger_rx(dev); | |
844 | ||
845 | dev_info(&pdev->dev, "%s is OPENED\n", dev->name); | |
846 | ||
847 | return 0; | |
848 | } | |
849 | ||
850 | static void w90p910_ether_set_multicast_list(struct net_device *dev) | |
851 | { | |
852 | struct w90p910_ether *ether; | |
853 | unsigned int rx_mode; | |
854 | ||
855 | ether = netdev_priv(dev); | |
856 | ||
857 | if (dev->flags & IFF_PROMISC) | |
858 | rx_mode = CAMCMR_AUP | CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP; | |
3b9a7728 JP |
859 | else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) |
860 | rx_mode = CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP; | |
861 | else | |
862 | rx_mode = CAMCMR_ECMP | CAMCMR_ABP; | |
a50a97d4 WZ |
863 | __raw_writel(rx_mode, ether->reg + REG_CAMCMR); |
864 | } | |
865 | ||
866 | static int w90p910_ether_ioctl(struct net_device *dev, | |
867 | struct ifreq *ifr, int cmd) | |
868 | { | |
869 | struct w90p910_ether *ether = netdev_priv(dev); | |
870 | struct mii_ioctl_data *data = if_mii(ifr); | |
871 | ||
872 | return generic_mii_ioctl(ðer->mii, data, cmd, NULL); | |
873 | } | |
874 | ||
875 | static void w90p910_get_drvinfo(struct net_device *dev, | |
876 | struct ethtool_drvinfo *info) | |
877 | { | |
878 | strcpy(info->driver, DRV_MODULE_NAME); | |
879 | strcpy(info->version, DRV_MODULE_VERSION); | |
880 | } | |
881 | ||
882 | static int w90p910_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
883 | { | |
884 | struct w90p910_ether *ether = netdev_priv(dev); | |
885 | return mii_ethtool_gset(ðer->mii, cmd); | |
886 | } | |
887 | ||
888 | static int w90p910_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
889 | { | |
890 | struct w90p910_ether *ether = netdev_priv(dev); | |
891 | return mii_ethtool_sset(ðer->mii, cmd); | |
892 | } | |
893 | ||
894 | static int w90p910_nway_reset(struct net_device *dev) | |
895 | { | |
896 | struct w90p910_ether *ether = netdev_priv(dev); | |
897 | return mii_nway_restart(ðer->mii); | |
898 | } | |
899 | ||
900 | static u32 w90p910_get_link(struct net_device *dev) | |
901 | { | |
902 | struct w90p910_ether *ether = netdev_priv(dev); | |
903 | return mii_link_ok(ðer->mii); | |
904 | } | |
905 | ||
906 | static const struct ethtool_ops w90p910_ether_ethtool_ops = { | |
907 | .get_settings = w90p910_get_settings, | |
908 | .set_settings = w90p910_set_settings, | |
909 | .get_drvinfo = w90p910_get_drvinfo, | |
910 | .nway_reset = w90p910_nway_reset, | |
911 | .get_link = w90p910_get_link, | |
912 | }; | |
913 | ||
914 | static const struct net_device_ops w90p910_ether_netdev_ops = { | |
915 | .ndo_open = w90p910_ether_open, | |
916 | .ndo_stop = w90p910_ether_close, | |
917 | .ndo_start_xmit = w90p910_ether_start_xmit, | |
918 | .ndo_get_stats = w90p910_ether_stats, | |
919 | .ndo_set_multicast_list = w90p910_ether_set_multicast_list, | |
1e5053b7 | 920 | .ndo_set_mac_address = w90p910_set_mac_address, |
a50a97d4 WZ |
921 | .ndo_do_ioctl = w90p910_ether_ioctl, |
922 | .ndo_validate_addr = eth_validate_addr, | |
923 | .ndo_change_mtu = eth_change_mtu, | |
924 | }; | |
925 | ||
926 | static void __init get_mac_address(struct net_device *dev) | |
927 | { | |
928 | struct w90p910_ether *ether = netdev_priv(dev); | |
929 | struct platform_device *pdev; | |
930 | char addr[6]; | |
931 | ||
932 | pdev = ether->pdev; | |
933 | ||
934 | addr[0] = 0x00; | |
935 | addr[1] = 0x02; | |
936 | addr[2] = 0xac; | |
937 | addr[3] = 0x55; | |
938 | addr[4] = 0x88; | |
939 | addr[5] = 0xa8; | |
940 | ||
941 | if (is_valid_ether_addr(addr)) | |
942 | memcpy(dev->dev_addr, &addr, 0x06); | |
943 | else | |
944 | dev_err(&pdev->dev, "invalid mac address\n"); | |
945 | } | |
946 | ||
947 | static int w90p910_ether_setup(struct net_device *dev) | |
948 | { | |
949 | struct w90p910_ether *ether = netdev_priv(dev); | |
950 | ||
951 | ether_setup(dev); | |
952 | dev->netdev_ops = &w90p910_ether_netdev_ops; | |
953 | dev->ethtool_ops = &w90p910_ether_ethtool_ops; | |
954 | ||
955 | dev->tx_queue_len = 16; | |
956 | dev->dma = 0x0; | |
957 | dev->watchdog_timeo = TX_TIMEOUT; | |
958 | ||
959 | get_mac_address(dev); | |
960 | ||
a50a97d4 WZ |
961 | ether->cur_tx = 0x0; |
962 | ether->cur_rx = 0x0; | |
963 | ether->finish_tx = 0x0; | |
964 | ether->linkflag = 0x0; | |
965 | ether->mii.phy_id = 0x01; | |
966 | ether->mii.phy_id_mask = 0x1f; | |
967 | ether->mii.reg_num_mask = 0x1f; | |
968 | ether->mii.dev = dev; | |
969 | ether->mii.mdio_read = w90p910_mdio_read; | |
970 | ether->mii.mdio_write = w90p910_mdio_write; | |
971 | ||
972 | setup_timer(ðer->check_timer, w90p910_check_link, | |
973 | (unsigned long)dev); | |
974 | ||
975 | return 0; | |
976 | } | |
977 | ||
978 | static int __devinit w90p910_ether_probe(struct platform_device *pdev) | |
979 | { | |
980 | struct w90p910_ether *ether; | |
981 | struct net_device *dev; | |
a50a97d4 WZ |
982 | int error; |
983 | ||
984 | dev = alloc_etherdev(sizeof(struct w90p910_ether)); | |
985 | if (!dev) | |
986 | return -ENOMEM; | |
987 | ||
1e5053b7 WZ |
988 | ether = netdev_priv(dev); |
989 | ||
990 | ether->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
991 | if (ether->res == NULL) { | |
a50a97d4 WZ |
992 | dev_err(&pdev->dev, "failed to get I/O memory\n"); |
993 | error = -ENXIO; | |
994 | goto failed_free; | |
995 | } | |
996 | ||
1e5053b7 WZ |
997 | if (!request_mem_region(ether->res->start, |
998 | resource_size(ether->res), pdev->name)) { | |
a50a97d4 WZ |
999 | dev_err(&pdev->dev, "failed to request I/O memory\n"); |
1000 | error = -EBUSY; | |
1001 | goto failed_free; | |
1002 | } | |
1003 | ||
1e5053b7 | 1004 | ether->reg = ioremap(ether->res->start, resource_size(ether->res)); |
a50a97d4 WZ |
1005 | if (ether->reg == NULL) { |
1006 | dev_err(&pdev->dev, "failed to remap I/O memory\n"); | |
1007 | error = -ENXIO; | |
1008 | goto failed_free_mem; | |
1009 | } | |
1010 | ||
1011 | ether->txirq = platform_get_irq(pdev, 0); | |
1012 | if (ether->txirq < 0) { | |
1013 | dev_err(&pdev->dev, "failed to get ether tx irq\n"); | |
1014 | error = -ENXIO; | |
1015 | goto failed_free_io; | |
1016 | } | |
1017 | ||
1018 | ether->rxirq = platform_get_irq(pdev, 1); | |
1019 | if (ether->rxirq < 0) { | |
1020 | dev_err(&pdev->dev, "failed to get ether rx irq\n"); | |
1021 | error = -ENXIO; | |
1022 | goto failed_free_txirq; | |
1023 | } | |
1024 | ||
1025 | platform_set_drvdata(pdev, dev); | |
1026 | ||
1027 | ether->clk = clk_get(&pdev->dev, NULL); | |
1028 | if (IS_ERR(ether->clk)) { | |
1029 | dev_err(&pdev->dev, "failed to get ether clock\n"); | |
1030 | error = PTR_ERR(ether->clk); | |
1031 | goto failed_free_rxirq; | |
1032 | } | |
1033 | ||
1034 | ether->rmiiclk = clk_get(&pdev->dev, "RMII"); | |
1035 | if (IS_ERR(ether->rmiiclk)) { | |
1036 | dev_err(&pdev->dev, "failed to get ether clock\n"); | |
1037 | error = PTR_ERR(ether->rmiiclk); | |
1038 | goto failed_put_clk; | |
1039 | } | |
1040 | ||
1041 | ether->pdev = pdev; | |
1042 | ||
1043 | w90p910_ether_setup(dev); | |
1044 | ||
1045 | error = register_netdev(dev); | |
1046 | if (error != 0) { | |
1047 | dev_err(&pdev->dev, "Regiter EMC w90p910 FAILED\n"); | |
1048 | error = -ENODEV; | |
1049 | goto failed_put_rmiiclk; | |
1050 | } | |
1051 | ||
1052 | return 0; | |
1053 | failed_put_rmiiclk: | |
1054 | clk_put(ether->rmiiclk); | |
1055 | failed_put_clk: | |
1056 | clk_put(ether->clk); | |
1057 | failed_free_rxirq: | |
1058 | free_irq(ether->rxirq, pdev); | |
1059 | platform_set_drvdata(pdev, NULL); | |
1060 | failed_free_txirq: | |
1061 | free_irq(ether->txirq, pdev); | |
1062 | failed_free_io: | |
1063 | iounmap(ether->reg); | |
1064 | failed_free_mem: | |
1e5053b7 | 1065 | release_mem_region(ether->res->start, resource_size(ether->res)); |
a50a97d4 WZ |
1066 | failed_free: |
1067 | free_netdev(dev); | |
1068 | return error; | |
1069 | } | |
1070 | ||
1071 | static int __devexit w90p910_ether_remove(struct platform_device *pdev) | |
1072 | { | |
1073 | struct net_device *dev = platform_get_drvdata(pdev); | |
1074 | struct w90p910_ether *ether = netdev_priv(dev); | |
1075 | ||
1076 | unregister_netdev(dev); | |
1e5053b7 | 1077 | |
a50a97d4 WZ |
1078 | clk_put(ether->rmiiclk); |
1079 | clk_put(ether->clk); | |
1e5053b7 WZ |
1080 | |
1081 | iounmap(ether->reg); | |
1082 | release_mem_region(ether->res->start, resource_size(ether->res)); | |
1083 | ||
1084 | free_irq(ether->txirq, dev); | |
1085 | free_irq(ether->rxirq, dev); | |
1086 | ||
a50a97d4 WZ |
1087 | del_timer_sync(ðer->check_timer); |
1088 | platform_set_drvdata(pdev, NULL); | |
1e5053b7 | 1089 | |
a50a97d4 WZ |
1090 | free_netdev(dev); |
1091 | return 0; | |
1092 | } | |
1093 | ||
1094 | static struct platform_driver w90p910_ether_driver = { | |
1095 | .probe = w90p910_ether_probe, | |
1096 | .remove = __devexit_p(w90p910_ether_remove), | |
1097 | .driver = { | |
456d8991 | 1098 | .name = "nuc900-emc", |
a50a97d4 WZ |
1099 | .owner = THIS_MODULE, |
1100 | }, | |
1101 | }; | |
1102 | ||
1103 | static int __init w90p910_ether_init(void) | |
1104 | { | |
1105 | return platform_driver_register(&w90p910_ether_driver); | |
1106 | } | |
1107 | ||
1108 | static void __exit w90p910_ether_exit(void) | |
1109 | { | |
1110 | platform_driver_unregister(&w90p910_ether_driver); | |
1111 | } | |
1112 | ||
1113 | module_init(w90p910_ether_init); | |
1114 | module_exit(w90p910_ether_exit); | |
1115 | ||
1116 | MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>"); | |
1117 | MODULE_DESCRIPTION("w90p910 MAC driver!"); | |
1118 | MODULE_LICENSE("GPL"); | |
456d8991 | 1119 | MODULE_ALIAS("platform:nuc900-emc"); |
a50a97d4 | 1120 |