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atlx: use embedded net_device_stats
[deliverable/linux.git] / drivers / net / atlx / atl2.c
CommitLineData
452c1ce2
CS		 1/*
2 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved.
3 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com>
4 *
5 * Derived from Intel e1000 driver
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23#include <asm/atomic.h>
24#include <linux/crc32.h>
25#include <linux/dma-mapping.h>
26#include <linux/etherdevice.h>
27#include <linux/ethtool.h>
28#include <linux/hardirq.h>
29#include <linux/if_vlan.h>
30#include <linux/in.h>
31#include <linux/interrupt.h>
32#include <linux/ip.h>
33#include <linux/irqflags.h>
34#include <linux/irqreturn.h>
35#include <linux/mii.h>
36#include <linux/net.h>
37#include <linux/netdevice.h>
38#include <linux/pci.h>
39#include <linux/pci_ids.h>
40#include <linux/pm.h>
41#include <linux/skbuff.h>
42#include <linux/spinlock.h>
43#include <linux/string.h>
44#include <linux/tcp.h>
45#include <linux/timer.h>
46#include <linux/types.h>
47#include <linux/workqueue.h>
48
49#include "atl2.h"
50
51#define ATL2_DRV_VERSION "2.2.3"
52
53static char atl2_driver_name[] = "atl2";
54static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver";
55static char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation.";
56static char atl2_driver_version[] = ATL2_DRV_VERSION;
57
58MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>");
59MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver");
60MODULE_LICENSE("GPL");
61MODULE_VERSION(ATL2_DRV_VERSION);
62
63/*
64 * atl2_pci_tbl - PCI Device ID Table
65 */
66static struct pci_device_id atl2_pci_tbl[] = {
67 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)},
68 /* required last entry */
69 {0,}
70};
71MODULE_DEVICE_TABLE(pci, atl2_pci_tbl);
72
73static void atl2_set_ethtool_ops(struct net_device *netdev);
74
75static void atl2_check_options(struct atl2_adapter *adapter);
76
77/*
78 * atl2_sw_init - Initialize general software structures (struct atl2_adapter)
79 * @adapter: board private structure to initialize
80 *
81 * atl2_sw_init initializes the Adapter private data structure.
82 * Fields are initialized based on PCI device information and
83 * OS network device settings (MTU size).
84 */
85static int __devinit atl2_sw_init(struct atl2_adapter *adapter)
86{
87 struct atl2_hw *hw = &adapter->hw;
88 struct pci_dev *pdev = adapter->pdev;
89
90 /* PCI config space info */
91 hw->vendor_id = pdev->vendor;
92 hw->device_id = pdev->device;
93 hw->subsystem_vendor_id = pdev->subsystem_vendor;
94 hw->subsystem_id = pdev->subsystem_device;
95
96 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
97 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
98
99 adapter->wol = 0;
100 adapter->ict = 50000; /* ~100ms */
101 adapter->link_speed = SPEED_0; /* hardware init */
102 adapter->link_duplex = FULL_DUPLEX;
103
104 hw->phy_configured = false;
105 hw->preamble_len = 7;
106 hw->ipgt = 0x60;
107 hw->min_ifg = 0x50;
108 hw->ipgr1 = 0x40;
109 hw->ipgr2 = 0x60;
110 hw->retry_buf = 2;
111 hw->max_retry = 0xf;
112 hw->lcol = 0x37;
113 hw->jam_ipg = 7;
114 hw->fc_rxd_hi = 0;
115 hw->fc_rxd_lo = 0;
116 hw->max_frame_size = adapter->netdev->mtu;
117
118 spin_lock_init(&adapter->stats_lock);
452c1ce2
CS		 119
120 set_bit(__ATL2_DOWN, &adapter->flags);
121
122 return 0;
123}
124
125/*
126 * atl2_set_multi - Multicast and Promiscuous mode set
127 * @netdev: network interface device structure
128 *
129 * The set_multi entry point is called whenever the multicast address
130 * list or the network interface flags are updated. This routine is
131 * responsible for configuring the hardware for proper multicast,
132 * promiscuous mode, and all-multi behavior.
133 */
134static void atl2_set_multi(struct net_device *netdev)
135{
136 struct atl2_adapter *adapter = netdev_priv(netdev);
137 struct atl2_hw *hw = &adapter->hw;
138 struct dev_mc_list *mc_ptr;
139 u32 rctl;
140 u32 hash_value;
141
142 /* Check for Promiscuous and All Multicast modes */
143 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL);
144
145 if (netdev->flags & IFF_PROMISC) {
146 rctl |= MAC_CTRL_PROMIS_EN;
147 } else if (netdev->flags & IFF_ALLMULTI) {
148 rctl |= MAC_CTRL_MC_ALL_EN;
149 rctl &= ~MAC_CTRL_PROMIS_EN;
150 } else
151 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
152
153 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);
154
155 /* clear the old settings from the multicast hash table */
156 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
157 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
158
159 /* comoute mc addresses' hash value ,and put it into hash table */
160 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
161 hash_value = atl2_hash_mc_addr(hw, mc_ptr->dmi_addr);
162 atl2_hash_set(hw, hash_value);
163 }
164}
165
166static void init_ring_ptrs(struct atl2_adapter *adapter)
167{
168 /* Read / Write Ptr Initialize: */
169 adapter->txd_write_ptr = 0;
170 atomic_set(&adapter->txd_read_ptr, 0);
171
172 adapter->rxd_read_ptr = 0;
173 adapter->rxd_write_ptr = 0;
174
175 atomic_set(&adapter->txs_write_ptr, 0);
176 adapter->txs_next_clear = 0;
177}
178
179/*
180 * atl2_configure - Configure Transmit&Receive Unit after Reset
181 * @adapter: board private structure
182 *
183 * Configure the Tx /Rx unit of the MAC after a reset.
184 */
185static int atl2_configure(struct atl2_adapter *adapter)
186{
187 struct atl2_hw *hw = &adapter->hw;
188 u32 value;
189
190 /* clear interrupt status */
191 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);
192
193 /* set MAC Address */
194 value = (((u32)hw->mac_addr[2]) << 24) |
195 (((u32)hw->mac_addr[3]) << 16) |
196 (((u32)hw->mac_addr[4]) << 8) |
197 (((u32)hw->mac_addr[5]));
198 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);
199 value = (((u32)hw->mac_addr[0]) << 8) |
200 (((u32)hw->mac_addr[1]));
201 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);
202
203 /* HI base address */
204 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
205 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32));
206
207 /* LO base address */
208 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,
209 (u32)(adapter->txd_dma & 0x00000000ffffffffULL));
210 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,
211 (u32)(adapter->txs_dma & 0x00000000ffffffffULL));
212 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,
213 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL));
214
215 /* element count */
216 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4));
217 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size);
218 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size);
219
220 /* config Internal SRAM */
221/*
222 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end);
223 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end);
224*/
225
226 /* config IPG/IFG */
227 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) <<
228 MAC_IPG_IFG_IPGT_SHIFT) |
229 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) <<
230 MAC_IPG_IFG_MIFG_SHIFT) |
231 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) <<
232 MAC_IPG_IFG_IPGR1_SHIFT)|
233 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) <<
234 MAC_IPG_IFG_IPGR2_SHIFT);
235 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);
236
237 /* config Half-Duplex Control */
238 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
239 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) <<
240 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
241 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
242 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
243 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) <<
244 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
245 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);
246
247 /* set Interrupt Moderator Timer */
248 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt);
249 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);
250
251 /* set Interrupt Clear Timer */
252 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict);
253
254 /* set MTU */
255 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +
256 ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE);
257
258 /* 1590 */
259 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);
260
261 /* flow control */
262 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi);
263 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo);
264
265 /* Init mailbox */
266 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr);
267 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr);
268
269 /* enable DMA read/write */
270 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN);
271 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN);
272
273 value = ATL2_READ_REG(&adapter->hw, REG_ISR);
274 if ((value & ISR_PHY_LINKDOWN) != 0)
275 value = 1; /* config failed */
276 else
277 value = 0;
278
279 /* clear all interrupt status */
280 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);
281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
282 return value;
283}
284
285/*
286 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources
287 * @adapter: board private structure
288 *
289 * Return 0 on success, negative on failure
290 */
291static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter)
292{
293 struct pci_dev *pdev = adapter->pdev;
294 int size;
295 u8 offset = 0;
296
297 /* real ring DMA buffer */
298 adapter->ring_size = size =
299 adapter->txd_ring_size * 1 + 7 + /* dword align */
300 adapter->txs_ring_size * 4 + 7 + /* dword align */
301 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */
302
303 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size,
304 &adapter->ring_dma);
305 if (!adapter->ring_vir_addr)
306 return -ENOMEM;
307 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
308
309 /* Init TXD Ring */
310 adapter->txd_dma = adapter->ring_dma ;
311 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;
312 adapter->txd_dma += offset;
313 adapter->txd_ring = (struct tx_pkt_header *) (adapter->ring_vir_addr +
314 offset);
315
316 /* Init TXS Ring */
317 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;
318 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0;
319 adapter->txs_dma += offset;
320 adapter->txs_ring = (struct tx_pkt_status *)
321 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset));
322
323 /* Init RXD Ring */
324 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4;
325 offset = (adapter->rxd_dma & 127) ?
326 (128 - (adapter->rxd_dma & 127)) : 0;
327 if (offset > 7)
328 offset -= 8;
329 else
330 offset += (128 - 8);
331
332 adapter->rxd_dma += offset;
333 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) +
334 (adapter->txs_ring_size * 4 + offset));
335
336/*
337 * Read / Write Ptr Initialize:
338 * init_ring_ptrs(adapter);
339 */
340 return 0;
341}
342
343/*
344 * atl2_irq_enable - Enable default interrupt generation settings
345 * @adapter: board private structure
346 */
347static inline void atl2_irq_enable(struct atl2_adapter *adapter)
348{
349 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
350 ATL2_WRITE_FLUSH(&adapter->hw);
351}
352
353/*
354 * atl2_irq_disable - Mask off interrupt generation on the NIC
355 * @adapter: board private structure
356 */
357static inline void atl2_irq_disable(struct atl2_adapter *adapter)
358{
359 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);
360 ATL2_WRITE_FLUSH(&adapter->hw);
361 synchronize_irq(adapter->pdev->irq);
362}
363
364#ifdef NETIF_F_HW_VLAN_TX
365static void atl2_vlan_rx_register(struct net_device *netdev,
366 struct vlan_group *grp)
367{
368 struct atl2_adapter *adapter = netdev_priv(netdev);
369 u32 ctrl;
370
371 atl2_irq_disable(adapter);
372 adapter->vlgrp = grp;
373
374 if (grp) {
375 /* enable VLAN tag insert/strip */
376 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
377 ctrl |= MAC_CTRL_RMV_VLAN;
378 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
379 } else {
380 /* disable VLAN tag insert/strip */
381 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
382 ctrl &= ~MAC_CTRL_RMV_VLAN;
383 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
384 }
385
386 atl2_irq_enable(adapter);
387}
388
389static void atl2_restore_vlan(struct atl2_adapter *adapter)
390{
391 atl2_vlan_rx_register(adapter->netdev, adapter->vlgrp);
392}
393#endif
394
395static void atl2_intr_rx(struct atl2_adapter *adapter)
396{
397 struct net_device *netdev = adapter->netdev;
398 struct rx_desc *rxd;
399 struct sk_buff *skb;
400
401 do {
402 rxd = adapter->rxd_ring+adapter->rxd_write_ptr;
403 if (!rxd->status.update)
404 break; /* end of tx */
405
406 /* clear this flag at once */
407 rxd->status.update = 0;
408
409 if (rxd->status.ok && rxd->status.pkt_size >= 60) {
410 int rx_size = (int)(rxd->status.pkt_size - 4);
411 /* alloc new buffer */
412 skb = netdev_alloc_skb(netdev, rx_size + NET_IP_ALIGN);
413 if (NULL == skb) {
414 printk(KERN_WARNING
415 "%s: Mem squeeze, deferring packet.\n",
416 netdev->name);
417 /*
418 * Check that some rx space is free. If not,
419 * free one and mark stats->rx_dropped++.
420 */
02e71731 421 netdev->stats.rx_dropped++;
452c1ce2
CS		 422 break;
423 }
424 skb_reserve(skb, NET_IP_ALIGN);
425 skb->dev = netdev;
426 memcpy(skb->data, rxd->packet, rx_size);
427 skb_put(skb, rx_size);
428 skb->protocol = eth_type_trans(skb, netdev);
429#ifdef NETIF_F_HW_VLAN_TX
430 if (adapter->vlgrp && (rxd->status.vlan)) {
431 u16 vlan_tag = (rxd->status.vtag>>4) |
432 ((rxd->status.vtag&7) << 13) |
433 ((rxd->status.vtag&8) << 9);
434 vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
435 } else
436#endif
437 netif_rx(skb);
02e71731
SH		 438 netdev->stats.rx_bytes += rx_size;
439 netdev->stats.rx_packets++;
452c1ce2
CS		 440 netdev->last_rx = jiffies;
441 } else {
02e71731 442 netdev->stats.rx_errors++;
452c1ce2
CS		 443
444 if (rxd->status.ok && rxd->status.pkt_size <= 60)
02e71731 445 netdev->stats.rx_length_errors++;
452c1ce2 446 if (rxd->status.mcast)
02e71731 447 netdev->stats.multicast++;
452c1ce2 448 if (rxd->status.crc)
02e71731 449 netdev->stats.rx_crc_errors++;
452c1ce2 450 if (rxd->status.align)
02e71731 451 netdev->stats.rx_frame_errors++;
452c1ce2
CS		 452 }
453
454 /* advance write ptr */
455 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size)
456 adapter->rxd_write_ptr = 0;
457 } while (1);
458
459 /* update mailbox? */
460 adapter->rxd_read_ptr = adapter->rxd_write_ptr;
461 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr);
462}
463
464static void atl2_intr_tx(struct atl2_adapter *adapter)
465{
02e71731 466 struct net_device *netdev = adapter->netdev;
452c1ce2
CS		 467 u32 txd_read_ptr;
468 u32 txs_write_ptr;
469 struct tx_pkt_status *txs;
470 struct tx_pkt_header *txph;
471 int free_hole = 0;
472
473 do {
474 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
475 txs = adapter->txs_ring + txs_write_ptr;
476 if (!txs->update)
477 break; /* tx stop here */
478
479 free_hole = 1;
480 txs->update = 0;
481
482 if (++txs_write_ptr == adapter->txs_ring_size)
483 txs_write_ptr = 0;
484 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr);
485
486 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr);
487 txph = (struct tx_pkt_header *)
488 (((u8 *)adapter->txd_ring) + txd_read_ptr);
489
490 if (txph->pkt_size != txs->pkt_size) {
491 struct tx_pkt_status *old_txs = txs;
492 printk(KERN_WARNING
493 "%s: txs packet size not consistent with txd"
494 " txd_:0x%08x, txs_:0x%08x!\n",
495 adapter->netdev->name,
496 *(u32 *)txph, *(u32 *)txs);
497 printk(KERN_WARNING
498 "txd read ptr: 0x%x\n",
499 txd_read_ptr);
500 txs = adapter->txs_ring + txs_write_ptr;
501 printk(KERN_WARNING
502 "txs-behind:0x%08x\n",
503 *(u32 *)txs);
504 if (txs_write_ptr < 2) {
505 txs = adapter->txs_ring +
506 (adapter->txs_ring_size +
507 txs_write_ptr - 2);
508 } else {
509 txs = adapter->txs_ring + (txs_write_ptr - 2);
510 }
511 printk(KERN_WARNING
512 "txs-before:0x%08x\n",
513 *(u32 *)txs);
514 txs = old_txs;
515 }
516
517 /* 4for TPH */
518 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3);
519 if (txd_read_ptr >= adapter->txd_ring_size)
520 txd_read_ptr -= adapter->txd_ring_size;
521
522 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr);
523
524 /* tx statistics: */
e2f092ff 525 if (txs->ok) {
02e71731
SH		 526 netdev->stats.tx_bytes += txs->pkt_size;
527 netdev->stats.tx_packets++;
e2f092ff 528 }
452c1ce2 529 else
02e71731 530 netdev->stats.tx_errors++;
452c1ce2
CS		 531
532 if (txs->defer)
02e71731 533 netdev->stats.collisions++;
452c1ce2 534 if (txs->abort_col)
02e71731 535 netdev->stats.tx_aborted_errors++;
452c1ce2 536 if (txs->late_col)
02e71731 537 netdev->stats.tx_window_errors++;
452c1ce2 538 if (txs->underun)
02e71731 539 netdev->stats.tx_fifo_errors++;
452c1ce2
CS		 540 } while (1);
541
542 if (free_hole) {
543 if (netif_queue_stopped(adapter->netdev) &&
544 netif_carrier_ok(adapter->netdev))
545 netif_wake_queue(adapter->netdev);
546 }
547}
548
549static void atl2_check_for_link(struct atl2_adapter *adapter)
550{
551 struct net_device *netdev = adapter->netdev;
552 u16 phy_data = 0;
553
554 spin_lock(&adapter->stats_lock);
555 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
556 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
557 spin_unlock(&adapter->stats_lock);
558
559 /* notify upper layer link down ASAP */
560 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
561 if (netif_carrier_ok(netdev)) { /* old link state: Up */
562 printk(KERN_INFO "%s: %s NIC Link is Down\n",
563 atl2_driver_name, netdev->name);
564 adapter->link_speed = SPEED_0;
565 netif_carrier_off(netdev);
566 netif_stop_queue(netdev);
567 }
568 }
569 schedule_work(&adapter->link_chg_task);
570}
571
572static inline void atl2_clear_phy_int(struct atl2_adapter *adapter)
573{
574 u16 phy_data;
575 spin_lock(&adapter->stats_lock);
576 atl2_read_phy_reg(&adapter->hw, 19, &phy_data);
577 spin_unlock(&adapter->stats_lock);
578}
579
580/*
581 * atl2_intr - Interrupt Handler
582 * @irq: interrupt number
583 * @data: pointer to a network interface device structure
584 * @pt_regs: CPU registers structure
585 */
586static irqreturn_t atl2_intr(int irq, void *data)
587{
588 struct atl2_adapter *adapter = netdev_priv(data);
589 struct atl2_hw *hw = &adapter->hw;
590 u32 status;
591
592 status = ATL2_READ_REG(hw, REG_ISR);
593 if (0 == status)
594 return IRQ_NONE;
595
596 /* link event */
597 if (status & ISR_PHY)
598 atl2_clear_phy_int(adapter);
599
600 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
601 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
602
603 /* check if PCIE PHY Link down */
604 if (status & ISR_PHY_LINKDOWN) {
605 if (netif_running(adapter->netdev)) { /* reset MAC */
606 ATL2_WRITE_REG(hw, REG_ISR, 0);
607 ATL2_WRITE_REG(hw, REG_IMR, 0);
608 ATL2_WRITE_FLUSH(hw);
609 schedule_work(&adapter->reset_task);
610 return IRQ_HANDLED;
611 }
612 }
613
614 /* check if DMA read/write error? */
615 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
616 ATL2_WRITE_REG(hw, REG_ISR, 0);
617 ATL2_WRITE_REG(hw, REG_IMR, 0);
618 ATL2_WRITE_FLUSH(hw);
619 schedule_work(&adapter->reset_task);
620 return IRQ_HANDLED;
621 }
622
623 /* link event */
624 if (status & (ISR_PHY | ISR_MANUAL)) {
02e71731 625 adapter->netdev->stats.tx_carrier_errors++;
452c1ce2
CS		 626 atl2_check_for_link(adapter);
627 }
628
629 /* transmit event */
630 if (status & ISR_TX_EVENT)
631 atl2_intr_tx(adapter);
632
633 /* rx exception */
634 if (status & ISR_RX_EVENT)
635 atl2_intr_rx(adapter);
636
637 /* re-enable Interrupt */
638 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
639 return IRQ_HANDLED;
640}
641
642static int atl2_request_irq(struct atl2_adapter *adapter)
643{
644 struct net_device *netdev = adapter->netdev;
645 int flags, err = 0;
646
647 flags = IRQF_SHARED;
648#ifdef CONFIG_PCI_MSI
649 adapter->have_msi = true;
650 err = pci_enable_msi(adapter->pdev);
651 if (err)
652 adapter->have_msi = false;
653
654 if (adapter->have_msi)
655 flags &= ~IRQF_SHARED;
656#endif
657
658 return request_irq(adapter->pdev->irq, &atl2_intr, flags, netdev->name,
659 netdev);
660}
661
662/*
663 * atl2_free_ring_resources - Free Tx / RX descriptor Resources
664 * @adapter: board private structure
665 *
666 * Free all transmit software resources
667 */
668static void atl2_free_ring_resources(struct atl2_adapter *adapter)
669{
670 struct pci_dev *pdev = adapter->pdev;
671 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr,
672 adapter->ring_dma);
673}
674
675/*
676 * atl2_open - Called when a network interface is made active
677 * @netdev: network interface device structure
678 *
679 * Returns 0 on success, negative value on failure
680 *
681 * The open entry point is called when a network interface is made
682 * active by the system (IFF_UP). At this point all resources needed
683 * for transmit and receive operations are allocated, the interrupt
684 * handler is registered with the OS, the watchdog timer is started,
685 * and the stack is notified that the interface is ready.
686 */
687static int atl2_open(struct net_device *netdev)
688{
689 struct atl2_adapter *adapter = netdev_priv(netdev);
690 int err;
691 u32 val;
692
693 /* disallow open during test */
694 if (test_bit(__ATL2_TESTING, &adapter->flags))
695 return -EBUSY;
696
697 /* allocate transmit descriptors */
698 err = atl2_setup_ring_resources(adapter);
699 if (err)
700 return err;
701
702 err = atl2_init_hw(&adapter->hw);
703 if (err) {
704 err = -EIO;
705 goto err_init_hw;
706 }
707
708 /* hardware has been reset, we need to reload some things */
709 atl2_set_multi(netdev);
710 init_ring_ptrs(adapter);
711
712#ifdef NETIF_F_HW_VLAN_TX
713 atl2_restore_vlan(adapter);
714#endif
715
716 if (atl2_configure(adapter)) {
717 err = -EIO;
718 goto err_config;
719 }
720
721 err = atl2_request_irq(adapter);
722 if (err)
723 goto err_req_irq;
724
725 clear_bit(__ATL2_DOWN, &adapter->flags);
726
727 mod_timer(&adapter->watchdog_timer, jiffies + 4*HZ);
728
729 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
730 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
731 val | MASTER_CTRL_MANUAL_INT);
732
733 atl2_irq_enable(adapter);
734
735 return 0;
736
737err_init_hw:
738err_req_irq:
739err_config:
740 atl2_free_ring_resources(adapter);
741 atl2_reset_hw(&adapter->hw);
742
743 return err;
744}
745
746static void atl2_down(struct atl2_adapter *adapter)
747{
748 struct net_device *netdev = adapter->netdev;
749
750 /* signal that we're down so the interrupt handler does not
751 * reschedule our watchdog timer */
752 set_bit(__ATL2_DOWN, &adapter->flags);
753
452c1ce2 754 netif_tx_disable(netdev);
452c1ce2
CS		 755
756 /* reset MAC to disable all RX/TX */
757 atl2_reset_hw(&adapter->hw);
758 msleep(1);
759
760 atl2_irq_disable(adapter);
761
762 del_timer_sync(&adapter->watchdog_timer);
763 del_timer_sync(&adapter->phy_config_timer);
764 clear_bit(0, &adapter->cfg_phy);
765
766 netif_carrier_off(netdev);
767 adapter->link_speed = SPEED_0;
768 adapter->link_duplex = -1;
769}
770
771static void atl2_free_irq(struct atl2_adapter *adapter)
772{
773 struct net_device *netdev = adapter->netdev;
774
775 free_irq(adapter->pdev->irq, netdev);
776
777#ifdef CONFIG_PCI_MSI
778 if (adapter->have_msi)
779 pci_disable_msi(adapter->pdev);
780#endif
781}
782
783/*
784 * atl2_close - Disables a network interface
785 * @netdev: network interface device structure
786 *
787 * Returns 0, this is not allowed to fail
788 *
789 * The close entry point is called when an interface is de-activated
790 * by the OS. The hardware is still under the drivers control, but
791 * needs to be disabled. A global MAC reset is issued to stop the
792 * hardware, and all transmit and receive resources are freed.
793 */
794static int atl2_close(struct net_device *netdev)
795{
796 struct atl2_adapter *adapter = netdev_priv(netdev);
797
798 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
799
800 atl2_down(adapter);
801 atl2_free_irq(adapter);
802 atl2_free_ring_resources(adapter);
803
804 return 0;
805}
806
807static inline int TxsFreeUnit(struct atl2_adapter *adapter)
808{
809 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
810
811 return (adapter->txs_next_clear >= txs_write_ptr) ?
812 (int) (adapter->txs_ring_size - adapter->txs_next_clear +
813 txs_write_ptr - 1) :
814 (int) (txs_write_ptr - adapter->txs_next_clear - 1);
815}
816
817static inline int TxdFreeBytes(struct atl2_adapter *adapter)
818{
819 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr);
820
821 return (adapter->txd_write_ptr >= txd_read_ptr) ?
822 (int) (adapter->txd_ring_size - adapter->txd_write_ptr +
823 txd_read_ptr - 1) :
824 (int) (txd_read_ptr - adapter->txd_write_ptr - 1);
825}
826
827static int atl2_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
828{
829 struct atl2_adapter *adapter = netdev_priv(netdev);
452c1ce2
CS		 830 struct tx_pkt_header *txph;
831 u32 offset, copy_len;
832 int txs_unused;
833 int txbuf_unused;
834
835 if (test_bit(__ATL2_DOWN, &adapter->flags)) {
836 dev_kfree_skb_any(skb);
837 return NETDEV_TX_OK;
838 }
839
840 if (unlikely(skb->len <= 0)) {
841 dev_kfree_skb_any(skb);
842 return NETDEV_TX_OK;
843 }
844
452c1ce2
CS		 845 txs_unused = TxsFreeUnit(adapter);
846 txbuf_unused = TxdFreeBytes(adapter);
847
848 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused ||
849 txs_unused < 1) {
850 /* not enough resources */
851 netif_stop_queue(netdev);
452c1ce2
CS		 852 return NETDEV_TX_BUSY;
853 }
854
855 offset = adapter->txd_write_ptr;
856
857 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset);
858
859 *(u32 *)txph = 0;
860 txph->pkt_size = skb->len;
861
862 offset += 4;
863 if (offset >= adapter->txd_ring_size)
864 offset -= adapter->txd_ring_size;
865 copy_len = adapter->txd_ring_size - offset;
866 if (copy_len >= skb->len) {
867 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len);
868 offset += ((u32)(skb->len + 3) & ~3);
869 } else {
870 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len);
871 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len,
872 skb->len-copy_len);
873 offset = ((u32)(skb->len-copy_len + 3) & ~3);
874 }
875#ifdef NETIF_F_HW_VLAN_TX
876 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
877 u16 vlan_tag = vlan_tx_tag_get(skb);
878 vlan_tag = (vlan_tag << 4) |
879 (vlan_tag >> 13) |
880 ((vlan_tag >> 9) & 0x8);
881 txph->ins_vlan = 1;
882 txph->vlan = vlan_tag;
883 }
884#endif
885 if (offset >= adapter->txd_ring_size)
886 offset -= adapter->txd_ring_size;
887 adapter->txd_write_ptr = offset;
888
889 /* clear txs before send */
890 adapter->txs_ring[adapter->txs_next_clear].update = 0;
891 if (++adapter->txs_next_clear == adapter->txs_ring_size)
892 adapter->txs_next_clear = 0;
893
894 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX,
895 (adapter->txd_write_ptr >> 2));
896
87241840 897 mmiowb();
452c1ce2
CS		 898 netdev->trans_start = jiffies;
899 dev_kfree_skb_any(skb);
900 return NETDEV_TX_OK;
901}
902
452c1ce2
CS		 903/*
904 * atl2_change_mtu - Change the Maximum Transfer Unit
905 * @netdev: network interface device structure
906 * @new_mtu: new value for maximum frame size
907 *
908 * Returns 0 on success, negative on failure
909 */
910static int atl2_change_mtu(struct net_device *netdev, int new_mtu)
911{
912 struct atl2_adapter *adapter = netdev_priv(netdev);
913 struct atl2_hw *hw = &adapter->hw;
914
915 if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE)))
916 return -EINVAL;
917
918 /* set MTU */
919 if (hw->max_frame_size != new_mtu) {
920 netdev->mtu = new_mtu;
921 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE +
922 VLAN_SIZE + ETHERNET_FCS_SIZE);
923 }
924
925 return 0;
926}
927
928/*
929 * atl2_set_mac - Change the Ethernet Address of the NIC
930 * @netdev: network interface device structure
931 * @p: pointer to an address structure
932 *
933 * Returns 0 on success, negative on failure
934 */
935static int atl2_set_mac(struct net_device *netdev, void *p)
936{
937 struct atl2_adapter *adapter = netdev_priv(netdev);
938 struct sockaddr *addr = p;
939
940 if (!is_valid_ether_addr(addr->sa_data))
941 return -EADDRNOTAVAIL;
942
943 if (netif_running(netdev))
944 return -EBUSY;
945
946 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
947 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
948
949 atl2_set_mac_addr(&adapter->hw);
950
951 return 0;
952}
953
954/*
955 * atl2_mii_ioctl -
956 * @netdev:
957 * @ifreq:
958 * @cmd:
959 */
960static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
961{
962 struct atl2_adapter *adapter = netdev_priv(netdev);
963 struct mii_ioctl_data *data = if_mii(ifr);
964 unsigned long flags;
965
966 switch (cmd) {
967 case SIOCGMIIPHY:
968 data->phy_id = 0;
969 break;
970 case SIOCGMIIREG:
971 if (!capable(CAP_NET_ADMIN))
972 return -EPERM;
973 spin_lock_irqsave(&adapter->stats_lock, flags);
974 if (atl2_read_phy_reg(&adapter->hw,
975 data->reg_num & 0x1F, &data->val_out)) {
976 spin_unlock_irqrestore(&adapter->stats_lock, flags);
977 return -EIO;
978 }
979 spin_unlock_irqrestore(&adapter->stats_lock, flags);
980 break;
981 case SIOCSMIIREG:
982 if (!capable(CAP_NET_ADMIN))
983 return -EPERM;
984 if (data->reg_num & ~(0x1F))
985 return -EFAULT;
986 spin_lock_irqsave(&adapter->stats_lock, flags);
987 if (atl2_write_phy_reg(&adapter->hw, data->reg_num,
988 data->val_in)) {
989 spin_unlock_irqrestore(&adapter->stats_lock, flags);
990 return -EIO;
991 }
992 spin_unlock_irqrestore(&adapter->stats_lock, flags);
993 break;
994 default:
995 return -EOPNOTSUPP;
996 }
997 return 0;
998}
999
1000/*
1001 * atl2_ioctl -
1002 * @netdev:
1003 * @ifreq:
1004 * @cmd:
1005 */
1006static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1007{
1008 switch (cmd) {
1009 case SIOCGMIIPHY:
1010 case SIOCGMIIREG:
1011 case SIOCSMIIREG:
1012 return atl2_mii_ioctl(netdev, ifr, cmd);
1013#ifdef ETHTOOL_OPS_COMPAT
1014 case SIOCETHTOOL:
1015 return ethtool_ioctl(ifr);
1016#endif
1017 default:
1018 return -EOPNOTSUPP;
1019 }
1020}
1021
1022/*
1023 * atl2_tx_timeout - Respond to a Tx Hang
1024 * @netdev: network interface device structure
1025 */
1026static void atl2_tx_timeout(struct net_device *netdev)
1027{
1028 struct atl2_adapter *adapter = netdev_priv(netdev);
1029
1030 /* Do the reset outside of interrupt context */
1031 schedule_work(&adapter->reset_task);
1032}
1033
1034/*
1035 * atl2_watchdog - Timer Call-back
1036 * @data: pointer to netdev cast into an unsigned long
1037 */
1038static void atl2_watchdog(unsigned long data)
1039{
1040 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
452c1ce2
CS		 1041
1042 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
02e71731
SH		 1043 u32 drop_rxd, drop_rxs;
1044 unsigned long flags;
1045
452c1ce2
CS		 1046 spin_lock_irqsave(&adapter->stats_lock, flags);
1047 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV);
1048 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV);
452c1ce2
CS		 1049 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1050
02e71731
SH		 1051 adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs;
1052
452c1ce2
CS		 1053 /* Reset the timer */
1054 mod_timer(&adapter->watchdog_timer, jiffies + 4 * HZ);
1055 }
1056}
1057
1058/*
1059 * atl2_phy_config - Timer Call-back
1060 * @data: pointer to netdev cast into an unsigned long
1061 */
1062static void atl2_phy_config(unsigned long data)
1063{
1064 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1065 struct atl2_hw *hw = &adapter->hw;
1066 unsigned long flags;
1067
1068 spin_lock_irqsave(&adapter->stats_lock, flags);
1069 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1070 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN |
1071 MII_CR_RESTART_AUTO_NEG);
1072 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1073 clear_bit(0, &adapter->cfg_phy);
1074}
1075
1076static int atl2_up(struct atl2_adapter *adapter)
1077{
1078 struct net_device *netdev = adapter->netdev;
1079 int err = 0;
1080 u32 val;
1081
1082 /* hardware has been reset, we need to reload some things */
1083
1084 err = atl2_init_hw(&adapter->hw);
1085 if (err) {
1086 err = -EIO;
1087 return err;
1088 }
1089
1090 atl2_set_multi(netdev);
1091 init_ring_ptrs(adapter);
1092
1093#ifdef NETIF_F_HW_VLAN_TX
1094 atl2_restore_vlan(adapter);
1095#endif
1096
1097 if (atl2_configure(adapter)) {
1098 err = -EIO;
1099 goto err_up;
1100 }
1101
1102 clear_bit(__ATL2_DOWN, &adapter->flags);
1103
1104 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1105 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val |
1106 MASTER_CTRL_MANUAL_INT);
1107
1108 atl2_irq_enable(adapter);
1109
1110err_up:
1111 return err;
1112}
1113
1114static void atl2_reinit_locked(struct atl2_adapter *adapter)
1115{
1116 WARN_ON(in_interrupt());
1117 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1118 msleep(1);
1119 atl2_down(adapter);
1120 atl2_up(adapter);
1121 clear_bit(__ATL2_RESETTING, &adapter->flags);
1122}
1123
1124static void atl2_reset_task(struct work_struct *work)
1125{
1126 struct atl2_adapter *adapter;
1127 adapter = container_of(work, struct atl2_adapter, reset_task);
1128
1129 atl2_reinit_locked(adapter);
1130}
1131
1132static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter)
1133{
1134 u32 value;
1135 struct atl2_hw *hw = &adapter->hw;
1136 struct net_device *netdev = adapter->netdev;
1137
1138 /* Config MAC CTRL Register */
1139 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1140
1141 /* duplex */
1142 if (FULL_DUPLEX == adapter->link_duplex)
1143 value |= MAC_CTRL_DUPLX;
1144
1145 /* flow control */
1146 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1147
1148 /* PAD & CRC */
1149 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1150
1151 /* preamble length */
1152 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) <<
1153 MAC_CTRL_PRMLEN_SHIFT);
1154
1155 /* vlan */
1156 if (adapter->vlgrp)
1157 value |= MAC_CTRL_RMV_VLAN;
1158
1159 /* filter mode */
1160 value |= MAC_CTRL_BC_EN;
1161 if (netdev->flags & IFF_PROMISC)
1162 value |= MAC_CTRL_PROMIS_EN;
1163 else if (netdev->flags & IFF_ALLMULTI)
1164 value |= MAC_CTRL_MC_ALL_EN;
1165
1166 /* half retry buffer */
1167 value |= (((u32)(adapter->hw.retry_buf &
1168 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1169
1170 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1171}
1172
1173static int atl2_check_link(struct atl2_adapter *adapter)
1174{
1175 struct atl2_hw *hw = &adapter->hw;
1176 struct net_device *netdev = adapter->netdev;
1177 int ret_val;
1178 u16 speed, duplex, phy_data;
1179 int reconfig = 0;
1180
1181 /* MII_BMSR must read twise */
1182 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1183 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1184 if (!(phy_data&BMSR_LSTATUS)) { /* link down */
1185 if (netif_carrier_ok(netdev)) { /* old link state: Up */
1186 u32 value;
1187 /* disable rx */
1188 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1189 value &= ~MAC_CTRL_RX_EN;
1190 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1191 adapter->link_speed = SPEED_0;
1192 netif_carrier_off(netdev);
1193 netif_stop_queue(netdev);
1194 }
1195 return 0;
1196 }
1197
1198 /* Link Up */
1199 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1200 if (ret_val)
1201 return ret_val;
1202 switch (hw->MediaType) {
1203 case MEDIA_TYPE_100M_FULL:
1204 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1205 reconfig = 1;
1206 break;
1207 case MEDIA_TYPE_100M_HALF:
1208 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1209 reconfig = 1;
1210 break;
1211 case MEDIA_TYPE_10M_FULL:
1212 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1213 reconfig = 1;
1214 break;
1215 case MEDIA_TYPE_10M_HALF:
1216 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1217 reconfig = 1;
1218 break;
1219 }
1220 /* link result is our setting */
1221 if (reconfig == 0) {
1222 if (adapter->link_speed != speed ||
1223 adapter->link_duplex != duplex) {
1224 adapter->link_speed = speed;
1225 adapter->link_duplex = duplex;
1226 atl2_setup_mac_ctrl(adapter);
1227 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n",
1228 atl2_driver_name, netdev->name,
1229 adapter->link_speed,
1230 adapter->link_duplex == FULL_DUPLEX ?
1231 "Full Duplex" : "Half Duplex");
1232 }
1233
1234 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
1235 netif_carrier_on(netdev);
1236 netif_wake_queue(netdev);
1237 }
1238 return 0;
1239 }
1240
1241 /* change original link status */
1242 if (netif_carrier_ok(netdev)) {
1243 u32 value;
1244 /* disable rx */
1245 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1246 value &= ~MAC_CTRL_RX_EN;
1247 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1248
1249 adapter->link_speed = SPEED_0;
1250 netif_carrier_off(netdev);
1251 netif_stop_queue(netdev);
1252 }
1253
1254 /* auto-neg, insert timer to re-config phy
1255 * (if interval smaller than 5 seconds, something strange) */
1256 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1257 if (!test_and_set_bit(0, &adapter->cfg_phy))
1258 mod_timer(&adapter->phy_config_timer, jiffies + 5 * HZ);
1259 }
1260
1261 return 0;
1262}
1263
1264/*
1265 * atl2_link_chg_task - deal with link change event Out of interrupt context
1266 * @netdev: network interface device structure
1267 */
1268static void atl2_link_chg_task(struct work_struct *work)
1269{
1270 struct atl2_adapter *adapter;
1271 unsigned long flags;
1272
1273 adapter = container_of(work, struct atl2_adapter, link_chg_task);
1274
1275 spin_lock_irqsave(&adapter->stats_lock, flags);
1276 atl2_check_link(adapter);
1277 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1278}
1279
1280static void atl2_setup_pcicmd(struct pci_dev *pdev)
1281{
1282 u16 cmd;
1283
1284 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1285
1286 if (cmd & PCI_COMMAND_INTX_DISABLE)
1287 cmd &= ~PCI_COMMAND_INTX_DISABLE;
1288 if (cmd & PCI_COMMAND_IO)
1289 cmd &= ~PCI_COMMAND_IO;
1290 if (0 == (cmd & PCI_COMMAND_MEMORY))
1291 cmd |= PCI_COMMAND_MEMORY;
1292 if (0 == (cmd & PCI_COMMAND_MASTER))
1293 cmd |= PCI_COMMAND_MASTER;
1294 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1295
1296 /*
1297 * some motherboards BIOS(PXE/EFI) driver may set PME
1298 * while they transfer control to OS (Windows/Linux)
1299 * so we should clear this bit before NIC work normally
1300 */
1301 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
1302}
1303
8d1b1fc9
KH		 1304#ifdef CONFIG_NET_POLL_CONTROLLER
1305static void atl2_poll_controller(struct net_device *netdev)
1306{
1307 disable_irq(netdev->irq);
1308 atl2_intr(netdev->irq, netdev);
1309 enable_irq(netdev->irq);
1310}
1311#endif
1312
452c1ce2
CS		 1313/*
1314 * atl2_probe - Device Initialization Routine
1315 * @pdev: PCI device information struct
1316 * @ent: entry in atl2_pci_tbl
1317 *
1318 * Returns 0 on success, negative on failure
1319 *
1320 * atl2_probe initializes an adapter identified by a pci_dev structure.
1321 * The OS initialization, configuring of the adapter private structure,
1322 * and a hardware reset occur.
1323 */
1324static int __devinit atl2_probe(struct pci_dev *pdev,
1325 const struct pci_device_id *ent)
1326{
1327 struct net_device *netdev;
1328 struct atl2_adapter *adapter;
1329 static int cards_found;
1330 unsigned long mmio_start;
1331 int mmio_len;
1332 int err;
1333
1334 cards_found = 0;
1335
1336 err = pci_enable_device(pdev);
1337 if (err)
1338 return err;
1339
1340 /*
1341 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA
1342 * until the kernel has the proper infrastructure to support 64-bit DMA
1343 * on these devices.
1344 */
1345 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) &&
1346 pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
1347 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n");
1348 goto err_dma;
1349 }
1350
1351 /* Mark all PCI regions associated with PCI device
1352 * pdev as being reserved by owner atl2_driver_name */
1353 err = pci_request_regions(pdev, atl2_driver_name);
1354 if (err)
1355 goto err_pci_reg;
1356
1357 /* Enables bus-mastering on the device and calls
1358 * pcibios_set_master to do the needed arch specific settings */
1359 pci_set_master(pdev);
1360
1361 err = -ENOMEM;
1362 netdev = alloc_etherdev(sizeof(struct atl2_adapter));
1363 if (!netdev)
1364 goto err_alloc_etherdev;
1365
1366 SET_NETDEV_DEV(netdev, &pdev->dev);
1367
1368 pci_set_drvdata(pdev, netdev);
1369 adapter = netdev_priv(netdev);
1370 adapter->netdev = netdev;
1371 adapter->pdev = pdev;
1372 adapter->hw.back = adapter;
1373
1374 mmio_start = pci_resource_start(pdev, 0x0);
1375 mmio_len = pci_resource_len(pdev, 0x0);
1376
1377 adapter->hw.mem_rang = (u32)mmio_len;
1378 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1379 if (!adapter->hw.hw_addr) {
1380 err = -EIO;
1381 goto err_ioremap;
1382 }
1383
1384 atl2_setup_pcicmd(pdev);
1385
1386 netdev->open = &atl2_open;
1387 netdev->stop = &atl2_close;
1388 netdev->hard_start_xmit = &atl2_xmit_frame;
452c1ce2
CS		 1389 netdev->set_multicast_list = &atl2_set_multi;
1390 netdev->set_mac_address = &atl2_set_mac;
1391 netdev->change_mtu = &atl2_change_mtu;
1392 netdev->do_ioctl = &atl2_ioctl;
1393 atl2_set_ethtool_ops(netdev);
1394
8d1b1fc9
KH		 1395#ifdef CONFIG_NET_POLL_CONTROLLER
1396 netdev->poll_controller = atl2_poll_controller;
1397#endif
452c1ce2
CS		 1398#ifdef HAVE_TX_TIMEOUT
1399 netdev->tx_timeout = &atl2_tx_timeout;
1400 netdev->watchdog_timeo = 5 * HZ;
1401#endif
1402#ifdef NETIF_F_HW_VLAN_TX
1403 netdev->vlan_rx_register = atl2_vlan_rx_register;
1404#endif
1405 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1406
1407 netdev->mem_start = mmio_start;
1408 netdev->mem_end = mmio_start + mmio_len;
1409 adapter->bd_number = cards_found;
1410 adapter->pci_using_64 = false;
1411
1412 /* setup the private structure */
1413 err = atl2_sw_init(adapter);
1414 if (err)
1415 goto err_sw_init;
1416
1417 err = -EIO;
1418
1419#ifdef NETIF_F_HW_VLAN_TX
1420 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
1421#endif
1422
452c1ce2
CS		 1423 /* Init PHY as early as possible due to power saving issue */
1424 atl2_phy_init(&adapter->hw);
1425
1426 /* reset the controller to
1427 * put the device in a known good starting state */
1428
1429 if (atl2_reset_hw(&adapter->hw)) {
1430 err = -EIO;
1431 goto err_reset;
1432 }
1433
1434 /* copy the MAC address out of the EEPROM */
1435 atl2_read_mac_addr(&adapter->hw);
1436 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
1437/* FIXME: do we still need this? */
1438#ifdef ETHTOOL_GPERMADDR
1439 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1440
1441 if (!is_valid_ether_addr(netdev->perm_addr)) {
1442#else
1443 if (!is_valid_ether_addr(netdev->dev_addr)) {
1444#endif
1445 err = -EIO;
1446 goto err_eeprom;
1447 }
1448
1449 atl2_check_options(adapter);
1450
1451 init_timer(&adapter->watchdog_timer);
1452 adapter->watchdog_timer.function = &atl2_watchdog;
1453 adapter->watchdog_timer.data = (unsigned long) adapter;
1454
1455 init_timer(&adapter->phy_config_timer);
1456 adapter->phy_config_timer.function = &atl2_phy_config;
1457 adapter->phy_config_timer.data = (unsigned long) adapter;
1458
1459 INIT_WORK(&adapter->reset_task, atl2_reset_task);
1460 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task);
1461
1462 strcpy(netdev->name, "eth%d"); /* ?? */
1463 err = register_netdev(netdev);
1464 if (err)
1465 goto err_register;
1466
1467 /* assume we have no link for now */
1468 netif_carrier_off(netdev);
1469 netif_stop_queue(netdev);
1470
1471 cards_found++;
1472
1473 return 0;
1474
1475err_reset:
1476err_register:
1477err_sw_init:
1478err_eeprom:
1479 iounmap(adapter->hw.hw_addr);
1480err_ioremap:
1481 free_netdev(netdev);
1482err_alloc_etherdev:
1483 pci_release_regions(pdev);
1484err_pci_reg:
1485err_dma:
1486 pci_disable_device(pdev);
1487 return err;
1488}
1489
1490/*
1491 * atl2_remove - Device Removal Routine
1492 * @pdev: PCI device information struct
1493 *
1494 * atl2_remove is called by the PCI subsystem to alert the driver
1495 * that it should release a PCI device. The could be caused by a
1496 * Hot-Plug event, or because the driver is going to be removed from
1497 * memory.
1498 */
1499/* FIXME: write the original MAC address back in case it was changed from a
1500 * BIOS-set value, as in atl1 -- CHS */
1501static void __devexit atl2_remove(struct pci_dev *pdev)
1502{
1503 struct net_device *netdev = pci_get_drvdata(pdev);
1504 struct atl2_adapter *adapter = netdev_priv(netdev);
1505
1506 /* flush_scheduled work may reschedule our watchdog task, so
1507 * explicitly disable watchdog tasks from being rescheduled */
1508 set_bit(__ATL2_DOWN, &adapter->flags);
1509
1510 del_timer_sync(&adapter->watchdog_timer);
1511 del_timer_sync(&adapter->phy_config_timer);
1512
1513 flush_scheduled_work();
1514
1515 unregister_netdev(netdev);
1516
1517 atl2_force_ps(&adapter->hw);
1518
1519 iounmap(adapter->hw.hw_addr);
1520 pci_release_regions(pdev);
1521
1522 free_netdev(netdev);
1523
1524 pci_disable_device(pdev);
1525}
1526
1527static int atl2_suspend(struct pci_dev *pdev, pm_message_t state)
1528{
1529 struct net_device *netdev = pci_get_drvdata(pdev);
1530 struct atl2_adapter *adapter = netdev_priv(netdev);
1531 struct atl2_hw *hw = &adapter->hw;
1532 u16 speed, duplex;
1533 u32 ctrl = 0;
1534 u32 wufc = adapter->wol;
1535
1536#ifdef CONFIG_PM
1537 int retval = 0;
1538#endif
1539
1540 netif_device_detach(netdev);
1541
1542 if (netif_running(netdev)) {
1543 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
1544 atl2_down(adapter);
1545 }
1546
1547#ifdef CONFIG_PM
1548 retval = pci_save_state(pdev);
1549 if (retval)
1550 return retval;
1551#endif
1552
1553 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1554 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1555 if (ctrl & BMSR_LSTATUS)
1556 wufc &= ~ATLX_WUFC_LNKC;
1557
1558 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) {
1559 u32 ret_val;
1560 /* get current link speed & duplex */
1561 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1562 if (ret_val) {
1563 printk(KERN_DEBUG
1564 "%s: get speed&duplex error while suspend\n",
1565 atl2_driver_name);
1566 goto wol_dis;
1567 }
1568
1569 ctrl = 0;
1570
1571 /* turn on magic packet wol */
1572 if (wufc & ATLX_WUFC_MAG)
1573 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
1574
1575 /* ignore Link Chg event when Link is up */
1576 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1577
1578 /* Config MAC CTRL Register */
1579 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1580 if (FULL_DUPLEX == adapter->link_duplex)
1581 ctrl |= MAC_CTRL_DUPLX;
1582 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1583 ctrl |= (((u32)adapter->hw.preamble_len &
1584 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1585 ctrl |= (((u32)(adapter->hw.retry_buf &
1586 MAC_CTRL_HALF_LEFT_BUF_MASK)) <<
1587 MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1588 if (wufc & ATLX_WUFC_MAG) {
1589 /* magic packet maybe Broadcast&multicast&Unicast */
1590 ctrl |= MAC_CTRL_BC_EN;
1591 }
1592
1593 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);
1594
1595 /* pcie patch */
1596 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1597 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1598 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1599 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1600 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1601 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1602
1603 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1604 goto suspend_exit;
1605 }
1606
1607 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) {
1608 /* link is down, so only LINK CHG WOL event enable */
1609 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
1610 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1611 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);
1612
1613 /* pcie patch */
1614 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1615 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1616 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1617 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1618 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1619 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1620
1621 hw->phy_configured = false; /* re-init PHY when resume */
1622
1623 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1624
1625 goto suspend_exit;
1626 }
1627
1628wol_dis:
1629 /* WOL disabled */
1630 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);
1631
1632 /* pcie patch */
1633 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1634 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1635 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1636 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1637 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1638 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1639
1640 atl2_force_ps(hw);
1641 hw->phy_configured = false; /* re-init PHY when resume */
1642
1643 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1644
1645suspend_exit:
1646 if (netif_running(netdev))
1647 atl2_free_irq(adapter);
1648
1649 pci_disable_device(pdev);
1650
1651 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1652
1653 return 0;
1654}
1655
1656#ifdef CONFIG_PM
1657static int atl2_resume(struct pci_dev *pdev)
1658{
1659 struct net_device *netdev = pci_get_drvdata(pdev);
1660 struct atl2_adapter *adapter = netdev_priv(netdev);
1661 u32 err;
1662
1663 pci_set_power_state(pdev, PCI_D0);
1664 pci_restore_state(pdev);
1665
1666 err = pci_enable_device(pdev);
1667 if (err) {
1668 printk(KERN_ERR
1669 "atl2: Cannot enable PCI device from suspend\n");
1670 return err;
1671 }
1672
1673 pci_set_master(pdev);
1674
1675 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
1676
1677 pci_enable_wake(pdev, PCI_D3hot, 0);
1678 pci_enable_wake(pdev, PCI_D3cold, 0);
1679
1680 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
1681
1682 err = atl2_request_irq(adapter);
1683 if (netif_running(netdev) && err)
1684 return err;
1685
1686 atl2_reset_hw(&adapter->hw);
1687
1688 if (netif_running(netdev))
1689 atl2_up(adapter);
1690
1691 netif_device_attach(netdev);
1692
1693 return 0;
1694}
1695#endif
1696
1697static void atl2_shutdown(struct pci_dev *pdev)
1698{
1699 atl2_suspend(pdev, PMSG_SUSPEND);
1700}
1701
1702static struct pci_driver atl2_driver = {
1703 .name = atl2_driver_name,
1704 .id_table = atl2_pci_tbl,
1705 .probe = atl2_probe,
1706 .remove = __devexit_p(atl2_remove),
1707 /* Power Managment Hooks */
1708 .suspend = atl2_suspend,
1709#ifdef CONFIG_PM
1710 .resume = atl2_resume,
1711#endif
1712 .shutdown = atl2_shutdown,
1713};
1714
1715/*
1716 * atl2_init_module - Driver Registration Routine
1717 *
1718 * atl2_init_module is the first routine called when the driver is
1719 * loaded. All it does is register with the PCI subsystem.
1720 */
1721static int __init atl2_init_module(void)
1722{
1723 printk(KERN_INFO "%s - version %s\n", atl2_driver_string,
1724 atl2_driver_version);
1725 printk(KERN_INFO "%s\n", atl2_copyright);
1726 return pci_register_driver(&atl2_driver);
1727}
1728module_init(atl2_init_module);
1729
1730/*
1731 * atl2_exit_module - Driver Exit Cleanup Routine
1732 *
1733 * atl2_exit_module is called just before the driver is removed
1734 * from memory.
1735 */
1736static void __exit atl2_exit_module(void)
1737{
1738 pci_unregister_driver(&atl2_driver);
1739}
1740module_exit(atl2_exit_module);
1741
1742static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1743{
1744 struct atl2_adapter *adapter = hw->back;
1745 pci_read_config_word(adapter->pdev, reg, value);
1746}
1747
1748static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1749{
1750 struct atl2_adapter *adapter = hw->back;
1751 pci_write_config_word(adapter->pdev, reg, *value);
1752}
1753
1754static int atl2_get_settings(struct net_device *netdev,
1755 struct ethtool_cmd *ecmd)
1756{
1757 struct atl2_adapter *adapter = netdev_priv(netdev);
1758 struct atl2_hw *hw = &adapter->hw;
1759
1760 ecmd->supported = (SUPPORTED_10baseT_Half |
1761 SUPPORTED_10baseT_Full |
1762 SUPPORTED_100baseT_Half |
1763 SUPPORTED_100baseT_Full |
1764 SUPPORTED_Autoneg |
1765 SUPPORTED_TP);
1766 ecmd->advertising = ADVERTISED_TP;
1767
1768 ecmd->advertising |= ADVERTISED_Autoneg;
1769 ecmd->advertising |= hw->autoneg_advertised;
1770
1771 ecmd->port = PORT_TP;
1772 ecmd->phy_address = 0;
1773 ecmd->transceiver = XCVR_INTERNAL;
1774
1775 if (adapter->link_speed != SPEED_0) {
1776 ecmd->speed = adapter->link_speed;
1777 if (adapter->link_duplex == FULL_DUPLEX)
1778 ecmd->duplex = DUPLEX_FULL;
1779 else
1780 ecmd->duplex = DUPLEX_HALF;
1781 } else {
1782 ecmd->speed = -1;
1783 ecmd->duplex = -1;
1784 }
1785
1786 ecmd->autoneg = AUTONEG_ENABLE;
1787 return 0;
1788}
1789
1790static int atl2_set_settings(struct net_device *netdev,
1791 struct ethtool_cmd *ecmd)
1792{
1793 struct atl2_adapter *adapter = netdev_priv(netdev);
1794 struct atl2_hw *hw = &adapter->hw;
1795
1796 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1797 msleep(1);
1798
1799 if (ecmd->autoneg == AUTONEG_ENABLE) {
1800#define MY_ADV_MASK (ADVERTISE_10_HALF | \
1801 ADVERTISE_10_FULL | \
1802 ADVERTISE_100_HALF| \
1803 ADVERTISE_100_FULL)
1804
1805 if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) {
1806 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR;
1807 hw->autoneg_advertised = MY_ADV_MASK;
1808 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1809 ADVERTISE_100_FULL) {
1810 hw->MediaType = MEDIA_TYPE_100M_FULL;
1811 hw->autoneg_advertised = ADVERTISE_100_FULL;
1812 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1813 ADVERTISE_100_HALF) {
1814 hw->MediaType = MEDIA_TYPE_100M_HALF;
1815 hw->autoneg_advertised = ADVERTISE_100_HALF;
1816 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1817 ADVERTISE_10_FULL) {
1818 hw->MediaType = MEDIA_TYPE_10M_FULL;
1819 hw->autoneg_advertised = ADVERTISE_10_FULL;
1820 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1821 ADVERTISE_10_HALF) {
1822 hw->MediaType = MEDIA_TYPE_10M_HALF;
1823 hw->autoneg_advertised = ADVERTISE_10_HALF;
1824 } else {
1825 clear_bit(__ATL2_RESETTING, &adapter->flags);
1826 return -EINVAL;
1827 }
1828 ecmd->advertising = hw->autoneg_advertised |
1829 ADVERTISED_TP | ADVERTISED_Autoneg;
1830 } else {
1831 clear_bit(__ATL2_RESETTING, &adapter->flags);
1832 return -EINVAL;
1833 }
1834
1835 /* reset the link */
1836 if (netif_running(adapter->netdev)) {
1837 atl2_down(adapter);
1838 atl2_up(adapter);
1839 } else
1840 atl2_reset_hw(&adapter->hw);
1841
1842 clear_bit(__ATL2_RESETTING, &adapter->flags);
1843 return 0;
1844}
1845
1846static u32 atl2_get_tx_csum(struct net_device *netdev)
1847{
1848 return (netdev->features & NETIF_F_HW_CSUM) != 0;
1849}
1850
1851static u32 atl2_get_msglevel(struct net_device *netdev)
1852{
1853 return 0;
1854}
1855
1856/*
1857 * It's sane for this to be empty, but we might want to take advantage of this.
1858 */
1859static void atl2_set_msglevel(struct net_device *netdev, u32 data)
1860{
1861}
1862
1863static int atl2_get_regs_len(struct net_device *netdev)
1864{
1865#define ATL2_REGS_LEN 42
1866 return sizeof(u32) * ATL2_REGS_LEN;
1867}
1868
1869static void atl2_get_regs(struct net_device *netdev,
1870 struct ethtool_regs *regs, void *p)
1871{
1872 struct atl2_adapter *adapter = netdev_priv(netdev);
1873 struct atl2_hw *hw = &adapter->hw;
1874 u32 *regs_buff = p;
1875 u16 phy_data;
1876
1877 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN);
1878
1879 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
1880
1881 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP);
1882 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
1883 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG);
1884 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL);
1885 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
1886 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL);
1887 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT);
1888 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
1889 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE);
1890 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER);
1891 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS);
1892 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL);
1893 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK);
1894 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL);
1895 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG);
1896 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
1897 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4);
1898 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE);
1899 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4);
1900 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
1901 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU);
1902 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL);
1903 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END);
1904 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI);
1905 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO);
1906 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE);
1907 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO);
1908 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE);
1909 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO);
1910 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM);
1911 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR);
1912 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH);
1913 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW);
1914 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH);
1915 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH);
1916 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX);
1917 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX);
1918 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR);
1919 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR);
1920
1921 atl2_read_phy_reg(hw, MII_BMCR, &phy_data);
1922 regs_buff[40] = (u32)phy_data;
1923 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1924 regs_buff[41] = (u32)phy_data;
1925}
1926
1927static int atl2_get_eeprom_len(struct net_device *netdev)
1928{
1929 struct atl2_adapter *adapter = netdev_priv(netdev);
1930
1931 if (!atl2_check_eeprom_exist(&adapter->hw))
1932 return 512;
1933 else
1934 return 0;
1935}
1936
1937static int atl2_get_eeprom(struct net_device *netdev,
1938 struct ethtool_eeprom *eeprom, u8 *bytes)
1939{
1940 struct atl2_adapter *adapter = netdev_priv(netdev);
1941 struct atl2_hw *hw = &adapter->hw;
1942 u32 *eeprom_buff;
1943 int first_dword, last_dword;
1944 int ret_val = 0;
1945 int i;
1946
1947 if (eeprom->len == 0)
1948 return -EINVAL;
1949
1950 if (atl2_check_eeprom_exist(hw))
1951 return -EINVAL;
1952
1953 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1954
1955 first_dword = eeprom->offset >> 2;
1956 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1957
1958 eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1),
1959 GFP_KERNEL);
1960 if (!eeprom_buff)
1961 return -ENOMEM;
1962
1963 for (i = first_dword; i < last_dword; i++) {
1964 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword])))
1965 return -EIO;
1966 }
1967
1968 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
1969 eeprom->len);
1970 kfree(eeprom_buff);
1971
1972 return ret_val;
1973}
1974
1975static int atl2_set_eeprom(struct net_device *netdev,
1976 struct ethtool_eeprom *eeprom, u8 *bytes)
1977{
1978 struct atl2_adapter *adapter = netdev_priv(netdev);
1979 struct atl2_hw *hw = &adapter->hw;
1980 u32 *eeprom_buff;
1981 u32 *ptr;
1982 int max_len, first_dword, last_dword, ret_val = 0;
1983 int i;
1984
1985 if (eeprom->len == 0)
1986 return -EOPNOTSUPP;
1987
1988 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
1989 return -EFAULT;
1990
1991 max_len = 512;
1992
1993 first_dword = eeprom->offset >> 2;
1994 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1995 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
1996 if (!eeprom_buff)
1997 return -ENOMEM;
1998
1999 ptr = (u32 *)eeprom_buff;
2000
2001 if (eeprom->offset & 3) {
2002 /* need read/modify/write of first changed EEPROM word */
2003 /* only the second byte of the word is being modified */
2004 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0])))
2005 return -EIO;
2006 ptr++;
2007 }
2008 if (((eeprom->offset + eeprom->len) & 3)) {
2009 /*
2010 * need read/modify/write of last changed EEPROM word
2011 * only the first byte of the word is being modified
2012 */
2013 if (!atl2_read_eeprom(hw, last_dword * 4,
2014 &(eeprom_buff[last_dword - first_dword])))
2015 return -EIO;
2016 }
2017
2018 /* Device's eeprom is always little-endian, word addressable */
2019 memcpy(ptr, bytes, eeprom->len);
2020
2021 for (i = 0; i < last_dword - first_dword + 1; i++) {
2022 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i]))
2023 return -EIO;
2024 }
2025
2026 kfree(eeprom_buff);
2027 return ret_val;
2028}
2029
2030static void atl2_get_drvinfo(struct net_device *netdev,
2031 struct ethtool_drvinfo *drvinfo)
2032{
2033 struct atl2_adapter *adapter = netdev_priv(netdev);
2034
2035 strncpy(drvinfo->driver, atl2_driver_name, 32);
2036 strncpy(drvinfo->version, atl2_driver_version, 32);
2037 strncpy(drvinfo->fw_version, "L2", 32);
2038 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
2039 drvinfo->n_stats = 0;
2040 drvinfo->testinfo_len = 0;
2041 drvinfo->regdump_len = atl2_get_regs_len(netdev);
2042 drvinfo->eedump_len = atl2_get_eeprom_len(netdev);
2043}
2044
2045static void atl2_get_wol(struct net_device *netdev,
2046 struct ethtool_wolinfo *wol)
2047{
2048 struct atl2_adapter *adapter = netdev_priv(netdev);
2049
2050 wol->supported = WAKE_MAGIC;
2051 wol->wolopts = 0;
2052
2053 if (adapter->wol & ATLX_WUFC_EX)
2054 wol->wolopts |= WAKE_UCAST;
2055 if (adapter->wol & ATLX_WUFC_MC)
2056 wol->wolopts |= WAKE_MCAST;
2057 if (adapter->wol & ATLX_WUFC_BC)
2058 wol->wolopts |= WAKE_BCAST;
2059 if (adapter->wol & ATLX_WUFC_MAG)
2060 wol->wolopts |= WAKE_MAGIC;
2061 if (adapter->wol & ATLX_WUFC_LNKC)
2062 wol->wolopts |= WAKE_PHY;
2063}
2064
2065static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2066{
2067 struct atl2_adapter *adapter = netdev_priv(netdev);
2068
2069 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2070 return -EOPNOTSUPP;
2071
2072 if (wol->wolopts & (WAKE_MCAST|WAKE_BCAST|WAKE_MCAST))
2073 return -EOPNOTSUPP;
2074
2075 /* these settings will always override what we currently have */
2076 adapter->wol = 0;
2077
2078 if (wol->wolopts & WAKE_MAGIC)
2079 adapter->wol |= ATLX_WUFC_MAG;
2080 if (wol->wolopts & WAKE_PHY)
2081 adapter->wol |= ATLX_WUFC_LNKC;
2082
2083 return 0;
2084}
2085
2086static int atl2_nway_reset(struct net_device *netdev)
2087{
2088 struct atl2_adapter *adapter = netdev_priv(netdev);
2089 if (netif_running(netdev))
2090 atl2_reinit_locked(adapter);
2091 return 0;
2092}
2093
2094static struct ethtool_ops atl2_ethtool_ops = {
2095 .get_settings = atl2_get_settings,
2096 .set_settings = atl2_set_settings,
2097 .get_drvinfo = atl2_get_drvinfo,
2098 .get_regs_len = atl2_get_regs_len,
2099 .get_regs = atl2_get_regs,
2100 .get_wol = atl2_get_wol,
2101 .set_wol = atl2_set_wol,
2102 .get_msglevel = atl2_get_msglevel,
2103 .set_msglevel = atl2_set_msglevel,
2104 .nway_reset = atl2_nway_reset,
2105 .get_link = ethtool_op_get_link,
2106 .get_eeprom_len = atl2_get_eeprom_len,
2107 .get_eeprom = atl2_get_eeprom,
2108 .set_eeprom = atl2_set_eeprom,
2109 .get_tx_csum = atl2_get_tx_csum,
2110 .get_sg = ethtool_op_get_sg,
2111 .set_sg = ethtool_op_set_sg,
2112#ifdef NETIF_F_TSO
2113 .get_tso = ethtool_op_get_tso,
2114#endif
2115};
2116
2117static void atl2_set_ethtool_ops(struct net_device *netdev)
2118{
2119 SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops);
2120}
2121
2122#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
2123 (((a) & 0xff00ff00) >> 8))
2124#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
2125#define SHORTSWAP(a) (((a) << 8) | ((a) >> 8))
2126
2127/*
2128 * Reset the transmit and receive units; mask and clear all interrupts.
2129 *
2130 * hw - Struct containing variables accessed by shared code
2131 * return : 0 or idle status (if error)
2132 */
2133static s32 atl2_reset_hw(struct atl2_hw *hw)
2134{
2135 u32 icr;
2136 u16 pci_cfg_cmd_word;
2137 int i;
2138
2139 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
2140 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2141 if ((pci_cfg_cmd_word &
2142 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) !=
2143 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) {
2144 pci_cfg_cmd_word |=
2145 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER);
2146 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2147 }
2148
2149 /* Clear Interrupt mask to stop board from generating
2150 * interrupts & Clear any pending interrupt events
2151 */
2152 /* FIXME */
2153 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */
2154 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */
2155
2156 /* Issue Soft Reset to the MAC. This will reset the chip's
2157 * transmit, receive, DMA. It will not effect
2158 * the current PCI configuration. The global reset bit is self-
2159 * clearing, and should clear within a microsecond.
2160 */
2161 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
2162 wmb();
2163 msleep(1); /* delay about 1ms */
2164
2165 /* Wait at least 10ms for All module to be Idle */
2166 for (i = 0; i < 10; i++) {
2167 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS);
2168 if (!icr)
2169 break;
2170 msleep(1); /* delay 1 ms */
2171 cpu_relax();
2172 }
2173
2174 if (icr)
2175 return icr;
2176
2177 return 0;
2178}
2179
2180#define CUSTOM_SPI_CS_SETUP 2
2181#define CUSTOM_SPI_CLK_HI 2
2182#define CUSTOM_SPI_CLK_LO 2
2183#define CUSTOM_SPI_CS_HOLD 2
2184#define CUSTOM_SPI_CS_HI 3
2185
2186static struct atl2_spi_flash_dev flash_table[] =
2187{
2188/* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
2189{"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 },
2190{"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 },
2191{"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 },
2192};
2193
2194static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf)
2195{
2196 int i;
2197 u32 value;
2198
2199 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);
2200 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);
2201
2202 value = SPI_FLASH_CTRL_WAIT_READY |
2203 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
2204 SPI_FLASH_CTRL_CS_SETUP_SHIFT |
2205 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) <<
2206 SPI_FLASH_CTRL_CLK_HI_SHIFT |
2207 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) <<
2208 SPI_FLASH_CTRL_CLK_LO_SHIFT |
2209 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) <<
2210 SPI_FLASH_CTRL_CS_HOLD_SHIFT |
2211 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) <<
2212 SPI_FLASH_CTRL_CS_HI_SHIFT |
2213 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT;
2214
2215 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2216
2217 value |= SPI_FLASH_CTRL_START;
2218
2219 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2220
2221 for (i = 0; i < 10; i++) {
2222 msleep(1);
2223 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2224 if (!(value & SPI_FLASH_CTRL_START))
2225 break;
2226 }
2227
2228 if (value & SPI_FLASH_CTRL_START)
2229 return false;
2230
2231 *buf = ATL2_READ_REG(hw, REG_SPI_DATA);
2232
2233 return true;
2234}
2235
2236/*
2237 * get_permanent_address
2238 * return 0 if get valid mac address,
2239 */
2240static int get_permanent_address(struct atl2_hw *hw)
2241{
2242 u32 Addr[2];
2243 u32 i, Control;
2244 u16 Register;
2245 u8 EthAddr[NODE_ADDRESS_SIZE];
2246 bool KeyValid;
2247
2248 if (is_valid_ether_addr(hw->perm_mac_addr))
2249 return 0;
2250
2251 Addr[0] = 0;
2252 Addr[1] = 0;
2253
2254 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */
2255 Register = 0;
2256 KeyValid = false;
2257
2258 /* Read out all EEPROM content */
2259 i = 0;
2260 while (1) {
2261 if (atl2_read_eeprom(hw, i + 0x100, &Control)) {
2262 if (KeyValid) {
2263 if (Register == REG_MAC_STA_ADDR)
2264 Addr[0] = Control;
2265 else if (Register ==
2266 (REG_MAC_STA_ADDR + 4))
2267 Addr[1] = Control;
2268 KeyValid = false;
2269 } else if ((Control & 0xff) == 0x5A) {
2270 KeyValid = true;
2271 Register = (u16) (Control >> 16);
2272 } else {
2273 /* assume data end while encount an invalid KEYWORD */
2274 break;
2275 }
2276 } else {
2277 break; /* read error */
2278 }
2279 i += 4;
2280 }
2281
2282 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2283 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2284
2285 if (is_valid_ether_addr(EthAddr)) {
2286 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2287 return 0;
2288 }
2289 return 1;
2290 }
2291
2292 /* see if SPI flash exists? */
2293 Addr[0] = 0;
2294 Addr[1] = 0;
2295 Register = 0;
2296 KeyValid = false;
2297 i = 0;
2298 while (1) {
2299 if (atl2_spi_read(hw, i + 0x1f000, &Control)) {
2300 if (KeyValid) {
2301 if (Register == REG_MAC_STA_ADDR)
2302 Addr[0] = Control;
2303 else if (Register == (REG_MAC_STA_ADDR + 4))
2304 Addr[1] = Control;
2305 KeyValid = false;
2306 } else if ((Control & 0xff) == 0x5A) {
2307 KeyValid = true;
2308 Register = (u16) (Control >> 16);
2309 } else {
2310 break; /* data end */
2311 }
2312 } else {
2313 break; /* read error */
2314 }
2315 i += 4;
2316 }
2317
2318 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2319 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]);
2320 if (is_valid_ether_addr(EthAddr)) {
2321 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2322 return 0;
2323 }
2324 /* maybe MAC-address is from BIOS */
2325 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
2326 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4);
2327 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2328 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2329
2330 if (is_valid_ether_addr(EthAddr)) {
2331 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2332 return 0;
2333 }
2334
2335 return 1;
2336}
2337
2338/*
2339 * Reads the adapter's MAC address from the EEPROM
2340 *
2341 * hw - Struct containing variables accessed by shared code
2342 */
2343static s32 atl2_read_mac_addr(struct atl2_hw *hw)
2344{
2345 u16 i;
2346
2347 if (get_permanent_address(hw)) {
2348 /* for test */
2349 /* FIXME: shouldn't we use random_ether_addr() here? */
2350 hw->perm_mac_addr[0] = 0x00;
2351 hw->perm_mac_addr[1] = 0x13;
2352 hw->perm_mac_addr[2] = 0x74;
2353 hw->perm_mac_addr[3] = 0x00;
2354 hw->perm_mac_addr[4] = 0x5c;
2355 hw->perm_mac_addr[5] = 0x38;
2356 }
2357
2358 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
2359 hw->mac_addr[i] = hw->perm_mac_addr[i];
2360
2361 return 0;
2362}
2363
2364/*
2365 * Hashes an address to determine its location in the multicast table
2366 *
2367 * hw - Struct containing variables accessed by shared code
2368 * mc_addr - the multicast address to hash
2369 *
2370 * atl2_hash_mc_addr
2371 * purpose
2372 * set hash value for a multicast address
2373 * hash calcu processing :
2374 * 1. calcu 32bit CRC for multicast address
2375 * 2. reverse crc with MSB to LSB
2376 */
2377static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr)
2378{
2379 u32 crc32, value;
2380 int i;
2381
2382 value = 0;
2383 crc32 = ether_crc_le(6, mc_addr);
2384
2385 for (i = 0; i < 32; i++)
2386 value |= (((crc32 >> i) & 1) << (31 - i));
2387
2388 return value;
2389}
2390
2391/*
2392 * Sets the bit in the multicast table corresponding to the hash value.
2393 *
2394 * hw - Struct containing variables accessed by shared code
2395 * hash_value - Multicast address hash value
2396 */
2397static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value)
2398{
2399 u32 hash_bit, hash_reg;
2400 u32 mta;
2401
2402 /* The HASH Table is a register array of 2 32-bit registers.
2403 * It is treated like an array of 64 bits. We want to set
2404 * bit BitArray[hash_value]. So we figure out what register
2405 * the bit is in, read it, OR in the new bit, then write
2406 * back the new value. The register is determined by the
2407 * upper 7 bits of the hash value and the bit within that
2408 * register are determined by the lower 5 bits of the value.
2409 */
2410 hash_reg = (hash_value >> 31) & 0x1;
2411 hash_bit = (hash_value >> 26) & 0x1F;
2412
2413 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
2414
2415 mta |= (1 << hash_bit);
2416
2417 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
2418}
2419
2420/*
2421 * atl2_init_pcie - init PCIE module
2422 */
2423static void atl2_init_pcie(struct atl2_hw *hw)
2424{
2425 u32 value;
2426 value = LTSSM_TEST_MODE_DEF;
2427 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
2428
2429 value = PCIE_DLL_TX_CTRL1_DEF;
2430 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);
2431}
2432
2433static void atl2_init_flash_opcode(struct atl2_hw *hw)
2434{
2435 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
2436 hw->flash_vendor = 0; /* ATMEL */
2437
2438 /* Init OP table */
2439 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM,
2440 flash_table[hw->flash_vendor].cmdPROGRAM);
2441 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE,
2442 flash_table[hw->flash_vendor].cmdSECTOR_ERASE);
2443 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE,
2444 flash_table[hw->flash_vendor].cmdCHIP_ERASE);
2445 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID,
2446 flash_table[hw->flash_vendor].cmdRDID);
2447 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN,
2448 flash_table[hw->flash_vendor].cmdWREN);
2449 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR,
2450 flash_table[hw->flash_vendor].cmdRDSR);
2451 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR,
2452 flash_table[hw->flash_vendor].cmdWRSR);
2453 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ,
2454 flash_table[hw->flash_vendor].cmdREAD);
2455}
2456
2457/********************************************************************
2458* Performs basic configuration of the adapter.
2459*
2460* hw - Struct containing variables accessed by shared code
2461* Assumes that the controller has previously been reset and is in a
2462* post-reset uninitialized state. Initializes multicast table,
2463* and Calls routines to setup link
2464* Leaves the transmit and receive units disabled and uninitialized.
2465********************************************************************/
2466static s32 atl2_init_hw(struct atl2_hw *hw)
2467{
2468 u32 ret_val = 0;
2469
2470 atl2_init_pcie(hw);
2471
2472 /* Zero out the Multicast HASH table */
2473 /* clear the old settings from the multicast hash table */
2474 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
2475 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
2476
2477 atl2_init_flash_opcode(hw);
2478
2479 ret_val = atl2_phy_init(hw);
2480
2481 return ret_val;
2482}
2483
2484/*
2485 * Detects the current speed and duplex settings of the hardware.
2486 *
2487 * hw - Struct containing variables accessed by shared code
2488 * speed - Speed of the connection
2489 * duplex - Duplex setting of the connection
2490 */
2491static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
2492 u16 *duplex)
2493{
2494 s32 ret_val;
2495 u16 phy_data;
2496
2497 /* Read PHY Specific Status Register (17) */
2498 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
2499 if (ret_val)
2500 return ret_val;
2501
2502 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
2503 return ATLX_ERR_PHY_RES;
2504
2505 switch (phy_data & MII_ATLX_PSSR_SPEED) {
2506 case MII_ATLX_PSSR_100MBS:
2507 *speed = SPEED_100;
2508 break;
2509 case MII_ATLX_PSSR_10MBS:
2510 *speed = SPEED_10;
2511 break;
2512 default:
2513 return ATLX_ERR_PHY_SPEED;
2514 break;
2515 }
2516
2517 if (phy_data & MII_ATLX_PSSR_DPLX)
2518 *duplex = FULL_DUPLEX;
2519 else
2520 *duplex = HALF_DUPLEX;
2521
2522 return 0;
2523}
2524
2525/*
2526 * Reads the value from a PHY register
2527 * hw - Struct containing variables accessed by shared code
2528 * reg_addr - address of the PHY register to read
2529 */
2530static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data)
2531{
2532 u32 val;
2533 int i;
2534
2535 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
2536 MDIO_START |
2537 MDIO_SUP_PREAMBLE |
2538 MDIO_RW |
2539 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2540 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2541
2542 wmb();
2543
2544 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2545 udelay(2);
2546 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2547 if (!(val & (MDIO_START | MDIO_BUSY)))
2548 break;
2549 wmb();
2550 }
2551 if (!(val & (MDIO_START | MDIO_BUSY))) {
2552 *phy_data = (u16)val;
2553 return 0;
2554 }
2555
2556 return ATLX_ERR_PHY;
2557}
2558
2559/*
2560 * Writes a value to a PHY register
2561 * hw - Struct containing variables accessed by shared code
2562 * reg_addr - address of the PHY register to write
2563 * data - data to write to the PHY
2564 */
2565static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data)
2566{
2567 int i;
2568 u32 val;
2569
2570 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
2571 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
2572 MDIO_SUP_PREAMBLE |
2573 MDIO_START |
2574 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2575 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2576
2577 wmb();
2578
2579 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2580 udelay(2);
2581 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2582 if (!(val & (MDIO_START | MDIO_BUSY)))
2583 break;
2584
2585 wmb();
2586 }
2587
2588 if (!(val & (MDIO_START | MDIO_BUSY)))
2589 return 0;
2590
2591 return ATLX_ERR_PHY;
2592}
2593
2594/*
2595 * Configures PHY autoneg and flow control advertisement settings
2596 *
2597 * hw - Struct containing variables accessed by shared code
2598 */
2599static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw)
2600{
2601 s32 ret_val;
2602 s16 mii_autoneg_adv_reg;
2603
2604 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2605 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
2606
2607 /* Need to parse autoneg_advertised and set up
2608 * the appropriate PHY registers. First we will parse for
2609 * autoneg_advertised software override. Since we can advertise
2610 * a plethora of combinations, we need to check each bit
2611 * individually.
2612 */
2613
2614 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2615 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2616 * the 1000Base-T Control Register (Address 9). */
2617 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
2618
2619 /* Need to parse MediaType and setup the
2620 * appropriate PHY registers. */
2621 switch (hw->MediaType) {
2622 case MEDIA_TYPE_AUTO_SENSOR:
2623 mii_autoneg_adv_reg |=
2624 (MII_AR_10T_HD_CAPS |
2625 MII_AR_10T_FD_CAPS |
2626 MII_AR_100TX_HD_CAPS|
2627 MII_AR_100TX_FD_CAPS);
2628 hw->autoneg_advertised =
2629 ADVERTISE_10_HALF |
2630 ADVERTISE_10_FULL |
2631 ADVERTISE_100_HALF|
2632 ADVERTISE_100_FULL;
2633 break;
2634 case MEDIA_TYPE_100M_FULL:
2635 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
2636 hw->autoneg_advertised = ADVERTISE_100_FULL;
2637 break;
2638 case MEDIA_TYPE_100M_HALF:
2639 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
2640 hw->autoneg_advertised = ADVERTISE_100_HALF;
2641 break;
2642 case MEDIA_TYPE_10M_FULL:
2643 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
2644 hw->autoneg_advertised = ADVERTISE_10_FULL;
2645 break;
2646 default:
2647 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
2648 hw->autoneg_advertised = ADVERTISE_10_HALF;
2649 break;
2650 }
2651
2652 /* flow control fixed to enable all */
2653 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
2654
2655 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
2656
2657 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
2658
2659 if (ret_val)
2660 return ret_val;
2661
2662 return 0;
2663}
2664
2665/*
2666 * Resets the PHY and make all config validate
2667 *
2668 * hw - Struct containing variables accessed by shared code
2669 *
2670 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
2671 */
2672static s32 atl2_phy_commit(struct atl2_hw *hw)
2673{
2674 s32 ret_val;
2675 u16 phy_data;
2676
2677 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2678 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data);
2679 if (ret_val) {
2680 u32 val;
2681 int i;
2682 /* pcie serdes link may be down ! */
2683 for (i = 0; i < 25; i++) {
2684 msleep(1);
2685 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2686 if (!(val & (MDIO_START | MDIO_BUSY)))
2687 break;
2688 }
2689
2690 if (0 != (val & (MDIO_START | MDIO_BUSY))) {
2691 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n");
2692 return ret_val;
2693 }
2694 }
2695 return 0;
2696}
2697
2698static s32 atl2_phy_init(struct atl2_hw *hw)
2699{
2700 s32 ret_val;
2701 u16 phy_val;
2702
2703 if (hw->phy_configured)
2704 return 0;
2705
2706 /* Enable PHY */
2707 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1);
2708 ATL2_WRITE_FLUSH(hw);
2709 msleep(1);
2710
2711 /* check if the PHY is in powersaving mode */
2712 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2713 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2714
2715 /* 024E / 124E 0r 0274 / 1274 ? */
2716 if (phy_val & 0x1000) {
2717 phy_val &= ~0x1000;
2718 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val);
2719 }
2720
2721 msleep(1);
2722
2723 /*Enable PHY LinkChange Interrupt */
2724 ret_val = atl2_write_phy_reg(hw, 18, 0xC00);
2725 if (ret_val)
2726 return ret_val;
2727
2728 /* setup AutoNeg parameters */
2729 ret_val = atl2_phy_setup_autoneg_adv(hw);
2730 if (ret_val)
2731 return ret_val;
2732
2733 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */
2734 ret_val = atl2_phy_commit(hw);
2735 if (ret_val)
2736 return ret_val;
2737
2738 hw->phy_configured = true;
2739
2740 return ret_val;
2741}
2742
2743static void atl2_set_mac_addr(struct atl2_hw *hw)
2744{
2745 u32 value;
2746 /* 00-0B-6A-F6-00-DC
2747 * 0: 6AF600DC 1: 000B
2748 * low dword */
2749 value = (((u32)hw->mac_addr[2]) << 24) |
2750 (((u32)hw->mac_addr[3]) << 16) |
2751 (((u32)hw->mac_addr[4]) << 8) |
2752 (((u32)hw->mac_addr[5]));
2753 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
2754 /* hight dword */
2755 value = (((u32)hw->mac_addr[0]) << 8) |
2756 (((u32)hw->mac_addr[1]));
2757 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
2758}
2759
2760/*
2761 * check_eeprom_exist
2762 * return 0 if eeprom exist
2763 */
2764static int atl2_check_eeprom_exist(struct atl2_hw *hw)
2765{
2766 u32 value;
2767
2768 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2769 if (value & SPI_FLASH_CTRL_EN_VPD) {
2770 value &= ~SPI_FLASH_CTRL_EN_VPD;
2771 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2772 }
2773 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST);
2774 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
2775}
2776
2777/* FIXME: This doesn't look right. -- CHS */
2778static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value)
2779{
2780 return true;
2781}
2782
2783static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue)
2784{
2785 int i;
2786 u32 Control;
2787
2788 if (Offset & 0x3)
2789 return false; /* address do not align */
2790
2791 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);
2792 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
2793 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);
2794
2795 for (i = 0; i < 10; i++) {
2796 msleep(2);
2797 Control = ATL2_READ_REG(hw, REG_VPD_CAP);
2798 if (Control & VPD_CAP_VPD_FLAG)
2799 break;
2800 }
2801
2802 if (Control & VPD_CAP_VPD_FLAG) {
2803 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA);
2804 return true;
2805 }
2806 return false; /* timeout */
2807}
2808
2809static void atl2_force_ps(struct atl2_hw *hw)
2810{
2811 u16 phy_val;
2812
2813 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2814 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2815 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000);
2816
2817 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2);
2818 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
2819 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3);
2820 atl2_write_phy_reg(hw, MII_DBG_DATA, 0);
2821}
2822
2823/* This is the only thing that needs to be changed to adjust the
2824 * maximum number of ports that the driver can manage.
2825 */
2826#define ATL2_MAX_NIC 4
2827
2828#define OPTION_UNSET -1
2829#define OPTION_DISABLED 0
2830#define OPTION_ENABLED 1
2831
2832/* All parameters are treated the same, as an integer array of values.
2833 * This macro just reduces the need to repeat the same declaration code
2834 * over and over (plus this helps to avoid typo bugs).
2835 */
2836#define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET}
2837#ifndef module_param_array
2838/* Module Parameters are always initialized to -1, so that the driver
2839 * can tell the difference between no user specified value or the
2840 * user asking for the default value.
2841 * The true default values are loaded in when atl2_check_options is called.
2842 *
2843 * This is a GCC extension to ANSI C.
2844 * See the item "Labeled Elements in Initializers" in the section
2845 * "Extensions to the C Language Family" of the GCC documentation.
2846 */
2847
2848#define ATL2_PARAM(X, desc) \
2849 static const int __devinitdata X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \
2850 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \
2851 MODULE_PARM_DESC(X, desc);
2852#else
2853#define ATL2_PARAM(X, desc) \
2854 static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \
2855 static int num_##X = 0; \
2856 module_param_array_named(X, X, int, &num_##X, 0); \
2857 MODULE_PARM_DESC(X, desc);
2858#endif
2859
2860/*
2861 * Transmit Memory Size
2862 * Valid Range: 64-2048
2863 * Default Value: 128
2864 */
2865#define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */
2866#define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */
2867#define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */
2868ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory");
2869
2870/*
2871 * Receive Memory Block Count
2872 * Valid Range: 16-512
2873 * Default Value: 128
2874 */
2875#define ATL2_MIN_RXD_COUNT 16
2876#define ATL2_MAX_RXD_COUNT 512
2877#define ATL2_DEFAULT_RXD_COUNT 64
2878ATL2_PARAM(RxMemBlock, "Number of receive memory block");
2879
2880/*
2881 * User Specified MediaType Override
2882 *
2883 * Valid Range: 0-5
2884 * - 0 - auto-negotiate at all supported speeds
2885 * - 1 - only link at 1000Mbps Full Duplex
2886 * - 2 - only link at 100Mbps Full Duplex
2887 * - 3 - only link at 100Mbps Half Duplex
2888 * - 4 - only link at 10Mbps Full Duplex
2889 * - 5 - only link at 10Mbps Half Duplex
2890 * Default Value: 0
2891 */
2892ATL2_PARAM(MediaType, "MediaType Select");
2893
2894/*
2895 * Interrupt Moderate Timer in units of 2048 ns (~2 us)
2896 * Valid Range: 10-65535
2897 * Default Value: 45000(90ms)
2898 */
2899#define INT_MOD_DEFAULT_CNT 100 /* 200us */
2900#define INT_MOD_MAX_CNT 65000
2901#define INT_MOD_MIN_CNT 50
2902ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer");
2903
2904/*
2905 * FlashVendor
2906 * Valid Range: 0-2
2907 * 0 - Atmel
2908 * 1 - SST
2909 * 2 - ST
2910 */
2911ATL2_PARAM(FlashVendor, "SPI Flash Vendor");
2912
2913#define AUTONEG_ADV_DEFAULT 0x2F
2914#define AUTONEG_ADV_MASK 0x2F
2915#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
2916
2917#define FLASH_VENDOR_DEFAULT 0
2918#define FLASH_VENDOR_MIN 0
2919#define FLASH_VENDOR_MAX 2
2920
2921struct atl2_option {
2922 enum { enable_option, range_option, list_option } type;
2923 char *name;
2924 char *err;
2925 int def;
2926 union {
2927 struct { /* range_option info */
2928 int min;
2929 int max;
2930 } r;
2931 struct { /* list_option info */
2932 int nr;
2933 struct atl2_opt_list { int i; char *str; } *p;
2934 } l;
2935 } arg;
2936};
2937
2938static int __devinit atl2_validate_option(int *value, struct atl2_option *opt)
2939{
2940 int i;
2941 struct atl2_opt_list *ent;
2942
2943 if (*value == OPTION_UNSET) {
2944 *value = opt->def;
2945 return 0;
2946 }
2947
2948 switch (opt->type) {
2949 case enable_option:
2950 switch (*value) {
2951 case OPTION_ENABLED:
2952 printk(KERN_INFO "%s Enabled\n", opt->name);
2953 return 0;
2954 break;
2955 case OPTION_DISABLED:
2956 printk(KERN_INFO "%s Disabled\n", opt->name);
2957 return 0;
2958 break;
2959 }
2960 break;
2961 case range_option:
2962 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
2963 printk(KERN_INFO "%s set to %i\n", opt->name, *value);
2964 return 0;
2965 }
2966 break;
2967 case list_option:
2968 for (i = 0; i < opt->arg.l.nr; i++) {
2969 ent = &opt->arg.l.p[i];
2970 if (*value == ent->i) {
2971 if (ent->str[0] != '\0')
2972 printk(KERN_INFO "%s\n", ent->str);
2973 return 0;
2974 }
2975 }
2976 break;
2977 default:
2978 BUG();
2979 }
2980
2981 printk(KERN_INFO "Invalid %s specified (%i) %s\n",
2982 opt->name, *value, opt->err);
2983 *value = opt->def;
2984 return -1;
2985}
2986
2987/*
2988 * atl2_check_options - Range Checking for Command Line Parameters
2989 * @adapter: board private structure
2990 *
2991 * This routine checks all command line parameters for valid user
2992 * input. If an invalid value is given, or if no user specified
2993 * value exists, a default value is used. The final value is stored
2994 * in a variable in the adapter structure.
2995 */
2996static void __devinit atl2_check_options(struct atl2_adapter *adapter)
2997{
2998 int val;
2999 struct atl2_option opt;
3000 int bd = adapter->bd_number;
3001 if (bd >= ATL2_MAX_NIC) {
3002 printk(KERN_NOTICE "Warning: no configuration for board #%i\n",
3003 bd);
3004 printk(KERN_NOTICE "Using defaults for all values\n");
3005#ifndef module_param_array
3006 bd = ATL2_MAX_NIC;
3007#endif
3008 }
3009
3010 /* Bytes of Transmit Memory */
3011 opt.type = range_option;
3012 opt.name = "Bytes of Transmit Memory";
3013 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE);
3014 opt.def = ATL2_DEFAULT_TX_MEMSIZE;
3015 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE;
3016 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE;
3017#ifdef module_param_array
3018 if (num_TxMemSize > bd) {
3019#endif
3020 val = TxMemSize[bd];
3021 atl2_validate_option(&val, &opt);
3022 adapter->txd_ring_size = ((u32) val) * 1024;
3023#ifdef module_param_array
3024 } else
3025 adapter->txd_ring_size = ((u32)opt.def) * 1024;
3026#endif
3027 /* txs ring size: */
3028 adapter->txs_ring_size = adapter->txd_ring_size / 128;
3029 if (adapter->txs_ring_size > 160)
3030 adapter->txs_ring_size = 160;
3031
3032 /* Receive Memory Block Count */
3033 opt.type = range_option;
3034 opt.name = "Number of receive memory block";
3035 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT);
3036 opt.def = ATL2_DEFAULT_RXD_COUNT;
3037 opt.arg.r.min = ATL2_MIN_RXD_COUNT;
3038 opt.arg.r.max = ATL2_MAX_RXD_COUNT;
3039#ifdef module_param_array
3040 if (num_RxMemBlock > bd) {
3041#endif
3042 val = RxMemBlock[bd];
3043 atl2_validate_option(&val, &opt);
3044 adapter->rxd_ring_size = (u32)val;
3045 /* FIXME */
3046 /* ((u16)val)&~1; */ /* even number */
3047#ifdef module_param_array
3048 } else
3049 adapter->rxd_ring_size = (u32)opt.def;
3050#endif
3051 /* init RXD Flow control value */
3052 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7;
3053 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) >
3054 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) :
3055 (adapter->rxd_ring_size / 12);
3056
3057 /* Interrupt Moderate Timer */
3058 opt.type = range_option;
3059 opt.name = "Interrupt Moderate Timer";
3060 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT);
3061 opt.def = INT_MOD_DEFAULT_CNT;
3062 opt.arg.r.min = INT_MOD_MIN_CNT;
3063 opt.arg.r.max = INT_MOD_MAX_CNT;
3064#ifdef module_param_array
3065 if (num_IntModTimer > bd) {
3066#endif
3067 val = IntModTimer[bd];
3068 atl2_validate_option(&val, &opt);
3069 adapter->imt = (u16) val;
3070#ifdef module_param_array
3071 } else
3072 adapter->imt = (u16)(opt.def);
3073#endif
3074 /* Flash Vendor */
3075 opt.type = range_option;
3076 opt.name = "SPI Flash Vendor";
3077 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT);
3078 opt.def = FLASH_VENDOR_DEFAULT;
3079 opt.arg.r.min = FLASH_VENDOR_MIN;
3080 opt.arg.r.max = FLASH_VENDOR_MAX;
3081#ifdef module_param_array
3082 if (num_FlashVendor > bd) {
3083#endif
3084 val = FlashVendor[bd];
3085 atl2_validate_option(&val, &opt);
3086 adapter->hw.flash_vendor = (u8) val;
3087#ifdef module_param_array
3088 } else
3089 adapter->hw.flash_vendor = (u8)(opt.def);
3090#endif
3091 /* MediaType */
3092 opt.type = range_option;
3093 opt.name = "Speed/Duplex Selection";
3094 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR);
3095 opt.def = MEDIA_TYPE_AUTO_SENSOR;
3096 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR;
3097 opt.arg.r.max = MEDIA_TYPE_10M_HALF;
3098#ifdef module_param_array
3099 if (num_MediaType > bd) {
3100#endif
3101 val = MediaType[bd];
3102 atl2_validate_option(&val, &opt);
3103 adapter->hw.MediaType = (u16) val;
3104#ifdef module_param_array
3105 } else
3106 adapter->hw.MediaType = (u16)(opt.def);
3107#endif
3108}
Linux kernel - Deliverables
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