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phylib: Wake PHY state machine on interrupt
[deliverable/linux.git] / drivers / net / atlx / atl2.c
CommitLineData
452c1ce2
CS		 1/*
2 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved.
3 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com>
4 *
5 * Derived from Intel e1000 driver
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23#include <asm/atomic.h>
24#include <linux/crc32.h>
25#include <linux/dma-mapping.h>
26#include <linux/etherdevice.h>
27#include <linux/ethtool.h>
28#include <linux/hardirq.h>
29#include <linux/if_vlan.h>
30#include <linux/in.h>
31#include <linux/interrupt.h>
32#include <linux/ip.h>
33#include <linux/irqflags.h>
34#include <linux/irqreturn.h>
35#include <linux/mii.h>
36#include <linux/net.h>
37#include <linux/netdevice.h>
38#include <linux/pci.h>
39#include <linux/pci_ids.h>
40#include <linux/pm.h>
41#include <linux/skbuff.h>
42#include <linux/spinlock.h>
43#include <linux/string.h>
44#include <linux/tcp.h>
45#include <linux/timer.h>
46#include <linux/types.h>
47#include <linux/workqueue.h>
48
49#include "atl2.h"
50
51#define ATL2_DRV_VERSION "2.2.3"
52
53static char atl2_driver_name[] = "atl2";
54static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver";
55static char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation.";
56static char atl2_driver_version[] = ATL2_DRV_VERSION;
57
58MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>");
59MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver");
60MODULE_LICENSE("GPL");
61MODULE_VERSION(ATL2_DRV_VERSION);
62
63/*
64 * atl2_pci_tbl - PCI Device ID Table
65 */
66static struct pci_device_id atl2_pci_tbl[] = {
67 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)},
68 /* required last entry */
69 {0,}
70};
71MODULE_DEVICE_TABLE(pci, atl2_pci_tbl);
72
73static void atl2_set_ethtool_ops(struct net_device *netdev);
74
75static void atl2_check_options(struct atl2_adapter *adapter);
76
77/*
78 * atl2_sw_init - Initialize general software structures (struct atl2_adapter)
79 * @adapter: board private structure to initialize
80 *
81 * atl2_sw_init initializes the Adapter private data structure.
82 * Fields are initialized based on PCI device information and
83 * OS network device settings (MTU size).
84 */
85static int __devinit atl2_sw_init(struct atl2_adapter *adapter)
86{
87 struct atl2_hw *hw = &adapter->hw;
88 struct pci_dev *pdev = adapter->pdev;
89
90 /* PCI config space info */
91 hw->vendor_id = pdev->vendor;
92 hw->device_id = pdev->device;
93 hw->subsystem_vendor_id = pdev->subsystem_vendor;
94 hw->subsystem_id = pdev->subsystem_device;
95
96 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
97 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
98
99 adapter->wol = 0;
100 adapter->ict = 50000; /* ~100ms */
101 adapter->link_speed = SPEED_0; /* hardware init */
102 adapter->link_duplex = FULL_DUPLEX;
103
104 hw->phy_configured = false;
105 hw->preamble_len = 7;
106 hw->ipgt = 0x60;
107 hw->min_ifg = 0x50;
108 hw->ipgr1 = 0x40;
109 hw->ipgr2 = 0x60;
110 hw->retry_buf = 2;
111 hw->max_retry = 0xf;
112 hw->lcol = 0x37;
113 hw->jam_ipg = 7;
114 hw->fc_rxd_hi = 0;
115 hw->fc_rxd_lo = 0;
116 hw->max_frame_size = adapter->netdev->mtu;
117
118 spin_lock_init(&adapter->stats_lock);
119 spin_lock_init(&adapter->tx_lock);
120
121 set_bit(__ATL2_DOWN, &adapter->flags);
122
123 return 0;
124}
125
126/*
127 * atl2_set_multi - Multicast and Promiscuous mode set
128 * @netdev: network interface device structure
129 *
130 * The set_multi entry point is called whenever the multicast address
131 * list or the network interface flags are updated. This routine is
132 * responsible for configuring the hardware for proper multicast,
133 * promiscuous mode, and all-multi behavior.
134 */
135static void atl2_set_multi(struct net_device *netdev)
136{
137 struct atl2_adapter *adapter = netdev_priv(netdev);
138 struct atl2_hw *hw = &adapter->hw;
139 struct dev_mc_list *mc_ptr;
140 u32 rctl;
141 u32 hash_value;
142
143 /* Check for Promiscuous and All Multicast modes */
144 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL);
145
146 if (netdev->flags & IFF_PROMISC) {
147 rctl |= MAC_CTRL_PROMIS_EN;
148 } else if (netdev->flags & IFF_ALLMULTI) {
149 rctl |= MAC_CTRL_MC_ALL_EN;
150 rctl &= ~MAC_CTRL_PROMIS_EN;
151 } else
152 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
153
154 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);
155
156 /* clear the old settings from the multicast hash table */
157 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
158 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
159
160 /* comoute mc addresses' hash value ,and put it into hash table */
161 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
162 hash_value = atl2_hash_mc_addr(hw, mc_ptr->dmi_addr);
163 atl2_hash_set(hw, hash_value);
164 }
165}
166
167static void init_ring_ptrs(struct atl2_adapter *adapter)
168{
169 /* Read / Write Ptr Initialize: */
170 adapter->txd_write_ptr = 0;
171 atomic_set(&adapter->txd_read_ptr, 0);
172
173 adapter->rxd_read_ptr = 0;
174 adapter->rxd_write_ptr = 0;
175
176 atomic_set(&adapter->txs_write_ptr, 0);
177 adapter->txs_next_clear = 0;
178}
179
180/*
181 * atl2_configure - Configure Transmit&Receive Unit after Reset
182 * @adapter: board private structure
183 *
184 * Configure the Tx /Rx unit of the MAC after a reset.
185 */
186static int atl2_configure(struct atl2_adapter *adapter)
187{
188 struct atl2_hw *hw = &adapter->hw;
189 u32 value;
190
191 /* clear interrupt status */
192 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);
193
194 /* set MAC Address */
195 value = (((u32)hw->mac_addr[2]) << 24) |
196 (((u32)hw->mac_addr[3]) << 16) |
197 (((u32)hw->mac_addr[4]) << 8) |
198 (((u32)hw->mac_addr[5]));
199 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);
200 value = (((u32)hw->mac_addr[0]) << 8) |
201 (((u32)hw->mac_addr[1]));
202 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);
203
204 /* HI base address */
205 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
206 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32));
207
208 /* LO base address */
209 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,
210 (u32)(adapter->txd_dma & 0x00000000ffffffffULL));
211 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,
212 (u32)(adapter->txs_dma & 0x00000000ffffffffULL));
213 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,
214 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL));
215
216 /* element count */
217 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4));
218 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size);
219 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size);
220
221 /* config Internal SRAM */
222/*
223 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end);
224 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end);
225*/
226
227 /* config IPG/IFG */
228 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) <<
229 MAC_IPG_IFG_IPGT_SHIFT) |
230 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) <<
231 MAC_IPG_IFG_MIFG_SHIFT) |
232 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) <<
233 MAC_IPG_IFG_IPGR1_SHIFT)|
234 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) <<
235 MAC_IPG_IFG_IPGR2_SHIFT);
236 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);
237
238 /* config Half-Duplex Control */
239 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
240 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) <<
241 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
242 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
243 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
244 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) <<
245 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
246 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);
247
248 /* set Interrupt Moderator Timer */
249 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt);
250 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);
251
252 /* set Interrupt Clear Timer */
253 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict);
254
255 /* set MTU */
256 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +
257 ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE);
258
259 /* 1590 */
260 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);
261
262 /* flow control */
263 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi);
264 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo);
265
266 /* Init mailbox */
267 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr);
268 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr);
269
270 /* enable DMA read/write */
271 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN);
272 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN);
273
274 value = ATL2_READ_REG(&adapter->hw, REG_ISR);
275 if ((value & ISR_PHY_LINKDOWN) != 0)
276 value = 1; /* config failed */
277 else
278 value = 0;
279
280 /* clear all interrupt status */
281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);
282 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
283 return value;
284}
285
286/*
287 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources
288 * @adapter: board private structure
289 *
290 * Return 0 on success, negative on failure
291 */
292static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter)
293{
294 struct pci_dev *pdev = adapter->pdev;
295 int size;
296 u8 offset = 0;
297
298 /* real ring DMA buffer */
299 adapter->ring_size = size =
300 adapter->txd_ring_size * 1 + 7 + /* dword align */
301 adapter->txs_ring_size * 4 + 7 + /* dword align */
302 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */
303
304 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size,
305 &adapter->ring_dma);
306 if (!adapter->ring_vir_addr)
307 return -ENOMEM;
308 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
309
310 /* Init TXD Ring */
311 adapter->txd_dma = adapter->ring_dma ;
312 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;
313 adapter->txd_dma += offset;
314 adapter->txd_ring = (struct tx_pkt_header *) (adapter->ring_vir_addr +
315 offset);
316
317 /* Init TXS Ring */
318 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;
319 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0;
320 adapter->txs_dma += offset;
321 adapter->txs_ring = (struct tx_pkt_status *)
322 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset));
323
324 /* Init RXD Ring */
325 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4;
326 offset = (adapter->rxd_dma & 127) ?
327 (128 - (adapter->rxd_dma & 127)) : 0;
328 if (offset > 7)
329 offset -= 8;
330 else
331 offset += (128 - 8);
332
333 adapter->rxd_dma += offset;
334 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) +
335 (adapter->txs_ring_size * 4 + offset));
336
337/*
338 * Read / Write Ptr Initialize:
339 * init_ring_ptrs(adapter);
340 */
341 return 0;
342}
343
344/*
345 * atl2_irq_enable - Enable default interrupt generation settings
346 * @adapter: board private structure
347 */
348static inline void atl2_irq_enable(struct atl2_adapter *adapter)
349{
350 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
351 ATL2_WRITE_FLUSH(&adapter->hw);
352}
353
354/*
355 * atl2_irq_disable - Mask off interrupt generation on the NIC
356 * @adapter: board private structure
357 */
358static inline void atl2_irq_disable(struct atl2_adapter *adapter)
359{
360 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);
361 ATL2_WRITE_FLUSH(&adapter->hw);
362 synchronize_irq(adapter->pdev->irq);
363}
364
365#ifdef NETIF_F_HW_VLAN_TX
366static void atl2_vlan_rx_register(struct net_device *netdev,
367 struct vlan_group *grp)
368{
369 struct atl2_adapter *adapter = netdev_priv(netdev);
370 u32 ctrl;
371
372 atl2_irq_disable(adapter);
373 adapter->vlgrp = grp;
374
375 if (grp) {
376 /* enable VLAN tag insert/strip */
377 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
378 ctrl |= MAC_CTRL_RMV_VLAN;
379 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
380 } else {
381 /* disable VLAN tag insert/strip */
382 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
383 ctrl &= ~MAC_CTRL_RMV_VLAN;
384 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
385 }
386
387 atl2_irq_enable(adapter);
388}
389
390static void atl2_restore_vlan(struct atl2_adapter *adapter)
391{
392 atl2_vlan_rx_register(adapter->netdev, adapter->vlgrp);
393}
394#endif
395
396static void atl2_intr_rx(struct atl2_adapter *adapter)
397{
398 struct net_device *netdev = adapter->netdev;
399 struct rx_desc *rxd;
400 struct sk_buff *skb;
401
402 do {
403 rxd = adapter->rxd_ring+adapter->rxd_write_ptr;
404 if (!rxd->status.update)
405 break; /* end of tx */
406
407 /* clear this flag at once */
408 rxd->status.update = 0;
409
410 if (rxd->status.ok && rxd->status.pkt_size >= 60) {
411 int rx_size = (int)(rxd->status.pkt_size - 4);
412 /* alloc new buffer */
413 skb = netdev_alloc_skb(netdev, rx_size + NET_IP_ALIGN);
414 if (NULL == skb) {
415 printk(KERN_WARNING
416 "%s: Mem squeeze, deferring packet.\n",
417 netdev->name);
418 /*
419 * Check that some rx space is free. If not,
420 * free one and mark stats->rx_dropped++.
421 */
422 adapter->net_stats.rx_dropped++;
423 break;
424 }
425 skb_reserve(skb, NET_IP_ALIGN);
426 skb->dev = netdev;
427 memcpy(skb->data, rxd->packet, rx_size);
428 skb_put(skb, rx_size);
429 skb->protocol = eth_type_trans(skb, netdev);
430#ifdef NETIF_F_HW_VLAN_TX
431 if (adapter->vlgrp && (rxd->status.vlan)) {
432 u16 vlan_tag = (rxd->status.vtag>>4) |
433 ((rxd->status.vtag&7) << 13) |
434 ((rxd->status.vtag&8) << 9);
435 vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
436 } else
437#endif
438 netif_rx(skb);
439 adapter->net_stats.rx_bytes += rx_size;
440 adapter->net_stats.rx_packets++;
441 netdev->last_rx = jiffies;
442 } else {
443 adapter->net_stats.rx_errors++;
444
445 if (rxd->status.ok && rxd->status.pkt_size <= 60)
446 adapter->net_stats.rx_length_errors++;
447 if (rxd->status.mcast)
448 adapter->net_stats.multicast++;
449 if (rxd->status.crc)
450 adapter->net_stats.rx_crc_errors++;
451 if (rxd->status.align)
452 adapter->net_stats.rx_frame_errors++;
453 }
454
455 /* advance write ptr */
456 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size)
457 adapter->rxd_write_ptr = 0;
458 } while (1);
459
460 /* update mailbox? */
461 adapter->rxd_read_ptr = adapter->rxd_write_ptr;
462 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr);
463}
464
465static void atl2_intr_tx(struct atl2_adapter *adapter)
466{
467 u32 txd_read_ptr;
468 u32 txs_write_ptr;
469 struct tx_pkt_status *txs;
470 struct tx_pkt_header *txph;
471 int free_hole = 0;
472
473 do {
474 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
475 txs = adapter->txs_ring + txs_write_ptr;
476 if (!txs->update)
477 break; /* tx stop here */
478
479 free_hole = 1;
480 txs->update = 0;
481
482 if (++txs_write_ptr == adapter->txs_ring_size)
483 txs_write_ptr = 0;
484 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr);
485
486 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr);
487 txph = (struct tx_pkt_header *)
488 (((u8 *)adapter->txd_ring) + txd_read_ptr);
489
490 if (txph->pkt_size != txs->pkt_size) {
491 struct tx_pkt_status *old_txs = txs;
492 printk(KERN_WARNING
493 "%s: txs packet size not consistent with txd"
494 " txd_:0x%08x, txs_:0x%08x!\n",
495 adapter->netdev->name,
496 *(u32 *)txph, *(u32 *)txs);
497 printk(KERN_WARNING
498 "txd read ptr: 0x%x\n",
499 txd_read_ptr);
500 txs = adapter->txs_ring + txs_write_ptr;
501 printk(KERN_WARNING
502 "txs-behind:0x%08x\n",
503 *(u32 *)txs);
504 if (txs_write_ptr < 2) {
505 txs = adapter->txs_ring +
506 (adapter->txs_ring_size +
507 txs_write_ptr - 2);
508 } else {
509 txs = adapter->txs_ring + (txs_write_ptr - 2);
510 }
511 printk(KERN_WARNING
512 "txs-before:0x%08x\n",
513 *(u32 *)txs);
514 txs = old_txs;
515 }
516
517 /* 4for TPH */
518 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3);
519 if (txd_read_ptr >= adapter->txd_ring_size)
520 txd_read_ptr -= adapter->txd_ring_size;
521
522 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr);
523
524 /* tx statistics: */
e2f092ff
JC		 525 if (txs->ok) {
526 adapter->net_stats.tx_bytes += txs->pkt_size;
452c1ce2 527 adapter->net_stats.tx_packets++;
e2f092ff 528 }
452c1ce2
CS		 529 else
530 adapter->net_stats.tx_errors++;
531
532 if (txs->defer)
533 adapter->net_stats.collisions++;
534 if (txs->abort_col)
535 adapter->net_stats.tx_aborted_errors++;
536 if (txs->late_col)
537 adapter->net_stats.tx_window_errors++;
538 if (txs->underun)
539 adapter->net_stats.tx_fifo_errors++;
540 } while (1);
541
542 if (free_hole) {
543 if (netif_queue_stopped(adapter->netdev) &&
544 netif_carrier_ok(adapter->netdev))
545 netif_wake_queue(adapter->netdev);
546 }
547}
548
549static void atl2_check_for_link(struct atl2_adapter *adapter)
550{
551 struct net_device *netdev = adapter->netdev;
552 u16 phy_data = 0;
553
554 spin_lock(&adapter->stats_lock);
555 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
556 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
557 spin_unlock(&adapter->stats_lock);
558
559 /* notify upper layer link down ASAP */
560 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
561 if (netif_carrier_ok(netdev)) { /* old link state: Up */
562 printk(KERN_INFO "%s: %s NIC Link is Down\n",
563 atl2_driver_name, netdev->name);
564 adapter->link_speed = SPEED_0;
565 netif_carrier_off(netdev);
566 netif_stop_queue(netdev);
567 }
568 }
569 schedule_work(&adapter->link_chg_task);
570}
571
572static inline void atl2_clear_phy_int(struct atl2_adapter *adapter)
573{
574 u16 phy_data;
575 spin_lock(&adapter->stats_lock);
576 atl2_read_phy_reg(&adapter->hw, 19, &phy_data);
577 spin_unlock(&adapter->stats_lock);
578}
579
580/*
581 * atl2_intr - Interrupt Handler
582 * @irq: interrupt number
583 * @data: pointer to a network interface device structure
584 * @pt_regs: CPU registers structure
585 */
586static irqreturn_t atl2_intr(int irq, void *data)
587{
588 struct atl2_adapter *adapter = netdev_priv(data);
589 struct atl2_hw *hw = &adapter->hw;
590 u32 status;
591
592 status = ATL2_READ_REG(hw, REG_ISR);
593 if (0 == status)
594 return IRQ_NONE;
595
596 /* link event */
597 if (status & ISR_PHY)
598 atl2_clear_phy_int(adapter);
599
600 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
601 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
602
603 /* check if PCIE PHY Link down */
604 if (status & ISR_PHY_LINKDOWN) {
605 if (netif_running(adapter->netdev)) { /* reset MAC */
606 ATL2_WRITE_REG(hw, REG_ISR, 0);
607 ATL2_WRITE_REG(hw, REG_IMR, 0);
608 ATL2_WRITE_FLUSH(hw);
609 schedule_work(&adapter->reset_task);
610 return IRQ_HANDLED;
611 }
612 }
613
614 /* check if DMA read/write error? */
615 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
616 ATL2_WRITE_REG(hw, REG_ISR, 0);
617 ATL2_WRITE_REG(hw, REG_IMR, 0);
618 ATL2_WRITE_FLUSH(hw);
619 schedule_work(&adapter->reset_task);
620 return IRQ_HANDLED;
621 }
622
623 /* link event */
624 if (status & (ISR_PHY | ISR_MANUAL)) {
625 adapter->net_stats.tx_carrier_errors++;
626 atl2_check_for_link(adapter);
627 }
628
629 /* transmit event */
630 if (status & ISR_TX_EVENT)
631 atl2_intr_tx(adapter);
632
633 /* rx exception */
634 if (status & ISR_RX_EVENT)
635 atl2_intr_rx(adapter);
636
637 /* re-enable Interrupt */
638 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
639 return IRQ_HANDLED;
640}
641
642static int atl2_request_irq(struct atl2_adapter *adapter)
643{
644 struct net_device *netdev = adapter->netdev;
645 int flags, err = 0;
646
647 flags = IRQF_SHARED;
648#ifdef CONFIG_PCI_MSI
649 adapter->have_msi = true;
650 err = pci_enable_msi(adapter->pdev);
651 if (err)
652 adapter->have_msi = false;
653
654 if (adapter->have_msi)
655 flags &= ~IRQF_SHARED;
656#endif
657
658 return request_irq(adapter->pdev->irq, &atl2_intr, flags, netdev->name,
659 netdev);
660}
661
662/*
663 * atl2_free_ring_resources - Free Tx / RX descriptor Resources
664 * @adapter: board private structure
665 *
666 * Free all transmit software resources
667 */
668static void atl2_free_ring_resources(struct atl2_adapter *adapter)
669{
670 struct pci_dev *pdev = adapter->pdev;
671 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr,
672 adapter->ring_dma);
673}
674
675/*
676 * atl2_open - Called when a network interface is made active
677 * @netdev: network interface device structure
678 *
679 * Returns 0 on success, negative value on failure
680 *
681 * The open entry point is called when a network interface is made
682 * active by the system (IFF_UP). At this point all resources needed
683 * for transmit and receive operations are allocated, the interrupt
684 * handler is registered with the OS, the watchdog timer is started,
685 * and the stack is notified that the interface is ready.
686 */
687static int atl2_open(struct net_device *netdev)
688{
689 struct atl2_adapter *adapter = netdev_priv(netdev);
690 int err;
691 u32 val;
692
693 /* disallow open during test */
694 if (test_bit(__ATL2_TESTING, &adapter->flags))
695 return -EBUSY;
696
697 /* allocate transmit descriptors */
698 err = atl2_setup_ring_resources(adapter);
699 if (err)
700 return err;
701
702 err = atl2_init_hw(&adapter->hw);
703 if (err) {
704 err = -EIO;
705 goto err_init_hw;
706 }
707
708 /* hardware has been reset, we need to reload some things */
709 atl2_set_multi(netdev);
710 init_ring_ptrs(adapter);
711
712#ifdef NETIF_F_HW_VLAN_TX
713 atl2_restore_vlan(adapter);
714#endif
715
716 if (atl2_configure(adapter)) {
717 err = -EIO;
718 goto err_config;
719 }
720
721 err = atl2_request_irq(adapter);
722 if (err)
723 goto err_req_irq;
724
725 clear_bit(__ATL2_DOWN, &adapter->flags);
726
727 mod_timer(&adapter->watchdog_timer, jiffies + 4*HZ);
728
729 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
730 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
731 val | MASTER_CTRL_MANUAL_INT);
732
733 atl2_irq_enable(adapter);
734
735 return 0;
736
737err_init_hw:
738err_req_irq:
739err_config:
740 atl2_free_ring_resources(adapter);
741 atl2_reset_hw(&adapter->hw);
742
743 return err;
744}
745
746static void atl2_down(struct atl2_adapter *adapter)
747{
748 struct net_device *netdev = adapter->netdev;
749
750 /* signal that we're down so the interrupt handler does not
751 * reschedule our watchdog timer */
752 set_bit(__ATL2_DOWN, &adapter->flags);
753
754#ifdef NETIF_F_LLTX
755 netif_stop_queue(netdev);
756#else
757 netif_tx_disable(netdev);
758#endif
759
760 /* reset MAC to disable all RX/TX */
761 atl2_reset_hw(&adapter->hw);
762 msleep(1);
763
764 atl2_irq_disable(adapter);
765
766 del_timer_sync(&adapter->watchdog_timer);
767 del_timer_sync(&adapter->phy_config_timer);
768 clear_bit(0, &adapter->cfg_phy);
769
770 netif_carrier_off(netdev);
771 adapter->link_speed = SPEED_0;
772 adapter->link_duplex = -1;
773}
774
775static void atl2_free_irq(struct atl2_adapter *adapter)
776{
777 struct net_device *netdev = adapter->netdev;
778
779 free_irq(adapter->pdev->irq, netdev);
780
781#ifdef CONFIG_PCI_MSI
782 if (adapter->have_msi)
783 pci_disable_msi(adapter->pdev);
784#endif
785}
786
787/*
788 * atl2_close - Disables a network interface
789 * @netdev: network interface device structure
790 *
791 * Returns 0, this is not allowed to fail
792 *
793 * The close entry point is called when an interface is de-activated
794 * by the OS. The hardware is still under the drivers control, but
795 * needs to be disabled. A global MAC reset is issued to stop the
796 * hardware, and all transmit and receive resources are freed.
797 */
798static int atl2_close(struct net_device *netdev)
799{
800 struct atl2_adapter *adapter = netdev_priv(netdev);
801
802 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
803
804 atl2_down(adapter);
805 atl2_free_irq(adapter);
806 atl2_free_ring_resources(adapter);
807
808 return 0;
809}
810
811static inline int TxsFreeUnit(struct atl2_adapter *adapter)
812{
813 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
814
815 return (adapter->txs_next_clear >= txs_write_ptr) ?
816 (int) (adapter->txs_ring_size - adapter->txs_next_clear +
817 txs_write_ptr - 1) :
818 (int) (txs_write_ptr - adapter->txs_next_clear - 1);
819}
820
821static inline int TxdFreeBytes(struct atl2_adapter *adapter)
822{
823 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr);
824
825 return (adapter->txd_write_ptr >= txd_read_ptr) ?
826 (int) (adapter->txd_ring_size - adapter->txd_write_ptr +
827 txd_read_ptr - 1) :
828 (int) (txd_read_ptr - adapter->txd_write_ptr - 1);
829}
830
831static int atl2_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
832{
833 struct atl2_adapter *adapter = netdev_priv(netdev);
834 unsigned long flags;
835 struct tx_pkt_header *txph;
836 u32 offset, copy_len;
837 int txs_unused;
838 int txbuf_unused;
839
840 if (test_bit(__ATL2_DOWN, &adapter->flags)) {
841 dev_kfree_skb_any(skb);
842 return NETDEV_TX_OK;
843 }
844
845 if (unlikely(skb->len <= 0)) {
846 dev_kfree_skb_any(skb);
847 return NETDEV_TX_OK;
848 }
849
850#ifdef NETIF_F_LLTX
851 local_irq_save(flags);
852 if (!spin_trylock(&adapter->tx_lock)) {
853 /* Collision - tell upper layer to requeue */
854 local_irq_restore(flags);
855 return NETDEV_TX_LOCKED;
856 }
857#else
858 spin_lock_irqsave(&adapter->tx_lock, flags);
859#endif
860 txs_unused = TxsFreeUnit(adapter);
861 txbuf_unused = TxdFreeBytes(adapter);
862
863 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused ||
864 txs_unused < 1) {
865 /* not enough resources */
866 netif_stop_queue(netdev);
867 spin_unlock_irqrestore(&adapter->tx_lock, flags);
868 return NETDEV_TX_BUSY;
869 }
870
871 offset = adapter->txd_write_ptr;
872
873 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset);
874
875 *(u32 *)txph = 0;
876 txph->pkt_size = skb->len;
877
878 offset += 4;
879 if (offset >= adapter->txd_ring_size)
880 offset -= adapter->txd_ring_size;
881 copy_len = adapter->txd_ring_size - offset;
882 if (copy_len >= skb->len) {
883 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len);
884 offset += ((u32)(skb->len + 3) & ~3);
885 } else {
886 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len);
887 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len,
888 skb->len-copy_len);
889 offset = ((u32)(skb->len-copy_len + 3) & ~3);
890 }
891#ifdef NETIF_F_HW_VLAN_TX
892 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
893 u16 vlan_tag = vlan_tx_tag_get(skb);
894 vlan_tag = (vlan_tag << 4) |
895 (vlan_tag >> 13) |
896 ((vlan_tag >> 9) & 0x8);
897 txph->ins_vlan = 1;
898 txph->vlan = vlan_tag;
899 }
900#endif
901 if (offset >= adapter->txd_ring_size)
902 offset -= adapter->txd_ring_size;
903 adapter->txd_write_ptr = offset;
904
905 /* clear txs before send */
906 adapter->txs_ring[adapter->txs_next_clear].update = 0;
907 if (++adapter->txs_next_clear == adapter->txs_ring_size)
908 adapter->txs_next_clear = 0;
909
910 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX,
911 (adapter->txd_write_ptr >> 2));
912
913 spin_unlock_irqrestore(&adapter->tx_lock, flags);
914
915 netdev->trans_start = jiffies;
916 dev_kfree_skb_any(skb);
917 return NETDEV_TX_OK;
918}
919
920/*
921 * atl2_get_stats - Get System Network Statistics
922 * @netdev: network interface device structure
923 *
924 * Returns the address of the device statistics structure.
925 * The statistics are actually updated from the timer callback.
926 */
927static struct net_device_stats *atl2_get_stats(struct net_device *netdev)
928{
929 struct atl2_adapter *adapter = netdev_priv(netdev);
930 return &adapter->net_stats;
931}
932
933/*
934 * atl2_change_mtu - Change the Maximum Transfer Unit
935 * @netdev: network interface device structure
936 * @new_mtu: new value for maximum frame size
937 *
938 * Returns 0 on success, negative on failure
939 */
940static int atl2_change_mtu(struct net_device *netdev, int new_mtu)
941{
942 struct atl2_adapter *adapter = netdev_priv(netdev);
943 struct atl2_hw *hw = &adapter->hw;
944
945 if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE)))
946 return -EINVAL;
947
948 /* set MTU */
949 if (hw->max_frame_size != new_mtu) {
950 netdev->mtu = new_mtu;
951 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE +
952 VLAN_SIZE + ETHERNET_FCS_SIZE);
953 }
954
955 return 0;
956}
957
958/*
959 * atl2_set_mac - Change the Ethernet Address of the NIC
960 * @netdev: network interface device structure
961 * @p: pointer to an address structure
962 *
963 * Returns 0 on success, negative on failure
964 */
965static int atl2_set_mac(struct net_device *netdev, void *p)
966{
967 struct atl2_adapter *adapter = netdev_priv(netdev);
968 struct sockaddr *addr = p;
969
970 if (!is_valid_ether_addr(addr->sa_data))
971 return -EADDRNOTAVAIL;
972
973 if (netif_running(netdev))
974 return -EBUSY;
975
976 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
977 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
978
979 atl2_set_mac_addr(&adapter->hw);
980
981 return 0;
982}
983
984/*
985 * atl2_mii_ioctl -
986 * @netdev:
987 * @ifreq:
988 * @cmd:
989 */
990static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
991{
992 struct atl2_adapter *adapter = netdev_priv(netdev);
993 struct mii_ioctl_data *data = if_mii(ifr);
994 unsigned long flags;
995
996 switch (cmd) {
997 case SIOCGMIIPHY:
998 data->phy_id = 0;
999 break;
1000 case SIOCGMIIREG:
1001 if (!capable(CAP_NET_ADMIN))
1002 return -EPERM;
1003 spin_lock_irqsave(&adapter->stats_lock, flags);
1004 if (atl2_read_phy_reg(&adapter->hw,
1005 data->reg_num & 0x1F, &data->val_out)) {
1006 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1007 return -EIO;
1008 }
1009 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1010 break;
1011 case SIOCSMIIREG:
1012 if (!capable(CAP_NET_ADMIN))
1013 return -EPERM;
1014 if (data->reg_num & ~(0x1F))
1015 return -EFAULT;
1016 spin_lock_irqsave(&adapter->stats_lock, flags);
1017 if (atl2_write_phy_reg(&adapter->hw, data->reg_num,
1018 data->val_in)) {
1019 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1020 return -EIO;
1021 }
1022 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1023 break;
1024 default:
1025 return -EOPNOTSUPP;
1026 }
1027 return 0;
1028}
1029
1030/*
1031 * atl2_ioctl -
1032 * @netdev:
1033 * @ifreq:
1034 * @cmd:
1035 */
1036static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1037{
1038 switch (cmd) {
1039 case SIOCGMIIPHY:
1040 case SIOCGMIIREG:
1041 case SIOCSMIIREG:
1042 return atl2_mii_ioctl(netdev, ifr, cmd);
1043#ifdef ETHTOOL_OPS_COMPAT
1044 case SIOCETHTOOL:
1045 return ethtool_ioctl(ifr);
1046#endif
1047 default:
1048 return -EOPNOTSUPP;
1049 }
1050}
1051
1052/*
1053 * atl2_tx_timeout - Respond to a Tx Hang
1054 * @netdev: network interface device structure
1055 */
1056static void atl2_tx_timeout(struct net_device *netdev)
1057{
1058 struct atl2_adapter *adapter = netdev_priv(netdev);
1059
1060 /* Do the reset outside of interrupt context */
1061 schedule_work(&adapter->reset_task);
1062}
1063
1064/*
1065 * atl2_watchdog - Timer Call-back
1066 * @data: pointer to netdev cast into an unsigned long
1067 */
1068static void atl2_watchdog(unsigned long data)
1069{
1070 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1071 u32 drop_rxd, drop_rxs;
1072 unsigned long flags;
1073
1074 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1075 spin_lock_irqsave(&adapter->stats_lock, flags);
1076 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV);
1077 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV);
1078 adapter->net_stats.rx_over_errors += (drop_rxd+drop_rxs);
1079 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1080
1081 /* Reset the timer */
1082 mod_timer(&adapter->watchdog_timer, jiffies + 4 * HZ);
1083 }
1084}
1085
1086/*
1087 * atl2_phy_config - Timer Call-back
1088 * @data: pointer to netdev cast into an unsigned long
1089 */
1090static void atl2_phy_config(unsigned long data)
1091{
1092 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1093 struct atl2_hw *hw = &adapter->hw;
1094 unsigned long flags;
1095
1096 spin_lock_irqsave(&adapter->stats_lock, flags);
1097 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1098 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN |
1099 MII_CR_RESTART_AUTO_NEG);
1100 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1101 clear_bit(0, &adapter->cfg_phy);
1102}
1103
1104static int atl2_up(struct atl2_adapter *adapter)
1105{
1106 struct net_device *netdev = adapter->netdev;
1107 int err = 0;
1108 u32 val;
1109
1110 /* hardware has been reset, we need to reload some things */
1111
1112 err = atl2_init_hw(&adapter->hw);
1113 if (err) {
1114 err = -EIO;
1115 return err;
1116 }
1117
1118 atl2_set_multi(netdev);
1119 init_ring_ptrs(adapter);
1120
1121#ifdef NETIF_F_HW_VLAN_TX
1122 atl2_restore_vlan(adapter);
1123#endif
1124
1125 if (atl2_configure(adapter)) {
1126 err = -EIO;
1127 goto err_up;
1128 }
1129
1130 clear_bit(__ATL2_DOWN, &adapter->flags);
1131
1132 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1133 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val |
1134 MASTER_CTRL_MANUAL_INT);
1135
1136 atl2_irq_enable(adapter);
1137
1138err_up:
1139 return err;
1140}
1141
1142static void atl2_reinit_locked(struct atl2_adapter *adapter)
1143{
1144 WARN_ON(in_interrupt());
1145 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1146 msleep(1);
1147 atl2_down(adapter);
1148 atl2_up(adapter);
1149 clear_bit(__ATL2_RESETTING, &adapter->flags);
1150}
1151
1152static void atl2_reset_task(struct work_struct *work)
1153{
1154 struct atl2_adapter *adapter;
1155 adapter = container_of(work, struct atl2_adapter, reset_task);
1156
1157 atl2_reinit_locked(adapter);
1158}
1159
1160static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter)
1161{
1162 u32 value;
1163 struct atl2_hw *hw = &adapter->hw;
1164 struct net_device *netdev = adapter->netdev;
1165
1166 /* Config MAC CTRL Register */
1167 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1168
1169 /* duplex */
1170 if (FULL_DUPLEX == adapter->link_duplex)
1171 value |= MAC_CTRL_DUPLX;
1172
1173 /* flow control */
1174 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1175
1176 /* PAD & CRC */
1177 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1178
1179 /* preamble length */
1180 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) <<
1181 MAC_CTRL_PRMLEN_SHIFT);
1182
1183 /* vlan */
1184 if (adapter->vlgrp)
1185 value |= MAC_CTRL_RMV_VLAN;
1186
1187 /* filter mode */
1188 value |= MAC_CTRL_BC_EN;
1189 if (netdev->flags & IFF_PROMISC)
1190 value |= MAC_CTRL_PROMIS_EN;
1191 else if (netdev->flags & IFF_ALLMULTI)
1192 value |= MAC_CTRL_MC_ALL_EN;
1193
1194 /* half retry buffer */
1195 value |= (((u32)(adapter->hw.retry_buf &
1196 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1197
1198 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1199}
1200
1201static int atl2_check_link(struct atl2_adapter *adapter)
1202{
1203 struct atl2_hw *hw = &adapter->hw;
1204 struct net_device *netdev = adapter->netdev;
1205 int ret_val;
1206 u16 speed, duplex, phy_data;
1207 int reconfig = 0;
1208
1209 /* MII_BMSR must read twise */
1210 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1211 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1212 if (!(phy_data&BMSR_LSTATUS)) { /* link down */
1213 if (netif_carrier_ok(netdev)) { /* old link state: Up */
1214 u32 value;
1215 /* disable rx */
1216 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1217 value &= ~MAC_CTRL_RX_EN;
1218 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1219 adapter->link_speed = SPEED_0;
1220 netif_carrier_off(netdev);
1221 netif_stop_queue(netdev);
1222 }
1223 return 0;
1224 }
1225
1226 /* Link Up */
1227 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1228 if (ret_val)
1229 return ret_val;
1230 switch (hw->MediaType) {
1231 case MEDIA_TYPE_100M_FULL:
1232 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1233 reconfig = 1;
1234 break;
1235 case MEDIA_TYPE_100M_HALF:
1236 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1237 reconfig = 1;
1238 break;
1239 case MEDIA_TYPE_10M_FULL:
1240 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1241 reconfig = 1;
1242 break;
1243 case MEDIA_TYPE_10M_HALF:
1244 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1245 reconfig = 1;
1246 break;
1247 }
1248 /* link result is our setting */
1249 if (reconfig == 0) {
1250 if (adapter->link_speed != speed ||
1251 adapter->link_duplex != duplex) {
1252 adapter->link_speed = speed;
1253 adapter->link_duplex = duplex;
1254 atl2_setup_mac_ctrl(adapter);
1255 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n",
1256 atl2_driver_name, netdev->name,
1257 adapter->link_speed,
1258 adapter->link_duplex == FULL_DUPLEX ?
1259 "Full Duplex" : "Half Duplex");
1260 }
1261
1262 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
1263 netif_carrier_on(netdev);
1264 netif_wake_queue(netdev);
1265 }
1266 return 0;
1267 }
1268
1269 /* change original link status */
1270 if (netif_carrier_ok(netdev)) {
1271 u32 value;
1272 /* disable rx */
1273 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1274 value &= ~MAC_CTRL_RX_EN;
1275 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1276
1277 adapter->link_speed = SPEED_0;
1278 netif_carrier_off(netdev);
1279 netif_stop_queue(netdev);
1280 }
1281
1282 /* auto-neg, insert timer to re-config phy
1283 * (if interval smaller than 5 seconds, something strange) */
1284 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1285 if (!test_and_set_bit(0, &adapter->cfg_phy))
1286 mod_timer(&adapter->phy_config_timer, jiffies + 5 * HZ);
1287 }
1288
1289 return 0;
1290}
1291
1292/*
1293 * atl2_link_chg_task - deal with link change event Out of interrupt context
1294 * @netdev: network interface device structure
1295 */
1296static void atl2_link_chg_task(struct work_struct *work)
1297{
1298 struct atl2_adapter *adapter;
1299 unsigned long flags;
1300
1301 adapter = container_of(work, struct atl2_adapter, link_chg_task);
1302
1303 spin_lock_irqsave(&adapter->stats_lock, flags);
1304 atl2_check_link(adapter);
1305 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1306}
1307
1308static void atl2_setup_pcicmd(struct pci_dev *pdev)
1309{
1310 u16 cmd;
1311
1312 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1313
1314 if (cmd & PCI_COMMAND_INTX_DISABLE)
1315 cmd &= ~PCI_COMMAND_INTX_DISABLE;
1316 if (cmd & PCI_COMMAND_IO)
1317 cmd &= ~PCI_COMMAND_IO;
1318 if (0 == (cmd & PCI_COMMAND_MEMORY))
1319 cmd |= PCI_COMMAND_MEMORY;
1320 if (0 == (cmd & PCI_COMMAND_MASTER))
1321 cmd |= PCI_COMMAND_MASTER;
1322 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1323
1324 /*
1325 * some motherboards BIOS(PXE/EFI) driver may set PME
1326 * while they transfer control to OS (Windows/Linux)
1327 * so we should clear this bit before NIC work normally
1328 */
1329 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
1330}
1331
8d1b1fc9
KH		 1332#ifdef CONFIG_NET_POLL_CONTROLLER
1333static void atl2_poll_controller(struct net_device *netdev)
1334{
1335 disable_irq(netdev->irq);
1336 atl2_intr(netdev->irq, netdev);
1337 enable_irq(netdev->irq);
1338}
1339#endif
1340
452c1ce2
CS		 1341/*
1342 * atl2_probe - Device Initialization Routine
1343 * @pdev: PCI device information struct
1344 * @ent: entry in atl2_pci_tbl
1345 *
1346 * Returns 0 on success, negative on failure
1347 *
1348 * atl2_probe initializes an adapter identified by a pci_dev structure.
1349 * The OS initialization, configuring of the adapter private structure,
1350 * and a hardware reset occur.
1351 */
1352static int __devinit atl2_probe(struct pci_dev *pdev,
1353 const struct pci_device_id *ent)
1354{
1355 struct net_device *netdev;
1356 struct atl2_adapter *adapter;
1357 static int cards_found;
1358 unsigned long mmio_start;
1359 int mmio_len;
1360 int err;
1361
1362 cards_found = 0;
1363
1364 err = pci_enable_device(pdev);
1365 if (err)
1366 return err;
1367
1368 /*
1369 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA
1370 * until the kernel has the proper infrastructure to support 64-bit DMA
1371 * on these devices.
1372 */
1373 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) &&
1374 pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
1375 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n");
1376 goto err_dma;
1377 }
1378
1379 /* Mark all PCI regions associated with PCI device
1380 * pdev as being reserved by owner atl2_driver_name */
1381 err = pci_request_regions(pdev, atl2_driver_name);
1382 if (err)
1383 goto err_pci_reg;
1384
1385 /* Enables bus-mastering on the device and calls
1386 * pcibios_set_master to do the needed arch specific settings */
1387 pci_set_master(pdev);
1388
1389 err = -ENOMEM;
1390 netdev = alloc_etherdev(sizeof(struct atl2_adapter));
1391 if (!netdev)
1392 goto err_alloc_etherdev;
1393
1394 SET_NETDEV_DEV(netdev, &pdev->dev);
1395
1396 pci_set_drvdata(pdev, netdev);
1397 adapter = netdev_priv(netdev);
1398 adapter->netdev = netdev;
1399 adapter->pdev = pdev;
1400 adapter->hw.back = adapter;
1401
1402 mmio_start = pci_resource_start(pdev, 0x0);
1403 mmio_len = pci_resource_len(pdev, 0x0);
1404
1405 adapter->hw.mem_rang = (u32)mmio_len;
1406 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1407 if (!adapter->hw.hw_addr) {
1408 err = -EIO;
1409 goto err_ioremap;
1410 }
1411
1412 atl2_setup_pcicmd(pdev);
1413
1414 netdev->open = &atl2_open;
1415 netdev->stop = &atl2_close;
1416 netdev->hard_start_xmit = &atl2_xmit_frame;
1417 netdev->get_stats = &atl2_get_stats;
1418 netdev->set_multicast_list = &atl2_set_multi;
1419 netdev->set_mac_address = &atl2_set_mac;
1420 netdev->change_mtu = &atl2_change_mtu;
1421 netdev->do_ioctl = &atl2_ioctl;
1422 atl2_set_ethtool_ops(netdev);
1423
8d1b1fc9
KH		 1424#ifdef CONFIG_NET_POLL_CONTROLLER
1425 netdev->poll_controller = atl2_poll_controller;
1426#endif
452c1ce2
CS		 1427#ifdef HAVE_TX_TIMEOUT
1428 netdev->tx_timeout = &atl2_tx_timeout;
1429 netdev->watchdog_timeo = 5 * HZ;
1430#endif
1431#ifdef NETIF_F_HW_VLAN_TX
1432 netdev->vlan_rx_register = atl2_vlan_rx_register;
1433#endif
1434 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1435
1436 netdev->mem_start = mmio_start;
1437 netdev->mem_end = mmio_start + mmio_len;
1438 adapter->bd_number = cards_found;
1439 adapter->pci_using_64 = false;
1440
1441 /* setup the private structure */
1442 err = atl2_sw_init(adapter);
1443 if (err)
1444 goto err_sw_init;
1445
1446 err = -EIO;
1447
1448#ifdef NETIF_F_HW_VLAN_TX
1449 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
1450#endif
1451
1452#ifdef NETIF_F_LLTX
1453 netdev->features |= NETIF_F_LLTX;
1454#endif
1455
1456 /* Init PHY as early as possible due to power saving issue */
1457 atl2_phy_init(&adapter->hw);
1458
1459 /* reset the controller to
1460 * put the device in a known good starting state */
1461
1462 if (atl2_reset_hw(&adapter->hw)) {
1463 err = -EIO;
1464 goto err_reset;
1465 }
1466
1467 /* copy the MAC address out of the EEPROM */
1468 atl2_read_mac_addr(&adapter->hw);
1469 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
1470/* FIXME: do we still need this? */
1471#ifdef ETHTOOL_GPERMADDR
1472 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1473
1474 if (!is_valid_ether_addr(netdev->perm_addr)) {
1475#else
1476 if (!is_valid_ether_addr(netdev->dev_addr)) {
1477#endif
1478 err = -EIO;
1479 goto err_eeprom;
1480 }
1481
1482 atl2_check_options(adapter);
1483
1484 init_timer(&adapter->watchdog_timer);
1485 adapter->watchdog_timer.function = &atl2_watchdog;
1486 adapter->watchdog_timer.data = (unsigned long) adapter;
1487
1488 init_timer(&adapter->phy_config_timer);
1489 adapter->phy_config_timer.function = &atl2_phy_config;
1490 adapter->phy_config_timer.data = (unsigned long) adapter;
1491
1492 INIT_WORK(&adapter->reset_task, atl2_reset_task);
1493 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task);
1494
1495 strcpy(netdev->name, "eth%d"); /* ?? */
1496 err = register_netdev(netdev);
1497 if (err)
1498 goto err_register;
1499
1500 /* assume we have no link for now */
1501 netif_carrier_off(netdev);
1502 netif_stop_queue(netdev);
1503
1504 cards_found++;
1505
1506 return 0;
1507
1508err_reset:
1509err_register:
1510err_sw_init:
1511err_eeprom:
1512 iounmap(adapter->hw.hw_addr);
1513err_ioremap:
1514 free_netdev(netdev);
1515err_alloc_etherdev:
1516 pci_release_regions(pdev);
1517err_pci_reg:
1518err_dma:
1519 pci_disable_device(pdev);
1520 return err;
1521}
1522
1523/*
1524 * atl2_remove - Device Removal Routine
1525 * @pdev: PCI device information struct
1526 *
1527 * atl2_remove is called by the PCI subsystem to alert the driver
1528 * that it should release a PCI device. The could be caused by a
1529 * Hot-Plug event, or because the driver is going to be removed from
1530 * memory.
1531 */
1532/* FIXME: write the original MAC address back in case it was changed from a
1533 * BIOS-set value, as in atl1 -- CHS */
1534static void __devexit atl2_remove(struct pci_dev *pdev)
1535{
1536 struct net_device *netdev = pci_get_drvdata(pdev);
1537 struct atl2_adapter *adapter = netdev_priv(netdev);
1538
1539 /* flush_scheduled work may reschedule our watchdog task, so
1540 * explicitly disable watchdog tasks from being rescheduled */
1541 set_bit(__ATL2_DOWN, &adapter->flags);
1542
1543 del_timer_sync(&adapter->watchdog_timer);
1544 del_timer_sync(&adapter->phy_config_timer);
1545
1546 flush_scheduled_work();
1547
1548 unregister_netdev(netdev);
1549
1550 atl2_force_ps(&adapter->hw);
1551
1552 iounmap(adapter->hw.hw_addr);
1553 pci_release_regions(pdev);
1554
1555 free_netdev(netdev);
1556
1557 pci_disable_device(pdev);
1558}
1559
1560static int atl2_suspend(struct pci_dev *pdev, pm_message_t state)
1561{
1562 struct net_device *netdev = pci_get_drvdata(pdev);
1563 struct atl2_adapter *adapter = netdev_priv(netdev);
1564 struct atl2_hw *hw = &adapter->hw;
1565 u16 speed, duplex;
1566 u32 ctrl = 0;
1567 u32 wufc = adapter->wol;
1568
1569#ifdef CONFIG_PM
1570 int retval = 0;
1571#endif
1572
1573 netif_device_detach(netdev);
1574
1575 if (netif_running(netdev)) {
1576 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
1577 atl2_down(adapter);
1578 }
1579
1580#ifdef CONFIG_PM
1581 retval = pci_save_state(pdev);
1582 if (retval)
1583 return retval;
1584#endif
1585
1586 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1587 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1588 if (ctrl & BMSR_LSTATUS)
1589 wufc &= ~ATLX_WUFC_LNKC;
1590
1591 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) {
1592 u32 ret_val;
1593 /* get current link speed & duplex */
1594 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1595 if (ret_val) {
1596 printk(KERN_DEBUG
1597 "%s: get speed&duplex error while suspend\n",
1598 atl2_driver_name);
1599 goto wol_dis;
1600 }
1601
1602 ctrl = 0;
1603
1604 /* turn on magic packet wol */
1605 if (wufc & ATLX_WUFC_MAG)
1606 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
1607
1608 /* ignore Link Chg event when Link is up */
1609 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1610
1611 /* Config MAC CTRL Register */
1612 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1613 if (FULL_DUPLEX == adapter->link_duplex)
1614 ctrl |= MAC_CTRL_DUPLX;
1615 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1616 ctrl |= (((u32)adapter->hw.preamble_len &
1617 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1618 ctrl |= (((u32)(adapter->hw.retry_buf &
1619 MAC_CTRL_HALF_LEFT_BUF_MASK)) <<
1620 MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1621 if (wufc & ATLX_WUFC_MAG) {
1622 /* magic packet maybe Broadcast&multicast&Unicast */
1623 ctrl |= MAC_CTRL_BC_EN;
1624 }
1625
1626 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);
1627
1628 /* pcie patch */
1629 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1630 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1631 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1632 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1633 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1634 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1635
1636 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1637 goto suspend_exit;
1638 }
1639
1640 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) {
1641 /* link is down, so only LINK CHG WOL event enable */
1642 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
1643 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1644 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);
1645
1646 /* pcie patch */
1647 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1648 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1649 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1650 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1651 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1652 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1653
1654 hw->phy_configured = false; /* re-init PHY when resume */
1655
1656 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1657
1658 goto suspend_exit;
1659 }
1660
1661wol_dis:
1662 /* WOL disabled */
1663 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);
1664
1665 /* pcie patch */
1666 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1667 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1668 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1669 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1670 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1671 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1672
1673 atl2_force_ps(hw);
1674 hw->phy_configured = false; /* re-init PHY when resume */
1675
1676 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1677
1678suspend_exit:
1679 if (netif_running(netdev))
1680 atl2_free_irq(adapter);
1681
1682 pci_disable_device(pdev);
1683
1684 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1685
1686 return 0;
1687}
1688
1689#ifdef CONFIG_PM
1690static int atl2_resume(struct pci_dev *pdev)
1691{
1692 struct net_device *netdev = pci_get_drvdata(pdev);
1693 struct atl2_adapter *adapter = netdev_priv(netdev);
1694 u32 err;
1695
1696 pci_set_power_state(pdev, PCI_D0);
1697 pci_restore_state(pdev);
1698
1699 err = pci_enable_device(pdev);
1700 if (err) {
1701 printk(KERN_ERR
1702 "atl2: Cannot enable PCI device from suspend\n");
1703 return err;
1704 }
1705
1706 pci_set_master(pdev);
1707
1708 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
1709
1710 pci_enable_wake(pdev, PCI_D3hot, 0);
1711 pci_enable_wake(pdev, PCI_D3cold, 0);
1712
1713 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
1714
1715 err = atl2_request_irq(adapter);
1716 if (netif_running(netdev) && err)
1717 return err;
1718
1719 atl2_reset_hw(&adapter->hw);
1720
1721 if (netif_running(netdev))
1722 atl2_up(adapter);
1723
1724 netif_device_attach(netdev);
1725
1726 return 0;
1727}
1728#endif
1729
1730static void atl2_shutdown(struct pci_dev *pdev)
1731{
1732 atl2_suspend(pdev, PMSG_SUSPEND);
1733}
1734
1735static struct pci_driver atl2_driver = {
1736 .name = atl2_driver_name,
1737 .id_table = atl2_pci_tbl,
1738 .probe = atl2_probe,
1739 .remove = __devexit_p(atl2_remove),
1740 /* Power Managment Hooks */
1741 .suspend = atl2_suspend,
1742#ifdef CONFIG_PM
1743 .resume = atl2_resume,
1744#endif
1745 .shutdown = atl2_shutdown,
1746};
1747
1748/*
1749 * atl2_init_module - Driver Registration Routine
1750 *
1751 * atl2_init_module is the first routine called when the driver is
1752 * loaded. All it does is register with the PCI subsystem.
1753 */
1754static int __init atl2_init_module(void)
1755{
1756 printk(KERN_INFO "%s - version %s\n", atl2_driver_string,
1757 atl2_driver_version);
1758 printk(KERN_INFO "%s\n", atl2_copyright);
1759 return pci_register_driver(&atl2_driver);
1760}
1761module_init(atl2_init_module);
1762
1763/*
1764 * atl2_exit_module - Driver Exit Cleanup Routine
1765 *
1766 * atl2_exit_module is called just before the driver is removed
1767 * from memory.
1768 */
1769static void __exit atl2_exit_module(void)
1770{
1771 pci_unregister_driver(&atl2_driver);
1772}
1773module_exit(atl2_exit_module);
1774
1775static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1776{
1777 struct atl2_adapter *adapter = hw->back;
1778 pci_read_config_word(adapter->pdev, reg, value);
1779}
1780
1781static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1782{
1783 struct atl2_adapter *adapter = hw->back;
1784 pci_write_config_word(adapter->pdev, reg, *value);
1785}
1786
1787static int atl2_get_settings(struct net_device *netdev,
1788 struct ethtool_cmd *ecmd)
1789{
1790 struct atl2_adapter *adapter = netdev_priv(netdev);
1791 struct atl2_hw *hw = &adapter->hw;
1792
1793 ecmd->supported = (SUPPORTED_10baseT_Half |
1794 SUPPORTED_10baseT_Full |
1795 SUPPORTED_100baseT_Half |
1796 SUPPORTED_100baseT_Full |
1797 SUPPORTED_Autoneg |
1798 SUPPORTED_TP);
1799 ecmd->advertising = ADVERTISED_TP;
1800
1801 ecmd->advertising |= ADVERTISED_Autoneg;
1802 ecmd->advertising |= hw->autoneg_advertised;
1803
1804 ecmd->port = PORT_TP;
1805 ecmd->phy_address = 0;
1806 ecmd->transceiver = XCVR_INTERNAL;
1807
1808 if (adapter->link_speed != SPEED_0) {
1809 ecmd->speed = adapter->link_speed;
1810 if (adapter->link_duplex == FULL_DUPLEX)
1811 ecmd->duplex = DUPLEX_FULL;
1812 else
1813 ecmd->duplex = DUPLEX_HALF;
1814 } else {
1815 ecmd->speed = -1;
1816 ecmd->duplex = -1;
1817 }
1818
1819 ecmd->autoneg = AUTONEG_ENABLE;
1820 return 0;
1821}
1822
1823static int atl2_set_settings(struct net_device *netdev,
1824 struct ethtool_cmd *ecmd)
1825{
1826 struct atl2_adapter *adapter = netdev_priv(netdev);
1827 struct atl2_hw *hw = &adapter->hw;
1828
1829 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1830 msleep(1);
1831
1832 if (ecmd->autoneg == AUTONEG_ENABLE) {
1833#define MY_ADV_MASK (ADVERTISE_10_HALF | \
1834 ADVERTISE_10_FULL | \
1835 ADVERTISE_100_HALF| \
1836 ADVERTISE_100_FULL)
1837
1838 if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) {
1839 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR;
1840 hw->autoneg_advertised = MY_ADV_MASK;
1841 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1842 ADVERTISE_100_FULL) {
1843 hw->MediaType = MEDIA_TYPE_100M_FULL;
1844 hw->autoneg_advertised = ADVERTISE_100_FULL;
1845 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1846 ADVERTISE_100_HALF) {
1847 hw->MediaType = MEDIA_TYPE_100M_HALF;
1848 hw->autoneg_advertised = ADVERTISE_100_HALF;
1849 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1850 ADVERTISE_10_FULL) {
1851 hw->MediaType = MEDIA_TYPE_10M_FULL;
1852 hw->autoneg_advertised = ADVERTISE_10_FULL;
1853 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1854 ADVERTISE_10_HALF) {
1855 hw->MediaType = MEDIA_TYPE_10M_HALF;
1856 hw->autoneg_advertised = ADVERTISE_10_HALF;
1857 } else {
1858 clear_bit(__ATL2_RESETTING, &adapter->flags);
1859 return -EINVAL;
1860 }
1861 ecmd->advertising = hw->autoneg_advertised |
1862 ADVERTISED_TP | ADVERTISED_Autoneg;
1863 } else {
1864 clear_bit(__ATL2_RESETTING, &adapter->flags);
1865 return -EINVAL;
1866 }
1867
1868 /* reset the link */
1869 if (netif_running(adapter->netdev)) {
1870 atl2_down(adapter);
1871 atl2_up(adapter);
1872 } else
1873 atl2_reset_hw(&adapter->hw);
1874
1875 clear_bit(__ATL2_RESETTING, &adapter->flags);
1876 return 0;
1877}
1878
1879static u32 atl2_get_tx_csum(struct net_device *netdev)
1880{
1881 return (netdev->features & NETIF_F_HW_CSUM) != 0;
1882}
1883
1884static u32 atl2_get_msglevel(struct net_device *netdev)
1885{
1886 return 0;
1887}
1888
1889/*
1890 * It's sane for this to be empty, but we might want to take advantage of this.
1891 */
1892static void atl2_set_msglevel(struct net_device *netdev, u32 data)
1893{
1894}
1895
1896static int atl2_get_regs_len(struct net_device *netdev)
1897{
1898#define ATL2_REGS_LEN 42
1899 return sizeof(u32) * ATL2_REGS_LEN;
1900}
1901
1902static void atl2_get_regs(struct net_device *netdev,
1903 struct ethtool_regs *regs, void *p)
1904{
1905 struct atl2_adapter *adapter = netdev_priv(netdev);
1906 struct atl2_hw *hw = &adapter->hw;
1907 u32 *regs_buff = p;
1908 u16 phy_data;
1909
1910 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN);
1911
1912 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
1913
1914 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP);
1915 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
1916 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG);
1917 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL);
1918 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
1919 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL);
1920 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT);
1921 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
1922 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE);
1923 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER);
1924 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS);
1925 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL);
1926 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK);
1927 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL);
1928 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG);
1929 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
1930 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4);
1931 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE);
1932 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4);
1933 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
1934 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU);
1935 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL);
1936 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END);
1937 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI);
1938 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO);
1939 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE);
1940 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO);
1941 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE);
1942 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO);
1943 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM);
1944 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR);
1945 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH);
1946 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW);
1947 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH);
1948 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH);
1949 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX);
1950 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX);
1951 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR);
1952 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR);
1953
1954 atl2_read_phy_reg(hw, MII_BMCR, &phy_data);
1955 regs_buff[40] = (u32)phy_data;
1956 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1957 regs_buff[41] = (u32)phy_data;
1958}
1959
1960static int atl2_get_eeprom_len(struct net_device *netdev)
1961{
1962 struct atl2_adapter *adapter = netdev_priv(netdev);
1963
1964 if (!atl2_check_eeprom_exist(&adapter->hw))
1965 return 512;
1966 else
1967 return 0;
1968}
1969
1970static int atl2_get_eeprom(struct net_device *netdev,
1971 struct ethtool_eeprom *eeprom, u8 *bytes)
1972{
1973 struct atl2_adapter *adapter = netdev_priv(netdev);
1974 struct atl2_hw *hw = &adapter->hw;
1975 u32 *eeprom_buff;
1976 int first_dword, last_dword;
1977 int ret_val = 0;
1978 int i;
1979
1980 if (eeprom->len == 0)
1981 return -EINVAL;
1982
1983 if (atl2_check_eeprom_exist(hw))
1984 return -EINVAL;
1985
1986 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1987
1988 first_dword = eeprom->offset >> 2;
1989 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1990
1991 eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1),
1992 GFP_KERNEL);
1993 if (!eeprom_buff)
1994 return -ENOMEM;
1995
1996 for (i = first_dword; i < last_dword; i++) {
1997 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword])))
1998 return -EIO;
1999 }
2000
2001 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
2002 eeprom->len);
2003 kfree(eeprom_buff);
2004
2005 return ret_val;
2006}
2007
2008static int atl2_set_eeprom(struct net_device *netdev,
2009 struct ethtool_eeprom *eeprom, u8 *bytes)
2010{
2011 struct atl2_adapter *adapter = netdev_priv(netdev);
2012 struct atl2_hw *hw = &adapter->hw;
2013 u32 *eeprom_buff;
2014 u32 *ptr;
2015 int max_len, first_dword, last_dword, ret_val = 0;
2016 int i;
2017
2018 if (eeprom->len == 0)
2019 return -EOPNOTSUPP;
2020
2021 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
2022 return -EFAULT;
2023
2024 max_len = 512;
2025
2026 first_dword = eeprom->offset >> 2;
2027 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
2028 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
2029 if (!eeprom_buff)
2030 return -ENOMEM;
2031
2032 ptr = (u32 *)eeprom_buff;
2033
2034 if (eeprom->offset & 3) {
2035 /* need read/modify/write of first changed EEPROM word */
2036 /* only the second byte of the word is being modified */
2037 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0])))
2038 return -EIO;
2039 ptr++;
2040 }
2041 if (((eeprom->offset + eeprom->len) & 3)) {
2042 /*
2043 * need read/modify/write of last changed EEPROM word
2044 * only the first byte of the word is being modified
2045 */
2046 if (!atl2_read_eeprom(hw, last_dword * 4,
2047 &(eeprom_buff[last_dword - first_dword])))
2048 return -EIO;
2049 }
2050
2051 /* Device's eeprom is always little-endian, word addressable */
2052 memcpy(ptr, bytes, eeprom->len);
2053
2054 for (i = 0; i < last_dword - first_dword + 1; i++) {
2055 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i]))
2056 return -EIO;
2057 }
2058
2059 kfree(eeprom_buff);
2060 return ret_val;
2061}
2062
2063static void atl2_get_drvinfo(struct net_device *netdev,
2064 struct ethtool_drvinfo *drvinfo)
2065{
2066 struct atl2_adapter *adapter = netdev_priv(netdev);
2067
2068 strncpy(drvinfo->driver, atl2_driver_name, 32);
2069 strncpy(drvinfo->version, atl2_driver_version, 32);
2070 strncpy(drvinfo->fw_version, "L2", 32);
2071 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
2072 drvinfo->n_stats = 0;
2073 drvinfo->testinfo_len = 0;
2074 drvinfo->regdump_len = atl2_get_regs_len(netdev);
2075 drvinfo->eedump_len = atl2_get_eeprom_len(netdev);
2076}
2077
2078static void atl2_get_wol(struct net_device *netdev,
2079 struct ethtool_wolinfo *wol)
2080{
2081 struct atl2_adapter *adapter = netdev_priv(netdev);
2082
2083 wol->supported = WAKE_MAGIC;
2084 wol->wolopts = 0;
2085
2086 if (adapter->wol & ATLX_WUFC_EX)
2087 wol->wolopts |= WAKE_UCAST;
2088 if (adapter->wol & ATLX_WUFC_MC)
2089 wol->wolopts |= WAKE_MCAST;
2090 if (adapter->wol & ATLX_WUFC_BC)
2091 wol->wolopts |= WAKE_BCAST;
2092 if (adapter->wol & ATLX_WUFC_MAG)
2093 wol->wolopts |= WAKE_MAGIC;
2094 if (adapter->wol & ATLX_WUFC_LNKC)
2095 wol->wolopts |= WAKE_PHY;
2096}
2097
2098static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2099{
2100 struct atl2_adapter *adapter = netdev_priv(netdev);
2101
2102 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2103 return -EOPNOTSUPP;
2104
2105 if (wol->wolopts & (WAKE_MCAST|WAKE_BCAST|WAKE_MCAST))
2106 return -EOPNOTSUPP;
2107
2108 /* these settings will always override what we currently have */
2109 adapter->wol = 0;
2110
2111 if (wol->wolopts & WAKE_MAGIC)
2112 adapter->wol |= ATLX_WUFC_MAG;
2113 if (wol->wolopts & WAKE_PHY)
2114 adapter->wol |= ATLX_WUFC_LNKC;
2115
2116 return 0;
2117}
2118
2119static int atl2_nway_reset(struct net_device *netdev)
2120{
2121 struct atl2_adapter *adapter = netdev_priv(netdev);
2122 if (netif_running(netdev))
2123 atl2_reinit_locked(adapter);
2124 return 0;
2125}
2126
2127static struct ethtool_ops atl2_ethtool_ops = {
2128 .get_settings = atl2_get_settings,
2129 .set_settings = atl2_set_settings,
2130 .get_drvinfo = atl2_get_drvinfo,
2131 .get_regs_len = atl2_get_regs_len,
2132 .get_regs = atl2_get_regs,
2133 .get_wol = atl2_get_wol,
2134 .set_wol = atl2_set_wol,
2135 .get_msglevel = atl2_get_msglevel,
2136 .set_msglevel = atl2_set_msglevel,
2137 .nway_reset = atl2_nway_reset,
2138 .get_link = ethtool_op_get_link,
2139 .get_eeprom_len = atl2_get_eeprom_len,
2140 .get_eeprom = atl2_get_eeprom,
2141 .set_eeprom = atl2_set_eeprom,
2142 .get_tx_csum = atl2_get_tx_csum,
2143 .get_sg = ethtool_op_get_sg,
2144 .set_sg = ethtool_op_set_sg,
2145#ifdef NETIF_F_TSO
2146 .get_tso = ethtool_op_get_tso,
2147#endif
2148};
2149
2150static void atl2_set_ethtool_ops(struct net_device *netdev)
2151{
2152 SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops);
2153}
2154
2155#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
2156 (((a) & 0xff00ff00) >> 8))
2157#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
2158#define SHORTSWAP(a) (((a) << 8) | ((a) >> 8))
2159
2160/*
2161 * Reset the transmit and receive units; mask and clear all interrupts.
2162 *
2163 * hw - Struct containing variables accessed by shared code
2164 * return : 0 or idle status (if error)
2165 */
2166static s32 atl2_reset_hw(struct atl2_hw *hw)
2167{
2168 u32 icr;
2169 u16 pci_cfg_cmd_word;
2170 int i;
2171
2172 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
2173 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2174 if ((pci_cfg_cmd_word &
2175 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) !=
2176 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) {
2177 pci_cfg_cmd_word |=
2178 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER);
2179 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2180 }
2181
2182 /* Clear Interrupt mask to stop board from generating
2183 * interrupts & Clear any pending interrupt events
2184 */
2185 /* FIXME */
2186 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */
2187 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */
2188
2189 /* Issue Soft Reset to the MAC. This will reset the chip's
2190 * transmit, receive, DMA. It will not effect
2191 * the current PCI configuration. The global reset bit is self-
2192 * clearing, and should clear within a microsecond.
2193 */
2194 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
2195 wmb();
2196 msleep(1); /* delay about 1ms */
2197
2198 /* Wait at least 10ms for All module to be Idle */
2199 for (i = 0; i < 10; i++) {
2200 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS);
2201 if (!icr)
2202 break;
2203 msleep(1); /* delay 1 ms */
2204 cpu_relax();
2205 }
2206
2207 if (icr)
2208 return icr;
2209
2210 return 0;
2211}
2212
2213#define CUSTOM_SPI_CS_SETUP 2
2214#define CUSTOM_SPI_CLK_HI 2
2215#define CUSTOM_SPI_CLK_LO 2
2216#define CUSTOM_SPI_CS_HOLD 2
2217#define CUSTOM_SPI_CS_HI 3
2218
2219static struct atl2_spi_flash_dev flash_table[] =
2220{
2221/* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
2222{"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 },
2223{"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 },
2224{"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 },
2225};
2226
2227static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf)
2228{
2229 int i;
2230 u32 value;
2231
2232 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);
2233 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);
2234
2235 value = SPI_FLASH_CTRL_WAIT_READY |
2236 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
2237 SPI_FLASH_CTRL_CS_SETUP_SHIFT |
2238 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) <<
2239 SPI_FLASH_CTRL_CLK_HI_SHIFT |
2240 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) <<
2241 SPI_FLASH_CTRL_CLK_LO_SHIFT |
2242 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) <<
2243 SPI_FLASH_CTRL_CS_HOLD_SHIFT |
2244 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) <<
2245 SPI_FLASH_CTRL_CS_HI_SHIFT |
2246 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT;
2247
2248 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2249
2250 value |= SPI_FLASH_CTRL_START;
2251
2252 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2253
2254 for (i = 0; i < 10; i++) {
2255 msleep(1);
2256 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2257 if (!(value & SPI_FLASH_CTRL_START))
2258 break;
2259 }
2260
2261 if (value & SPI_FLASH_CTRL_START)
2262 return false;
2263
2264 *buf = ATL2_READ_REG(hw, REG_SPI_DATA);
2265
2266 return true;
2267}
2268
2269/*
2270 * get_permanent_address
2271 * return 0 if get valid mac address,
2272 */
2273static int get_permanent_address(struct atl2_hw *hw)
2274{
2275 u32 Addr[2];
2276 u32 i, Control;
2277 u16 Register;
2278 u8 EthAddr[NODE_ADDRESS_SIZE];
2279 bool KeyValid;
2280
2281 if (is_valid_ether_addr(hw->perm_mac_addr))
2282 return 0;
2283
2284 Addr[0] = 0;
2285 Addr[1] = 0;
2286
2287 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */
2288 Register = 0;
2289 KeyValid = false;
2290
2291 /* Read out all EEPROM content */
2292 i = 0;
2293 while (1) {
2294 if (atl2_read_eeprom(hw, i + 0x100, &Control)) {
2295 if (KeyValid) {
2296 if (Register == REG_MAC_STA_ADDR)
2297 Addr[0] = Control;
2298 else if (Register ==
2299 (REG_MAC_STA_ADDR + 4))
2300 Addr[1] = Control;
2301 KeyValid = false;
2302 } else if ((Control & 0xff) == 0x5A) {
2303 KeyValid = true;
2304 Register = (u16) (Control >> 16);
2305 } else {
2306 /* assume data end while encount an invalid KEYWORD */
2307 break;
2308 }
2309 } else {
2310 break; /* read error */
2311 }
2312 i += 4;
2313 }
2314
2315 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2316 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2317
2318 if (is_valid_ether_addr(EthAddr)) {
2319 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2320 return 0;
2321 }
2322 return 1;
2323 }
2324
2325 /* see if SPI flash exists? */
2326 Addr[0] = 0;
2327 Addr[1] = 0;
2328 Register = 0;
2329 KeyValid = false;
2330 i = 0;
2331 while (1) {
2332 if (atl2_spi_read(hw, i + 0x1f000, &Control)) {
2333 if (KeyValid) {
2334 if (Register == REG_MAC_STA_ADDR)
2335 Addr[0] = Control;
2336 else if (Register == (REG_MAC_STA_ADDR + 4))
2337 Addr[1] = Control;
2338 KeyValid = false;
2339 } else if ((Control & 0xff) == 0x5A) {
2340 KeyValid = true;
2341 Register = (u16) (Control >> 16);
2342 } else {
2343 break; /* data end */
2344 }
2345 } else {
2346 break; /* read error */
2347 }
2348 i += 4;
2349 }
2350
2351 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2352 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]);
2353 if (is_valid_ether_addr(EthAddr)) {
2354 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2355 return 0;
2356 }
2357 /* maybe MAC-address is from BIOS */
2358 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
2359 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4);
2360 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2361 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2362
2363 if (is_valid_ether_addr(EthAddr)) {
2364 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2365 return 0;
2366 }
2367
2368 return 1;
2369}
2370
2371/*
2372 * Reads the adapter's MAC address from the EEPROM
2373 *
2374 * hw - Struct containing variables accessed by shared code
2375 */
2376static s32 atl2_read_mac_addr(struct atl2_hw *hw)
2377{
2378 u16 i;
2379
2380 if (get_permanent_address(hw)) {
2381 /* for test */
2382 /* FIXME: shouldn't we use random_ether_addr() here? */
2383 hw->perm_mac_addr[0] = 0x00;
2384 hw->perm_mac_addr[1] = 0x13;
2385 hw->perm_mac_addr[2] = 0x74;
2386 hw->perm_mac_addr[3] = 0x00;
2387 hw->perm_mac_addr[4] = 0x5c;
2388 hw->perm_mac_addr[5] = 0x38;
2389 }
2390
2391 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
2392 hw->mac_addr[i] = hw->perm_mac_addr[i];
2393
2394 return 0;
2395}
2396
2397/*
2398 * Hashes an address to determine its location in the multicast table
2399 *
2400 * hw - Struct containing variables accessed by shared code
2401 * mc_addr - the multicast address to hash
2402 *
2403 * atl2_hash_mc_addr
2404 * purpose
2405 * set hash value for a multicast address
2406 * hash calcu processing :
2407 * 1. calcu 32bit CRC for multicast address
2408 * 2. reverse crc with MSB to LSB
2409 */
2410static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr)
2411{
2412 u32 crc32, value;
2413 int i;
2414
2415 value = 0;
2416 crc32 = ether_crc_le(6, mc_addr);
2417
2418 for (i = 0; i < 32; i++)
2419 value |= (((crc32 >> i) & 1) << (31 - i));
2420
2421 return value;
2422}
2423
2424/*
2425 * Sets the bit in the multicast table corresponding to the hash value.
2426 *
2427 * hw - Struct containing variables accessed by shared code
2428 * hash_value - Multicast address hash value
2429 */
2430static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value)
2431{
2432 u32 hash_bit, hash_reg;
2433 u32 mta;
2434
2435 /* The HASH Table is a register array of 2 32-bit registers.
2436 * It is treated like an array of 64 bits. We want to set
2437 * bit BitArray[hash_value]. So we figure out what register
2438 * the bit is in, read it, OR in the new bit, then write
2439 * back the new value. The register is determined by the
2440 * upper 7 bits of the hash value and the bit within that
2441 * register are determined by the lower 5 bits of the value.
2442 */
2443 hash_reg = (hash_value >> 31) & 0x1;
2444 hash_bit = (hash_value >> 26) & 0x1F;
2445
2446 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
2447
2448 mta |= (1 << hash_bit);
2449
2450 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
2451}
2452
2453/*
2454 * atl2_init_pcie - init PCIE module
2455 */
2456static void atl2_init_pcie(struct atl2_hw *hw)
2457{
2458 u32 value;
2459 value = LTSSM_TEST_MODE_DEF;
2460 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
2461
2462 value = PCIE_DLL_TX_CTRL1_DEF;
2463 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);
2464}
2465
2466static void atl2_init_flash_opcode(struct atl2_hw *hw)
2467{
2468 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
2469 hw->flash_vendor = 0; /* ATMEL */
2470
2471 /* Init OP table */
2472 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM,
2473 flash_table[hw->flash_vendor].cmdPROGRAM);
2474 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE,
2475 flash_table[hw->flash_vendor].cmdSECTOR_ERASE);
2476 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE,
2477 flash_table[hw->flash_vendor].cmdCHIP_ERASE);
2478 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID,
2479 flash_table[hw->flash_vendor].cmdRDID);
2480 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN,
2481 flash_table[hw->flash_vendor].cmdWREN);
2482 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR,
2483 flash_table[hw->flash_vendor].cmdRDSR);
2484 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR,
2485 flash_table[hw->flash_vendor].cmdWRSR);
2486 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ,
2487 flash_table[hw->flash_vendor].cmdREAD);
2488}
2489
2490/********************************************************************
2491* Performs basic configuration of the adapter.
2492*
2493* hw - Struct containing variables accessed by shared code
2494* Assumes that the controller has previously been reset and is in a
2495* post-reset uninitialized state. Initializes multicast table,
2496* and Calls routines to setup link
2497* Leaves the transmit and receive units disabled and uninitialized.
2498********************************************************************/
2499static s32 atl2_init_hw(struct atl2_hw *hw)
2500{
2501 u32 ret_val = 0;
2502
2503 atl2_init_pcie(hw);
2504
2505 /* Zero out the Multicast HASH table */
2506 /* clear the old settings from the multicast hash table */
2507 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
2508 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
2509
2510 atl2_init_flash_opcode(hw);
2511
2512 ret_val = atl2_phy_init(hw);
2513
2514 return ret_val;
2515}
2516
2517/*
2518 * Detects the current speed and duplex settings of the hardware.
2519 *
2520 * hw - Struct containing variables accessed by shared code
2521 * speed - Speed of the connection
2522 * duplex - Duplex setting of the connection
2523 */
2524static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
2525 u16 *duplex)
2526{
2527 s32 ret_val;
2528 u16 phy_data;
2529
2530 /* Read PHY Specific Status Register (17) */
2531 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
2532 if (ret_val)
2533 return ret_val;
2534
2535 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
2536 return ATLX_ERR_PHY_RES;
2537
2538 switch (phy_data & MII_ATLX_PSSR_SPEED) {
2539 case MII_ATLX_PSSR_100MBS:
2540 *speed = SPEED_100;
2541 break;
2542 case MII_ATLX_PSSR_10MBS:
2543 *speed = SPEED_10;
2544 break;
2545 default:
2546 return ATLX_ERR_PHY_SPEED;
2547 break;
2548 }
2549
2550 if (phy_data & MII_ATLX_PSSR_DPLX)
2551 *duplex = FULL_DUPLEX;
2552 else
2553 *duplex = HALF_DUPLEX;
2554
2555 return 0;
2556}
2557
2558/*
2559 * Reads the value from a PHY register
2560 * hw - Struct containing variables accessed by shared code
2561 * reg_addr - address of the PHY register to read
2562 */
2563static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data)
2564{
2565 u32 val;
2566 int i;
2567
2568 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
2569 MDIO_START |
2570 MDIO_SUP_PREAMBLE |
2571 MDIO_RW |
2572 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2573 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2574
2575 wmb();
2576
2577 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2578 udelay(2);
2579 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2580 if (!(val & (MDIO_START | MDIO_BUSY)))
2581 break;
2582 wmb();
2583 }
2584 if (!(val & (MDIO_START | MDIO_BUSY))) {
2585 *phy_data = (u16)val;
2586 return 0;
2587 }
2588
2589 return ATLX_ERR_PHY;
2590}
2591
2592/*
2593 * Writes a value to a PHY register
2594 * hw - Struct containing variables accessed by shared code
2595 * reg_addr - address of the PHY register to write
2596 * data - data to write to the PHY
2597 */
2598static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data)
2599{
2600 int i;
2601 u32 val;
2602
2603 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
2604 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
2605 MDIO_SUP_PREAMBLE |
2606 MDIO_START |
2607 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2608 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2609
2610 wmb();
2611
2612 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2613 udelay(2);
2614 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2615 if (!(val & (MDIO_START | MDIO_BUSY)))
2616 break;
2617
2618 wmb();
2619 }
2620
2621 if (!(val & (MDIO_START | MDIO_BUSY)))
2622 return 0;
2623
2624 return ATLX_ERR_PHY;
2625}
2626
2627/*
2628 * Configures PHY autoneg and flow control advertisement settings
2629 *
2630 * hw - Struct containing variables accessed by shared code
2631 */
2632static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw)
2633{
2634 s32 ret_val;
2635 s16 mii_autoneg_adv_reg;
2636
2637 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2638 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
2639
2640 /* Need to parse autoneg_advertised and set up
2641 * the appropriate PHY registers. First we will parse for
2642 * autoneg_advertised software override. Since we can advertise
2643 * a plethora of combinations, we need to check each bit
2644 * individually.
2645 */
2646
2647 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2648 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2649 * the 1000Base-T Control Register (Address 9). */
2650 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
2651
2652 /* Need to parse MediaType and setup the
2653 * appropriate PHY registers. */
2654 switch (hw->MediaType) {
2655 case MEDIA_TYPE_AUTO_SENSOR:
2656 mii_autoneg_adv_reg |=
2657 (MII_AR_10T_HD_CAPS |
2658 MII_AR_10T_FD_CAPS |
2659 MII_AR_100TX_HD_CAPS|
2660 MII_AR_100TX_FD_CAPS);
2661 hw->autoneg_advertised =
2662 ADVERTISE_10_HALF |
2663 ADVERTISE_10_FULL |
2664 ADVERTISE_100_HALF|
2665 ADVERTISE_100_FULL;
2666 break;
2667 case MEDIA_TYPE_100M_FULL:
2668 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
2669 hw->autoneg_advertised = ADVERTISE_100_FULL;
2670 break;
2671 case MEDIA_TYPE_100M_HALF:
2672 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
2673 hw->autoneg_advertised = ADVERTISE_100_HALF;
2674 break;
2675 case MEDIA_TYPE_10M_FULL:
2676 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
2677 hw->autoneg_advertised = ADVERTISE_10_FULL;
2678 break;
2679 default:
2680 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
2681 hw->autoneg_advertised = ADVERTISE_10_HALF;
2682 break;
2683 }
2684
2685 /* flow control fixed to enable all */
2686 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
2687
2688 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
2689
2690 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
2691
2692 if (ret_val)
2693 return ret_val;
2694
2695 return 0;
2696}
2697
2698/*
2699 * Resets the PHY and make all config validate
2700 *
2701 * hw - Struct containing variables accessed by shared code
2702 *
2703 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
2704 */
2705static s32 atl2_phy_commit(struct atl2_hw *hw)
2706{
2707 s32 ret_val;
2708 u16 phy_data;
2709
2710 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2711 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data);
2712 if (ret_val) {
2713 u32 val;
2714 int i;
2715 /* pcie serdes link may be down ! */
2716 for (i = 0; i < 25; i++) {
2717 msleep(1);
2718 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2719 if (!(val & (MDIO_START | MDIO_BUSY)))
2720 break;
2721 }
2722
2723 if (0 != (val & (MDIO_START | MDIO_BUSY))) {
2724 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n");
2725 return ret_val;
2726 }
2727 }
2728 return 0;
2729}
2730
2731static s32 atl2_phy_init(struct atl2_hw *hw)
2732{
2733 s32 ret_val;
2734 u16 phy_val;
2735
2736 if (hw->phy_configured)
2737 return 0;
2738
2739 /* Enable PHY */
2740 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1);
2741 ATL2_WRITE_FLUSH(hw);
2742 msleep(1);
2743
2744 /* check if the PHY is in powersaving mode */
2745 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2746 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2747
2748 /* 024E / 124E 0r 0274 / 1274 ? */
2749 if (phy_val & 0x1000) {
2750 phy_val &= ~0x1000;
2751 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val);
2752 }
2753
2754 msleep(1);
2755
2756 /*Enable PHY LinkChange Interrupt */
2757 ret_val = atl2_write_phy_reg(hw, 18, 0xC00);
2758 if (ret_val)
2759 return ret_val;
2760
2761 /* setup AutoNeg parameters */
2762 ret_val = atl2_phy_setup_autoneg_adv(hw);
2763 if (ret_val)
2764 return ret_val;
2765
2766 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */
2767 ret_val = atl2_phy_commit(hw);
2768 if (ret_val)
2769 return ret_val;
2770
2771 hw->phy_configured = true;
2772
2773 return ret_val;
2774}
2775
2776static void atl2_set_mac_addr(struct atl2_hw *hw)
2777{
2778 u32 value;
2779 /* 00-0B-6A-F6-00-DC
2780 * 0: 6AF600DC 1: 000B
2781 * low dword */
2782 value = (((u32)hw->mac_addr[2]) << 24) |
2783 (((u32)hw->mac_addr[3]) << 16) |
2784 (((u32)hw->mac_addr[4]) << 8) |
2785 (((u32)hw->mac_addr[5]));
2786 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
2787 /* hight dword */
2788 value = (((u32)hw->mac_addr[0]) << 8) |
2789 (((u32)hw->mac_addr[1]));
2790 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
2791}
2792
2793/*
2794 * check_eeprom_exist
2795 * return 0 if eeprom exist
2796 */
2797static int atl2_check_eeprom_exist(struct atl2_hw *hw)
2798{
2799 u32 value;
2800
2801 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2802 if (value & SPI_FLASH_CTRL_EN_VPD) {
2803 value &= ~SPI_FLASH_CTRL_EN_VPD;
2804 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2805 }
2806 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST);
2807 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
2808}
2809
2810/* FIXME: This doesn't look right. -- CHS */
2811static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value)
2812{
2813 return true;
2814}
2815
2816static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue)
2817{
2818 int i;
2819 u32 Control;
2820
2821 if (Offset & 0x3)
2822 return false; /* address do not align */
2823
2824 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);
2825 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
2826 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);
2827
2828 for (i = 0; i < 10; i++) {
2829 msleep(2);
2830 Control = ATL2_READ_REG(hw, REG_VPD_CAP);
2831 if (Control & VPD_CAP_VPD_FLAG)
2832 break;
2833 }
2834
2835 if (Control & VPD_CAP_VPD_FLAG) {
2836 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA);
2837 return true;
2838 }
2839 return false; /* timeout */
2840}
2841
2842static void atl2_force_ps(struct atl2_hw *hw)
2843{
2844 u16 phy_val;
2845
2846 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2847 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2848 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000);
2849
2850 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2);
2851 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
2852 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3);
2853 atl2_write_phy_reg(hw, MII_DBG_DATA, 0);
2854}
2855
2856/* This is the only thing that needs to be changed to adjust the
2857 * maximum number of ports that the driver can manage.
2858 */
2859#define ATL2_MAX_NIC 4
2860
2861#define OPTION_UNSET -1
2862#define OPTION_DISABLED 0
2863#define OPTION_ENABLED 1
2864
2865/* All parameters are treated the same, as an integer array of values.
2866 * This macro just reduces the need to repeat the same declaration code
2867 * over and over (plus this helps to avoid typo bugs).
2868 */
2869#define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET}
2870#ifndef module_param_array
2871/* Module Parameters are always initialized to -1, so that the driver
2872 * can tell the difference between no user specified value or the
2873 * user asking for the default value.
2874 * The true default values are loaded in when atl2_check_options is called.
2875 *
2876 * This is a GCC extension to ANSI C.
2877 * See the item "Labeled Elements in Initializers" in the section
2878 * "Extensions to the C Language Family" of the GCC documentation.
2879 */
2880
2881#define ATL2_PARAM(X, desc) \
2882 static const int __devinitdata X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \
2883 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \
2884 MODULE_PARM_DESC(X, desc);
2885#else
2886#define ATL2_PARAM(X, desc) \
2887 static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \
2888 static int num_##X = 0; \
2889 module_param_array_named(X, X, int, &num_##X, 0); \
2890 MODULE_PARM_DESC(X, desc);
2891#endif
2892
2893/*
2894 * Transmit Memory Size
2895 * Valid Range: 64-2048
2896 * Default Value: 128
2897 */
2898#define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */
2899#define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */
2900#define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */
2901ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory");
2902
2903/*
2904 * Receive Memory Block Count
2905 * Valid Range: 16-512
2906 * Default Value: 128
2907 */
2908#define ATL2_MIN_RXD_COUNT 16
2909#define ATL2_MAX_RXD_COUNT 512
2910#define ATL2_DEFAULT_RXD_COUNT 64
2911ATL2_PARAM(RxMemBlock, "Number of receive memory block");
2912
2913/*
2914 * User Specified MediaType Override
2915 *
2916 * Valid Range: 0-5
2917 * - 0 - auto-negotiate at all supported speeds
2918 * - 1 - only link at 1000Mbps Full Duplex
2919 * - 2 - only link at 100Mbps Full Duplex
2920 * - 3 - only link at 100Mbps Half Duplex
2921 * - 4 - only link at 10Mbps Full Duplex
2922 * - 5 - only link at 10Mbps Half Duplex
2923 * Default Value: 0
2924 */
2925ATL2_PARAM(MediaType, "MediaType Select");
2926
2927/*
2928 * Interrupt Moderate Timer in units of 2048 ns (~2 us)
2929 * Valid Range: 10-65535
2930 * Default Value: 45000(90ms)
2931 */
2932#define INT_MOD_DEFAULT_CNT 100 /* 200us */
2933#define INT_MOD_MAX_CNT 65000
2934#define INT_MOD_MIN_CNT 50
2935ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer");
2936
2937/*
2938 * FlashVendor
2939 * Valid Range: 0-2
2940 * 0 - Atmel
2941 * 1 - SST
2942 * 2 - ST
2943 */
2944ATL2_PARAM(FlashVendor, "SPI Flash Vendor");
2945
2946#define AUTONEG_ADV_DEFAULT 0x2F
2947#define AUTONEG_ADV_MASK 0x2F
2948#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
2949
2950#define FLASH_VENDOR_DEFAULT 0
2951#define FLASH_VENDOR_MIN 0
2952#define FLASH_VENDOR_MAX 2
2953
2954struct atl2_option {
2955 enum { enable_option, range_option, list_option } type;
2956 char *name;
2957 char *err;
2958 int def;
2959 union {
2960 struct { /* range_option info */
2961 int min;
2962 int max;
2963 } r;
2964 struct { /* list_option info */
2965 int nr;
2966 struct atl2_opt_list { int i; char *str; } *p;
2967 } l;
2968 } arg;
2969};
2970
2971static int __devinit atl2_validate_option(int *value, struct atl2_option *opt)
2972{
2973 int i;
2974 struct atl2_opt_list *ent;
2975
2976 if (*value == OPTION_UNSET) {
2977 *value = opt->def;
2978 return 0;
2979 }
2980
2981 switch (opt->type) {
2982 case enable_option:
2983 switch (*value) {
2984 case OPTION_ENABLED:
2985 printk(KERN_INFO "%s Enabled\n", opt->name);
2986 return 0;
2987 break;
2988 case OPTION_DISABLED:
2989 printk(KERN_INFO "%s Disabled\n", opt->name);
2990 return 0;
2991 break;
2992 }
2993 break;
2994 case range_option:
2995 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
2996 printk(KERN_INFO "%s set to %i\n", opt->name, *value);
2997 return 0;
2998 }
2999 break;
3000 case list_option:
3001 for (i = 0; i < opt->arg.l.nr; i++) {
3002 ent = &opt->arg.l.p[i];
3003 if (*value == ent->i) {
3004 if (ent->str[0] != '\0')
3005 printk(KERN_INFO "%s\n", ent->str);
3006 return 0;
3007 }
3008 }
3009 break;
3010 default:
3011 BUG();
3012 }
3013
3014 printk(KERN_INFO "Invalid %s specified (%i) %s\n",
3015 opt->name, *value, opt->err);
3016 *value = opt->def;
3017 return -1;
3018}
3019
3020/*
3021 * atl2_check_options - Range Checking for Command Line Parameters
3022 * @adapter: board private structure
3023 *
3024 * This routine checks all command line parameters for valid user
3025 * input. If an invalid value is given, or if no user specified
3026 * value exists, a default value is used. The final value is stored
3027 * in a variable in the adapter structure.
3028 */
3029static void __devinit atl2_check_options(struct atl2_adapter *adapter)
3030{
3031 int val;
3032 struct atl2_option opt;
3033 int bd = adapter->bd_number;
3034 if (bd >= ATL2_MAX_NIC) {
3035 printk(KERN_NOTICE "Warning: no configuration for board #%i\n",
3036 bd);
3037 printk(KERN_NOTICE "Using defaults for all values\n");
3038#ifndef module_param_array
3039 bd = ATL2_MAX_NIC;
3040#endif
3041 }
3042
3043 /* Bytes of Transmit Memory */
3044 opt.type = range_option;
3045 opt.name = "Bytes of Transmit Memory";
3046 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE);
3047 opt.def = ATL2_DEFAULT_TX_MEMSIZE;
3048 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE;
3049 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE;
3050#ifdef module_param_array
3051 if (num_TxMemSize > bd) {
3052#endif
3053 val = TxMemSize[bd];
3054 atl2_validate_option(&val, &opt);
3055 adapter->txd_ring_size = ((u32) val) * 1024;
3056#ifdef module_param_array
3057 } else
3058 adapter->txd_ring_size = ((u32)opt.def) * 1024;
3059#endif
3060 /* txs ring size: */
3061 adapter->txs_ring_size = adapter->txd_ring_size / 128;
3062 if (adapter->txs_ring_size > 160)
3063 adapter->txs_ring_size = 160;
3064
3065 /* Receive Memory Block Count */
3066 opt.type = range_option;
3067 opt.name = "Number of receive memory block";
3068 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT);
3069 opt.def = ATL2_DEFAULT_RXD_COUNT;
3070 opt.arg.r.min = ATL2_MIN_RXD_COUNT;
3071 opt.arg.r.max = ATL2_MAX_RXD_COUNT;
3072#ifdef module_param_array
3073 if (num_RxMemBlock > bd) {
3074#endif
3075 val = RxMemBlock[bd];
3076 atl2_validate_option(&val, &opt);
3077 adapter->rxd_ring_size = (u32)val;
3078 /* FIXME */
3079 /* ((u16)val)&~1; */ /* even number */
3080#ifdef module_param_array
3081 } else
3082 adapter->rxd_ring_size = (u32)opt.def;
3083#endif
3084 /* init RXD Flow control value */
3085 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7;
3086 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) >
3087 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) :
3088 (adapter->rxd_ring_size / 12);
3089
3090 /* Interrupt Moderate Timer */
3091 opt.type = range_option;
3092 opt.name = "Interrupt Moderate Timer";
3093 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT);
3094 opt.def = INT_MOD_DEFAULT_CNT;
3095 opt.arg.r.min = INT_MOD_MIN_CNT;
3096 opt.arg.r.max = INT_MOD_MAX_CNT;
3097#ifdef module_param_array
3098 if (num_IntModTimer > bd) {
3099#endif
3100 val = IntModTimer[bd];
3101 atl2_validate_option(&val, &opt);
3102 adapter->imt = (u16) val;
3103#ifdef module_param_array
3104 } else
3105 adapter->imt = (u16)(opt.def);
3106#endif
3107 /* Flash Vendor */
3108 opt.type = range_option;
3109 opt.name = "SPI Flash Vendor";
3110 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT);
3111 opt.def = FLASH_VENDOR_DEFAULT;
3112 opt.arg.r.min = FLASH_VENDOR_MIN;
3113 opt.arg.r.max = FLASH_VENDOR_MAX;
3114#ifdef module_param_array
3115 if (num_FlashVendor > bd) {
3116#endif
3117 val = FlashVendor[bd];
3118 atl2_validate_option(&val, &opt);
3119 adapter->hw.flash_vendor = (u8) val;
3120#ifdef module_param_array
3121 } else
3122 adapter->hw.flash_vendor = (u8)(opt.def);
3123#endif
3124 /* MediaType */
3125 opt.type = range_option;
3126 opt.name = "Speed/Duplex Selection";
3127 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR);
3128 opt.def = MEDIA_TYPE_AUTO_SENSOR;
3129 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR;
3130 opt.arg.r.max = MEDIA_TYPE_10M_HALF;
3131#ifdef module_param_array
3132 if (num_MediaType > bd) {
3133#endif
3134 val = MediaType[bd];
3135 atl2_validate_option(&val, &opt);
3136 adapter->hw.MediaType = (u16) val;
3137#ifdef module_param_array
3138 } else
3139 adapter->hw.MediaType = (u16)(opt.def);
3140#endif
3141}
Linux kernel - Deliverables
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