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[deliverable/linux.git] / drivers / net / atlx / atl2.c
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452c1ce2
CS		 1/*
2 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved.
3 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com>
4 *
5 * Derived from Intel e1000 driver
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23#include <asm/atomic.h>
24#include <linux/crc32.h>
25#include <linux/dma-mapping.h>
26#include <linux/etherdevice.h>
27#include <linux/ethtool.h>
28#include <linux/hardirq.h>
29#include <linux/if_vlan.h>
30#include <linux/in.h>
31#include <linux/interrupt.h>
32#include <linux/ip.h>
33#include <linux/irqflags.h>
34#include <linux/irqreturn.h>
35#include <linux/mii.h>
36#include <linux/net.h>
37#include <linux/netdevice.h>
38#include <linux/pci.h>
39#include <linux/pci_ids.h>
40#include <linux/pm.h>
41#include <linux/skbuff.h>
42#include <linux/spinlock.h>
43#include <linux/string.h>
44#include <linux/tcp.h>
45#include <linux/timer.h>
46#include <linux/types.h>
47#include <linux/workqueue.h>
48
49#include "atl2.h"
50
51#define ATL2_DRV_VERSION "2.2.3"
52
53static char atl2_driver_name[] = "atl2";
54static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver";
55static char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation.";
56static char atl2_driver_version[] = ATL2_DRV_VERSION;
57
58MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>");
59MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver");
60MODULE_LICENSE("GPL");
61MODULE_VERSION(ATL2_DRV_VERSION);
62
63/*
64 * atl2_pci_tbl - PCI Device ID Table
65 */
66static struct pci_device_id atl2_pci_tbl[] = {
67 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)},
68 /* required last entry */
69 {0,}
70};
71MODULE_DEVICE_TABLE(pci, atl2_pci_tbl);
72
73static void atl2_set_ethtool_ops(struct net_device *netdev);
74
75static void atl2_check_options(struct atl2_adapter *adapter);
76
77/*
78 * atl2_sw_init - Initialize general software structures (struct atl2_adapter)
79 * @adapter: board private structure to initialize
80 *
81 * atl2_sw_init initializes the Adapter private data structure.
82 * Fields are initialized based on PCI device information and
83 * OS network device settings (MTU size).
84 */
85static int __devinit atl2_sw_init(struct atl2_adapter *adapter)
86{
87 struct atl2_hw *hw = &adapter->hw;
88 struct pci_dev *pdev = adapter->pdev;
89
90 /* PCI config space info */
91 hw->vendor_id = pdev->vendor;
92 hw->device_id = pdev->device;
93 hw->subsystem_vendor_id = pdev->subsystem_vendor;
94 hw->subsystem_id = pdev->subsystem_device;
95
96 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
97 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
98
99 adapter->wol = 0;
100 adapter->ict = 50000; /* ~100ms */
101 adapter->link_speed = SPEED_0; /* hardware init */
102 adapter->link_duplex = FULL_DUPLEX;
103
104 hw->phy_configured = false;
105 hw->preamble_len = 7;
106 hw->ipgt = 0x60;
107 hw->min_ifg = 0x50;
108 hw->ipgr1 = 0x40;
109 hw->ipgr2 = 0x60;
110 hw->retry_buf = 2;
111 hw->max_retry = 0xf;
112 hw->lcol = 0x37;
113 hw->jam_ipg = 7;
114 hw->fc_rxd_hi = 0;
115 hw->fc_rxd_lo = 0;
116 hw->max_frame_size = adapter->netdev->mtu;
117
118 spin_lock_init(&adapter->stats_lock);
452c1ce2
CS		 119
120 set_bit(__ATL2_DOWN, &adapter->flags);
121
122 return 0;
123}
124
125/*
126 * atl2_set_multi - Multicast and Promiscuous mode set
127 * @netdev: network interface device structure
128 *
129 * The set_multi entry point is called whenever the multicast address
130 * list or the network interface flags are updated. This routine is
131 * responsible for configuring the hardware for proper multicast,
132 * promiscuous mode, and all-multi behavior.
133 */
134static void atl2_set_multi(struct net_device *netdev)
135{
136 struct atl2_adapter *adapter = netdev_priv(netdev);
137 struct atl2_hw *hw = &adapter->hw;
138 struct dev_mc_list *mc_ptr;
139 u32 rctl;
140 u32 hash_value;
141
142 /* Check for Promiscuous and All Multicast modes */
143 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL);
144
145 if (netdev->flags & IFF_PROMISC) {
146 rctl |= MAC_CTRL_PROMIS_EN;
147 } else if (netdev->flags & IFF_ALLMULTI) {
148 rctl |= MAC_CTRL_MC_ALL_EN;
149 rctl &= ~MAC_CTRL_PROMIS_EN;
150 } else
151 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
152
153 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);
154
155 /* clear the old settings from the multicast hash table */
156 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
157 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
158
159 /* comoute mc addresses' hash value ,and put it into hash table */
160 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
161 hash_value = atl2_hash_mc_addr(hw, mc_ptr->dmi_addr);
162 atl2_hash_set(hw, hash_value);
163 }
164}
165
166static void init_ring_ptrs(struct atl2_adapter *adapter)
167{
168 /* Read / Write Ptr Initialize: */
169 adapter->txd_write_ptr = 0;
170 atomic_set(&adapter->txd_read_ptr, 0);
171
172 adapter->rxd_read_ptr = 0;
173 adapter->rxd_write_ptr = 0;
174
175 atomic_set(&adapter->txs_write_ptr, 0);
176 adapter->txs_next_clear = 0;
177}
178
179/*
180 * atl2_configure - Configure Transmit&Receive Unit after Reset
181 * @adapter: board private structure
182 *
183 * Configure the Tx /Rx unit of the MAC after a reset.
184 */
185static int atl2_configure(struct atl2_adapter *adapter)
186{
187 struct atl2_hw *hw = &adapter->hw;
188 u32 value;
189
190 /* clear interrupt status */
191 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);
192
193 /* set MAC Address */
194 value = (((u32)hw->mac_addr[2]) << 24) |
195 (((u32)hw->mac_addr[3]) << 16) |
196 (((u32)hw->mac_addr[4]) << 8) |
197 (((u32)hw->mac_addr[5]));
198 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);
199 value = (((u32)hw->mac_addr[0]) << 8) |
200 (((u32)hw->mac_addr[1]));
201 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);
202
203 /* HI base address */
204 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
205 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32));
206
207 /* LO base address */
208 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,
209 (u32)(adapter->txd_dma & 0x00000000ffffffffULL));
210 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,
211 (u32)(adapter->txs_dma & 0x00000000ffffffffULL));
212 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,
213 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL));
214
215 /* element count */
216 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4));
217 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size);
218 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size);
219
220 /* config Internal SRAM */
221/*
222 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end);
223 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end);
224*/
225
226 /* config IPG/IFG */
227 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) <<
228 MAC_IPG_IFG_IPGT_SHIFT) |
229 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) <<
230 MAC_IPG_IFG_MIFG_SHIFT) |
231 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) <<
232 MAC_IPG_IFG_IPGR1_SHIFT)|
233 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) <<
234 MAC_IPG_IFG_IPGR2_SHIFT);
235 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);
236
237 /* config Half-Duplex Control */
238 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
239 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) <<
240 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
241 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
242 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
243 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) <<
244 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
245 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);
246
247 /* set Interrupt Moderator Timer */
248 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt);
249 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);
250
251 /* set Interrupt Clear Timer */
252 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict);
253
254 /* set MTU */
255 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +
256 ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE);
257
258 /* 1590 */
259 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);
260
261 /* flow control */
262 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi);
263 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo);
264
265 /* Init mailbox */
266 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr);
267 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr);
268
269 /* enable DMA read/write */
270 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN);
271 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN);
272
273 value = ATL2_READ_REG(&adapter->hw, REG_ISR);
274 if ((value & ISR_PHY_LINKDOWN) != 0)
275 value = 1; /* config failed */
276 else
277 value = 0;
278
279 /* clear all interrupt status */
280 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);
281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
282 return value;
283}
284
285/*
286 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources
287 * @adapter: board private structure
288 *
289 * Return 0 on success, negative on failure
290 */
291static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter)
292{
293 struct pci_dev *pdev = adapter->pdev;
294 int size;
295 u8 offset = 0;
296
297 /* real ring DMA buffer */
298 adapter->ring_size = size =
299 adapter->txd_ring_size * 1 + 7 + /* dword align */
300 adapter->txs_ring_size * 4 + 7 + /* dword align */
301 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */
302
303 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size,
304 &adapter->ring_dma);
305 if (!adapter->ring_vir_addr)
306 return -ENOMEM;
307 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
308
309 /* Init TXD Ring */
310 adapter->txd_dma = adapter->ring_dma ;
311 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;
312 adapter->txd_dma += offset;
313 adapter->txd_ring = (struct tx_pkt_header *) (adapter->ring_vir_addr +
314 offset);
315
316 /* Init TXS Ring */
317 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;
318 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0;
319 adapter->txs_dma += offset;
320 adapter->txs_ring = (struct tx_pkt_status *)
321 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset));
322
323 /* Init RXD Ring */
324 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4;
325 offset = (adapter->rxd_dma & 127) ?
326 (128 - (adapter->rxd_dma & 127)) : 0;
327 if (offset > 7)
328 offset -= 8;
329 else
330 offset += (128 - 8);
331
332 adapter->rxd_dma += offset;
333 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) +
334 (adapter->txs_ring_size * 4 + offset));
335
336/*
337 * Read / Write Ptr Initialize:
338 * init_ring_ptrs(adapter);
339 */
340 return 0;
341}
342
343/*
344 * atl2_irq_enable - Enable default interrupt generation settings
345 * @adapter: board private structure
346 */
347static inline void atl2_irq_enable(struct atl2_adapter *adapter)
348{
349 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
350 ATL2_WRITE_FLUSH(&adapter->hw);
351}
352
353/*
354 * atl2_irq_disable - Mask off interrupt generation on the NIC
355 * @adapter: board private structure
356 */
357static inline void atl2_irq_disable(struct atl2_adapter *adapter)
358{
359 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);
360 ATL2_WRITE_FLUSH(&adapter->hw);
361 synchronize_irq(adapter->pdev->irq);
362}
363
364#ifdef NETIF_F_HW_VLAN_TX
365static void atl2_vlan_rx_register(struct net_device *netdev,
366 struct vlan_group *grp)
367{
368 struct atl2_adapter *adapter = netdev_priv(netdev);
369 u32 ctrl;
370
371 atl2_irq_disable(adapter);
372 adapter->vlgrp = grp;
373
374 if (grp) {
375 /* enable VLAN tag insert/strip */
376 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
377 ctrl |= MAC_CTRL_RMV_VLAN;
378 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
379 } else {
380 /* disable VLAN tag insert/strip */
381 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
382 ctrl &= ~MAC_CTRL_RMV_VLAN;
383 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
384 }
385
386 atl2_irq_enable(adapter);
387}
388
389static void atl2_restore_vlan(struct atl2_adapter *adapter)
390{
391 atl2_vlan_rx_register(adapter->netdev, adapter->vlgrp);
392}
393#endif
394
395static void atl2_intr_rx(struct atl2_adapter *adapter)
396{
397 struct net_device *netdev = adapter->netdev;
398 struct rx_desc *rxd;
399 struct sk_buff *skb;
400
401 do {
402 rxd = adapter->rxd_ring+adapter->rxd_write_ptr;
403 if (!rxd->status.update)
404 break; /* end of tx */
405
406 /* clear this flag at once */
407 rxd->status.update = 0;
408
409 if (rxd->status.ok && rxd->status.pkt_size >= 60) {
410 int rx_size = (int)(rxd->status.pkt_size - 4);
411 /* alloc new buffer */
412 skb = netdev_alloc_skb(netdev, rx_size + NET_IP_ALIGN);
413 if (NULL == skb) {
414 printk(KERN_WARNING
415 "%s: Mem squeeze, deferring packet.\n",
416 netdev->name);
417 /*
418 * Check that some rx space is free. If not,
419 * free one and mark stats->rx_dropped++.
420 */
421 adapter->net_stats.rx_dropped++;
422 break;
423 }
424 skb_reserve(skb, NET_IP_ALIGN);
425 skb->dev = netdev;
426 memcpy(skb->data, rxd->packet, rx_size);
427 skb_put(skb, rx_size);
428 skb->protocol = eth_type_trans(skb, netdev);
429#ifdef NETIF_F_HW_VLAN_TX
430 if (adapter->vlgrp && (rxd->status.vlan)) {
431 u16 vlan_tag = (rxd->status.vtag>>4) |
432 ((rxd->status.vtag&7) << 13) |
433 ((rxd->status.vtag&8) << 9);
434 vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
435 } else
436#endif
437 netif_rx(skb);
438 adapter->net_stats.rx_bytes += rx_size;
439 adapter->net_stats.rx_packets++;
440 netdev->last_rx = jiffies;
441 } else {
442 adapter->net_stats.rx_errors++;
443
444 if (rxd->status.ok && rxd->status.pkt_size <= 60)
445 adapter->net_stats.rx_length_errors++;
446 if (rxd->status.mcast)
447 adapter->net_stats.multicast++;
448 if (rxd->status.crc)
449 adapter->net_stats.rx_crc_errors++;
450 if (rxd->status.align)
451 adapter->net_stats.rx_frame_errors++;
452 }
453
454 /* advance write ptr */
455 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size)
456 adapter->rxd_write_ptr = 0;
457 } while (1);
458
459 /* update mailbox? */
460 adapter->rxd_read_ptr = adapter->rxd_write_ptr;
461 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr);
462}
463
464static void atl2_intr_tx(struct atl2_adapter *adapter)
465{
466 u32 txd_read_ptr;
467 u32 txs_write_ptr;
468 struct tx_pkt_status *txs;
469 struct tx_pkt_header *txph;
470 int free_hole = 0;
471
472 do {
473 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
474 txs = adapter->txs_ring + txs_write_ptr;
475 if (!txs->update)
476 break; /* tx stop here */
477
478 free_hole = 1;
479 txs->update = 0;
480
481 if (++txs_write_ptr == adapter->txs_ring_size)
482 txs_write_ptr = 0;
483 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr);
484
485 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr);
486 txph = (struct tx_pkt_header *)
487 (((u8 *)adapter->txd_ring) + txd_read_ptr);
488
489 if (txph->pkt_size != txs->pkt_size) {
490 struct tx_pkt_status *old_txs = txs;
491 printk(KERN_WARNING
492 "%s: txs packet size not consistent with txd"
493 " txd_:0x%08x, txs_:0x%08x!\n",
494 adapter->netdev->name,
495 *(u32 *)txph, *(u32 *)txs);
496 printk(KERN_WARNING
497 "txd read ptr: 0x%x\n",
498 txd_read_ptr);
499 txs = adapter->txs_ring + txs_write_ptr;
500 printk(KERN_WARNING
501 "txs-behind:0x%08x\n",
502 *(u32 *)txs);
503 if (txs_write_ptr < 2) {
504 txs = adapter->txs_ring +
505 (adapter->txs_ring_size +
506 txs_write_ptr - 2);
507 } else {
508 txs = adapter->txs_ring + (txs_write_ptr - 2);
509 }
510 printk(KERN_WARNING
511 "txs-before:0x%08x\n",
512 *(u32 *)txs);
513 txs = old_txs;
514 }
515
516 /* 4for TPH */
517 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3);
518 if (txd_read_ptr >= adapter->txd_ring_size)
519 txd_read_ptr -= adapter->txd_ring_size;
520
521 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr);
522
523 /* tx statistics: */
e2f092ff
JC		 524 if (txs->ok) {
525 adapter->net_stats.tx_bytes += txs->pkt_size;
452c1ce2 526 adapter->net_stats.tx_packets++;
e2f092ff 527 }
452c1ce2
CS		 528 else
529 adapter->net_stats.tx_errors++;
530
531 if (txs->defer)
532 adapter->net_stats.collisions++;
533 if (txs->abort_col)
534 adapter->net_stats.tx_aborted_errors++;
535 if (txs->late_col)
536 adapter->net_stats.tx_window_errors++;
537 if (txs->underun)
538 adapter->net_stats.tx_fifo_errors++;
539 } while (1);
540
541 if (free_hole) {
542 if (netif_queue_stopped(adapter->netdev) &&
543 netif_carrier_ok(adapter->netdev))
544 netif_wake_queue(adapter->netdev);
545 }
546}
547
548static void atl2_check_for_link(struct atl2_adapter *adapter)
549{
550 struct net_device *netdev = adapter->netdev;
551 u16 phy_data = 0;
552
553 spin_lock(&adapter->stats_lock);
554 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
555 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
556 spin_unlock(&adapter->stats_lock);
557
558 /* notify upper layer link down ASAP */
559 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
560 if (netif_carrier_ok(netdev)) { /* old link state: Up */
561 printk(KERN_INFO "%s: %s NIC Link is Down\n",
562 atl2_driver_name, netdev->name);
563 adapter->link_speed = SPEED_0;
564 netif_carrier_off(netdev);
565 netif_stop_queue(netdev);
566 }
567 }
568 schedule_work(&adapter->link_chg_task);
569}
570
571static inline void atl2_clear_phy_int(struct atl2_adapter *adapter)
572{
573 u16 phy_data;
574 spin_lock(&adapter->stats_lock);
575 atl2_read_phy_reg(&adapter->hw, 19, &phy_data);
576 spin_unlock(&adapter->stats_lock);
577}
578
579/*
580 * atl2_intr - Interrupt Handler
581 * @irq: interrupt number
582 * @data: pointer to a network interface device structure
583 * @pt_regs: CPU registers structure
584 */
585static irqreturn_t atl2_intr(int irq, void *data)
586{
587 struct atl2_adapter *adapter = netdev_priv(data);
588 struct atl2_hw *hw = &adapter->hw;
589 u32 status;
590
591 status = ATL2_READ_REG(hw, REG_ISR);
592 if (0 == status)
593 return IRQ_NONE;
594
595 /* link event */
596 if (status & ISR_PHY)
597 atl2_clear_phy_int(adapter);
598
599 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
600 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
601
602 /* check if PCIE PHY Link down */
603 if (status & ISR_PHY_LINKDOWN) {
604 if (netif_running(adapter->netdev)) { /* reset MAC */
605 ATL2_WRITE_REG(hw, REG_ISR, 0);
606 ATL2_WRITE_REG(hw, REG_IMR, 0);
607 ATL2_WRITE_FLUSH(hw);
608 schedule_work(&adapter->reset_task);
609 return IRQ_HANDLED;
610 }
611 }
612
613 /* check if DMA read/write error? */
614 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
615 ATL2_WRITE_REG(hw, REG_ISR, 0);
616 ATL2_WRITE_REG(hw, REG_IMR, 0);
617 ATL2_WRITE_FLUSH(hw);
618 schedule_work(&adapter->reset_task);
619 return IRQ_HANDLED;
620 }
621
622 /* link event */
623 if (status & (ISR_PHY | ISR_MANUAL)) {
624 adapter->net_stats.tx_carrier_errors++;
625 atl2_check_for_link(adapter);
626 }
627
628 /* transmit event */
629 if (status & ISR_TX_EVENT)
630 atl2_intr_tx(adapter);
631
632 /* rx exception */
633 if (status & ISR_RX_EVENT)
634 atl2_intr_rx(adapter);
635
636 /* re-enable Interrupt */
637 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
638 return IRQ_HANDLED;
639}
640
641static int atl2_request_irq(struct atl2_adapter *adapter)
642{
643 struct net_device *netdev = adapter->netdev;
644 int flags, err = 0;
645
646 flags = IRQF_SHARED;
647#ifdef CONFIG_PCI_MSI
648 adapter->have_msi = true;
649 err = pci_enable_msi(adapter->pdev);
650 if (err)
651 adapter->have_msi = false;
652
653 if (adapter->have_msi)
654 flags &= ~IRQF_SHARED;
655#endif
656
657 return request_irq(adapter->pdev->irq, &atl2_intr, flags, netdev->name,
658 netdev);
659}
660
661/*
662 * atl2_free_ring_resources - Free Tx / RX descriptor Resources
663 * @adapter: board private structure
664 *
665 * Free all transmit software resources
666 */
667static void atl2_free_ring_resources(struct atl2_adapter *adapter)
668{
669 struct pci_dev *pdev = adapter->pdev;
670 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr,
671 adapter->ring_dma);
672}
673
674/*
675 * atl2_open - Called when a network interface is made active
676 * @netdev: network interface device structure
677 *
678 * Returns 0 on success, negative value on failure
679 *
680 * The open entry point is called when a network interface is made
681 * active by the system (IFF_UP). At this point all resources needed
682 * for transmit and receive operations are allocated, the interrupt
683 * handler is registered with the OS, the watchdog timer is started,
684 * and the stack is notified that the interface is ready.
685 */
686static int atl2_open(struct net_device *netdev)
687{
688 struct atl2_adapter *adapter = netdev_priv(netdev);
689 int err;
690 u32 val;
691
692 /* disallow open during test */
693 if (test_bit(__ATL2_TESTING, &adapter->flags))
694 return -EBUSY;
695
696 /* allocate transmit descriptors */
697 err = atl2_setup_ring_resources(adapter);
698 if (err)
699 return err;
700
701 err = atl2_init_hw(&adapter->hw);
702 if (err) {
703 err = -EIO;
704 goto err_init_hw;
705 }
706
707 /* hardware has been reset, we need to reload some things */
708 atl2_set_multi(netdev);
709 init_ring_ptrs(adapter);
710
711#ifdef NETIF_F_HW_VLAN_TX
712 atl2_restore_vlan(adapter);
713#endif
714
715 if (atl2_configure(adapter)) {
716 err = -EIO;
717 goto err_config;
718 }
719
720 err = atl2_request_irq(adapter);
721 if (err)
722 goto err_req_irq;
723
724 clear_bit(__ATL2_DOWN, &adapter->flags);
725
726 mod_timer(&adapter->watchdog_timer, jiffies + 4*HZ);
727
728 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
729 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
730 val | MASTER_CTRL_MANUAL_INT);
731
732 atl2_irq_enable(adapter);
733
734 return 0;
735
736err_init_hw:
737err_req_irq:
738err_config:
739 atl2_free_ring_resources(adapter);
740 atl2_reset_hw(&adapter->hw);
741
742 return err;
743}
744
745static void atl2_down(struct atl2_adapter *adapter)
746{
747 struct net_device *netdev = adapter->netdev;
748
749 /* signal that we're down so the interrupt handler does not
750 * reschedule our watchdog timer */
751 set_bit(__ATL2_DOWN, &adapter->flags);
752
452c1ce2 753 netif_tx_disable(netdev);
452c1ce2
CS		 754
755 /* reset MAC to disable all RX/TX */
756 atl2_reset_hw(&adapter->hw);
757 msleep(1);
758
759 atl2_irq_disable(adapter);
760
761 del_timer_sync(&adapter->watchdog_timer);
762 del_timer_sync(&adapter->phy_config_timer);
763 clear_bit(0, &adapter->cfg_phy);
764
765 netif_carrier_off(netdev);
766 adapter->link_speed = SPEED_0;
767 adapter->link_duplex = -1;
768}
769
770static void atl2_free_irq(struct atl2_adapter *adapter)
771{
772 struct net_device *netdev = adapter->netdev;
773
774 free_irq(adapter->pdev->irq, netdev);
775
776#ifdef CONFIG_PCI_MSI
777 if (adapter->have_msi)
778 pci_disable_msi(adapter->pdev);
779#endif
780}
781
782/*
783 * atl2_close - Disables a network interface
784 * @netdev: network interface device structure
785 *
786 * Returns 0, this is not allowed to fail
787 *
788 * The close entry point is called when an interface is de-activated
789 * by the OS. The hardware is still under the drivers control, but
790 * needs to be disabled. A global MAC reset is issued to stop the
791 * hardware, and all transmit and receive resources are freed.
792 */
793static int atl2_close(struct net_device *netdev)
794{
795 struct atl2_adapter *adapter = netdev_priv(netdev);
796
797 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
798
799 atl2_down(adapter);
800 atl2_free_irq(adapter);
801 atl2_free_ring_resources(adapter);
802
803 return 0;
804}
805
806static inline int TxsFreeUnit(struct atl2_adapter *adapter)
807{
808 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
809
810 return (adapter->txs_next_clear >= txs_write_ptr) ?
811 (int) (adapter->txs_ring_size - adapter->txs_next_clear +
812 txs_write_ptr - 1) :
813 (int) (txs_write_ptr - adapter->txs_next_clear - 1);
814}
815
816static inline int TxdFreeBytes(struct atl2_adapter *adapter)
817{
818 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr);
819
820 return (adapter->txd_write_ptr >= txd_read_ptr) ?
821 (int) (adapter->txd_ring_size - adapter->txd_write_ptr +
822 txd_read_ptr - 1) :
823 (int) (txd_read_ptr - adapter->txd_write_ptr - 1);
824}
825
826static int atl2_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
827{
828 struct atl2_adapter *adapter = netdev_priv(netdev);
452c1ce2
CS		 829 struct tx_pkt_header *txph;
830 u32 offset, copy_len;
831 int txs_unused;
832 int txbuf_unused;
833
834 if (test_bit(__ATL2_DOWN, &adapter->flags)) {
835 dev_kfree_skb_any(skb);
836 return NETDEV_TX_OK;
837 }
838
839 if (unlikely(skb->len <= 0)) {
840 dev_kfree_skb_any(skb);
841 return NETDEV_TX_OK;
842 }
843
452c1ce2
CS		 844 txs_unused = TxsFreeUnit(adapter);
845 txbuf_unused = TxdFreeBytes(adapter);
846
847 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused ||
848 txs_unused < 1) {
849 /* not enough resources */
850 netif_stop_queue(netdev);
452c1ce2
CS		 851 return NETDEV_TX_BUSY;
852 }
853
854 offset = adapter->txd_write_ptr;
855
856 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset);
857
858 *(u32 *)txph = 0;
859 txph->pkt_size = skb->len;
860
861 offset += 4;
862 if (offset >= adapter->txd_ring_size)
863 offset -= adapter->txd_ring_size;
864 copy_len = adapter->txd_ring_size - offset;
865 if (copy_len >= skb->len) {
866 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len);
867 offset += ((u32)(skb->len + 3) & ~3);
868 } else {
869 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len);
870 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len,
871 skb->len-copy_len);
872 offset = ((u32)(skb->len-copy_len + 3) & ~3);
873 }
874#ifdef NETIF_F_HW_VLAN_TX
875 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
876 u16 vlan_tag = vlan_tx_tag_get(skb);
877 vlan_tag = (vlan_tag << 4) |
878 (vlan_tag >> 13) |
879 ((vlan_tag >> 9) & 0x8);
880 txph->ins_vlan = 1;
881 txph->vlan = vlan_tag;
882 }
883#endif
884 if (offset >= adapter->txd_ring_size)
885 offset -= adapter->txd_ring_size;
886 adapter->txd_write_ptr = offset;
887
888 /* clear txs before send */
889 adapter->txs_ring[adapter->txs_next_clear].update = 0;
890 if (++adapter->txs_next_clear == adapter->txs_ring_size)
891 adapter->txs_next_clear = 0;
892
893 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX,
894 (adapter->txd_write_ptr >> 2));
895
87241840 896 mmiowb();
452c1ce2
CS		 897 netdev->trans_start = jiffies;
898 dev_kfree_skb_any(skb);
899 return NETDEV_TX_OK;
900}
901
902/*
903 * atl2_get_stats - Get System Network Statistics
904 * @netdev: network interface device structure
905 *
906 * Returns the address of the device statistics structure.
907 * The statistics are actually updated from the timer callback.
908 */
909static struct net_device_stats *atl2_get_stats(struct net_device *netdev)
910{
911 struct atl2_adapter *adapter = netdev_priv(netdev);
912 return &adapter->net_stats;
913}
914
915/*
916 * atl2_change_mtu - Change the Maximum Transfer Unit
917 * @netdev: network interface device structure
918 * @new_mtu: new value for maximum frame size
919 *
920 * Returns 0 on success, negative on failure
921 */
922static int atl2_change_mtu(struct net_device *netdev, int new_mtu)
923{
924 struct atl2_adapter *adapter = netdev_priv(netdev);
925 struct atl2_hw *hw = &adapter->hw;
926
927 if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE)))
928 return -EINVAL;
929
930 /* set MTU */
931 if (hw->max_frame_size != new_mtu) {
932 netdev->mtu = new_mtu;
933 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE +
934 VLAN_SIZE + ETHERNET_FCS_SIZE);
935 }
936
937 return 0;
938}
939
940/*
941 * atl2_set_mac - Change the Ethernet Address of the NIC
942 * @netdev: network interface device structure
943 * @p: pointer to an address structure
944 *
945 * Returns 0 on success, negative on failure
946 */
947static int atl2_set_mac(struct net_device *netdev, void *p)
948{
949 struct atl2_adapter *adapter = netdev_priv(netdev);
950 struct sockaddr *addr = p;
951
952 if (!is_valid_ether_addr(addr->sa_data))
953 return -EADDRNOTAVAIL;
954
955 if (netif_running(netdev))
956 return -EBUSY;
957
958 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
959 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
960
961 atl2_set_mac_addr(&adapter->hw);
962
963 return 0;
964}
965
966/*
967 * atl2_mii_ioctl -
968 * @netdev:
969 * @ifreq:
970 * @cmd:
971 */
972static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
973{
974 struct atl2_adapter *adapter = netdev_priv(netdev);
975 struct mii_ioctl_data *data = if_mii(ifr);
976 unsigned long flags;
977
978 switch (cmd) {
979 case SIOCGMIIPHY:
980 data->phy_id = 0;
981 break;
982 case SIOCGMIIREG:
983 if (!capable(CAP_NET_ADMIN))
984 return -EPERM;
985 spin_lock_irqsave(&adapter->stats_lock, flags);
986 if (atl2_read_phy_reg(&adapter->hw,
987 data->reg_num & 0x1F, &data->val_out)) {
988 spin_unlock_irqrestore(&adapter->stats_lock, flags);
989 return -EIO;
990 }
991 spin_unlock_irqrestore(&adapter->stats_lock, flags);
992 break;
993 case SIOCSMIIREG:
994 if (!capable(CAP_NET_ADMIN))
995 return -EPERM;
996 if (data->reg_num & ~(0x1F))
997 return -EFAULT;
998 spin_lock_irqsave(&adapter->stats_lock, flags);
999 if (atl2_write_phy_reg(&adapter->hw, data->reg_num,
1000 data->val_in)) {
1001 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1002 return -EIO;
1003 }
1004 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1005 break;
1006 default:
1007 return -EOPNOTSUPP;
1008 }
1009 return 0;
1010}
1011
1012/*
1013 * atl2_ioctl -
1014 * @netdev:
1015 * @ifreq:
1016 * @cmd:
1017 */
1018static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1019{
1020 switch (cmd) {
1021 case SIOCGMIIPHY:
1022 case SIOCGMIIREG:
1023 case SIOCSMIIREG:
1024 return atl2_mii_ioctl(netdev, ifr, cmd);
1025#ifdef ETHTOOL_OPS_COMPAT
1026 case SIOCETHTOOL:
1027 return ethtool_ioctl(ifr);
1028#endif
1029 default:
1030 return -EOPNOTSUPP;
1031 }
1032}
1033
1034/*
1035 * atl2_tx_timeout - Respond to a Tx Hang
1036 * @netdev: network interface device structure
1037 */
1038static void atl2_tx_timeout(struct net_device *netdev)
1039{
1040 struct atl2_adapter *adapter = netdev_priv(netdev);
1041
1042 /* Do the reset outside of interrupt context */
1043 schedule_work(&adapter->reset_task);
1044}
1045
1046/*
1047 * atl2_watchdog - Timer Call-back
1048 * @data: pointer to netdev cast into an unsigned long
1049 */
1050static void atl2_watchdog(unsigned long data)
1051{
1052 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1053 u32 drop_rxd, drop_rxs;
1054 unsigned long flags;
1055
1056 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1057 spin_lock_irqsave(&adapter->stats_lock, flags);
1058 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV);
1059 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV);
1060 adapter->net_stats.rx_over_errors += (drop_rxd+drop_rxs);
1061 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1062
1063 /* Reset the timer */
1064 mod_timer(&adapter->watchdog_timer, jiffies + 4 * HZ);
1065 }
1066}
1067
1068/*
1069 * atl2_phy_config - Timer Call-back
1070 * @data: pointer to netdev cast into an unsigned long
1071 */
1072static void atl2_phy_config(unsigned long data)
1073{
1074 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1075 struct atl2_hw *hw = &adapter->hw;
1076 unsigned long flags;
1077
1078 spin_lock_irqsave(&adapter->stats_lock, flags);
1079 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1080 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN |
1081 MII_CR_RESTART_AUTO_NEG);
1082 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1083 clear_bit(0, &adapter->cfg_phy);
1084}
1085
1086static int atl2_up(struct atl2_adapter *adapter)
1087{
1088 struct net_device *netdev = adapter->netdev;
1089 int err = 0;
1090 u32 val;
1091
1092 /* hardware has been reset, we need to reload some things */
1093
1094 err = atl2_init_hw(&adapter->hw);
1095 if (err) {
1096 err = -EIO;
1097 return err;
1098 }
1099
1100 atl2_set_multi(netdev);
1101 init_ring_ptrs(adapter);
1102
1103#ifdef NETIF_F_HW_VLAN_TX
1104 atl2_restore_vlan(adapter);
1105#endif
1106
1107 if (atl2_configure(adapter)) {
1108 err = -EIO;
1109 goto err_up;
1110 }
1111
1112 clear_bit(__ATL2_DOWN, &adapter->flags);
1113
1114 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1115 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val |
1116 MASTER_CTRL_MANUAL_INT);
1117
1118 atl2_irq_enable(adapter);
1119
1120err_up:
1121 return err;
1122}
1123
1124static void atl2_reinit_locked(struct atl2_adapter *adapter)
1125{
1126 WARN_ON(in_interrupt());
1127 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1128 msleep(1);
1129 atl2_down(adapter);
1130 atl2_up(adapter);
1131 clear_bit(__ATL2_RESETTING, &adapter->flags);
1132}
1133
1134static void atl2_reset_task(struct work_struct *work)
1135{
1136 struct atl2_adapter *adapter;
1137 adapter = container_of(work, struct atl2_adapter, reset_task);
1138
1139 atl2_reinit_locked(adapter);
1140}
1141
1142static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter)
1143{
1144 u32 value;
1145 struct atl2_hw *hw = &adapter->hw;
1146 struct net_device *netdev = adapter->netdev;
1147
1148 /* Config MAC CTRL Register */
1149 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1150
1151 /* duplex */
1152 if (FULL_DUPLEX == adapter->link_duplex)
1153 value |= MAC_CTRL_DUPLX;
1154
1155 /* flow control */
1156 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1157
1158 /* PAD & CRC */
1159 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1160
1161 /* preamble length */
1162 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) <<
1163 MAC_CTRL_PRMLEN_SHIFT);
1164
1165 /* vlan */
1166 if (adapter->vlgrp)
1167 value |= MAC_CTRL_RMV_VLAN;
1168
1169 /* filter mode */
1170 value |= MAC_CTRL_BC_EN;
1171 if (netdev->flags & IFF_PROMISC)
1172 value |= MAC_CTRL_PROMIS_EN;
1173 else if (netdev->flags & IFF_ALLMULTI)
1174 value |= MAC_CTRL_MC_ALL_EN;
1175
1176 /* half retry buffer */
1177 value |= (((u32)(adapter->hw.retry_buf &
1178 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1179
1180 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1181}
1182
1183static int atl2_check_link(struct atl2_adapter *adapter)
1184{
1185 struct atl2_hw *hw = &adapter->hw;
1186 struct net_device *netdev = adapter->netdev;
1187 int ret_val;
1188 u16 speed, duplex, phy_data;
1189 int reconfig = 0;
1190
1191 /* MII_BMSR must read twise */
1192 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1193 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1194 if (!(phy_data&BMSR_LSTATUS)) { /* link down */
1195 if (netif_carrier_ok(netdev)) { /* old link state: Up */
1196 u32 value;
1197 /* disable rx */
1198 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1199 value &= ~MAC_CTRL_RX_EN;
1200 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1201 adapter->link_speed = SPEED_0;
1202 netif_carrier_off(netdev);
1203 netif_stop_queue(netdev);
1204 }
1205 return 0;
1206 }
1207
1208 /* Link Up */
1209 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1210 if (ret_val)
1211 return ret_val;
1212 switch (hw->MediaType) {
1213 case MEDIA_TYPE_100M_FULL:
1214 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1215 reconfig = 1;
1216 break;
1217 case MEDIA_TYPE_100M_HALF:
1218 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1219 reconfig = 1;
1220 break;
1221 case MEDIA_TYPE_10M_FULL:
1222 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1223 reconfig = 1;
1224 break;
1225 case MEDIA_TYPE_10M_HALF:
1226 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1227 reconfig = 1;
1228 break;
1229 }
1230 /* link result is our setting */
1231 if (reconfig == 0) {
1232 if (adapter->link_speed != speed ||
1233 adapter->link_duplex != duplex) {
1234 adapter->link_speed = speed;
1235 adapter->link_duplex = duplex;
1236 atl2_setup_mac_ctrl(adapter);
1237 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n",
1238 atl2_driver_name, netdev->name,
1239 adapter->link_speed,
1240 adapter->link_duplex == FULL_DUPLEX ?
1241 "Full Duplex" : "Half Duplex");
1242 }
1243
1244 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
1245 netif_carrier_on(netdev);
1246 netif_wake_queue(netdev);
1247 }
1248 return 0;
1249 }
1250
1251 /* change original link status */
1252 if (netif_carrier_ok(netdev)) {
1253 u32 value;
1254 /* disable rx */
1255 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1256 value &= ~MAC_CTRL_RX_EN;
1257 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1258
1259 adapter->link_speed = SPEED_0;
1260 netif_carrier_off(netdev);
1261 netif_stop_queue(netdev);
1262 }
1263
1264 /* auto-neg, insert timer to re-config phy
1265 * (if interval smaller than 5 seconds, something strange) */
1266 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1267 if (!test_and_set_bit(0, &adapter->cfg_phy))
1268 mod_timer(&adapter->phy_config_timer, jiffies + 5 * HZ);
1269 }
1270
1271 return 0;
1272}
1273
1274/*
1275 * atl2_link_chg_task - deal with link change event Out of interrupt context
1276 * @netdev: network interface device structure
1277 */
1278static void atl2_link_chg_task(struct work_struct *work)
1279{
1280 struct atl2_adapter *adapter;
1281 unsigned long flags;
1282
1283 adapter = container_of(work, struct atl2_adapter, link_chg_task);
1284
1285 spin_lock_irqsave(&adapter->stats_lock, flags);
1286 atl2_check_link(adapter);
1287 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1288}
1289
1290static void atl2_setup_pcicmd(struct pci_dev *pdev)
1291{
1292 u16 cmd;
1293
1294 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1295
1296 if (cmd & PCI_COMMAND_INTX_DISABLE)
1297 cmd &= ~PCI_COMMAND_INTX_DISABLE;
1298 if (cmd & PCI_COMMAND_IO)
1299 cmd &= ~PCI_COMMAND_IO;
1300 if (0 == (cmd & PCI_COMMAND_MEMORY))
1301 cmd |= PCI_COMMAND_MEMORY;
1302 if (0 == (cmd & PCI_COMMAND_MASTER))
1303 cmd |= PCI_COMMAND_MASTER;
1304 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1305
1306 /*
1307 * some motherboards BIOS(PXE/EFI) driver may set PME
1308 * while they transfer control to OS (Windows/Linux)
1309 * so we should clear this bit before NIC work normally
1310 */
1311 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
1312}
1313
8d1b1fc9
KH		 1314#ifdef CONFIG_NET_POLL_CONTROLLER
1315static void atl2_poll_controller(struct net_device *netdev)
1316{
1317 disable_irq(netdev->irq);
1318 atl2_intr(netdev->irq, netdev);
1319 enable_irq(netdev->irq);
1320}
1321#endif
1322
452c1ce2
CS		 1323/*
1324 * atl2_probe - Device Initialization Routine
1325 * @pdev: PCI device information struct
1326 * @ent: entry in atl2_pci_tbl
1327 *
1328 * Returns 0 on success, negative on failure
1329 *
1330 * atl2_probe initializes an adapter identified by a pci_dev structure.
1331 * The OS initialization, configuring of the adapter private structure,
1332 * and a hardware reset occur.
1333 */
1334static int __devinit atl2_probe(struct pci_dev *pdev,
1335 const struct pci_device_id *ent)
1336{
1337 struct net_device *netdev;
1338 struct atl2_adapter *adapter;
1339 static int cards_found;
1340 unsigned long mmio_start;
1341 int mmio_len;
1342 int err;
1343
1344 cards_found = 0;
1345
1346 err = pci_enable_device(pdev);
1347 if (err)
1348 return err;
1349
1350 /*
1351 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA
1352 * until the kernel has the proper infrastructure to support 64-bit DMA
1353 * on these devices.
1354 */
1355 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) &&
1356 pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
1357 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n");
1358 goto err_dma;
1359 }
1360
1361 /* Mark all PCI regions associated with PCI device
1362 * pdev as being reserved by owner atl2_driver_name */
1363 err = pci_request_regions(pdev, atl2_driver_name);
1364 if (err)
1365 goto err_pci_reg;
1366
1367 /* Enables bus-mastering on the device and calls
1368 * pcibios_set_master to do the needed arch specific settings */
1369 pci_set_master(pdev);
1370
1371 err = -ENOMEM;
1372 netdev = alloc_etherdev(sizeof(struct atl2_adapter));
1373 if (!netdev)
1374 goto err_alloc_etherdev;
1375
1376 SET_NETDEV_DEV(netdev, &pdev->dev);
1377
1378 pci_set_drvdata(pdev, netdev);
1379 adapter = netdev_priv(netdev);
1380 adapter->netdev = netdev;
1381 adapter->pdev = pdev;
1382 adapter->hw.back = adapter;
1383
1384 mmio_start = pci_resource_start(pdev, 0x0);
1385 mmio_len = pci_resource_len(pdev, 0x0);
1386
1387 adapter->hw.mem_rang = (u32)mmio_len;
1388 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1389 if (!adapter->hw.hw_addr) {
1390 err = -EIO;
1391 goto err_ioremap;
1392 }
1393
1394 atl2_setup_pcicmd(pdev);
1395
1396 netdev->open = &atl2_open;
1397 netdev->stop = &atl2_close;
1398 netdev->hard_start_xmit = &atl2_xmit_frame;
1399 netdev->get_stats = &atl2_get_stats;
1400 netdev->set_multicast_list = &atl2_set_multi;
1401 netdev->set_mac_address = &atl2_set_mac;
1402 netdev->change_mtu = &atl2_change_mtu;
1403 netdev->do_ioctl = &atl2_ioctl;
1404 atl2_set_ethtool_ops(netdev);
1405
8d1b1fc9
KH		 1406#ifdef CONFIG_NET_POLL_CONTROLLER
1407 netdev->poll_controller = atl2_poll_controller;
1408#endif
452c1ce2
CS		 1409#ifdef HAVE_TX_TIMEOUT
1410 netdev->tx_timeout = &atl2_tx_timeout;
1411 netdev->watchdog_timeo = 5 * HZ;
1412#endif
1413#ifdef NETIF_F_HW_VLAN_TX
1414 netdev->vlan_rx_register = atl2_vlan_rx_register;
1415#endif
1416 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1417
1418 netdev->mem_start = mmio_start;
1419 netdev->mem_end = mmio_start + mmio_len;
1420 adapter->bd_number = cards_found;
1421 adapter->pci_using_64 = false;
1422
1423 /* setup the private structure */
1424 err = atl2_sw_init(adapter);
1425 if (err)
1426 goto err_sw_init;
1427
1428 err = -EIO;
1429
1430#ifdef NETIF_F_HW_VLAN_TX
1431 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
1432#endif
1433
452c1ce2
CS		 1434 /* Init PHY as early as possible due to power saving issue */
1435 atl2_phy_init(&adapter->hw);
1436
1437 /* reset the controller to
1438 * put the device in a known good starting state */
1439
1440 if (atl2_reset_hw(&adapter->hw)) {
1441 err = -EIO;
1442 goto err_reset;
1443 }
1444
1445 /* copy the MAC address out of the EEPROM */
1446 atl2_read_mac_addr(&adapter->hw);
1447 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
1448/* FIXME: do we still need this? */
1449#ifdef ETHTOOL_GPERMADDR
1450 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1451
1452 if (!is_valid_ether_addr(netdev->perm_addr)) {
1453#else
1454 if (!is_valid_ether_addr(netdev->dev_addr)) {
1455#endif
1456 err = -EIO;
1457 goto err_eeprom;
1458 }
1459
1460 atl2_check_options(adapter);
1461
1462 init_timer(&adapter->watchdog_timer);
1463 adapter->watchdog_timer.function = &atl2_watchdog;
1464 adapter->watchdog_timer.data = (unsigned long) adapter;
1465
1466 init_timer(&adapter->phy_config_timer);
1467 adapter->phy_config_timer.function = &atl2_phy_config;
1468 adapter->phy_config_timer.data = (unsigned long) adapter;
1469
1470 INIT_WORK(&adapter->reset_task, atl2_reset_task);
1471 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task);
1472
1473 strcpy(netdev->name, "eth%d"); /* ?? */
1474 err = register_netdev(netdev);
1475 if (err)
1476 goto err_register;
1477
1478 /* assume we have no link for now */
1479 netif_carrier_off(netdev);
1480 netif_stop_queue(netdev);
1481
1482 cards_found++;
1483
1484 return 0;
1485
1486err_reset:
1487err_register:
1488err_sw_init:
1489err_eeprom:
1490 iounmap(adapter->hw.hw_addr);
1491err_ioremap:
1492 free_netdev(netdev);
1493err_alloc_etherdev:
1494 pci_release_regions(pdev);
1495err_pci_reg:
1496err_dma:
1497 pci_disable_device(pdev);
1498 return err;
1499}
1500
1501/*
1502 * atl2_remove - Device Removal Routine
1503 * @pdev: PCI device information struct
1504 *
1505 * atl2_remove is called by the PCI subsystem to alert the driver
1506 * that it should release a PCI device. The could be caused by a
1507 * Hot-Plug event, or because the driver is going to be removed from
1508 * memory.
1509 */
1510/* FIXME: write the original MAC address back in case it was changed from a
1511 * BIOS-set value, as in atl1 -- CHS */
1512static void __devexit atl2_remove(struct pci_dev *pdev)
1513{
1514 struct net_device *netdev = pci_get_drvdata(pdev);
1515 struct atl2_adapter *adapter = netdev_priv(netdev);
1516
1517 /* flush_scheduled work may reschedule our watchdog task, so
1518 * explicitly disable watchdog tasks from being rescheduled */
1519 set_bit(__ATL2_DOWN, &adapter->flags);
1520
1521 del_timer_sync(&adapter->watchdog_timer);
1522 del_timer_sync(&adapter->phy_config_timer);
1523
1524 flush_scheduled_work();
1525
1526 unregister_netdev(netdev);
1527
1528 atl2_force_ps(&adapter->hw);
1529
1530 iounmap(adapter->hw.hw_addr);
1531 pci_release_regions(pdev);
1532
1533 free_netdev(netdev);
1534
1535 pci_disable_device(pdev);
1536}
1537
1538static int atl2_suspend(struct pci_dev *pdev, pm_message_t state)
1539{
1540 struct net_device *netdev = pci_get_drvdata(pdev);
1541 struct atl2_adapter *adapter = netdev_priv(netdev);
1542 struct atl2_hw *hw = &adapter->hw;
1543 u16 speed, duplex;
1544 u32 ctrl = 0;
1545 u32 wufc = adapter->wol;
1546
1547#ifdef CONFIG_PM
1548 int retval = 0;
1549#endif
1550
1551 netif_device_detach(netdev);
1552
1553 if (netif_running(netdev)) {
1554 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
1555 atl2_down(adapter);
1556 }
1557
1558#ifdef CONFIG_PM
1559 retval = pci_save_state(pdev);
1560 if (retval)
1561 return retval;
1562#endif
1563
1564 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1565 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1566 if (ctrl & BMSR_LSTATUS)
1567 wufc &= ~ATLX_WUFC_LNKC;
1568
1569 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) {
1570 u32 ret_val;
1571 /* get current link speed & duplex */
1572 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1573 if (ret_val) {
1574 printk(KERN_DEBUG
1575 "%s: get speed&duplex error while suspend\n",
1576 atl2_driver_name);
1577 goto wol_dis;
1578 }
1579
1580 ctrl = 0;
1581
1582 /* turn on magic packet wol */
1583 if (wufc & ATLX_WUFC_MAG)
1584 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
1585
1586 /* ignore Link Chg event when Link is up */
1587 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1588
1589 /* Config MAC CTRL Register */
1590 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1591 if (FULL_DUPLEX == adapter->link_duplex)
1592 ctrl |= MAC_CTRL_DUPLX;
1593 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1594 ctrl |= (((u32)adapter->hw.preamble_len &
1595 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1596 ctrl |= (((u32)(adapter->hw.retry_buf &
1597 MAC_CTRL_HALF_LEFT_BUF_MASK)) <<
1598 MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1599 if (wufc & ATLX_WUFC_MAG) {
1600 /* magic packet maybe Broadcast&multicast&Unicast */
1601 ctrl |= MAC_CTRL_BC_EN;
1602 }
1603
1604 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);
1605
1606 /* pcie patch */
1607 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1608 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1609 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1610 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1611 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1612 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1613
1614 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1615 goto suspend_exit;
1616 }
1617
1618 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) {
1619 /* link is down, so only LINK CHG WOL event enable */
1620 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
1621 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1622 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);
1623
1624 /* pcie patch */
1625 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1626 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1627 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1628 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1629 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1630 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1631
1632 hw->phy_configured = false; /* re-init PHY when resume */
1633
1634 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1635
1636 goto suspend_exit;
1637 }
1638
1639wol_dis:
1640 /* WOL disabled */
1641 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);
1642
1643 /* pcie patch */
1644 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1645 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1646 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1647 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1648 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1649 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1650
1651 atl2_force_ps(hw);
1652 hw->phy_configured = false; /* re-init PHY when resume */
1653
1654 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1655
1656suspend_exit:
1657 if (netif_running(netdev))
1658 atl2_free_irq(adapter);
1659
1660 pci_disable_device(pdev);
1661
1662 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1663
1664 return 0;
1665}
1666
1667#ifdef CONFIG_PM
1668static int atl2_resume(struct pci_dev *pdev)
1669{
1670 struct net_device *netdev = pci_get_drvdata(pdev);
1671 struct atl2_adapter *adapter = netdev_priv(netdev);
1672 u32 err;
1673
1674 pci_set_power_state(pdev, PCI_D0);
1675 pci_restore_state(pdev);
1676
1677 err = pci_enable_device(pdev);
1678 if (err) {
1679 printk(KERN_ERR
1680 "atl2: Cannot enable PCI device from suspend\n");
1681 return err;
1682 }
1683
1684 pci_set_master(pdev);
1685
1686 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
1687
1688 pci_enable_wake(pdev, PCI_D3hot, 0);
1689 pci_enable_wake(pdev, PCI_D3cold, 0);
1690
1691 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
1692
1693 err = atl2_request_irq(adapter);
1694 if (netif_running(netdev) && err)
1695 return err;
1696
1697 atl2_reset_hw(&adapter->hw);
1698
1699 if (netif_running(netdev))
1700 atl2_up(adapter);
1701
1702 netif_device_attach(netdev);
1703
1704 return 0;
1705}
1706#endif
1707
1708static void atl2_shutdown(struct pci_dev *pdev)
1709{
1710 atl2_suspend(pdev, PMSG_SUSPEND);
1711}
1712
1713static struct pci_driver atl2_driver = {
1714 .name = atl2_driver_name,
1715 .id_table = atl2_pci_tbl,
1716 .probe = atl2_probe,
1717 .remove = __devexit_p(atl2_remove),
1718 /* Power Managment Hooks */
1719 .suspend = atl2_suspend,
1720#ifdef CONFIG_PM
1721 .resume = atl2_resume,
1722#endif
1723 .shutdown = atl2_shutdown,
1724};
1725
1726/*
1727 * atl2_init_module - Driver Registration Routine
1728 *
1729 * atl2_init_module is the first routine called when the driver is
1730 * loaded. All it does is register with the PCI subsystem.
1731 */
1732static int __init atl2_init_module(void)
1733{
1734 printk(KERN_INFO "%s - version %s\n", atl2_driver_string,
1735 atl2_driver_version);
1736 printk(KERN_INFO "%s\n", atl2_copyright);
1737 return pci_register_driver(&atl2_driver);
1738}
1739module_init(atl2_init_module);
1740
1741/*
1742 * atl2_exit_module - Driver Exit Cleanup Routine
1743 *
1744 * atl2_exit_module is called just before the driver is removed
1745 * from memory.
1746 */
1747static void __exit atl2_exit_module(void)
1748{
1749 pci_unregister_driver(&atl2_driver);
1750}
1751module_exit(atl2_exit_module);
1752
1753static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1754{
1755 struct atl2_adapter *adapter = hw->back;
1756 pci_read_config_word(adapter->pdev, reg, value);
1757}
1758
1759static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1760{
1761 struct atl2_adapter *adapter = hw->back;
1762 pci_write_config_word(adapter->pdev, reg, *value);
1763}
1764
1765static int atl2_get_settings(struct net_device *netdev,
1766 struct ethtool_cmd *ecmd)
1767{
1768 struct atl2_adapter *adapter = netdev_priv(netdev);
1769 struct atl2_hw *hw = &adapter->hw;
1770
1771 ecmd->supported = (SUPPORTED_10baseT_Half |
1772 SUPPORTED_10baseT_Full |
1773 SUPPORTED_100baseT_Half |
1774 SUPPORTED_100baseT_Full |
1775 SUPPORTED_Autoneg |
1776 SUPPORTED_TP);
1777 ecmd->advertising = ADVERTISED_TP;
1778
1779 ecmd->advertising |= ADVERTISED_Autoneg;
1780 ecmd->advertising |= hw->autoneg_advertised;
1781
1782 ecmd->port = PORT_TP;
1783 ecmd->phy_address = 0;
1784 ecmd->transceiver = XCVR_INTERNAL;
1785
1786 if (adapter->link_speed != SPEED_0) {
1787 ecmd->speed = adapter->link_speed;
1788 if (adapter->link_duplex == FULL_DUPLEX)
1789 ecmd->duplex = DUPLEX_FULL;
1790 else
1791 ecmd->duplex = DUPLEX_HALF;
1792 } else {
1793 ecmd->speed = -1;
1794 ecmd->duplex = -1;
1795 }
1796
1797 ecmd->autoneg = AUTONEG_ENABLE;
1798 return 0;
1799}
1800
1801static int atl2_set_settings(struct net_device *netdev,
1802 struct ethtool_cmd *ecmd)
1803{
1804 struct atl2_adapter *adapter = netdev_priv(netdev);
1805 struct atl2_hw *hw = &adapter->hw;
1806
1807 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1808 msleep(1);
1809
1810 if (ecmd->autoneg == AUTONEG_ENABLE) {
1811#define MY_ADV_MASK (ADVERTISE_10_HALF | \
1812 ADVERTISE_10_FULL | \
1813 ADVERTISE_100_HALF| \
1814 ADVERTISE_100_FULL)
1815
1816 if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) {
1817 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR;
1818 hw->autoneg_advertised = MY_ADV_MASK;
1819 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1820 ADVERTISE_100_FULL) {
1821 hw->MediaType = MEDIA_TYPE_100M_FULL;
1822 hw->autoneg_advertised = ADVERTISE_100_FULL;
1823 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1824 ADVERTISE_100_HALF) {
1825 hw->MediaType = MEDIA_TYPE_100M_HALF;
1826 hw->autoneg_advertised = ADVERTISE_100_HALF;
1827 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1828 ADVERTISE_10_FULL) {
1829 hw->MediaType = MEDIA_TYPE_10M_FULL;
1830 hw->autoneg_advertised = ADVERTISE_10_FULL;
1831 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1832 ADVERTISE_10_HALF) {
1833 hw->MediaType = MEDIA_TYPE_10M_HALF;
1834 hw->autoneg_advertised = ADVERTISE_10_HALF;
1835 } else {
1836 clear_bit(__ATL2_RESETTING, &adapter->flags);
1837 return -EINVAL;
1838 }
1839 ecmd->advertising = hw->autoneg_advertised |
1840 ADVERTISED_TP | ADVERTISED_Autoneg;
1841 } else {
1842 clear_bit(__ATL2_RESETTING, &adapter->flags);
1843 return -EINVAL;
1844 }
1845
1846 /* reset the link */
1847 if (netif_running(adapter->netdev)) {
1848 atl2_down(adapter);
1849 atl2_up(adapter);
1850 } else
1851 atl2_reset_hw(&adapter->hw);
1852
1853 clear_bit(__ATL2_RESETTING, &adapter->flags);
1854 return 0;
1855}
1856
1857static u32 atl2_get_tx_csum(struct net_device *netdev)
1858{
1859 return (netdev->features & NETIF_F_HW_CSUM) != 0;
1860}
1861
1862static u32 atl2_get_msglevel(struct net_device *netdev)
1863{
1864 return 0;
1865}
1866
1867/*
1868 * It's sane for this to be empty, but we might want to take advantage of this.
1869 */
1870static void atl2_set_msglevel(struct net_device *netdev, u32 data)
1871{
1872}
1873
1874static int atl2_get_regs_len(struct net_device *netdev)
1875{
1876#define ATL2_REGS_LEN 42
1877 return sizeof(u32) * ATL2_REGS_LEN;
1878}
1879
1880static void atl2_get_regs(struct net_device *netdev,
1881 struct ethtool_regs *regs, void *p)
1882{
1883 struct atl2_adapter *adapter = netdev_priv(netdev);
1884 struct atl2_hw *hw = &adapter->hw;
1885 u32 *regs_buff = p;
1886 u16 phy_data;
1887
1888 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN);
1889
1890 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
1891
1892 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP);
1893 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
1894 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG);
1895 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL);
1896 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
1897 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL);
1898 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT);
1899 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
1900 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE);
1901 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER);
1902 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS);
1903 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL);
1904 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK);
1905 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL);
1906 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG);
1907 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
1908 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4);
1909 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE);
1910 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4);
1911 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
1912 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU);
1913 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL);
1914 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END);
1915 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI);
1916 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO);
1917 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE);
1918 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO);
1919 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE);
1920 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO);
1921 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM);
1922 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR);
1923 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH);
1924 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW);
1925 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH);
1926 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH);
1927 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX);
1928 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX);
1929 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR);
1930 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR);
1931
1932 atl2_read_phy_reg(hw, MII_BMCR, &phy_data);
1933 regs_buff[40] = (u32)phy_data;
1934 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1935 regs_buff[41] = (u32)phy_data;
1936}
1937
1938static int atl2_get_eeprom_len(struct net_device *netdev)
1939{
1940 struct atl2_adapter *adapter = netdev_priv(netdev);
1941
1942 if (!atl2_check_eeprom_exist(&adapter->hw))
1943 return 512;
1944 else
1945 return 0;
1946}
1947
1948static int atl2_get_eeprom(struct net_device *netdev,
1949 struct ethtool_eeprom *eeprom, u8 *bytes)
1950{
1951 struct atl2_adapter *adapter = netdev_priv(netdev);
1952 struct atl2_hw *hw = &adapter->hw;
1953 u32 *eeprom_buff;
1954 int first_dword, last_dword;
1955 int ret_val = 0;
1956 int i;
1957
1958 if (eeprom->len == 0)
1959 return -EINVAL;
1960
1961 if (atl2_check_eeprom_exist(hw))
1962 return -EINVAL;
1963
1964 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1965
1966 first_dword = eeprom->offset >> 2;
1967 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1968
1969 eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1),
1970 GFP_KERNEL);
1971 if (!eeprom_buff)
1972 return -ENOMEM;
1973
1974 for (i = first_dword; i < last_dword; i++) {
1975 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword])))
1976 return -EIO;
1977 }
1978
1979 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
1980 eeprom->len);
1981 kfree(eeprom_buff);
1982
1983 return ret_val;
1984}
1985
1986static int atl2_set_eeprom(struct net_device *netdev,
1987 struct ethtool_eeprom *eeprom, u8 *bytes)
1988{
1989 struct atl2_adapter *adapter = netdev_priv(netdev);
1990 struct atl2_hw *hw = &adapter->hw;
1991 u32 *eeprom_buff;
1992 u32 *ptr;
1993 int max_len, first_dword, last_dword, ret_val = 0;
1994 int i;
1995
1996 if (eeprom->len == 0)
1997 return -EOPNOTSUPP;
1998
1999 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
2000 return -EFAULT;
2001
2002 max_len = 512;
2003
2004 first_dword = eeprom->offset >> 2;
2005 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
2006 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
2007 if (!eeprom_buff)
2008 return -ENOMEM;
2009
2010 ptr = (u32 *)eeprom_buff;
2011
2012 if (eeprom->offset & 3) {
2013 /* need read/modify/write of first changed EEPROM word */
2014 /* only the second byte of the word is being modified */
2015 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0])))
2016 return -EIO;
2017 ptr++;
2018 }
2019 if (((eeprom->offset + eeprom->len) & 3)) {
2020 /*
2021 * need read/modify/write of last changed EEPROM word
2022 * only the first byte of the word is being modified
2023 */
2024 if (!atl2_read_eeprom(hw, last_dword * 4,
2025 &(eeprom_buff[last_dword - first_dword])))
2026 return -EIO;
2027 }
2028
2029 /* Device's eeprom is always little-endian, word addressable */
2030 memcpy(ptr, bytes, eeprom->len);
2031
2032 for (i = 0; i < last_dword - first_dword + 1; i++) {
2033 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i]))
2034 return -EIO;
2035 }
2036
2037 kfree(eeprom_buff);
2038 return ret_val;
2039}
2040
2041static void atl2_get_drvinfo(struct net_device *netdev,
2042 struct ethtool_drvinfo *drvinfo)
2043{
2044 struct atl2_adapter *adapter = netdev_priv(netdev);
2045
2046 strncpy(drvinfo->driver, atl2_driver_name, 32);
2047 strncpy(drvinfo->version, atl2_driver_version, 32);
2048 strncpy(drvinfo->fw_version, "L2", 32);
2049 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
2050 drvinfo->n_stats = 0;
2051 drvinfo->testinfo_len = 0;
2052 drvinfo->regdump_len = atl2_get_regs_len(netdev);
2053 drvinfo->eedump_len = atl2_get_eeprom_len(netdev);
2054}
2055
2056static void atl2_get_wol(struct net_device *netdev,
2057 struct ethtool_wolinfo *wol)
2058{
2059 struct atl2_adapter *adapter = netdev_priv(netdev);
2060
2061 wol->supported = WAKE_MAGIC;
2062 wol->wolopts = 0;
2063
2064 if (adapter->wol & ATLX_WUFC_EX)
2065 wol->wolopts |= WAKE_UCAST;
2066 if (adapter->wol & ATLX_WUFC_MC)
2067 wol->wolopts |= WAKE_MCAST;
2068 if (adapter->wol & ATLX_WUFC_BC)
2069 wol->wolopts |= WAKE_BCAST;
2070 if (adapter->wol & ATLX_WUFC_MAG)
2071 wol->wolopts |= WAKE_MAGIC;
2072 if (adapter->wol & ATLX_WUFC_LNKC)
2073 wol->wolopts |= WAKE_PHY;
2074}
2075
2076static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2077{
2078 struct atl2_adapter *adapter = netdev_priv(netdev);
2079
2080 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2081 return -EOPNOTSUPP;
2082
2083 if (wol->wolopts & (WAKE_MCAST|WAKE_BCAST|WAKE_MCAST))
2084 return -EOPNOTSUPP;
2085
2086 /* these settings will always override what we currently have */
2087 adapter->wol = 0;
2088
2089 if (wol->wolopts & WAKE_MAGIC)
2090 adapter->wol |= ATLX_WUFC_MAG;
2091 if (wol->wolopts & WAKE_PHY)
2092 adapter->wol |= ATLX_WUFC_LNKC;
2093
2094 return 0;
2095}
2096
2097static int atl2_nway_reset(struct net_device *netdev)
2098{
2099 struct atl2_adapter *adapter = netdev_priv(netdev);
2100 if (netif_running(netdev))
2101 atl2_reinit_locked(adapter);
2102 return 0;
2103}
2104
2105static struct ethtool_ops atl2_ethtool_ops = {
2106 .get_settings = atl2_get_settings,
2107 .set_settings = atl2_set_settings,
2108 .get_drvinfo = atl2_get_drvinfo,
2109 .get_regs_len = atl2_get_regs_len,
2110 .get_regs = atl2_get_regs,
2111 .get_wol = atl2_get_wol,
2112 .set_wol = atl2_set_wol,
2113 .get_msglevel = atl2_get_msglevel,
2114 .set_msglevel = atl2_set_msglevel,
2115 .nway_reset = atl2_nway_reset,
2116 .get_link = ethtool_op_get_link,
2117 .get_eeprom_len = atl2_get_eeprom_len,
2118 .get_eeprom = atl2_get_eeprom,
2119 .set_eeprom = atl2_set_eeprom,
2120 .get_tx_csum = atl2_get_tx_csum,
2121 .get_sg = ethtool_op_get_sg,
2122 .set_sg = ethtool_op_set_sg,
2123#ifdef NETIF_F_TSO
2124 .get_tso = ethtool_op_get_tso,
2125#endif
2126};
2127
2128static void atl2_set_ethtool_ops(struct net_device *netdev)
2129{
2130 SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops);
2131}
2132
2133#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
2134 (((a) & 0xff00ff00) >> 8))
2135#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
2136#define SHORTSWAP(a) (((a) << 8) | ((a) >> 8))
2137
2138/*
2139 * Reset the transmit and receive units; mask and clear all interrupts.
2140 *
2141 * hw - Struct containing variables accessed by shared code
2142 * return : 0 or idle status (if error)
2143 */
2144static s32 atl2_reset_hw(struct atl2_hw *hw)
2145{
2146 u32 icr;
2147 u16 pci_cfg_cmd_word;
2148 int i;
2149
2150 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
2151 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2152 if ((pci_cfg_cmd_word &
2153 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) !=
2154 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) {
2155 pci_cfg_cmd_word |=
2156 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER);
2157 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2158 }
2159
2160 /* Clear Interrupt mask to stop board from generating
2161 * interrupts & Clear any pending interrupt events
2162 */
2163 /* FIXME */
2164 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */
2165 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */
2166
2167 /* Issue Soft Reset to the MAC. This will reset the chip's
2168 * transmit, receive, DMA. It will not effect
2169 * the current PCI configuration. The global reset bit is self-
2170 * clearing, and should clear within a microsecond.
2171 */
2172 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
2173 wmb();
2174 msleep(1); /* delay about 1ms */
2175
2176 /* Wait at least 10ms for All module to be Idle */
2177 for (i = 0; i < 10; i++) {
2178 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS);
2179 if (!icr)
2180 break;
2181 msleep(1); /* delay 1 ms */
2182 cpu_relax();
2183 }
2184
2185 if (icr)
2186 return icr;
2187
2188 return 0;
2189}
2190
2191#define CUSTOM_SPI_CS_SETUP 2
2192#define CUSTOM_SPI_CLK_HI 2
2193#define CUSTOM_SPI_CLK_LO 2
2194#define CUSTOM_SPI_CS_HOLD 2
2195#define CUSTOM_SPI_CS_HI 3
2196
2197static struct atl2_spi_flash_dev flash_table[] =
2198{
2199/* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
2200{"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 },
2201{"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 },
2202{"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 },
2203};
2204
2205static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf)
2206{
2207 int i;
2208 u32 value;
2209
2210 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);
2211 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);
2212
2213 value = SPI_FLASH_CTRL_WAIT_READY |
2214 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
2215 SPI_FLASH_CTRL_CS_SETUP_SHIFT |
2216 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) <<
2217 SPI_FLASH_CTRL_CLK_HI_SHIFT |
2218 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) <<
2219 SPI_FLASH_CTRL_CLK_LO_SHIFT |
2220 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) <<
2221 SPI_FLASH_CTRL_CS_HOLD_SHIFT |
2222 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) <<
2223 SPI_FLASH_CTRL_CS_HI_SHIFT |
2224 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT;
2225
2226 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2227
2228 value |= SPI_FLASH_CTRL_START;
2229
2230 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2231
2232 for (i = 0; i < 10; i++) {
2233 msleep(1);
2234 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2235 if (!(value & SPI_FLASH_CTRL_START))
2236 break;
2237 }
2238
2239 if (value & SPI_FLASH_CTRL_START)
2240 return false;
2241
2242 *buf = ATL2_READ_REG(hw, REG_SPI_DATA);
2243
2244 return true;
2245}
2246
2247/*
2248 * get_permanent_address
2249 * return 0 if get valid mac address,
2250 */
2251static int get_permanent_address(struct atl2_hw *hw)
2252{
2253 u32 Addr[2];
2254 u32 i, Control;
2255 u16 Register;
2256 u8 EthAddr[NODE_ADDRESS_SIZE];
2257 bool KeyValid;
2258
2259 if (is_valid_ether_addr(hw->perm_mac_addr))
2260 return 0;
2261
2262 Addr[0] = 0;
2263 Addr[1] = 0;
2264
2265 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */
2266 Register = 0;
2267 KeyValid = false;
2268
2269 /* Read out all EEPROM content */
2270 i = 0;
2271 while (1) {
2272 if (atl2_read_eeprom(hw, i + 0x100, &Control)) {
2273 if (KeyValid) {
2274 if (Register == REG_MAC_STA_ADDR)
2275 Addr[0] = Control;
2276 else if (Register ==
2277 (REG_MAC_STA_ADDR + 4))
2278 Addr[1] = Control;
2279 KeyValid = false;
2280 } else if ((Control & 0xff) == 0x5A) {
2281 KeyValid = true;
2282 Register = (u16) (Control >> 16);
2283 } else {
2284 /* assume data end while encount an invalid KEYWORD */
2285 break;
2286 }
2287 } else {
2288 break; /* read error */
2289 }
2290 i += 4;
2291 }
2292
2293 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2294 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2295
2296 if (is_valid_ether_addr(EthAddr)) {
2297 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2298 return 0;
2299 }
2300 return 1;
2301 }
2302
2303 /* see if SPI flash exists? */
2304 Addr[0] = 0;
2305 Addr[1] = 0;
2306 Register = 0;
2307 KeyValid = false;
2308 i = 0;
2309 while (1) {
2310 if (atl2_spi_read(hw, i + 0x1f000, &Control)) {
2311 if (KeyValid) {
2312 if (Register == REG_MAC_STA_ADDR)
2313 Addr[0] = Control;
2314 else if (Register == (REG_MAC_STA_ADDR + 4))
2315 Addr[1] = Control;
2316 KeyValid = false;
2317 } else if ((Control & 0xff) == 0x5A) {
2318 KeyValid = true;
2319 Register = (u16) (Control >> 16);
2320 } else {
2321 break; /* data end */
2322 }
2323 } else {
2324 break; /* read error */
2325 }
2326 i += 4;
2327 }
2328
2329 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2330 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]);
2331 if (is_valid_ether_addr(EthAddr)) {
2332 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2333 return 0;
2334 }
2335 /* maybe MAC-address is from BIOS */
2336 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
2337 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4);
2338 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2339 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2340
2341 if (is_valid_ether_addr(EthAddr)) {
2342 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2343 return 0;
2344 }
2345
2346 return 1;
2347}
2348
2349/*
2350 * Reads the adapter's MAC address from the EEPROM
2351 *
2352 * hw - Struct containing variables accessed by shared code
2353 */
2354static s32 atl2_read_mac_addr(struct atl2_hw *hw)
2355{
2356 u16 i;
2357
2358 if (get_permanent_address(hw)) {
2359 /* for test */
2360 /* FIXME: shouldn't we use random_ether_addr() here? */
2361 hw->perm_mac_addr[0] = 0x00;
2362 hw->perm_mac_addr[1] = 0x13;
2363 hw->perm_mac_addr[2] = 0x74;
2364 hw->perm_mac_addr[3] = 0x00;
2365 hw->perm_mac_addr[4] = 0x5c;
2366 hw->perm_mac_addr[5] = 0x38;
2367 }
2368
2369 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
2370 hw->mac_addr[i] = hw->perm_mac_addr[i];
2371
2372 return 0;
2373}
2374
2375/*
2376 * Hashes an address to determine its location in the multicast table
2377 *
2378 * hw - Struct containing variables accessed by shared code
2379 * mc_addr - the multicast address to hash
2380 *
2381 * atl2_hash_mc_addr
2382 * purpose
2383 * set hash value for a multicast address
2384 * hash calcu processing :
2385 * 1. calcu 32bit CRC for multicast address
2386 * 2. reverse crc with MSB to LSB
2387 */
2388static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr)
2389{
2390 u32 crc32, value;
2391 int i;
2392
2393 value = 0;
2394 crc32 = ether_crc_le(6, mc_addr);
2395
2396 for (i = 0; i < 32; i++)
2397 value |= (((crc32 >> i) & 1) << (31 - i));
2398
2399 return value;
2400}
2401
2402/*
2403 * Sets the bit in the multicast table corresponding to the hash value.
2404 *
2405 * hw - Struct containing variables accessed by shared code
2406 * hash_value - Multicast address hash value
2407 */
2408static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value)
2409{
2410 u32 hash_bit, hash_reg;
2411 u32 mta;
2412
2413 /* The HASH Table is a register array of 2 32-bit registers.
2414 * It is treated like an array of 64 bits. We want to set
2415 * bit BitArray[hash_value]. So we figure out what register
2416 * the bit is in, read it, OR in the new bit, then write
2417 * back the new value. The register is determined by the
2418 * upper 7 bits of the hash value and the bit within that
2419 * register are determined by the lower 5 bits of the value.
2420 */
2421 hash_reg = (hash_value >> 31) & 0x1;
2422 hash_bit = (hash_value >> 26) & 0x1F;
2423
2424 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
2425
2426 mta |= (1 << hash_bit);
2427
2428 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
2429}
2430
2431/*
2432 * atl2_init_pcie - init PCIE module
2433 */
2434static void atl2_init_pcie(struct atl2_hw *hw)
2435{
2436 u32 value;
2437 value = LTSSM_TEST_MODE_DEF;
2438 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
2439
2440 value = PCIE_DLL_TX_CTRL1_DEF;
2441 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);
2442}
2443
2444static void atl2_init_flash_opcode(struct atl2_hw *hw)
2445{
2446 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
2447 hw->flash_vendor = 0; /* ATMEL */
2448
2449 /* Init OP table */
2450 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM,
2451 flash_table[hw->flash_vendor].cmdPROGRAM);
2452 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE,
2453 flash_table[hw->flash_vendor].cmdSECTOR_ERASE);
2454 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE,
2455 flash_table[hw->flash_vendor].cmdCHIP_ERASE);
2456 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID,
2457 flash_table[hw->flash_vendor].cmdRDID);
2458 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN,
2459 flash_table[hw->flash_vendor].cmdWREN);
2460 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR,
2461 flash_table[hw->flash_vendor].cmdRDSR);
2462 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR,
2463 flash_table[hw->flash_vendor].cmdWRSR);
2464 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ,
2465 flash_table[hw->flash_vendor].cmdREAD);
2466}
2467
2468/********************************************************************
2469* Performs basic configuration of the adapter.
2470*
2471* hw - Struct containing variables accessed by shared code
2472* Assumes that the controller has previously been reset and is in a
2473* post-reset uninitialized state. Initializes multicast table,
2474* and Calls routines to setup link
2475* Leaves the transmit and receive units disabled and uninitialized.
2476********************************************************************/
2477static s32 atl2_init_hw(struct atl2_hw *hw)
2478{
2479 u32 ret_val = 0;
2480
2481 atl2_init_pcie(hw);
2482
2483 /* Zero out the Multicast HASH table */
2484 /* clear the old settings from the multicast hash table */
2485 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
2486 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
2487
2488 atl2_init_flash_opcode(hw);
2489
2490 ret_val = atl2_phy_init(hw);
2491
2492 return ret_val;
2493}
2494
2495/*
2496 * Detects the current speed and duplex settings of the hardware.
2497 *
2498 * hw - Struct containing variables accessed by shared code
2499 * speed - Speed of the connection
2500 * duplex - Duplex setting of the connection
2501 */
2502static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
2503 u16 *duplex)
2504{
2505 s32 ret_val;
2506 u16 phy_data;
2507
2508 /* Read PHY Specific Status Register (17) */
2509 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
2510 if (ret_val)
2511 return ret_val;
2512
2513 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
2514 return ATLX_ERR_PHY_RES;
2515
2516 switch (phy_data & MII_ATLX_PSSR_SPEED) {
2517 case MII_ATLX_PSSR_100MBS:
2518 *speed = SPEED_100;
2519 break;
2520 case MII_ATLX_PSSR_10MBS:
2521 *speed = SPEED_10;
2522 break;
2523 default:
2524 return ATLX_ERR_PHY_SPEED;
2525 break;
2526 }
2527
2528 if (phy_data & MII_ATLX_PSSR_DPLX)
2529 *duplex = FULL_DUPLEX;
2530 else
2531 *duplex = HALF_DUPLEX;
2532
2533 return 0;
2534}
2535
2536/*
2537 * Reads the value from a PHY register
2538 * hw - Struct containing variables accessed by shared code
2539 * reg_addr - address of the PHY register to read
2540 */
2541static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data)
2542{
2543 u32 val;
2544 int i;
2545
2546 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
2547 MDIO_START |
2548 MDIO_SUP_PREAMBLE |
2549 MDIO_RW |
2550 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2551 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2552
2553 wmb();
2554
2555 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2556 udelay(2);
2557 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2558 if (!(val & (MDIO_START | MDIO_BUSY)))
2559 break;
2560 wmb();
2561 }
2562 if (!(val & (MDIO_START | MDIO_BUSY))) {
2563 *phy_data = (u16)val;
2564 return 0;
2565 }
2566
2567 return ATLX_ERR_PHY;
2568}
2569
2570/*
2571 * Writes a value to a PHY register
2572 * hw - Struct containing variables accessed by shared code
2573 * reg_addr - address of the PHY register to write
2574 * data - data to write to the PHY
2575 */
2576static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data)
2577{
2578 int i;
2579 u32 val;
2580
2581 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
2582 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
2583 MDIO_SUP_PREAMBLE |
2584 MDIO_START |
2585 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2586 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2587
2588 wmb();
2589
2590 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2591 udelay(2);
2592 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2593 if (!(val & (MDIO_START | MDIO_BUSY)))
2594 break;
2595
2596 wmb();
2597 }
2598
2599 if (!(val & (MDIO_START | MDIO_BUSY)))
2600 return 0;
2601
2602 return ATLX_ERR_PHY;
2603}
2604
2605/*
2606 * Configures PHY autoneg and flow control advertisement settings
2607 *
2608 * hw - Struct containing variables accessed by shared code
2609 */
2610static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw)
2611{
2612 s32 ret_val;
2613 s16 mii_autoneg_adv_reg;
2614
2615 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2616 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
2617
2618 /* Need to parse autoneg_advertised and set up
2619 * the appropriate PHY registers. First we will parse for
2620 * autoneg_advertised software override. Since we can advertise
2621 * a plethora of combinations, we need to check each bit
2622 * individually.
2623 */
2624
2625 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2626 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2627 * the 1000Base-T Control Register (Address 9). */
2628 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
2629
2630 /* Need to parse MediaType and setup the
2631 * appropriate PHY registers. */
2632 switch (hw->MediaType) {
2633 case MEDIA_TYPE_AUTO_SENSOR:
2634 mii_autoneg_adv_reg |=
2635 (MII_AR_10T_HD_CAPS |
2636 MII_AR_10T_FD_CAPS |
2637 MII_AR_100TX_HD_CAPS|
2638 MII_AR_100TX_FD_CAPS);
2639 hw->autoneg_advertised =
2640 ADVERTISE_10_HALF |
2641 ADVERTISE_10_FULL |
2642 ADVERTISE_100_HALF|
2643 ADVERTISE_100_FULL;
2644 break;
2645 case MEDIA_TYPE_100M_FULL:
2646 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
2647 hw->autoneg_advertised = ADVERTISE_100_FULL;
2648 break;
2649 case MEDIA_TYPE_100M_HALF:
2650 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
2651 hw->autoneg_advertised = ADVERTISE_100_HALF;
2652 break;
2653 case MEDIA_TYPE_10M_FULL:
2654 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
2655 hw->autoneg_advertised = ADVERTISE_10_FULL;
2656 break;
2657 default:
2658 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
2659 hw->autoneg_advertised = ADVERTISE_10_HALF;
2660 break;
2661 }
2662
2663 /* flow control fixed to enable all */
2664 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
2665
2666 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
2667
2668 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
2669
2670 if (ret_val)
2671 return ret_val;
2672
2673 return 0;
2674}
2675
2676/*
2677 * Resets the PHY and make all config validate
2678 *
2679 * hw - Struct containing variables accessed by shared code
2680 *
2681 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
2682 */
2683static s32 atl2_phy_commit(struct atl2_hw *hw)
2684{
2685 s32 ret_val;
2686 u16 phy_data;
2687
2688 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2689 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data);
2690 if (ret_val) {
2691 u32 val;
2692 int i;
2693 /* pcie serdes link may be down ! */
2694 for (i = 0; i < 25; i++) {
2695 msleep(1);
2696 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2697 if (!(val & (MDIO_START | MDIO_BUSY)))
2698 break;
2699 }
2700
2701 if (0 != (val & (MDIO_START | MDIO_BUSY))) {
2702 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n");
2703 return ret_val;
2704 }
2705 }
2706 return 0;
2707}
2708
2709static s32 atl2_phy_init(struct atl2_hw *hw)
2710{
2711 s32 ret_val;
2712 u16 phy_val;
2713
2714 if (hw->phy_configured)
2715 return 0;
2716
2717 /* Enable PHY */
2718 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1);
2719 ATL2_WRITE_FLUSH(hw);
2720 msleep(1);
2721
2722 /* check if the PHY is in powersaving mode */
2723 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2724 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2725
2726 /* 024E / 124E 0r 0274 / 1274 ? */
2727 if (phy_val & 0x1000) {
2728 phy_val &= ~0x1000;
2729 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val);
2730 }
2731
2732 msleep(1);
2733
2734 /*Enable PHY LinkChange Interrupt */
2735 ret_val = atl2_write_phy_reg(hw, 18, 0xC00);
2736 if (ret_val)
2737 return ret_val;
2738
2739 /* setup AutoNeg parameters */
2740 ret_val = atl2_phy_setup_autoneg_adv(hw);
2741 if (ret_val)
2742 return ret_val;
2743
2744 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */
2745 ret_val = atl2_phy_commit(hw);
2746 if (ret_val)
2747 return ret_val;
2748
2749 hw->phy_configured = true;
2750
2751 return ret_val;
2752}
2753
2754static void atl2_set_mac_addr(struct atl2_hw *hw)
2755{
2756 u32 value;
2757 /* 00-0B-6A-F6-00-DC
2758 * 0: 6AF600DC 1: 000B
2759 * low dword */
2760 value = (((u32)hw->mac_addr[2]) << 24) |
2761 (((u32)hw->mac_addr[3]) << 16) |
2762 (((u32)hw->mac_addr[4]) << 8) |
2763 (((u32)hw->mac_addr[5]));
2764 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
2765 /* hight dword */
2766 value = (((u32)hw->mac_addr[0]) << 8) |
2767 (((u32)hw->mac_addr[1]));
2768 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
2769}
2770
2771/*
2772 * check_eeprom_exist
2773 * return 0 if eeprom exist
2774 */
2775static int atl2_check_eeprom_exist(struct atl2_hw *hw)
2776{
2777 u32 value;
2778
2779 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2780 if (value & SPI_FLASH_CTRL_EN_VPD) {
2781 value &= ~SPI_FLASH_CTRL_EN_VPD;
2782 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2783 }
2784 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST);
2785 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
2786}
2787
2788/* FIXME: This doesn't look right. -- CHS */
2789static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value)
2790{
2791 return true;
2792}
2793
2794static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue)
2795{
2796 int i;
2797 u32 Control;
2798
2799 if (Offset & 0x3)
2800 return false; /* address do not align */
2801
2802 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);
2803 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
2804 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);
2805
2806 for (i = 0; i < 10; i++) {
2807 msleep(2);
2808 Control = ATL2_READ_REG(hw, REG_VPD_CAP);
2809 if (Control & VPD_CAP_VPD_FLAG)
2810 break;
2811 }
2812
2813 if (Control & VPD_CAP_VPD_FLAG) {
2814 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA);
2815 return true;
2816 }
2817 return false; /* timeout */
2818}
2819
2820static void atl2_force_ps(struct atl2_hw *hw)
2821{
2822 u16 phy_val;
2823
2824 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2825 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2826 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000);
2827
2828 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2);
2829 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
2830 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3);
2831 atl2_write_phy_reg(hw, MII_DBG_DATA, 0);
2832}
2833
2834/* This is the only thing that needs to be changed to adjust the
2835 * maximum number of ports that the driver can manage.
2836 */
2837#define ATL2_MAX_NIC 4
2838
2839#define OPTION_UNSET -1
2840#define OPTION_DISABLED 0
2841#define OPTION_ENABLED 1
2842
2843/* All parameters are treated the same, as an integer array of values.
2844 * This macro just reduces the need to repeat the same declaration code
2845 * over and over (plus this helps to avoid typo bugs).
2846 */
2847#define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET}
2848#ifndef module_param_array
2849/* Module Parameters are always initialized to -1, so that the driver
2850 * can tell the difference between no user specified value or the
2851 * user asking for the default value.
2852 * The true default values are loaded in when atl2_check_options is called.
2853 *
2854 * This is a GCC extension to ANSI C.
2855 * See the item "Labeled Elements in Initializers" in the section
2856 * "Extensions to the C Language Family" of the GCC documentation.
2857 */
2858
2859#define ATL2_PARAM(X, desc) \
2860 static const int __devinitdata X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \
2861 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \
2862 MODULE_PARM_DESC(X, desc);
2863#else
2864#define ATL2_PARAM(X, desc) \
2865 static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \
2866 static int num_##X = 0; \
2867 module_param_array_named(X, X, int, &num_##X, 0); \
2868 MODULE_PARM_DESC(X, desc);
2869#endif
2870
2871/*
2872 * Transmit Memory Size
2873 * Valid Range: 64-2048
2874 * Default Value: 128
2875 */
2876#define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */
2877#define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */
2878#define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */
2879ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory");
2880
2881/*
2882 * Receive Memory Block Count
2883 * Valid Range: 16-512
2884 * Default Value: 128
2885 */
2886#define ATL2_MIN_RXD_COUNT 16
2887#define ATL2_MAX_RXD_COUNT 512
2888#define ATL2_DEFAULT_RXD_COUNT 64
2889ATL2_PARAM(RxMemBlock, "Number of receive memory block");
2890
2891/*
2892 * User Specified MediaType Override
2893 *
2894 * Valid Range: 0-5
2895 * - 0 - auto-negotiate at all supported speeds
2896 * - 1 - only link at 1000Mbps Full Duplex
2897 * - 2 - only link at 100Mbps Full Duplex
2898 * - 3 - only link at 100Mbps Half Duplex
2899 * - 4 - only link at 10Mbps Full Duplex
2900 * - 5 - only link at 10Mbps Half Duplex
2901 * Default Value: 0
2902 */
2903ATL2_PARAM(MediaType, "MediaType Select");
2904
2905/*
2906 * Interrupt Moderate Timer in units of 2048 ns (~2 us)
2907 * Valid Range: 10-65535
2908 * Default Value: 45000(90ms)
2909 */
2910#define INT_MOD_DEFAULT_CNT 100 /* 200us */
2911#define INT_MOD_MAX_CNT 65000
2912#define INT_MOD_MIN_CNT 50
2913ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer");
2914
2915/*
2916 * FlashVendor
2917 * Valid Range: 0-2
2918 * 0 - Atmel
2919 * 1 - SST
2920 * 2 - ST
2921 */
2922ATL2_PARAM(FlashVendor, "SPI Flash Vendor");
2923
2924#define AUTONEG_ADV_DEFAULT 0x2F
2925#define AUTONEG_ADV_MASK 0x2F
2926#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
2927
2928#define FLASH_VENDOR_DEFAULT 0
2929#define FLASH_VENDOR_MIN 0
2930#define FLASH_VENDOR_MAX 2
2931
2932struct atl2_option {
2933 enum { enable_option, range_option, list_option } type;
2934 char *name;
2935 char *err;
2936 int def;
2937 union {
2938 struct { /* range_option info */
2939 int min;
2940 int max;
2941 } r;
2942 struct { /* list_option info */
2943 int nr;
2944 struct atl2_opt_list { int i; char *str; } *p;
2945 } l;
2946 } arg;
2947};
2948
2949static int __devinit atl2_validate_option(int *value, struct atl2_option *opt)
2950{
2951 int i;
2952 struct atl2_opt_list *ent;
2953
2954 if (*value == OPTION_UNSET) {
2955 *value = opt->def;
2956 return 0;
2957 }
2958
2959 switch (opt->type) {
2960 case enable_option:
2961 switch (*value) {
2962 case OPTION_ENABLED:
2963 printk(KERN_INFO "%s Enabled\n", opt->name);
2964 return 0;
2965 break;
2966 case OPTION_DISABLED:
2967 printk(KERN_INFO "%s Disabled\n", opt->name);
2968 return 0;
2969 break;
2970 }
2971 break;
2972 case range_option:
2973 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
2974 printk(KERN_INFO "%s set to %i\n", opt->name, *value);
2975 return 0;
2976 }
2977 break;
2978 case list_option:
2979 for (i = 0; i < opt->arg.l.nr; i++) {
2980 ent = &opt->arg.l.p[i];
2981 if (*value == ent->i) {
2982 if (ent->str[0] != '\0')
2983 printk(KERN_INFO "%s\n", ent->str);
2984 return 0;
2985 }
2986 }
2987 break;
2988 default:
2989 BUG();
2990 }
2991
2992 printk(KERN_INFO "Invalid %s specified (%i) %s\n",
2993 opt->name, *value, opt->err);
2994 *value = opt->def;
2995 return -1;
2996}
2997
2998/*
2999 * atl2_check_options - Range Checking for Command Line Parameters
3000 * @adapter: board private structure
3001 *
3002 * This routine checks all command line parameters for valid user
3003 * input. If an invalid value is given, or if no user specified
3004 * value exists, a default value is used. The final value is stored
3005 * in a variable in the adapter structure.
3006 */
3007static void __devinit atl2_check_options(struct atl2_adapter *adapter)
3008{
3009 int val;
3010 struct atl2_option opt;
3011 int bd = adapter->bd_number;
3012 if (bd >= ATL2_MAX_NIC) {
3013 printk(KERN_NOTICE "Warning: no configuration for board #%i\n",
3014 bd);
3015 printk(KERN_NOTICE "Using defaults for all values\n");
3016#ifndef module_param_array
3017 bd = ATL2_MAX_NIC;
3018#endif
3019 }
3020
3021 /* Bytes of Transmit Memory */
3022 opt.type = range_option;
3023 opt.name = "Bytes of Transmit Memory";
3024 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE);
3025 opt.def = ATL2_DEFAULT_TX_MEMSIZE;
3026 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE;
3027 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE;
3028#ifdef module_param_array
3029 if (num_TxMemSize > bd) {
3030#endif
3031 val = TxMemSize[bd];
3032 atl2_validate_option(&val, &opt);
3033 adapter->txd_ring_size = ((u32) val) * 1024;
3034#ifdef module_param_array
3035 } else
3036 adapter->txd_ring_size = ((u32)opt.def) * 1024;
3037#endif
3038 /* txs ring size: */
3039 adapter->txs_ring_size = adapter->txd_ring_size / 128;
3040 if (adapter->txs_ring_size > 160)
3041 adapter->txs_ring_size = 160;
3042
3043 /* Receive Memory Block Count */
3044 opt.type = range_option;
3045 opt.name = "Number of receive memory block";
3046 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT);
3047 opt.def = ATL2_DEFAULT_RXD_COUNT;
3048 opt.arg.r.min = ATL2_MIN_RXD_COUNT;
3049 opt.arg.r.max = ATL2_MAX_RXD_COUNT;
3050#ifdef module_param_array
3051 if (num_RxMemBlock > bd) {
3052#endif
3053 val = RxMemBlock[bd];
3054 atl2_validate_option(&val, &opt);
3055 adapter->rxd_ring_size = (u32)val;
3056 /* FIXME */
3057 /* ((u16)val)&~1; */ /* even number */
3058#ifdef module_param_array
3059 } else
3060 adapter->rxd_ring_size = (u32)opt.def;
3061#endif
3062 /* init RXD Flow control value */
3063 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7;
3064 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) >
3065 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) :
3066 (adapter->rxd_ring_size / 12);
3067
3068 /* Interrupt Moderate Timer */
3069 opt.type = range_option;
3070 opt.name = "Interrupt Moderate Timer";
3071 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT);
3072 opt.def = INT_MOD_DEFAULT_CNT;
3073 opt.arg.r.min = INT_MOD_MIN_CNT;
3074 opt.arg.r.max = INT_MOD_MAX_CNT;
3075#ifdef module_param_array
3076 if (num_IntModTimer > bd) {
3077#endif
3078 val = IntModTimer[bd];
3079 atl2_validate_option(&val, &opt);
3080 adapter->imt = (u16) val;
3081#ifdef module_param_array
3082 } else
3083 adapter->imt = (u16)(opt.def);
3084#endif
3085 /* Flash Vendor */
3086 opt.type = range_option;
3087 opt.name = "SPI Flash Vendor";
3088 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT);
3089 opt.def = FLASH_VENDOR_DEFAULT;
3090 opt.arg.r.min = FLASH_VENDOR_MIN;
3091 opt.arg.r.max = FLASH_VENDOR_MAX;
3092#ifdef module_param_array
3093 if (num_FlashVendor > bd) {
3094#endif
3095 val = FlashVendor[bd];
3096 atl2_validate_option(&val, &opt);
3097 adapter->hw.flash_vendor = (u8) val;
3098#ifdef module_param_array
3099 } else
3100 adapter->hw.flash_vendor = (u8)(opt.def);
3101#endif
3102 /* MediaType */
3103 opt.type = range_option;
3104 opt.name = "Speed/Duplex Selection";
3105 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR);
3106 opt.def = MEDIA_TYPE_AUTO_SENSOR;
3107 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR;
3108 opt.arg.r.max = MEDIA_TYPE_10M_HALF;
3109#ifdef module_param_array
3110 if (num_MediaType > bd) {
3111#endif
3112 val = MediaType[bd];
3113 atl2_validate_option(&val, &opt);
3114 adapter->hw.MediaType = (u16) val;
3115#ifdef module_param_array
3116 } else
3117 adapter->hw.MediaType = (u16)(opt.def);
3118#endif
3119}
Linux kernel - Deliverables
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