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netdevice: safe convert to netdev_priv() #part-1
[deliverable/linux.git] / drivers / net / au1000_eth.c
CommitLineData
1da177e4
LT		 1/*
2 *
3 * Alchemy Au1x00 ethernet driver
4 *
89be0501 5 * Copyright 2001-2003, 2006 MontaVista Software Inc.
1da177e4
LT		 6 * Copyright 2002 TimeSys Corp.
7 * Added ethtool/mii-tool support,
8 * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
6aa20a22
JG		 9 * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
10 * or riemer@riemer-nt.de: fixed the link beat detection with
1da177e4 11 * ioctls (SIOCGMIIPHY)
0638dec0
HVR		 12 * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
13 * converted to use linux-2.6.x's PHY framework
14 *
1da177e4
LT		 15 * Author: MontaVista Software, Inc.
16 * ppopov@mvista.com or source@mvista.com
17 *
18 * ########################################################################
19 *
20 * This program is free software; you can distribute it and/or modify it
21 * under the terms of the GNU General Public License (Version 2) as
22 * published by the Free Software Foundation.
23 *
24 * This program is distributed in the hope it will be useful, but WITHOUT
25 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
26 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * for more details.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
32 *
33 * ########################################################################
34 *
6aa20a22 35 *
1da177e4 36 */
d791c2bd 37#include <linux/dma-mapping.h>
1da177e4
LT		 38#include <linux/module.h>
39#include <linux/kernel.h>
1da177e4
LT		 40#include <linux/string.h>
41#include <linux/timer.h>
42#include <linux/errno.h>
43#include <linux/in.h>
44#include <linux/ioport.h>
45#include <linux/bitops.h>
46#include <linux/slab.h>
47#include <linux/interrupt.h>
1da177e4
LT		 48#include <linux/init.h>
49#include <linux/netdevice.h>
50#include <linux/etherdevice.h>
51#include <linux/ethtool.h>
52#include <linux/mii.h>
53#include <linux/skbuff.h>
54#include <linux/delay.h>
8cd35da0 55#include <linux/crc32.h>
0638dec0 56#include <linux/phy.h>
25b31cb1
YY		 57
58#include <asm/cpu.h>
1da177e4
LT		 59#include <asm/mipsregs.h>
60#include <asm/irq.h>
61#include <asm/io.h>
62#include <asm/processor.h>
63
25b31cb1
YY		 64#include <au1000.h>
65#include <prom.h>
66
1da177e4
LT		 67#include "au1000_eth.h"
68
69#ifdef AU1000_ETH_DEBUG
70static int au1000_debug = 5;
71#else
72static int au1000_debug = 3;
73#endif
74
89be0501 75#define DRV_NAME "au1000_eth"
d5b20697 76#define DRV_VERSION "1.6"
1da177e4
LT		 77#define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
78#define DRV_DESC "Au1xxx on-chip Ethernet driver"
79
80MODULE_AUTHOR(DRV_AUTHOR);
81MODULE_DESCRIPTION(DRV_DESC);
82MODULE_LICENSE("GPL");
83
84// prototypes
85static void hard_stop(struct net_device *);
86static void enable_rx_tx(struct net_device *dev);
89be0501 87static struct net_device * au1000_probe(int port_num);
1da177e4
LT		 88static int au1000_init(struct net_device *);
89static int au1000_open(struct net_device *);
90static int au1000_close(struct net_device *);
91static int au1000_tx(struct sk_buff *, struct net_device *);
92static int au1000_rx(struct net_device *);
7d12e780 93static irqreturn_t au1000_interrupt(int, void *);
1da177e4 94static void au1000_tx_timeout(struct net_device *);
1da177e4 95static void set_rx_mode(struct net_device *);
1da177e4 96static int au1000_ioctl(struct net_device *, struct ifreq *, int);
1210dde7
AB		 97static int au1000_mdio_read(struct net_device *, int, int);
98static void au1000_mdio_write(struct net_device *, int, int, u16);
0638dec0
HVR		 99static void au1000_adjust_link(struct net_device *);
100static void enable_mac(struct net_device *, int);
1da177e4 101
1da177e4
LT		 102/*
103 * Theory of operation
104 *
6aa20a22
JG		 105 * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
106 * There are four receive and four transmit descriptors. These
107 * descriptors are not in memory; rather, they are just a set of
1da177e4
LT		 108 * hardware registers.
109 *
110 * Since the Au1000 has a coherent data cache, the receive and
6aa20a22 111 * transmit buffers are allocated from the KSEG0 segment. The
1da177e4
LT		 112 * hardware registers, however, are still mapped at KSEG1 to
113 * make sure there's no out-of-order writes, and that all writes
114 * complete immediately.
115 */
116
117/* These addresses are only used if yamon doesn't tell us what
118 * the mac address is, and the mac address is not passed on the
119 * command line.
120 */
6aa20a22 121static unsigned char au1000_mac_addr[6] __devinitdata = {
1da177e4
LT		 122 0x00, 0x50, 0xc2, 0x0c, 0x30, 0x00
123};
124
1da177e4
LT		 125struct au1000_private *au_macs[NUM_ETH_INTERFACES];
126
0638dec0
HVR		 127/*
128 * board-specific configurations
129 *
130 * PHY detection algorithm
131 *
132 * If AU1XXX_PHY_STATIC_CONFIG is undefined, the PHY setup is
133 * autodetected:
134 *
135 * mii_probe() first searches the current MAC's MII bus for a PHY,
136 * selecting the first (or last, if AU1XXX_PHY_SEARCH_HIGHEST_ADDR is
137 * defined) PHY address not already claimed by another netdev.
138 *
139 * If nothing was found that way when searching for the 2nd ethernet
140 * controller's PHY and AU1XXX_PHY1_SEARCH_ON_MAC0 is defined, then
141 * the first MII bus is searched as well for an unclaimed PHY; this is
142 * needed in case of a dual-PHY accessible only through the MAC0's MII
143 * bus.
144 *
145 * Finally, if no PHY is found, then the corresponding ethernet
146 * controller is not registered to the network subsystem.
1da177e4
LT		 147 */
148
0638dec0
HVR		 149/* autodetection defaults */
150#undef AU1XXX_PHY_SEARCH_HIGHEST_ADDR
151#define AU1XXX_PHY1_SEARCH_ON_MAC0
1da177e4 152
0638dec0
HVR		 153/* static PHY setup
154 *
155 * most boards PHY setup should be detectable properly with the
156 * autodetection algorithm in mii_probe(), but in some cases (e.g. if
157 * you have a switch attached, or want to use the PHY's interrupt
158 * notification capabilities) you can provide a static PHY
159 * configuration here
160 *
161 * IRQs may only be set, if a PHY address was configured
162 * If a PHY address is given, also a bus id is required to be set
163 *
164 * ps: make sure the used irqs are configured properly in the board
165 * specific irq-map
166 */
1da177e4 167
0638dec0
HVR		 168#if defined(CONFIG_MIPS_BOSPORUS)
169/*
170 * Micrel/Kendin 5 port switch attached to MAC0,
171 * MAC0 is associated with PHY address 5 (== WAN port)
172 * MAC1 is not associated with any PHY, since it's connected directly
173 * to the switch.
174 * no interrupts are used
175 */
176# define AU1XXX_PHY_STATIC_CONFIG
1da177e4 177
0638dec0
HVR		 178# define AU1XXX_PHY0_ADDR 5
179# define AU1XXX_PHY0_BUSID 0
180# undef AU1XXX_PHY0_IRQ
1da177e4 181
0638dec0
HVR		 182# undef AU1XXX_PHY1_ADDR
183# undef AU1XXX_PHY1_BUSID
184# undef AU1XXX_PHY1_IRQ
1da177e4
LT		 185#endif
186
0638dec0
HVR		 187#if defined(AU1XXX_PHY0_BUSID) && (AU1XXX_PHY0_BUSID > 0)
188# error MAC0-associated PHY attached 2nd MACs MII bus not supported yet
1da177e4 189#endif
1da177e4 190
0638dec0
HVR		 191/*
192 * MII operations
193 */
1210dde7 194static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
1da177e4 195{
454d7c9b 196 struct au1000_private *aup = netdev_priv(dev);
0638dec0
HVR		 197 volatile u32 *const mii_control_reg = &aup->mac->mii_control;
198 volatile u32 *const mii_data_reg = &aup->mac->mii_data;
1da177e4
LT		 199 u32 timedout = 20;
200 u32 mii_control;
201
1da177e4
LT		 202 while (*mii_control_reg & MAC_MII_BUSY) {
203 mdelay(1);
204 if (--timedout == 0) {
6aa20a22 205 printk(KERN_ERR "%s: read_MII busy timeout!!\n",
1da177e4
LT		 206 dev->name);
207 return -1;
208 }
209 }
210
6aa20a22 211 mii_control = MAC_SET_MII_SELECT_REG(reg) |
0638dec0 212 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
1da177e4
LT		 213
214 *mii_control_reg = mii_control;
215
216 timedout = 20;
217 while (*mii_control_reg & MAC_MII_BUSY) {
218 mdelay(1);
219 if (--timedout == 0) {
6aa20a22 220 printk(KERN_ERR "%s: mdio_read busy timeout!!\n",
1da177e4
LT		 221 dev->name);
222 return -1;
223 }
224 }
225 return (int)*mii_data_reg;
226}
227
1210dde7
AB		 228static void au1000_mdio_write(struct net_device *dev, int phy_addr,
229 int reg, u16 value)
1da177e4 230{
454d7c9b 231 struct au1000_private *aup = netdev_priv(dev);
0638dec0
HVR		 232 volatile u32 *const mii_control_reg = &aup->mac->mii_control;
233 volatile u32 *const mii_data_reg = &aup->mac->mii_data;
1da177e4
LT		 234 u32 timedout = 20;
235 u32 mii_control;
236
1da177e4
LT		 237 while (*mii_control_reg & MAC_MII_BUSY) {
238 mdelay(1);
239 if (--timedout == 0) {
6aa20a22 240 printk(KERN_ERR "%s: mdio_write busy timeout!!\n",
1da177e4
LT		 241 dev->name);
242 return;
243 }
244 }
245
6aa20a22 246 mii_control = MAC_SET_MII_SELECT_REG(reg) |
0638dec0 247 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
1da177e4
LT		 248
249 *mii_data_reg = value;
250 *mii_control_reg = mii_control;
251}
252
1210dde7 253static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
0638dec0
HVR		 254{
255 /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does
256 * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus) */
257 struct net_device *const dev = bus->priv;
258
259 enable_mac(dev, 0); /* make sure the MAC associated with this
260 * mii_bus is enabled */
1210dde7 261 return au1000_mdio_read(dev, phy_addr, regnum);
0638dec0 262}
1da177e4 263
1210dde7
AB		 264static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
265 u16 value)
1da177e4 266{
0638dec0 267 struct net_device *const dev = bus->priv;
1da177e4 268
0638dec0
HVR		 269 enable_mac(dev, 0); /* make sure the MAC associated with this
270 * mii_bus is enabled */
1210dde7 271 au1000_mdio_write(dev, phy_addr, regnum, value);
0638dec0 272 return 0;
1da177e4
LT		 273}
274
1210dde7 275static int au1000_mdiobus_reset(struct mii_bus *bus)
1da177e4 276{
0638dec0 277 struct net_device *const dev = bus->priv;
1da177e4 278
0638dec0
HVR		 279 enable_mac(dev, 0); /* make sure the MAC associated with this
280 * mii_bus is enabled */
281 return 0;
282}
1da177e4 283
0638dec0
HVR		 284static int mii_probe (struct net_device *dev)
285{
454d7c9b 286 struct au1000_private *const aup = netdev_priv(dev);
0638dec0
HVR		 287 struct phy_device *phydev = NULL;
288
289#if defined(AU1XXX_PHY_STATIC_CONFIG)
290 BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
291
292 if(aup->mac_id == 0) { /* get PHY0 */
293# if defined(AU1XXX_PHY0_ADDR)
298cf9be 294 phydev = au_macs[AU1XXX_PHY0_BUSID]->mii_bus->phy_map[AU1XXX_PHY0_ADDR];
0638dec0
HVR		 295# else
296 printk (KERN_INFO DRV_NAME ":%s: using PHY-less setup\n",
297 dev->name);
298 return 0;
299# endif /* defined(AU1XXX_PHY0_ADDR) */
300 } else if (aup->mac_id == 1) { /* get PHY1 */
301# if defined(AU1XXX_PHY1_ADDR)
298cf9be 302 phydev = au_macs[AU1XXX_PHY1_BUSID]->mii_bus->phy_map[AU1XXX_PHY1_ADDR];
0638dec0
HVR		 303# else
304 printk (KERN_INFO DRV_NAME ":%s: using PHY-less setup\n",
305 dev->name);
306 return 0;
307# endif /* defined(AU1XXX_PHY1_ADDR) */
308 }
309
310#else /* defined(AU1XXX_PHY_STATIC_CONFIG) */
311 int phy_addr;
312
313 /* find the first (lowest address) PHY on the current MAC's MII bus */
314 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
298cf9be
LB		 315 if (aup->mii_bus->phy_map[phy_addr]) {
316 phydev = aup->mii_bus->phy_map[phy_addr];
0638dec0
HVR		 317# if !defined(AU1XXX_PHY_SEARCH_HIGHEST_ADDR)
318 break; /* break out with first one found */
319# endif
1da177e4 320 }
1da177e4 321
0638dec0
HVR		 322# if defined(AU1XXX_PHY1_SEARCH_ON_MAC0)
323 /* try harder to find a PHY */
324 if (!phydev && (aup->mac_id == 1)) {
325 /* no PHY found, maybe we have a dual PHY? */
326 printk (KERN_INFO DRV_NAME ": no PHY found on MAC1, "
327 "let's see if it's attached to MAC0...\n");
328
329 BUG_ON(!au_macs[0]);
330
331 /* find the first (lowest address) non-attached PHY on
332 * the MAC0 MII bus */
333 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
334 struct phy_device *const tmp_phydev =
298cf9be 335 au_macs[0]->mii_bus->phy_map[phy_addr];
0638dec0
HVR		 336
337 if (!tmp_phydev)
338 continue; /* no PHY here... */
339
340 if (tmp_phydev->attached_dev)
341 continue; /* already claimed by MAC0 */
342
343 phydev = tmp_phydev;
344 break; /* found it */
1da177e4
LT		 345 }
346 }
0638dec0 347# endif /* defined(AU1XXX_PHY1_SEARCH_OTHER_BUS) */
1da177e4 348
0638dec0
HVR		 349#endif /* defined(AU1XXX_PHY_STATIC_CONFIG) */
350 if (!phydev) {
351 printk (KERN_ERR DRV_NAME ":%s: no PHY found\n", dev->name);
1da177e4
LT		 352 return -1;
353 }
354
0638dec0
HVR		 355 /* now we are supposed to have a proper phydev, to attach to... */
356 BUG_ON(!phydev);
357 BUG_ON(phydev->attached_dev);
358
e8a2b6a4
AF		 359 phydev = phy_connect(dev, phydev->dev.bus_id, &au1000_adjust_link, 0,
360 PHY_INTERFACE_MODE_MII);
0638dec0
HVR		 361
362 if (IS_ERR(phydev)) {
363 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
364 return PTR_ERR(phydev);
365 }
366
367 /* mask with MAC supported features */
368 phydev->supported &= (SUPPORTED_10baseT_Half
369 | SUPPORTED_10baseT_Full
370 | SUPPORTED_100baseT_Half
371 | SUPPORTED_100baseT_Full
372 | SUPPORTED_Autoneg
373 /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
374 | SUPPORTED_MII
375 | SUPPORTED_TP);
376
377 phydev->advertising = phydev->supported;
378
379 aup->old_link = 0;
380 aup->old_speed = 0;
381 aup->old_duplex = -1;
382 aup->phy_dev = phydev;
383
384 printk(KERN_INFO "%s: attached PHY driver [%s] "
385 "(mii_bus:phy_addr=%s, irq=%d)\n",
386 dev->name, phydev->drv->name, phydev->dev.bus_id, phydev->irq);
1da177e4
LT		 387
388 return 0;
389}
390
391
392/*
393 * Buffer allocation/deallocation routines. The buffer descriptor returned
6aa20a22 394 * has the virtual and dma address of a buffer suitable for
1da177e4
LT		 395 * both, receive and transmit operations.
396 */
397static db_dest_t *GetFreeDB(struct au1000_private *aup)
398{
399 db_dest_t *pDB;
400 pDB = aup->pDBfree;
401
402 if (pDB) {
403 aup->pDBfree = pDB->pnext;
404 }
405 return pDB;
406}
407
408void ReleaseDB(struct au1000_private *aup, db_dest_t *pDB)
409{
410 db_dest_t *pDBfree = aup->pDBfree;
411 if (pDBfree)
412 pDBfree->pnext = pDB;
413 aup->pDBfree = pDB;
414}
415
416static void enable_rx_tx(struct net_device *dev)
417{
454d7c9b 418 struct au1000_private *aup = netdev_priv(dev);
1da177e4
LT		 419
420 if (au1000_debug > 4)
421 printk(KERN_INFO "%s: enable_rx_tx\n", dev->name);
422
423 aup->mac->control |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
424 au_sync_delay(10);
425}
426
427static void hard_stop(struct net_device *dev)
428{
454d7c9b 429 struct au1000_private *aup = netdev_priv(dev);
1da177e4
LT		 430
431 if (au1000_debug > 4)
432 printk(KERN_INFO "%s: hard stop\n", dev->name);
433
434 aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
435 au_sync_delay(10);
436}
437
0638dec0 438static void enable_mac(struct net_device *dev, int force_reset)
1da177e4 439{
0638dec0 440 unsigned long flags;
454d7c9b 441 struct au1000_private *aup = netdev_priv(dev);
1da177e4 442
1da177e4 443 spin_lock_irqsave(&aup->lock, flags);
1da177e4 444
0638dec0 445 if(force_reset || (!aup->mac_enabled)) {
1da177e4
LT		 446 *aup->enable = MAC_EN_CLOCK_ENABLE;
447 au_sync_delay(2);
0638dec0
HVR		 448 *aup->enable = (MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
449 | MAC_EN_CLOCK_ENABLE);
1da177e4 450 au_sync_delay(2);
0638dec0
HVR		 451
452 aup->mac_enabled = 1;
1da177e4 453 }
0638dec0
HVR		 454
455 spin_unlock_irqrestore(&aup->lock, flags);
456}
457
458static void reset_mac_unlocked(struct net_device *dev)
459{
454d7c9b 460 struct au1000_private *const aup = netdev_priv(dev);
0638dec0
HVR		 461 int i;
462
463 hard_stop(dev);
464
465 *aup->enable = MAC_EN_CLOCK_ENABLE;
466 au_sync_delay(2);
467 *aup->enable = 0;
468 au_sync_delay(2);
469
1da177e4
LT		 470 aup->tx_full = 0;
471 for (i = 0; i < NUM_RX_DMA; i++) {
472 /* reset control bits */
473 aup->rx_dma_ring[i]->buff_stat &= ~0xf;
474 }
475 for (i = 0; i < NUM_TX_DMA; i++) {
476 /* reset control bits */
477 aup->tx_dma_ring[i]->buff_stat &= ~0xf;
478 }
0638dec0
HVR		 479
480 aup->mac_enabled = 0;
481
1da177e4
LT		 482}
483
0638dec0
HVR		 484static void reset_mac(struct net_device *dev)
485{
454d7c9b 486 struct au1000_private *const aup = netdev_priv(dev);
0638dec0
HVR		 487 unsigned long flags;
488
489 if (au1000_debug > 4)
490 printk(KERN_INFO "%s: reset mac, aup %x\n",
491 dev->name, (unsigned)aup);
492
493 spin_lock_irqsave(&aup->lock, flags);
494
495 reset_mac_unlocked (dev);
496
497 spin_unlock_irqrestore(&aup->lock, flags);
498}
1da177e4 499
6aa20a22 500/*
1da177e4
LT		 501 * Setup the receive and transmit "rings". These pointers are the addresses
502 * of the rx and tx MAC DMA registers so they are fixed by the hardware --
503 * these are not descriptors sitting in memory.
504 */
6aa20a22 505static void
1da177e4
LT		 506setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base)
507{
508 int i;
509
510 for (i = 0; i < NUM_RX_DMA; i++) {
6aa20a22 511 aup->rx_dma_ring[i] =
1da177e4
LT		 512 (volatile rx_dma_t *) (rx_base + sizeof(rx_dma_t)*i);
513 }
514 for (i = 0; i < NUM_TX_DMA; i++) {
6aa20a22 515 aup->tx_dma_ring[i] =
1da177e4
LT		 516 (volatile tx_dma_t *) (tx_base + sizeof(tx_dma_t)*i);
517 }
518}
519
520static struct {
1da177e4
LT		 521 u32 base_addr;
522 u32 macen_addr;
523 int irq;
524 struct net_device *dev;
89be0501
SS		 525} iflist[2] = {
526#ifdef CONFIG_SOC_AU1000
527 {AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT},
528 {AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT}
529#endif
530#ifdef CONFIG_SOC_AU1100
531 {AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT}
532#endif
533#ifdef CONFIG_SOC_AU1500
534 {AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT},
535 {AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT}
536#endif
537#ifdef CONFIG_SOC_AU1550
538 {AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT},
539 {AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT}
540#endif
541};
1da177e4
LT		 542
543static int num_ifs;
544
545/*
3a4fa0a2 546 * Setup the base address and interrupt of the Au1xxx ethernet macs
1da177e4
LT		 547 * based on cpu type and whether the interface is enabled in sys_pinfunc
548 * register. The last interface is enabled if SYS_PF_NI2 (bit 4) is 0.
549 */
550static int __init au1000_init_module(void)
551{
1da177e4
LT		 552 int ni = (int)((au_readl(SYS_PINFUNC) & (u32)(SYS_PF_NI2)) >> 4);
553 struct net_device *dev;
554 int i, found_one = 0;
555
89be0501
SS		 556 num_ifs = NUM_ETH_INTERFACES - ni;
557
1da177e4 558 for(i = 0; i < num_ifs; i++) {
89be0501 559 dev = au1000_probe(i);
1da177e4
LT		 560 iflist[i].dev = dev;
561 if (dev)
562 found_one++;
563 }
564 if (!found_one)
565 return -ENODEV;
566 return 0;
567}
568
0638dec0
HVR		 569/*
570 * ethtool operations
571 */
1da177e4 572
0638dec0 573static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 574{
454d7c9b 575 struct au1000_private *aup = netdev_priv(dev);
1da177e4 576
0638dec0
HVR		 577 if (aup->phy_dev)
578 return phy_ethtool_gset(aup->phy_dev, cmd);
1da177e4 579
0638dec0 580 return -EINVAL;
1da177e4
LT		 581}
582
0638dec0 583static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 584{
454d7c9b 585 struct au1000_private *aup = netdev_priv(dev);
1da177e4 586
0638dec0
HVR		 587 if (!capable(CAP_NET_ADMIN))
588 return -EPERM;
1da177e4 589
0638dec0
HVR		 590 if (aup->phy_dev)
591 return phy_ethtool_sset(aup->phy_dev, cmd);
1da177e4 592
0638dec0 593 return -EINVAL;
1da177e4
LT		 594}
595
596static void
597au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
598{
454d7c9b 599 struct au1000_private *aup = netdev_priv(dev);
1da177e4
LT		 600
601 strcpy(info->driver, DRV_NAME);
602 strcpy(info->version, DRV_VERSION);
603 info->fw_version[0] = '\0';
604 sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id);
605 info->regdump_len = 0;
606}
607
7282d491 608static const struct ethtool_ops au1000_ethtool_ops = {
1da177e4
LT		 609 .get_settings = au1000_get_settings,
610 .set_settings = au1000_set_settings,
611 .get_drvinfo = au1000_get_drvinfo,
0638dec0 612 .get_link = ethtool_op_get_link,
1da177e4
LT		 613};
614
89be0501 615static struct net_device * au1000_probe(int port_num)
1da177e4
LT		 616{
617 static unsigned version_printed = 0;
618 struct au1000_private *aup = NULL;
619 struct net_device *dev = NULL;
620 db_dest_t *pDB, *pDBfree;
1da177e4 621 char ethaddr[6];
89be0501
SS		 622 int irq, i, err;
623 u32 base, macen;
624
625 if (port_num >= NUM_ETH_INTERFACES)
626 return NULL;
1da177e4 627
89be0501
SS		 628 base = CPHYSADDR(iflist[port_num].base_addr );
629 macen = CPHYSADDR(iflist[port_num].macen_addr);
630 irq = iflist[port_num].irq;
631
632 if (!request_mem_region( base, MAC_IOSIZE, "Au1x00 ENET") ||
633 !request_mem_region(macen, 4, "Au1x00 ENET"))
1da177e4
LT		 634 return NULL;
635
89be0501 636 if (version_printed++ == 0)
1da177e4
LT		 637 printk("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR);
638
639 dev = alloc_etherdev(sizeof(struct au1000_private));
640 if (!dev) {
89be0501 641 printk(KERN_ERR "%s: alloc_etherdev failed\n", DRV_NAME);
1da177e4
LT		 642 return NULL;
643 }
644
89be0501
SS		 645 if ((err = register_netdev(dev)) != 0) {
646 printk(KERN_ERR "%s: Cannot register net device, error %d\n",
647 DRV_NAME, err);
1da177e4
LT		 648 free_netdev(dev);
649 return NULL;
650 }
651
89be0501
SS		 652 printk("%s: Au1xx0 Ethernet found at 0x%x, irq %d\n",
653 dev->name, base, irq);
1da177e4 654
454d7c9b 655 aup = netdev_priv(dev);
1da177e4 656
533763d3
MG		 657 spin_lock_init(&aup->lock);
658
1da177e4
LT		 659 /* Allocate the data buffers */
660 /* Snooping works fine with eth on all au1xxx */
89be0501
SS		 661 aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
662 (NUM_TX_BUFFS + NUM_RX_BUFFS),
663 &aup->dma_addr, 0);
1da177e4
LT		 664 if (!aup->vaddr) {
665 free_netdev(dev);
89be0501
SS		 666 release_mem_region( base, MAC_IOSIZE);
667 release_mem_region(macen, 4);
1da177e4
LT		 668 return NULL;
669 }
670
671 /* aup->mac is the base address of the MAC's registers */
89be0501
SS		 672 aup->mac = (volatile mac_reg_t *)iflist[port_num].base_addr;
673
1da177e4 674 /* Setup some variables for quick register address access */
89be0501
SS		 675 aup->enable = (volatile u32 *)iflist[port_num].macen_addr;
676 aup->mac_id = port_num;
677 au_macs[port_num] = aup;
678
679 if (port_num == 0) {
2de88923 680 if (prom_get_ethernet_addr(ethaddr) == 0)
1da177e4 681 memcpy(au1000_mac_addr, ethaddr, sizeof(au1000_mac_addr));
89be0501 682 else {
2de88923
YY		 683 printk(KERN_INFO "%s: No MAC address found\n",
684 dev->name);
89be0501 685 /* Use the hard coded MAC addresses */
1da177e4 686 }
89be0501 687
1da177e4 688 setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
89be0501 689 } else if (port_num == 1)
1da177e4 690 setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
1da177e4 691
89be0501
SS		 692 /*
693 * Assign to the Ethernet ports two consecutive MAC addresses
694 * to match those that are printed on their stickers
695 */
696 memcpy(dev->dev_addr, au1000_mac_addr, sizeof(au1000_mac_addr));
697 dev->dev_addr[5] += port_num;
698
0638dec0
HVR		 699 *aup->enable = 0;
700 aup->mac_enabled = 0;
701
298cf9be
LB		 702 aup->mii_bus = mdiobus_alloc();
703 if (aup->mii_bus == NULL)
704 goto err_out;
705
706 aup->mii_bus->priv = dev;
1210dde7
AB		 707 aup->mii_bus->read = au1000_mdiobus_read;
708 aup->mii_bus->write = au1000_mdiobus_write;
709 aup->mii_bus->reset = au1000_mdiobus_reset;
298cf9be
LB		 710 aup->mii_bus->name = "au1000_eth_mii";
711 snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%x", aup->mac_id);
712 aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
0638dec0 713 for(i = 0; i < PHY_MAX_ADDR; ++i)
298cf9be 714 aup->mii_bus->irq[i] = PHY_POLL;
0638dec0
HVR		 715
716 /* if known, set corresponding PHY IRQs */
717#if defined(AU1XXX_PHY_STATIC_CONFIG)
718# if defined(AU1XXX_PHY0_IRQ)
9d9326d3 719 if (AU1XXX_PHY0_BUSID == aup->mac_id)
298cf9be 720 aup->mii_bus->irq[AU1XXX_PHY0_ADDR] = AU1XXX_PHY0_IRQ;
0638dec0
HVR		 721# endif
722# if defined(AU1XXX_PHY1_IRQ)
9d9326d3 723 if (AU1XXX_PHY1_BUSID == aup->mac_id)
298cf9be 724 aup->mii_bus->irq[AU1XXX_PHY1_ADDR] = AU1XXX_PHY1_IRQ;
0638dec0
HVR		 725# endif
726#endif
298cf9be 727 mdiobus_register(aup->mii_bus);
1da177e4
LT		 728
729 if (mii_probe(dev) != 0) {
730 goto err_out;
731 }
732
733 pDBfree = NULL;
734 /* setup the data buffer descriptors and attach a buffer to each one */
735 pDB = aup->db;
736 for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
737 pDB->pnext = pDBfree;
738 pDBfree = pDB;
739 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
740 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
741 pDB++;
742 }
743 aup->pDBfree = pDBfree;
744
745 for (i = 0; i < NUM_RX_DMA; i++) {
746 pDB = GetFreeDB(aup);
747 if (!pDB) {
748 goto err_out;
749 }
750 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
751 aup->rx_db_inuse[i] = pDB;
752 }
753 for (i = 0; i < NUM_TX_DMA; i++) {
754 pDB = GetFreeDB(aup);
755 if (!pDB) {
756 goto err_out;
757 }
758 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
759 aup->tx_dma_ring[i]->len = 0;
760 aup->tx_db_inuse[i] = pDB;
761 }
762
89be0501 763 dev->base_addr = base;
1da177e4
LT		 764 dev->irq = irq;
765 dev->open = au1000_open;
766 dev->hard_start_xmit = au1000_tx;
767 dev->stop = au1000_close;
1da177e4
LT		 768 dev->set_multicast_list = &set_rx_mode;
769 dev->do_ioctl = &au1000_ioctl;
770 SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
1da177e4
LT		 771 dev->tx_timeout = au1000_tx_timeout;
772 dev->watchdog_timeo = ETH_TX_TIMEOUT;
773
6aa20a22
JG		 774 /*
775 * The boot code uses the ethernet controller, so reset it to start
1da177e4
LT		 776 * fresh. au1000_init() expects that the device is in reset state.
777 */
778 reset_mac(dev);
779
780 return dev;
781
782err_out:
298cf9be
LB		 783 if (aup->mii_bus != NULL) {
784 mdiobus_unregister(aup->mii_bus);
785 mdiobus_free(aup->mii_bus);
786 }
787
1da177e4
LT		 788 /* here we should have a valid dev plus aup-> register addresses
789 * so we can reset the mac properly.*/
790 reset_mac(dev);
0638dec0 791
1da177e4
LT		 792 for (i = 0; i < NUM_RX_DMA; i++) {
793 if (aup->rx_db_inuse[i])
794 ReleaseDB(aup, aup->rx_db_inuse[i]);
795 }
796 for (i = 0; i < NUM_TX_DMA; i++) {
797 if (aup->tx_db_inuse[i])
798 ReleaseDB(aup, aup->tx_db_inuse[i]);
799 }
89be0501
SS		 800 dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
801 (void *)aup->vaddr, aup->dma_addr);
1da177e4
LT		 802 unregister_netdev(dev);
803 free_netdev(dev);
89be0501
SS		 804 release_mem_region( base, MAC_IOSIZE);
805 release_mem_region(macen, 4);
1da177e4
LT		 806 return NULL;
807}
808
6aa20a22 809/*
1da177e4
LT		 810 * Initialize the interface.
811 *
812 * When the device powers up, the clocks are disabled and the
813 * mac is in reset state. When the interface is closed, we
814 * do the same -- reset the device and disable the clocks to
815 * conserve power. Thus, whenever au1000_init() is called,
816 * the device should already be in reset state.
817 */
818static int au1000_init(struct net_device *dev)
819{
454d7c9b 820 struct au1000_private *aup = netdev_priv(dev);
2726fcf0 821 unsigned long flags;
1da177e4
LT		 822 int i;
823 u32 control;
1da177e4 824
6aa20a22 825 if (au1000_debug > 4)
1da177e4
LT		 826 printk("%s: au1000_init\n", dev->name);
827
1da177e4 828 /* bring the device out of reset */
0638dec0
HVR		 829 enable_mac(dev, 1);
830
831 spin_lock_irqsave(&aup->lock, flags);
1da177e4
LT		 832
833 aup->mac->control = 0;
834 aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
835 aup->tx_tail = aup->tx_head;
836 aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
837
838 aup->mac->mac_addr_high = dev->dev_addr[5]<<8 | dev->dev_addr[4];
839 aup->mac->mac_addr_low = dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
840 dev->dev_addr[1]<<8 | dev->dev_addr[0];
841
842 for (i = 0; i < NUM_RX_DMA; i++) {
843 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
844 }
845 au_sync();
846
0638dec0 847 control = MAC_RX_ENABLE | MAC_TX_ENABLE;
1da177e4
LT		 848#ifndef CONFIG_CPU_LITTLE_ENDIAN
849 control |= MAC_BIG_ENDIAN;
850#endif
0638dec0
HVR		 851 if (aup->phy_dev) {
852 if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
853 control |= MAC_FULL_DUPLEX;
854 else
855 control |= MAC_DISABLE_RX_OWN;
856 } else { /* PHY-less op, assume full-duplex */
1da177e4
LT		 857 control |= MAC_FULL_DUPLEX;
858 }
859
1da177e4
LT		 860 aup->mac->control = control;
861 aup->mac->vlan1_tag = 0x8100; /* activate vlan support */
862 au_sync();
863
864 spin_unlock_irqrestore(&aup->lock, flags);
865 return 0;
866}
867
0638dec0
HVR		 868static void
869au1000_adjust_link(struct net_device *dev)
1da177e4 870{
454d7c9b 871 struct au1000_private *aup = netdev_priv(dev);
0638dec0
HVR		 872 struct phy_device *phydev = aup->phy_dev;
873 unsigned long flags;
1da177e4 874
0638dec0 875 int status_change = 0;
1da177e4 876
0638dec0
HVR		 877 BUG_ON(!aup->phy_dev);
878
879 spin_lock_irqsave(&aup->lock, flags);
880
881 if (phydev->link && (aup->old_speed != phydev->speed)) {
882 // speed changed
883
884 switch(phydev->speed) {
885 case SPEED_10:
886 case SPEED_100:
887 break;
888 default:
889 printk(KERN_WARNING
890 "%s: Speed (%d) is not 10/100 ???\n",
891 dev->name, phydev->speed);
892 break;
1da177e4 893 }
0638dec0
HVR		 894
895 aup->old_speed = phydev->speed;
896
897 status_change = 1;
1da177e4
LT		 898 }
899
0638dec0
HVR		 900 if (phydev->link && (aup->old_duplex != phydev->duplex)) {
901 // duplex mode changed
902
903 /* switching duplex mode requires to disable rx and tx! */
1da177e4 904 hard_stop(dev);
0638dec0
HVR		 905
906 if (DUPLEX_FULL == phydev->duplex)
907 aup->mac->control = ((aup->mac->control
908 | MAC_FULL_DUPLEX)
909 & ~MAC_DISABLE_RX_OWN);
910 else
911 aup->mac->control = ((aup->mac->control
912 & ~MAC_FULL_DUPLEX)
913 | MAC_DISABLE_RX_OWN);
914 au_sync_delay(1);
915
1da177e4 916 enable_rx_tx(dev);
0638dec0
HVR		 917 aup->old_duplex = phydev->duplex;
918
919 status_change = 1;
920 }
921
922 if(phydev->link != aup->old_link) {
923 // link state changed
924
c8f15686
AV		 925 if (!phydev->link) {
926 /* link went down */
0638dec0
HVR		 927 aup->old_speed = 0;
928 aup->old_duplex = -1;
929 }
930
931 aup->old_link = phydev->link;
932 status_change = 1;
1da177e4
LT		 933 }
934
0638dec0 935 spin_unlock_irqrestore(&aup->lock, flags);
1da177e4 936
0638dec0
HVR		 937 if (status_change) {
938 if (phydev->link)
939 printk(KERN_INFO "%s: link up (%d/%s)\n",
940 dev->name, phydev->speed,
941 DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
942 else
943 printk(KERN_INFO "%s: link down\n", dev->name);
944 }
1da177e4
LT		 945}
946
947static int au1000_open(struct net_device *dev)
948{
949 int retval;
454d7c9b 950 struct au1000_private *aup = netdev_priv(dev);
1da177e4
LT		 951
952 if (au1000_debug > 4)
953 printk("%s: open: dev=%p\n", dev->name, dev);
954
0638dec0
HVR		 955 if ((retval = request_irq(dev->irq, &au1000_interrupt, 0,
956 dev->name, dev))) {
957 printk(KERN_ERR "%s: unable to get IRQ %d\n",
958 dev->name, dev->irq);
959 return retval;
960 }
961
1da177e4
LT		 962 if ((retval = au1000_init(dev))) {
963 printk(KERN_ERR "%s: error in au1000_init\n", dev->name);
964 free_irq(dev->irq, dev);
965 return retval;
966 }
1da177e4 967
0638dec0
HVR		 968 if (aup->phy_dev) {
969 /* cause the PHY state machine to schedule a link state check */
970 aup->phy_dev->state = PHY_CHANGELINK;
971 phy_start(aup->phy_dev);
1da177e4
LT		 972 }
973
0638dec0 974 netif_start_queue(dev);
1da177e4
LT		 975
976 if (au1000_debug > 4)
977 printk("%s: open: Initialization done.\n", dev->name);
978
979 return 0;
980}
981
982static int au1000_close(struct net_device *dev)
983{
0638dec0 984 unsigned long flags;
454d7c9b 985 struct au1000_private *const aup = netdev_priv(dev);
1da177e4
LT		 986
987 if (au1000_debug > 4)
988 printk("%s: close: dev=%p\n", dev->name, dev);
989
0638dec0
HVR		 990 if (aup->phy_dev)
991 phy_stop(aup->phy_dev);
1da177e4
LT		 992
993 spin_lock_irqsave(&aup->lock, flags);
0638dec0
HVR		 994
995 reset_mac_unlocked (dev);
996
1da177e4
LT		 997 /* stop the device */
998 netif_stop_queue(dev);
999
1000 /* disable the interrupt */
1001 free_irq(dev->irq, dev);
1002 spin_unlock_irqrestore(&aup->lock, flags);
1003
1004 return 0;
1005}
1006
1007static void __exit au1000_cleanup_module(void)
1008{
1009 int i, j;
1010 struct net_device *dev;
1011 struct au1000_private *aup;
1012
1013 for (i = 0; i < num_ifs; i++) {
1014 dev = iflist[i].dev;
1015 if (dev) {
454d7c9b 1016 aup = netdev_priv(dev);
1da177e4 1017 unregister_netdev(dev);
298cf9be
LB		 1018 mdiobus_unregister(aup->mii_bus);
1019 mdiobus_free(aup->mii_bus);
89be0501 1020 for (j = 0; j < NUM_RX_DMA; j++)
1da177e4
LT		 1021 if (aup->rx_db_inuse[j])
1022 ReleaseDB(aup, aup->rx_db_inuse[j]);
89be0501 1023 for (j = 0; j < NUM_TX_DMA; j++)
1da177e4
LT		 1024 if (aup->tx_db_inuse[j])
1025 ReleaseDB(aup, aup->tx_db_inuse[j]);
89be0501
SS		 1026 dma_free_noncoherent(NULL, MAX_BUF_SIZE *
1027 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1028 (void *)aup->vaddr, aup->dma_addr);
1029 release_mem_region(dev->base_addr, MAC_IOSIZE);
1030 release_mem_region(CPHYSADDR(iflist[i].macen_addr), 4);
1da177e4 1031 free_netdev(dev);
1da177e4
LT		 1032 }
1033 }
1034}
1035
c2d3d4b9 1036static void update_tx_stats(struct net_device *dev, u32 status)
1da177e4 1037{
454d7c9b 1038 struct au1000_private *aup = netdev_priv(dev);
09f75cd7 1039 struct net_device_stats *ps = &dev->stats;
1da177e4 1040
1da177e4 1041 if (status & TX_FRAME_ABORTED) {
0638dec0 1042 if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
1da177e4
LT		 1043 if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
1044 /* any other tx errors are only valid
1045 * in half duplex mode */
1046 ps->tx_errors++;
1047 ps->tx_aborted_errors++;
1048 }
1049 }
1050 else {
1051 ps->tx_errors++;
1052 ps->tx_aborted_errors++;
1053 if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
1054 ps->tx_carrier_errors++;
1055 }
1056 }
1057}
1058
1059
1060/*
1061 * Called from the interrupt service routine to acknowledge
1062 * the TX DONE bits. This is a must if the irq is setup as
1063 * edge triggered.
1064 */
1065static void au1000_tx_ack(struct net_device *dev)
1066{
454d7c9b 1067 struct au1000_private *aup = netdev_priv(dev);
1da177e4
LT		 1068 volatile tx_dma_t *ptxd;
1069
1070 ptxd = aup->tx_dma_ring[aup->tx_tail];
1071
1072 while (ptxd->buff_stat & TX_T_DONE) {
c2d3d4b9 1073 update_tx_stats(dev, ptxd->status);
1da177e4
LT		 1074 ptxd->buff_stat &= ~TX_T_DONE;
1075 ptxd->len = 0;
1076 au_sync();
1077
1078 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
1079 ptxd = aup->tx_dma_ring[aup->tx_tail];
1080
1081 if (aup->tx_full) {
1082 aup->tx_full = 0;
1083 netif_wake_queue(dev);
1084 }
1085 }
1086}
1087
1088
1089/*
1090 * Au1000 transmit routine.
1091 */
1092static int au1000_tx(struct sk_buff *skb, struct net_device *dev)
1093{
454d7c9b 1094 struct au1000_private *aup = netdev_priv(dev);
09f75cd7 1095 struct net_device_stats *ps = &dev->stats;
1da177e4
LT		 1096 volatile tx_dma_t *ptxd;
1097 u32 buff_stat;
1098 db_dest_t *pDB;
1099 int i;
1100
1101 if (au1000_debug > 5)
6aa20a22
JG		 1102 printk("%s: tx: aup %x len=%d, data=%p, head %d\n",
1103 dev->name, (unsigned)aup, skb->len,
1da177e4
LT		 1104 skb->data, aup->tx_head);
1105
1106 ptxd = aup->tx_dma_ring[aup->tx_head];
1107 buff_stat = ptxd->buff_stat;
1108 if (buff_stat & TX_DMA_ENABLE) {
1109 /* We've wrapped around and the transmitter is still busy */
1110 netif_stop_queue(dev);
1111 aup->tx_full = 1;
1112 return 1;
1113 }
1114 else if (buff_stat & TX_T_DONE) {
c2d3d4b9 1115 update_tx_stats(dev, ptxd->status);
1da177e4
LT		 1116 ptxd->len = 0;
1117 }
1118
1119 if (aup->tx_full) {
1120 aup->tx_full = 0;
1121 netif_wake_queue(dev);
1122 }
1123
1124 pDB = aup->tx_db_inuse[aup->tx_head];
d626f62b 1125 skb_copy_from_linear_data(skb, pDB->vaddr, skb->len);
1da177e4 1126 if (skb->len < ETH_ZLEN) {
6aa20a22 1127 for (i=skb->len; i<ETH_ZLEN; i++) {
1da177e4
LT		 1128 ((char *)pDB->vaddr)[i] = 0;
1129 }
1130 ptxd->len = ETH_ZLEN;
1131 }
1132 else
1133 ptxd->len = skb->len;
1134
c2d3d4b9
SS		 1135 ps->tx_packets++;
1136 ps->tx_bytes += ptxd->len;
1137
1da177e4
LT		 1138 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
1139 au_sync();
1140 dev_kfree_skb(skb);
1141 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
1142 dev->trans_start = jiffies;
1143 return 0;
1144}
1145
1da177e4
LT		 1146static inline void update_rx_stats(struct net_device *dev, u32 status)
1147{
454d7c9b 1148 struct au1000_private *aup = netdev_priv(dev);
09f75cd7 1149 struct net_device_stats *ps = &dev->stats;
1da177e4
LT		 1150
1151 ps->rx_packets++;
1152 if (status & RX_MCAST_FRAME)
1153 ps->multicast++;
1154
1155 if (status & RX_ERROR) {
1156 ps->rx_errors++;
1157 if (status & RX_MISSED_FRAME)
1158 ps->rx_missed_errors++;
1159 if (status & (RX_OVERLEN | RX_OVERLEN | RX_LEN_ERROR))
1160 ps->rx_length_errors++;
1161 if (status & RX_CRC_ERROR)
1162 ps->rx_crc_errors++;
1163 if (status & RX_COLL)
1164 ps->collisions++;
1165 }
6aa20a22 1166 else
1da177e4
LT		 1167 ps->rx_bytes += status & RX_FRAME_LEN_MASK;
1168
1169}
1170
1171/*
1172 * Au1000 receive routine.
1173 */
1174static int au1000_rx(struct net_device *dev)
1175{
454d7c9b 1176 struct au1000_private *aup = netdev_priv(dev);
1da177e4
LT		 1177 struct sk_buff *skb;
1178 volatile rx_dma_t *prxd;
1179 u32 buff_stat, status;
1180 db_dest_t *pDB;
1181 u32 frmlen;
1182
1183 if (au1000_debug > 5)
1184 printk("%s: au1000_rx head %d\n", dev->name, aup->rx_head);
1185
1186 prxd = aup->rx_dma_ring[aup->rx_head];
1187 buff_stat = prxd->buff_stat;
1188 while (buff_stat & RX_T_DONE) {
1189 status = prxd->status;
1190 pDB = aup->rx_db_inuse[aup->rx_head];
1191 update_rx_stats(dev, status);
1192 if (!(status & RX_ERROR)) {
1193
1194 /* good frame */
1195 frmlen = (status & RX_FRAME_LEN_MASK);
1196 frmlen -= 4; /* Remove FCS */
1197 skb = dev_alloc_skb(frmlen + 2);
1198 if (skb == NULL) {
1199 printk(KERN_ERR
1200 "%s: Memory squeeze, dropping packet.\n",
1201 dev->name);
09f75cd7 1202 dev->stats.rx_dropped++;
1da177e4
LT		 1203 continue;
1204 }
1da177e4 1205 skb_reserve(skb, 2); /* 16 byte IP header align */
8c7b7faa
DM		 1206 skb_copy_to_linear_data(skb,
1207 (unsigned char *)pDB->vaddr, frmlen);
1da177e4
LT		 1208 skb_put(skb, frmlen);
1209 skb->protocol = eth_type_trans(skb, dev);
1210 netif_rx(skb); /* pass the packet to upper layers */
1211 }
1212 else {
1213 if (au1000_debug > 4) {
6aa20a22 1214 if (status & RX_MISSED_FRAME)
1da177e4 1215 printk("rx miss\n");
6aa20a22 1216 if (status & RX_WDOG_TIMER)
1da177e4 1217 printk("rx wdog\n");
6aa20a22 1218 if (status & RX_RUNT)
1da177e4 1219 printk("rx runt\n");
6aa20a22 1220 if (status & RX_OVERLEN)
1da177e4
LT		 1221 printk("rx overlen\n");
1222 if (status & RX_COLL)
1223 printk("rx coll\n");
1224 if (status & RX_MII_ERROR)
1225 printk("rx mii error\n");
1226 if (status & RX_CRC_ERROR)
1227 printk("rx crc error\n");
1228 if (status & RX_LEN_ERROR)
1229 printk("rx len error\n");
1230 if (status & RX_U_CNTRL_FRAME)
1231 printk("rx u control frame\n");
1232 if (status & RX_MISSED_FRAME)
1233 printk("rx miss\n");
1234 }
1235 }
1236 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
1237 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
1238 au_sync();
1239
1240 /* next descriptor */
1241 prxd = aup->rx_dma_ring[aup->rx_head];
1242 buff_stat = prxd->buff_stat;
1da177e4
LT		 1243 }
1244 return 0;
1245}
1246
1247
1248/*
1249 * Au1000 interrupt service routine.
1250 */
7d12e780 1251static irqreturn_t au1000_interrupt(int irq, void *dev_id)
1da177e4 1252{
d04455fb 1253 struct net_device *dev = dev_id;
1da177e4
LT		 1254
1255 /* Handle RX interrupts first to minimize chance of overrun */
1256
1257 au1000_rx(dev);
1258 au1000_tx_ack(dev);
1259 return IRQ_RETVAL(1);
1260}
1261
1262
1263/*
1264 * The Tx ring has been full longer than the watchdog timeout
1265 * value. The transmitter must be hung?
1266 */
1267static void au1000_tx_timeout(struct net_device *dev)
1268{
1269 printk(KERN_ERR "%s: au1000_tx_timeout: dev=%p\n", dev->name, dev);
1270 reset_mac(dev);
1271 au1000_init(dev);
1272 dev->trans_start = jiffies;
1273 netif_wake_queue(dev);
1274}
1275
1da177e4
LT		 1276static void set_rx_mode(struct net_device *dev)
1277{
454d7c9b 1278 struct au1000_private *aup = netdev_priv(dev);
1da177e4 1279
6aa20a22 1280 if (au1000_debug > 4)
1da177e4
LT		 1281 printk("%s: set_rx_mode: flags=%x\n", dev->name, dev->flags);
1282
1283 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1284 aup->mac->control |= MAC_PROMISCUOUS;
1da177e4
LT		 1285 } else if ((dev->flags & IFF_ALLMULTI) ||
1286 dev->mc_count > MULTICAST_FILTER_LIMIT) {
1287 aup->mac->control |= MAC_PASS_ALL_MULTI;
1288 aup->mac->control &= ~MAC_PROMISCUOUS;
1289 printk(KERN_INFO "%s: Pass all multicast\n", dev->name);
1290 } else {
1291 int i;
1292 struct dev_mc_list *mclist;
1293 u32 mc_filter[2]; /* Multicast hash filter */
1294
1295 mc_filter[1] = mc_filter[0] = 0;
1296 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1297 i++, mclist = mclist->next) {
6aa20a22 1298 set_bit(ether_crc(ETH_ALEN, mclist->dmi_addr)>>26,
1da177e4
LT		 1299 (long *)mc_filter);
1300 }
1301 aup->mac->multi_hash_high = mc_filter[1];
1302 aup->mac->multi_hash_low = mc_filter[0];
1303 aup->mac->control &= ~MAC_PROMISCUOUS;
1304 aup->mac->control |= MAC_HASH_MODE;
1305 }
1306}
1307
1da177e4
LT		 1308static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1309{
454d7c9b 1310 struct au1000_private *aup = netdev_priv(dev);
1da177e4 1311
0638dec0 1312 if (!netif_running(dev)) return -EINVAL;
1da177e4 1313
0638dec0 1314 if (!aup->phy_dev) return -EINVAL; // PHY not controllable
1da177e4 1315
0638dec0 1316 return phy_mii_ioctl(aup->phy_dev, if_mii(rq), cmd);
1da177e4
LT		 1317}
1318
1da177e4
LT		 1319module_init(au1000_init_module);
1320module_exit(au1000_cleanup_module);
Linux kernel - Deliverables
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