Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * | |
3 | * Alchemy Au1x00 ethernet driver | |
4 | * | |
89be0501 | 5 | * Copyright 2001-2003, 2006 MontaVista Software Inc. |
1da177e4 LT |
6 | * Copyright 2002 TimeSys Corp. |
7 | * Added ethtool/mii-tool support, | |
8 | * Copyright 2004 Matt Porter <mporter@kernel.crashing.org> | |
6aa20a22 JG |
9 | * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de |
10 | * or riemer@riemer-nt.de: fixed the link beat detection with | |
1da177e4 | 11 | * ioctls (SIOCGMIIPHY) |
0638dec0 HVR |
12 | * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org> |
13 | * converted to use linux-2.6.x's PHY framework | |
14 | * | |
1da177e4 LT |
15 | * Author: MontaVista Software, Inc. |
16 | * ppopov@mvista.com or source@mvista.com | |
17 | * | |
18 | * ######################################################################## | |
19 | * | |
20 | * This program is free software; you can distribute it and/or modify it | |
21 | * under the terms of the GNU General Public License (Version 2) as | |
22 | * published by the Free Software Foundation. | |
23 | * | |
24 | * This program is distributed in the hope it will be useful, but WITHOUT | |
25 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
26 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
27 | * for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License along | |
30 | * with this program; if not, write to the Free Software Foundation, Inc., | |
31 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
32 | * | |
33 | * ######################################################################## | |
34 | * | |
6aa20a22 | 35 | * |
1da177e4 | 36 | */ |
d791c2bd | 37 | #include <linux/dma-mapping.h> |
1da177e4 LT |
38 | #include <linux/module.h> |
39 | #include <linux/kernel.h> | |
1da177e4 LT |
40 | #include <linux/string.h> |
41 | #include <linux/timer.h> | |
42 | #include <linux/errno.h> | |
43 | #include <linux/in.h> | |
44 | #include <linux/ioport.h> | |
45 | #include <linux/bitops.h> | |
46 | #include <linux/slab.h> | |
47 | #include <linux/interrupt.h> | |
1da177e4 LT |
48 | #include <linux/init.h> |
49 | #include <linux/netdevice.h> | |
50 | #include <linux/etherdevice.h> | |
51 | #include <linux/ethtool.h> | |
52 | #include <linux/mii.h> | |
53 | #include <linux/skbuff.h> | |
54 | #include <linux/delay.h> | |
8cd35da0 | 55 | #include <linux/crc32.h> |
0638dec0 | 56 | #include <linux/phy.h> |
1da177e4 LT |
57 | #include <asm/mipsregs.h> |
58 | #include <asm/irq.h> | |
59 | #include <asm/io.h> | |
60 | #include <asm/processor.h> | |
61 | ||
62 | #include <asm/mach-au1x00/au1000.h> | |
63 | #include <asm/cpu.h> | |
64 | #include "au1000_eth.h" | |
65 | ||
66 | #ifdef AU1000_ETH_DEBUG | |
67 | static int au1000_debug = 5; | |
68 | #else | |
69 | static int au1000_debug = 3; | |
70 | #endif | |
71 | ||
89be0501 | 72 | #define DRV_NAME "au1000_eth" |
d5b20697 | 73 | #define DRV_VERSION "1.6" |
1da177e4 LT |
74 | #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>" |
75 | #define DRV_DESC "Au1xxx on-chip Ethernet driver" | |
76 | ||
77 | MODULE_AUTHOR(DRV_AUTHOR); | |
78 | MODULE_DESCRIPTION(DRV_DESC); | |
79 | MODULE_LICENSE("GPL"); | |
80 | ||
81 | // prototypes | |
82 | static void hard_stop(struct net_device *); | |
83 | static void enable_rx_tx(struct net_device *dev); | |
89be0501 | 84 | static struct net_device * au1000_probe(int port_num); |
1da177e4 LT |
85 | static int au1000_init(struct net_device *); |
86 | static int au1000_open(struct net_device *); | |
87 | static int au1000_close(struct net_device *); | |
88 | static int au1000_tx(struct sk_buff *, struct net_device *); | |
89 | static int au1000_rx(struct net_device *); | |
7d12e780 | 90 | static irqreturn_t au1000_interrupt(int, void *); |
1da177e4 | 91 | static void au1000_tx_timeout(struct net_device *); |
1da177e4 | 92 | static void set_rx_mode(struct net_device *); |
1da177e4 LT |
93 | static int au1000_ioctl(struct net_device *, struct ifreq *, int); |
94 | static int mdio_read(struct net_device *, int, int); | |
95 | static void mdio_write(struct net_device *, int, int, u16); | |
0638dec0 HVR |
96 | static void au1000_adjust_link(struct net_device *); |
97 | static void enable_mac(struct net_device *, int); | |
1da177e4 LT |
98 | |
99 | // externs | |
1da177e4 LT |
100 | extern int get_ethernet_addr(char *ethernet_addr); |
101 | extern void str2eaddr(unsigned char *ea, unsigned char *str); | |
c21e6d65 | 102 | extern char * prom_getcmdline(void); |
1da177e4 LT |
103 | |
104 | /* | |
105 | * Theory of operation | |
106 | * | |
6aa20a22 JG |
107 | * The Au1000 MACs use a simple rx and tx descriptor ring scheme. |
108 | * There are four receive and four transmit descriptors. These | |
109 | * descriptors are not in memory; rather, they are just a set of | |
1da177e4 LT |
110 | * hardware registers. |
111 | * | |
112 | * Since the Au1000 has a coherent data cache, the receive and | |
6aa20a22 | 113 | * transmit buffers are allocated from the KSEG0 segment. The |
1da177e4 LT |
114 | * hardware registers, however, are still mapped at KSEG1 to |
115 | * make sure there's no out-of-order writes, and that all writes | |
116 | * complete immediately. | |
117 | */ | |
118 | ||
119 | /* These addresses are only used if yamon doesn't tell us what | |
120 | * the mac address is, and the mac address is not passed on the | |
121 | * command line. | |
122 | */ | |
6aa20a22 | 123 | static unsigned char au1000_mac_addr[6] __devinitdata = { |
1da177e4 LT |
124 | 0x00, 0x50, 0xc2, 0x0c, 0x30, 0x00 |
125 | }; | |
126 | ||
1da177e4 LT |
127 | struct au1000_private *au_macs[NUM_ETH_INTERFACES]; |
128 | ||
0638dec0 HVR |
129 | /* |
130 | * board-specific configurations | |
131 | * | |
132 | * PHY detection algorithm | |
133 | * | |
134 | * If AU1XXX_PHY_STATIC_CONFIG is undefined, the PHY setup is | |
135 | * autodetected: | |
136 | * | |
137 | * mii_probe() first searches the current MAC's MII bus for a PHY, | |
138 | * selecting the first (or last, if AU1XXX_PHY_SEARCH_HIGHEST_ADDR is | |
139 | * defined) PHY address not already claimed by another netdev. | |
140 | * | |
141 | * If nothing was found that way when searching for the 2nd ethernet | |
142 | * controller's PHY and AU1XXX_PHY1_SEARCH_ON_MAC0 is defined, then | |
143 | * the first MII bus is searched as well for an unclaimed PHY; this is | |
144 | * needed in case of a dual-PHY accessible only through the MAC0's MII | |
145 | * bus. | |
146 | * | |
147 | * Finally, if no PHY is found, then the corresponding ethernet | |
148 | * controller is not registered to the network subsystem. | |
1da177e4 LT |
149 | */ |
150 | ||
0638dec0 HVR |
151 | /* autodetection defaults */ |
152 | #undef AU1XXX_PHY_SEARCH_HIGHEST_ADDR | |
153 | #define AU1XXX_PHY1_SEARCH_ON_MAC0 | |
1da177e4 | 154 | |
0638dec0 HVR |
155 | /* static PHY setup |
156 | * | |
157 | * most boards PHY setup should be detectable properly with the | |
158 | * autodetection algorithm in mii_probe(), but in some cases (e.g. if | |
159 | * you have a switch attached, or want to use the PHY's interrupt | |
160 | * notification capabilities) you can provide a static PHY | |
161 | * configuration here | |
162 | * | |
163 | * IRQs may only be set, if a PHY address was configured | |
164 | * If a PHY address is given, also a bus id is required to be set | |
165 | * | |
166 | * ps: make sure the used irqs are configured properly in the board | |
167 | * specific irq-map | |
168 | */ | |
1da177e4 | 169 | |
0638dec0 HVR |
170 | #if defined(CONFIG_MIPS_BOSPORUS) |
171 | /* | |
172 | * Micrel/Kendin 5 port switch attached to MAC0, | |
173 | * MAC0 is associated with PHY address 5 (== WAN port) | |
174 | * MAC1 is not associated with any PHY, since it's connected directly | |
175 | * to the switch. | |
176 | * no interrupts are used | |
177 | */ | |
178 | # define AU1XXX_PHY_STATIC_CONFIG | |
1da177e4 | 179 | |
0638dec0 HVR |
180 | # define AU1XXX_PHY0_ADDR 5 |
181 | # define AU1XXX_PHY0_BUSID 0 | |
182 | # undef AU1XXX_PHY0_IRQ | |
1da177e4 | 183 | |
0638dec0 HVR |
184 | # undef AU1XXX_PHY1_ADDR |
185 | # undef AU1XXX_PHY1_BUSID | |
186 | # undef AU1XXX_PHY1_IRQ | |
1da177e4 LT |
187 | #endif |
188 | ||
0638dec0 HVR |
189 | #if defined(AU1XXX_PHY0_BUSID) && (AU1XXX_PHY0_BUSID > 0) |
190 | # error MAC0-associated PHY attached 2nd MACs MII bus not supported yet | |
1da177e4 | 191 | #endif |
1da177e4 | 192 | |
0638dec0 HVR |
193 | /* |
194 | * MII operations | |
195 | */ | |
196 | static int mdio_read(struct net_device *dev, int phy_addr, int reg) | |
1da177e4 LT |
197 | { |
198 | struct au1000_private *aup = (struct au1000_private *) dev->priv; | |
0638dec0 HVR |
199 | volatile u32 *const mii_control_reg = &aup->mac->mii_control; |
200 | volatile u32 *const mii_data_reg = &aup->mac->mii_data; | |
1da177e4 LT |
201 | u32 timedout = 20; |
202 | u32 mii_control; | |
203 | ||
1da177e4 LT |
204 | while (*mii_control_reg & MAC_MII_BUSY) { |
205 | mdelay(1); | |
206 | if (--timedout == 0) { | |
6aa20a22 | 207 | printk(KERN_ERR "%s: read_MII busy timeout!!\n", |
1da177e4 LT |
208 | dev->name); |
209 | return -1; | |
210 | } | |
211 | } | |
212 | ||
6aa20a22 | 213 | mii_control = MAC_SET_MII_SELECT_REG(reg) | |
0638dec0 | 214 | MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ; |
1da177e4 LT |
215 | |
216 | *mii_control_reg = mii_control; | |
217 | ||
218 | timedout = 20; | |
219 | while (*mii_control_reg & MAC_MII_BUSY) { | |
220 | mdelay(1); | |
221 | if (--timedout == 0) { | |
6aa20a22 | 222 | printk(KERN_ERR "%s: mdio_read busy timeout!!\n", |
1da177e4 LT |
223 | dev->name); |
224 | return -1; | |
225 | } | |
226 | } | |
227 | return (int)*mii_data_reg; | |
228 | } | |
229 | ||
0638dec0 | 230 | static void mdio_write(struct net_device *dev, int phy_addr, int reg, u16 value) |
1da177e4 LT |
231 | { |
232 | struct au1000_private *aup = (struct au1000_private *) dev->priv; | |
0638dec0 HVR |
233 | volatile u32 *const mii_control_reg = &aup->mac->mii_control; |
234 | volatile u32 *const mii_data_reg = &aup->mac->mii_data; | |
1da177e4 LT |
235 | u32 timedout = 20; |
236 | u32 mii_control; | |
237 | ||
1da177e4 LT |
238 | while (*mii_control_reg & MAC_MII_BUSY) { |
239 | mdelay(1); | |
240 | if (--timedout == 0) { | |
6aa20a22 | 241 | printk(KERN_ERR "%s: mdio_write busy timeout!!\n", |
1da177e4 LT |
242 | dev->name); |
243 | return; | |
244 | } | |
245 | } | |
246 | ||
6aa20a22 | 247 | mii_control = MAC_SET_MII_SELECT_REG(reg) | |
0638dec0 | 248 | MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE; |
1da177e4 LT |
249 | |
250 | *mii_data_reg = value; | |
251 | *mii_control_reg = mii_control; | |
252 | } | |
253 | ||
0638dec0 HVR |
254 | static int mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) |
255 | { | |
256 | /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does | |
257 | * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus) */ | |
258 | struct net_device *const dev = bus->priv; | |
259 | ||
260 | enable_mac(dev, 0); /* make sure the MAC associated with this | |
261 | * mii_bus is enabled */ | |
262 | return mdio_read(dev, phy_addr, regnum); | |
263 | } | |
1da177e4 | 264 | |
0638dec0 HVR |
265 | static int mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, |
266 | u16 value) | |
1da177e4 | 267 | { |
0638dec0 | 268 | struct net_device *const dev = bus->priv; |
1da177e4 | 269 | |
0638dec0 HVR |
270 | enable_mac(dev, 0); /* make sure the MAC associated with this |
271 | * mii_bus is enabled */ | |
272 | mdio_write(dev, phy_addr, regnum, value); | |
273 | return 0; | |
1da177e4 LT |
274 | } |
275 | ||
0638dec0 | 276 | static int mdiobus_reset(struct mii_bus *bus) |
1da177e4 | 277 | { |
0638dec0 | 278 | struct net_device *const dev = bus->priv; |
1da177e4 | 279 | |
0638dec0 HVR |
280 | enable_mac(dev, 0); /* make sure the MAC associated with this |
281 | * mii_bus is enabled */ | |
282 | return 0; | |
283 | } | |
1da177e4 | 284 | |
0638dec0 HVR |
285 | static int mii_probe (struct net_device *dev) |
286 | { | |
287 | struct au1000_private *const aup = (struct au1000_private *) dev->priv; | |
288 | struct phy_device *phydev = NULL; | |
289 | ||
290 | #if defined(AU1XXX_PHY_STATIC_CONFIG) | |
291 | BUG_ON(aup->mac_id < 0 || aup->mac_id > 1); | |
292 | ||
293 | if(aup->mac_id == 0) { /* get PHY0 */ | |
294 | # if defined(AU1XXX_PHY0_ADDR) | |
295 | phydev = au_macs[AU1XXX_PHY0_BUSID]->mii_bus.phy_map[AU1XXX_PHY0_ADDR]; | |
296 | # else | |
297 | printk (KERN_INFO DRV_NAME ":%s: using PHY-less setup\n", | |
298 | dev->name); | |
299 | return 0; | |
300 | # endif /* defined(AU1XXX_PHY0_ADDR) */ | |
301 | } else if (aup->mac_id == 1) { /* get PHY1 */ | |
302 | # if defined(AU1XXX_PHY1_ADDR) | |
303 | phydev = au_macs[AU1XXX_PHY1_BUSID]->mii_bus.phy_map[AU1XXX_PHY1_ADDR]; | |
304 | # else | |
305 | printk (KERN_INFO DRV_NAME ":%s: using PHY-less setup\n", | |
306 | dev->name); | |
307 | return 0; | |
308 | # endif /* defined(AU1XXX_PHY1_ADDR) */ | |
309 | } | |
310 | ||
311 | #else /* defined(AU1XXX_PHY_STATIC_CONFIG) */ | |
312 | int phy_addr; | |
313 | ||
314 | /* find the first (lowest address) PHY on the current MAC's MII bus */ | |
315 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) | |
316 | if (aup->mii_bus.phy_map[phy_addr]) { | |
317 | phydev = aup->mii_bus.phy_map[phy_addr]; | |
318 | # if !defined(AU1XXX_PHY_SEARCH_HIGHEST_ADDR) | |
319 | break; /* break out with first one found */ | |
320 | # endif | |
1da177e4 | 321 | } |
1da177e4 | 322 | |
0638dec0 HVR |
323 | # if defined(AU1XXX_PHY1_SEARCH_ON_MAC0) |
324 | /* try harder to find a PHY */ | |
325 | if (!phydev && (aup->mac_id == 1)) { | |
326 | /* no PHY found, maybe we have a dual PHY? */ | |
327 | printk (KERN_INFO DRV_NAME ": no PHY found on MAC1, " | |
328 | "let's see if it's attached to MAC0...\n"); | |
329 | ||
330 | BUG_ON(!au_macs[0]); | |
331 | ||
332 | /* find the first (lowest address) non-attached PHY on | |
333 | * the MAC0 MII bus */ | |
334 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { | |
335 | struct phy_device *const tmp_phydev = | |
336 | au_macs[0]->mii_bus.phy_map[phy_addr]; | |
337 | ||
338 | if (!tmp_phydev) | |
339 | continue; /* no PHY here... */ | |
340 | ||
341 | if (tmp_phydev->attached_dev) | |
342 | continue; /* already claimed by MAC0 */ | |
343 | ||
344 | phydev = tmp_phydev; | |
345 | break; /* found it */ | |
1da177e4 LT |
346 | } |
347 | } | |
0638dec0 | 348 | # endif /* defined(AU1XXX_PHY1_SEARCH_OTHER_BUS) */ |
1da177e4 | 349 | |
0638dec0 HVR |
350 | #endif /* defined(AU1XXX_PHY_STATIC_CONFIG) */ |
351 | if (!phydev) { | |
352 | printk (KERN_ERR DRV_NAME ":%s: no PHY found\n", dev->name); | |
1da177e4 LT |
353 | return -1; |
354 | } | |
355 | ||
0638dec0 HVR |
356 | /* now we are supposed to have a proper phydev, to attach to... */ |
357 | BUG_ON(!phydev); | |
358 | BUG_ON(phydev->attached_dev); | |
359 | ||
e8a2b6a4 AF |
360 | phydev = phy_connect(dev, phydev->dev.bus_id, &au1000_adjust_link, 0, |
361 | PHY_INTERFACE_MODE_MII); | |
0638dec0 HVR |
362 | |
363 | if (IS_ERR(phydev)) { | |
364 | printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); | |
365 | return PTR_ERR(phydev); | |
366 | } | |
367 | ||
368 | /* mask with MAC supported features */ | |
369 | phydev->supported &= (SUPPORTED_10baseT_Half | |
370 | | SUPPORTED_10baseT_Full | |
371 | | SUPPORTED_100baseT_Half | |
372 | | SUPPORTED_100baseT_Full | |
373 | | SUPPORTED_Autoneg | |
374 | /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */ | |
375 | | SUPPORTED_MII | |
376 | | SUPPORTED_TP); | |
377 | ||
378 | phydev->advertising = phydev->supported; | |
379 | ||
380 | aup->old_link = 0; | |
381 | aup->old_speed = 0; | |
382 | aup->old_duplex = -1; | |
383 | aup->phy_dev = phydev; | |
384 | ||
385 | printk(KERN_INFO "%s: attached PHY driver [%s] " | |
386 | "(mii_bus:phy_addr=%s, irq=%d)\n", | |
387 | dev->name, phydev->drv->name, phydev->dev.bus_id, phydev->irq); | |
1da177e4 LT |
388 | |
389 | return 0; | |
390 | } | |
391 | ||
392 | ||
393 | /* | |
394 | * Buffer allocation/deallocation routines. The buffer descriptor returned | |
6aa20a22 | 395 | * has the virtual and dma address of a buffer suitable for |
1da177e4 LT |
396 | * both, receive and transmit operations. |
397 | */ | |
398 | static db_dest_t *GetFreeDB(struct au1000_private *aup) | |
399 | { | |
400 | db_dest_t *pDB; | |
401 | pDB = aup->pDBfree; | |
402 | ||
403 | if (pDB) { | |
404 | aup->pDBfree = pDB->pnext; | |
405 | } | |
406 | return pDB; | |
407 | } | |
408 | ||
409 | void ReleaseDB(struct au1000_private *aup, db_dest_t *pDB) | |
410 | { | |
411 | db_dest_t *pDBfree = aup->pDBfree; | |
412 | if (pDBfree) | |
413 | pDBfree->pnext = pDB; | |
414 | aup->pDBfree = pDB; | |
415 | } | |
416 | ||
417 | static void enable_rx_tx(struct net_device *dev) | |
418 | { | |
419 | struct au1000_private *aup = (struct au1000_private *) dev->priv; | |
420 | ||
421 | if (au1000_debug > 4) | |
422 | printk(KERN_INFO "%s: enable_rx_tx\n", dev->name); | |
423 | ||
424 | aup->mac->control |= (MAC_RX_ENABLE | MAC_TX_ENABLE); | |
425 | au_sync_delay(10); | |
426 | } | |
427 | ||
428 | static void hard_stop(struct net_device *dev) | |
429 | { | |
430 | struct au1000_private *aup = (struct au1000_private *) dev->priv; | |
431 | ||
432 | if (au1000_debug > 4) | |
433 | printk(KERN_INFO "%s: hard stop\n", dev->name); | |
434 | ||
435 | aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE); | |
436 | au_sync_delay(10); | |
437 | } | |
438 | ||
0638dec0 | 439 | static void enable_mac(struct net_device *dev, int force_reset) |
1da177e4 | 440 | { |
0638dec0 | 441 | unsigned long flags; |
1da177e4 LT |
442 | struct au1000_private *aup = (struct au1000_private *) dev->priv; |
443 | ||
1da177e4 | 444 | spin_lock_irqsave(&aup->lock, flags); |
1da177e4 | 445 | |
0638dec0 | 446 | if(force_reset || (!aup->mac_enabled)) { |
1da177e4 LT |
447 | *aup->enable = MAC_EN_CLOCK_ENABLE; |
448 | au_sync_delay(2); | |
0638dec0 HVR |
449 | *aup->enable = (MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 |
450 | | MAC_EN_CLOCK_ENABLE); | |
1da177e4 | 451 | au_sync_delay(2); |
0638dec0 HVR |
452 | |
453 | aup->mac_enabled = 1; | |
1da177e4 | 454 | } |
0638dec0 HVR |
455 | |
456 | spin_unlock_irqrestore(&aup->lock, flags); | |
457 | } | |
458 | ||
459 | static void reset_mac_unlocked(struct net_device *dev) | |
460 | { | |
461 | struct au1000_private *const aup = (struct au1000_private *) dev->priv; | |
462 | int i; | |
463 | ||
464 | hard_stop(dev); | |
465 | ||
466 | *aup->enable = MAC_EN_CLOCK_ENABLE; | |
467 | au_sync_delay(2); | |
468 | *aup->enable = 0; | |
469 | au_sync_delay(2); | |
470 | ||
1da177e4 LT |
471 | aup->tx_full = 0; |
472 | for (i = 0; i < NUM_RX_DMA; i++) { | |
473 | /* reset control bits */ | |
474 | aup->rx_dma_ring[i]->buff_stat &= ~0xf; | |
475 | } | |
476 | for (i = 0; i < NUM_TX_DMA; i++) { | |
477 | /* reset control bits */ | |
478 | aup->tx_dma_ring[i]->buff_stat &= ~0xf; | |
479 | } | |
0638dec0 HVR |
480 | |
481 | aup->mac_enabled = 0; | |
482 | ||
1da177e4 LT |
483 | } |
484 | ||
0638dec0 HVR |
485 | static void reset_mac(struct net_device *dev) |
486 | { | |
487 | struct au1000_private *const aup = (struct au1000_private *) dev->priv; | |
488 | unsigned long flags; | |
489 | ||
490 | if (au1000_debug > 4) | |
491 | printk(KERN_INFO "%s: reset mac, aup %x\n", | |
492 | dev->name, (unsigned)aup); | |
493 | ||
494 | spin_lock_irqsave(&aup->lock, flags); | |
495 | ||
496 | reset_mac_unlocked (dev); | |
497 | ||
498 | spin_unlock_irqrestore(&aup->lock, flags); | |
499 | } | |
1da177e4 | 500 | |
6aa20a22 | 501 | /* |
1da177e4 LT |
502 | * Setup the receive and transmit "rings". These pointers are the addresses |
503 | * of the rx and tx MAC DMA registers so they are fixed by the hardware -- | |
504 | * these are not descriptors sitting in memory. | |
505 | */ | |
6aa20a22 | 506 | static void |
1da177e4 LT |
507 | setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base) |
508 | { | |
509 | int i; | |
510 | ||
511 | for (i = 0; i < NUM_RX_DMA; i++) { | |
6aa20a22 | 512 | aup->rx_dma_ring[i] = |
1da177e4 LT |
513 | (volatile rx_dma_t *) (rx_base + sizeof(rx_dma_t)*i); |
514 | } | |
515 | for (i = 0; i < NUM_TX_DMA; i++) { | |
6aa20a22 | 516 | aup->tx_dma_ring[i] = |
1da177e4 LT |
517 | (volatile tx_dma_t *) (tx_base + sizeof(tx_dma_t)*i); |
518 | } | |
519 | } | |
520 | ||
521 | static struct { | |
1da177e4 LT |
522 | u32 base_addr; |
523 | u32 macen_addr; | |
524 | int irq; | |
525 | struct net_device *dev; | |
89be0501 SS |
526 | } iflist[2] = { |
527 | #ifdef CONFIG_SOC_AU1000 | |
528 | {AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT}, | |
529 | {AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT} | |
530 | #endif | |
531 | #ifdef CONFIG_SOC_AU1100 | |
532 | {AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT} | |
533 | #endif | |
534 | #ifdef CONFIG_SOC_AU1500 | |
535 | {AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT}, | |
536 | {AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT} | |
537 | #endif | |
538 | #ifdef CONFIG_SOC_AU1550 | |
539 | {AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT}, | |
540 | {AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT} | |
541 | #endif | |
542 | }; | |
1da177e4 LT |
543 | |
544 | static int num_ifs; | |
545 | ||
546 | /* | |
547 | * Setup the base address and interupt of the Au1xxx ethernet macs | |
548 | * based on cpu type and whether the interface is enabled in sys_pinfunc | |
549 | * register. The last interface is enabled if SYS_PF_NI2 (bit 4) is 0. | |
550 | */ | |
551 | static int __init au1000_init_module(void) | |
552 | { | |
1da177e4 LT |
553 | int ni = (int)((au_readl(SYS_PINFUNC) & (u32)(SYS_PF_NI2)) >> 4); |
554 | struct net_device *dev; | |
555 | int i, found_one = 0; | |
556 | ||
89be0501 SS |
557 | num_ifs = NUM_ETH_INTERFACES - ni; |
558 | ||
1da177e4 | 559 | for(i = 0; i < num_ifs; i++) { |
89be0501 | 560 | dev = au1000_probe(i); |
1da177e4 LT |
561 | iflist[i].dev = dev; |
562 | if (dev) | |
563 | found_one++; | |
564 | } | |
565 | if (!found_one) | |
566 | return -ENODEV; | |
567 | return 0; | |
568 | } | |
569 | ||
0638dec0 HVR |
570 | /* |
571 | * ethtool operations | |
572 | */ | |
1da177e4 | 573 | |
0638dec0 | 574 | static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
575 | { |
576 | struct au1000_private *aup = (struct au1000_private *)dev->priv; | |
1da177e4 | 577 | |
0638dec0 HVR |
578 | if (aup->phy_dev) |
579 | return phy_ethtool_gset(aup->phy_dev, cmd); | |
1da177e4 | 580 | |
0638dec0 | 581 | return -EINVAL; |
1da177e4 LT |
582 | } |
583 | ||
0638dec0 | 584 | static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
585 | { |
586 | struct au1000_private *aup = (struct au1000_private *)dev->priv; | |
1da177e4 | 587 | |
0638dec0 HVR |
588 | if (!capable(CAP_NET_ADMIN)) |
589 | return -EPERM; | |
1da177e4 | 590 | |
0638dec0 HVR |
591 | if (aup->phy_dev) |
592 | return phy_ethtool_sset(aup->phy_dev, cmd); | |
1da177e4 | 593 | |
0638dec0 | 594 | return -EINVAL; |
1da177e4 LT |
595 | } |
596 | ||
597 | static void | |
598 | au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
599 | { | |
600 | struct au1000_private *aup = (struct au1000_private *)dev->priv; | |
601 | ||
602 | strcpy(info->driver, DRV_NAME); | |
603 | strcpy(info->version, DRV_VERSION); | |
604 | info->fw_version[0] = '\0'; | |
605 | sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id); | |
606 | info->regdump_len = 0; | |
607 | } | |
608 | ||
7282d491 | 609 | static const struct ethtool_ops au1000_ethtool_ops = { |
1da177e4 LT |
610 | .get_settings = au1000_get_settings, |
611 | .set_settings = au1000_set_settings, | |
612 | .get_drvinfo = au1000_get_drvinfo, | |
0638dec0 | 613 | .get_link = ethtool_op_get_link, |
1da177e4 LT |
614 | }; |
615 | ||
89be0501 | 616 | static struct net_device * au1000_probe(int port_num) |
1da177e4 LT |
617 | { |
618 | static unsigned version_printed = 0; | |
619 | struct au1000_private *aup = NULL; | |
620 | struct net_device *dev = NULL; | |
621 | db_dest_t *pDB, *pDBfree; | |
622 | char *pmac, *argptr; | |
623 | char ethaddr[6]; | |
89be0501 SS |
624 | int irq, i, err; |
625 | u32 base, macen; | |
626 | ||
627 | if (port_num >= NUM_ETH_INTERFACES) | |
628 | return NULL; | |
1da177e4 | 629 | |
89be0501 SS |
630 | base = CPHYSADDR(iflist[port_num].base_addr ); |
631 | macen = CPHYSADDR(iflist[port_num].macen_addr); | |
632 | irq = iflist[port_num].irq; | |
633 | ||
634 | if (!request_mem_region( base, MAC_IOSIZE, "Au1x00 ENET") || | |
635 | !request_mem_region(macen, 4, "Au1x00 ENET")) | |
1da177e4 LT |
636 | return NULL; |
637 | ||
89be0501 | 638 | if (version_printed++ == 0) |
1da177e4 LT |
639 | printk("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR); |
640 | ||
641 | dev = alloc_etherdev(sizeof(struct au1000_private)); | |
642 | if (!dev) { | |
89be0501 | 643 | printk(KERN_ERR "%s: alloc_etherdev failed\n", DRV_NAME); |
1da177e4 LT |
644 | return NULL; |
645 | } | |
646 | ||
89be0501 SS |
647 | if ((err = register_netdev(dev)) != 0) { |
648 | printk(KERN_ERR "%s: Cannot register net device, error %d\n", | |
649 | DRV_NAME, err); | |
1da177e4 LT |
650 | free_netdev(dev); |
651 | return NULL; | |
652 | } | |
653 | ||
89be0501 SS |
654 | printk("%s: Au1xx0 Ethernet found at 0x%x, irq %d\n", |
655 | dev->name, base, irq); | |
1da177e4 LT |
656 | |
657 | aup = dev->priv; | |
658 | ||
659 | /* Allocate the data buffers */ | |
660 | /* Snooping works fine with eth on all au1xxx */ | |
89be0501 SS |
661 | aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE * |
662 | (NUM_TX_BUFFS + NUM_RX_BUFFS), | |
663 | &aup->dma_addr, 0); | |
1da177e4 LT |
664 | if (!aup->vaddr) { |
665 | free_netdev(dev); | |
89be0501 SS |
666 | release_mem_region( base, MAC_IOSIZE); |
667 | release_mem_region(macen, 4); | |
1da177e4 LT |
668 | return NULL; |
669 | } | |
670 | ||
671 | /* aup->mac is the base address of the MAC's registers */ | |
89be0501 SS |
672 | aup->mac = (volatile mac_reg_t *)iflist[port_num].base_addr; |
673 | ||
1da177e4 | 674 | /* Setup some variables for quick register address access */ |
89be0501 SS |
675 | aup->enable = (volatile u32 *)iflist[port_num].macen_addr; |
676 | aup->mac_id = port_num; | |
677 | au_macs[port_num] = aup; | |
678 | ||
679 | if (port_num == 0) { | |
680 | /* Check the environment variables first */ | |
681 | if (get_ethernet_addr(ethaddr) == 0) | |
1da177e4 | 682 | memcpy(au1000_mac_addr, ethaddr, sizeof(au1000_mac_addr)); |
89be0501 | 683 | else { |
1da177e4 LT |
684 | /* Check command line */ |
685 | argptr = prom_getcmdline(); | |
89be0501 SS |
686 | if ((pmac = strstr(argptr, "ethaddr=")) == NULL) |
687 | printk(KERN_INFO "%s: No MAC address found\n", | |
688 | dev->name); | |
689 | /* Use the hard coded MAC addresses */ | |
690 | else { | |
1da177e4 | 691 | str2eaddr(ethaddr, pmac + strlen("ethaddr=")); |
6aa20a22 | 692 | memcpy(au1000_mac_addr, ethaddr, |
89be0501 | 693 | sizeof(au1000_mac_addr)); |
1da177e4 LT |
694 | } |
695 | } | |
89be0501 | 696 | |
1da177e4 | 697 | setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR); |
89be0501 | 698 | } else if (port_num == 1) |
1da177e4 | 699 | setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR); |
1da177e4 | 700 | |
89be0501 SS |
701 | /* |
702 | * Assign to the Ethernet ports two consecutive MAC addresses | |
703 | * to match those that are printed on their stickers | |
704 | */ | |
705 | memcpy(dev->dev_addr, au1000_mac_addr, sizeof(au1000_mac_addr)); | |
706 | dev->dev_addr[5] += port_num; | |
707 | ||
0638dec0 HVR |
708 | *aup->enable = 0; |
709 | aup->mac_enabled = 0; | |
710 | ||
711 | aup->mii_bus.priv = dev; | |
712 | aup->mii_bus.read = mdiobus_read; | |
713 | aup->mii_bus.write = mdiobus_write; | |
714 | aup->mii_bus.reset = mdiobus_reset; | |
715 | aup->mii_bus.name = "au1000_eth_mii"; | |
716 | aup->mii_bus.id = aup->mac_id; | |
717 | aup->mii_bus.irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); | |
718 | for(i = 0; i < PHY_MAX_ADDR; ++i) | |
719 | aup->mii_bus.irq[i] = PHY_POLL; | |
720 | ||
721 | /* if known, set corresponding PHY IRQs */ | |
722 | #if defined(AU1XXX_PHY_STATIC_CONFIG) | |
723 | # if defined(AU1XXX_PHY0_IRQ) | |
724 | if (AU1XXX_PHY0_BUSID == aup->mii_bus.id) | |
725 | aup->mii_bus.irq[AU1XXX_PHY0_ADDR] = AU1XXX_PHY0_IRQ; | |
726 | # endif | |
727 | # if defined(AU1XXX_PHY1_IRQ) | |
728 | if (AU1XXX_PHY1_BUSID == aup->mii_bus.id) | |
729 | aup->mii_bus.irq[AU1XXX_PHY1_ADDR] = AU1XXX_PHY1_IRQ; | |
730 | # endif | |
731 | #endif | |
732 | mdiobus_register(&aup->mii_bus); | |
1da177e4 LT |
733 | |
734 | if (mii_probe(dev) != 0) { | |
735 | goto err_out; | |
736 | } | |
737 | ||
738 | pDBfree = NULL; | |
739 | /* setup the data buffer descriptors and attach a buffer to each one */ | |
740 | pDB = aup->db; | |
741 | for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) { | |
742 | pDB->pnext = pDBfree; | |
743 | pDBfree = pDB; | |
744 | pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i); | |
745 | pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr); | |
746 | pDB++; | |
747 | } | |
748 | aup->pDBfree = pDBfree; | |
749 | ||
750 | for (i = 0; i < NUM_RX_DMA; i++) { | |
751 | pDB = GetFreeDB(aup); | |
752 | if (!pDB) { | |
753 | goto err_out; | |
754 | } | |
755 | aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr; | |
756 | aup->rx_db_inuse[i] = pDB; | |
757 | } | |
758 | for (i = 0; i < NUM_TX_DMA; i++) { | |
759 | pDB = GetFreeDB(aup); | |
760 | if (!pDB) { | |
761 | goto err_out; | |
762 | } | |
763 | aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr; | |
764 | aup->tx_dma_ring[i]->len = 0; | |
765 | aup->tx_db_inuse[i] = pDB; | |
766 | } | |
767 | ||
768 | spin_lock_init(&aup->lock); | |
89be0501 | 769 | dev->base_addr = base; |
1da177e4 LT |
770 | dev->irq = irq; |
771 | dev->open = au1000_open; | |
772 | dev->hard_start_xmit = au1000_tx; | |
773 | dev->stop = au1000_close; | |
1da177e4 LT |
774 | dev->set_multicast_list = &set_rx_mode; |
775 | dev->do_ioctl = &au1000_ioctl; | |
776 | SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops); | |
1da177e4 LT |
777 | dev->tx_timeout = au1000_tx_timeout; |
778 | dev->watchdog_timeo = ETH_TX_TIMEOUT; | |
779 | ||
6aa20a22 JG |
780 | /* |
781 | * The boot code uses the ethernet controller, so reset it to start | |
1da177e4 LT |
782 | * fresh. au1000_init() expects that the device is in reset state. |
783 | */ | |
784 | reset_mac(dev); | |
785 | ||
786 | return dev; | |
787 | ||
788 | err_out: | |
789 | /* here we should have a valid dev plus aup-> register addresses | |
790 | * so we can reset the mac properly.*/ | |
791 | reset_mac(dev); | |
0638dec0 | 792 | |
1da177e4 LT |
793 | for (i = 0; i < NUM_RX_DMA; i++) { |
794 | if (aup->rx_db_inuse[i]) | |
795 | ReleaseDB(aup, aup->rx_db_inuse[i]); | |
796 | } | |
797 | for (i = 0; i < NUM_TX_DMA; i++) { | |
798 | if (aup->tx_db_inuse[i]) | |
799 | ReleaseDB(aup, aup->tx_db_inuse[i]); | |
800 | } | |
89be0501 SS |
801 | dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS), |
802 | (void *)aup->vaddr, aup->dma_addr); | |
1da177e4 LT |
803 | unregister_netdev(dev); |
804 | free_netdev(dev); | |
89be0501 SS |
805 | release_mem_region( base, MAC_IOSIZE); |
806 | release_mem_region(macen, 4); | |
1da177e4 LT |
807 | return NULL; |
808 | } | |
809 | ||
6aa20a22 | 810 | /* |
1da177e4 LT |
811 | * Initialize the interface. |
812 | * | |
813 | * When the device powers up, the clocks are disabled and the | |
814 | * mac is in reset state. When the interface is closed, we | |
815 | * do the same -- reset the device and disable the clocks to | |
816 | * conserve power. Thus, whenever au1000_init() is called, | |
817 | * the device should already be in reset state. | |
818 | */ | |
819 | static int au1000_init(struct net_device *dev) | |
820 | { | |
821 | struct au1000_private *aup = (struct au1000_private *) dev->priv; | |
822 | u32 flags; | |
823 | int i; | |
824 | u32 control; | |
1da177e4 | 825 | |
6aa20a22 | 826 | if (au1000_debug > 4) |
1da177e4 LT |
827 | printk("%s: au1000_init\n", dev->name); |
828 | ||
1da177e4 | 829 | /* bring the device out of reset */ |
0638dec0 HVR |
830 | enable_mac(dev, 1); |
831 | ||
832 | spin_lock_irqsave(&aup->lock, flags); | |
1da177e4 LT |
833 | |
834 | aup->mac->control = 0; | |
835 | aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2; | |
836 | aup->tx_tail = aup->tx_head; | |
837 | aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2; | |
838 | ||
839 | aup->mac->mac_addr_high = dev->dev_addr[5]<<8 | dev->dev_addr[4]; | |
840 | aup->mac->mac_addr_low = dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 | | |
841 | dev->dev_addr[1]<<8 | dev->dev_addr[0]; | |
842 | ||
843 | for (i = 0; i < NUM_RX_DMA; i++) { | |
844 | aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE; | |
845 | } | |
846 | au_sync(); | |
847 | ||
0638dec0 | 848 | control = MAC_RX_ENABLE | MAC_TX_ENABLE; |
1da177e4 LT |
849 | #ifndef CONFIG_CPU_LITTLE_ENDIAN |
850 | control |= MAC_BIG_ENDIAN; | |
851 | #endif | |
0638dec0 HVR |
852 | if (aup->phy_dev) { |
853 | if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex)) | |
854 | control |= MAC_FULL_DUPLEX; | |
855 | else | |
856 | control |= MAC_DISABLE_RX_OWN; | |
857 | } else { /* PHY-less op, assume full-duplex */ | |
1da177e4 LT |
858 | control |= MAC_FULL_DUPLEX; |
859 | } | |
860 | ||
1da177e4 LT |
861 | aup->mac->control = control; |
862 | aup->mac->vlan1_tag = 0x8100; /* activate vlan support */ | |
863 | au_sync(); | |
864 | ||
865 | spin_unlock_irqrestore(&aup->lock, flags); | |
866 | return 0; | |
867 | } | |
868 | ||
0638dec0 HVR |
869 | static void |
870 | au1000_adjust_link(struct net_device *dev) | |
1da177e4 | 871 | { |
1da177e4 | 872 | struct au1000_private *aup = (struct au1000_private *) dev->priv; |
0638dec0 HVR |
873 | struct phy_device *phydev = aup->phy_dev; |
874 | unsigned long flags; | |
1da177e4 | 875 | |
0638dec0 | 876 | int status_change = 0; |
1da177e4 | 877 | |
0638dec0 HVR |
878 | BUG_ON(!aup->phy_dev); |
879 | ||
880 | spin_lock_irqsave(&aup->lock, flags); | |
881 | ||
882 | if (phydev->link && (aup->old_speed != phydev->speed)) { | |
883 | // speed changed | |
884 | ||
885 | switch(phydev->speed) { | |
886 | case SPEED_10: | |
887 | case SPEED_100: | |
888 | break; | |
889 | default: | |
890 | printk(KERN_WARNING | |
891 | "%s: Speed (%d) is not 10/100 ???\n", | |
892 | dev->name, phydev->speed); | |
893 | break; | |
1da177e4 | 894 | } |
0638dec0 HVR |
895 | |
896 | aup->old_speed = phydev->speed; | |
897 | ||
898 | status_change = 1; | |
1da177e4 LT |
899 | } |
900 | ||
0638dec0 HVR |
901 | if (phydev->link && (aup->old_duplex != phydev->duplex)) { |
902 | // duplex mode changed | |
903 | ||
904 | /* switching duplex mode requires to disable rx and tx! */ | |
1da177e4 | 905 | hard_stop(dev); |
0638dec0 HVR |
906 | |
907 | if (DUPLEX_FULL == phydev->duplex) | |
908 | aup->mac->control = ((aup->mac->control | |
909 | | MAC_FULL_DUPLEX) | |
910 | & ~MAC_DISABLE_RX_OWN); | |
911 | else | |
912 | aup->mac->control = ((aup->mac->control | |
913 | & ~MAC_FULL_DUPLEX) | |
914 | | MAC_DISABLE_RX_OWN); | |
915 | au_sync_delay(1); | |
916 | ||
1da177e4 | 917 | enable_rx_tx(dev); |
0638dec0 HVR |
918 | aup->old_duplex = phydev->duplex; |
919 | ||
920 | status_change = 1; | |
921 | } | |
922 | ||
923 | if(phydev->link != aup->old_link) { | |
924 | // link state changed | |
925 | ||
926 | if (phydev->link) // link went up | |
927 | netif_schedule(dev); | |
928 | else { // link went down | |
929 | aup->old_speed = 0; | |
930 | aup->old_duplex = -1; | |
931 | } | |
932 | ||
933 | aup->old_link = phydev->link; | |
934 | status_change = 1; | |
1da177e4 LT |
935 | } |
936 | ||
0638dec0 | 937 | spin_unlock_irqrestore(&aup->lock, flags); |
1da177e4 | 938 | |
0638dec0 HVR |
939 | if (status_change) { |
940 | if (phydev->link) | |
941 | printk(KERN_INFO "%s: link up (%d/%s)\n", | |
942 | dev->name, phydev->speed, | |
943 | DUPLEX_FULL == phydev->duplex ? "Full" : "Half"); | |
944 | else | |
945 | printk(KERN_INFO "%s: link down\n", dev->name); | |
946 | } | |
1da177e4 LT |
947 | } |
948 | ||
949 | static int au1000_open(struct net_device *dev) | |
950 | { | |
951 | int retval; | |
952 | struct au1000_private *aup = (struct au1000_private *) dev->priv; | |
953 | ||
954 | if (au1000_debug > 4) | |
955 | printk("%s: open: dev=%p\n", dev->name, dev); | |
956 | ||
0638dec0 HVR |
957 | if ((retval = request_irq(dev->irq, &au1000_interrupt, 0, |
958 | dev->name, dev))) { | |
959 | printk(KERN_ERR "%s: unable to get IRQ %d\n", | |
960 | dev->name, dev->irq); | |
961 | return retval; | |
962 | } | |
963 | ||
1da177e4 LT |
964 | if ((retval = au1000_init(dev))) { |
965 | printk(KERN_ERR "%s: error in au1000_init\n", dev->name); | |
966 | free_irq(dev->irq, dev); | |
967 | return retval; | |
968 | } | |
1da177e4 | 969 | |
0638dec0 HVR |
970 | if (aup->phy_dev) { |
971 | /* cause the PHY state machine to schedule a link state check */ | |
972 | aup->phy_dev->state = PHY_CHANGELINK; | |
973 | phy_start(aup->phy_dev); | |
1da177e4 LT |
974 | } |
975 | ||
0638dec0 | 976 | netif_start_queue(dev); |
1da177e4 LT |
977 | |
978 | if (au1000_debug > 4) | |
979 | printk("%s: open: Initialization done.\n", dev->name); | |
980 | ||
981 | return 0; | |
982 | } | |
983 | ||
984 | static int au1000_close(struct net_device *dev) | |
985 | { | |
0638dec0 HVR |
986 | unsigned long flags; |
987 | struct au1000_private *const aup = (struct au1000_private *) dev->priv; | |
1da177e4 LT |
988 | |
989 | if (au1000_debug > 4) | |
990 | printk("%s: close: dev=%p\n", dev->name, dev); | |
991 | ||
0638dec0 HVR |
992 | if (aup->phy_dev) |
993 | phy_stop(aup->phy_dev); | |
1da177e4 LT |
994 | |
995 | spin_lock_irqsave(&aup->lock, flags); | |
0638dec0 HVR |
996 | |
997 | reset_mac_unlocked (dev); | |
998 | ||
1da177e4 LT |
999 | /* stop the device */ |
1000 | netif_stop_queue(dev); | |
1001 | ||
1002 | /* disable the interrupt */ | |
1003 | free_irq(dev->irq, dev); | |
1004 | spin_unlock_irqrestore(&aup->lock, flags); | |
1005 | ||
1006 | return 0; | |
1007 | } | |
1008 | ||
1009 | static void __exit au1000_cleanup_module(void) | |
1010 | { | |
1011 | int i, j; | |
1012 | struct net_device *dev; | |
1013 | struct au1000_private *aup; | |
1014 | ||
1015 | for (i = 0; i < num_ifs; i++) { | |
1016 | dev = iflist[i].dev; | |
1017 | if (dev) { | |
1018 | aup = (struct au1000_private *) dev->priv; | |
1019 | unregister_netdev(dev); | |
89be0501 | 1020 | for (j = 0; j < NUM_RX_DMA; j++) |
1da177e4 LT |
1021 | if (aup->rx_db_inuse[j]) |
1022 | ReleaseDB(aup, aup->rx_db_inuse[j]); | |
89be0501 | 1023 | for (j = 0; j < NUM_TX_DMA; j++) |
1da177e4 LT |
1024 | if (aup->tx_db_inuse[j]) |
1025 | ReleaseDB(aup, aup->tx_db_inuse[j]); | |
89be0501 SS |
1026 | dma_free_noncoherent(NULL, MAX_BUF_SIZE * |
1027 | (NUM_TX_BUFFS + NUM_RX_BUFFS), | |
1028 | (void *)aup->vaddr, aup->dma_addr); | |
1029 | release_mem_region(dev->base_addr, MAC_IOSIZE); | |
1030 | release_mem_region(CPHYSADDR(iflist[i].macen_addr), 4); | |
1da177e4 | 1031 | free_netdev(dev); |
1da177e4 LT |
1032 | } |
1033 | } | |
1034 | } | |
1035 | ||
c2d3d4b9 | 1036 | static void update_tx_stats(struct net_device *dev, u32 status) |
1da177e4 LT |
1037 | { |
1038 | struct au1000_private *aup = (struct au1000_private *) dev->priv; | |
09f75cd7 | 1039 | struct net_device_stats *ps = &dev->stats; |
1da177e4 | 1040 | |
1da177e4 | 1041 | if (status & TX_FRAME_ABORTED) { |
0638dec0 | 1042 | if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) { |
1da177e4 LT |
1043 | if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) { |
1044 | /* any other tx errors are only valid | |
1045 | * in half duplex mode */ | |
1046 | ps->tx_errors++; | |
1047 | ps->tx_aborted_errors++; | |
1048 | } | |
1049 | } | |
1050 | else { | |
1051 | ps->tx_errors++; | |
1052 | ps->tx_aborted_errors++; | |
1053 | if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER)) | |
1054 | ps->tx_carrier_errors++; | |
1055 | } | |
1056 | } | |
1057 | } | |
1058 | ||
1059 | ||
1060 | /* | |
1061 | * Called from the interrupt service routine to acknowledge | |
1062 | * the TX DONE bits. This is a must if the irq is setup as | |
1063 | * edge triggered. | |
1064 | */ | |
1065 | static void au1000_tx_ack(struct net_device *dev) | |
1066 | { | |
1067 | struct au1000_private *aup = (struct au1000_private *) dev->priv; | |
1068 | volatile tx_dma_t *ptxd; | |
1069 | ||
1070 | ptxd = aup->tx_dma_ring[aup->tx_tail]; | |
1071 | ||
1072 | while (ptxd->buff_stat & TX_T_DONE) { | |
c2d3d4b9 | 1073 | update_tx_stats(dev, ptxd->status); |
1da177e4 LT |
1074 | ptxd->buff_stat &= ~TX_T_DONE; |
1075 | ptxd->len = 0; | |
1076 | au_sync(); | |
1077 | ||
1078 | aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1); | |
1079 | ptxd = aup->tx_dma_ring[aup->tx_tail]; | |
1080 | ||
1081 | if (aup->tx_full) { | |
1082 | aup->tx_full = 0; | |
1083 | netif_wake_queue(dev); | |
1084 | } | |
1085 | } | |
1086 | } | |
1087 | ||
1088 | ||
1089 | /* | |
1090 | * Au1000 transmit routine. | |
1091 | */ | |
1092 | static int au1000_tx(struct sk_buff *skb, struct net_device *dev) | |
1093 | { | |
1094 | struct au1000_private *aup = (struct au1000_private *) dev->priv; | |
09f75cd7 | 1095 | struct net_device_stats *ps = &dev->stats; |
1da177e4 LT |
1096 | volatile tx_dma_t *ptxd; |
1097 | u32 buff_stat; | |
1098 | db_dest_t *pDB; | |
1099 | int i; | |
1100 | ||
1101 | if (au1000_debug > 5) | |
6aa20a22 JG |
1102 | printk("%s: tx: aup %x len=%d, data=%p, head %d\n", |
1103 | dev->name, (unsigned)aup, skb->len, | |
1da177e4 LT |
1104 | skb->data, aup->tx_head); |
1105 | ||
1106 | ptxd = aup->tx_dma_ring[aup->tx_head]; | |
1107 | buff_stat = ptxd->buff_stat; | |
1108 | if (buff_stat & TX_DMA_ENABLE) { | |
1109 | /* We've wrapped around and the transmitter is still busy */ | |
1110 | netif_stop_queue(dev); | |
1111 | aup->tx_full = 1; | |
1112 | return 1; | |
1113 | } | |
1114 | else if (buff_stat & TX_T_DONE) { | |
c2d3d4b9 | 1115 | update_tx_stats(dev, ptxd->status); |
1da177e4 LT |
1116 | ptxd->len = 0; |
1117 | } | |
1118 | ||
1119 | if (aup->tx_full) { | |
1120 | aup->tx_full = 0; | |
1121 | netif_wake_queue(dev); | |
1122 | } | |
1123 | ||
1124 | pDB = aup->tx_db_inuse[aup->tx_head]; | |
d626f62b | 1125 | skb_copy_from_linear_data(skb, pDB->vaddr, skb->len); |
1da177e4 | 1126 | if (skb->len < ETH_ZLEN) { |
6aa20a22 | 1127 | for (i=skb->len; i<ETH_ZLEN; i++) { |
1da177e4 LT |
1128 | ((char *)pDB->vaddr)[i] = 0; |
1129 | } | |
1130 | ptxd->len = ETH_ZLEN; | |
1131 | } | |
1132 | else | |
1133 | ptxd->len = skb->len; | |
1134 | ||
c2d3d4b9 SS |
1135 | ps->tx_packets++; |
1136 | ps->tx_bytes += ptxd->len; | |
1137 | ||
1da177e4 LT |
1138 | ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE; |
1139 | au_sync(); | |
1140 | dev_kfree_skb(skb); | |
1141 | aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1); | |
1142 | dev->trans_start = jiffies; | |
1143 | return 0; | |
1144 | } | |
1145 | ||
1da177e4 LT |
1146 | static inline void update_rx_stats(struct net_device *dev, u32 status) |
1147 | { | |
1148 | struct au1000_private *aup = (struct au1000_private *) dev->priv; | |
09f75cd7 | 1149 | struct net_device_stats *ps = &dev->stats; |
1da177e4 LT |
1150 | |
1151 | ps->rx_packets++; | |
1152 | if (status & RX_MCAST_FRAME) | |
1153 | ps->multicast++; | |
1154 | ||
1155 | if (status & RX_ERROR) { | |
1156 | ps->rx_errors++; | |
1157 | if (status & RX_MISSED_FRAME) | |
1158 | ps->rx_missed_errors++; | |
1159 | if (status & (RX_OVERLEN | RX_OVERLEN | RX_LEN_ERROR)) | |
1160 | ps->rx_length_errors++; | |
1161 | if (status & RX_CRC_ERROR) | |
1162 | ps->rx_crc_errors++; | |
1163 | if (status & RX_COLL) | |
1164 | ps->collisions++; | |
1165 | } | |
6aa20a22 | 1166 | else |
1da177e4 LT |
1167 | ps->rx_bytes += status & RX_FRAME_LEN_MASK; |
1168 | ||
1169 | } | |
1170 | ||
1171 | /* | |
1172 | * Au1000 receive routine. | |
1173 | */ | |
1174 | static int au1000_rx(struct net_device *dev) | |
1175 | { | |
1176 | struct au1000_private *aup = (struct au1000_private *) dev->priv; | |
1177 | struct sk_buff *skb; | |
1178 | volatile rx_dma_t *prxd; | |
1179 | u32 buff_stat, status; | |
1180 | db_dest_t *pDB; | |
1181 | u32 frmlen; | |
1182 | ||
1183 | if (au1000_debug > 5) | |
1184 | printk("%s: au1000_rx head %d\n", dev->name, aup->rx_head); | |
1185 | ||
1186 | prxd = aup->rx_dma_ring[aup->rx_head]; | |
1187 | buff_stat = prxd->buff_stat; | |
1188 | while (buff_stat & RX_T_DONE) { | |
1189 | status = prxd->status; | |
1190 | pDB = aup->rx_db_inuse[aup->rx_head]; | |
1191 | update_rx_stats(dev, status); | |
1192 | if (!(status & RX_ERROR)) { | |
1193 | ||
1194 | /* good frame */ | |
1195 | frmlen = (status & RX_FRAME_LEN_MASK); | |
1196 | frmlen -= 4; /* Remove FCS */ | |
1197 | skb = dev_alloc_skb(frmlen + 2); | |
1198 | if (skb == NULL) { | |
1199 | printk(KERN_ERR | |
1200 | "%s: Memory squeeze, dropping packet.\n", | |
1201 | dev->name); | |
09f75cd7 | 1202 | dev->stats.rx_dropped++; |
1da177e4 LT |
1203 | continue; |
1204 | } | |
1da177e4 | 1205 | skb_reserve(skb, 2); /* 16 byte IP header align */ |
8c7b7faa DM |
1206 | skb_copy_to_linear_data(skb, |
1207 | (unsigned char *)pDB->vaddr, frmlen); | |
1da177e4 LT |
1208 | skb_put(skb, frmlen); |
1209 | skb->protocol = eth_type_trans(skb, dev); | |
1210 | netif_rx(skb); /* pass the packet to upper layers */ | |
1211 | } | |
1212 | else { | |
1213 | if (au1000_debug > 4) { | |
6aa20a22 | 1214 | if (status & RX_MISSED_FRAME) |
1da177e4 | 1215 | printk("rx miss\n"); |
6aa20a22 | 1216 | if (status & RX_WDOG_TIMER) |
1da177e4 | 1217 | printk("rx wdog\n"); |
6aa20a22 | 1218 | if (status & RX_RUNT) |
1da177e4 | 1219 | printk("rx runt\n"); |
6aa20a22 | 1220 | if (status & RX_OVERLEN) |
1da177e4 LT |
1221 | printk("rx overlen\n"); |
1222 | if (status & RX_COLL) | |
1223 | printk("rx coll\n"); | |
1224 | if (status & RX_MII_ERROR) | |
1225 | printk("rx mii error\n"); | |
1226 | if (status & RX_CRC_ERROR) | |
1227 | printk("rx crc error\n"); | |
1228 | if (status & RX_LEN_ERROR) | |
1229 | printk("rx len error\n"); | |
1230 | if (status & RX_U_CNTRL_FRAME) | |
1231 | printk("rx u control frame\n"); | |
1232 | if (status & RX_MISSED_FRAME) | |
1233 | printk("rx miss\n"); | |
1234 | } | |
1235 | } | |
1236 | prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE); | |
1237 | aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1); | |
1238 | au_sync(); | |
1239 | ||
1240 | /* next descriptor */ | |
1241 | prxd = aup->rx_dma_ring[aup->rx_head]; | |
1242 | buff_stat = prxd->buff_stat; | |
1243 | dev->last_rx = jiffies; | |
1244 | } | |
1245 | return 0; | |
1246 | } | |
1247 | ||
1248 | ||
1249 | /* | |
1250 | * Au1000 interrupt service routine. | |
1251 | */ | |
7d12e780 | 1252 | static irqreturn_t au1000_interrupt(int irq, void *dev_id) |
1da177e4 LT |
1253 | { |
1254 | struct net_device *dev = (struct net_device *) dev_id; | |
1255 | ||
1256 | if (dev == NULL) { | |
1257 | printk(KERN_ERR "%s: isr: null dev ptr\n", dev->name); | |
1258 | return IRQ_RETVAL(1); | |
1259 | } | |
1260 | ||
1261 | /* Handle RX interrupts first to minimize chance of overrun */ | |
1262 | ||
1263 | au1000_rx(dev); | |
1264 | au1000_tx_ack(dev); | |
1265 | return IRQ_RETVAL(1); | |
1266 | } | |
1267 | ||
1268 | ||
1269 | /* | |
1270 | * The Tx ring has been full longer than the watchdog timeout | |
1271 | * value. The transmitter must be hung? | |
1272 | */ | |
1273 | static void au1000_tx_timeout(struct net_device *dev) | |
1274 | { | |
1275 | printk(KERN_ERR "%s: au1000_tx_timeout: dev=%p\n", dev->name, dev); | |
1276 | reset_mac(dev); | |
1277 | au1000_init(dev); | |
1278 | dev->trans_start = jiffies; | |
1279 | netif_wake_queue(dev); | |
1280 | } | |
1281 | ||
1da177e4 LT |
1282 | static void set_rx_mode(struct net_device *dev) |
1283 | { | |
1284 | struct au1000_private *aup = (struct au1000_private *) dev->priv; | |
1285 | ||
6aa20a22 | 1286 | if (au1000_debug > 4) |
1da177e4 LT |
1287 | printk("%s: set_rx_mode: flags=%x\n", dev->name, dev->flags); |
1288 | ||
1289 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ | |
1290 | aup->mac->control |= MAC_PROMISCUOUS; | |
1da177e4 LT |
1291 | } else if ((dev->flags & IFF_ALLMULTI) || |
1292 | dev->mc_count > MULTICAST_FILTER_LIMIT) { | |
1293 | aup->mac->control |= MAC_PASS_ALL_MULTI; | |
1294 | aup->mac->control &= ~MAC_PROMISCUOUS; | |
1295 | printk(KERN_INFO "%s: Pass all multicast\n", dev->name); | |
1296 | } else { | |
1297 | int i; | |
1298 | struct dev_mc_list *mclist; | |
1299 | u32 mc_filter[2]; /* Multicast hash filter */ | |
1300 | ||
1301 | mc_filter[1] = mc_filter[0] = 0; | |
1302 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
1303 | i++, mclist = mclist->next) { | |
6aa20a22 | 1304 | set_bit(ether_crc(ETH_ALEN, mclist->dmi_addr)>>26, |
1da177e4 LT |
1305 | (long *)mc_filter); |
1306 | } | |
1307 | aup->mac->multi_hash_high = mc_filter[1]; | |
1308 | aup->mac->multi_hash_low = mc_filter[0]; | |
1309 | aup->mac->control &= ~MAC_PROMISCUOUS; | |
1310 | aup->mac->control |= MAC_HASH_MODE; | |
1311 | } | |
1312 | } | |
1313 | ||
1da177e4 LT |
1314 | static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
1315 | { | |
1316 | struct au1000_private *aup = (struct au1000_private *)dev->priv; | |
1da177e4 | 1317 | |
0638dec0 | 1318 | if (!netif_running(dev)) return -EINVAL; |
1da177e4 | 1319 | |
0638dec0 | 1320 | if (!aup->phy_dev) return -EINVAL; // PHY not controllable |
1da177e4 | 1321 | |
0638dec0 | 1322 | return phy_mii_ioctl(aup->phy_dev, if_mii(rq), cmd); |
1da177e4 LT |
1323 | } |
1324 | ||
1da177e4 LT |
1325 | module_init(au1000_init_module); |
1326 | module_exit(au1000_cleanup_module); |