Commit | Line | Data |
---|---|---|
e190d6b1 | 1 | /* |
2fb9d6f5 | 2 | * Blackfin On-Chip MAC Driver |
e190d6b1 | 3 | * |
2fb9d6f5 | 4 | * Copyright 2004-2007 Analog Devices Inc. |
e190d6b1 | 5 | * |
2fb9d6f5 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
e190d6b1 | 7 | * |
2fb9d6f5 | 8 | * Licensed under the GPL-2 or later. |
e190d6b1 BW |
9 | */ |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/timer.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/ioport.h> | |
22 | #include <linux/crc32.h> | |
23 | #include <linux/device.h> | |
24 | #include <linux/spinlock.h> | |
e190d6b1 | 25 | #include <linux/mii.h> |
4ae5a3ad | 26 | #include <linux/phy.h> |
e190d6b1 BW |
27 | #include <linux/netdevice.h> |
28 | #include <linux/etherdevice.h> | |
679dce39 | 29 | #include <linux/ethtool.h> |
e190d6b1 | 30 | #include <linux/skbuff.h> |
e190d6b1 | 31 | #include <linux/platform_device.h> |
e190d6b1 BW |
32 | |
33 | #include <asm/dma.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | ||
98f672ca | 36 | #include <asm/dpmc.h> |
e190d6b1 BW |
37 | #include <asm/blackfin.h> |
38 | #include <asm/cacheflush.h> | |
39 | #include <asm/portmux.h> | |
40 | ||
41 | #include "bfin_mac.h" | |
42 | ||
43 | #define DRV_NAME "bfin_mac" | |
44 | #define DRV_VERSION "1.1" | |
45 | #define DRV_AUTHOR "Bryan Wu, Luke Yang" | |
7ef0a7ee | 46 | #define DRV_DESC "Blackfin on-chip Ethernet MAC driver" |
e190d6b1 BW |
47 | |
48 | MODULE_AUTHOR(DRV_AUTHOR); | |
49 | MODULE_LICENSE("GPL"); | |
50 | MODULE_DESCRIPTION(DRV_DESC); | |
72abb461 | 51 | MODULE_ALIAS("platform:bfin_mac"); |
e190d6b1 BW |
52 | |
53 | #if defined(CONFIG_BFIN_MAC_USE_L1) | |
54 | # define bfin_mac_alloc(dma_handle, size) l1_data_sram_zalloc(size) | |
55 | # define bfin_mac_free(dma_handle, ptr) l1_data_sram_free(ptr) | |
56 | #else | |
57 | # define bfin_mac_alloc(dma_handle, size) \ | |
58 | dma_alloc_coherent(NULL, size, dma_handle, GFP_KERNEL) | |
59 | # define bfin_mac_free(dma_handle, ptr) \ | |
60 | dma_free_coherent(NULL, sizeof(*ptr), ptr, dma_handle) | |
61 | #endif | |
62 | ||
63 | #define PKT_BUF_SZ 1580 | |
64 | ||
65 | #define MAX_TIMEOUT_CNT 500 | |
66 | ||
67 | /* pointers to maintain transmit list */ | |
68 | static struct net_dma_desc_tx *tx_list_head; | |
69 | static struct net_dma_desc_tx *tx_list_tail; | |
70 | static struct net_dma_desc_rx *rx_list_head; | |
71 | static struct net_dma_desc_rx *rx_list_tail; | |
72 | static struct net_dma_desc_rx *current_rx_ptr; | |
73 | static struct net_dma_desc_tx *current_tx_ptr; | |
74 | static struct net_dma_desc_tx *tx_desc; | |
75 | static struct net_dma_desc_rx *rx_desc; | |
76 | ||
7ef0a7ee BW |
77 | #if defined(CONFIG_BFIN_MAC_RMII) |
78 | static u16 pin_req[] = P_RMII0; | |
79 | #else | |
80 | static u16 pin_req[] = P_MII0; | |
81 | #endif | |
82 | ||
83 | static void bfin_mac_disable(void); | |
84 | static void bfin_mac_enable(void); | |
4ae5a3ad | 85 | |
e190d6b1 BW |
86 | static void desc_list_free(void) |
87 | { | |
88 | struct net_dma_desc_rx *r; | |
89 | struct net_dma_desc_tx *t; | |
90 | int i; | |
91 | #if !defined(CONFIG_BFIN_MAC_USE_L1) | |
92 | dma_addr_t dma_handle = 0; | |
93 | #endif | |
94 | ||
95 | if (tx_desc) { | |
96 | t = tx_list_head; | |
97 | for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) { | |
98 | if (t) { | |
99 | if (t->skb) { | |
100 | dev_kfree_skb(t->skb); | |
101 | t->skb = NULL; | |
102 | } | |
103 | t = t->next; | |
104 | } | |
105 | } | |
106 | bfin_mac_free(dma_handle, tx_desc); | |
107 | } | |
108 | ||
109 | if (rx_desc) { | |
110 | r = rx_list_head; | |
111 | for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) { | |
112 | if (r) { | |
113 | if (r->skb) { | |
114 | dev_kfree_skb(r->skb); | |
115 | r->skb = NULL; | |
116 | } | |
117 | r = r->next; | |
118 | } | |
119 | } | |
120 | bfin_mac_free(dma_handle, rx_desc); | |
121 | } | |
122 | } | |
123 | ||
124 | static int desc_list_init(void) | |
125 | { | |
126 | int i; | |
127 | struct sk_buff *new_skb; | |
128 | #if !defined(CONFIG_BFIN_MAC_USE_L1) | |
129 | /* | |
130 | * This dma_handle is useless in Blackfin dma_alloc_coherent(). | |
131 | * The real dma handler is the return value of dma_alloc_coherent(). | |
132 | */ | |
133 | dma_addr_t dma_handle; | |
134 | #endif | |
135 | ||
136 | tx_desc = bfin_mac_alloc(&dma_handle, | |
137 | sizeof(struct net_dma_desc_tx) * | |
138 | CONFIG_BFIN_TX_DESC_NUM); | |
139 | if (tx_desc == NULL) | |
140 | goto init_error; | |
141 | ||
142 | rx_desc = bfin_mac_alloc(&dma_handle, | |
143 | sizeof(struct net_dma_desc_rx) * | |
144 | CONFIG_BFIN_RX_DESC_NUM); | |
145 | if (rx_desc == NULL) | |
146 | goto init_error; | |
147 | ||
148 | /* init tx_list */ | |
149 | tx_list_head = tx_list_tail = tx_desc; | |
150 | ||
151 | for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) { | |
152 | struct net_dma_desc_tx *t = tx_desc + i; | |
153 | struct dma_descriptor *a = &(t->desc_a); | |
154 | struct dma_descriptor *b = &(t->desc_b); | |
155 | ||
156 | /* | |
157 | * disable DMA | |
158 | * read from memory WNR = 0 | |
159 | * wordsize is 32 bits | |
160 | * 6 half words is desc size | |
161 | * large desc flow | |
162 | */ | |
163 | a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
164 | a->start_addr = (unsigned long)t->packet; | |
165 | a->x_count = 0; | |
166 | a->next_dma_desc = b; | |
167 | ||
168 | /* | |
169 | * enabled DMA | |
170 | * write to memory WNR = 1 | |
171 | * wordsize is 32 bits | |
172 | * disable interrupt | |
173 | * 6 half words is desc size | |
174 | * large desc flow | |
175 | */ | |
176 | b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
177 | b->start_addr = (unsigned long)(&(t->status)); | |
178 | b->x_count = 0; | |
179 | ||
180 | t->skb = NULL; | |
181 | tx_list_tail->desc_b.next_dma_desc = a; | |
182 | tx_list_tail->next = t; | |
183 | tx_list_tail = t; | |
184 | } | |
185 | tx_list_tail->next = tx_list_head; /* tx_list is a circle */ | |
186 | tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a); | |
187 | current_tx_ptr = tx_list_head; | |
188 | ||
189 | /* init rx_list */ | |
190 | rx_list_head = rx_list_tail = rx_desc; | |
191 | ||
192 | for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) { | |
193 | struct net_dma_desc_rx *r = rx_desc + i; | |
194 | struct dma_descriptor *a = &(r->desc_a); | |
195 | struct dma_descriptor *b = &(r->desc_b); | |
196 | ||
197 | /* allocate a new skb for next time receive */ | |
015dac88 | 198 | new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN); |
e190d6b1 BW |
199 | if (!new_skb) { |
200 | printk(KERN_NOTICE DRV_NAME | |
201 | ": init: low on mem - packet dropped\n"); | |
202 | goto init_error; | |
203 | } | |
015dac88 | 204 | skb_reserve(new_skb, NET_IP_ALIGN); |
e190d6b1 BW |
205 | r->skb = new_skb; |
206 | ||
207 | /* | |
208 | * enabled DMA | |
209 | * write to memory WNR = 1 | |
210 | * wordsize is 32 bits | |
211 | * disable interrupt | |
212 | * 6 half words is desc size | |
213 | * large desc flow | |
214 | */ | |
215 | a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
216 | /* since RXDWA is enabled */ | |
217 | a->start_addr = (unsigned long)new_skb->data - 2; | |
218 | a->x_count = 0; | |
219 | a->next_dma_desc = b; | |
220 | ||
221 | /* | |
222 | * enabled DMA | |
223 | * write to memory WNR = 1 | |
224 | * wordsize is 32 bits | |
225 | * enable interrupt | |
226 | * 6 half words is desc size | |
227 | * large desc flow | |
228 | */ | |
229 | b->config = DMAEN | WNR | WDSIZE_32 | DI_EN | | |
230 | NDSIZE_6 | DMAFLOW_LARGE; | |
231 | b->start_addr = (unsigned long)(&(r->status)); | |
232 | b->x_count = 0; | |
233 | ||
234 | rx_list_tail->desc_b.next_dma_desc = a; | |
235 | rx_list_tail->next = r; | |
236 | rx_list_tail = r; | |
237 | } | |
238 | rx_list_tail->next = rx_list_head; /* rx_list is a circle */ | |
239 | rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a); | |
240 | current_rx_ptr = rx_list_head; | |
241 | ||
242 | return 0; | |
243 | ||
244 | init_error: | |
245 | desc_list_free(); | |
246 | printk(KERN_ERR DRV_NAME ": kmalloc failed\n"); | |
247 | return -ENOMEM; | |
248 | } | |
249 | ||
250 | ||
251 | /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/ | |
252 | ||
4ae5a3ad BW |
253 | /* |
254 | * MII operations | |
255 | */ | |
e190d6b1 | 256 | /* Wait until the previous MDC/MDIO transaction has completed */ |
0ed0563e | 257 | static void bfin_mdio_poll(void) |
e190d6b1 BW |
258 | { |
259 | int timeout_cnt = MAX_TIMEOUT_CNT; | |
260 | ||
261 | /* poll the STABUSY bit */ | |
262 | while ((bfin_read_EMAC_STAADD()) & STABUSY) { | |
6db9e461 | 263 | udelay(1); |
e190d6b1 BW |
264 | if (timeout_cnt-- < 0) { |
265 | printk(KERN_ERR DRV_NAME | |
266 | ": wait MDC/MDIO transaction to complete timeout\n"); | |
267 | break; | |
268 | } | |
269 | } | |
270 | } | |
271 | ||
272 | /* Read an off-chip register in a PHY through the MDC/MDIO port */ | |
0ed0563e | 273 | static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) |
e190d6b1 | 274 | { |
0ed0563e | 275 | bfin_mdio_poll(); |
4ae5a3ad | 276 | |
e190d6b1 | 277 | /* read mode */ |
4ae5a3ad BW |
278 | bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) | |
279 | SET_REGAD((u16) regnum) | | |
e190d6b1 | 280 | STABUSY); |
e190d6b1 | 281 | |
0ed0563e | 282 | bfin_mdio_poll(); |
4ae5a3ad BW |
283 | |
284 | return (int) bfin_read_EMAC_STADAT(); | |
e190d6b1 BW |
285 | } |
286 | ||
287 | /* Write an off-chip register in a PHY through the MDC/MDIO port */ | |
0ed0563e AB |
288 | static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, |
289 | u16 value) | |
e190d6b1 | 290 | { |
0ed0563e | 291 | bfin_mdio_poll(); |
4ae5a3ad BW |
292 | |
293 | bfin_write_EMAC_STADAT((u32) value); | |
e190d6b1 BW |
294 | |
295 | /* write mode */ | |
4ae5a3ad BW |
296 | bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) | |
297 | SET_REGAD((u16) regnum) | | |
e190d6b1 BW |
298 | STAOP | |
299 | STABUSY); | |
300 | ||
0ed0563e | 301 | bfin_mdio_poll(); |
4ae5a3ad BW |
302 | |
303 | return 0; | |
e190d6b1 BW |
304 | } |
305 | ||
0ed0563e | 306 | static int bfin_mdiobus_reset(struct mii_bus *bus) |
e190d6b1 | 307 | { |
4ae5a3ad | 308 | return 0; |
e190d6b1 BW |
309 | } |
310 | ||
7ef0a7ee | 311 | static void bfin_mac_adjust_link(struct net_device *dev) |
e190d6b1 | 312 | { |
7ef0a7ee | 313 | struct bfin_mac_local *lp = netdev_priv(dev); |
4ae5a3ad BW |
314 | struct phy_device *phydev = lp->phydev; |
315 | unsigned long flags; | |
316 | int new_state = 0; | |
317 | ||
318 | spin_lock_irqsave(&lp->lock, flags); | |
319 | if (phydev->link) { | |
320 | /* Now we make sure that we can be in full duplex mode. | |
321 | * If not, we operate in half-duplex mode. */ | |
322 | if (phydev->duplex != lp->old_duplex) { | |
323 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
324 | new_state = 1; | |
325 | ||
326 | if (phydev->duplex) | |
327 | opmode |= FDMODE; | |
328 | else | |
329 | opmode &= ~(FDMODE); | |
330 | ||
331 | bfin_write_EMAC_OPMODE(opmode); | |
332 | lp->old_duplex = phydev->duplex; | |
333 | } | |
e190d6b1 | 334 | |
4ae5a3ad BW |
335 | if (phydev->speed != lp->old_speed) { |
336 | #if defined(CONFIG_BFIN_MAC_RMII) | |
337 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
4ae5a3ad BW |
338 | switch (phydev->speed) { |
339 | case 10: | |
340 | opmode |= RMII_10; | |
341 | break; | |
342 | case 100: | |
343 | opmode &= ~(RMII_10); | |
344 | break; | |
345 | default: | |
346 | printk(KERN_WARNING | |
347 | "%s: Ack! Speed (%d) is not 10/100!\n", | |
348 | DRV_NAME, phydev->speed); | |
349 | break; | |
350 | } | |
351 | bfin_write_EMAC_OPMODE(opmode); | |
4ae5a3ad | 352 | #endif |
e190d6b1 | 353 | |
4ae5a3ad BW |
354 | new_state = 1; |
355 | lp->old_speed = phydev->speed; | |
356 | } | |
e190d6b1 | 357 | |
4ae5a3ad BW |
358 | if (!lp->old_link) { |
359 | new_state = 1; | |
360 | lp->old_link = 1; | |
4ae5a3ad BW |
361 | } |
362 | } else if (lp->old_link) { | |
363 | new_state = 1; | |
364 | lp->old_link = 0; | |
365 | lp->old_speed = 0; | |
366 | lp->old_duplex = -1; | |
e190d6b1 BW |
367 | } |
368 | ||
4ae5a3ad BW |
369 | if (new_state) { |
370 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
371 | phy_print_status(phydev); | |
372 | pr_debug("EMAC_OPMODE = 0x%08x\n", opmode); | |
e190d6b1 | 373 | } |
4ae5a3ad BW |
374 | |
375 | spin_unlock_irqrestore(&lp->lock, flags); | |
e190d6b1 BW |
376 | } |
377 | ||
7cc8f381 BW |
378 | /* MDC = 2.5 MHz */ |
379 | #define MDC_CLK 2500000 | |
380 | ||
4ae5a3ad | 381 | static int mii_probe(struct net_device *dev) |
e190d6b1 | 382 | { |
7ef0a7ee | 383 | struct bfin_mac_local *lp = netdev_priv(dev); |
4ae5a3ad BW |
384 | struct phy_device *phydev = NULL; |
385 | unsigned short sysctl; | |
386 | int i; | |
7cc8f381 | 387 | u32 sclk, mdc_div; |
e190d6b1 | 388 | |
4ae5a3ad | 389 | /* Enable PHY output early */ |
98f672ca MF |
390 | if (!(bfin_read_VR_CTL() & CLKBUFOE)) |
391 | bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); | |
e190d6b1 | 392 | |
7cc8f381 BW |
393 | sclk = get_sclk(); |
394 | mdc_div = ((sclk / MDC_CLK) / 2) - 1; | |
395 | ||
4ae5a3ad | 396 | sysctl = bfin_read_EMAC_SYSCTL(); |
9dc7f30e | 397 | sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div); |
e190d6b1 | 398 | bfin_write_EMAC_SYSCTL(sysctl); |
e190d6b1 | 399 | |
4ae5a3ad BW |
400 | /* search for connect PHY device */ |
401 | for (i = 0; i < PHY_MAX_ADDR; i++) { | |
298cf9be | 402 | struct phy_device *const tmp_phydev = lp->mii_bus->phy_map[i]; |
e190d6b1 | 403 | |
4ae5a3ad BW |
404 | if (!tmp_phydev) |
405 | continue; /* no PHY here... */ | |
e190d6b1 | 406 | |
4ae5a3ad BW |
407 | phydev = tmp_phydev; |
408 | break; /* found it */ | |
409 | } | |
410 | ||
411 | /* now we are supposed to have a proper phydev, to attach to... */ | |
412 | if (!phydev) { | |
413 | printk(KERN_INFO "%s: Don't found any phy device at all\n", | |
414 | dev->name); | |
415 | return -ENODEV; | |
e190d6b1 BW |
416 | } |
417 | ||
418 | #if defined(CONFIG_BFIN_MAC_RMII) | |
c2313557 KS |
419 | phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link, |
420 | 0, PHY_INTERFACE_MODE_RMII); | |
4ae5a3ad | 421 | #else |
c2313557 KS |
422 | phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link, |
423 | 0, PHY_INTERFACE_MODE_MII); | |
e190d6b1 BW |
424 | #endif |
425 | ||
4ae5a3ad BW |
426 | if (IS_ERR(phydev)) { |
427 | printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); | |
428 | return PTR_ERR(phydev); | |
429 | } | |
430 | ||
431 | /* mask with MAC supported features */ | |
432 | phydev->supported &= (SUPPORTED_10baseT_Half | |
433 | | SUPPORTED_10baseT_Full | |
434 | | SUPPORTED_100baseT_Half | |
435 | | SUPPORTED_100baseT_Full | |
436 | | SUPPORTED_Autoneg | |
437 | | SUPPORTED_Pause | SUPPORTED_Asym_Pause | |
438 | | SUPPORTED_MII | |
439 | | SUPPORTED_TP); | |
440 | ||
441 | phydev->advertising = phydev->supported; | |
442 | ||
443 | lp->old_link = 0; | |
444 | lp->old_speed = 0; | |
445 | lp->old_duplex = -1; | |
446 | lp->phydev = phydev; | |
447 | ||
448 | printk(KERN_INFO "%s: attached PHY driver [%s] " | |
7cc8f381 BW |
449 | "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)" |
450 | "@sclk=%dMHz)\n", | |
c2313557 | 451 | DRV_NAME, phydev->drv->name, dev_name(&phydev->dev), phydev->irq, |
7cc8f381 | 452 | MDC_CLK, mdc_div, sclk/1000000); |
4ae5a3ad BW |
453 | |
454 | return 0; | |
455 | } | |
456 | ||
679dce39 BW |
457 | /* |
458 | * Ethtool support | |
459 | */ | |
460 | ||
461 | static int | |
462 | bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
463 | { | |
464 | struct bfin_mac_local *lp = netdev_priv(dev); | |
465 | ||
466 | if (lp->phydev) | |
467 | return phy_ethtool_gset(lp->phydev, cmd); | |
468 | ||
469 | return -EINVAL; | |
470 | } | |
471 | ||
472 | static int | |
473 | bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
474 | { | |
475 | struct bfin_mac_local *lp = netdev_priv(dev); | |
476 | ||
477 | if (!capable(CAP_NET_ADMIN)) | |
478 | return -EPERM; | |
479 | ||
480 | if (lp->phydev) | |
481 | return phy_ethtool_sset(lp->phydev, cmd); | |
482 | ||
483 | return -EINVAL; | |
484 | } | |
485 | ||
486 | static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev, | |
487 | struct ethtool_drvinfo *info) | |
488 | { | |
489 | strcpy(info->driver, DRV_NAME); | |
490 | strcpy(info->version, DRV_VERSION); | |
491 | strcpy(info->fw_version, "N/A"); | |
c2313557 | 492 | strcpy(info->bus_info, dev_name(&dev->dev)); |
679dce39 BW |
493 | } |
494 | ||
0fc0b732 | 495 | static const struct ethtool_ops bfin_mac_ethtool_ops = { |
679dce39 BW |
496 | .get_settings = bfin_mac_ethtool_getsettings, |
497 | .set_settings = bfin_mac_ethtool_setsettings, | |
498 | .get_link = ethtool_op_get_link, | |
499 | .get_drvinfo = bfin_mac_ethtool_getdrvinfo, | |
500 | }; | |
501 | ||
4ae5a3ad BW |
502 | /**************************************************************************/ |
503 | void setup_system_regs(struct net_device *dev) | |
504 | { | |
505 | unsigned short sysctl; | |
506 | ||
507 | /* | |
508 | * Odd word alignment for Receive Frame DMA word | |
509 | * Configure checksum support and rcve frame word alignment | |
510 | */ | |
511 | sysctl = bfin_read_EMAC_SYSCTL(); | |
512 | #if defined(BFIN_MAC_CSUM_OFFLOAD) | |
513 | sysctl |= RXDWA | RXCKS; | |
514 | #else | |
515 | sysctl |= RXDWA; | |
516 | #endif | |
517 | bfin_write_EMAC_SYSCTL(sysctl); | |
e190d6b1 BW |
518 | |
519 | bfin_write_EMAC_MMC_CTL(RSTC | CROLL); | |
520 | ||
521 | /* Initialize the TX DMA channel registers */ | |
522 | bfin_write_DMA2_X_COUNT(0); | |
523 | bfin_write_DMA2_X_MODIFY(4); | |
524 | bfin_write_DMA2_Y_COUNT(0); | |
525 | bfin_write_DMA2_Y_MODIFY(0); | |
526 | ||
527 | /* Initialize the RX DMA channel registers */ | |
528 | bfin_write_DMA1_X_COUNT(0); | |
529 | bfin_write_DMA1_X_MODIFY(4); | |
530 | bfin_write_DMA1_Y_COUNT(0); | |
531 | bfin_write_DMA1_Y_MODIFY(0); | |
532 | } | |
533 | ||
73f83182 | 534 | static void setup_mac_addr(u8 *mac_addr) |
e190d6b1 BW |
535 | { |
536 | u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]); | |
537 | u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]); | |
538 | ||
539 | /* this depends on a little-endian machine */ | |
540 | bfin_write_EMAC_ADDRLO(addr_low); | |
541 | bfin_write_EMAC_ADDRHI(addr_hi); | |
542 | } | |
543 | ||
7ef0a7ee | 544 | static int bfin_mac_set_mac_address(struct net_device *dev, void *p) |
73f83182 AL |
545 | { |
546 | struct sockaddr *addr = p; | |
547 | if (netif_running(dev)) | |
548 | return -EBUSY; | |
549 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
550 | setup_mac_addr(dev->dev_addr); | |
551 | return 0; | |
552 | } | |
553 | ||
e190d6b1 BW |
554 | static void adjust_tx_list(void) |
555 | { | |
556 | int timeout_cnt = MAX_TIMEOUT_CNT; | |
557 | ||
8e95a202 JP |
558 | if (tx_list_head->status.status_word != 0 && |
559 | current_tx_ptr != tx_list_head) { | |
e190d6b1 BW |
560 | goto adjust_head; /* released something, just return; */ |
561 | } | |
562 | ||
563 | /* | |
564 | * if nothing released, check wait condition | |
565 | * current's next can not be the head, | |
566 | * otherwise the dma will not stop as we want | |
567 | */ | |
568 | if (current_tx_ptr->next->next == tx_list_head) { | |
569 | while (tx_list_head->status.status_word == 0) { | |
015dac88 | 570 | udelay(10); |
8e95a202 JP |
571 | if (tx_list_head->status.status_word != 0 || |
572 | !(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)) { | |
e190d6b1 BW |
573 | goto adjust_head; |
574 | } | |
575 | if (timeout_cnt-- < 0) { | |
576 | printk(KERN_ERR DRV_NAME | |
577 | ": wait for adjust tx list head timeout\n"); | |
578 | break; | |
579 | } | |
580 | } | |
581 | if (tx_list_head->status.status_word != 0) { | |
582 | goto adjust_head; | |
583 | } | |
584 | } | |
585 | ||
586 | return; | |
587 | ||
588 | adjust_head: | |
589 | do { | |
590 | tx_list_head->desc_a.config &= ~DMAEN; | |
591 | tx_list_head->status.status_word = 0; | |
592 | if (tx_list_head->skb) { | |
593 | dev_kfree_skb(tx_list_head->skb); | |
594 | tx_list_head->skb = NULL; | |
595 | } else { | |
596 | printk(KERN_ERR DRV_NAME | |
597 | ": no sk_buff in a transmitted frame!\n"); | |
598 | } | |
599 | tx_list_head = tx_list_head->next; | |
8e95a202 JP |
600 | } while (tx_list_head->status.status_word != 0 && |
601 | current_tx_ptr != tx_list_head); | |
e190d6b1 BW |
602 | return; |
603 | ||
604 | } | |
605 | ||
7ef0a7ee | 606 | static int bfin_mac_hard_start_xmit(struct sk_buff *skb, |
e190d6b1 BW |
607 | struct net_device *dev) |
608 | { | |
a50c0c05 | 609 | u16 *data; |
015dac88 | 610 | u32 data_align = (unsigned long)(skb->data) & 0x3; |
e190d6b1 BW |
611 | current_tx_ptr->skb = skb; |
612 | ||
015dac88 MH |
613 | if (data_align == 0x2) { |
614 | /* move skb->data to current_tx_ptr payload */ | |
615 | data = (u16 *)(skb->data) - 1; | |
616 | *data = (u16)(skb->len); | |
617 | current_tx_ptr->desc_a.start_addr = (u32)data; | |
618 | /* this is important! */ | |
619 | blackfin_dcache_flush_range((u32)data, | |
620 | (u32)((u8 *)data + skb->len + 4)); | |
e190d6b1 | 621 | } else { |
015dac88 MH |
622 | *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len); |
623 | memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data, | |
624 | skb->len); | |
625 | current_tx_ptr->desc_a.start_addr = | |
626 | (u32)current_tx_ptr->packet; | |
627 | if (current_tx_ptr->status.status_word != 0) | |
628 | current_tx_ptr->status.status_word = 0; | |
629 | blackfin_dcache_flush_range( | |
630 | (u32)current_tx_ptr->packet, | |
631 | (u32)(current_tx_ptr->packet + skb->len + 2)); | |
e190d6b1 BW |
632 | } |
633 | ||
805a8ab3 SZ |
634 | /* make sure the internal data buffers in the core are drained |
635 | * so that the DMA descriptors are completely written when the | |
636 | * DMA engine goes to fetch them below | |
637 | */ | |
638 | SSYNC(); | |
639 | ||
e190d6b1 BW |
640 | /* enable this packet's dma */ |
641 | current_tx_ptr->desc_a.config |= DMAEN; | |
642 | ||
643 | /* tx dma is running, just return */ | |
015dac88 | 644 | if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN) |
e190d6b1 BW |
645 | goto out; |
646 | ||
647 | /* tx dma is not running */ | |
648 | bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a)); | |
649 | /* dma enabled, read from memory, size is 6 */ | |
650 | bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config); | |
651 | /* Turn on the EMAC tx */ | |
652 | bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE); | |
653 | ||
654 | out: | |
655 | adjust_tx_list(); | |
656 | current_tx_ptr = current_tx_ptr->next; | |
09f75cd7 JG |
657 | dev->stats.tx_packets++; |
658 | dev->stats.tx_bytes += (skb->len); | |
6ed10654 | 659 | return NETDEV_TX_OK; |
e190d6b1 BW |
660 | } |
661 | ||
7ef0a7ee | 662 | static void bfin_mac_rx(struct net_device *dev) |
e190d6b1 BW |
663 | { |
664 | struct sk_buff *skb, *new_skb; | |
e190d6b1 BW |
665 | unsigned short len; |
666 | ||
667 | /* allocate a new skb for next time receive */ | |
668 | skb = current_rx_ptr->skb; | |
015dac88 | 669 | new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN); |
e190d6b1 BW |
670 | if (!new_skb) { |
671 | printk(KERN_NOTICE DRV_NAME | |
672 | ": rx: low on mem - packet dropped\n"); | |
09f75cd7 | 673 | dev->stats.rx_dropped++; |
e190d6b1 BW |
674 | goto out; |
675 | } | |
676 | /* reserve 2 bytes for RXDWA padding */ | |
015dac88 | 677 | skb_reserve(new_skb, NET_IP_ALIGN); |
e190d6b1 BW |
678 | current_rx_ptr->skb = new_skb; |
679 | current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2; | |
680 | ||
6e01d1a4 AD |
681 | /* Invidate the data cache of skb->data range when it is write back |
682 | * cache. It will prevent overwritting the new data from DMA | |
683 | */ | |
684 | blackfin_dcache_invalidate_range((unsigned long)new_skb->head, | |
685 | (unsigned long)new_skb->end); | |
686 | ||
e190d6b1 BW |
687 | len = (unsigned short)((current_rx_ptr->status.status_word) & RX_FRLEN); |
688 | skb_put(skb, len); | |
689 | blackfin_dcache_invalidate_range((unsigned long)skb->head, | |
690 | (unsigned long)skb->tail); | |
691 | ||
e190d6b1 BW |
692 | skb->protocol = eth_type_trans(skb, dev); |
693 | #if defined(BFIN_MAC_CSUM_OFFLOAD) | |
694 | skb->csum = current_rx_ptr->status.ip_payload_csum; | |
00ff49a9 | 695 | skb->ip_summed = CHECKSUM_COMPLETE; |
e190d6b1 BW |
696 | #endif |
697 | ||
698 | netif_rx(skb); | |
09f75cd7 JG |
699 | dev->stats.rx_packets++; |
700 | dev->stats.rx_bytes += len; | |
e190d6b1 BW |
701 | current_rx_ptr->status.status_word = 0x00000000; |
702 | current_rx_ptr = current_rx_ptr->next; | |
703 | ||
704 | out: | |
705 | return; | |
706 | } | |
707 | ||
708 | /* interrupt routine to handle rx and error signal */ | |
7ef0a7ee | 709 | static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id) |
e190d6b1 BW |
710 | { |
711 | struct net_device *dev = dev_id; | |
712 | int number = 0; | |
713 | ||
714 | get_one_packet: | |
715 | if (current_rx_ptr->status.status_word == 0) { | |
716 | /* no more new packet received */ | |
717 | if (number == 0) { | |
718 | if (current_rx_ptr->next->status.status_word != 0) { | |
719 | current_rx_ptr = current_rx_ptr->next; | |
720 | goto real_rx; | |
721 | } | |
722 | } | |
723 | bfin_write_DMA1_IRQ_STATUS(bfin_read_DMA1_IRQ_STATUS() | | |
724 | DMA_DONE | DMA_ERR); | |
725 | return IRQ_HANDLED; | |
726 | } | |
727 | ||
728 | real_rx: | |
7ef0a7ee | 729 | bfin_mac_rx(dev); |
e190d6b1 BW |
730 | number++; |
731 | goto get_one_packet; | |
732 | } | |
733 | ||
734 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
7ef0a7ee | 735 | static void bfin_mac_poll(struct net_device *dev) |
e190d6b1 BW |
736 | { |
737 | disable_irq(IRQ_MAC_RX); | |
7ef0a7ee | 738 | bfin_mac_interrupt(IRQ_MAC_RX, dev); |
e190d6b1 BW |
739 | enable_irq(IRQ_MAC_RX); |
740 | } | |
741 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
742 | ||
7ef0a7ee | 743 | static void bfin_mac_disable(void) |
e190d6b1 BW |
744 | { |
745 | unsigned int opmode; | |
746 | ||
747 | opmode = bfin_read_EMAC_OPMODE(); | |
748 | opmode &= (~RE); | |
749 | opmode &= (~TE); | |
750 | /* Turn off the EMAC */ | |
751 | bfin_write_EMAC_OPMODE(opmode); | |
752 | } | |
753 | ||
754 | /* | |
755 | * Enable Interrupts, Receive, and Transmit | |
756 | */ | |
7ef0a7ee | 757 | static void bfin_mac_enable(void) |
e190d6b1 BW |
758 | { |
759 | u32 opmode; | |
760 | ||
b39d66a8 | 761 | pr_debug("%s: %s\n", DRV_NAME, __func__); |
e190d6b1 BW |
762 | |
763 | /* Set RX DMA */ | |
764 | bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a)); | |
765 | bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config); | |
766 | ||
767 | /* Wait MII done */ | |
0ed0563e | 768 | bfin_mdio_poll(); |
e190d6b1 BW |
769 | |
770 | /* We enable only RX here */ | |
771 | /* ASTP : Enable Automatic Pad Stripping | |
772 | PR : Promiscuous Mode for test | |
773 | PSF : Receive frames with total length less than 64 bytes. | |
774 | FDMODE : Full Duplex Mode | |
775 | LB : Internal Loopback for test | |
776 | RE : Receiver Enable */ | |
777 | opmode = bfin_read_EMAC_OPMODE(); | |
778 | if (opmode & FDMODE) | |
779 | opmode |= PSF; | |
780 | else | |
781 | opmode |= DRO | DC | PSF; | |
782 | opmode |= RE; | |
783 | ||
784 | #if defined(CONFIG_BFIN_MAC_RMII) | |
785 | opmode |= RMII; /* For Now only 100MBit are supported */ | |
6893ff1c | 786 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) && CONFIG_BF_REV_0_2 |
e190d6b1 BW |
787 | opmode |= TE; |
788 | #endif | |
789 | #endif | |
790 | /* Turn on the EMAC rx */ | |
791 | bfin_write_EMAC_OPMODE(opmode); | |
e190d6b1 BW |
792 | } |
793 | ||
794 | /* Our watchdog timed out. Called by the networking layer */ | |
7ef0a7ee | 795 | static void bfin_mac_timeout(struct net_device *dev) |
e190d6b1 | 796 | { |
b39d66a8 | 797 | pr_debug("%s: %s\n", dev->name, __func__); |
e190d6b1 | 798 | |
7ef0a7ee | 799 | bfin_mac_disable(); |
e190d6b1 BW |
800 | |
801 | /* reset tx queue */ | |
802 | tx_list_tail = tx_list_head->next; | |
803 | ||
7ef0a7ee | 804 | bfin_mac_enable(); |
e190d6b1 BW |
805 | |
806 | /* We can accept TX packets again */ | |
1ae5dc34 | 807 | dev->trans_start = jiffies; /* prevent tx timeout */ |
e190d6b1 BW |
808 | netif_wake_queue(dev); |
809 | } | |
810 | ||
7ef0a7ee | 811 | static void bfin_mac_multicast_hash(struct net_device *dev) |
775919bc AW |
812 | { |
813 | u32 emac_hashhi, emac_hashlo; | |
22bedad3 | 814 | struct netdev_hw_addr *ha; |
775919bc | 815 | char *addrs; |
775919bc AW |
816 | u32 crc; |
817 | ||
818 | emac_hashhi = emac_hashlo = 0; | |
819 | ||
22bedad3 JP |
820 | netdev_for_each_mc_addr(ha, dev) { |
821 | addrs = ha->addr; | |
775919bc AW |
822 | |
823 | /* skip non-multicast addresses */ | |
824 | if (!(*addrs & 1)) | |
825 | continue; | |
826 | ||
827 | crc = ether_crc(ETH_ALEN, addrs); | |
828 | crc >>= 26; | |
829 | ||
830 | if (crc & 0x20) | |
831 | emac_hashhi |= 1 << (crc & 0x1f); | |
832 | else | |
833 | emac_hashlo |= 1 << (crc & 0x1f); | |
834 | } | |
835 | ||
836 | bfin_write_EMAC_HASHHI(emac_hashhi); | |
837 | bfin_write_EMAC_HASHLO(emac_hashlo); | |
838 | ||
839 | return; | |
840 | } | |
841 | ||
e190d6b1 BW |
842 | /* |
843 | * This routine will, depending on the values passed to it, | |
844 | * either make it accept multicast packets, go into | |
845 | * promiscuous mode (for TCPDUMP and cousins) or accept | |
846 | * a select set of multicast packets | |
847 | */ | |
7ef0a7ee | 848 | static void bfin_mac_set_multicast_list(struct net_device *dev) |
e190d6b1 BW |
849 | { |
850 | u32 sysctl; | |
851 | ||
852 | if (dev->flags & IFF_PROMISC) { | |
853 | printk(KERN_INFO "%s: set to promisc mode\n", dev->name); | |
854 | sysctl = bfin_read_EMAC_OPMODE(); | |
855 | sysctl |= RAF; | |
856 | bfin_write_EMAC_OPMODE(sysctl); | |
775919bc | 857 | } else if (dev->flags & IFF_ALLMULTI) { |
e190d6b1 BW |
858 | /* accept all multicast */ |
859 | sysctl = bfin_read_EMAC_OPMODE(); | |
860 | sysctl |= PAM; | |
861 | bfin_write_EMAC_OPMODE(sysctl); | |
4cd24eaf | 862 | } else if (!netdev_mc_empty(dev)) { |
775919bc AW |
863 | /* set up multicast hash table */ |
864 | sysctl = bfin_read_EMAC_OPMODE(); | |
865 | sysctl |= HM; | |
866 | bfin_write_EMAC_OPMODE(sysctl); | |
7ef0a7ee | 867 | bfin_mac_multicast_hash(dev); |
e190d6b1 BW |
868 | } else { |
869 | /* clear promisc or multicast mode */ | |
870 | sysctl = bfin_read_EMAC_OPMODE(); | |
871 | sysctl &= ~(RAF | PAM); | |
872 | bfin_write_EMAC_OPMODE(sysctl); | |
873 | } | |
874 | } | |
875 | ||
876 | /* | |
877 | * this puts the device in an inactive state | |
878 | */ | |
7ef0a7ee | 879 | static void bfin_mac_shutdown(struct net_device *dev) |
e190d6b1 BW |
880 | { |
881 | /* Turn off the EMAC */ | |
882 | bfin_write_EMAC_OPMODE(0x00000000); | |
883 | /* Turn off the EMAC RX DMA */ | |
884 | bfin_write_DMA1_CONFIG(0x0000); | |
885 | bfin_write_DMA2_CONFIG(0x0000); | |
886 | } | |
887 | ||
888 | /* | |
889 | * Open and Initialize the interface | |
890 | * | |
891 | * Set up everything, reset the card, etc.. | |
892 | */ | |
7ef0a7ee | 893 | static int bfin_mac_open(struct net_device *dev) |
e190d6b1 | 894 | { |
7ef0a7ee | 895 | struct bfin_mac_local *lp = netdev_priv(dev); |
4af4b840 | 896 | int retval; |
b39d66a8 | 897 | pr_debug("%s: %s\n", dev->name, __func__); |
e190d6b1 BW |
898 | |
899 | /* | |
900 | * Check that the address is valid. If its not, refuse | |
901 | * to bring the device up. The user must specify an | |
902 | * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx | |
903 | */ | |
904 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
905 | printk(KERN_WARNING DRV_NAME ": no valid ethernet hw addr\n"); | |
906 | return -EINVAL; | |
907 | } | |
908 | ||
909 | /* initial rx and tx list */ | |
4af4b840 MH |
910 | retval = desc_list_init(); |
911 | ||
912 | if (retval) | |
913 | return retval; | |
e190d6b1 | 914 | |
4ae5a3ad | 915 | phy_start(lp->phydev); |
136492b2 | 916 | phy_write(lp->phydev, MII_BMCR, BMCR_RESET); |
e190d6b1 | 917 | setup_system_regs(dev); |
ee02fee8 | 918 | setup_mac_addr(dev->dev_addr); |
7ef0a7ee BW |
919 | bfin_mac_disable(); |
920 | bfin_mac_enable(); | |
e190d6b1 BW |
921 | pr_debug("hardware init finished\n"); |
922 | netif_start_queue(dev); | |
923 | netif_carrier_on(dev); | |
924 | ||
925 | return 0; | |
926 | } | |
927 | ||
928 | /* | |
e190d6b1 BW |
929 | * this makes the board clean up everything that it can |
930 | * and not talk to the outside world. Caused by | |
931 | * an 'ifconfig ethX down' | |
932 | */ | |
7ef0a7ee | 933 | static int bfin_mac_close(struct net_device *dev) |
e190d6b1 | 934 | { |
7ef0a7ee | 935 | struct bfin_mac_local *lp = netdev_priv(dev); |
b39d66a8 | 936 | pr_debug("%s: %s\n", dev->name, __func__); |
e190d6b1 BW |
937 | |
938 | netif_stop_queue(dev); | |
939 | netif_carrier_off(dev); | |
940 | ||
4ae5a3ad | 941 | phy_stop(lp->phydev); |
136492b2 | 942 | phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN); |
4ae5a3ad | 943 | |
e190d6b1 | 944 | /* clear everything */ |
7ef0a7ee | 945 | bfin_mac_shutdown(dev); |
e190d6b1 BW |
946 | |
947 | /* free the rx/tx buffers */ | |
948 | desc_list_free(); | |
949 | ||
950 | return 0; | |
951 | } | |
952 | ||
b63dc8fe MF |
953 | static const struct net_device_ops bfin_mac_netdev_ops = { |
954 | .ndo_open = bfin_mac_open, | |
955 | .ndo_stop = bfin_mac_close, | |
956 | .ndo_start_xmit = bfin_mac_hard_start_xmit, | |
957 | .ndo_set_mac_address = bfin_mac_set_mac_address, | |
958 | .ndo_tx_timeout = bfin_mac_timeout, | |
959 | .ndo_set_multicast_list = bfin_mac_set_multicast_list, | |
960 | .ndo_validate_addr = eth_validate_addr, | |
961 | .ndo_change_mtu = eth_change_mtu, | |
962 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
963 | .ndo_poll_controller = bfin_mac_poll, | |
964 | #endif | |
965 | }; | |
966 | ||
d7b843d3 | 967 | static int __devinit bfin_mac_probe(struct platform_device *pdev) |
e190d6b1 | 968 | { |
7ef0a7ee BW |
969 | struct net_device *ndev; |
970 | struct bfin_mac_local *lp; | |
080c8255 GY |
971 | struct platform_device *pd; |
972 | int rc; | |
7ef0a7ee BW |
973 | |
974 | ndev = alloc_etherdev(sizeof(struct bfin_mac_local)); | |
975 | if (!ndev) { | |
976 | dev_err(&pdev->dev, "Cannot allocate net device!\n"); | |
977 | return -ENOMEM; | |
978 | } | |
979 | ||
980 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
981 | platform_set_drvdata(pdev, ndev); | |
982 | lp = netdev_priv(ndev); | |
e190d6b1 BW |
983 | |
984 | /* Grab the MAC address in the MAC */ | |
7ef0a7ee BW |
985 | *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO()); |
986 | *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI()); | |
e190d6b1 BW |
987 | |
988 | /* probe mac */ | |
989 | /*todo: how to proble? which is revision_register */ | |
990 | bfin_write_EMAC_ADDRLO(0x12345678); | |
991 | if (bfin_read_EMAC_ADDRLO() != 0x12345678) { | |
7ef0a7ee BW |
992 | dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n"); |
993 | rc = -ENODEV; | |
994 | goto out_err_probe_mac; | |
e190d6b1 BW |
995 | } |
996 | ||
e190d6b1 | 997 | |
7ef0a7ee BW |
998 | /* |
999 | * Is it valid? (Did bootloader initialize it?) | |
1000 | * Grab the MAC from the board somehow | |
1001 | * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c | |
1002 | */ | |
1003 | if (!is_valid_ether_addr(ndev->dev_addr)) | |
1004 | bfin_get_ether_addr(ndev->dev_addr); | |
1005 | ||
e190d6b1 | 1006 | /* If still not valid, get a random one */ |
7ef0a7ee BW |
1007 | if (!is_valid_ether_addr(ndev->dev_addr)) |
1008 | random_ether_addr(ndev->dev_addr); | |
e190d6b1 | 1009 | |
7ef0a7ee | 1010 | setup_mac_addr(ndev->dev_addr); |
e190d6b1 | 1011 | |
080c8255 GY |
1012 | if (!pdev->dev.platform_data) { |
1013 | dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n"); | |
1014 | rc = -ENODEV; | |
1015 | goto out_err_probe_mac; | |
7ef0a7ee | 1016 | } |
080c8255 GY |
1017 | pd = pdev->dev.platform_data; |
1018 | lp->mii_bus = platform_get_drvdata(pd); | |
1019 | lp->mii_bus->priv = ndev; | |
4ae5a3ad | 1020 | |
7ef0a7ee BW |
1021 | rc = mii_probe(ndev); |
1022 | if (rc) { | |
1023 | dev_err(&pdev->dev, "MII Probe failed!\n"); | |
1024 | goto out_err_mii_probe; | |
1025 | } | |
4ae5a3ad | 1026 | |
e190d6b1 | 1027 | /* Fill in the fields of the device structure with ethernet values. */ |
7ef0a7ee BW |
1028 | ether_setup(ndev); |
1029 | ||
149da651 | 1030 | ndev->netdev_ops = &bfin_mac_netdev_ops; |
679dce39 | 1031 | ndev->ethtool_ops = &bfin_mac_ethtool_ops; |
e190d6b1 | 1032 | |
e190d6b1 BW |
1033 | spin_lock_init(&lp->lock); |
1034 | ||
1035 | /* now, enable interrupts */ | |
1036 | /* register irq handler */ | |
7ef0a7ee | 1037 | rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt, |
91a455f0 | 1038 | IRQF_DISABLED, "EMAC_RX", ndev); |
7ef0a7ee BW |
1039 | if (rc) { |
1040 | dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n"); | |
1041 | rc = -EBUSY; | |
1042 | goto out_err_request_irq; | |
e190d6b1 BW |
1043 | } |
1044 | ||
7ef0a7ee BW |
1045 | rc = register_netdev(ndev); |
1046 | if (rc) { | |
1047 | dev_err(&pdev->dev, "Cannot register net device!\n"); | |
1048 | goto out_err_reg_ndev; | |
e190d6b1 BW |
1049 | } |
1050 | ||
7ef0a7ee BW |
1051 | /* now, print out the card info, in a short format.. */ |
1052 | dev_info(&pdev->dev, "%s, Version %s\n", DRV_DESC, DRV_VERSION); | |
e190d6b1 | 1053 | |
7ef0a7ee | 1054 | return 0; |
e190d6b1 | 1055 | |
7ef0a7ee BW |
1056 | out_err_reg_ndev: |
1057 | free_irq(IRQ_MAC_RX, ndev); | |
1058 | out_err_request_irq: | |
1059 | out_err_mii_probe: | |
298cf9be | 1060 | mdiobus_unregister(lp->mii_bus); |
298cf9be | 1061 | mdiobus_free(lp->mii_bus); |
7ef0a7ee | 1062 | peripheral_free_list(pin_req); |
7ef0a7ee BW |
1063 | out_err_probe_mac: |
1064 | platform_set_drvdata(pdev, NULL); | |
1065 | free_netdev(ndev); | |
e190d6b1 | 1066 | |
7ef0a7ee | 1067 | return rc; |
e190d6b1 BW |
1068 | } |
1069 | ||
d7b843d3 | 1070 | static int __devexit bfin_mac_remove(struct platform_device *pdev) |
e190d6b1 BW |
1071 | { |
1072 | struct net_device *ndev = platform_get_drvdata(pdev); | |
7ef0a7ee | 1073 | struct bfin_mac_local *lp = netdev_priv(ndev); |
e190d6b1 BW |
1074 | |
1075 | platform_set_drvdata(pdev, NULL); | |
1076 | ||
080c8255 | 1077 | lp->mii_bus->priv = NULL; |
7ef0a7ee | 1078 | |
e190d6b1 BW |
1079 | unregister_netdev(ndev); |
1080 | ||
1081 | free_irq(IRQ_MAC_RX, ndev); | |
1082 | ||
1083 | free_netdev(ndev); | |
1084 | ||
7ef0a7ee | 1085 | peripheral_free_list(pin_req); |
e190d6b1 BW |
1086 | |
1087 | return 0; | |
1088 | } | |
1089 | ||
496a34c2 BW |
1090 | #ifdef CONFIG_PM |
1091 | static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg) | |
e190d6b1 | 1092 | { |
496a34c2 BW |
1093 | struct net_device *net_dev = platform_get_drvdata(pdev); |
1094 | ||
1095 | if (netif_running(net_dev)) | |
7ef0a7ee | 1096 | bfin_mac_close(net_dev); |
496a34c2 | 1097 | |
e190d6b1 BW |
1098 | return 0; |
1099 | } | |
1100 | ||
1101 | static int bfin_mac_resume(struct platform_device *pdev) | |
1102 | { | |
496a34c2 BW |
1103 | struct net_device *net_dev = platform_get_drvdata(pdev); |
1104 | ||
1105 | if (netif_running(net_dev)) | |
7ef0a7ee | 1106 | bfin_mac_open(net_dev); |
496a34c2 | 1107 | |
e190d6b1 BW |
1108 | return 0; |
1109 | } | |
496a34c2 BW |
1110 | #else |
1111 | #define bfin_mac_suspend NULL | |
1112 | #define bfin_mac_resume NULL | |
1113 | #endif /* CONFIG_PM */ | |
e190d6b1 | 1114 | |
080c8255 GY |
1115 | static int __devinit bfin_mii_bus_probe(struct platform_device *pdev) |
1116 | { | |
1117 | struct mii_bus *miibus; | |
1118 | int rc, i; | |
1119 | ||
1120 | /* | |
1121 | * We are setting up a network card, | |
1122 | * so set the GPIO pins to Ethernet mode | |
1123 | */ | |
1124 | rc = peripheral_request_list(pin_req, DRV_NAME); | |
1125 | if (rc) { | |
1126 | dev_err(&pdev->dev, "Requesting peripherals failed!\n"); | |
1127 | return rc; | |
1128 | } | |
1129 | ||
1130 | rc = -ENOMEM; | |
1131 | miibus = mdiobus_alloc(); | |
1132 | if (miibus == NULL) | |
1133 | goto out_err_alloc; | |
1134 | miibus->read = bfin_mdiobus_read; | |
1135 | miibus->write = bfin_mdiobus_write; | |
1136 | miibus->reset = bfin_mdiobus_reset; | |
1137 | ||
1138 | miibus->parent = &pdev->dev; | |
1139 | miibus->name = "bfin_mii_bus"; | |
1140 | snprintf(miibus->id, MII_BUS_ID_SIZE, "0"); | |
1141 | miibus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); | |
1142 | if (miibus->irq == NULL) | |
1143 | goto out_err_alloc; | |
1144 | for (i = 0; i < PHY_MAX_ADDR; ++i) | |
1145 | miibus->irq[i] = PHY_POLL; | |
1146 | ||
1147 | rc = mdiobus_register(miibus); | |
1148 | if (rc) { | |
1149 | dev_err(&pdev->dev, "Cannot register MDIO bus!\n"); | |
1150 | goto out_err_mdiobus_register; | |
1151 | } | |
1152 | ||
1153 | platform_set_drvdata(pdev, miibus); | |
1154 | return 0; | |
1155 | ||
1156 | out_err_mdiobus_register: | |
1157 | mdiobus_free(miibus); | |
1158 | out_err_alloc: | |
1159 | peripheral_free_list(pin_req); | |
1160 | ||
1161 | return rc; | |
1162 | } | |
1163 | ||
1164 | static int __devexit bfin_mii_bus_remove(struct platform_device *pdev) | |
1165 | { | |
1166 | struct mii_bus *miibus = platform_get_drvdata(pdev); | |
1167 | platform_set_drvdata(pdev, NULL); | |
1168 | mdiobus_unregister(miibus); | |
1169 | mdiobus_free(miibus); | |
1170 | peripheral_free_list(pin_req); | |
1171 | return 0; | |
1172 | } | |
1173 | ||
1174 | static struct platform_driver bfin_mii_bus_driver = { | |
1175 | .probe = bfin_mii_bus_probe, | |
1176 | .remove = __devexit_p(bfin_mii_bus_remove), | |
1177 | .driver = { | |
1178 | .name = "bfin_mii_bus", | |
1179 | .owner = THIS_MODULE, | |
1180 | }, | |
1181 | }; | |
1182 | ||
e190d6b1 BW |
1183 | static struct platform_driver bfin_mac_driver = { |
1184 | .probe = bfin_mac_probe, | |
d7b843d3 | 1185 | .remove = __devexit_p(bfin_mac_remove), |
e190d6b1 BW |
1186 | .resume = bfin_mac_resume, |
1187 | .suspend = bfin_mac_suspend, | |
1188 | .driver = { | |
72abb461 KS |
1189 | .name = DRV_NAME, |
1190 | .owner = THIS_MODULE, | |
1191 | }, | |
e190d6b1 BW |
1192 | }; |
1193 | ||
1194 | static int __init bfin_mac_init(void) | |
1195 | { | |
080c8255 GY |
1196 | int ret; |
1197 | ret = platform_driver_register(&bfin_mii_bus_driver); | |
1198 | if (!ret) | |
1199 | return platform_driver_register(&bfin_mac_driver); | |
1200 | return -ENODEV; | |
e190d6b1 BW |
1201 | } |
1202 | ||
1203 | module_init(bfin_mac_init); | |
1204 | ||
1205 | static void __exit bfin_mac_cleanup(void) | |
1206 | { | |
1207 | platform_driver_unregister(&bfin_mac_driver); | |
080c8255 | 1208 | platform_driver_unregister(&bfin_mii_bus_driver); |
e190d6b1 BW |
1209 | } |
1210 | ||
1211 | module_exit(bfin_mac_cleanup); | |
72abb461 | 1212 |