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netxen: update module description
[deliverable/linux.git] / drivers / net / bnx2.c
CommitLineData
b6016b76
MC		 1/* bnx2.c: Broadcom NX2 network driver.
2 *
bec92044 3 * Copyright (c) 2004-2010 Broadcom Corporation
b6016b76
MC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
3a9c6a49 12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
f2a4f052
MC		 13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16
17#include <linux/kernel.h>
18#include <linux/timer.h>
19#include <linux/errno.h>
20#include <linux/ioport.h>
21#include <linux/slab.h>
22#include <linux/vmalloc.h>
23#include <linux/interrupt.h>
24#include <linux/pci.h>
25#include <linux/init.h>
26#include <linux/netdevice.h>
27#include <linux/etherdevice.h>
28#include <linux/skbuff.h>
29#include <linux/dma-mapping.h>
1977f032 30#include <linux/bitops.h>
f2a4f052
MC		 31#include <asm/io.h>
32#include <asm/irq.h>
33#include <linux/delay.h>
34#include <asm/byteorder.h>
c86a31f4 35#include <asm/page.h>
f2a4f052
MC		 36#include <linux/time.h>
37#include <linux/ethtool.h>
38#include <linux/mii.h>
f2a4f052 39#include <linux/if_vlan.h>
f2a4f052 40#include <net/ip.h>
de081fa5 41#include <net/tcp.h>
f2a4f052 42#include <net/checksum.h>
f2a4f052
MC		 43#include <linux/workqueue.h>
44#include <linux/crc32.h>
45#include <linux/prefetch.h>
29b12174 46#include <linux/cache.h>
57579f76 47#include <linux/firmware.h>
706bf240 48#include <linux/log2.h>
cd709aa9 49#include <linux/aer.h>
f2a4f052 50
4edd473f
MC		 51#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
52#define BCM_CNIC 1
53#include "cnic_if.h"
54#endif
b6016b76
MC		 55#include "bnx2.h"
56#include "bnx2_fw.h"
b3448b0b 57
b6016b76 58#define DRV_MODULE_NAME "bnx2"
be7ff1af
MC		 59#define DRV_MODULE_VERSION "2.0.20"
60#define DRV_MODULE_RELDATE "Nov 24, 2010"
22fa159d
MC		 61#define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.0.15.fw"
62#define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw"
63#define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.0.17.fw"
64#define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-6.0.17.fw"
65#define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-6.0.17.fw"
b6016b76
MC		 66
67#define RUN_AT(x) (jiffies + (x))
68
69/* Time in jiffies before concluding the transmitter is hung. */
70#define TX_TIMEOUT (5*HZ)
71
fefa8645 72static char version[] __devinitdata =
b6016b76
MC		 73 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
74
75MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
453a9c6e 76MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
b6016b76
MC		 77MODULE_LICENSE("GPL");
78MODULE_VERSION(DRV_MODULE_VERSION);
57579f76
MC		 79MODULE_FIRMWARE(FW_MIPS_FILE_06);
80MODULE_FIRMWARE(FW_RV2P_FILE_06);
81MODULE_FIRMWARE(FW_MIPS_FILE_09);
82MODULE_FIRMWARE(FW_RV2P_FILE_09);
078b0735 83MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
b6016b76
MC		 84
85static int disable_msi = 0;
86
87module_param(disable_msi, int, 0);
88MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
89
90typedef enum {
91 BCM5706 = 0,
92 NC370T,
93 NC370I,
94 BCM5706S,
95 NC370F,
5b0c76ad
MC		 96 BCM5708,
97 BCM5708S,
bac0dff6 98 BCM5709,
27a005b8 99 BCM5709S,
7bb0a04f 100 BCM5716,
1caacecb 101 BCM5716S,
b6016b76
MC		 102} board_t;
103
104/* indexed by board_t, above */
fefa8645 105static struct {
b6016b76
MC		 106 char *name;
107} board_info[] __devinitdata = {
108 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
109 { "HP NC370T Multifunction Gigabit Server Adapter" },
110 { "HP NC370i Multifunction Gigabit Server Adapter" },
111 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
112 { "HP NC370F Multifunction Gigabit Server Adapter" },
5b0c76ad
MC		 113 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
114 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
bac0dff6 115 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
27a005b8 116 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
7bb0a04f 117 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
1caacecb 118 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
b6016b76
MC		 119 };
120
7bb0a04f 121static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
b6016b76
MC		 122 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
123 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
125 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
126 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
5b0c76ad
MC		 128 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
b6016b76
MC		 130 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
131 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
132 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
5b0c76ad
MC		 134 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
bac0dff6
MC		 136 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
27a005b8
MC		 138 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
7bb0a04f
MC		 140 { PCI_VENDOR_ID_BROADCOM, 0x163b,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
1caacecb 142 { PCI_VENDOR_ID_BROADCOM, 0x163c,
1f2435e5 143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
b6016b76
MC		 144 { 0, }
145};
146
0ced9d01 147static const struct flash_spec flash_table[] =
b6016b76 148{
e30372c9
MC		 149#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
150#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
b6016b76 151 /* Slow EEPROM */
37137709 152 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 153 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
b6016b76
MC		 154 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
155 "EEPROM - slow"},
37137709
MC		 156 /* Expansion entry 0001 */
157 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 158 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 159 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
160 "Entry 0001"},
b6016b76
MC		 161 /* Saifun SA25F010 (non-buffered flash) */
162 /* strap, cfg1, & write1 need updates */
37137709 163 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 164 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 165 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
166 "Non-buffered flash (128kB)"},
167 /* Saifun SA25F020 (non-buffered flash) */
168 /* strap, cfg1, & write1 need updates */
37137709 169 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 170 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 171 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
172 "Non-buffered flash (256kB)"},
37137709
MC		 173 /* Expansion entry 0100 */
174 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 175 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 176 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
177 "Entry 0100"},
178 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
6aa20a22 179 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 180 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 181 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
182 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
183 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
184 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 185 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 186 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
187 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
188 /* Saifun SA25F005 (non-buffered flash) */
189 /* strap, cfg1, & write1 need updates */
190 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 191 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 192 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
193 "Non-buffered flash (64kB)"},
194 /* Fast EEPROM */
195 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 196 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
37137709
MC		 197 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
198 "EEPROM - fast"},
199 /* Expansion entry 1001 */
200 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 201 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 202 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
203 "Entry 1001"},
204 /* Expansion entry 1010 */
205 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 206 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 207 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
208 "Entry 1010"},
209 /* ATMEL AT45DB011B (buffered flash) */
210 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 211 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 212 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
213 "Buffered flash (128kB)"},
214 /* Expansion entry 1100 */
215 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 216 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 217 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
218 "Entry 1100"},
219 /* Expansion entry 1101 */
220 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 221 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 222 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
223 "Entry 1101"},
224 /* Ateml Expansion entry 1110 */
225 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 226 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 227 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
228 "Entry 1110 (Atmel)"},
229 /* ATMEL AT45DB021B (buffered flash) */
230 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 231 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 232 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
233 "Buffered flash (256kB)"},
b6016b76
MC		 234};
235
0ced9d01 236static const struct flash_spec flash_5709 = {
e30372c9
MC		 237 .flags = BNX2_NV_BUFFERED,
238 .page_bits = BCM5709_FLASH_PAGE_BITS,
239 .page_size = BCM5709_FLASH_PAGE_SIZE,
240 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
241 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
242 .name = "5709 Buffered flash (256kB)",
243};
244
b6016b76
MC		 245MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
246
4327ba43 247static void bnx2_init_napi(struct bnx2 *bp);
f048fa9c 248static void bnx2_del_napi(struct bnx2 *bp);
4327ba43 249
35e9010b 250static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
e89bbf10 251{
2f8af120 252 u32 diff;
e89bbf10 253
11848b96
MC		 254 /* Tell compiler to fetch tx_prod and tx_cons from memory. */
255 barrier();
faac9c4b
MC		 256
257 /* The ring uses 256 indices for 255 entries, one of them
258 * needs to be skipped.
259 */
35e9010b 260 diff = txr->tx_prod - txr->tx_cons;
faac9c4b
MC		 261 if (unlikely(diff >= TX_DESC_CNT)) {
262 diff &= 0xffff;
263 if (diff == TX_DESC_CNT)
264 diff = MAX_TX_DESC_CNT;
265 }
807540ba 266 return bp->tx_ring_size - diff;
e89bbf10
MC		 267}
268
b6016b76
MC		 269static u32
270bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
271{
1b8227c4
MC		 272 u32 val;
273
274 spin_lock_bh(&bp->indirect_lock);
b6016b76 275 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
1b8227c4
MC		 276 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
277 spin_unlock_bh(&bp->indirect_lock);
278 return val;
b6016b76
MC		 279}
280
281static void
282bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
283{
1b8227c4 284 spin_lock_bh(&bp->indirect_lock);
b6016b76
MC		 285 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
286 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
1b8227c4 287 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 288}
289
2726d6e1
MC		 290static void
291bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
292{
293 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
294}
295
296static u32
297bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
298{
807540ba 299 return bnx2_reg_rd_ind(bp, bp->shmem_base + offset);
2726d6e1
MC		 300}
301
b6016b76
MC		 302static void
303bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
304{
305 offset += cid_addr;
1b8227c4 306 spin_lock_bh(&bp->indirect_lock);
59b47d8a
MC		 307 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
308 int i;
309
310 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
311 REG_WR(bp, BNX2_CTX_CTX_CTRL,
312 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
313 for (i = 0; i < 5; i++) {
59b47d8a
MC		 314 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
315 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
316 break;
317 udelay(5);
318 }
319 } else {
320 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
321 REG_WR(bp, BNX2_CTX_DATA, val);
322 }
1b8227c4 323 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 324}
325
4edd473f
MC		 326#ifdef BCM_CNIC
327static int
328bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
329{
330 struct bnx2 *bp = netdev_priv(dev);
331 struct drv_ctl_io *io = &info->data.io;
332
333 switch (info->cmd) {
334 case DRV_CTL_IO_WR_CMD:
335 bnx2_reg_wr_ind(bp, io->offset, io->data);
336 break;
337 case DRV_CTL_IO_RD_CMD:
338 io->data = bnx2_reg_rd_ind(bp, io->offset);
339 break;
340 case DRV_CTL_CTX_WR_CMD:
341 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
342 break;
343 default:
344 return -EINVAL;
345 }
346 return 0;
347}
348
349static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
350{
351 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
352 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
353 int sb_id;
354
355 if (bp->flags & BNX2_FLAG_USING_MSIX) {
356 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
357 bnapi->cnic_present = 0;
358 sb_id = bp->irq_nvecs;
359 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
360 } else {
361 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
362 bnapi->cnic_tag = bnapi->last_status_idx;
363 bnapi->cnic_present = 1;
364 sb_id = 0;
365 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
366 }
367
368 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
369 cp->irq_arr[0].status_blk = (void *)
370 ((unsigned long) bnapi->status_blk.msi +
371 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
372 cp->irq_arr[0].status_blk_num = sb_id;
373 cp->num_irq = 1;
374}
375
376static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
377 void *data)
378{
379 struct bnx2 *bp = netdev_priv(dev);
380 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
381
382 if (ops == NULL)
383 return -EINVAL;
384
385 if (cp->drv_state & CNIC_DRV_STATE_REGD)
386 return -EBUSY;
387
388 bp->cnic_data = data;
389 rcu_assign_pointer(bp->cnic_ops, ops);
390
391 cp->num_irq = 0;
392 cp->drv_state = CNIC_DRV_STATE_REGD;
393
394 bnx2_setup_cnic_irq_info(bp);
395
396 return 0;
397}
398
399static int bnx2_unregister_cnic(struct net_device *dev)
400{
401 struct bnx2 *bp = netdev_priv(dev);
402 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
403 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
404
c5a88950 405 mutex_lock(&bp->cnic_lock);
4edd473f
MC		 406 cp->drv_state = 0;
407 bnapi->cnic_present = 0;
408 rcu_assign_pointer(bp->cnic_ops, NULL);
c5a88950 409 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 410 synchronize_rcu();
411 return 0;
412}
413
414struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
415{
416 struct bnx2 *bp = netdev_priv(dev);
417 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
418
419 cp->drv_owner = THIS_MODULE;
420 cp->chip_id = bp->chip_id;
421 cp->pdev = bp->pdev;
422 cp->io_base = bp->regview;
423 cp->drv_ctl = bnx2_drv_ctl;
424 cp->drv_register_cnic = bnx2_register_cnic;
425 cp->drv_unregister_cnic = bnx2_unregister_cnic;
426
427 return cp;
428}
429EXPORT_SYMBOL(bnx2_cnic_probe);
430
431static void
432bnx2_cnic_stop(struct bnx2 *bp)
433{
434 struct cnic_ops *c_ops;
435 struct cnic_ctl_info info;
436
c5a88950
MC		 437 mutex_lock(&bp->cnic_lock);
438 c_ops = bp->cnic_ops;
4edd473f
MC		 439 if (c_ops) {
440 info.cmd = CNIC_CTL_STOP_CMD;
441 c_ops->cnic_ctl(bp->cnic_data, &info);
442 }
c5a88950 443 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 444}
445
446static void
447bnx2_cnic_start(struct bnx2 *bp)
448{
449 struct cnic_ops *c_ops;
450 struct cnic_ctl_info info;
451
c5a88950
MC		 452 mutex_lock(&bp->cnic_lock);
453 c_ops = bp->cnic_ops;
4edd473f
MC		 454 if (c_ops) {
455 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
456 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
457
458 bnapi->cnic_tag = bnapi->last_status_idx;
459 }
460 info.cmd = CNIC_CTL_START_CMD;
461 c_ops->cnic_ctl(bp->cnic_data, &info);
462 }
c5a88950 463 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 464}
465
466#else
467
468static void
469bnx2_cnic_stop(struct bnx2 *bp)
470{
471}
472
473static void
474bnx2_cnic_start(struct bnx2 *bp)
475{
476}
477
478#endif
479
b6016b76
MC		 480static int
481bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
482{
483 u32 val1;
484 int i, ret;
485
583c28e5 486 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 487 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
488 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
489
490 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
491 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
492
493 udelay(40);
494 }
495
496 val1 = (bp->phy_addr << 21) | (reg << 16) |
497 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
498 BNX2_EMAC_MDIO_COMM_START_BUSY;
499 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
500
501 for (i = 0; i < 50; i++) {
502 udelay(10);
503
504 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
505 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
506 udelay(5);
507
508 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
509 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
510
511 break;
512 }
513 }
514
515 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
516 *val = 0x0;
517 ret = -EBUSY;
518 }
519 else {
520 *val = val1;
521 ret = 0;
522 }
523
583c28e5 524 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 525 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
526 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
527
528 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
529 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
530
531 udelay(40);
532 }
533
534 return ret;
535}
536
537static int
538bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
539{
540 u32 val1;
541 int i, ret;
542
583c28e5 543 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 544 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
545 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
546
547 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
548 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
549
550 udelay(40);
551 }
552
553 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
554 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
555 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
556 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
6aa20a22 557
b6016b76
MC		 558 for (i = 0; i < 50; i++) {
559 udelay(10);
560
561 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
562 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
563 udelay(5);
564 break;
565 }
566 }
567
568 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
569 ret = -EBUSY;
570 else
571 ret = 0;
572
583c28e5 573 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 574 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
575 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
576
577 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
578 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
579
580 udelay(40);
581 }
582
583 return ret;
584}
585
586static void
587bnx2_disable_int(struct bnx2 *bp)
588{
b4b36042
MC		 589 int i;
590 struct bnx2_napi *bnapi;
591
592 for (i = 0; i < bp->irq_nvecs; i++) {
593 bnapi = &bp->bnx2_napi[i];
594 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
595 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
596 }
b6016b76
MC		 597 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
598}
599
600static void
601bnx2_enable_int(struct bnx2 *bp)
602{
b4b36042
MC		 603 int i;
604 struct bnx2_napi *bnapi;
35efa7c1 605
b4b36042
MC		 606 for (i = 0; i < bp->irq_nvecs; i++) {
607 bnapi = &bp->bnx2_napi[i];
1269a8a6 608
b4b36042
MC		 609 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
610 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
611 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
612 bnapi->last_status_idx);
b6016b76 613
b4b36042
MC		 614 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
615 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
616 bnapi->last_status_idx);
617 }
bf5295bb 618 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 619}
620
621static void
622bnx2_disable_int_sync(struct bnx2 *bp)
623{
b4b36042
MC		 624 int i;
625
b6016b76 626 atomic_inc(&bp->intr_sem);
3767546c
MC		 627 if (!netif_running(bp->dev))
628 return;
629
b6016b76 630 bnx2_disable_int(bp);
b4b36042
MC		 631 for (i = 0; i < bp->irq_nvecs; i++)
632 synchronize_irq(bp->irq_tbl[i].vector);
b6016b76
MC		 633}
634
35efa7c1
MC		 635static void
636bnx2_napi_disable(struct bnx2 *bp)
637{
b4b36042
MC		 638 int i;
639
640 for (i = 0; i < bp->irq_nvecs; i++)
641 napi_disable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 642}
643
644static void
645bnx2_napi_enable(struct bnx2 *bp)
646{
b4b36042
MC		 647 int i;
648
649 for (i = 0; i < bp->irq_nvecs; i++)
650 napi_enable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 651}
652
b6016b76 653static void
212f9934 654bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)
b6016b76 655{
212f9934
MC		 656 if (stop_cnic)
657 bnx2_cnic_stop(bp);
b6016b76 658 if (netif_running(bp->dev)) {
35efa7c1 659 bnx2_napi_disable(bp);
b6016b76 660 netif_tx_disable(bp->dev);
b6016b76 661 }
b7466560 662 bnx2_disable_int_sync(bp);
a0ba6760 663 netif_carrier_off(bp->dev); /* prevent tx timeout */
b6016b76
MC		 664}
665
666static void
212f9934 667bnx2_netif_start(struct bnx2 *bp, bool start_cnic)
b6016b76
MC		 668{
669 if (atomic_dec_and_test(&bp->intr_sem)) {
670 if (netif_running(bp->dev)) {
706bf240 671 netif_tx_wake_all_queues(bp->dev);
a0ba6760
MC		 672 spin_lock_bh(&bp->phy_lock);
673 if (bp->link_up)
674 netif_carrier_on(bp->dev);
675 spin_unlock_bh(&bp->phy_lock);
35efa7c1 676 bnx2_napi_enable(bp);
b6016b76 677 bnx2_enable_int(bp);
212f9934
MC		 678 if (start_cnic)
679 bnx2_cnic_start(bp);
b6016b76
MC		 680 }
681 }
682}
683
35e9010b
MC		 684static void
685bnx2_free_tx_mem(struct bnx2 *bp)
686{
687 int i;
688
689 for (i = 0; i < bp->num_tx_rings; i++) {
690 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
691 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
692
693 if (txr->tx_desc_ring) {
36227e88
SG		 694 dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
695 txr->tx_desc_ring,
696 txr->tx_desc_mapping);
35e9010b
MC		 697 txr->tx_desc_ring = NULL;
698 }
699 kfree(txr->tx_buf_ring);
700 txr->tx_buf_ring = NULL;
701 }
702}
703
bb4f98ab
MC		 704static void
705bnx2_free_rx_mem(struct bnx2 *bp)
706{
707 int i;
708
709 for (i = 0; i < bp->num_rx_rings; i++) {
710 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
711 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
712 int j;
713
714 for (j = 0; j < bp->rx_max_ring; j++) {
715 if (rxr->rx_desc_ring[j])
36227e88
SG		 716 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
717 rxr->rx_desc_ring[j],
718 rxr->rx_desc_mapping[j]);
bb4f98ab
MC		 719 rxr->rx_desc_ring[j] = NULL;
720 }
25b0b999 721 vfree(rxr->rx_buf_ring);
bb4f98ab
MC		 722 rxr->rx_buf_ring = NULL;
723
724 for (j = 0; j < bp->rx_max_pg_ring; j++) {
725 if (rxr->rx_pg_desc_ring[j])
36227e88
SG		 726 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
727 rxr->rx_pg_desc_ring[j],
728 rxr->rx_pg_desc_mapping[j]);
3298a738 729 rxr->rx_pg_desc_ring[j] = NULL;
bb4f98ab 730 }
25b0b999 731 vfree(rxr->rx_pg_ring);
bb4f98ab
MC		 732 rxr->rx_pg_ring = NULL;
733 }
734}
735
35e9010b
MC		 736static int
737bnx2_alloc_tx_mem(struct bnx2 *bp)
738{
739 int i;
740
741 for (i = 0; i < bp->num_tx_rings; i++) {
742 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
743 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
744
745 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
746 if (txr->tx_buf_ring == NULL)
747 return -ENOMEM;
748
749 txr->tx_desc_ring =
36227e88
SG		 750 dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
751 &txr->tx_desc_mapping, GFP_KERNEL);
35e9010b
MC		 752 if (txr->tx_desc_ring == NULL)
753 return -ENOMEM;
754 }
755 return 0;
756}
757
bb4f98ab
MC		 758static int
759bnx2_alloc_rx_mem(struct bnx2 *bp)
760{
761 int i;
762
763 for (i = 0; i < bp->num_rx_rings; i++) {
764 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
765 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
766 int j;
767
768 rxr->rx_buf_ring =
89bf67f1 769 vzalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
bb4f98ab
MC		 770 if (rxr->rx_buf_ring == NULL)
771 return -ENOMEM;
772
bb4f98ab
MC		 773 for (j = 0; j < bp->rx_max_ring; j++) {
774 rxr->rx_desc_ring[j] =
36227e88
SG		 775 dma_alloc_coherent(&bp->pdev->dev,
776 RXBD_RING_SIZE,
777 &rxr->rx_desc_mapping[j],
778 GFP_KERNEL);
bb4f98ab
MC		 779 if (rxr->rx_desc_ring[j] == NULL)
780 return -ENOMEM;
781
782 }
783
784 if (bp->rx_pg_ring_size) {
89bf67f1 785 rxr->rx_pg_ring = vzalloc(SW_RXPG_RING_SIZE *
bb4f98ab
MC		 786 bp->rx_max_pg_ring);
787 if (rxr->rx_pg_ring == NULL)
788 return -ENOMEM;
789
bb4f98ab
MC		 790 }
791
792 for (j = 0; j < bp->rx_max_pg_ring; j++) {
793 rxr->rx_pg_desc_ring[j] =
36227e88
SG		 794 dma_alloc_coherent(&bp->pdev->dev,
795 RXBD_RING_SIZE,
796 &rxr->rx_pg_desc_mapping[j],
797 GFP_KERNEL);
bb4f98ab
MC		 798 if (rxr->rx_pg_desc_ring[j] == NULL)
799 return -ENOMEM;
800
801 }
802 }
803 return 0;
804}
805
b6016b76
MC		 806static void
807bnx2_free_mem(struct bnx2 *bp)
808{
13daffa2 809 int i;
43e80b89 810 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
13daffa2 811
35e9010b 812 bnx2_free_tx_mem(bp);
bb4f98ab 813 bnx2_free_rx_mem(bp);
35e9010b 814
59b47d8a
MC		 815 for (i = 0; i < bp->ctx_pages; i++) {
816 if (bp->ctx_blk[i]) {
36227e88
SG		 817 dma_free_coherent(&bp->pdev->dev, BCM_PAGE_SIZE,
818 bp->ctx_blk[i],
819 bp->ctx_blk_mapping[i]);
59b47d8a
MC		 820 bp->ctx_blk[i] = NULL;
821 }
822 }
43e80b89 823 if (bnapi->status_blk.msi) {
36227e88
SG		 824 dma_free_coherent(&bp->pdev->dev, bp->status_stats_size,
825 bnapi->status_blk.msi,
826 bp->status_blk_mapping);
43e80b89 827 bnapi->status_blk.msi = NULL;
0f31f994 828 bp->stats_blk = NULL;
b6016b76 829 }
b6016b76
MC		 830}
831
832static int
833bnx2_alloc_mem(struct bnx2 *bp)
834{
35e9010b 835 int i, status_blk_size, err;
43e80b89
MC		 836 struct bnx2_napi *bnapi;
837 void *status_blk;
b6016b76 838
0f31f994
MC		 839 /* Combine status and statistics blocks into one allocation. */
840 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
f86e82fb 841 if (bp->flags & BNX2_FLAG_MSIX_CAP)
b4b36042
MC		 842 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
843 BNX2_SBLK_MSIX_ALIGN_SIZE);
0f31f994
MC		 844 bp->status_stats_size = status_blk_size +
845 sizeof(struct statistics_block);
846
36227e88
SG		 847 status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size,
848 &bp->status_blk_mapping, GFP_KERNEL);
43e80b89 849 if (status_blk == NULL)
b6016b76
MC		 850 goto alloc_mem_err;
851
43e80b89 852 memset(status_blk, 0, bp->status_stats_size);
b6016b76 853
43e80b89
MC		 854 bnapi = &bp->bnx2_napi[0];
855 bnapi->status_blk.msi = status_blk;
856 bnapi->hw_tx_cons_ptr =
857 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
858 bnapi->hw_rx_cons_ptr =
859 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
f86e82fb 860 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
379b39a2 861 for (i = 1; i < bp->irq_nvecs; i++) {
43e80b89
MC		 862 struct status_block_msix *sblk;
863
864 bnapi = &bp->bnx2_napi[i];
b4b36042 865
43e80b89
MC		 866 sblk = (void *) (status_blk +
867 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
868 bnapi->status_blk.msix = sblk;
869 bnapi->hw_tx_cons_ptr =
870 &sblk->status_tx_quick_consumer_index;
871 bnapi->hw_rx_cons_ptr =
872 &sblk->status_rx_quick_consumer_index;
b4b36042
MC		 873 bnapi->int_num = i << 24;
874 }
875 }
35efa7c1 876
43e80b89 877 bp->stats_blk = status_blk + status_blk_size;
b6016b76 878
0f31f994 879 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
b6016b76 880
59b47d8a
MC		 881 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
882 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
883 if (bp->ctx_pages == 0)
884 bp->ctx_pages = 1;
885 for (i = 0; i < bp->ctx_pages; i++) {
36227e88 886 bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev,
59b47d8a 887 BCM_PAGE_SIZE,
36227e88
SG		 888 &bp->ctx_blk_mapping[i],
889 GFP_KERNEL);
59b47d8a
MC		 890 if (bp->ctx_blk[i] == NULL)
891 goto alloc_mem_err;
892 }
893 }
35e9010b 894
bb4f98ab
MC		 895 err = bnx2_alloc_rx_mem(bp);
896 if (err)
897 goto alloc_mem_err;
898
35e9010b
MC		 899 err = bnx2_alloc_tx_mem(bp);
900 if (err)
901 goto alloc_mem_err;
902
b6016b76
MC		 903 return 0;
904
905alloc_mem_err:
906 bnx2_free_mem(bp);
907 return -ENOMEM;
908}
909
e3648b3d
MC		 910static void
911bnx2_report_fw_link(struct bnx2 *bp)
912{
913 u32 fw_link_status = 0;
914
583c28e5 915 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 916 return;
917
e3648b3d
MC		 918 if (bp->link_up) {
919 u32 bmsr;
920
921 switch (bp->line_speed) {
922 case SPEED_10:
923 if (bp->duplex == DUPLEX_HALF)
924 fw_link_status = BNX2_LINK_STATUS_10HALF;
925 else
926 fw_link_status = BNX2_LINK_STATUS_10FULL;
927 break;
928 case SPEED_100:
929 if (bp->duplex == DUPLEX_HALF)
930 fw_link_status = BNX2_LINK_STATUS_100HALF;
931 else
932 fw_link_status = BNX2_LINK_STATUS_100FULL;
933 break;
934 case SPEED_1000:
935 if (bp->duplex == DUPLEX_HALF)
936 fw_link_status = BNX2_LINK_STATUS_1000HALF;
937 else
938 fw_link_status = BNX2_LINK_STATUS_1000FULL;
939 break;
940 case SPEED_2500:
941 if (bp->duplex == DUPLEX_HALF)
942 fw_link_status = BNX2_LINK_STATUS_2500HALF;
943 else
944 fw_link_status = BNX2_LINK_STATUS_2500FULL;
945 break;
946 }
947
948 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
949
950 if (bp->autoneg) {
951 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
952
ca58c3af
MC		 953 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
954 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
e3648b3d
MC		 955
956 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
583c28e5 957 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
e3648b3d
MC		 958 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
959 else
960 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
961 }
962 }
963 else
964 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
965
2726d6e1 966 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
e3648b3d
MC		 967}
968
9b1084b8
MC		 969static char *
970bnx2_xceiver_str(struct bnx2 *bp)
971{
807540ba 972 return (bp->phy_port == PORT_FIBRE) ? "SerDes" :
583c28e5 973 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
807540ba 974 "Copper");
9b1084b8
MC		 975}
976
b6016b76
MC		 977static void
978bnx2_report_link(struct bnx2 *bp)
979{
980 if (bp->link_up) {
981 netif_carrier_on(bp->dev);
3a9c6a49
JP		 982 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",
983 bnx2_xceiver_str(bp),
984 bp->line_speed,
985 bp->duplex == DUPLEX_FULL ? "full" : "half");
b6016b76
MC		 986
987 if (bp->flow_ctrl) {
988 if (bp->flow_ctrl & FLOW_CTRL_RX) {
3a9c6a49 989 pr_cont(", receive ");
b6016b76 990 if (bp->flow_ctrl & FLOW_CTRL_TX)
3a9c6a49 991 pr_cont("& transmit ");
b6016b76
MC		 992 }
993 else {
3a9c6a49 994 pr_cont(", transmit ");
b6016b76 995 }
3a9c6a49 996 pr_cont("flow control ON");
b6016b76 997 }
3a9c6a49
JP		 998 pr_cont("\n");
999 } else {
b6016b76 1000 netif_carrier_off(bp->dev);
3a9c6a49
JP		 1001 netdev_err(bp->dev, "NIC %s Link is Down\n",
1002 bnx2_xceiver_str(bp));
b6016b76 1003 }
e3648b3d
MC		 1004
1005 bnx2_report_fw_link(bp);
b6016b76
MC		 1006}
1007
1008static void
1009bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1010{
1011 u32 local_adv, remote_adv;
1012
1013 bp->flow_ctrl = 0;
6aa20a22 1014 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
b6016b76
MC		 1015 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1016
1017 if (bp->duplex == DUPLEX_FULL) {
1018 bp->flow_ctrl = bp->req_flow_ctrl;
1019 }
1020 return;
1021 }
1022
1023 if (bp->duplex != DUPLEX_FULL) {
1024 return;
1025 }
1026
583c28e5 1027 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
5b0c76ad
MC		 1028 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
1029 u32 val;
1030
1031 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1032 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1033 bp->flow_ctrl |= FLOW_CTRL_TX;
1034 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1035 bp->flow_ctrl |= FLOW_CTRL_RX;
1036 return;
1037 }
1038
ca58c3af
MC		 1039 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1040 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76 1041
583c28e5 1042 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1043 u32 new_local_adv = 0;
1044 u32 new_remote_adv = 0;
1045
1046 if (local_adv & ADVERTISE_1000XPAUSE)
1047 new_local_adv |= ADVERTISE_PAUSE_CAP;
1048 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1049 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1050 if (remote_adv & ADVERTISE_1000XPAUSE)
1051 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1052 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1053 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1054
1055 local_adv = new_local_adv;
1056 remote_adv = new_remote_adv;
1057 }
1058
1059 /* See Table 28B-3 of 802.3ab-1999 spec. */
1060 if (local_adv & ADVERTISE_PAUSE_CAP) {
1061 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1062 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1063 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1064 }
1065 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1066 bp->flow_ctrl = FLOW_CTRL_RX;
1067 }
1068 }
1069 else {
1070 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1071 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1072 }
1073 }
1074 }
1075 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1076 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1077 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1078
1079 bp->flow_ctrl = FLOW_CTRL_TX;
1080 }
1081 }
1082}
1083
27a005b8
MC		 1084static int
1085bnx2_5709s_linkup(struct bnx2 *bp)
1086{
1087 u32 val, speed;
1088
1089 bp->link_up = 1;
1090
1091 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1092 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1093 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1094
1095 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1096 bp->line_speed = bp->req_line_speed;
1097 bp->duplex = bp->req_duplex;
1098 return 0;
1099 }
1100 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1101 switch (speed) {
1102 case MII_BNX2_GP_TOP_AN_SPEED_10:
1103 bp->line_speed = SPEED_10;
1104 break;
1105 case MII_BNX2_GP_TOP_AN_SPEED_100:
1106 bp->line_speed = SPEED_100;
1107 break;
1108 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1109 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1110 bp->line_speed = SPEED_1000;
1111 break;
1112 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1113 bp->line_speed = SPEED_2500;
1114 break;
1115 }
1116 if (val & MII_BNX2_GP_TOP_AN_FD)
1117 bp->duplex = DUPLEX_FULL;
1118 else
1119 bp->duplex = DUPLEX_HALF;
1120 return 0;
1121}
1122
b6016b76 1123static int
5b0c76ad
MC		 1124bnx2_5708s_linkup(struct bnx2 *bp)
1125{
1126 u32 val;
1127
1128 bp->link_up = 1;
1129 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1130 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1131 case BCM5708S_1000X_STAT1_SPEED_10:
1132 bp->line_speed = SPEED_10;
1133 break;
1134 case BCM5708S_1000X_STAT1_SPEED_100:
1135 bp->line_speed = SPEED_100;
1136 break;
1137 case BCM5708S_1000X_STAT1_SPEED_1G:
1138 bp->line_speed = SPEED_1000;
1139 break;
1140 case BCM5708S_1000X_STAT1_SPEED_2G5:
1141 bp->line_speed = SPEED_2500;
1142 break;
1143 }
1144 if (val & BCM5708S_1000X_STAT1_FD)
1145 bp->duplex = DUPLEX_FULL;
1146 else
1147 bp->duplex = DUPLEX_HALF;
1148
1149 return 0;
1150}
1151
1152static int
1153bnx2_5706s_linkup(struct bnx2 *bp)
b6016b76
MC		 1154{
1155 u32 bmcr, local_adv, remote_adv, common;
1156
1157 bp->link_up = 1;
1158 bp->line_speed = SPEED_1000;
1159
ca58c3af 1160 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1161 if (bmcr & BMCR_FULLDPLX) {
1162 bp->duplex = DUPLEX_FULL;
1163 }
1164 else {
1165 bp->duplex = DUPLEX_HALF;
1166 }
1167
1168 if (!(bmcr & BMCR_ANENABLE)) {
1169 return 0;
1170 }
1171
ca58c3af
MC		 1172 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1173 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 1174
1175 common = local_adv & remote_adv;
1176 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1177
1178 if (common & ADVERTISE_1000XFULL) {
1179 bp->duplex = DUPLEX_FULL;
1180 }
1181 else {
1182 bp->duplex = DUPLEX_HALF;
1183 }
1184 }
1185
1186 return 0;
1187}
1188
1189static int
1190bnx2_copper_linkup(struct bnx2 *bp)
1191{
1192 u32 bmcr;
1193
ca58c3af 1194 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1195 if (bmcr & BMCR_ANENABLE) {
1196 u32 local_adv, remote_adv, common;
1197
1198 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1199 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1200
1201 common = local_adv & (remote_adv >> 2);
1202 if (common & ADVERTISE_1000FULL) {
1203 bp->line_speed = SPEED_1000;
1204 bp->duplex = DUPLEX_FULL;
1205 }
1206 else if (common & ADVERTISE_1000HALF) {
1207 bp->line_speed = SPEED_1000;
1208 bp->duplex = DUPLEX_HALF;
1209 }
1210 else {
ca58c3af
MC		 1211 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1212 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 1213
1214 common = local_adv & remote_adv;
1215 if (common & ADVERTISE_100FULL) {
1216 bp->line_speed = SPEED_100;
1217 bp->duplex = DUPLEX_FULL;
1218 }
1219 else if (common & ADVERTISE_100HALF) {
1220 bp->line_speed = SPEED_100;
1221 bp->duplex = DUPLEX_HALF;
1222 }
1223 else if (common & ADVERTISE_10FULL) {
1224 bp->line_speed = SPEED_10;
1225 bp->duplex = DUPLEX_FULL;
1226 }
1227 else if (common & ADVERTISE_10HALF) {
1228 bp->line_speed = SPEED_10;
1229 bp->duplex = DUPLEX_HALF;
1230 }
1231 else {
1232 bp->line_speed = 0;
1233 bp->link_up = 0;
1234 }
1235 }
1236 }
1237 else {
1238 if (bmcr & BMCR_SPEED100) {
1239 bp->line_speed = SPEED_100;
1240 }
1241 else {
1242 bp->line_speed = SPEED_10;
1243 }
1244 if (bmcr & BMCR_FULLDPLX) {
1245 bp->duplex = DUPLEX_FULL;
1246 }
1247 else {
1248 bp->duplex = DUPLEX_HALF;
1249 }
1250 }
1251
1252 return 0;
1253}
1254
83e3fc89 1255static void
bb4f98ab 1256bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
83e3fc89 1257{
bb4f98ab 1258 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
83e3fc89
MC		 1259
1260 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1261 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1262 val |= 0x02 << 8;
1263
22fa159d
MC		 1264 if (bp->flow_ctrl & FLOW_CTRL_TX)
1265 val |= BNX2_L2CTX_FLOW_CTRL_ENABLE;
83e3fc89 1266
83e3fc89
MC		 1267 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1268}
1269
bb4f98ab
MC		 1270static void
1271bnx2_init_all_rx_contexts(struct bnx2 *bp)
1272{
1273 int i;
1274 u32 cid;
1275
1276 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1277 if (i == 1)
1278 cid = RX_RSS_CID;
1279 bnx2_init_rx_context(bp, cid);
1280 }
1281}
1282
344478db 1283static void
b6016b76
MC		 1284bnx2_set_mac_link(struct bnx2 *bp)
1285{
1286 u32 val;
1287
1288 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1289 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1290 (bp->duplex == DUPLEX_HALF)) {
1291 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1292 }
1293
1294 /* Configure the EMAC mode register. */
1295 val = REG_RD(bp, BNX2_EMAC_MODE);
1296
1297 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
5b0c76ad 1298 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 1299 BNX2_EMAC_MODE_25G_MODE);
b6016b76
MC		 1300
1301 if (bp->link_up) {
5b0c76ad
MC		 1302 switch (bp->line_speed) {
1303 case SPEED_10:
59b47d8a
MC		 1304 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1305 val |= BNX2_EMAC_MODE_PORT_MII_10M;
5b0c76ad
MC		 1306 break;
1307 }
1308 /* fall through */
1309 case SPEED_100:
1310 val |= BNX2_EMAC_MODE_PORT_MII;
1311 break;
1312 case SPEED_2500:
59b47d8a 1313 val |= BNX2_EMAC_MODE_25G_MODE;
5b0c76ad
MC		 1314 /* fall through */
1315 case SPEED_1000:
1316 val |= BNX2_EMAC_MODE_PORT_GMII;
1317 break;
1318 }
b6016b76
MC		 1319 }
1320 else {
1321 val |= BNX2_EMAC_MODE_PORT_GMII;
1322 }
1323
1324 /* Set the MAC to operate in the appropriate duplex mode. */
1325 if (bp->duplex == DUPLEX_HALF)
1326 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1327 REG_WR(bp, BNX2_EMAC_MODE, val);
1328
1329 /* Enable/disable rx PAUSE. */
1330 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1331
1332 if (bp->flow_ctrl & FLOW_CTRL_RX)
1333 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1334 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1335
1336 /* Enable/disable tx PAUSE. */
1337 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1338 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1339
1340 if (bp->flow_ctrl & FLOW_CTRL_TX)
1341 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1342 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1343
1344 /* Acknowledge the interrupt. */
1345 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1346
22fa159d 1347 bnx2_init_all_rx_contexts(bp);
b6016b76
MC		 1348}
1349
27a005b8
MC		 1350static void
1351bnx2_enable_bmsr1(struct bnx2 *bp)
1352{
583c28e5 1353 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1354 (CHIP_NUM(bp) == CHIP_NUM_5709))
1355 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1356 MII_BNX2_BLK_ADDR_GP_STATUS);
1357}
1358
1359static void
1360bnx2_disable_bmsr1(struct bnx2 *bp)
1361{
583c28e5 1362 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1363 (CHIP_NUM(bp) == CHIP_NUM_5709))
1364 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1365 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1366}
1367
605a9e20
MC		 1368static int
1369bnx2_test_and_enable_2g5(struct bnx2 *bp)
1370{
1371 u32 up1;
1372 int ret = 1;
1373
583c28e5 1374 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1375 return 0;
1376
1377 if (bp->autoneg & AUTONEG_SPEED)
1378 bp->advertising |= ADVERTISED_2500baseX_Full;
1379
27a005b8
MC		 1380 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1381 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1382
605a9e20
MC		 1383 bnx2_read_phy(bp, bp->mii_up1, &up1);
1384 if (!(up1 & BCM5708S_UP1_2G5)) {
1385 up1 |= BCM5708S_UP1_2G5;
1386 bnx2_write_phy(bp, bp->mii_up1, up1);
1387 ret = 0;
1388 }
1389
27a005b8
MC		 1390 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1391 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1392 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1393
605a9e20
MC		 1394 return ret;
1395}
1396
1397static int
1398bnx2_test_and_disable_2g5(struct bnx2 *bp)
1399{
1400 u32 up1;
1401 int ret = 0;
1402
583c28e5 1403 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1404 return 0;
1405
27a005b8
MC		 1406 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1407 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1408
605a9e20
MC		 1409 bnx2_read_phy(bp, bp->mii_up1, &up1);
1410 if (up1 & BCM5708S_UP1_2G5) {
1411 up1 &= ~BCM5708S_UP1_2G5;
1412 bnx2_write_phy(bp, bp->mii_up1, up1);
1413 ret = 1;
1414 }
1415
27a005b8
MC		 1416 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1417 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1418 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1419
605a9e20
MC		 1420 return ret;
1421}
1422
1423static void
1424bnx2_enable_forced_2g5(struct bnx2 *bp)
1425{
cbd6890c
MC		 1426 u32 uninitialized_var(bmcr);
1427 int err;
605a9e20 1428
583c28e5 1429 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1430 return;
1431
27a005b8
MC		 1432 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1433 u32 val;
1434
1435 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1436 MII_BNX2_BLK_ADDR_SERDES_DIG);
cbd6890c
MC		 1437 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1438 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1439 val |= MII_BNX2_SD_MISC1_FORCE |
1440 MII_BNX2_SD_MISC1_FORCE_2_5G;
1441 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1442 }
27a005b8
MC		 1443
1444 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1445 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
cbd6890c 1446 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
27a005b8
MC		 1447
1448 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
cbd6890c
MC		 1449 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1450 if (!err)
1451 bmcr |= BCM5708S_BMCR_FORCE_2500;
c7079857
ED		 1452 } else {
1453 return;
605a9e20
MC		 1454 }
1455
cbd6890c
MC		 1456 if (err)
1457 return;
1458
605a9e20
MC		 1459 if (bp->autoneg & AUTONEG_SPEED) {
1460 bmcr &= ~BMCR_ANENABLE;
1461 if (bp->req_duplex == DUPLEX_FULL)
1462 bmcr |= BMCR_FULLDPLX;
1463 }
1464 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1465}
1466
1467static void
1468bnx2_disable_forced_2g5(struct bnx2 *bp)
1469{
cbd6890c
MC		 1470 u32 uninitialized_var(bmcr);
1471 int err;
605a9e20 1472
583c28e5 1473 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1474 return;
1475
27a005b8
MC		 1476 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1477 u32 val;
1478
1479 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1480 MII_BNX2_BLK_ADDR_SERDES_DIG);
cbd6890c
MC		 1481 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1482 val &= ~MII_BNX2_SD_MISC1_FORCE;
1483 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1484 }
27a005b8
MC		 1485
1486 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1487 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
cbd6890c 1488 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
27a005b8
MC		 1489
1490 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
cbd6890c
MC		 1491 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1492 if (!err)
1493 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
c7079857
ED		 1494 } else {
1495 return;
605a9e20
MC		 1496 }
1497
cbd6890c
MC		 1498 if (err)
1499 return;
1500
605a9e20
MC		 1501 if (bp->autoneg & AUTONEG_SPEED)
1502 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1503 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1504}
1505
b2fadeae
MC		 1506static void
1507bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1508{
1509 u32 val;
1510
1511 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1512 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1513 if (start)
1514 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1515 else
1516 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1517}
1518
b6016b76
MC		 1519static int
1520bnx2_set_link(struct bnx2 *bp)
1521{
1522 u32 bmsr;
1523 u8 link_up;
1524
80be4434 1525 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
b6016b76
MC		 1526 bp->link_up = 1;
1527 return 0;
1528 }
1529
583c28e5 1530 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1531 return 0;
1532
b6016b76
MC		 1533 link_up = bp->link_up;
1534
27a005b8
MC		 1535 bnx2_enable_bmsr1(bp);
1536 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1537 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1538 bnx2_disable_bmsr1(bp);
b6016b76 1539
583c28e5 1540 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
b6016b76 1541 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
a2724e25 1542 u32 val, an_dbg;
b6016b76 1543
583c28e5 1544 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
b2fadeae 1545 bnx2_5706s_force_link_dn(bp, 0);
583c28e5 1546 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
b2fadeae 1547 }
b6016b76 1548 val = REG_RD(bp, BNX2_EMAC_STATUS);
a2724e25
MC		 1549
1550 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1551 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1552 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1553
1554 if ((val & BNX2_EMAC_STATUS_LINK) &&
1555 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
b6016b76
MC		 1556 bmsr |= BMSR_LSTATUS;
1557 else
1558 bmsr &= ~BMSR_LSTATUS;
1559 }
1560
1561 if (bmsr & BMSR_LSTATUS) {
1562 bp->link_up = 1;
1563
583c28e5 1564 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad
MC		 1565 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1566 bnx2_5706s_linkup(bp);
1567 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1568 bnx2_5708s_linkup(bp);
27a005b8
MC		 1569 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1570 bnx2_5709s_linkup(bp);
b6016b76
MC		 1571 }
1572 else {
1573 bnx2_copper_linkup(bp);
1574 }
1575 bnx2_resolve_flow_ctrl(bp);
1576 }
1577 else {
583c28e5 1578 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
605a9e20
MC		 1579 (bp->autoneg & AUTONEG_SPEED))
1580 bnx2_disable_forced_2g5(bp);
b6016b76 1581
583c28e5 1582 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
b2fadeae
MC		 1583 u32 bmcr;
1584
1585 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1586 bmcr |= BMCR_ANENABLE;
1587 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1588
583c28e5 1589 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b2fadeae 1590 }
b6016b76
MC		 1591 bp->link_up = 0;
1592 }
1593
1594 if (bp->link_up != link_up) {
1595 bnx2_report_link(bp);
1596 }
1597
1598 bnx2_set_mac_link(bp);
1599
1600 return 0;
1601}
1602
1603static int
1604bnx2_reset_phy(struct bnx2 *bp)
1605{
1606 int i;
1607 u32 reg;
1608
ca58c3af 1609 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
b6016b76
MC		 1610
1611#define PHY_RESET_MAX_WAIT 100
1612 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1613 udelay(10);
1614
ca58c3af 1615 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
b6016b76
MC		 1616 if (!(reg & BMCR_RESET)) {
1617 udelay(20);
1618 break;
1619 }
1620 }
1621 if (i == PHY_RESET_MAX_WAIT) {
1622 return -EBUSY;
1623 }
1624 return 0;
1625}
1626
1627static u32
1628bnx2_phy_get_pause_adv(struct bnx2 *bp)
1629{
1630 u32 adv = 0;
1631
1632 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1633 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1634
583c28e5 1635 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1636 adv = ADVERTISE_1000XPAUSE;
1637 }
1638 else {
1639 adv = ADVERTISE_PAUSE_CAP;
1640 }
1641 }
1642 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
583c28e5 1643 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1644 adv = ADVERTISE_1000XPSE_ASYM;
1645 }
1646 else {
1647 adv = ADVERTISE_PAUSE_ASYM;
1648 }
1649 }
1650 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
583c28e5 1651 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1652 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1653 }
1654 else {
1655 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1656 }
1657 }
1658 return adv;
1659}
1660
a2f13890 1661static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
0d8a6571 1662
b6016b76 1663static int
0d8a6571 1664bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 1665__releases(&bp->phy_lock)
1666__acquires(&bp->phy_lock)
0d8a6571
MC		 1667{
1668 u32 speed_arg = 0, pause_adv;
1669
1670 pause_adv = bnx2_phy_get_pause_adv(bp);
1671
1672 if (bp->autoneg & AUTONEG_SPEED) {
1673 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1674 if (bp->advertising & ADVERTISED_10baseT_Half)
1675 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1676 if (bp->advertising & ADVERTISED_10baseT_Full)
1677 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1678 if (bp->advertising & ADVERTISED_100baseT_Half)
1679 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1680 if (bp->advertising & ADVERTISED_100baseT_Full)
1681 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1682 if (bp->advertising & ADVERTISED_1000baseT_Full)
1683 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1684 if (bp->advertising & ADVERTISED_2500baseX_Full)
1685 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1686 } else {
1687 if (bp->req_line_speed == SPEED_2500)
1688 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1689 else if (bp->req_line_speed == SPEED_1000)
1690 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1691 else if (bp->req_line_speed == SPEED_100) {
1692 if (bp->req_duplex == DUPLEX_FULL)
1693 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1694 else
1695 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1696 } else if (bp->req_line_speed == SPEED_10) {
1697 if (bp->req_duplex == DUPLEX_FULL)
1698 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1699 else
1700 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1701 }
1702 }
1703
1704 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1705 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
c26736ec 1706 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
0d8a6571
MC		 1707 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1708
1709 if (port == PORT_TP)
1710 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1711 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1712
2726d6e1 1713 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
0d8a6571
MC		 1714
1715 spin_unlock_bh(&bp->phy_lock);
a2f13890 1716 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
0d8a6571
MC		 1717 spin_lock_bh(&bp->phy_lock);
1718
1719 return 0;
1720}
1721
1722static int
1723bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 1724__releases(&bp->phy_lock)
1725__acquires(&bp->phy_lock)
b6016b76 1726{
605a9e20 1727 u32 adv, bmcr;
b6016b76
MC		 1728 u32 new_adv = 0;
1729
583c28e5 1730 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
807540ba 1731 return bnx2_setup_remote_phy(bp, port);
0d8a6571 1732
b6016b76
MC		 1733 if (!(bp->autoneg & AUTONEG_SPEED)) {
1734 u32 new_bmcr;
5b0c76ad
MC		 1735 int force_link_down = 0;
1736
605a9e20
MC		 1737 if (bp->req_line_speed == SPEED_2500) {
1738 if (!bnx2_test_and_enable_2g5(bp))
1739 force_link_down = 1;
1740 } else if (bp->req_line_speed == SPEED_1000) {
1741 if (bnx2_test_and_disable_2g5(bp))
1742 force_link_down = 1;
1743 }
ca58c3af 1744 bnx2_read_phy(bp, bp->mii_adv, &adv);
80be4434
MC		 1745 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1746
ca58c3af 1747 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
605a9e20 1748 new_bmcr = bmcr & ~BMCR_ANENABLE;
80be4434 1749 new_bmcr |= BMCR_SPEED1000;
605a9e20 1750
27a005b8
MC		 1751 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1752 if (bp->req_line_speed == SPEED_2500)
1753 bnx2_enable_forced_2g5(bp);
1754 else if (bp->req_line_speed == SPEED_1000) {
1755 bnx2_disable_forced_2g5(bp);
1756 new_bmcr &= ~0x2000;
1757 }
1758
1759 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1760 if (bp->req_line_speed == SPEED_2500)
1761 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1762 else
1763 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
5b0c76ad
MC		 1764 }
1765
b6016b76 1766 if (bp->req_duplex == DUPLEX_FULL) {
5b0c76ad 1767 adv |= ADVERTISE_1000XFULL;
b6016b76
MC		 1768 new_bmcr |= BMCR_FULLDPLX;
1769 }
1770 else {
5b0c76ad 1771 adv |= ADVERTISE_1000XHALF;
b6016b76
MC		 1772 new_bmcr &= ~BMCR_FULLDPLX;
1773 }
5b0c76ad 1774 if ((new_bmcr != bmcr) || (force_link_down)) {
b6016b76
MC		 1775 /* Force a link down visible on the other side */
1776 if (bp->link_up) {
ca58c3af 1777 bnx2_write_phy(bp, bp->mii_adv, adv &
5b0c76ad
MC		 1778 ~(ADVERTISE_1000XFULL |
1779 ADVERTISE_1000XHALF));
ca58c3af 1780 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
b6016b76
MC		 1781 BMCR_ANRESTART | BMCR_ANENABLE);
1782
1783 bp->link_up = 0;
1784 netif_carrier_off(bp->dev);
ca58c3af 1785 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
80be4434 1786 bnx2_report_link(bp);
b6016b76 1787 }
ca58c3af
MC		 1788 bnx2_write_phy(bp, bp->mii_adv, adv);
1789 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
605a9e20
MC		 1790 } else {
1791 bnx2_resolve_flow_ctrl(bp);
1792 bnx2_set_mac_link(bp);
b6016b76
MC		 1793 }
1794 return 0;
1795 }
1796
605a9e20 1797 bnx2_test_and_enable_2g5(bp);
5b0c76ad 1798
b6016b76
MC		 1799 if (bp->advertising & ADVERTISED_1000baseT_Full)
1800 new_adv |= ADVERTISE_1000XFULL;
1801
1802 new_adv |= bnx2_phy_get_pause_adv(bp);
1803
ca58c3af
MC		 1804 bnx2_read_phy(bp, bp->mii_adv, &adv);
1805 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1806
1807 bp->serdes_an_pending = 0;
1808 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1809 /* Force a link down visible on the other side */
1810 if (bp->link_up) {
ca58c3af 1811 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
80be4434
MC		 1812 spin_unlock_bh(&bp->phy_lock);
1813 msleep(20);
1814 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 1815 }
1816
ca58c3af
MC		 1817 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1818 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
b6016b76 1819 BMCR_ANENABLE);
f8dd064e
MC		 1820 /* Speed up link-up time when the link partner
1821 * does not autonegotiate which is very common
1822 * in blade servers. Some blade servers use
1823 * IPMI for kerboard input and it's important
1824 * to minimize link disruptions. Autoneg. involves
1825 * exchanging base pages plus 3 next pages and
1826 * normally completes in about 120 msec.
1827 */
40105c0b 1828 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
f8dd064e
MC		 1829 bp->serdes_an_pending = 1;
1830 mod_timer(&bp->timer, jiffies + bp->current_interval);
605a9e20
MC		 1831 } else {
1832 bnx2_resolve_flow_ctrl(bp);
1833 bnx2_set_mac_link(bp);
b6016b76
MC		 1834 }
1835
1836 return 0;
1837}
1838
1839#define ETHTOOL_ALL_FIBRE_SPEED \
583c28e5 1840 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
deaf391b
MC		 1841 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1842 (ADVERTISED_1000baseT_Full)
b6016b76
MC		 1843
1844#define ETHTOOL_ALL_COPPER_SPEED \
1845 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1846 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1847 ADVERTISED_1000baseT_Full)
1848
1849#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1850 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
6aa20a22 1851
b6016b76
MC		 1852#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1853
0d8a6571
MC		 1854static void
1855bnx2_set_default_remote_link(struct bnx2 *bp)
1856{
1857 u32 link;
1858
1859 if (bp->phy_port == PORT_TP)
2726d6e1 1860 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
0d8a6571 1861 else
2726d6e1 1862 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
0d8a6571
MC		 1863
1864 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1865 bp->req_line_speed = 0;
1866 bp->autoneg |= AUTONEG_SPEED;
1867 bp->advertising = ADVERTISED_Autoneg;
1868 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1869 bp->advertising |= ADVERTISED_10baseT_Half;
1870 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1871 bp->advertising |= ADVERTISED_10baseT_Full;
1872 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1873 bp->advertising |= ADVERTISED_100baseT_Half;
1874 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1875 bp->advertising |= ADVERTISED_100baseT_Full;
1876 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1877 bp->advertising |= ADVERTISED_1000baseT_Full;
1878 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1879 bp->advertising |= ADVERTISED_2500baseX_Full;
1880 } else {
1881 bp->autoneg = 0;
1882 bp->advertising = 0;
1883 bp->req_duplex = DUPLEX_FULL;
1884 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1885 bp->req_line_speed = SPEED_10;
1886 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1887 bp->req_duplex = DUPLEX_HALF;
1888 }
1889 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1890 bp->req_line_speed = SPEED_100;
1891 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1892 bp->req_duplex = DUPLEX_HALF;
1893 }
1894 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1895 bp->req_line_speed = SPEED_1000;
1896 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1897 bp->req_line_speed = SPEED_2500;
1898 }
1899}
1900
deaf391b
MC		 1901static void
1902bnx2_set_default_link(struct bnx2 *bp)
1903{
ab59859d
HH		 1904 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1905 bnx2_set_default_remote_link(bp);
1906 return;
1907 }
0d8a6571 1908
deaf391b
MC		 1909 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1910 bp->req_line_speed = 0;
583c28e5 1911 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
deaf391b
MC		 1912 u32 reg;
1913
1914 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1915
2726d6e1 1916 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
deaf391b
MC		 1917 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1918 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1919 bp->autoneg = 0;
1920 bp->req_line_speed = bp->line_speed = SPEED_1000;
1921 bp->req_duplex = DUPLEX_FULL;
1922 }
1923 } else
1924 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1925}
1926
df149d70
MC		 1927static void
1928bnx2_send_heart_beat(struct bnx2 *bp)
1929{
1930 u32 msg;
1931 u32 addr;
1932
1933 spin_lock(&bp->indirect_lock);
1934 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1935 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1936 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1937 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1938 spin_unlock(&bp->indirect_lock);
1939}
1940
0d8a6571
MC		 1941static void
1942bnx2_remote_phy_event(struct bnx2 *bp)
1943{
1944 u32 msg;
1945 u8 link_up = bp->link_up;
1946 u8 old_port;
1947
2726d6e1 1948 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
0d8a6571 1949
df149d70
MC		 1950 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1951 bnx2_send_heart_beat(bp);
1952
1953 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1954
0d8a6571
MC		 1955 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1956 bp->link_up = 0;
1957 else {
1958 u32 speed;
1959
1960 bp->link_up = 1;
1961 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1962 bp->duplex = DUPLEX_FULL;
1963 switch (speed) {
1964 case BNX2_LINK_STATUS_10HALF:
1965 bp->duplex = DUPLEX_HALF;
1966 case BNX2_LINK_STATUS_10FULL:
1967 bp->line_speed = SPEED_10;
1968 break;
1969 case BNX2_LINK_STATUS_100HALF:
1970 bp->duplex = DUPLEX_HALF;
1971 case BNX2_LINK_STATUS_100BASE_T4:
1972 case BNX2_LINK_STATUS_100FULL:
1973 bp->line_speed = SPEED_100;
1974 break;
1975 case BNX2_LINK_STATUS_1000HALF:
1976 bp->duplex = DUPLEX_HALF;
1977 case BNX2_LINK_STATUS_1000FULL:
1978 bp->line_speed = SPEED_1000;
1979 break;
1980 case BNX2_LINK_STATUS_2500HALF:
1981 bp->duplex = DUPLEX_HALF;
1982 case BNX2_LINK_STATUS_2500FULL:
1983 bp->line_speed = SPEED_2500;
1984 break;
1985 default:
1986 bp->line_speed = 0;
1987 break;
1988 }
1989
0d8a6571
MC		 1990 bp->flow_ctrl = 0;
1991 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1992 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1993 if (bp->duplex == DUPLEX_FULL)
1994 bp->flow_ctrl = bp->req_flow_ctrl;
1995 } else {
1996 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1997 bp->flow_ctrl |= FLOW_CTRL_TX;
1998 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1999 bp->flow_ctrl |= FLOW_CTRL_RX;
2000 }
2001
2002 old_port = bp->phy_port;
2003 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2004 bp->phy_port = PORT_FIBRE;
2005 else
2006 bp->phy_port = PORT_TP;
2007
2008 if (old_port != bp->phy_port)
2009 bnx2_set_default_link(bp);
2010
0d8a6571
MC		 2011 }
2012 if (bp->link_up != link_up)
2013 bnx2_report_link(bp);
2014
2015 bnx2_set_mac_link(bp);
2016}
2017
2018static int
2019bnx2_set_remote_link(struct bnx2 *bp)
2020{
2021 u32 evt_code;
2022
2726d6e1 2023 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
0d8a6571
MC		 2024 switch (evt_code) {
2025 case BNX2_FW_EVT_CODE_LINK_EVENT:
2026 bnx2_remote_phy_event(bp);
2027 break;
2028 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2029 default:
df149d70 2030 bnx2_send_heart_beat(bp);
0d8a6571
MC		 2031 break;
2032 }
2033 return 0;
2034}
2035
b6016b76
MC		 2036static int
2037bnx2_setup_copper_phy(struct bnx2 *bp)
52d07b1f
HH		 2038__releases(&bp->phy_lock)
2039__acquires(&bp->phy_lock)
b6016b76
MC		 2040{
2041 u32 bmcr;
2042 u32 new_bmcr;
2043
ca58c3af 2044 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 2045
2046 if (bp->autoneg & AUTONEG_SPEED) {
2047 u32 adv_reg, adv1000_reg;
2048 u32 new_adv_reg = 0;
2049 u32 new_adv1000_reg = 0;
2050
ca58c3af 2051 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
b6016b76
MC		 2052 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2053 ADVERTISE_PAUSE_ASYM);
2054
2055 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2056 adv1000_reg &= PHY_ALL_1000_SPEED;
2057
2058 if (bp->advertising & ADVERTISED_10baseT_Half)
2059 new_adv_reg |= ADVERTISE_10HALF;
2060 if (bp->advertising & ADVERTISED_10baseT_Full)
2061 new_adv_reg |= ADVERTISE_10FULL;
2062 if (bp->advertising & ADVERTISED_100baseT_Half)
2063 new_adv_reg |= ADVERTISE_100HALF;
2064 if (bp->advertising & ADVERTISED_100baseT_Full)
2065 new_adv_reg |= ADVERTISE_100FULL;
2066 if (bp->advertising & ADVERTISED_1000baseT_Full)
2067 new_adv1000_reg |= ADVERTISE_1000FULL;
6aa20a22 2068
b6016b76
MC		 2069 new_adv_reg |= ADVERTISE_CSMA;
2070
2071 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
2072
2073 if ((adv1000_reg != new_adv1000_reg) ||
2074 (adv_reg != new_adv_reg) ||
2075 ((bmcr & BMCR_ANENABLE) == 0)) {
2076
ca58c3af 2077 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
b6016b76 2078 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
ca58c3af 2079 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
b6016b76
MC		 2080 BMCR_ANENABLE);
2081 }
2082 else if (bp->link_up) {
2083 /* Flow ctrl may have changed from auto to forced */
2084 /* or vice-versa. */
2085
2086 bnx2_resolve_flow_ctrl(bp);
2087 bnx2_set_mac_link(bp);
2088 }
2089 return 0;
2090 }
2091
2092 new_bmcr = 0;
2093 if (bp->req_line_speed == SPEED_100) {
2094 new_bmcr |= BMCR_SPEED100;
2095 }
2096 if (bp->req_duplex == DUPLEX_FULL) {
2097 new_bmcr |= BMCR_FULLDPLX;
2098 }
2099 if (new_bmcr != bmcr) {
2100 u32 bmsr;
b6016b76 2101
ca58c3af
MC		 2102 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2103 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
6aa20a22 2104
b6016b76
MC		 2105 if (bmsr & BMSR_LSTATUS) {
2106 /* Force link down */
ca58c3af 2107 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
a16dda0e
MC		 2108 spin_unlock_bh(&bp->phy_lock);
2109 msleep(50);
2110 spin_lock_bh(&bp->phy_lock);
2111
ca58c3af
MC		 2112 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2113 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
b6016b76
MC		 2114 }
2115
ca58c3af 2116 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
b6016b76
MC		 2117
2118 /* Normally, the new speed is setup after the link has
2119 * gone down and up again. In some cases, link will not go
2120 * down so we need to set up the new speed here.
2121 */
2122 if (bmsr & BMSR_LSTATUS) {
2123 bp->line_speed = bp->req_line_speed;
2124 bp->duplex = bp->req_duplex;
2125 bnx2_resolve_flow_ctrl(bp);
2126 bnx2_set_mac_link(bp);
2127 }
27a005b8
MC		 2128 } else {
2129 bnx2_resolve_flow_ctrl(bp);
2130 bnx2_set_mac_link(bp);
b6016b76
MC		 2131 }
2132 return 0;
2133}
2134
2135static int
0d8a6571 2136bnx2_setup_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 2137__releases(&bp->phy_lock)
2138__acquires(&bp->phy_lock)
b6016b76
MC		 2139{
2140 if (bp->loopback == MAC_LOOPBACK)
2141 return 0;
2142
583c28e5 2143 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
807540ba 2144 return bnx2_setup_serdes_phy(bp, port);
b6016b76
MC		 2145 }
2146 else {
807540ba 2147 return bnx2_setup_copper_phy(bp);
b6016b76
MC		 2148 }
2149}
2150
27a005b8 2151static int
9a120bc5 2152bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
27a005b8
MC		 2153{
2154 u32 val;
2155
2156 bp->mii_bmcr = MII_BMCR + 0x10;
2157 bp->mii_bmsr = MII_BMSR + 0x10;
2158 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2159 bp->mii_adv = MII_ADVERTISE + 0x10;
2160 bp->mii_lpa = MII_LPA + 0x10;
2161 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2162
2163 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2164 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2165
2166 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
9a120bc5
MC		 2167 if (reset_phy)
2168 bnx2_reset_phy(bp);
27a005b8
MC		 2169
2170 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2171
2172 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2173 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2174 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2175 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2176
2177 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2178 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
583c28e5 2179 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
27a005b8
MC		 2180 val |= BCM5708S_UP1_2G5;
2181 else
2182 val &= ~BCM5708S_UP1_2G5;
2183 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2184
2185 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2186 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2187 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2188 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2189
2190 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2191
2192 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2193 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2194 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2195
2196 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2197
2198 return 0;
2199}
2200
b6016b76 2201static int
9a120bc5 2202bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
5b0c76ad
MC		 2203{
2204 u32 val;
2205
9a120bc5
MC		 2206 if (reset_phy)
2207 bnx2_reset_phy(bp);
27a005b8
MC		 2208
2209 bp->mii_up1 = BCM5708S_UP1;
2210
5b0c76ad
MC		 2211 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2212 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2213 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2214
2215 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2216 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2217 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2218
2219 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2220 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2221 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2222
583c28e5 2223 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
5b0c76ad
MC		 2224 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2225 val |= BCM5708S_UP1_2G5;
2226 bnx2_write_phy(bp, BCM5708S_UP1, val);
2227 }
2228
2229 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
dda1e390
MC		 2230 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2231 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
5b0c76ad
MC		 2232 /* increase tx signal amplitude */
2233 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2234 BCM5708S_BLK_ADDR_TX_MISC);
2235 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2236 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2237 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2238 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2239 }
2240
2726d6e1 2241 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
5b0c76ad
MC		 2242 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2243
2244 if (val) {
2245 u32 is_backplane;
2246
2726d6e1 2247 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
5b0c76ad
MC		 2248 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2249 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2250 BCM5708S_BLK_ADDR_TX_MISC);
2251 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2252 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2253 BCM5708S_BLK_ADDR_DIG);
2254 }
2255 }
2256 return 0;
2257}
2258
2259static int
9a120bc5 2260bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2261{
9a120bc5
MC		 2262 if (reset_phy)
2263 bnx2_reset_phy(bp);
27a005b8 2264
583c28e5 2265 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b6016b76 2266
59b47d8a
MC		 2267 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2268 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
b6016b76
MC		 2269
2270 if (bp->dev->mtu > 1500) {
2271 u32 val;
2272
2273 /* Set extended packet length bit */
2274 bnx2_write_phy(bp, 0x18, 0x7);
2275 bnx2_read_phy(bp, 0x18, &val);
2276 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2277
2278 bnx2_write_phy(bp, 0x1c, 0x6c00);
2279 bnx2_read_phy(bp, 0x1c, &val);
2280 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2281 }
2282 else {
2283 u32 val;
2284
2285 bnx2_write_phy(bp, 0x18, 0x7);
2286 bnx2_read_phy(bp, 0x18, &val);
2287 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2288
2289 bnx2_write_phy(bp, 0x1c, 0x6c00);
2290 bnx2_read_phy(bp, 0x1c, &val);
2291 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2292 }
2293
2294 return 0;
2295}
2296
2297static int
9a120bc5 2298bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2299{
5b0c76ad
MC		 2300 u32 val;
2301
9a120bc5
MC		 2302 if (reset_phy)
2303 bnx2_reset_phy(bp);
27a005b8 2304
583c28e5 2305 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
b6016b76
MC		 2306 bnx2_write_phy(bp, 0x18, 0x0c00);
2307 bnx2_write_phy(bp, 0x17, 0x000a);
2308 bnx2_write_phy(bp, 0x15, 0x310b);
2309 bnx2_write_phy(bp, 0x17, 0x201f);
2310 bnx2_write_phy(bp, 0x15, 0x9506);
2311 bnx2_write_phy(bp, 0x17, 0x401f);
2312 bnx2_write_phy(bp, 0x15, 0x14e2);
2313 bnx2_write_phy(bp, 0x18, 0x0400);
2314 }
2315
583c28e5 2316 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
b659f44e
MC		 2317 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2318 MII_BNX2_DSP_EXPAND_REG | 0x8);
2319 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2320 val &= ~(1 << 8);
2321 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2322 }
2323
b6016b76 2324 if (bp->dev->mtu > 1500) {
b6016b76
MC		 2325 /* Set extended packet length bit */
2326 bnx2_write_phy(bp, 0x18, 0x7);
2327 bnx2_read_phy(bp, 0x18, &val);
2328 bnx2_write_phy(bp, 0x18, val | 0x4000);
2329
2330 bnx2_read_phy(bp, 0x10, &val);
2331 bnx2_write_phy(bp, 0x10, val | 0x1);
2332 }
2333 else {
b6016b76
MC		 2334 bnx2_write_phy(bp, 0x18, 0x7);
2335 bnx2_read_phy(bp, 0x18, &val);
2336 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2337
2338 bnx2_read_phy(bp, 0x10, &val);
2339 bnx2_write_phy(bp, 0x10, val & ~0x1);
2340 }
2341
5b0c76ad
MC		 2342 /* ethernet@wirespeed */
2343 bnx2_write_phy(bp, 0x18, 0x7007);
2344 bnx2_read_phy(bp, 0x18, &val);
2345 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
b6016b76
MC		 2346 return 0;
2347}
2348
2349
2350static int
9a120bc5 2351bnx2_init_phy(struct bnx2 *bp, int reset_phy)
52d07b1f
HH		 2352__releases(&bp->phy_lock)
2353__acquires(&bp->phy_lock)
b6016b76
MC		 2354{
2355 u32 val;
2356 int rc = 0;
2357
583c28e5
MC		 2358 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2359 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
b6016b76 2360
ca58c3af
MC		 2361 bp->mii_bmcr = MII_BMCR;
2362 bp->mii_bmsr = MII_BMSR;
27a005b8 2363 bp->mii_bmsr1 = MII_BMSR;
ca58c3af
MC		 2364 bp->mii_adv = MII_ADVERTISE;
2365 bp->mii_lpa = MII_LPA;
2366
b6016b76
MC		 2367 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2368
583c28e5 2369 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 2370 goto setup_phy;
2371
b6016b76
MC		 2372 bnx2_read_phy(bp, MII_PHYSID1, &val);
2373 bp->phy_id = val << 16;
2374 bnx2_read_phy(bp, MII_PHYSID2, &val);
2375 bp->phy_id |= val & 0xffff;
2376
583c28e5 2377 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad 2378 if (CHIP_NUM(bp) == CHIP_NUM_5706)
9a120bc5 2379 rc = bnx2_init_5706s_phy(bp, reset_phy);
5b0c76ad 2380 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
9a120bc5 2381 rc = bnx2_init_5708s_phy(bp, reset_phy);
27a005b8 2382 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
9a120bc5 2383 rc = bnx2_init_5709s_phy(bp, reset_phy);
b6016b76
MC		 2384 }
2385 else {
9a120bc5 2386 rc = bnx2_init_copper_phy(bp, reset_phy);
b6016b76
MC		 2387 }
2388
0d8a6571
MC		 2389setup_phy:
2390 if (!rc)
2391 rc = bnx2_setup_phy(bp, bp->phy_port);
b6016b76
MC		 2392
2393 return rc;
2394}
2395
2396static int
2397bnx2_set_mac_loopback(struct bnx2 *bp)
2398{
2399 u32 mac_mode;
2400
2401 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2402 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2403 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2404 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2405 bp->link_up = 1;
2406 return 0;
2407}
2408
bc5a0690
MC		 2409static int bnx2_test_link(struct bnx2 *);
2410
2411static int
2412bnx2_set_phy_loopback(struct bnx2 *bp)
2413{
2414 u32 mac_mode;
2415 int rc, i;
2416
2417 spin_lock_bh(&bp->phy_lock);
ca58c3af 2418 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
bc5a0690
MC		 2419 BMCR_SPEED1000);
2420 spin_unlock_bh(&bp->phy_lock);
2421 if (rc)
2422 return rc;
2423
2424 for (i = 0; i < 10; i++) {
2425 if (bnx2_test_link(bp) == 0)
2426 break;
80be4434 2427 msleep(100);
bc5a0690
MC		 2428 }
2429
2430 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2431 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2432 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 2433 BNX2_EMAC_MODE_25G_MODE);
bc5a0690
MC		 2434
2435 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2436 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2437 bp->link_up = 1;
2438 return 0;
2439}
2440
b6016b76 2441static int
a2f13890 2442bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
b6016b76
MC		 2443{
2444 int i;
2445 u32 val;
2446
b6016b76
MC		 2447 bp->fw_wr_seq++;
2448 msg_data |= bp->fw_wr_seq;
2449
2726d6e1 2450 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76 2451
a2f13890
MC		 2452 if (!ack)
2453 return 0;
2454
b6016b76 2455 /* wait for an acknowledgement. */
40105c0b 2456 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
b090ae2b 2457 msleep(10);
b6016b76 2458
2726d6e1 2459 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
b6016b76
MC		 2460
2461 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2462 break;
2463 }
b090ae2b
MC		 2464 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2465 return 0;
b6016b76
MC		 2466
2467 /* If we timed out, inform the firmware that this is the case. */
b090ae2b
MC		 2468 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2469 if (!silent)
3a9c6a49 2470 pr_err("fw sync timeout, reset code = %x\n", msg_data);
b6016b76
MC		 2471
2472 msg_data &= ~BNX2_DRV_MSG_CODE;
2473 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2474
2726d6e1 2475 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76 2476
b6016b76
MC		 2477 return -EBUSY;
2478 }
2479
b090ae2b
MC		 2480 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2481 return -EIO;
2482
b6016b76
MC		 2483 return 0;
2484}
2485
59b47d8a
MC		 2486static int
2487bnx2_init_5709_context(struct bnx2 *bp)
2488{
2489 int i, ret = 0;
2490 u32 val;
2491
2492 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2493 val |= (BCM_PAGE_BITS - 8) << 16;
2494 REG_WR(bp, BNX2_CTX_COMMAND, val);
641bdcd5
MC		 2495 for (i = 0; i < 10; i++) {
2496 val = REG_RD(bp, BNX2_CTX_COMMAND);
2497 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2498 break;
2499 udelay(2);
2500 }
2501 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2502 return -EBUSY;
2503
59b47d8a
MC		 2504 for (i = 0; i < bp->ctx_pages; i++) {
2505 int j;
2506
352f7687
MC		 2507 if (bp->ctx_blk[i])
2508 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2509 else
2510 return -ENOMEM;
2511
59b47d8a
MC		 2512 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2513 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2514 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2515 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2516 (u64) bp->ctx_blk_mapping[i] >> 32);
2517 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2518 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2519 for (j = 0; j < 10; j++) {
2520
2521 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2522 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2523 break;
2524 udelay(5);
2525 }
2526 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2527 ret = -EBUSY;
2528 break;
2529 }
2530 }
2531 return ret;
2532}
2533
b6016b76
MC		 2534static void
2535bnx2_init_context(struct bnx2 *bp)
2536{
2537 u32 vcid;
2538
2539 vcid = 96;
2540 while (vcid) {
2541 u32 vcid_addr, pcid_addr, offset;
7947b20e 2542 int i;
b6016b76
MC		 2543
2544 vcid--;
2545
2546 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2547 u32 new_vcid;
2548
2549 vcid_addr = GET_PCID_ADDR(vcid);
2550 if (vcid & 0x8) {
2551 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2552 }
2553 else {
2554 new_vcid = vcid;
2555 }
2556 pcid_addr = GET_PCID_ADDR(new_vcid);
2557 }
2558 else {
2559 vcid_addr = GET_CID_ADDR(vcid);
2560 pcid_addr = vcid_addr;
2561 }
2562
7947b20e
MC		 2563 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2564 vcid_addr += (i << PHY_CTX_SHIFT);
2565 pcid_addr += (i << PHY_CTX_SHIFT);
b6016b76 2566
5d5d0015 2567 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
7947b20e 2568 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
b6016b76 2569
7947b20e
MC		 2570 /* Zero out the context. */
2571 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
62a8313c 2572 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
7947b20e 2573 }
b6016b76
MC		 2574 }
2575}
2576
2577static int
2578bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2579{
2580 u16 *good_mbuf;
2581 u32 good_mbuf_cnt;
2582 u32 val;
2583
2584 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2585 if (good_mbuf == NULL) {
3a9c6a49 2586 pr_err("Failed to allocate memory in %s\n", __func__);
b6016b76
MC		 2587 return -ENOMEM;
2588 }
2589
2590 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2591 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2592
2593 good_mbuf_cnt = 0;
2594
2595 /* Allocate a bunch of mbufs and save the good ones in an array. */
2726d6e1 2596 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76 2597 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2726d6e1
MC		 2598 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2599 BNX2_RBUF_COMMAND_ALLOC_REQ);
b6016b76 2600
2726d6e1 2601 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
b6016b76
MC		 2602
2603 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2604
2605 /* The addresses with Bit 9 set are bad memory blocks. */
2606 if (!(val & (1 << 9))) {
2607 good_mbuf[good_mbuf_cnt] = (u16) val;
2608 good_mbuf_cnt++;
2609 }
2610
2726d6e1 2611 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76
MC		 2612 }
2613
2614 /* Free the good ones back to the mbuf pool thus discarding
2615 * all the bad ones. */
2616 while (good_mbuf_cnt) {
2617 good_mbuf_cnt--;
2618
2619 val = good_mbuf[good_mbuf_cnt];
2620 val = (val << 9) | val | 1;
2621
2726d6e1 2622 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
b6016b76
MC		 2623 }
2624 kfree(good_mbuf);
2625 return 0;
2626}
2627
2628static void
5fcaed01 2629bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
b6016b76
MC		 2630{
2631 u32 val;
b6016b76
MC		 2632
2633 val = (mac_addr[0] << 8) | mac_addr[1];
2634
5fcaed01 2635 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
b6016b76 2636
6aa20a22 2637 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
b6016b76
MC		 2638 (mac_addr[4] << 8) | mac_addr[5];
2639
5fcaed01 2640 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
b6016b76
MC		 2641}
2642
47bf4246 2643static inline int
a2df00aa 2644bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
47bf4246
MC		 2645{
2646 dma_addr_t mapping;
bb4f98ab 2647 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
47bf4246 2648 struct rx_bd *rxbd =
bb4f98ab 2649 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
a2df00aa 2650 struct page *page = alloc_page(gfp);
47bf4246
MC		 2651
2652 if (!page)
2653 return -ENOMEM;
36227e88 2654 mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE,
47bf4246 2655 PCI_DMA_FROMDEVICE);
36227e88 2656 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
3d16af86
BL		 2657 __free_page(page);
2658 return -EIO;
2659 }
2660
47bf4246 2661 rx_pg->page = page;
1a4ccc2d 2662 dma_unmap_addr_set(rx_pg, mapping, mapping);
47bf4246
MC		 2663 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2664 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2665 return 0;
2666}
2667
2668static void
bb4f98ab 2669bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
47bf4246 2670{
bb4f98ab 2671 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
47bf4246
MC		 2672 struct page *page = rx_pg->page;
2673
2674 if (!page)
2675 return;
2676
36227e88
SG		 2677 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping),
2678 PAGE_SIZE, PCI_DMA_FROMDEVICE);
47bf4246
MC		 2679
2680 __free_page(page);
2681 rx_pg->page = NULL;
2682}
2683
b6016b76 2684static inline int
a2df00aa 2685bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
b6016b76
MC		 2686{
2687 struct sk_buff *skb;
bb4f98ab 2688 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
b6016b76 2689 dma_addr_t mapping;
bb4f98ab 2690 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
b6016b76
MC		 2691 unsigned long align;
2692
a2df00aa 2693 skb = __netdev_alloc_skb(bp->dev, bp->rx_buf_size, gfp);
b6016b76
MC		 2694 if (skb == NULL) {
2695 return -ENOMEM;
2696 }
2697
59b47d8a
MC		 2698 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2699 skb_reserve(skb, BNX2_RX_ALIGN - align);
b6016b76 2700
36227e88
SG		 2701 mapping = dma_map_single(&bp->pdev->dev, skb->data, bp->rx_buf_use_size,
2702 PCI_DMA_FROMDEVICE);
2703 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
3d16af86
BL		 2704 dev_kfree_skb(skb);
2705 return -EIO;
2706 }
b6016b76
MC		 2707
2708 rx_buf->skb = skb;
a33fa66b 2709 rx_buf->desc = (struct l2_fhdr *) skb->data;
1a4ccc2d 2710 dma_unmap_addr_set(rx_buf, mapping, mapping);
b6016b76
MC		 2711
2712 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2713 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2714
bb4f98ab 2715 rxr->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76
MC		 2716
2717 return 0;
2718}
2719
da3e4fbe 2720static int
35efa7c1 2721bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
b6016b76 2722{
43e80b89 2723 struct status_block *sblk = bnapi->status_blk.msi;
b6016b76 2724 u32 new_link_state, old_link_state;
da3e4fbe 2725 int is_set = 1;
b6016b76 2726
da3e4fbe
MC		 2727 new_link_state = sblk->status_attn_bits & event;
2728 old_link_state = sblk->status_attn_bits_ack & event;
b6016b76 2729 if (new_link_state != old_link_state) {
da3e4fbe
MC		 2730 if (new_link_state)
2731 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2732 else
2733 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2734 } else
2735 is_set = 0;
2736
2737 return is_set;
2738}
2739
2740static void
35efa7c1 2741bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
da3e4fbe 2742{
74ecc62d
MC		 2743 spin_lock(&bp->phy_lock);
2744
2745 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
b6016b76 2746 bnx2_set_link(bp);
35efa7c1 2747 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
0d8a6571
MC		 2748 bnx2_set_remote_link(bp);
2749
74ecc62d
MC		 2750 spin_unlock(&bp->phy_lock);
2751
b6016b76
MC		 2752}
2753
ead7270b 2754static inline u16
35efa7c1 2755bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
ead7270b
MC		 2756{
2757 u16 cons;
2758
43e80b89
MC		 2759 /* Tell compiler that status block fields can change. */
2760 barrier();
2761 cons = *bnapi->hw_tx_cons_ptr;
581daf7e 2762 barrier();
ead7270b
MC		 2763 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2764 cons++;
2765 return cons;
2766}
2767
57851d84
MC		 2768static int
2769bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76 2770{
35e9010b 2771 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
b6016b76 2772 u16 hw_cons, sw_cons, sw_ring_cons;
706bf240
BL		 2773 int tx_pkt = 0, index;
2774 struct netdev_queue *txq;
2775
2776 index = (bnapi - bp->bnx2_napi);
2777 txq = netdev_get_tx_queue(bp->dev, index);
b6016b76 2778
35efa7c1 2779 hw_cons = bnx2_get_hw_tx_cons(bnapi);
35e9010b 2780 sw_cons = txr->tx_cons;
b6016b76
MC		 2781
2782 while (sw_cons != hw_cons) {
3d16af86 2783 struct sw_tx_bd *tx_buf;
b6016b76
MC		 2784 struct sk_buff *skb;
2785 int i, last;
2786
2787 sw_ring_cons = TX_RING_IDX(sw_cons);
2788
35e9010b 2789 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
b6016b76 2790 skb = tx_buf->skb;
1d39ed56 2791
d62fda08
ED		 2792 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2793 prefetch(&skb->end);
2794
b6016b76 2795 /* partial BD completions possible with TSO packets */
d62fda08 2796 if (tx_buf->is_gso) {
b6016b76
MC		 2797 u16 last_idx, last_ring_idx;
2798
d62fda08
ED		 2799 last_idx = sw_cons + tx_buf->nr_frags + 1;
2800 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
b6016b76
MC		 2801 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2802 last_idx++;
2803 }
2804 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2805 break;
2806 }
2807 }
1d39ed56 2808
36227e88 2809 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
e95524a7 2810 skb_headlen(skb), PCI_DMA_TODEVICE);
b6016b76
MC		 2811
2812 tx_buf->skb = NULL;
d62fda08 2813 last = tx_buf->nr_frags;
b6016b76
MC		 2814
2815 for (i = 0; i < last; i++) {
2816 sw_cons = NEXT_TX_BD(sw_cons);
e95524a7 2817
36227e88 2818 dma_unmap_page(&bp->pdev->dev,
1a4ccc2d 2819 dma_unmap_addr(
e95524a7
AD		 2820 &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2821 mapping),
2822 skb_shinfo(skb)->frags[i].size,
2823 PCI_DMA_TODEVICE);
b6016b76
MC		 2824 }
2825
2826 sw_cons = NEXT_TX_BD(sw_cons);
2827
745720e5 2828 dev_kfree_skb(skb);
57851d84
MC		 2829 tx_pkt++;
2830 if (tx_pkt == budget)
2831 break;
b6016b76 2832
d62fda08
ED		 2833 if (hw_cons == sw_cons)
2834 hw_cons = bnx2_get_hw_tx_cons(bnapi);
b6016b76
MC		 2835 }
2836
35e9010b
MC		 2837 txr->hw_tx_cons = hw_cons;
2838 txr->tx_cons = sw_cons;
706bf240 2839
2f8af120 2840 /* Need to make the tx_cons update visible to bnx2_start_xmit()
706bf240 2841 * before checking for netif_tx_queue_stopped(). Without the
2f8af120
MC		 2842 * memory barrier, there is a small possibility that bnx2_start_xmit()
2843 * will miss it and cause the queue to be stopped forever.
2844 */
2845 smp_mb();
b6016b76 2846
706bf240 2847 if (unlikely(netif_tx_queue_stopped(txq)) &&
35e9010b 2848 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
706bf240
BL		 2849 __netif_tx_lock(txq, smp_processor_id());
2850 if ((netif_tx_queue_stopped(txq)) &&
35e9010b 2851 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
706bf240
BL		 2852 netif_tx_wake_queue(txq);
2853 __netif_tx_unlock(txq);
b6016b76 2854 }
706bf240 2855
57851d84 2856 return tx_pkt;
b6016b76
MC		 2857}
2858
1db82f2a 2859static void
bb4f98ab 2860bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
a1f60190 2861 struct sk_buff *skb, int count)
1db82f2a
MC		 2862{
2863 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2864 struct rx_bd *cons_bd, *prod_bd;
1db82f2a 2865 int i;
3d16af86 2866 u16 hw_prod, prod;
bb4f98ab 2867 u16 cons = rxr->rx_pg_cons;
1db82f2a 2868
3d16af86
BL		 2869 cons_rx_pg = &rxr->rx_pg_ring[cons];
2870
2871 /* The caller was unable to allocate a new page to replace the
2872 * last one in the frags array, so we need to recycle that page
2873 * and then free the skb.
2874 */
2875 if (skb) {
2876 struct page *page;
2877 struct skb_shared_info *shinfo;
2878
2879 shinfo = skb_shinfo(skb);
2880 shinfo->nr_frags--;
2881 page = shinfo->frags[shinfo->nr_frags].page;
2882 shinfo->frags[shinfo->nr_frags].page = NULL;
2883
2884 cons_rx_pg->page = page;
2885 dev_kfree_skb(skb);
2886 }
2887
2888 hw_prod = rxr->rx_pg_prod;
2889
1db82f2a
MC		 2890 for (i = 0; i < count; i++) {
2891 prod = RX_PG_RING_IDX(hw_prod);
2892
bb4f98ab
MC		 2893 prod_rx_pg = &rxr->rx_pg_ring[prod];
2894 cons_rx_pg = &rxr->rx_pg_ring[cons];
2895 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2896 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1db82f2a 2897
1db82f2a
MC		 2898 if (prod != cons) {
2899 prod_rx_pg->page = cons_rx_pg->page;
2900 cons_rx_pg->page = NULL;
1a4ccc2d
FT		 2901 dma_unmap_addr_set(prod_rx_pg, mapping,
2902 dma_unmap_addr(cons_rx_pg, mapping));
1db82f2a
MC		 2903
2904 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2905 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2906
2907 }
2908 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2909 hw_prod = NEXT_RX_BD(hw_prod);
2910 }
bb4f98ab
MC		 2911 rxr->rx_pg_prod = hw_prod;
2912 rxr->rx_pg_cons = cons;
1db82f2a
MC		 2913}
2914
b6016b76 2915static inline void
bb4f98ab
MC		 2916bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2917 struct sk_buff *skb, u16 cons, u16 prod)
b6016b76 2918{
236b6394
MC		 2919 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2920 struct rx_bd *cons_bd, *prod_bd;
2921
bb4f98ab
MC		 2922 cons_rx_buf = &rxr->rx_buf_ring[cons];
2923 prod_rx_buf = &rxr->rx_buf_ring[prod];
b6016b76 2924
36227e88 2925 dma_sync_single_for_device(&bp->pdev->dev,
1a4ccc2d 2926 dma_unmap_addr(cons_rx_buf, mapping),
601d3d18 2927 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
b6016b76 2928
bb4f98ab 2929 rxr->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76 2930
236b6394 2931 prod_rx_buf->skb = skb;
a33fa66b 2932 prod_rx_buf->desc = (struct l2_fhdr *) skb->data;
b6016b76 2933
236b6394
MC		 2934 if (cons == prod)
2935 return;
b6016b76 2936
1a4ccc2d
FT		 2937 dma_unmap_addr_set(prod_rx_buf, mapping,
2938 dma_unmap_addr(cons_rx_buf, mapping));
236b6394 2939
bb4f98ab
MC		 2940 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2941 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
236b6394
MC		 2942 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2943 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
b6016b76
MC		 2944}
2945
85833c62 2946static int
bb4f98ab 2947bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
a1f60190
MC		 2948 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2949 u32 ring_idx)
85833c62
MC		 2950{
2951 int err;
2952 u16 prod = ring_idx & 0xffff;
2953
a2df00aa 2954 err = bnx2_alloc_rx_skb(bp, rxr, prod, GFP_ATOMIC);
85833c62 2955 if (unlikely(err)) {
bb4f98ab 2956 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
1db82f2a
MC		 2957 if (hdr_len) {
2958 unsigned int raw_len = len + 4;
2959 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2960
bb4f98ab 2961 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
1db82f2a 2962 }
85833c62
MC		 2963 return err;
2964 }
2965
d89cb6af 2966 skb_reserve(skb, BNX2_RX_OFFSET);
36227e88 2967 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
85833c62
MC		 2968 PCI_DMA_FROMDEVICE);
2969
1db82f2a
MC		 2970 if (hdr_len == 0) {
2971 skb_put(skb, len);
2972 return 0;
2973 } else {
2974 unsigned int i, frag_len, frag_size, pages;
2975 struct sw_pg *rx_pg;
bb4f98ab
MC		 2976 u16 pg_cons = rxr->rx_pg_cons;
2977 u16 pg_prod = rxr->rx_pg_prod;
1db82f2a
MC		 2978
2979 frag_size = len + 4 - hdr_len;
2980 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2981 skb_put(skb, hdr_len);
2982
2983 for (i = 0; i < pages; i++) {
3d16af86
BL		 2984 dma_addr_t mapping_old;
2985
1db82f2a
MC		 2986 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2987 if (unlikely(frag_len <= 4)) {
2988 unsigned int tail = 4 - frag_len;
2989
bb4f98ab
MC		 2990 rxr->rx_pg_cons = pg_cons;
2991 rxr->rx_pg_prod = pg_prod;
2992 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
a1f60190 2993 pages - i);
1db82f2a
MC		 2994 skb->len -= tail;
2995 if (i == 0) {
2996 skb->tail -= tail;
2997 } else {
2998 skb_frag_t *frag =
2999 &skb_shinfo(skb)->frags[i - 1];
3000 frag->size -= tail;
3001 skb->data_len -= tail;
3002 skb->truesize -= tail;
3003 }
3004 return 0;
3005 }
bb4f98ab 3006 rx_pg = &rxr->rx_pg_ring[pg_cons];
1db82f2a 3007
3d16af86
BL		 3008 /* Don't unmap yet. If we're unable to allocate a new
3009 * page, we need to recycle the page and the DMA addr.
3010 */
1a4ccc2d 3011 mapping_old = dma_unmap_addr(rx_pg, mapping);
1db82f2a
MC		 3012 if (i == pages - 1)
3013 frag_len -= 4;
3014
3015 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3016 rx_pg->page = NULL;
3017
bb4f98ab 3018 err = bnx2_alloc_rx_page(bp, rxr,
a2df00aa
SG		 3019 RX_PG_RING_IDX(pg_prod),
3020 GFP_ATOMIC);
1db82f2a 3021 if (unlikely(err)) {
bb4f98ab
MC		 3022 rxr->rx_pg_cons = pg_cons;
3023 rxr->rx_pg_prod = pg_prod;
3024 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
a1f60190 3025 pages - i);
1db82f2a
MC		 3026 return err;
3027 }
3028
36227e88 3029 dma_unmap_page(&bp->pdev->dev, mapping_old,
3d16af86
BL		 3030 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3031
1db82f2a
MC		 3032 frag_size -= frag_len;
3033 skb->data_len += frag_len;
3034 skb->truesize += frag_len;
3035 skb->len += frag_len;
3036
3037 pg_prod = NEXT_RX_BD(pg_prod);
3038 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
3039 }
bb4f98ab
MC		 3040 rxr->rx_pg_prod = pg_prod;
3041 rxr->rx_pg_cons = pg_cons;
1db82f2a 3042 }
85833c62
MC		 3043 return 0;
3044}
3045
c09c2627 3046static inline u16
35efa7c1 3047bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
c09c2627 3048{
bb4f98ab
MC		 3049 u16 cons;
3050
43e80b89
MC		 3051 /* Tell compiler that status block fields can change. */
3052 barrier();
3053 cons = *bnapi->hw_rx_cons_ptr;
581daf7e 3054 barrier();
c09c2627
MC		 3055 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
3056 cons++;
3057 return cons;
3058}
3059
b6016b76 3060static int
35efa7c1 3061bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76 3062{
bb4f98ab 3063 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
b6016b76
MC		 3064 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3065 struct l2_fhdr *rx_hdr;
1db82f2a 3066 int rx_pkt = 0, pg_ring_used = 0;
b6016b76 3067
35efa7c1 3068 hw_cons = bnx2_get_hw_rx_cons(bnapi);
bb4f98ab
MC		 3069 sw_cons = rxr->rx_cons;
3070 sw_prod = rxr->rx_prod;
b6016b76
MC		 3071
3072 /* Memory barrier necessary as speculative reads of the rx
3073 * buffer can be ahead of the index in the status block
3074 */
3075 rmb();
3076 while (sw_cons != hw_cons) {
1db82f2a 3077 unsigned int len, hdr_len;
ade2bfe7 3078 u32 status;
a33fa66b 3079 struct sw_bd *rx_buf, *next_rx_buf;
b6016b76 3080 struct sk_buff *skb;
236b6394 3081 dma_addr_t dma_addr;
b6016b76
MC		 3082
3083 sw_ring_cons = RX_RING_IDX(sw_cons);
3084 sw_ring_prod = RX_RING_IDX(sw_prod);
3085
bb4f98ab 3086 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
b6016b76 3087 skb = rx_buf->skb;
a33fa66b 3088 prefetchw(skb);
236b6394 3089
aabef8b2
FT		 3090 next_rx_buf =
3091 &rxr->rx_buf_ring[RX_RING_IDX(NEXT_RX_BD(sw_cons))];
3092 prefetch(next_rx_buf->desc);
3093
236b6394
MC		 3094 rx_buf->skb = NULL;
3095
1a4ccc2d 3096 dma_addr = dma_unmap_addr(rx_buf, mapping);
236b6394 3097
36227e88 3098 dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr,
601d3d18
BL		 3099 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3100 PCI_DMA_FROMDEVICE);
b6016b76 3101
a33fa66b 3102 rx_hdr = rx_buf->desc;
1db82f2a 3103 len = rx_hdr->l2_fhdr_pkt_len;
990ec380 3104 status = rx_hdr->l2_fhdr_status;
b6016b76 3105
1db82f2a
MC		 3106 hdr_len = 0;
3107 if (status & L2_FHDR_STATUS_SPLIT) {
3108 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3109 pg_ring_used = 1;
3110 } else if (len > bp->rx_jumbo_thresh) {
3111 hdr_len = bp->rx_jumbo_thresh;
3112 pg_ring_used = 1;
3113 }
3114
990ec380
MC		 3115 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3116 L2_FHDR_ERRORS_PHY_DECODE |
3117 L2_FHDR_ERRORS_ALIGNMENT |
3118 L2_FHDR_ERRORS_TOO_SHORT |
3119 L2_FHDR_ERRORS_GIANT_FRAME))) {
3120
3121 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3122 sw_ring_prod);
3123 if (pg_ring_used) {
3124 int pages;
3125
3126 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3127
3128 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3129 }
3130 goto next_rx;
3131 }
3132
1db82f2a 3133 len -= 4;
b6016b76 3134
5d5d0015 3135 if (len <= bp->rx_copy_thresh) {
b6016b76
MC		 3136 struct sk_buff *new_skb;
3137
f22828e8 3138 new_skb = netdev_alloc_skb(bp->dev, len + 6);
85833c62 3139 if (new_skb == NULL) {
bb4f98ab 3140 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
85833c62
MC		 3141 sw_ring_prod);
3142 goto next_rx;
3143 }
b6016b76
MC		 3144
3145 /* aligned copy */
d89cb6af 3146 skb_copy_from_linear_data_offset(skb,
f22828e8
MC		 3147 BNX2_RX_OFFSET - 6,
3148 new_skb->data, len + 6);
3149 skb_reserve(new_skb, 6);
b6016b76 3150 skb_put(new_skb, len);
b6016b76 3151
bb4f98ab 3152 bnx2_reuse_rx_skb(bp, rxr, skb,
b6016b76
MC		 3153 sw_ring_cons, sw_ring_prod);
3154
3155 skb = new_skb;
bb4f98ab 3156 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
a1f60190 3157 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
b6016b76 3158 goto next_rx;
b6016b76 3159
f22828e8 3160 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
7d0fd211
JG		 3161 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG))
3162 __vlan_hwaccel_put_tag(skb, rx_hdr->l2_fhdr_vlan_tag);
f22828e8 3163
b6016b76
MC		 3164 skb->protocol = eth_type_trans(skb, bp->dev);
3165
3166 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
d1e100ba 3167 (ntohs(skb->protocol) != 0x8100)) {
b6016b76 3168
745720e5 3169 dev_kfree_skb(skb);
b6016b76
MC		 3170 goto next_rx;
3171
3172 }
3173
bc8acf2c 3174 skb_checksum_none_assert(skb);
b6016b76
MC		 3175 if (bp->rx_csum &&
3176 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3177 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3178
ade2bfe7
MC		 3179 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3180 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
b6016b76
MC		 3181 skb->ip_summed = CHECKSUM_UNNECESSARY;
3182 }
fdc8541d
MC		 3183 if ((bp->dev->features & NETIF_F_RXHASH) &&
3184 ((status & L2_FHDR_STATUS_USE_RXHASH) ==
3185 L2_FHDR_STATUS_USE_RXHASH))
3186 skb->rxhash = rx_hdr->l2_fhdr_hash;
b6016b76 3187
0c8dfc83 3188 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
7d0fd211 3189 napi_gro_receive(&bnapi->napi, skb);
b6016b76
MC		 3190 rx_pkt++;
3191
3192next_rx:
b6016b76
MC		 3193 sw_cons = NEXT_RX_BD(sw_cons);
3194 sw_prod = NEXT_RX_BD(sw_prod);
3195
3196 if ((rx_pkt == budget))
3197 break;
f4e418f7
MC		 3198
3199 /* Refresh hw_cons to see if there is new work */
3200 if (sw_cons == hw_cons) {
35efa7c1 3201 hw_cons = bnx2_get_hw_rx_cons(bnapi);
f4e418f7
MC		 3202 rmb();
3203 }
b6016b76 3204 }
bb4f98ab
MC		 3205 rxr->rx_cons = sw_cons;
3206 rxr->rx_prod = sw_prod;
b6016b76 3207
1db82f2a 3208 if (pg_ring_used)
bb4f98ab 3209 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
1db82f2a 3210
bb4f98ab 3211 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
b6016b76 3212
bb4f98ab 3213 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
b6016b76
MC		 3214
3215 mmiowb();
3216
3217 return rx_pkt;
3218
3219}
3220
3221/* MSI ISR - The only difference between this and the INTx ISR
3222 * is that the MSI interrupt is always serviced.
3223 */
3224static irqreturn_t
7d12e780 3225bnx2_msi(int irq, void *dev_instance)
b6016b76 3226{
f0ea2e63
MC		 3227 struct bnx2_napi *bnapi = dev_instance;
3228 struct bnx2 *bp = bnapi->bp;
b6016b76 3229
43e80b89 3230 prefetch(bnapi->status_blk.msi);
b6016b76
MC		 3231 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3232 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3233 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3234
3235 /* Return here if interrupt is disabled. */
73eef4cd
MC		 3236 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3237 return IRQ_HANDLED;
b6016b76 3238
288379f0 3239 napi_schedule(&bnapi->napi);
b6016b76 3240
73eef4cd 3241 return IRQ_HANDLED;
b6016b76
MC		 3242}
3243
8e6a72c4
MC		 3244static irqreturn_t
3245bnx2_msi_1shot(int irq, void *dev_instance)
3246{
f0ea2e63
MC		 3247 struct bnx2_napi *bnapi = dev_instance;
3248 struct bnx2 *bp = bnapi->bp;
8e6a72c4 3249
43e80b89 3250 prefetch(bnapi->status_blk.msi);
8e6a72c4
MC		 3251
3252 /* Return here if interrupt is disabled. */
3253 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3254 return IRQ_HANDLED;
3255
288379f0 3256 napi_schedule(&bnapi->napi);
8e6a72c4
MC		 3257
3258 return IRQ_HANDLED;
3259}
3260
b6016b76 3261static irqreturn_t
7d12e780 3262bnx2_interrupt(int irq, void *dev_instance)
b6016b76 3263{
f0ea2e63
MC		 3264 struct bnx2_napi *bnapi = dev_instance;
3265 struct bnx2 *bp = bnapi->bp;
43e80b89 3266 struct status_block *sblk = bnapi->status_blk.msi;
b6016b76
MC		 3267
3268 /* When using INTx, it is possible for the interrupt to arrive
3269 * at the CPU before the status block posted prior to the
3270 * interrupt. Reading a register will flush the status block.
3271 * When using MSI, the MSI message will always complete after
3272 * the status block write.
3273 */
35efa7c1 3274 if ((sblk->status_idx == bnapi->last_status_idx) &&
b6016b76
MC		 3275 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3276 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
73eef4cd 3277 return IRQ_NONE;
b6016b76
MC		 3278
3279 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3280 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3281 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3282
b8a7ce7b
MC		 3283 /* Read back to deassert IRQ immediately to avoid too many
3284 * spurious interrupts.
3285 */
3286 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3287
b6016b76 3288 /* Return here if interrupt is shared and is disabled. */
73eef4cd
MC		 3289 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3290 return IRQ_HANDLED;
b6016b76 3291
288379f0 3292 if (napi_schedule_prep(&bnapi->napi)) {
35efa7c1 3293 bnapi->last_status_idx = sblk->status_idx;
288379f0 3294 __napi_schedule(&bnapi->napi);
b8a7ce7b 3295 }
b6016b76 3296
73eef4cd 3297 return IRQ_HANDLED;
b6016b76
MC		 3298}
3299
f4e418f7 3300static inline int
43e80b89 3301bnx2_has_fast_work(struct bnx2_napi *bnapi)
f4e418f7 3302{
35e9010b 3303 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
bb4f98ab 3304 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
f4e418f7 3305
bb4f98ab 3306 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
35e9010b 3307 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
f4e418f7 3308 return 1;
43e80b89
MC		 3309 return 0;
3310}
3311
3312#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3313 STATUS_ATTN_BITS_TIMER_ABORT)
3314
3315static inline int
3316bnx2_has_work(struct bnx2_napi *bnapi)
3317{
3318 struct status_block *sblk = bnapi->status_blk.msi;
3319
3320 if (bnx2_has_fast_work(bnapi))
3321 return 1;
f4e418f7 3322
4edd473f
MC		 3323#ifdef BCM_CNIC
3324 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3325 return 1;
3326#endif
3327
da3e4fbe
MC		 3328 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3329 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
f4e418f7
MC		 3330 return 1;
3331
3332 return 0;
3333}
3334
efba0180
MC		 3335static void
3336bnx2_chk_missed_msi(struct bnx2 *bp)
3337{
3338 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3339 u32 msi_ctrl;
3340
3341 if (bnx2_has_work(bnapi)) {
3342 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3343 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3344 return;
3345
3346 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3347 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3348 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3349 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3350 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3351 }
3352 }
3353
3354 bp->idle_chk_status_idx = bnapi->last_status_idx;
3355}
3356
4edd473f
MC		 3357#ifdef BCM_CNIC
3358static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3359{
3360 struct cnic_ops *c_ops;
3361
3362 if (!bnapi->cnic_present)
3363 return;
3364
3365 rcu_read_lock();
3366 c_ops = rcu_dereference(bp->cnic_ops);
3367 if (c_ops)
3368 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3369 bnapi->status_blk.msi);
3370 rcu_read_unlock();
3371}
3372#endif
3373
43e80b89 3374static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
b6016b76 3375{
43e80b89 3376 struct status_block *sblk = bnapi->status_blk.msi;
da3e4fbe
MC		 3377 u32 status_attn_bits = sblk->status_attn_bits;
3378 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
b6016b76 3379
da3e4fbe
MC		 3380 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3381 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
b6016b76 3382
35efa7c1 3383 bnx2_phy_int(bp, bnapi);
bf5295bb
MC		 3384
3385 /* This is needed to take care of transient status
3386 * during link changes.
3387 */
3388 REG_WR(bp, BNX2_HC_COMMAND,
3389 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3390 REG_RD(bp, BNX2_HC_COMMAND);
b6016b76 3391 }
43e80b89
MC		 3392}
3393
3394static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3395 int work_done, int budget)
3396{
3397 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3398 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
b6016b76 3399
35e9010b 3400 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
57851d84 3401 bnx2_tx_int(bp, bnapi, 0);
b6016b76 3402
bb4f98ab 3403 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
35efa7c1 3404 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
6aa20a22 3405
6f535763
DM		 3406 return work_done;
3407}
3408
f0ea2e63
MC		 3409static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3410{
3411 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3412 struct bnx2 *bp = bnapi->bp;
3413 int work_done = 0;
3414 struct status_block_msix *sblk = bnapi->status_blk.msix;
3415
3416 while (1) {
3417 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3418 if (unlikely(work_done >= budget))
3419 break;
3420
3421 bnapi->last_status_idx = sblk->status_idx;
3422 /* status idx must be read before checking for more work. */
3423 rmb();
3424 if (likely(!bnx2_has_fast_work(bnapi))) {
3425
288379f0 3426 napi_complete(napi);
f0ea2e63
MC		 3427 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3428 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3429 bnapi->last_status_idx);
3430 break;
3431 }
3432 }
3433 return work_done;
3434}
3435
6f535763
DM		 3436static int bnx2_poll(struct napi_struct *napi, int budget)
3437{
35efa7c1
MC		 3438 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3439 struct bnx2 *bp = bnapi->bp;
6f535763 3440 int work_done = 0;
43e80b89 3441 struct status_block *sblk = bnapi->status_blk.msi;
6f535763
DM		 3442
3443 while (1) {
43e80b89
MC		 3444 bnx2_poll_link(bp, bnapi);
3445
35efa7c1 3446 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
f4e418f7 3447
4edd473f
MC		 3448#ifdef BCM_CNIC
3449 bnx2_poll_cnic(bp, bnapi);
3450#endif
3451
35efa7c1 3452 /* bnapi->last_status_idx is used below to tell the hw how
6dee6421
MC		 3453 * much work has been processed, so we must read it before
3454 * checking for more work.
3455 */
35efa7c1 3456 bnapi->last_status_idx = sblk->status_idx;
efba0180
MC		 3457
3458 if (unlikely(work_done >= budget))
3459 break;
3460
6dee6421 3461 rmb();
35efa7c1 3462 if (likely(!bnx2_has_work(bnapi))) {
288379f0 3463 napi_complete(napi);
f86e82fb 3464 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
6f535763
DM		 3465 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3466 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3467 bnapi->last_status_idx);
6dee6421 3468 break;
6f535763 3469 }
1269a8a6
MC		 3470 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3471 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
6f535763 3472 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
35efa7c1 3473 bnapi->last_status_idx);
1269a8a6 3474
6f535763
DM		 3475 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3476 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3477 bnapi->last_status_idx);
6f535763
DM		 3478 break;
3479 }
b6016b76
MC		 3480 }
3481
bea3348e 3482 return work_done;
b6016b76
MC		 3483}
3484
932ff279 3485/* Called with rtnl_lock from vlan functions and also netif_tx_lock
b6016b76
MC		 3486 * from set_multicast.
3487 */
3488static void
3489bnx2_set_rx_mode(struct net_device *dev)
3490{
972ec0d4 3491 struct bnx2 *bp = netdev_priv(dev);
b6016b76 3492 u32 rx_mode, sort_mode;
ccffad25 3493 struct netdev_hw_addr *ha;
b6016b76 3494 int i;
b6016b76 3495
9f52b564
MC		 3496 if (!netif_running(dev))
3497 return;
3498
c770a65c 3499 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 3500
3501 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3502 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3503 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
7d0fd211
JG		 3504 if (!(dev->features & NETIF_F_HW_VLAN_RX) &&
3505 (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
b6016b76 3506 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76
MC		 3507 if (dev->flags & IFF_PROMISC) {
3508 /* Promiscuous mode. */
3509 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
7510873d
MC		 3510 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3511 BNX2_RPM_SORT_USER0_PROM_VLAN;
b6016b76
MC		 3512 }
3513 else if (dev->flags & IFF_ALLMULTI) {
3514 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3515 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3516 0xffffffff);
3517 }
3518 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3519 }
3520 else {
3521 /* Accept one or more multicast(s). */
b6016b76
MC		 3522 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3523 u32 regidx;
3524 u32 bit;
3525 u32 crc;
3526
3527 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3528
22bedad3
JP		 3529 netdev_for_each_mc_addr(ha, dev) {
3530 crc = ether_crc_le(ETH_ALEN, ha->addr);
b6016b76
MC		 3531 bit = crc & 0xff;
3532 regidx = (bit & 0xe0) >> 5;
3533 bit &= 0x1f;
3534 mc_filter[regidx] |= (1 << bit);
3535 }
3536
3537 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3538 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3539 mc_filter[i]);
3540 }
3541
3542 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3543 }
3544
32e7bfc4 3545 if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) {
5fcaed01
BL		 3546 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3547 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3548 BNX2_RPM_SORT_USER0_PROM_VLAN;
3549 } else if (!(dev->flags & IFF_PROMISC)) {
5fcaed01 3550 /* Add all entries into to the match filter list */
ccffad25 3551 i = 0;
32e7bfc4 3552 netdev_for_each_uc_addr(ha, dev) {
ccffad25 3553 bnx2_set_mac_addr(bp, ha->addr,
5fcaed01
BL		 3554 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3555 sort_mode |= (1 <<
3556 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
ccffad25 3557 i++;
5fcaed01
BL		 3558 }
3559
3560 }
3561
b6016b76
MC		 3562 if (rx_mode != bp->rx_mode) {
3563 bp->rx_mode = rx_mode;
3564 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3565 }
3566
3567 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3568 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3569 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3570
c770a65c 3571 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3572}
3573
57579f76
MC		 3574static int __devinit
3575check_fw_section(const struct firmware *fw,
3576 const struct bnx2_fw_file_section *section,
3577 u32 alignment, bool non_empty)
3578{
3579 u32 offset = be32_to_cpu(section->offset);
3580 u32 len = be32_to_cpu(section->len);
3581
3582 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3583 return -EINVAL;
3584 if ((non_empty && len == 0) || len > fw->size - offset ||
3585 len & (alignment - 1))
3586 return -EINVAL;
3587 return 0;
3588}
3589
3590static int __devinit
3591check_mips_fw_entry(const struct firmware *fw,
3592 const struct bnx2_mips_fw_file_entry *entry)
3593{
3594 if (check_fw_section(fw, &entry->text, 4, true) ||
3595 check_fw_section(fw, &entry->data, 4, false) ||
3596 check_fw_section(fw, &entry->rodata, 4, false))
3597 return -EINVAL;
3598 return 0;
3599}
3600
3601static int __devinit
3602bnx2_request_firmware(struct bnx2 *bp)
b6016b76 3603{
57579f76 3604 const char *mips_fw_file, *rv2p_fw_file;
5ee1c326
BB		 3605 const struct bnx2_mips_fw_file *mips_fw;
3606 const struct bnx2_rv2p_fw_file *rv2p_fw;
57579f76
MC		 3607 int rc;
3608
3609 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3610 mips_fw_file = FW_MIPS_FILE_09;
078b0735
MC		 3611 if ((CHIP_ID(bp) == CHIP_ID_5709_A0) ||
3612 (CHIP_ID(bp) == CHIP_ID_5709_A1))
3613 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3614 else
3615 rv2p_fw_file = FW_RV2P_FILE_09;
57579f76
MC		 3616 } else {
3617 mips_fw_file = FW_MIPS_FILE_06;
3618 rv2p_fw_file = FW_RV2P_FILE_06;
3619 }
3620
3621 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3622 if (rc) {
3a9c6a49 3623 pr_err("Can't load firmware file \"%s\"\n", mips_fw_file);
57579f76
MC		 3624 return rc;
3625 }
3626
3627 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3628 if (rc) {
3a9c6a49 3629 pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file);
57579f76
MC		 3630 return rc;
3631 }
5ee1c326
BB		 3632 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3633 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3634 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3635 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3636 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3637 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3638 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3639 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3a9c6a49 3640 pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file);
57579f76
MC		 3641 return -EINVAL;
3642 }
5ee1c326
BB		 3643 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3644 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3645 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3a9c6a49 3646 pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file);
57579f76
MC		 3647 return -EINVAL;
3648 }
3649
3650 return 0;
3651}
3652
3653static u32
3654rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3655{
3656 switch (idx) {
3657 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3658 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3659 rv2p_code |= RV2P_BD_PAGE_SIZE;
3660 break;
3661 }
3662 return rv2p_code;
3663}
3664
3665static int
3666load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3667 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3668{
3669 u32 rv2p_code_len, file_offset;
3670 __be32 *rv2p_code;
b6016b76 3671 int i;
57579f76
MC		 3672 u32 val, cmd, addr;
3673
3674 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3675 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3676
3677 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
b6016b76 3678
57579f76
MC		 3679 if (rv2p_proc == RV2P_PROC1) {
3680 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3681 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3682 } else {
3683 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3684 addr = BNX2_RV2P_PROC2_ADDR_CMD;
d25be1d3 3685 }
b6016b76
MC		 3686
3687 for (i = 0; i < rv2p_code_len; i += 8) {
57579f76 3688 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
b6016b76 3689 rv2p_code++;
57579f76 3690 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
b6016b76
MC		 3691 rv2p_code++;
3692
57579f76
MC		 3693 val = (i / 8) | cmd;
3694 REG_WR(bp, addr, val);
3695 }
3696
3697 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3698 for (i = 0; i < 8; i++) {
3699 u32 loc, code;
3700
3701 loc = be32_to_cpu(fw_entry->fixup[i]);
3702 if (loc && ((loc * 4) < rv2p_code_len)) {
3703 code = be32_to_cpu(*(rv2p_code + loc - 1));
3704 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3705 code = be32_to_cpu(*(rv2p_code + loc));
3706 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3707 REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3708
3709 val = (loc / 2) | cmd;
3710 REG_WR(bp, addr, val);
b6016b76
MC		 3711 }
3712 }
3713
3714 /* Reset the processor, un-stall is done later. */
3715 if (rv2p_proc == RV2P_PROC1) {
3716 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3717 }
3718 else {
3719 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3720 }
57579f76
MC		 3721
3722 return 0;
b6016b76
MC		 3723}
3724
af3ee519 3725static int
57579f76
MC		 3726load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3727 const struct bnx2_mips_fw_file_entry *fw_entry)
b6016b76 3728{
57579f76
MC		 3729 u32 addr, len, file_offset;
3730 __be32 *data;
b6016b76
MC		 3731 u32 offset;
3732 u32 val;
3733
3734 /* Halt the CPU. */
2726d6e1 3735 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3736 val |= cpu_reg->mode_value_halt;
2726d6e1
MC		 3737 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3738 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
b6016b76
MC		 3739
3740 /* Load the Text area. */
57579f76
MC		 3741 addr = be32_to_cpu(fw_entry->text.addr);
3742 len = be32_to_cpu(fw_entry->text.len);
3743 file_offset = be32_to_cpu(fw_entry->text.offset);
3744 data = (__be32 *)(bp->mips_firmware->data + file_offset);
ea1f8d5c 3745
57579f76
MC		 3746 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3747 if (len) {
b6016b76
MC		 3748 int j;
3749
57579f76
MC		 3750 for (j = 0; j < (len / 4); j++, offset += 4)
3751 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3752 }
3753
57579f76
MC		 3754 /* Load the Data area. */
3755 addr = be32_to_cpu(fw_entry->data.addr);
3756 len = be32_to_cpu(fw_entry->data.len);
3757 file_offset = be32_to_cpu(fw_entry->data.offset);
3758 data = (__be32 *)(bp->mips_firmware->data + file_offset);
b6016b76 3759
57579f76
MC		 3760 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3761 if (len) {
b6016b76
MC		 3762 int j;
3763
57579f76
MC		 3764 for (j = 0; j < (len / 4); j++, offset += 4)
3765 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3766 }
3767
3768 /* Load the Read-Only area. */
57579f76
MC		 3769 addr = be32_to_cpu(fw_entry->rodata.addr);
3770 len = be32_to_cpu(fw_entry->rodata.len);
3771 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3772 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3773
3774 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3775 if (len) {
b6016b76
MC		 3776 int j;
3777
57579f76
MC		 3778 for (j = 0; j < (len / 4); j++, offset += 4)
3779 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3780 }
3781
3782 /* Clear the pre-fetch instruction. */
2726d6e1 3783 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
57579f76
MC		 3784
3785 val = be32_to_cpu(fw_entry->start_addr);
3786 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
b6016b76
MC		 3787
3788 /* Start the CPU. */
2726d6e1 3789 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3790 val &= ~cpu_reg->mode_value_halt;
2726d6e1
MC		 3791 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3792 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
af3ee519
MC		 3793
3794 return 0;
b6016b76
MC		 3795}
3796
fba9fe91 3797static int
b6016b76
MC		 3798bnx2_init_cpus(struct bnx2 *bp)
3799{
57579f76
MC		 3800 const struct bnx2_mips_fw_file *mips_fw =
3801 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3802 const struct bnx2_rv2p_fw_file *rv2p_fw =
3803 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3804 int rc;
b6016b76
MC		 3805
3806 /* Initialize the RV2P processor. */
57579f76
MC		 3807 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3808 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
b6016b76
MC		 3809
3810 /* Initialize the RX Processor. */
57579f76 3811 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
fba9fe91
MC		 3812 if (rc)
3813 goto init_cpu_err;
3814
b6016b76 3815 /* Initialize the TX Processor. */
57579f76 3816 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
fba9fe91
MC		 3817 if (rc)
3818 goto init_cpu_err;
3819
b6016b76 3820 /* Initialize the TX Patch-up Processor. */
57579f76 3821 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
fba9fe91
MC		 3822 if (rc)
3823 goto init_cpu_err;
3824
b6016b76 3825 /* Initialize the Completion Processor. */
57579f76 3826 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
fba9fe91
MC		 3827 if (rc)
3828 goto init_cpu_err;
3829
d43584c8 3830 /* Initialize the Command Processor. */
57579f76 3831 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
b6016b76 3832
fba9fe91 3833init_cpu_err:
fba9fe91 3834 return rc;
b6016b76
MC		 3835}
3836
3837static int
829ca9a3 3838bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
b6016b76
MC		 3839{
3840 u16 pmcsr;
3841
3842 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3843
3844 switch (state) {
829ca9a3 3845 case PCI_D0: {
b6016b76
MC		 3846 u32 val;
3847
3848 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3849 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3850 PCI_PM_CTRL_PME_STATUS);
3851
3852 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3853 /* delay required during transition out of D3hot */
3854 msleep(20);
3855
3856 val = REG_RD(bp, BNX2_EMAC_MODE);
3857 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3858 val &= ~BNX2_EMAC_MODE_MPKT;
3859 REG_WR(bp, BNX2_EMAC_MODE, val);
3860
3861 val = REG_RD(bp, BNX2_RPM_CONFIG);
3862 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3863 REG_WR(bp, BNX2_RPM_CONFIG, val);
3864 break;
3865 }
829ca9a3 3866 case PCI_D3hot: {
b6016b76
MC		 3867 int i;
3868 u32 val, wol_msg;
3869
3870 if (bp->wol) {
3871 u32 advertising;
3872 u8 autoneg;
3873
3874 autoneg = bp->autoneg;
3875 advertising = bp->advertising;
3876
239cd343
MC		 3877 if (bp->phy_port == PORT_TP) {
3878 bp->autoneg = AUTONEG_SPEED;
3879 bp->advertising = ADVERTISED_10baseT_Half |
3880 ADVERTISED_10baseT_Full |
3881 ADVERTISED_100baseT_Half |
3882 ADVERTISED_100baseT_Full |
3883 ADVERTISED_Autoneg;
3884 }
b6016b76 3885
239cd343
MC		 3886 spin_lock_bh(&bp->phy_lock);
3887 bnx2_setup_phy(bp, bp->phy_port);
3888 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3889
3890 bp->autoneg = autoneg;
3891 bp->advertising = advertising;
3892
5fcaed01 3893 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 3894
3895 val = REG_RD(bp, BNX2_EMAC_MODE);
3896
3897 /* Enable port mode. */
3898 val &= ~BNX2_EMAC_MODE_PORT;
239cd343 3899 val |= BNX2_EMAC_MODE_MPKT_RCVD |
b6016b76 3900 BNX2_EMAC_MODE_ACPI_RCVD |
b6016b76 3901 BNX2_EMAC_MODE_MPKT;
239cd343
MC		 3902 if (bp->phy_port == PORT_TP)
3903 val |= BNX2_EMAC_MODE_PORT_MII;
3904 else {
3905 val |= BNX2_EMAC_MODE_PORT_GMII;
3906 if (bp->line_speed == SPEED_2500)
3907 val |= BNX2_EMAC_MODE_25G_MODE;
3908 }
b6016b76
MC		 3909
3910 REG_WR(bp, BNX2_EMAC_MODE, val);
3911
3912 /* receive all multicast */
3913 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3914 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3915 0xffffffff);
3916 }
3917 REG_WR(bp, BNX2_EMAC_RX_MODE,
3918 BNX2_EMAC_RX_MODE_SORT_MODE);
3919
3920 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3921 BNX2_RPM_SORT_USER0_MC_EN;
3922 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3923 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3924 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3925 BNX2_RPM_SORT_USER0_ENA);
3926
3927 /* Need to enable EMAC and RPM for WOL. */
3928 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3929 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3930 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3931 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3932
3933 val = REG_RD(bp, BNX2_RPM_CONFIG);
3934 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3935 REG_WR(bp, BNX2_RPM_CONFIG, val);
3936
3937 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3938 }
3939 else {
3940 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3941 }
3942
f86e82fb 3943 if (!(bp->flags & BNX2_FLAG_NO_WOL))
a2f13890
MC		 3944 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3945 1, 0);
b6016b76
MC		 3946
3947 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3948 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3949 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3950
3951 if (bp->wol)
3952 pmcsr |= 3;
3953 }
3954 else {
3955 pmcsr |= 3;
3956 }
3957 if (bp->wol) {
3958 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3959 }
3960 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3961 pmcsr);
3962
3963 /* No more memory access after this point until
3964 * device is brought back to D0.
3965 */
3966 udelay(50);
3967 break;
3968 }
3969 default:
3970 return -EINVAL;
3971 }
3972 return 0;
3973}
3974
3975static int
3976bnx2_acquire_nvram_lock(struct bnx2 *bp)
3977{
3978 u32 val;
3979 int j;
3980
3981 /* Request access to the flash interface. */
3982 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3983 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3984 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3985 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3986 break;
3987
3988 udelay(5);
3989 }
3990
3991 if (j >= NVRAM_TIMEOUT_COUNT)
3992 return -EBUSY;
3993
3994 return 0;
3995}
3996
3997static int
3998bnx2_release_nvram_lock(struct bnx2 *bp)
3999{
4000 int j;
4001 u32 val;
4002
4003 /* Relinquish nvram interface. */
4004 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4005
4006 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4007 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4008 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4009 break;
4010
4011 udelay(5);
4012 }
4013
4014 if (j >= NVRAM_TIMEOUT_COUNT)
4015 return -EBUSY;
4016
4017 return 0;
4018}
4019
4020
4021static int
4022bnx2_enable_nvram_write(struct bnx2 *bp)
4023{
4024 u32 val;
4025
4026 val = REG_RD(bp, BNX2_MISC_CFG);
4027 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4028
e30372c9 4029 if (bp->flash_info->flags & BNX2_NV_WREN) {
b6016b76
MC		 4030 int j;
4031
4032 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4033 REG_WR(bp, BNX2_NVM_COMMAND,
4034 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
4035
4036 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4037 udelay(5);
4038
4039 val = REG_RD(bp, BNX2_NVM_COMMAND);
4040 if (val & BNX2_NVM_COMMAND_DONE)
4041 break;
4042 }
4043
4044 if (j >= NVRAM_TIMEOUT_COUNT)
4045 return -EBUSY;
4046 }
4047 return 0;
4048}
4049
4050static void
4051bnx2_disable_nvram_write(struct bnx2 *bp)
4052{
4053 u32 val;
4054
4055 val = REG_RD(bp, BNX2_MISC_CFG);
4056 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4057}
4058
4059
4060static void
4061bnx2_enable_nvram_access(struct bnx2 *bp)
4062{
4063 u32 val;
4064
4065 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4066 /* Enable both bits, even on read. */
6aa20a22 4067 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 4068 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4069}
4070
4071static void
4072bnx2_disable_nvram_access(struct bnx2 *bp)
4073{
4074 u32 val;
4075
4076 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4077 /* Disable both bits, even after read. */
6aa20a22 4078 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 4079 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4080 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4081}
4082
4083static int
4084bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4085{
4086 u32 cmd;
4087 int j;
4088
e30372c9 4089 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
b6016b76
MC		 4090 /* Buffered flash, no erase needed */
4091 return 0;
4092
4093 /* Build an erase command */
4094 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4095 BNX2_NVM_COMMAND_DOIT;
4096
4097 /* Need to clear DONE bit separately. */
4098 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4099
4100 /* Address of the NVRAM to read from. */
4101 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4102
4103 /* Issue an erase command. */
4104 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4105
4106 /* Wait for completion. */
4107 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4108 u32 val;
4109
4110 udelay(5);
4111
4112 val = REG_RD(bp, BNX2_NVM_COMMAND);
4113 if (val & BNX2_NVM_COMMAND_DONE)
4114 break;
4115 }
4116
4117 if (j >= NVRAM_TIMEOUT_COUNT)
4118 return -EBUSY;
4119
4120 return 0;
4121}
4122
4123static int
4124bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4125{
4126 u32 cmd;
4127 int j;
4128
4129 /* Build the command word. */
4130 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4131
e30372c9
MC		 4132 /* Calculate an offset of a buffered flash, not needed for 5709. */
4133 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 4134 offset = ((offset / bp->flash_info->page_size) <<
4135 bp->flash_info->page_bits) +
4136 (offset % bp->flash_info->page_size);
4137 }
4138
4139 /* Need to clear DONE bit separately. */
4140 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4141
4142 /* Address of the NVRAM to read from. */
4143 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4144
4145 /* Issue a read command. */
4146 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4147
4148 /* Wait for completion. */
4149 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4150 u32 val;
4151
4152 udelay(5);
4153
4154 val = REG_RD(bp, BNX2_NVM_COMMAND);
4155 if (val & BNX2_NVM_COMMAND_DONE) {
b491edd5
AV		 4156 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
4157 memcpy(ret_val, &v, 4);
b6016b76
MC		 4158 break;
4159 }
4160 }
4161 if (j >= NVRAM_TIMEOUT_COUNT)
4162 return -EBUSY;
4163
4164 return 0;
4165}
4166
4167
4168static int
4169bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4170{
b491edd5
AV		 4171 u32 cmd;
4172 __be32 val32;
b6016b76
MC		 4173 int j;
4174
4175 /* Build the command word. */
4176 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4177
e30372c9
MC		 4178 /* Calculate an offset of a buffered flash, not needed for 5709. */
4179 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 4180 offset = ((offset / bp->flash_info->page_size) <<
4181 bp->flash_info->page_bits) +
4182 (offset % bp->flash_info->page_size);
4183 }
4184
4185 /* Need to clear DONE bit separately. */
4186 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4187
4188 memcpy(&val32, val, 4);
b6016b76
MC		 4189
4190 /* Write the data. */
b491edd5 4191 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
b6016b76
MC		 4192
4193 /* Address of the NVRAM to write to. */
4194 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4195
4196 /* Issue the write command. */
4197 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4198
4199 /* Wait for completion. */
4200 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4201 udelay(5);
4202
4203 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4204 break;
4205 }
4206 if (j >= NVRAM_TIMEOUT_COUNT)
4207 return -EBUSY;
4208
4209 return 0;
4210}
4211
4212static int
4213bnx2_init_nvram(struct bnx2 *bp)
4214{
4215 u32 val;
e30372c9 4216 int j, entry_count, rc = 0;
0ced9d01 4217 const struct flash_spec *flash;
b6016b76 4218
e30372c9
MC		 4219 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4220 bp->flash_info = &flash_5709;
4221 goto get_flash_size;
4222 }
4223
b6016b76
MC		 4224 /* Determine the selected interface. */
4225 val = REG_RD(bp, BNX2_NVM_CFG1);
4226
ff8ac609 4227 entry_count = ARRAY_SIZE(flash_table);
b6016b76 4228
b6016b76
MC		 4229 if (val & 0x40000000) {
4230
4231 /* Flash interface has been reconfigured */
4232 for (j = 0, flash = &flash_table[0]; j < entry_count;
37137709
MC		 4233 j++, flash++) {
4234 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4235 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
b6016b76
MC		 4236 bp->flash_info = flash;
4237 break;
4238 }
4239 }
4240 }
4241 else {
37137709 4242 u32 mask;
b6016b76
MC		 4243 /* Not yet been reconfigured */
4244
37137709
MC		 4245 if (val & (1 << 23))
4246 mask = FLASH_BACKUP_STRAP_MASK;
4247 else
4248 mask = FLASH_STRAP_MASK;
4249
b6016b76
MC		 4250 for (j = 0, flash = &flash_table[0]; j < entry_count;
4251 j++, flash++) {
4252
37137709 4253 if ((val & mask) == (flash->strapping & mask)) {
b6016b76
MC		 4254 bp->flash_info = flash;
4255
4256 /* Request access to the flash interface. */
4257 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4258 return rc;
4259
4260 /* Enable access to flash interface */
4261 bnx2_enable_nvram_access(bp);
4262
4263 /* Reconfigure the flash interface */
4264 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4265 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4266 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4267 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4268
4269 /* Disable access to flash interface */
4270 bnx2_disable_nvram_access(bp);
4271 bnx2_release_nvram_lock(bp);
4272
4273 break;
4274 }
4275 }
4276 } /* if (val & 0x40000000) */
4277
4278 if (j == entry_count) {
4279 bp->flash_info = NULL;
3a9c6a49 4280 pr_alert("Unknown flash/EEPROM type\n");
1122db71 4281 return -ENODEV;
b6016b76
MC		 4282 }
4283
e30372c9 4284get_flash_size:
2726d6e1 4285 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
1122db71
MC		 4286 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4287 if (val)
4288 bp->flash_size = val;
4289 else
4290 bp->flash_size = bp->flash_info->total_size;
4291
b6016b76
MC		 4292 return rc;
4293}
4294
4295static int
4296bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4297 int buf_size)
4298{
4299 int rc = 0;
4300 u32 cmd_flags, offset32, len32, extra;
4301
4302 if (buf_size == 0)
4303 return 0;
4304
4305 /* Request access to the flash interface. */
4306 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4307 return rc;
4308
4309 /* Enable access to flash interface */
4310 bnx2_enable_nvram_access(bp);
4311
4312 len32 = buf_size;
4313 offset32 = offset;
4314 extra = 0;
4315
4316 cmd_flags = 0;
4317
4318 if (offset32 & 3) {
4319 u8 buf[4];
4320 u32 pre_len;
4321
4322 offset32 &= ~3;
4323 pre_len = 4 - (offset & 3);
4324
4325 if (pre_len >= len32) {
4326 pre_len = len32;
4327 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4328 BNX2_NVM_COMMAND_LAST;
4329 }
4330 else {
4331 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4332 }
4333
4334 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4335
4336 if (rc)
4337 return rc;
4338
4339 memcpy(ret_buf, buf + (offset & 3), pre_len);
4340
4341 offset32 += 4;
4342 ret_buf += pre_len;
4343 len32 -= pre_len;
4344 }
4345 if (len32 & 3) {
4346 extra = 4 - (len32 & 3);
4347 len32 = (len32 + 4) & ~3;
4348 }
4349
4350 if (len32 == 4) {
4351 u8 buf[4];
4352
4353 if (cmd_flags)
4354 cmd_flags = BNX2_NVM_COMMAND_LAST;
4355 else
4356 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4357 BNX2_NVM_COMMAND_LAST;
4358
4359 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4360
4361 memcpy(ret_buf, buf, 4 - extra);
4362 }
4363 else if (len32 > 0) {
4364 u8 buf[4];
4365
4366 /* Read the first word. */
4367 if (cmd_flags)
4368 cmd_flags = 0;
4369 else
4370 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4371
4372 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4373
4374 /* Advance to the next dword. */
4375 offset32 += 4;
4376 ret_buf += 4;
4377 len32 -= 4;
4378
4379 while (len32 > 4 && rc == 0) {
4380 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4381
4382 /* Advance to the next dword. */
4383 offset32 += 4;
4384 ret_buf += 4;
4385 len32 -= 4;
4386 }
4387
4388 if (rc)
4389 return rc;
4390
4391 cmd_flags = BNX2_NVM_COMMAND_LAST;
4392 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4393
4394 memcpy(ret_buf, buf, 4 - extra);
4395 }
4396
4397 /* Disable access to flash interface */
4398 bnx2_disable_nvram_access(bp);
4399
4400 bnx2_release_nvram_lock(bp);
4401
4402 return rc;
4403}
4404
4405static int
4406bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4407 int buf_size)
4408{
4409 u32 written, offset32, len32;
e6be763f 4410 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
b6016b76
MC		 4411 int rc = 0;
4412 int align_start, align_end;
4413
4414 buf = data_buf;
4415 offset32 = offset;
4416 len32 = buf_size;
4417 align_start = align_end = 0;
4418
4419 if ((align_start = (offset32 & 3))) {
4420 offset32 &= ~3;
c873879c
MC		 4421 len32 += align_start;
4422 if (len32 < 4)
4423 len32 = 4;
b6016b76
MC		 4424 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4425 return rc;
4426 }
4427
4428 if (len32 & 3) {
c873879c
MC		 4429 align_end = 4 - (len32 & 3);
4430 len32 += align_end;
4431 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4432 return rc;
b6016b76
MC		 4433 }
4434
4435 if (align_start || align_end) {
e6be763f
MC		 4436 align_buf = kmalloc(len32, GFP_KERNEL);
4437 if (align_buf == NULL)
b6016b76
MC		 4438 return -ENOMEM;
4439 if (align_start) {
e6be763f 4440 memcpy(align_buf, start, 4);
b6016b76
MC		 4441 }
4442 if (align_end) {
e6be763f 4443 memcpy(align_buf + len32 - 4, end, 4);
b6016b76 4444 }
e6be763f
MC		 4445 memcpy(align_buf + align_start, data_buf, buf_size);
4446 buf = align_buf;
b6016b76
MC		 4447 }
4448
e30372c9 4449 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
ae181bc4
MC		 4450 flash_buffer = kmalloc(264, GFP_KERNEL);
4451 if (flash_buffer == NULL) {
4452 rc = -ENOMEM;
4453 goto nvram_write_end;
4454 }
4455 }
4456
b6016b76
MC		 4457 written = 0;
4458 while ((written < len32) && (rc == 0)) {
4459 u32 page_start, page_end, data_start, data_end;
4460 u32 addr, cmd_flags;
4461 int i;
b6016b76
MC		 4462
4463 /* Find the page_start addr */
4464 page_start = offset32 + written;
4465 page_start -= (page_start % bp->flash_info->page_size);
4466 /* Find the page_end addr */
4467 page_end = page_start + bp->flash_info->page_size;
4468 /* Find the data_start addr */
4469 data_start = (written == 0) ? offset32 : page_start;
4470 /* Find the data_end addr */
6aa20a22 4471 data_end = (page_end > offset32 + len32) ?
b6016b76
MC		 4472 (offset32 + len32) : page_end;
4473
4474 /* Request access to the flash interface. */
4475 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4476 goto nvram_write_end;
4477
4478 /* Enable access to flash interface */
4479 bnx2_enable_nvram_access(bp);
4480
4481 cmd_flags = BNX2_NVM_COMMAND_FIRST;
e30372c9 4482 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4483 int j;
4484
4485 /* Read the whole page into the buffer
4486 * (non-buffer flash only) */
4487 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4488 if (j == (bp->flash_info->page_size - 4)) {
4489 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4490 }
4491 rc = bnx2_nvram_read_dword(bp,
6aa20a22
JG		 4492 page_start + j,
4493 &flash_buffer[j],
b6016b76
MC		 4494 cmd_flags);
4495
4496 if (rc)
4497 goto nvram_write_end;
4498
4499 cmd_flags = 0;
4500 }
4501 }
4502
4503 /* Enable writes to flash interface (unlock write-protect) */
4504 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4505 goto nvram_write_end;
4506
b6016b76
MC		 4507 /* Loop to write back the buffer data from page_start to
4508 * data_start */
4509 i = 0;
e30372c9 4510 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
c873879c
MC		 4511 /* Erase the page */
4512 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4513 goto nvram_write_end;
4514
4515 /* Re-enable the write again for the actual write */
4516 bnx2_enable_nvram_write(bp);
4517
b6016b76
MC		 4518 for (addr = page_start; addr < data_start;
4519 addr += 4, i += 4) {
6aa20a22 4520
b6016b76
MC		 4521 rc = bnx2_nvram_write_dword(bp, addr,
4522 &flash_buffer[i], cmd_flags);
4523
4524 if (rc != 0)
4525 goto nvram_write_end;
4526
4527 cmd_flags = 0;
4528 }
4529 }
4530
4531 /* Loop to write the new data from data_start to data_end */
bae25761 4532 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
b6016b76 4533 if ((addr == page_end - 4) ||
e30372c9 4534 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
b6016b76
MC		 4535 (addr == data_end - 4))) {
4536
4537 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4538 }
4539 rc = bnx2_nvram_write_dword(bp, addr, buf,
4540 cmd_flags);
4541
4542 if (rc != 0)
4543 goto nvram_write_end;
4544
4545 cmd_flags = 0;
4546 buf += 4;
4547 }
4548
4549 /* Loop to write back the buffer data from data_end
4550 * to page_end */
e30372c9 4551 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4552 for (addr = data_end; addr < page_end;
4553 addr += 4, i += 4) {
6aa20a22 4554
b6016b76
MC		 4555 if (addr == page_end-4) {
4556 cmd_flags = BNX2_NVM_COMMAND_LAST;
4557 }
4558 rc = bnx2_nvram_write_dword(bp, addr,
4559 &flash_buffer[i], cmd_flags);
4560
4561 if (rc != 0)
4562 goto nvram_write_end;
4563
4564 cmd_flags = 0;
4565 }
4566 }
4567
4568 /* Disable writes to flash interface (lock write-protect) */
4569 bnx2_disable_nvram_write(bp);
4570
4571 /* Disable access to flash interface */
4572 bnx2_disable_nvram_access(bp);
4573 bnx2_release_nvram_lock(bp);
4574
4575 /* Increment written */
4576 written += data_end - data_start;
4577 }
4578
4579nvram_write_end:
e6be763f
MC		 4580 kfree(flash_buffer);
4581 kfree(align_buf);
b6016b76
MC		 4582 return rc;
4583}
4584
0d8a6571 4585static void
7c62e83b 4586bnx2_init_fw_cap(struct bnx2 *bp)
0d8a6571 4587{
7c62e83b 4588 u32 val, sig = 0;
0d8a6571 4589
583c28e5 4590 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
7c62e83b
MC		 4591 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4592
4593 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4594 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
0d8a6571 4595
2726d6e1 4596 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
0d8a6571
MC		 4597 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4598 return;
4599
7c62e83b
MC		 4600 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4601 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4602 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4603 }
4604
4605 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4606 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4607 u32 link;
4608
583c28e5 4609 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
0d8a6571 4610
7c62e83b
MC		 4611 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4612 if (link & BNX2_LINK_STATUS_SERDES_LINK)
0d8a6571
MC		 4613 bp->phy_port = PORT_FIBRE;
4614 else
4615 bp->phy_port = PORT_TP;
489310a4 4616
7c62e83b
MC		 4617 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4618 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
0d8a6571 4619 }
7c62e83b
MC		 4620
4621 if (netif_running(bp->dev) && sig)
4622 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
0d8a6571
MC		 4623}
4624
b4b36042
MC		 4625static void
4626bnx2_setup_msix_tbl(struct bnx2 *bp)
4627{
4628 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4629
4630 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4631 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4632}
4633
b6016b76
MC		 4634static int
4635bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4636{
4637 u32 val;
4638 int i, rc = 0;
489310a4 4639 u8 old_port;
b6016b76
MC		 4640
4641 /* Wait for the current PCI transaction to complete before
4642 * issuing a reset. */
a5dac108
EW		 4643 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
4644 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
4645 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4646 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4647 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4648 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4649 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4650 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4651 udelay(5);
4652 } else { /* 5709 */
4653 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4654 val &= ~BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4655 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4656 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4657
4658 for (i = 0; i < 100; i++) {
4659 msleep(1);
4660 val = REG_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);
4661 if (!(val & BNX2_PCICFG_DEVICE_STATUS_NO_PEND))
4662 break;
4663 }
4664 }
b6016b76 4665
b090ae2b 4666 /* Wait for the firmware to tell us it is ok to issue a reset. */
a2f13890 4667 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
b090ae2b 4668
b6016b76
MC		 4669 /* Deposit a driver reset signature so the firmware knows that
4670 * this is a soft reset. */
2726d6e1
MC		 4671 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4672 BNX2_DRV_RESET_SIGNATURE_MAGIC);
b6016b76 4673
b6016b76
MC		 4674 /* Do a dummy read to force the chip to complete all current transaction
4675 * before we issue a reset. */
4676 val = REG_RD(bp, BNX2_MISC_ID);
4677
234754d5
MC		 4678 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4679 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4680 REG_RD(bp, BNX2_MISC_COMMAND);
4681 udelay(5);
b6016b76 4682
234754d5
MC		 4683 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4684 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
b6016b76 4685
be7ff1af 4686 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
b6016b76 4687
234754d5
MC		 4688 } else {
4689 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4690 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4691 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4692
4693 /* Chip reset. */
4694 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4695
594a9dfa
MC		 4696 /* Reading back any register after chip reset will hang the
4697 * bus on 5706 A0 and A1. The msleep below provides plenty
4698 * of margin for write posting.
4699 */
234754d5 4700 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
8e545881
AV		 4701 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4702 msleep(20);
b6016b76 4703
234754d5
MC		 4704 /* Reset takes approximate 30 usec */
4705 for (i = 0; i < 10; i++) {
4706 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4707 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4708 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4709 break;
4710 udelay(10);
4711 }
4712
4713 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4714 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3a9c6a49 4715 pr_err("Chip reset did not complete\n");
234754d5
MC		 4716 return -EBUSY;
4717 }
b6016b76
MC		 4718 }
4719
4720 /* Make sure byte swapping is properly configured. */
4721 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4722 if (val != 0x01020304) {
3a9c6a49 4723 pr_err("Chip not in correct endian mode\n");
b6016b76
MC		 4724 return -ENODEV;
4725 }
4726
b6016b76 4727 /* Wait for the firmware to finish its initialization. */
a2f13890 4728 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
b090ae2b
MC		 4729 if (rc)
4730 return rc;
b6016b76 4731
0d8a6571 4732 spin_lock_bh(&bp->phy_lock);
489310a4 4733 old_port = bp->phy_port;
7c62e83b 4734 bnx2_init_fw_cap(bp);
583c28e5
MC		 4735 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4736 old_port != bp->phy_port)
0d8a6571
MC		 4737 bnx2_set_default_remote_link(bp);
4738 spin_unlock_bh(&bp->phy_lock);
4739
b6016b76
MC		 4740 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4741 /* Adjust the voltage regular to two steps lower. The default
4742 * of this register is 0x0000000e. */
4743 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4744
4745 /* Remove bad rbuf memory from the free pool. */
4746 rc = bnx2_alloc_bad_rbuf(bp);
4747 }
4748
c441b8d2 4749 if (bp->flags & BNX2_FLAG_USING_MSIX) {
b4b36042 4750 bnx2_setup_msix_tbl(bp);
c441b8d2
MC		 4751 /* Prevent MSIX table reads and write from timing out */
4752 REG_WR(bp, BNX2_MISC_ECO_HW_CTL,
4753 BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN);
4754 }
b4b36042 4755
b6016b76
MC		 4756 return rc;
4757}
4758
4759static int
4760bnx2_init_chip(struct bnx2 *bp)
4761{
d8026d93 4762 u32 val, mtu;
b4b36042 4763 int rc, i;
b6016b76
MC		 4764
4765 /* Make sure the interrupt is not active. */
4766 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4767
4768 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4769 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4770#ifdef __BIG_ENDIAN
6aa20a22 4771 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
b6016b76 4772#endif
6aa20a22 4773 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
b6016b76
MC		 4774 DMA_READ_CHANS << 12 |
4775 DMA_WRITE_CHANS << 16;
4776
4777 val |= (0x2 << 20) | (1 << 11);
4778
f86e82fb 4779 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
b6016b76
MC		 4780 val |= (1 << 23);
4781
4782 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
f86e82fb 4783 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
b6016b76
MC		 4784 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4785
4786 REG_WR(bp, BNX2_DMA_CONFIG, val);
4787
4788 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4789 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4790 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4791 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4792 }
4793
f86e82fb 4794 if (bp->flags & BNX2_FLAG_PCIX) {
b6016b76
MC		 4795 u16 val16;
4796
4797 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4798 &val16);
4799 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4800 val16 & ~PCI_X_CMD_ERO);
4801 }
4802
4803 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4804 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4805 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4806 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4807
4808 /* Initialize context mapping and zero out the quick contexts. The
4809 * context block must have already been enabled. */
641bdcd5
MC		 4810 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4811 rc = bnx2_init_5709_context(bp);
4812 if (rc)
4813 return rc;
4814 } else
59b47d8a 4815 bnx2_init_context(bp);
b6016b76 4816
fba9fe91
MC		 4817 if ((rc = bnx2_init_cpus(bp)) != 0)
4818 return rc;
4819
b6016b76
MC		 4820 bnx2_init_nvram(bp);
4821
5fcaed01 4822 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 4823
4824 val = REG_RD(bp, BNX2_MQ_CONFIG);
4825 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4826 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4edd473f
MC		 4827 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4828 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4829 if (CHIP_REV(bp) == CHIP_REV_Ax)
4830 val |= BNX2_MQ_CONFIG_HALT_DIS;
4831 }
68c9f75a 4832
b6016b76
MC		 4833 REG_WR(bp, BNX2_MQ_CONFIG, val);
4834
4835 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4836 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4837 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4838
4839 val = (BCM_PAGE_BITS - 8) << 24;
4840 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4841
4842 /* Configure page size. */
4843 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4844 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4845 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4846 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4847
4848 val = bp->mac_addr[0] +
4849 (bp->mac_addr[1] << 8) +
4850 (bp->mac_addr[2] << 16) +
4851 bp->mac_addr[3] +
4852 (bp->mac_addr[4] << 8) +
4853 (bp->mac_addr[5] << 16);
4854 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4855
4856 /* Program the MTU. Also include 4 bytes for CRC32. */
d8026d93
MC		 4857 mtu = bp->dev->mtu;
4858 val = mtu + ETH_HLEN + ETH_FCS_LEN;
b6016b76
MC		 4859 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4860 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4861 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4862
d8026d93
MC		 4863 if (mtu < 1500)
4864 mtu = 1500;
4865
4866 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4867 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4868 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4869
155d5561 4870 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
b4b36042
MC		 4871 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4872 bp->bnx2_napi[i].last_status_idx = 0;
4873
efba0180
MC		 4874 bp->idle_chk_status_idx = 0xffff;
4875
b6016b76
MC		 4876 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4877
4878 /* Set up how to generate a link change interrupt. */
4879 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4880
4881 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4882 (u64) bp->status_blk_mapping & 0xffffffff);
4883 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4884
4885 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4886 (u64) bp->stats_blk_mapping & 0xffffffff);
4887 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4888 (u64) bp->stats_blk_mapping >> 32);
4889
6aa20a22 4890 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
b6016b76
MC		 4891 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4892
4893 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4894 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4895
4896 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4897 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4898
4899 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4900
4901 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4902
4903 REG_WR(bp, BNX2_HC_COM_TICKS,
4904 (bp->com_ticks_int << 16) | bp->com_ticks);
4905
4906 REG_WR(bp, BNX2_HC_CMD_TICKS,
4907 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4908
61d9e3fa 4909 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
02537b06
MC		 4910 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4911 else
7ea6920e 4912 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
b6016b76
MC		 4913 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4914
4915 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
8e6a72c4 4916 val = BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76 4917 else {
8e6a72c4
MC		 4918 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4919 BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76
MC		 4920 }
4921
efde73a3 4922 if (bp->flags & BNX2_FLAG_USING_MSIX) {
c76c0475
MC		 4923 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4924 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4925
5e9ad9e1
MC		 4926 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4927 }
4928
4929 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
cf7474a6 4930 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
5e9ad9e1
MC		 4931
4932 REG_WR(bp, BNX2_HC_CONFIG, val);
4933
22fa159d
MC		 4934 if (bp->rx_ticks < 25)
4935 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1);
4936 else
4937 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0);
4938
5e9ad9e1
MC		 4939 for (i = 1; i < bp->irq_nvecs; i++) {
4940 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4941 BNX2_HC_SB_CONFIG_1;
4942
6f743ca0 4943 REG_WR(bp, base,
c76c0475 4944 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
5e9ad9e1 4945 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
c76c0475
MC		 4946 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4947
6f743ca0 4948 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
c76c0475
MC		 4949 (bp->tx_quick_cons_trip_int << 16) |
4950 bp->tx_quick_cons_trip);
4951
6f743ca0 4952 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
c76c0475
MC		 4953 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4954
5e9ad9e1
MC		 4955 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4956 (bp->rx_quick_cons_trip_int << 16) |
4957 bp->rx_quick_cons_trip);
8e6a72c4 4958
5e9ad9e1
MC		 4959 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4960 (bp->rx_ticks_int << 16) | bp->rx_ticks);
4961 }
8e6a72c4 4962
b6016b76
MC		 4963 /* Clear internal stats counters. */
4964 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4965
da3e4fbe 4966 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
b6016b76
MC		 4967
4968 /* Initialize the receive filter. */
4969 bnx2_set_rx_mode(bp->dev);
4970
0aa38df7
MC		 4971 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4972 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4973 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4974 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4975 }
b090ae2b 4976 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
a2f13890 4977 1, 0);
b6016b76 4978
df149d70 4979 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
b6016b76
MC		 4980 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4981
4982 udelay(20);
4983
bf5295bb
MC		 4984 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4985
b090ae2b 4986 return rc;
b6016b76
MC		 4987}
4988
c76c0475
MC		 4989static void
4990bnx2_clear_ring_states(struct bnx2 *bp)
4991{
4992 struct bnx2_napi *bnapi;
35e9010b 4993 struct bnx2_tx_ring_info *txr;
bb4f98ab 4994 struct bnx2_rx_ring_info *rxr;
c76c0475
MC		 4995 int i;
4996
4997 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4998 bnapi = &bp->bnx2_napi[i];
35e9010b 4999 txr = &bnapi->tx_ring;
bb4f98ab 5000 rxr = &bnapi->rx_ring;
c76c0475 5001
35e9010b
MC		 5002 txr->tx_cons = 0;
5003 txr->hw_tx_cons = 0;
bb4f98ab
MC		 5004 rxr->rx_prod_bseq = 0;
5005 rxr->rx_prod = 0;
5006 rxr->rx_cons = 0;
5007 rxr->rx_pg_prod = 0;
5008 rxr->rx_pg_cons = 0;
c76c0475
MC		 5009 }
5010}
5011
59b47d8a 5012static void
35e9010b 5013bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
59b47d8a
MC		 5014{
5015 u32 val, offset0, offset1, offset2, offset3;
62a8313c 5016 u32 cid_addr = GET_CID_ADDR(cid);
59b47d8a
MC		 5017
5018 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5019 offset0 = BNX2_L2CTX_TYPE_XI;
5020 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5021 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5022 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5023 } else {
5024 offset0 = BNX2_L2CTX_TYPE;
5025 offset1 = BNX2_L2CTX_CMD_TYPE;
5026 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5027 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5028 }
5029 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
62a8313c 5030 bnx2_ctx_wr(bp, cid_addr, offset0, val);
59b47d8a
MC		 5031
5032 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
62a8313c 5033 bnx2_ctx_wr(bp, cid_addr, offset1, val);
59b47d8a 5034
35e9010b 5035 val = (u64) txr->tx_desc_mapping >> 32;
62a8313c 5036 bnx2_ctx_wr(bp, cid_addr, offset2, val);
59b47d8a 5037
35e9010b 5038 val = (u64) txr->tx_desc_mapping & 0xffffffff;
62a8313c 5039 bnx2_ctx_wr(bp, cid_addr, offset3, val);
59b47d8a 5040}
b6016b76
MC		 5041
5042static void
35e9010b 5043bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
b6016b76
MC		 5044{
5045 struct tx_bd *txbd;
c76c0475
MC		 5046 u32 cid = TX_CID;
5047 struct bnx2_napi *bnapi;
35e9010b 5048 struct bnx2_tx_ring_info *txr;
c76c0475 5049
35e9010b
MC		 5050 bnapi = &bp->bnx2_napi[ring_num];
5051 txr = &bnapi->tx_ring;
5052
5053 if (ring_num == 0)
5054 cid = TX_CID;
5055 else
5056 cid = TX_TSS_CID + ring_num - 1;
b6016b76 5057
2f8af120
MC		 5058 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5059
35e9010b 5060 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
6aa20a22 5061
35e9010b
MC		 5062 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5063 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
b6016b76 5064
35e9010b
MC		 5065 txr->tx_prod = 0;
5066 txr->tx_prod_bseq = 0;
6aa20a22 5067
35e9010b
MC		 5068 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5069 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
b6016b76 5070
35e9010b 5071 bnx2_init_tx_context(bp, cid, txr);
b6016b76
MC		 5072}
5073
5074static void
5d5d0015
MC		 5075bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
5076 int num_rings)
b6016b76 5077{
b6016b76 5078 int i;
5d5d0015 5079 struct rx_bd *rxbd;
6aa20a22 5080
5d5d0015 5081 for (i = 0; i < num_rings; i++) {
13daffa2 5082 int j;
b6016b76 5083
5d5d0015 5084 rxbd = &rx_ring[i][0];
13daffa2 5085 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5d5d0015 5086 rxbd->rx_bd_len = buf_size;
13daffa2
MC		 5087 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5088 }
5d5d0015 5089 if (i == (num_rings - 1))
13daffa2
MC		 5090 j = 0;
5091 else
5092 j = i + 1;
5d5d0015
MC		 5093 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5094 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
13daffa2 5095 }
5d5d0015
MC		 5096}
5097
5098static void
bb4f98ab 5099bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5d5d0015
MC		 5100{
5101 int i;
5102 u16 prod, ring_prod;
bb4f98ab
MC		 5103 u32 cid, rx_cid_addr, val;
5104 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5105 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5106
5107 if (ring_num == 0)
5108 cid = RX_CID;
5109 else
5110 cid = RX_RSS_CID + ring_num - 1;
5111
5112 rx_cid_addr = GET_CID_ADDR(cid);
5d5d0015 5113
bb4f98ab 5114 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5d5d0015
MC		 5115 bp->rx_buf_use_size, bp->rx_max_ring);
5116
bb4f98ab 5117 bnx2_init_rx_context(bp, cid);
83e3fc89
MC		 5118
5119 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5120 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
5121 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5122 }
5123
62a8313c 5124 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
47bf4246 5125 if (bp->rx_pg_ring_size) {
bb4f98ab
MC		 5126 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5127 rxr->rx_pg_desc_mapping,
47bf4246
MC		 5128 PAGE_SIZE, bp->rx_max_pg_ring);
5129 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
62a8313c
MC		 5130 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5131 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5e9ad9e1 5132 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
47bf4246 5133
bb4f98ab 5134 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
62a8313c 5135 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
47bf4246 5136
bb4f98ab 5137 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
62a8313c 5138 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
47bf4246
MC		 5139
5140 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5141 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5142 }
b6016b76 5143
bb4f98ab 5144 val = (u64) rxr->rx_desc_mapping[0] >> 32;
62a8313c 5145 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
b6016b76 5146
bb4f98ab 5147 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
62a8313c 5148 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
b6016b76 5149
bb4f98ab 5150 ring_prod = prod = rxr->rx_pg_prod;
47bf4246 5151 for (i = 0; i < bp->rx_pg_ring_size; i++) {
a2df00aa 5152 if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
3a9c6a49
JP		 5153 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",
5154 ring_num, i, bp->rx_pg_ring_size);
47bf4246 5155 break;
b929e53c 5156 }
47bf4246
MC		 5157 prod = NEXT_RX_BD(prod);
5158 ring_prod = RX_PG_RING_IDX(prod);
5159 }
bb4f98ab 5160 rxr->rx_pg_prod = prod;
47bf4246 5161
bb4f98ab 5162 ring_prod = prod = rxr->rx_prod;
236b6394 5163 for (i = 0; i < bp->rx_ring_size; i++) {
a2df00aa 5164 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
3a9c6a49
JP		 5165 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
5166 ring_num, i, bp->rx_ring_size);
b6016b76 5167 break;
b929e53c 5168 }
b6016b76
MC		 5169 prod = NEXT_RX_BD(prod);
5170 ring_prod = RX_RING_IDX(prod);
5171 }
bb4f98ab 5172 rxr->rx_prod = prod;
b6016b76 5173
bb4f98ab
MC		 5174 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5175 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5176 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
b6016b76 5177
bb4f98ab
MC		 5178 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5179 REG_WR16(bp, rxr->rx_bidx_addr, prod);
5180
5181 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
b6016b76
MC		 5182}
5183
35e9010b
MC		 5184static void
5185bnx2_init_all_rings(struct bnx2 *bp)
5186{
5187 int i;
5e9ad9e1 5188 u32 val;
35e9010b
MC		 5189
5190 bnx2_clear_ring_states(bp);
5191
5192 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5193 for (i = 0; i < bp->num_tx_rings; i++)
5194 bnx2_init_tx_ring(bp, i);
5195
5196 if (bp->num_tx_rings > 1)
5197 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5198 (TX_TSS_CID << 7));
5199
5e9ad9e1
MC		 5200 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5201 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5202
bb4f98ab
MC		 5203 for (i = 0; i < bp->num_rx_rings; i++)
5204 bnx2_init_rx_ring(bp, i);
5e9ad9e1
MC		 5205
5206 if (bp->num_rx_rings > 1) {
22fa159d 5207 u32 tbl_32 = 0;
5e9ad9e1
MC		 5208
5209 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
22fa159d
MC		 5210 int shift = (i % 8) << 2;
5211
5212 tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift;
5213 if ((i % 8) == 7) {
5214 REG_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);
5215 REG_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |
5216 BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK |
5217 BNX2_RLUP_RSS_COMMAND_WRITE |
5218 BNX2_RLUP_RSS_COMMAND_HASH_MASK);
5219 tbl_32 = 0;
5220 }
5e9ad9e1
MC		 5221 }
5222
5223 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5224 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5225
5226 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5227
5228 }
35e9010b
MC		 5229}
5230
5d5d0015 5231static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
13daffa2 5232{
5d5d0015 5233 u32 max, num_rings = 1;
13daffa2 5234
5d5d0015
MC		 5235 while (ring_size > MAX_RX_DESC_CNT) {
5236 ring_size -= MAX_RX_DESC_CNT;
13daffa2
MC		 5237 num_rings++;
5238 }
5239 /* round to next power of 2 */
5d5d0015 5240 max = max_size;
13daffa2
MC		 5241 while ((max & num_rings) == 0)
5242 max >>= 1;
5243
5244 if (num_rings != max)
5245 max <<= 1;
5246
5d5d0015
MC		 5247 return max;
5248}
5249
5250static void
5251bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5252{
84eaa187 5253 u32 rx_size, rx_space, jumbo_size;
5d5d0015
MC		 5254
5255 /* 8 for CRC and VLAN */
d89cb6af 5256 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5d5d0015 5257
84eaa187
MC		 5258 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5259 sizeof(struct skb_shared_info);
5260
601d3d18 5261 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
47bf4246
MC		 5262 bp->rx_pg_ring_size = 0;
5263 bp->rx_max_pg_ring = 0;
5264 bp->rx_max_pg_ring_idx = 0;
f86e82fb 5265 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
84eaa187
MC		 5266 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5267
5268 jumbo_size = size * pages;
5269 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5270 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5271
5272 bp->rx_pg_ring_size = jumbo_size;
5273 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5274 MAX_RX_PG_RINGS);
5275 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
601d3d18 5276 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
84eaa187
MC		 5277 bp->rx_copy_thresh = 0;
5278 }
5d5d0015
MC		 5279
5280 bp->rx_buf_use_size = rx_size;
5281 /* hw alignment */
5282 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
d89cb6af 5283 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5d5d0015
MC		 5284 bp->rx_ring_size = size;
5285 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
13daffa2
MC		 5286 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5287}
5288
b6016b76
MC		 5289static void
5290bnx2_free_tx_skbs(struct bnx2 *bp)
5291{
5292 int i;
5293
35e9010b
MC		 5294 for (i = 0; i < bp->num_tx_rings; i++) {
5295 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5296 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5297 int j;
b6016b76 5298
35e9010b 5299 if (txr->tx_buf_ring == NULL)
b6016b76 5300 continue;
b6016b76 5301
35e9010b 5302 for (j = 0; j < TX_DESC_CNT; ) {
3d16af86 5303 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
35e9010b 5304 struct sk_buff *skb = tx_buf->skb;
e95524a7 5305 int k, last;
35e9010b
MC		 5306
5307 if (skb == NULL) {
5308 j++;
5309 continue;
5310 }
5311
36227e88 5312 dma_unmap_single(&bp->pdev->dev,
1a4ccc2d 5313 dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 5314 skb_headlen(skb),
5315 PCI_DMA_TODEVICE);
b6016b76 5316
35e9010b 5317 tx_buf->skb = NULL;
b6016b76 5318
e95524a7
AD		 5319 last = tx_buf->nr_frags;
5320 j++;
5321 for (k = 0; k < last; k++, j++) {
5322 tx_buf = &txr->tx_buf_ring[TX_RING_IDX(j)];
36227e88 5323 dma_unmap_page(&bp->pdev->dev,
1a4ccc2d 5324 dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 5325 skb_shinfo(skb)->frags[k].size,
5326 PCI_DMA_TODEVICE);
5327 }
35e9010b 5328 dev_kfree_skb(skb);
b6016b76 5329 }
b6016b76 5330 }
b6016b76
MC		 5331}
5332
5333static void
5334bnx2_free_rx_skbs(struct bnx2 *bp)
5335{
5336 int i;
5337
bb4f98ab
MC		 5338 for (i = 0; i < bp->num_rx_rings; i++) {
5339 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5340 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5341 int j;
b6016b76 5342
bb4f98ab
MC		 5343 if (rxr->rx_buf_ring == NULL)
5344 return;
b6016b76 5345
bb4f98ab
MC		 5346 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5347 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5348 struct sk_buff *skb = rx_buf->skb;
b6016b76 5349
bb4f98ab
MC		 5350 if (skb == NULL)
5351 continue;
b6016b76 5352
36227e88 5353 dma_unmap_single(&bp->pdev->dev,
1a4ccc2d 5354 dma_unmap_addr(rx_buf, mapping),
bb4f98ab
MC		 5355 bp->rx_buf_use_size,
5356 PCI_DMA_FROMDEVICE);
b6016b76 5357
bb4f98ab
MC		 5358 rx_buf->skb = NULL;
5359
5360 dev_kfree_skb(skb);
5361 }
5362 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5363 bnx2_free_rx_page(bp, rxr, j);
b6016b76
MC		 5364 }
5365}
5366
5367static void
5368bnx2_free_skbs(struct bnx2 *bp)
5369{
5370 bnx2_free_tx_skbs(bp);
5371 bnx2_free_rx_skbs(bp);
5372}
5373
5374static int
5375bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5376{
5377 int rc;
5378
5379 rc = bnx2_reset_chip(bp, reset_code);
5380 bnx2_free_skbs(bp);
5381 if (rc)
5382 return rc;
5383
fba9fe91
MC		 5384 if ((rc = bnx2_init_chip(bp)) != 0)
5385 return rc;
5386
35e9010b 5387 bnx2_init_all_rings(bp);
b6016b76
MC		 5388 return 0;
5389}
5390
5391static int
9a120bc5 5392bnx2_init_nic(struct bnx2 *bp, int reset_phy)
b6016b76
MC		 5393{
5394 int rc;
5395
5396 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5397 return rc;
5398
80be4434 5399 spin_lock_bh(&bp->phy_lock);
9a120bc5 5400 bnx2_init_phy(bp, reset_phy);
b6016b76 5401 bnx2_set_link(bp);
543a827d
MC		 5402 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5403 bnx2_remote_phy_event(bp);
0d8a6571 5404 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 5405 return 0;
5406}
5407
74bf4ba3
MC		 5408static int
5409bnx2_shutdown_chip(struct bnx2 *bp)
5410{
5411 u32 reset_code;
5412
5413 if (bp->flags & BNX2_FLAG_NO_WOL)
5414 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5415 else if (bp->wol)
5416 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5417 else
5418 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5419
5420 return bnx2_reset_chip(bp, reset_code);
5421}
5422
b6016b76
MC		 5423static int
5424bnx2_test_registers(struct bnx2 *bp)
5425{
5426 int ret;
5bae30c9 5427 int i, is_5709;
f71e1309 5428 static const struct {
b6016b76
MC		 5429 u16 offset;
5430 u16 flags;
5bae30c9 5431#define BNX2_FL_NOT_5709 1
b6016b76
MC		 5432 u32 rw_mask;
5433 u32 ro_mask;
5434 } reg_tbl[] = {
5435 { 0x006c, 0, 0x00000000, 0x0000003f },
5436 { 0x0090, 0, 0xffffffff, 0x00000000 },
5437 { 0x0094, 0, 0x00000000, 0x00000000 },
5438
5bae30c9
MC		 5439 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5440 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5441 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5442 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5443 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5444 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5445 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5446 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5447 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5448
5449 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5450 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5451 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5452 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5453 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5454 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5455
5456 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5457 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5458 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
b6016b76
MC		 5459
5460 { 0x1000, 0, 0x00000000, 0x00000001 },
15b169cc 5461 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
b6016b76
MC		 5462
5463 { 0x1408, 0, 0x01c00800, 0x00000000 },
5464 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5465 { 0x14a8, 0, 0x00000000, 0x000001ff },
5b0c76ad 5466 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
b6016b76
MC		 5467 { 0x14b0, 0, 0x00000002, 0x00000001 },
5468 { 0x14b8, 0, 0x00000000, 0x00000000 },
5469 { 0x14c0, 0, 0x00000000, 0x00000009 },
5470 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5471 { 0x14cc, 0, 0x00000000, 0x00000001 },
5472 { 0x14d0, 0, 0xffffffff, 0x00000000 },
b6016b76
MC		 5473
5474 { 0x1800, 0, 0x00000000, 0x00000001 },
5475 { 0x1804, 0, 0x00000000, 0x00000003 },
b6016b76
MC		 5476
5477 { 0x2800, 0, 0x00000000, 0x00000001 },
5478 { 0x2804, 0, 0x00000000, 0x00003f01 },
5479 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5480 { 0x2810, 0, 0xffff0000, 0x00000000 },
5481 { 0x2814, 0, 0xffff0000, 0x00000000 },
5482 { 0x2818, 0, 0xffff0000, 0x00000000 },
5483 { 0x281c, 0, 0xffff0000, 0x00000000 },
5484 { 0x2834, 0, 0xffffffff, 0x00000000 },
5485 { 0x2840, 0, 0x00000000, 0xffffffff },
5486 { 0x2844, 0, 0x00000000, 0xffffffff },
5487 { 0x2848, 0, 0xffffffff, 0x00000000 },
5488 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5489
5490 { 0x2c00, 0, 0x00000000, 0x00000011 },
5491 { 0x2c04, 0, 0x00000000, 0x00030007 },
5492
b6016b76
MC		 5493 { 0x3c00, 0, 0x00000000, 0x00000001 },
5494 { 0x3c04, 0, 0x00000000, 0x00070000 },
5495 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5496 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5497 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5498 { 0x3c14, 0, 0x00000000, 0xffffffff },
5499 { 0x3c18, 0, 0x00000000, 0xffffffff },
5500 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5501 { 0x3c20, 0, 0xffffff00, 0x00000000 },
b6016b76
MC		 5502
5503 { 0x5004, 0, 0x00000000, 0x0000007f },
5504 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
b6016b76 5505
b6016b76
MC		 5506 { 0x5c00, 0, 0x00000000, 0x00000001 },
5507 { 0x5c04, 0, 0x00000000, 0x0003000f },
5508 { 0x5c08, 0, 0x00000003, 0x00000000 },
5509 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5510 { 0x5c10, 0, 0x00000000, 0xffffffff },
5511 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5512 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5513 { 0x5c88, 0, 0x00000000, 0x00077373 },
5514 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5515
5516 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5517 { 0x680c, 0, 0xffffffff, 0x00000000 },
5518 { 0x6810, 0, 0xffffffff, 0x00000000 },
5519 { 0x6814, 0, 0xffffffff, 0x00000000 },
5520 { 0x6818, 0, 0xffffffff, 0x00000000 },
5521 { 0x681c, 0, 0xffffffff, 0x00000000 },
5522 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5523 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5524 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5525 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5526 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5527 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5528 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5529 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5530 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5531 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5532 { 0x684c, 0, 0xffffffff, 0x00000000 },
5533 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5534 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5535 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5536 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5537 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5538 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5539
5540 { 0xffff, 0, 0x00000000, 0x00000000 },
5541 };
5542
5543 ret = 0;
5bae30c9
MC		 5544 is_5709 = 0;
5545 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5546 is_5709 = 1;
5547
b6016b76
MC		 5548 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5549 u32 offset, rw_mask, ro_mask, save_val, val;
5bae30c9
MC		 5550 u16 flags = reg_tbl[i].flags;
5551
5552 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5553 continue;
b6016b76
MC		 5554
5555 offset = (u32) reg_tbl[i].offset;
5556 rw_mask = reg_tbl[i].rw_mask;
5557 ro_mask = reg_tbl[i].ro_mask;
5558
14ab9b86 5559 save_val = readl(bp->regview + offset);
b6016b76 5560
14ab9b86 5561 writel(0, bp->regview + offset);
b6016b76 5562
14ab9b86 5563 val = readl(bp->regview + offset);
b6016b76
MC		 5564 if ((val & rw_mask) != 0) {
5565 goto reg_test_err;
5566 }
5567
5568 if ((val & ro_mask) != (save_val & ro_mask)) {
5569 goto reg_test_err;
5570 }
5571
14ab9b86 5572 writel(0xffffffff, bp->regview + offset);
b6016b76 5573
14ab9b86 5574 val = readl(bp->regview + offset);
b6016b76
MC		 5575 if ((val & rw_mask) != rw_mask) {
5576 goto reg_test_err;
5577 }
5578
5579 if ((val & ro_mask) != (save_val & ro_mask)) {
5580 goto reg_test_err;
5581 }
5582
14ab9b86 5583 writel(save_val, bp->regview + offset);
b6016b76
MC		 5584 continue;
5585
5586reg_test_err:
14ab9b86 5587 writel(save_val, bp->regview + offset);
b6016b76
MC		 5588 ret = -ENODEV;
5589 break;
5590 }
5591 return ret;
5592}
5593
5594static int
5595bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5596{
f71e1309 5597 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
b6016b76
MC		 5598 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5599 int i;
5600
5601 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5602 u32 offset;
5603
5604 for (offset = 0; offset < size; offset += 4) {
5605
2726d6e1 5606 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
b6016b76 5607
2726d6e1 5608 if (bnx2_reg_rd_ind(bp, start + offset) !=
b6016b76
MC		 5609 test_pattern[i]) {
5610 return -ENODEV;
5611 }
5612 }
5613 }
5614 return 0;
5615}
5616
5617static int
5618bnx2_test_memory(struct bnx2 *bp)
5619{
5620 int ret = 0;
5621 int i;
5bae30c9 5622 static struct mem_entry {
b6016b76
MC		 5623 u32 offset;
5624 u32 len;
5bae30c9 5625 } mem_tbl_5706[] = {
b6016b76 5626 { 0x60000, 0x4000 },
5b0c76ad 5627 { 0xa0000, 0x3000 },
b6016b76
MC		 5628 { 0xe0000, 0x4000 },
5629 { 0x120000, 0x4000 },
5630 { 0x1a0000, 0x4000 },
5631 { 0x160000, 0x4000 },
5632 { 0xffffffff, 0 },
5bae30c9
MC		 5633 },
5634 mem_tbl_5709[] = {
5635 { 0x60000, 0x4000 },
5636 { 0xa0000, 0x3000 },
5637 { 0xe0000, 0x4000 },
5638 { 0x120000, 0x4000 },
5639 { 0x1a0000, 0x4000 },
5640 { 0xffffffff, 0 },
b6016b76 5641 };
5bae30c9
MC		 5642 struct mem_entry *mem_tbl;
5643
5644 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5645 mem_tbl = mem_tbl_5709;
5646 else
5647 mem_tbl = mem_tbl_5706;
b6016b76
MC		 5648
5649 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5650 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5651 mem_tbl[i].len)) != 0) {
5652 return ret;
5653 }
5654 }
6aa20a22 5655
b6016b76
MC		 5656 return ret;
5657}
5658
bc5a0690
MC		 5659#define BNX2_MAC_LOOPBACK 0
5660#define BNX2_PHY_LOOPBACK 1
5661
b6016b76 5662static int
bc5a0690 5663bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
b6016b76
MC		 5664{
5665 unsigned int pkt_size, num_pkts, i;
5666 struct sk_buff *skb, *rx_skb;
5667 unsigned char *packet;
bc5a0690 5668 u16 rx_start_idx, rx_idx;
b6016b76
MC		 5669 dma_addr_t map;
5670 struct tx_bd *txbd;
5671 struct sw_bd *rx_buf;
5672 struct l2_fhdr *rx_hdr;
5673 int ret = -ENODEV;
c76c0475 5674 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
35e9010b 5675 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
bb4f98ab 5676 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
c76c0475
MC		 5677
5678 tx_napi = bnapi;
b6016b76 5679
35e9010b 5680 txr = &tx_napi->tx_ring;
bb4f98ab 5681 rxr = &bnapi->rx_ring;
bc5a0690
MC		 5682 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5683 bp->loopback = MAC_LOOPBACK;
5684 bnx2_set_mac_loopback(bp);
5685 }
5686 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
583c28e5 5687 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
489310a4
MC		 5688 return 0;
5689
80be4434 5690 bp->loopback = PHY_LOOPBACK;
bc5a0690
MC		 5691 bnx2_set_phy_loopback(bp);
5692 }
5693 else
5694 return -EINVAL;
b6016b76 5695
84eaa187 5696 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
932f3772 5697 skb = netdev_alloc_skb(bp->dev, pkt_size);
b6cbc3b6
JL		 5698 if (!skb)
5699 return -ENOMEM;
b6016b76 5700 packet = skb_put(skb, pkt_size);
6634292b 5701 memcpy(packet, bp->dev->dev_addr, 6);
b6016b76
MC		 5702 memset(packet + 6, 0x0, 8);
5703 for (i = 14; i < pkt_size; i++)
5704 packet[i] = (unsigned char) (i & 0xff);
5705
36227e88
SG		 5706 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
5707 PCI_DMA_TODEVICE);
5708 if (dma_mapping_error(&bp->pdev->dev, map)) {
3d16af86
BL		 5709 dev_kfree_skb(skb);
5710 return -EIO;
5711 }
b6016b76 5712
bf5295bb
MC		 5713 REG_WR(bp, BNX2_HC_COMMAND,
5714 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5715
b6016b76
MC		 5716 REG_RD(bp, BNX2_HC_COMMAND);
5717
5718 udelay(5);
35efa7c1 5719 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76 5720
b6016b76
MC		 5721 num_pkts = 0;
5722
35e9010b 5723 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
b6016b76
MC		 5724
5725 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5726 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5727 txbd->tx_bd_mss_nbytes = pkt_size;
5728 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5729
5730 num_pkts++;
35e9010b
MC		 5731 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5732 txr->tx_prod_bseq += pkt_size;
b6016b76 5733
35e9010b
MC		 5734 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5735 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
b6016b76
MC		 5736
5737 udelay(100);
5738
bf5295bb
MC		 5739 REG_WR(bp, BNX2_HC_COMMAND,
5740 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5741
b6016b76
MC		 5742 REG_RD(bp, BNX2_HC_COMMAND);
5743
5744 udelay(5);
5745
36227e88 5746 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);
745720e5 5747 dev_kfree_skb(skb);
b6016b76 5748
35e9010b 5749 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
b6016b76 5750 goto loopback_test_done;
b6016b76 5751
35efa7c1 5752 rx_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76
MC		 5753 if (rx_idx != rx_start_idx + num_pkts) {
5754 goto loopback_test_done;
5755 }
5756
bb4f98ab 5757 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
b6016b76
MC		 5758 rx_skb = rx_buf->skb;
5759
a33fa66b 5760 rx_hdr = rx_buf->desc;
d89cb6af 5761 skb_reserve(rx_skb, BNX2_RX_OFFSET);
b6016b76 5762
36227e88 5763 dma_sync_single_for_cpu(&bp->pdev->dev,
1a4ccc2d 5764 dma_unmap_addr(rx_buf, mapping),
b6016b76
MC		 5765 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5766
ade2bfe7 5767 if (rx_hdr->l2_fhdr_status &
b6016b76
MC		 5768 (L2_FHDR_ERRORS_BAD_CRC |
5769 L2_FHDR_ERRORS_PHY_DECODE |
5770 L2_FHDR_ERRORS_ALIGNMENT |
5771 L2_FHDR_ERRORS_TOO_SHORT |
5772 L2_FHDR_ERRORS_GIANT_FRAME)) {
5773
5774 goto loopback_test_done;
5775 }
5776
5777 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5778 goto loopback_test_done;
5779 }
5780
5781 for (i = 14; i < pkt_size; i++) {
5782 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5783 goto loopback_test_done;
5784 }
5785 }
5786
5787 ret = 0;
5788
5789loopback_test_done:
5790 bp->loopback = 0;
5791 return ret;
5792}
5793
bc5a0690
MC		 5794#define BNX2_MAC_LOOPBACK_FAILED 1
5795#define BNX2_PHY_LOOPBACK_FAILED 2
5796#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5797 BNX2_PHY_LOOPBACK_FAILED)
5798
5799static int
5800bnx2_test_loopback(struct bnx2 *bp)
5801{
5802 int rc = 0;
5803
5804 if (!netif_running(bp->dev))
5805 return BNX2_LOOPBACK_FAILED;
5806
5807 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5808 spin_lock_bh(&bp->phy_lock);
9a120bc5 5809 bnx2_init_phy(bp, 1);
bc5a0690
MC		 5810 spin_unlock_bh(&bp->phy_lock);
5811 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5812 rc |= BNX2_MAC_LOOPBACK_FAILED;
5813 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5814 rc |= BNX2_PHY_LOOPBACK_FAILED;
5815 return rc;
5816}
5817
b6016b76
MC		 5818#define NVRAM_SIZE 0x200
5819#define CRC32_RESIDUAL 0xdebb20e3
5820
5821static int
5822bnx2_test_nvram(struct bnx2 *bp)
5823{
b491edd5 5824 __be32 buf[NVRAM_SIZE / 4];
b6016b76
MC		 5825 u8 *data = (u8 *) buf;
5826 int rc = 0;
5827 u32 magic, csum;
5828
5829 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5830 goto test_nvram_done;
5831
5832 magic = be32_to_cpu(buf[0]);
5833 if (magic != 0x669955aa) {
5834 rc = -ENODEV;
5835 goto test_nvram_done;
5836 }
5837
5838 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5839 goto test_nvram_done;
5840
5841 csum = ether_crc_le(0x100, data);
5842 if (csum != CRC32_RESIDUAL) {
5843 rc = -ENODEV;
5844 goto test_nvram_done;
5845 }
5846
5847 csum = ether_crc_le(0x100, data + 0x100);
5848 if (csum != CRC32_RESIDUAL) {
5849 rc = -ENODEV;
5850 }
5851
5852test_nvram_done:
5853 return rc;
5854}
5855
5856static int
5857bnx2_test_link(struct bnx2 *bp)
5858{
5859 u32 bmsr;
5860
9f52b564
MC		 5861 if (!netif_running(bp->dev))
5862 return -ENODEV;
5863
583c28e5 5864 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
489310a4
MC		 5865 if (bp->link_up)
5866 return 0;
5867 return -ENODEV;
5868 }
c770a65c 5869 spin_lock_bh(&bp->phy_lock);
27a005b8
MC		 5870 bnx2_enable_bmsr1(bp);
5871 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5872 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5873 bnx2_disable_bmsr1(bp);
c770a65c 5874 spin_unlock_bh(&bp->phy_lock);
6aa20a22 5875
b6016b76
MC		 5876 if (bmsr & BMSR_LSTATUS) {
5877 return 0;
5878 }
5879 return -ENODEV;
5880}
5881
5882static int
5883bnx2_test_intr(struct bnx2 *bp)
5884{
5885 int i;
b6016b76
MC		 5886 u16 status_idx;
5887
5888 if (!netif_running(bp->dev))
5889 return -ENODEV;
5890
5891 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5892
5893 /* This register is not touched during run-time. */
bf5295bb 5894 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 5895 REG_RD(bp, BNX2_HC_COMMAND);
5896
5897 for (i = 0; i < 10; i++) {
5898 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5899 status_idx) {
5900
5901 break;
5902 }
5903
5904 msleep_interruptible(10);
5905 }
5906 if (i < 10)
5907 return 0;
5908
5909 return -ENODEV;
5910}
5911
38ea3686 5912/* Determining link for parallel detection. */
b2fadeae
MC		 5913static int
5914bnx2_5706_serdes_has_link(struct bnx2 *bp)
5915{
5916 u32 mode_ctl, an_dbg, exp;
5917
38ea3686
MC		 5918 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5919 return 0;
5920
b2fadeae
MC		 5921 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5922 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5923
5924 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5925 return 0;
5926
5927 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5928 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5929 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5930
f3014c0c 5931 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
b2fadeae
MC		 5932 return 0;
5933
5934 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5935 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5936 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5937
5938 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5939 return 0;
5940
5941 return 1;
5942}
5943
b6016b76 5944static void
48b01e2d 5945bnx2_5706_serdes_timer(struct bnx2 *bp)
b6016b76 5946{
b2fadeae
MC		 5947 int check_link = 1;
5948
48b01e2d 5949 spin_lock(&bp->phy_lock);
b2fadeae 5950 if (bp->serdes_an_pending) {
48b01e2d 5951 bp->serdes_an_pending--;
b2fadeae
MC		 5952 check_link = 0;
5953 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
48b01e2d 5954 u32 bmcr;
b6016b76 5955
ac392abc 5956 bp->current_interval = BNX2_TIMER_INTERVAL;
cd339a0e 5957
ca58c3af 5958 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 5959
48b01e2d 5960 if (bmcr & BMCR_ANENABLE) {
b2fadeae 5961 if (bnx2_5706_serdes_has_link(bp)) {
48b01e2d
MC		 5962 bmcr &= ~BMCR_ANENABLE;
5963 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
ca58c3af 5964 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
583c28e5 5965 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d 5966 }
b6016b76 5967 }
48b01e2d
MC		 5968 }
5969 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
583c28e5 5970 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
48b01e2d 5971 u32 phy2;
b6016b76 5972
48b01e2d
MC		 5973 bnx2_write_phy(bp, 0x17, 0x0f01);
5974 bnx2_read_phy(bp, 0x15, &phy2);
5975 if (phy2 & 0x20) {
5976 u32 bmcr;
cd339a0e 5977
ca58c3af 5978 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
48b01e2d 5979 bmcr |= BMCR_ANENABLE;
ca58c3af 5980 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
b6016b76 5981
583c28e5 5982 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d
MC		 5983 }
5984 } else
ac392abc 5985 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 5986
a2724e25 5987 if (check_link) {
b2fadeae
MC		 5988 u32 val;
5989
5990 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5991 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5992 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5993
a2724e25
MC		 5994 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5995 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5996 bnx2_5706s_force_link_dn(bp, 1);
5997 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5998 } else
5999 bnx2_set_link(bp);
6000 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6001 bnx2_set_link(bp);
b2fadeae 6002 }
48b01e2d
MC		 6003 spin_unlock(&bp->phy_lock);
6004}
b6016b76 6005
f8dd064e
MC		 6006static void
6007bnx2_5708_serdes_timer(struct bnx2 *bp)
6008{
583c28e5 6009 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 6010 return;
6011
583c28e5 6012 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
f8dd064e
MC		 6013 bp->serdes_an_pending = 0;
6014 return;
6015 }
b6016b76 6016
f8dd064e
MC		 6017 spin_lock(&bp->phy_lock);
6018 if (bp->serdes_an_pending)
6019 bp->serdes_an_pending--;
6020 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6021 u32 bmcr;
b6016b76 6022
ca58c3af 6023 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
f8dd064e 6024 if (bmcr & BMCR_ANENABLE) {
605a9e20 6025 bnx2_enable_forced_2g5(bp);
40105c0b 6026 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
f8dd064e 6027 } else {
605a9e20 6028 bnx2_disable_forced_2g5(bp);
f8dd064e 6029 bp->serdes_an_pending = 2;
ac392abc 6030 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6031 }
b6016b76 6032
f8dd064e 6033 } else
ac392abc 6034 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6035
f8dd064e
MC		 6036 spin_unlock(&bp->phy_lock);
6037}
6038
48b01e2d
MC		 6039static void
6040bnx2_timer(unsigned long data)
6041{
6042 struct bnx2 *bp = (struct bnx2 *) data;
b6016b76 6043
48b01e2d
MC		 6044 if (!netif_running(bp->dev))
6045 return;
b6016b76 6046
48b01e2d
MC		 6047 if (atomic_read(&bp->intr_sem) != 0)
6048 goto bnx2_restart_timer;
b6016b76 6049
efba0180
MC		 6050 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6051 BNX2_FLAG_USING_MSI)
6052 bnx2_chk_missed_msi(bp);
6053
df149d70 6054 bnx2_send_heart_beat(bp);
b6016b76 6055
2726d6e1
MC		 6056 bp->stats_blk->stat_FwRxDrop =
6057 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
b6016b76 6058
02537b06 6059 /* workaround occasional corrupted counters */
61d9e3fa 6060 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
02537b06
MC		 6061 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6062 BNX2_HC_COMMAND_STATS_NOW);
6063
583c28e5 6064 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
f8dd064e
MC		 6065 if (CHIP_NUM(bp) == CHIP_NUM_5706)
6066 bnx2_5706_serdes_timer(bp);
27a005b8 6067 else
f8dd064e 6068 bnx2_5708_serdes_timer(bp);
b6016b76
MC		 6069 }
6070
6071bnx2_restart_timer:
cd339a0e 6072 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6073}
6074
8e6a72c4
MC		 6075static int
6076bnx2_request_irq(struct bnx2 *bp)
6077{
6d866ffc 6078 unsigned long flags;
b4b36042
MC		 6079 struct bnx2_irq *irq;
6080 int rc = 0, i;
8e6a72c4 6081
f86e82fb 6082 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6d866ffc
MC		 6083 flags = 0;
6084 else
6085 flags = IRQF_SHARED;
b4b36042
MC		 6086
6087 for (i = 0; i < bp->irq_nvecs; i++) {
6088 irq = &bp->irq_tbl[i];
c76c0475 6089 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
f0ea2e63 6090 &bp->bnx2_napi[i]);
b4b36042
MC		 6091 if (rc)
6092 break;
6093 irq->requested = 1;
6094 }
8e6a72c4
MC		 6095 return rc;
6096}
6097
6098static void
6099bnx2_free_irq(struct bnx2 *bp)
6100{
b4b36042
MC		 6101 struct bnx2_irq *irq;
6102 int i;
8e6a72c4 6103
b4b36042
MC		 6104 for (i = 0; i < bp->irq_nvecs; i++) {
6105 irq = &bp->irq_tbl[i];
6106 if (irq->requested)
f0ea2e63 6107 free_irq(irq->vector, &bp->bnx2_napi[i]);
b4b36042 6108 irq->requested = 0;
6d866ffc 6109 }
f86e82fb 6110 if (bp->flags & BNX2_FLAG_USING_MSI)
b4b36042 6111 pci_disable_msi(bp->pdev);
f86e82fb 6112 else if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 6113 pci_disable_msix(bp->pdev);
6114
f86e82fb 6115 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
b4b36042
MC		 6116}
6117
6118static void
5e9ad9e1 6119bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
b4b36042 6120{
379b39a2 6121 int i, total_vecs, rc;
57851d84 6122 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
4e1d0de9
MC		 6123 struct net_device *dev = bp->dev;
6124 const int len = sizeof(bp->irq_tbl[0].name);
57851d84 6125
b4b36042
MC		 6126 bnx2_setup_msix_tbl(bp);
6127 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6128 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6129 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
57851d84 6130
e2eb8e38
BL		 6131 /* Need to flush the previous three writes to ensure MSI-X
6132 * is setup properly */
6133 REG_RD(bp, BNX2_PCI_MSIX_CONTROL);
6134
57851d84
MC		 6135 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6136 msix_ent[i].entry = i;
6137 msix_ent[i].vector = 0;
6138 }
6139
379b39a2
MC		 6140 total_vecs = msix_vecs;
6141#ifdef BCM_CNIC
6142 total_vecs++;
6143#endif
6144 rc = -ENOSPC;
6145 while (total_vecs >= BNX2_MIN_MSIX_VEC) {
6146 rc = pci_enable_msix(bp->pdev, msix_ent, total_vecs);
6147 if (rc <= 0)
6148 break;
6149 if (rc > 0)
6150 total_vecs = rc;
6151 }
6152
57851d84
MC		 6153 if (rc != 0)
6154 return;
6155
379b39a2
MC		 6156 msix_vecs = total_vecs;
6157#ifdef BCM_CNIC
6158 msix_vecs--;
6159#endif
5e9ad9e1 6160 bp->irq_nvecs = msix_vecs;
f86e82fb 6161 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
379b39a2 6162 for (i = 0; i < total_vecs; i++) {
57851d84 6163 bp->irq_tbl[i].vector = msix_ent[i].vector;
69010313
MC		 6164 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6165 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6166 }
6d866ffc
MC		 6167}
6168
657d92fe 6169static int
6d866ffc
MC		 6170bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6171{
5e9ad9e1 6172 int cpus = num_online_cpus();
706bf240 6173 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
5e9ad9e1 6174
6d866ffc
MC		 6175 bp->irq_tbl[0].handler = bnx2_interrupt;
6176 strcpy(bp->irq_tbl[0].name, bp->dev->name);
b4b36042
MC		 6177 bp->irq_nvecs = 1;
6178 bp->irq_tbl[0].vector = bp->pdev->irq;
6179
3d5f3a7b 6180 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
5e9ad9e1 6181 bnx2_enable_msix(bp, msix_vecs);
6d866ffc 6182
f86e82fb
DM		 6183 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6184 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6d866ffc 6185 if (pci_enable_msi(bp->pdev) == 0) {
f86e82fb 6186 bp->flags |= BNX2_FLAG_USING_MSI;
6d866ffc 6187 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
f86e82fb 6188 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6d866ffc
MC		 6189 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6190 } else
6191 bp->irq_tbl[0].handler = bnx2_msi;
b4b36042
MC		 6192
6193 bp->irq_tbl[0].vector = bp->pdev->irq;
6d866ffc
MC		 6194 }
6195 }
706bf240
BL		 6196
6197 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
657d92fe 6198 netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings);
706bf240 6199
5e9ad9e1 6200 bp->num_rx_rings = bp->irq_nvecs;
657d92fe 6201 return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings);
8e6a72c4
MC		 6202}
6203
b6016b76
MC		 6204/* Called with rtnl_lock */
6205static int
6206bnx2_open(struct net_device *dev)
6207{
972ec0d4 6208 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6209 int rc;
6210
1b2f922f
MC		 6211 netif_carrier_off(dev);
6212
829ca9a3 6213 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 6214 bnx2_disable_int(bp);
6215
657d92fe
BH		 6216 rc = bnx2_setup_int_mode(bp, disable_msi);
6217 if (rc)
6218 goto open_err;
4327ba43 6219 bnx2_init_napi(bp);
35e9010b 6220 bnx2_napi_enable(bp);
b6016b76 6221 rc = bnx2_alloc_mem(bp);
2739a8bb
MC		 6222 if (rc)
6223 goto open_err;
b6016b76 6224
8e6a72c4 6225 rc = bnx2_request_irq(bp);
2739a8bb
MC		 6226 if (rc)
6227 goto open_err;
b6016b76 6228
9a120bc5 6229 rc = bnx2_init_nic(bp, 1);
2739a8bb
MC		 6230 if (rc)
6231 goto open_err;
6aa20a22 6232
cd339a0e 6233 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6234
6235 atomic_set(&bp->intr_sem, 0);
6236
354fcd77
MC		 6237 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));
6238
b6016b76
MC		 6239 bnx2_enable_int(bp);
6240
f86e82fb 6241 if (bp->flags & BNX2_FLAG_USING_MSI) {
b6016b76
MC		 6242 /* Test MSI to make sure it is working
6243 * If MSI test fails, go back to INTx mode
6244 */
6245 if (bnx2_test_intr(bp) != 0) {
3a9c6a49 6246 netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n");
b6016b76
MC		 6247
6248 bnx2_disable_int(bp);
8e6a72c4 6249 bnx2_free_irq(bp);
b6016b76 6250
6d866ffc
MC		 6251 bnx2_setup_int_mode(bp, 1);
6252
9a120bc5 6253 rc = bnx2_init_nic(bp, 0);
b6016b76 6254
8e6a72c4
MC		 6255 if (!rc)
6256 rc = bnx2_request_irq(bp);
6257
b6016b76 6258 if (rc) {
b6016b76 6259 del_timer_sync(&bp->timer);
2739a8bb 6260 goto open_err;
b6016b76
MC		 6261 }
6262 bnx2_enable_int(bp);
6263 }
6264 }
f86e82fb 6265 if (bp->flags & BNX2_FLAG_USING_MSI)
3a9c6a49 6266 netdev_info(dev, "using MSI\n");
f86e82fb 6267 else if (bp->flags & BNX2_FLAG_USING_MSIX)
3a9c6a49 6268 netdev_info(dev, "using MSIX\n");
b6016b76 6269
706bf240 6270 netif_tx_start_all_queues(dev);
b6016b76
MC		 6271
6272 return 0;
2739a8bb
MC		 6273
6274open_err:
6275 bnx2_napi_disable(bp);
6276 bnx2_free_skbs(bp);
6277 bnx2_free_irq(bp);
6278 bnx2_free_mem(bp);
f048fa9c 6279 bnx2_del_napi(bp);
2739a8bb 6280 return rc;
b6016b76
MC		 6281}
6282
6283static void
c4028958 6284bnx2_reset_task(struct work_struct *work)
b6016b76 6285{
c4028958 6286 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
b6016b76 6287
51bf6bb4
MC		 6288 rtnl_lock();
6289 if (!netif_running(bp->dev)) {
6290 rtnl_unlock();
afdc08b9 6291 return;
51bf6bb4 6292 }
afdc08b9 6293
212f9934 6294 bnx2_netif_stop(bp, true);
b6016b76 6295
9a120bc5 6296 bnx2_init_nic(bp, 1);
b6016b76
MC		 6297
6298 atomic_set(&bp->intr_sem, 1);
212f9934 6299 bnx2_netif_start(bp, true);
51bf6bb4 6300 rtnl_unlock();
b6016b76
MC		 6301}
6302
20175c57
MC		 6303static void
6304bnx2_dump_state(struct bnx2 *bp)
6305{
6306 struct net_device *dev = bp->dev;
5804a8fb
MC		 6307 u32 mcp_p0, mcp_p1, val1, val2;
6308
6309 pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1);
6310 netdev_err(dev, "DEBUG: intr_sem[%x] PCI_CMD[%08x]\n",
6311 atomic_read(&bp->intr_sem), val1);
6312 pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1);
6313 pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2);
6314 netdev_err(dev, "DEBUG: PCI_PM[%08x] PCI_MISC_CFG[%08x]\n", val1, val2);
b98eba52 6315 netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n",
3a9c6a49 6316 REG_RD(bp, BNX2_EMAC_TX_STATUS),
b98eba52
EW		 6317 REG_RD(bp, BNX2_EMAC_RX_STATUS));
6318 netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n",
3a9c6a49 6319 REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
b98eba52
EW		 6320 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6321 mcp_p0 = BNX2_MCP_STATE_P0;
6322 mcp_p1 = BNX2_MCP_STATE_P1;
6323 } else {
6324 mcp_p0 = BNX2_MCP_STATE_P0_5708;
6325 mcp_p1 = BNX2_MCP_STATE_P1_5708;
6326 }
3a9c6a49 6327 netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
b98eba52 6328 bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));
3a9c6a49
JP		 6329 netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
6330 REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
20175c57 6331 if (bp->flags & BNX2_FLAG_USING_MSIX)
3a9c6a49
JP		 6332 netdev_err(dev, "DEBUG: PBA[%08x]\n",
6333 REG_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
20175c57
MC		 6334}
6335
b6016b76
MC		 6336static void
6337bnx2_tx_timeout(struct net_device *dev)
6338{
972ec0d4 6339 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6340
20175c57
MC		 6341 bnx2_dump_state(bp);
6342
b6016b76
MC		 6343 /* This allows the netif to be shutdown gracefully before resetting */
6344 schedule_work(&bp->reset_task);
6345}
6346
932ff279 6347/* Called with netif_tx_lock.
2f8af120
MC		 6348 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6349 * netif_wake_queue().
b6016b76 6350 */
61357325 6351static netdev_tx_t
b6016b76
MC		 6352bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6353{
972ec0d4 6354 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6355 dma_addr_t mapping;
6356 struct tx_bd *txbd;
3d16af86 6357 struct sw_tx_bd *tx_buf;
b6016b76
MC		 6358 u32 len, vlan_tag_flags, last_frag, mss;
6359 u16 prod, ring_prod;
6360 int i;
706bf240
BL		 6361 struct bnx2_napi *bnapi;
6362 struct bnx2_tx_ring_info *txr;
6363 struct netdev_queue *txq;
6364
6365 /* Determine which tx ring we will be placed on */
6366 i = skb_get_queue_mapping(skb);
6367 bnapi = &bp->bnx2_napi[i];
6368 txr = &bnapi->tx_ring;
6369 txq = netdev_get_tx_queue(dev, i);
b6016b76 6370
35e9010b 6371 if (unlikely(bnx2_tx_avail(bp, txr) <
a550c99b 6372 (skb_shinfo(skb)->nr_frags + 1))) {
706bf240 6373 netif_tx_stop_queue(txq);
3a9c6a49 6374 netdev_err(dev, "BUG! Tx ring full when queue awake!\n");
b6016b76
MC		 6375
6376 return NETDEV_TX_BUSY;
6377 }
6378 len = skb_headlen(skb);
35e9010b 6379 prod = txr->tx_prod;
b6016b76
MC		 6380 ring_prod = TX_RING_IDX(prod);
6381
6382 vlan_tag_flags = 0;
84fa7933 6383 if (skb->ip_summed == CHECKSUM_PARTIAL) {
b6016b76
MC		 6384 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6385 }
6386
eab6d18d 6387 if (vlan_tx_tag_present(skb)) {
b6016b76
MC		 6388 vlan_tag_flags |=
6389 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6390 }
7d0fd211 6391
fde82055 6392 if ((mss = skb_shinfo(skb)->gso_size)) {
a1efb4b6 6393 u32 tcp_opt_len;
eddc9ec5 6394 struct iphdr *iph;
b6016b76 6395
b6016b76
MC		 6396 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6397
4666f87a
MC		 6398 tcp_opt_len = tcp_optlen(skb);
6399
6400 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6401 u32 tcp_off = skb_transport_offset(skb) -
6402 sizeof(struct ipv6hdr) - ETH_HLEN;
ab6a5bb6 6403
4666f87a
MC		 6404 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6405 TX_BD_FLAGS_SW_FLAGS;
6406 if (likely(tcp_off == 0))
6407 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6408 else {
6409 tcp_off >>= 3;
6410 vlan_tag_flags |= ((tcp_off & 0x3) <<
6411 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6412 ((tcp_off & 0x10) <<
6413 TX_BD_FLAGS_TCP6_OFF4_SHL);
6414 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6415 }
6416 } else {
4666f87a 6417 iph = ip_hdr(skb);
4666f87a
MC		 6418 if (tcp_opt_len || (iph->ihl > 5)) {
6419 vlan_tag_flags |= ((iph->ihl - 5) +
6420 (tcp_opt_len >> 2)) << 8;
6421 }
b6016b76 6422 }
4666f87a 6423 } else
b6016b76 6424 mss = 0;
b6016b76 6425
36227e88
SG		 6426 mapping = dma_map_single(&bp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
6427 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
3d16af86
BL		 6428 dev_kfree_skb(skb);
6429 return NETDEV_TX_OK;
6430 }
6431
35e9010b 6432 tx_buf = &txr->tx_buf_ring[ring_prod];
b6016b76 6433 tx_buf->skb = skb;
1a4ccc2d 6434 dma_unmap_addr_set(tx_buf, mapping, mapping);
b6016b76 6435
35e9010b 6436 txbd = &txr->tx_desc_ring[ring_prod];
b6016b76
MC		 6437
6438 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6439 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6440 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6441 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6442
6443 last_frag = skb_shinfo(skb)->nr_frags;
d62fda08
ED		 6444 tx_buf->nr_frags = last_frag;
6445 tx_buf->is_gso = skb_is_gso(skb);
b6016b76
MC		 6446
6447 for (i = 0; i < last_frag; i++) {
6448 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6449
6450 prod = NEXT_TX_BD(prod);
6451 ring_prod = TX_RING_IDX(prod);
35e9010b 6452 txbd = &txr->tx_desc_ring[ring_prod];
b6016b76
MC		 6453
6454 len = frag->size;
36227e88
SG		 6455 mapping = dma_map_page(&bp->pdev->dev, frag->page, frag->page_offset,
6456 len, PCI_DMA_TODEVICE);
6457 if (dma_mapping_error(&bp->pdev->dev, mapping))
e95524a7 6458 goto dma_error;
1a4ccc2d 6459 dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
e95524a7 6460 mapping);
b6016b76
MC		 6461
6462 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6463 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6464 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6465 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6466
6467 }
6468 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6469
6470 prod = NEXT_TX_BD(prod);
35e9010b 6471 txr->tx_prod_bseq += skb->len;
b6016b76 6472
35e9010b
MC		 6473 REG_WR16(bp, txr->tx_bidx_addr, prod);
6474 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
b6016b76
MC		 6475
6476 mmiowb();
6477
35e9010b 6478 txr->tx_prod = prod;
b6016b76 6479
35e9010b 6480 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
706bf240 6481 netif_tx_stop_queue(txq);
11848b96
MC		 6482
6483 /* netif_tx_stop_queue() must be done before checking
6484 * tx index in bnx2_tx_avail() below, because in
6485 * bnx2_tx_int(), we update tx index before checking for
6486 * netif_tx_queue_stopped().
6487 */
6488 smp_mb();
35e9010b 6489 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
706bf240 6490 netif_tx_wake_queue(txq);
b6016b76
MC		 6491 }
6492
e95524a7
AD		 6493 return NETDEV_TX_OK;
6494dma_error:
6495 /* save value of frag that failed */
6496 last_frag = i;
6497
6498 /* start back at beginning and unmap skb */
6499 prod = txr->tx_prod;
6500 ring_prod = TX_RING_IDX(prod);
6501 tx_buf = &txr->tx_buf_ring[ring_prod];
6502 tx_buf->skb = NULL;
36227e88 6503 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 6504 skb_headlen(skb), PCI_DMA_TODEVICE);
6505
6506 /* unmap remaining mapped pages */
6507 for (i = 0; i < last_frag; i++) {
6508 prod = NEXT_TX_BD(prod);
6509 ring_prod = TX_RING_IDX(prod);
6510 tx_buf = &txr->tx_buf_ring[ring_prod];
36227e88 6511 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 6512 skb_shinfo(skb)->frags[i].size,
6513 PCI_DMA_TODEVICE);
6514 }
6515
6516 dev_kfree_skb(skb);
b6016b76
MC		 6517 return NETDEV_TX_OK;
6518}
6519
6520/* Called with rtnl_lock */
6521static int
6522bnx2_close(struct net_device *dev)
6523{
972ec0d4 6524 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6525
4bb073c0 6526 cancel_work_sync(&bp->reset_task);
afdc08b9 6527
bea3348e 6528 bnx2_disable_int_sync(bp);
35efa7c1 6529 bnx2_napi_disable(bp);
b6016b76 6530 del_timer_sync(&bp->timer);
74bf4ba3 6531 bnx2_shutdown_chip(bp);
8e6a72c4 6532 bnx2_free_irq(bp);
b6016b76
MC		 6533 bnx2_free_skbs(bp);
6534 bnx2_free_mem(bp);
f048fa9c 6535 bnx2_del_napi(bp);
b6016b76
MC		 6536 bp->link_up = 0;
6537 netif_carrier_off(bp->dev);
829ca9a3 6538 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 6539 return 0;
6540}
6541
354fcd77
MC		 6542static void
6543bnx2_save_stats(struct bnx2 *bp)
6544{
6545 u32 *hw_stats = (u32 *) bp->stats_blk;
6546 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
6547 int i;
6548
6549 /* The 1st 10 counters are 64-bit counters */
6550 for (i = 0; i < 20; i += 2) {
6551 u32 hi;
6552 u64 lo;
6553
c9885fe5
PR		 6554 hi = temp_stats[i] + hw_stats[i];
6555 lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1];
354fcd77
MC		 6556 if (lo > 0xffffffff)
6557 hi++;
c9885fe5
PR		 6558 temp_stats[i] = hi;
6559 temp_stats[i + 1] = lo & 0xffffffff;
354fcd77
MC		 6560 }
6561
6562 for ( ; i < sizeof(struct statistics_block) / 4; i++)
c9885fe5 6563 temp_stats[i] += hw_stats[i];
354fcd77
MC		 6564}
6565
5d07bf26
ED		 6566#define GET_64BIT_NET_STATS64(ctr) \
6567 (((u64) (ctr##_hi) << 32) + (u64) (ctr##_lo))
b6016b76 6568
a4743058 6569#define GET_64BIT_NET_STATS(ctr) \
354fcd77
MC		 6570 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
6571 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
b6016b76 6572
a4743058 6573#define GET_32BIT_NET_STATS(ctr) \
354fcd77
MC		 6574 (unsigned long) (bp->stats_blk->ctr + \
6575 bp->temp_stats_blk->ctr)
a4743058 6576
5d07bf26
ED		 6577static struct rtnl_link_stats64 *
6578bnx2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats)
b6016b76 6579{
972ec0d4 6580 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6581
5d07bf26 6582 if (bp->stats_blk == NULL)
b6016b76 6583 return net_stats;
5d07bf26 6584
b6016b76 6585 net_stats->rx_packets =
a4743058
MC		 6586 GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) +
6587 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) +
6588 GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts);
b6016b76
MC		 6589
6590 net_stats->tx_packets =
a4743058
MC		 6591 GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) +
6592 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) +
6593 GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts);
b6016b76
MC		 6594
6595 net_stats->rx_bytes =
a4743058 6596 GET_64BIT_NET_STATS(stat_IfHCInOctets);
b6016b76
MC		 6597
6598 net_stats->tx_bytes =
a4743058 6599 GET_64BIT_NET_STATS(stat_IfHCOutOctets);
b6016b76 6600
6aa20a22 6601 net_stats->multicast =
6fdae995 6602 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts);
b6016b76 6603
6aa20a22 6604 net_stats->collisions =
a4743058 6605 GET_32BIT_NET_STATS(stat_EtherStatsCollisions);
b6016b76 6606
6aa20a22 6607 net_stats->rx_length_errors =
a4743058
MC		 6608 GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) +
6609 GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts);
b6016b76 6610
6aa20a22 6611 net_stats->rx_over_errors =
a4743058
MC		 6612 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6613 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards);
b6016b76 6614
6aa20a22 6615 net_stats->rx_frame_errors =
a4743058 6616 GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors);
b6016b76 6617
6aa20a22 6618 net_stats->rx_crc_errors =
a4743058 6619 GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors);
b6016b76
MC		 6620
6621 net_stats->rx_errors = net_stats->rx_length_errors +
6622 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6623 net_stats->rx_crc_errors;
6624
6625 net_stats->tx_aborted_errors =
a4743058
MC		 6626 GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) +
6627 GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions);
b6016b76 6628
5b0c76ad
MC		 6629 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6630 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76
MC		 6631 net_stats->tx_carrier_errors = 0;
6632 else {
6633 net_stats->tx_carrier_errors =
a4743058 6634 GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors);
b6016b76
MC		 6635 }
6636
6637 net_stats->tx_errors =
a4743058 6638 GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) +
b6016b76
MC		 6639 net_stats->tx_aborted_errors +
6640 net_stats->tx_carrier_errors;
6641
cea94db9 6642 net_stats->rx_missed_errors =
a4743058
MC		 6643 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6644 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) +
6645 GET_32BIT_NET_STATS(stat_FwRxDrop);
cea94db9 6646
b6016b76
MC		 6647 return net_stats;
6648}
6649
6650/* All ethtool functions called with rtnl_lock */
6651
6652static int
6653bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6654{
972ec0d4 6655 struct bnx2 *bp = netdev_priv(dev);
7b6b8347 6656 int support_serdes = 0, support_copper = 0;
b6016b76
MC		 6657
6658 cmd->supported = SUPPORTED_Autoneg;
583c28e5 6659 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6660 support_serdes = 1;
6661 support_copper = 1;
6662 } else if (bp->phy_port == PORT_FIBRE)
6663 support_serdes = 1;
6664 else
6665 support_copper = 1;
6666
6667 if (support_serdes) {
b6016b76
MC		 6668 cmd->supported |= SUPPORTED_1000baseT_Full |
6669 SUPPORTED_FIBRE;
583c28e5 6670 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
605a9e20 6671 cmd->supported |= SUPPORTED_2500baseX_Full;
b6016b76 6672
b6016b76 6673 }
7b6b8347 6674 if (support_copper) {
b6016b76
MC		 6675 cmd->supported |= SUPPORTED_10baseT_Half |
6676 SUPPORTED_10baseT_Full |
6677 SUPPORTED_100baseT_Half |
6678 SUPPORTED_100baseT_Full |
6679 SUPPORTED_1000baseT_Full |
6680 SUPPORTED_TP;
6681
b6016b76
MC		 6682 }
6683
7b6b8347
MC		 6684 spin_lock_bh(&bp->phy_lock);
6685 cmd->port = bp->phy_port;
b6016b76
MC		 6686 cmd->advertising = bp->advertising;
6687
6688 if (bp->autoneg & AUTONEG_SPEED) {
6689 cmd->autoneg = AUTONEG_ENABLE;
6690 }
6691 else {
6692 cmd->autoneg = AUTONEG_DISABLE;
6693 }
6694
6695 if (netif_carrier_ok(dev)) {
6696 cmd->speed = bp->line_speed;
6697 cmd->duplex = bp->duplex;
6698 }
6699 else {
6700 cmd->speed = -1;
6701 cmd->duplex = -1;
6702 }
7b6b8347 6703 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6704
6705 cmd->transceiver = XCVR_INTERNAL;
6706 cmd->phy_address = bp->phy_addr;
6707
6708 return 0;
6709}
6aa20a22 6710
b6016b76
MC		 6711static int
6712bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6713{
972ec0d4 6714 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6715 u8 autoneg = bp->autoneg;
6716 u8 req_duplex = bp->req_duplex;
6717 u16 req_line_speed = bp->req_line_speed;
6718 u32 advertising = bp->advertising;
7b6b8347
MC		 6719 int err = -EINVAL;
6720
6721 spin_lock_bh(&bp->phy_lock);
6722
6723 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6724 goto err_out_unlock;
6725
583c28e5
MC		 6726 if (cmd->port != bp->phy_port &&
6727 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
7b6b8347 6728 goto err_out_unlock;
b6016b76 6729
d6b14486
MC		 6730 /* If device is down, we can store the settings only if the user
6731 * is setting the currently active port.
6732 */
6733 if (!netif_running(dev) && cmd->port != bp->phy_port)
6734 goto err_out_unlock;
6735
b6016b76
MC		 6736 if (cmd->autoneg == AUTONEG_ENABLE) {
6737 autoneg |= AUTONEG_SPEED;
6738
beb499af
MC		 6739 advertising = cmd->advertising;
6740 if (cmd->port == PORT_TP) {
6741 advertising &= ETHTOOL_ALL_COPPER_SPEED;
6742 if (!advertising)
b6016b76 6743 advertising = ETHTOOL_ALL_COPPER_SPEED;
beb499af
MC		 6744 } else {
6745 advertising &= ETHTOOL_ALL_FIBRE_SPEED;
6746 if (!advertising)
6747 advertising = ETHTOOL_ALL_FIBRE_SPEED;
b6016b76
MC		 6748 }
6749 advertising |= ADVERTISED_Autoneg;
6750 }
6751 else {
7b6b8347 6752 if (cmd->port == PORT_FIBRE) {
80be4434
MC		 6753 if ((cmd->speed != SPEED_1000 &&
6754 cmd->speed != SPEED_2500) ||
6755 (cmd->duplex != DUPLEX_FULL))
7b6b8347 6756 goto err_out_unlock;
80be4434
MC		 6757
6758 if (cmd->speed == SPEED_2500 &&
583c28e5 6759 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
7b6b8347 6760 goto err_out_unlock;
b6016b76 6761 }
7b6b8347
MC		 6762 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6763 goto err_out_unlock;
6764
b6016b76
MC		 6765 autoneg &= ~AUTONEG_SPEED;
6766 req_line_speed = cmd->speed;
6767 req_duplex = cmd->duplex;
6768 advertising = 0;
6769 }
6770
6771 bp->autoneg = autoneg;
6772 bp->advertising = advertising;
6773 bp->req_line_speed = req_line_speed;
6774 bp->req_duplex = req_duplex;
6775
d6b14486
MC		 6776 err = 0;
6777 /* If device is down, the new settings will be picked up when it is
6778 * brought up.
6779 */
6780 if (netif_running(dev))
6781 err = bnx2_setup_phy(bp, cmd->port);
b6016b76 6782
7b6b8347 6783err_out_unlock:
c770a65c 6784 spin_unlock_bh(&bp->phy_lock);
b6016b76 6785
7b6b8347 6786 return err;
b6016b76
MC		 6787}
6788
6789static void
6790bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6791{
972ec0d4 6792 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6793
6794 strcpy(info->driver, DRV_MODULE_NAME);
6795 strcpy(info->version, DRV_MODULE_VERSION);
6796 strcpy(info->bus_info, pci_name(bp->pdev));
58fc2ea4 6797 strcpy(info->fw_version, bp->fw_version);
b6016b76
MC		 6798}
6799
244ac4f4
MC		 6800#define BNX2_REGDUMP_LEN (32 * 1024)
6801
6802static int
6803bnx2_get_regs_len(struct net_device *dev)
6804{
6805 return BNX2_REGDUMP_LEN;
6806}
6807
6808static void
6809bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6810{
6811 u32 *p = _p, i, offset;
6812 u8 *orig_p = _p;
6813 struct bnx2 *bp = netdev_priv(dev);
b6bc7650
JP		 6814 static const u32 reg_boundaries[] = {
6815 0x0000, 0x0098, 0x0400, 0x045c,
6816 0x0800, 0x0880, 0x0c00, 0x0c10,
6817 0x0c30, 0x0d08, 0x1000, 0x101c,
6818 0x1040, 0x1048, 0x1080, 0x10a4,
6819 0x1400, 0x1490, 0x1498, 0x14f0,
6820 0x1500, 0x155c, 0x1580, 0x15dc,
6821 0x1600, 0x1658, 0x1680, 0x16d8,
6822 0x1800, 0x1820, 0x1840, 0x1854,
6823 0x1880, 0x1894, 0x1900, 0x1984,
6824 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6825 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6826 0x2000, 0x2030, 0x23c0, 0x2400,
6827 0x2800, 0x2820, 0x2830, 0x2850,
6828 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6829 0x3c00, 0x3c94, 0x4000, 0x4010,
6830 0x4080, 0x4090, 0x43c0, 0x4458,
6831 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6832 0x4fc0, 0x5010, 0x53c0, 0x5444,
6833 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6834 0x5fc0, 0x6000, 0x6400, 0x6428,
6835 0x6800, 0x6848, 0x684c, 0x6860,
6836 0x6888, 0x6910, 0x8000
6837 };
244ac4f4
MC		 6838
6839 regs->version = 0;
6840
6841 memset(p, 0, BNX2_REGDUMP_LEN);
6842
6843 if (!netif_running(bp->dev))
6844 return;
6845
6846 i = 0;
6847 offset = reg_boundaries[0];
6848 p += offset;
6849 while (offset < BNX2_REGDUMP_LEN) {
6850 *p++ = REG_RD(bp, offset);
6851 offset += 4;
6852 if (offset == reg_boundaries[i + 1]) {
6853 offset = reg_boundaries[i + 2];
6854 p = (u32 *) (orig_p + offset);
6855 i += 2;
6856 }
6857 }
6858}
6859
b6016b76
MC		 6860static void
6861bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6862{
972ec0d4 6863 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6864
f86e82fb 6865 if (bp->flags & BNX2_FLAG_NO_WOL) {
b6016b76
MC		 6866 wol->supported = 0;
6867 wol->wolopts = 0;
6868 }
6869 else {
6870 wol->supported = WAKE_MAGIC;
6871 if (bp->wol)
6872 wol->wolopts = WAKE_MAGIC;
6873 else
6874 wol->wolopts = 0;
6875 }
6876 memset(&wol->sopass, 0, sizeof(wol->sopass));
6877}
6878
6879static int
6880bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6881{
972ec0d4 6882 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6883
6884 if (wol->wolopts & ~WAKE_MAGIC)
6885 return -EINVAL;
6886
6887 if (wol->wolopts & WAKE_MAGIC) {
f86e82fb 6888 if (bp->flags & BNX2_FLAG_NO_WOL)
b6016b76
MC		 6889 return -EINVAL;
6890
6891 bp->wol = 1;
6892 }
6893 else {
6894 bp->wol = 0;
6895 }
6896 return 0;
6897}
6898
6899static int
6900bnx2_nway_reset(struct net_device *dev)
6901{
972ec0d4 6902 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6903 u32 bmcr;
6904
9f52b564
MC		 6905 if (!netif_running(dev))
6906 return -EAGAIN;
6907
b6016b76
MC		 6908 if (!(bp->autoneg & AUTONEG_SPEED)) {
6909 return -EINVAL;
6910 }
6911
c770a65c 6912 spin_lock_bh(&bp->phy_lock);
b6016b76 6913
583c28e5 6914 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6915 int rc;
6916
6917 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6918 spin_unlock_bh(&bp->phy_lock);
6919 return rc;
6920 }
6921
b6016b76 6922 /* Force a link down visible on the other side */
583c28e5 6923 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
ca58c3af 6924 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
c770a65c 6925 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6926
6927 msleep(20);
6928
c770a65c 6929 spin_lock_bh(&bp->phy_lock);
f8dd064e 6930
40105c0b 6931 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
f8dd064e
MC		 6932 bp->serdes_an_pending = 1;
6933 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6934 }
6935
ca58c3af 6936 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 6937 bmcr &= ~BMCR_LOOPBACK;
ca58c3af 6938 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
b6016b76 6939
c770a65c 6940 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6941
6942 return 0;
6943}
6944
7959ea25
ON		 6945static u32
6946bnx2_get_link(struct net_device *dev)
6947{
6948 struct bnx2 *bp = netdev_priv(dev);
6949
6950 return bp->link_up;
6951}
6952
b6016b76
MC		 6953static int
6954bnx2_get_eeprom_len(struct net_device *dev)
6955{
972ec0d4 6956 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6957
1122db71 6958 if (bp->flash_info == NULL)
b6016b76
MC		 6959 return 0;
6960
1122db71 6961 return (int) bp->flash_size;
b6016b76
MC		 6962}
6963
6964static int
6965bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6966 u8 *eebuf)
6967{
972ec0d4 6968 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6969 int rc;
6970
9f52b564
MC		 6971 if (!netif_running(dev))
6972 return -EAGAIN;
6973
1064e944 6974 /* parameters already validated in ethtool_get_eeprom */
b6016b76
MC		 6975
6976 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6977
6978 return rc;
6979}
6980
6981static int
6982bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6983 u8 *eebuf)
6984{
972ec0d4 6985 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6986 int rc;
6987
9f52b564
MC		 6988 if (!netif_running(dev))
6989 return -EAGAIN;
6990
1064e944 6991 /* parameters already validated in ethtool_set_eeprom */
b6016b76
MC		 6992
6993 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6994
6995 return rc;
6996}
6997
6998static int
6999bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7000{
972ec0d4 7001 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7002
7003 memset(coal, 0, sizeof(struct ethtool_coalesce));
7004
7005 coal->rx_coalesce_usecs = bp->rx_ticks;
7006 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
7007 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
7008 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
7009
7010 coal->tx_coalesce_usecs = bp->tx_ticks;
7011 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
7012 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
7013 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
7014
7015 coal->stats_block_coalesce_usecs = bp->stats_ticks;
7016
7017 return 0;
7018}
7019
7020static int
7021bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7022{
972ec0d4 7023 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7024
7025 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7026 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
7027
6aa20a22 7028 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
b6016b76
MC		 7029 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
7030
7031 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
7032 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
7033
7034 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
7035 if (bp->rx_quick_cons_trip_int > 0xff)
7036 bp->rx_quick_cons_trip_int = 0xff;
7037
7038 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7039 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
7040
7041 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
7042 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
7043
7044 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
7045 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7046
7047 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7048 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7049 0xff;
7050
7051 bp->stats_ticks = coal->stats_block_coalesce_usecs;
61d9e3fa 7052 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
02537b06
MC		 7053 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7054 bp->stats_ticks = USEC_PER_SEC;
7055 }
7ea6920e
MC		 7056 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7057 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7058 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76
MC		 7059
7060 if (netif_running(bp->dev)) {
212f9934 7061 bnx2_netif_stop(bp, true);
9a120bc5 7062 bnx2_init_nic(bp, 0);
212f9934 7063 bnx2_netif_start(bp, true);
b6016b76
MC		 7064 }
7065
7066 return 0;
7067}
7068
7069static void
7070bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7071{
972ec0d4 7072 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7073
13daffa2 7074 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
b6016b76 7075 ering->rx_mini_max_pending = 0;
47bf4246 7076 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
b6016b76
MC		 7077
7078 ering->rx_pending = bp->rx_ring_size;
7079 ering->rx_mini_pending = 0;
47bf4246 7080 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
b6016b76
MC		 7081
7082 ering->tx_max_pending = MAX_TX_DESC_CNT;
7083 ering->tx_pending = bp->tx_ring_size;
7084}
7085
7086static int
5d5d0015 7087bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
b6016b76 7088{
13daffa2 7089 if (netif_running(bp->dev)) {
354fcd77
MC		 7090 /* Reset will erase chipset stats; save them */
7091 bnx2_save_stats(bp);
7092
212f9934 7093 bnx2_netif_stop(bp, true);
13daffa2
MC		 7094 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
7095 bnx2_free_skbs(bp);
7096 bnx2_free_mem(bp);
7097 }
7098
5d5d0015
MC		 7099 bnx2_set_rx_ring_size(bp, rx);
7100 bp->tx_ring_size = tx;
b6016b76
MC		 7101
7102 if (netif_running(bp->dev)) {
13daffa2
MC		 7103 int rc;
7104
7105 rc = bnx2_alloc_mem(bp);
6fefb65e
MC		 7106 if (!rc)
7107 rc = bnx2_init_nic(bp, 0);
7108
7109 if (rc) {
7110 bnx2_napi_enable(bp);
7111 dev_close(bp->dev);
13daffa2 7112 return rc;
6fefb65e 7113 }
e9f26c49
MC		 7114#ifdef BCM_CNIC
7115 mutex_lock(&bp->cnic_lock);
7116 /* Let cnic know about the new status block. */
7117 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)
7118 bnx2_setup_cnic_irq_info(bp);
7119 mutex_unlock(&bp->cnic_lock);
7120#endif
212f9934 7121 bnx2_netif_start(bp, true);
b6016b76 7122 }
b6016b76
MC		 7123 return 0;
7124}
7125
5d5d0015
MC		 7126static int
7127bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7128{
7129 struct bnx2 *bp = netdev_priv(dev);
7130 int rc;
7131
7132 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
7133 (ering->tx_pending > MAX_TX_DESC_CNT) ||
7134 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7135
7136 return -EINVAL;
7137 }
7138 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
7139 return rc;
7140}
7141
b6016b76
MC		 7142static void
7143bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7144{
972ec0d4 7145 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7146
7147 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7148 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7149 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7150}
7151
7152static int
7153bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7154{
972ec0d4 7155 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7156
7157 bp->req_flow_ctrl = 0;
7158 if (epause->rx_pause)
7159 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7160 if (epause->tx_pause)
7161 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7162
7163 if (epause->autoneg) {
7164 bp->autoneg |= AUTONEG_FLOW_CTRL;
7165 }
7166 else {
7167 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7168 }
7169
9f52b564
MC		 7170 if (netif_running(dev)) {
7171 spin_lock_bh(&bp->phy_lock);
7172 bnx2_setup_phy(bp, bp->phy_port);
7173 spin_unlock_bh(&bp->phy_lock);
7174 }
b6016b76
MC		 7175
7176 return 0;
7177}
7178
7179static u32
7180bnx2_get_rx_csum(struct net_device *dev)
7181{
972ec0d4 7182 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7183
7184 return bp->rx_csum;
7185}
7186
7187static int
7188bnx2_set_rx_csum(struct net_device *dev, u32 data)
7189{
972ec0d4 7190 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7191
7192 bp->rx_csum = data;
7193 return 0;
7194}
7195
b11d6213
MC		 7196static int
7197bnx2_set_tso(struct net_device *dev, u32 data)
7198{
4666f87a
MC		 7199 struct bnx2 *bp = netdev_priv(dev);
7200
7201 if (data) {
b11d6213 7202 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
4666f87a
MC		 7203 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7204 dev->features |= NETIF_F_TSO6;
7205 } else
7206 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
7207 NETIF_F_TSO_ECN);
b11d6213
MC		 7208 return 0;
7209}
7210
14ab9b86 7211static struct {
b6016b76 7212 char string[ETH_GSTRING_LEN];
790dab2f 7213} bnx2_stats_str_arr[] = {
b6016b76
MC		 7214 { "rx_bytes" },
7215 { "rx_error_bytes" },
7216 { "tx_bytes" },
7217 { "tx_error_bytes" },
7218 { "rx_ucast_packets" },
7219 { "rx_mcast_packets" },
7220 { "rx_bcast_packets" },
7221 { "tx_ucast_packets" },
7222 { "tx_mcast_packets" },
7223 { "tx_bcast_packets" },
7224 { "tx_mac_errors" },
7225 { "tx_carrier_errors" },
7226 { "rx_crc_errors" },
7227 { "rx_align_errors" },
7228 { "tx_single_collisions" },
7229 { "tx_multi_collisions" },
7230 { "tx_deferred" },
7231 { "tx_excess_collisions" },
7232 { "tx_late_collisions" },
7233 { "tx_total_collisions" },
7234 { "rx_fragments" },
7235 { "rx_jabbers" },
7236 { "rx_undersize_packets" },
7237 { "rx_oversize_packets" },
7238 { "rx_64_byte_packets" },
7239 { "rx_65_to_127_byte_packets" },
7240 { "rx_128_to_255_byte_packets" },
7241 { "rx_256_to_511_byte_packets" },
7242 { "rx_512_to_1023_byte_packets" },
7243 { "rx_1024_to_1522_byte_packets" },
7244 { "rx_1523_to_9022_byte_packets" },
7245 { "tx_64_byte_packets" },
7246 { "tx_65_to_127_byte_packets" },
7247 { "tx_128_to_255_byte_packets" },
7248 { "tx_256_to_511_byte_packets" },
7249 { "tx_512_to_1023_byte_packets" },
7250 { "tx_1024_to_1522_byte_packets" },
7251 { "tx_1523_to_9022_byte_packets" },
7252 { "rx_xon_frames" },
7253 { "rx_xoff_frames" },
7254 { "tx_xon_frames" },
7255 { "tx_xoff_frames" },
7256 { "rx_mac_ctrl_frames" },
7257 { "rx_filtered_packets" },
790dab2f 7258 { "rx_ftq_discards" },
b6016b76 7259 { "rx_discards" },
cea94db9 7260 { "rx_fw_discards" },
b6016b76
MC		 7261};
7262
790dab2f
MC		 7263#define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\
7264 sizeof(bnx2_stats_str_arr[0]))
7265
b6016b76
MC		 7266#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7267
f71e1309 7268static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 7269 STATS_OFFSET32(stat_IfHCInOctets_hi),
7270 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7271 STATS_OFFSET32(stat_IfHCOutOctets_hi),
7272 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7273 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7274 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7275 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7276 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7277 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7278 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7279 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6aa20a22
JG		 7280 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7281 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7282 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7283 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7284 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7285 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7286 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7287 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7288 STATS_OFFSET32(stat_EtherStatsCollisions),
7289 STATS_OFFSET32(stat_EtherStatsFragments),
7290 STATS_OFFSET32(stat_EtherStatsJabbers),
7291 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7292 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7293 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7294 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7295 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7296 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7297 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7298 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7299 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7300 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7301 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7302 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7303 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7304 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7305 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7306 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7307 STATS_OFFSET32(stat_XonPauseFramesReceived),
7308 STATS_OFFSET32(stat_XoffPauseFramesReceived),
7309 STATS_OFFSET32(stat_OutXonSent),
7310 STATS_OFFSET32(stat_OutXoffSent),
7311 STATS_OFFSET32(stat_MacControlFramesReceived),
7312 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
790dab2f 7313 STATS_OFFSET32(stat_IfInFTQDiscards),
6aa20a22 7314 STATS_OFFSET32(stat_IfInMBUFDiscards),
cea94db9 7315 STATS_OFFSET32(stat_FwRxDrop),
b6016b76
MC		 7316};
7317
7318/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7319 * skipped because of errata.
6aa20a22 7320 */
14ab9b86 7321static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 7322 8,0,8,8,8,8,8,8,8,8,
7323 4,0,4,4,4,4,4,4,4,4,
7324 4,4,4,4,4,4,4,4,4,4,
7325 4,4,4,4,4,4,4,4,4,4,
790dab2f 7326 4,4,4,4,4,4,4,
b6016b76
MC		 7327};
7328
5b0c76ad
MC		 7329static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7330 8,0,8,8,8,8,8,8,8,8,
7331 4,4,4,4,4,4,4,4,4,4,
7332 4,4,4,4,4,4,4,4,4,4,
7333 4,4,4,4,4,4,4,4,4,4,
790dab2f 7334 4,4,4,4,4,4,4,
5b0c76ad
MC		 7335};
7336
b6016b76
MC		 7337#define BNX2_NUM_TESTS 6
7338
14ab9b86 7339static struct {
b6016b76
MC		 7340 char string[ETH_GSTRING_LEN];
7341} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7342 { "register_test (offline)" },
7343 { "memory_test (offline)" },
7344 { "loopback_test (offline)" },
7345 { "nvram_test (online)" },
7346 { "interrupt_test (online)" },
7347 { "link_test (online)" },
7348};
7349
7350static int
b9f2c044 7351bnx2_get_sset_count(struct net_device *dev, int sset)
b6016b76 7352{
b9f2c044
JG		 7353 switch (sset) {
7354 case ETH_SS_TEST:
7355 return BNX2_NUM_TESTS;
7356 case ETH_SS_STATS:
7357 return BNX2_NUM_STATS;
7358 default:
7359 return -EOPNOTSUPP;
7360 }
b6016b76
MC		 7361}
7362
7363static void
7364bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7365{
972ec0d4 7366 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7367
9f52b564
MC		 7368 bnx2_set_power_state(bp, PCI_D0);
7369
b6016b76
MC		 7370 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7371 if (etest->flags & ETH_TEST_FL_OFFLINE) {
80be4434
MC		 7372 int i;
7373
212f9934 7374 bnx2_netif_stop(bp, true);
b6016b76
MC		 7375 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7376 bnx2_free_skbs(bp);
7377
7378 if (bnx2_test_registers(bp) != 0) {
7379 buf[0] = 1;
7380 etest->flags |= ETH_TEST_FL_FAILED;
7381 }
7382 if (bnx2_test_memory(bp) != 0) {
7383 buf[1] = 1;
7384 etest->flags |= ETH_TEST_FL_FAILED;
7385 }
bc5a0690 7386 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
b6016b76 7387 etest->flags |= ETH_TEST_FL_FAILED;
b6016b76 7388
9f52b564
MC		 7389 if (!netif_running(bp->dev))
7390 bnx2_shutdown_chip(bp);
b6016b76 7391 else {
9a120bc5 7392 bnx2_init_nic(bp, 1);
212f9934 7393 bnx2_netif_start(bp, true);
b6016b76
MC		 7394 }
7395
7396 /* wait for link up */
80be4434
MC		 7397 for (i = 0; i < 7; i++) {
7398 if (bp->link_up)
7399 break;
7400 msleep_interruptible(1000);
7401 }
b6016b76
MC		 7402 }
7403
7404 if (bnx2_test_nvram(bp) != 0) {
7405 buf[3] = 1;
7406 etest->flags |= ETH_TEST_FL_FAILED;
7407 }
7408 if (bnx2_test_intr(bp) != 0) {
7409 buf[4] = 1;
7410 etest->flags |= ETH_TEST_FL_FAILED;
7411 }
7412
7413 if (bnx2_test_link(bp) != 0) {
7414 buf[5] = 1;
7415 etest->flags |= ETH_TEST_FL_FAILED;
7416
7417 }
9f52b564
MC		 7418 if (!netif_running(bp->dev))
7419 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 7420}
7421
7422static void
7423bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7424{
7425 switch (stringset) {
7426 case ETH_SS_STATS:
7427 memcpy(buf, bnx2_stats_str_arr,
7428 sizeof(bnx2_stats_str_arr));
7429 break;
7430 case ETH_SS_TEST:
7431 memcpy(buf, bnx2_tests_str_arr,
7432 sizeof(bnx2_tests_str_arr));
7433 break;
7434 }
7435}
7436
b6016b76
MC		 7437static void
7438bnx2_get_ethtool_stats(struct net_device *dev,
7439 struct ethtool_stats *stats, u64 *buf)
7440{
972ec0d4 7441 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7442 int i;
7443 u32 *hw_stats = (u32 *) bp->stats_blk;
354fcd77 7444 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
14ab9b86 7445 u8 *stats_len_arr = NULL;
b6016b76
MC		 7446
7447 if (hw_stats == NULL) {
7448 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7449 return;
7450 }
7451
5b0c76ad
MC		 7452 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7453 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7454 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7455 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76 7456 stats_len_arr = bnx2_5706_stats_len_arr;
5b0c76ad
MC		 7457 else
7458 stats_len_arr = bnx2_5708_stats_len_arr;
b6016b76
MC		 7459
7460 for (i = 0; i < BNX2_NUM_STATS; i++) {
354fcd77
MC		 7461 unsigned long offset;
7462
b6016b76
MC		 7463 if (stats_len_arr[i] == 0) {
7464 /* skip this counter */
7465 buf[i] = 0;
7466 continue;
7467 }
354fcd77
MC		 7468
7469 offset = bnx2_stats_offset_arr[i];
b6016b76
MC		 7470 if (stats_len_arr[i] == 4) {
7471 /* 4-byte counter */
354fcd77
MC		 7472 buf[i] = (u64) *(hw_stats + offset) +
7473 *(temp_stats + offset);
b6016b76
MC		 7474 continue;
7475 }
7476 /* 8-byte counter */
354fcd77
MC		 7477 buf[i] = (((u64) *(hw_stats + offset)) << 32) +
7478 *(hw_stats + offset + 1) +
7479 (((u64) *(temp_stats + offset)) << 32) +
7480 *(temp_stats + offset + 1);
b6016b76
MC		 7481 }
7482}
7483
7484static int
7485bnx2_phys_id(struct net_device *dev, u32 data)
7486{
972ec0d4 7487 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7488 int i;
7489 u32 save;
7490
9f52b564
MC		 7491 bnx2_set_power_state(bp, PCI_D0);
7492
b6016b76
MC		 7493 if (data == 0)
7494 data = 2;
7495
7496 save = REG_RD(bp, BNX2_MISC_CFG);
7497 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7498
7499 for (i = 0; i < (data * 2); i++) {
7500 if ((i % 2) == 0) {
7501 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7502 }
7503 else {
7504 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7505 BNX2_EMAC_LED_1000MB_OVERRIDE |
7506 BNX2_EMAC_LED_100MB_OVERRIDE |
7507 BNX2_EMAC_LED_10MB_OVERRIDE |
7508 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7509 BNX2_EMAC_LED_TRAFFIC);
7510 }
7511 msleep_interruptible(500);
7512 if (signal_pending(current))
7513 break;
7514 }
7515 REG_WR(bp, BNX2_EMAC_LED, 0);
7516 REG_WR(bp, BNX2_MISC_CFG, save);
9f52b564
MC		 7517
7518 if (!netif_running(dev))
7519 bnx2_set_power_state(bp, PCI_D3hot);
7520
b6016b76
MC		 7521 return 0;
7522}
7523
4666f87a
MC		 7524static int
7525bnx2_set_tx_csum(struct net_device *dev, u32 data)
7526{
7527 struct bnx2 *bp = netdev_priv(dev);
7528
7529 if (CHIP_NUM(bp) == CHIP_NUM_5709)
807540ba 7530 return ethtool_op_set_tx_ipv6_csum(dev, data);
4666f87a 7531 else
807540ba 7532 return ethtool_op_set_tx_csum(dev, data);
4666f87a
MC		 7533}
7534
fdc8541d
MC		 7535static int
7536bnx2_set_flags(struct net_device *dev, u32 data)
7537{
7d0fd211
JG		 7538 struct bnx2 *bp = netdev_priv(dev);
7539 int rc;
7540
7541 if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN) &&
7542 !(data & ETH_FLAG_RXVLAN))
ec37a48d 7543 return -EINVAL;
7d0fd211
JG		 7544
7545 rc = ethtool_op_set_flags(dev, data, ETH_FLAG_RXHASH | ETH_FLAG_RXVLAN |
7546 ETH_FLAG_TXVLAN);
7547 if (rc)
7548 return rc;
7549
7550 if ((!!(data & ETH_FLAG_RXVLAN) !=
7551 !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) &&
7552 netif_running(dev)) {
7553 bnx2_netif_stop(bp, false);
7554 bnx2_set_rx_mode(dev);
7555 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
7556 bnx2_netif_start(bp, false);
7557 }
7558
7559 return 0;
fdc8541d
MC		 7560}
7561
7282d491 7562static const struct ethtool_ops bnx2_ethtool_ops = {
b6016b76
MC		 7563 .get_settings = bnx2_get_settings,
7564 .set_settings = bnx2_set_settings,
7565 .get_drvinfo = bnx2_get_drvinfo,
244ac4f4
MC		 7566 .get_regs_len = bnx2_get_regs_len,
7567 .get_regs = bnx2_get_regs,
b6016b76
MC		 7568 .get_wol = bnx2_get_wol,
7569 .set_wol = bnx2_set_wol,
7570 .nway_reset = bnx2_nway_reset,
7959ea25 7571 .get_link = bnx2_get_link,
b6016b76
MC		 7572 .get_eeprom_len = bnx2_get_eeprom_len,
7573 .get_eeprom = bnx2_get_eeprom,
7574 .set_eeprom = bnx2_set_eeprom,
7575 .get_coalesce = bnx2_get_coalesce,
7576 .set_coalesce = bnx2_set_coalesce,
7577 .get_ringparam = bnx2_get_ringparam,
7578 .set_ringparam = bnx2_set_ringparam,
7579 .get_pauseparam = bnx2_get_pauseparam,
7580 .set_pauseparam = bnx2_set_pauseparam,
7581 .get_rx_csum = bnx2_get_rx_csum,
7582 .set_rx_csum = bnx2_set_rx_csum,
4666f87a 7583 .set_tx_csum = bnx2_set_tx_csum,
b6016b76 7584 .set_sg = ethtool_op_set_sg,
b11d6213 7585 .set_tso = bnx2_set_tso,
b6016b76
MC		 7586 .self_test = bnx2_self_test,
7587 .get_strings = bnx2_get_strings,
7588 .phys_id = bnx2_phys_id,
b6016b76 7589 .get_ethtool_stats = bnx2_get_ethtool_stats,
b9f2c044 7590 .get_sset_count = bnx2_get_sset_count,
fdc8541d
MC		 7591 .set_flags = bnx2_set_flags,
7592 .get_flags = ethtool_op_get_flags,
b6016b76
MC		 7593};
7594
7595/* Called with rtnl_lock */
7596static int
7597bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7598{
14ab9b86 7599 struct mii_ioctl_data *data = if_mii(ifr);
972ec0d4 7600 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7601 int err;
7602
7603 switch(cmd) {
7604 case SIOCGMIIPHY:
7605 data->phy_id = bp->phy_addr;
7606
7607 /* fallthru */
7608 case SIOCGMIIREG: {
7609 u32 mii_regval;
7610
583c28e5 7611 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 7612 return -EOPNOTSUPP;
7613
dad3e452
MC		 7614 if (!netif_running(dev))
7615 return -EAGAIN;
7616
c770a65c 7617 spin_lock_bh(&bp->phy_lock);
b6016b76 7618 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
c770a65c 7619 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7620
7621 data->val_out = mii_regval;
7622
7623 return err;
7624 }
7625
7626 case SIOCSMIIREG:
583c28e5 7627 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 7628 return -EOPNOTSUPP;
7629
dad3e452
MC		 7630 if (!netif_running(dev))
7631 return -EAGAIN;
7632
c770a65c 7633 spin_lock_bh(&bp->phy_lock);
b6016b76 7634 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
c770a65c 7635 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7636
7637 return err;
7638
7639 default:
7640 /* do nothing */
7641 break;
7642 }
7643 return -EOPNOTSUPP;
7644}
7645
7646/* Called with rtnl_lock */
7647static int
7648bnx2_change_mac_addr(struct net_device *dev, void *p)
7649{
7650 struct sockaddr *addr = p;
972ec0d4 7651 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7652
73eef4cd
MC		 7653 if (!is_valid_ether_addr(addr->sa_data))
7654 return -EINVAL;
7655
b6016b76
MC		 7656 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7657 if (netif_running(dev))
5fcaed01 7658 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 7659
7660 return 0;
7661}
7662
7663/* Called with rtnl_lock */
7664static int
7665bnx2_change_mtu(struct net_device *dev, int new_mtu)
7666{
972ec0d4 7667 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7668
7669 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7670 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7671 return -EINVAL;
7672
7673 dev->mtu = new_mtu;
807540ba 7674 return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size);
b6016b76
MC		 7675}
7676
257ddbda 7677#ifdef CONFIG_NET_POLL_CONTROLLER
b6016b76
MC		 7678static void
7679poll_bnx2(struct net_device *dev)
7680{
972ec0d4 7681 struct bnx2 *bp = netdev_priv(dev);
b2af2c1d 7682 int i;
b6016b76 7683
b2af2c1d 7684 for (i = 0; i < bp->irq_nvecs; i++) {
1bf1e347
MC		 7685 struct bnx2_irq *irq = &bp->irq_tbl[i];
7686
7687 disable_irq(irq->vector);
7688 irq->handler(irq->vector, &bp->bnx2_napi[i]);
7689 enable_irq(irq->vector);
b2af2c1d 7690 }
b6016b76
MC		 7691}
7692#endif
7693
253c8b75
MC		 7694static void __devinit
7695bnx2_get_5709_media(struct bnx2 *bp)
7696{
7697 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7698 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7699 u32 strap;
7700
7701 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7702 return;
7703 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
583c28e5 7704 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7705 return;
7706 }
7707
7708 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7709 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7710 else
7711 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7712
7713 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7714 switch (strap) {
7715 case 0x4:
7716 case 0x5:
7717 case 0x6:
583c28e5 7718 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7719 return;
7720 }
7721 } else {
7722 switch (strap) {
7723 case 0x1:
7724 case 0x2:
7725 case 0x4:
583c28e5 7726 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7727 return;
7728 }
7729 }
7730}
7731
883e5151
MC		 7732static void __devinit
7733bnx2_get_pci_speed(struct bnx2 *bp)
7734{
7735 u32 reg;
7736
7737 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7738 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7739 u32 clkreg;
7740
f86e82fb 7741 bp->flags |= BNX2_FLAG_PCIX;
883e5151
MC		 7742
7743 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7744
7745 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7746 switch (clkreg) {
7747 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7748 bp->bus_speed_mhz = 133;
7749 break;
7750
7751 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7752 bp->bus_speed_mhz = 100;
7753 break;
7754
7755 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7756 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7757 bp->bus_speed_mhz = 66;
7758 break;
7759
7760 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7761 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7762 bp->bus_speed_mhz = 50;
7763 break;
7764
7765 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7766 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7767 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7768 bp->bus_speed_mhz = 33;
7769 break;
7770 }
7771 }
7772 else {
7773 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7774 bp->bus_speed_mhz = 66;
7775 else
7776 bp->bus_speed_mhz = 33;
7777 }
7778
7779 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
f86e82fb 7780 bp->flags |= BNX2_FLAG_PCI_32BIT;
883e5151
MC		 7781
7782}
7783
76d99061
MC		 7784static void __devinit
7785bnx2_read_vpd_fw_ver(struct bnx2 *bp)
7786{
df25bc38 7787 int rc, i, j;
76d99061 7788 u8 *data;
df25bc38 7789 unsigned int block_end, rosize, len;
76d99061 7790
012093f6
MC		 7791#define BNX2_VPD_NVRAM_OFFSET 0x300
7792#define BNX2_VPD_LEN 128
76d99061
MC		 7793#define BNX2_MAX_VER_SLEN 30
7794
7795 data = kmalloc(256, GFP_KERNEL);
7796 if (!data)
7797 return;
7798
012093f6
MC		 7799 rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,
7800 BNX2_VPD_LEN);
76d99061
MC		 7801 if (rc)
7802 goto vpd_done;
7803
012093f6
MC		 7804 for (i = 0; i < BNX2_VPD_LEN; i += 4) {
7805 data[i] = data[i + BNX2_VPD_LEN + 3];
7806 data[i + 1] = data[i + BNX2_VPD_LEN + 2];
7807 data[i + 2] = data[i + BNX2_VPD_LEN + 1];
7808 data[i + 3] = data[i + BNX2_VPD_LEN];
76d99061
MC		 7809 }
7810
df25bc38
MC		 7811 i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA);
7812 if (i < 0)
7813 goto vpd_done;
76d99061 7814
df25bc38
MC		 7815 rosize = pci_vpd_lrdt_size(&data[i]);
7816 i += PCI_VPD_LRDT_TAG_SIZE;
7817 block_end = i + rosize;
76d99061 7818
df25bc38
MC		 7819 if (block_end > BNX2_VPD_LEN)
7820 goto vpd_done;
76d99061 7821
df25bc38
MC		 7822 j = pci_vpd_find_info_keyword(data, i, rosize,
7823 PCI_VPD_RO_KEYWORD_MFR_ID);
7824 if (j < 0)
7825 goto vpd_done;
76d99061 7826
df25bc38 7827 len = pci_vpd_info_field_size(&data[j]);
76d99061 7828
df25bc38
MC		 7829 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7830 if (j + len > block_end || len != 4 ||
7831 memcmp(&data[j], "1028", 4))
7832 goto vpd_done;
4067a854 7833
df25bc38
MC		 7834 j = pci_vpd_find_info_keyword(data, i, rosize,
7835 PCI_VPD_RO_KEYWORD_VENDOR0);
7836 if (j < 0)
7837 goto vpd_done;
4067a854 7838
df25bc38 7839 len = pci_vpd_info_field_size(&data[j]);
4067a854 7840
df25bc38
MC		 7841 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7842 if (j + len > block_end || len > BNX2_MAX_VER_SLEN)
76d99061 7843 goto vpd_done;
df25bc38
MC		 7844
7845 memcpy(bp->fw_version, &data[j], len);
7846 bp->fw_version[len] = ' ';
76d99061
MC		 7847
7848vpd_done:
7849 kfree(data);
7850}
7851
b6016b76
MC		 7852static int __devinit
7853bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7854{
7855 struct bnx2 *bp;
7856 unsigned long mem_len;
58fc2ea4 7857 int rc, i, j;
b6016b76 7858 u32 reg;
40453c83 7859 u64 dma_mask, persist_dma_mask;
cd709aa9 7860 int err;
b6016b76 7861
b6016b76 7862 SET_NETDEV_DEV(dev, &pdev->dev);
972ec0d4 7863 bp = netdev_priv(dev);
b6016b76
MC		 7864
7865 bp->flags = 0;
7866 bp->phy_flags = 0;
7867
354fcd77
MC		 7868 bp->temp_stats_blk =
7869 kzalloc(sizeof(struct statistics_block), GFP_KERNEL);
7870
7871 if (bp->temp_stats_blk == NULL) {
7872 rc = -ENOMEM;
7873 goto err_out;
7874 }
7875
b6016b76
MC		 7876 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7877 rc = pci_enable_device(pdev);
7878 if (rc) {
3a9c6a49 7879 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
b6016b76
MC		 7880 goto err_out;
7881 }
7882
7883 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9b91cf9d 7884 dev_err(&pdev->dev,
3a9c6a49 7885 "Cannot find PCI device base address, aborting\n");
b6016b76
MC		 7886 rc = -ENODEV;
7887 goto err_out_disable;
7888 }
7889
7890 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7891 if (rc) {
3a9c6a49 7892 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
b6016b76
MC		 7893 goto err_out_disable;
7894 }
7895
7896 pci_set_master(pdev);
7897
7898 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7899 if (bp->pm_cap == 0) {
9b91cf9d 7900 dev_err(&pdev->dev,
3a9c6a49 7901 "Cannot find power management capability, aborting\n");
b6016b76
MC		 7902 rc = -EIO;
7903 goto err_out_release;
7904 }
7905
b6016b76
MC		 7906 bp->dev = dev;
7907 bp->pdev = pdev;
7908
7909 spin_lock_init(&bp->phy_lock);
1b8227c4 7910 spin_lock_init(&bp->indirect_lock);
c5a88950
MC		 7911#ifdef BCM_CNIC
7912 mutex_init(&bp->cnic_lock);
7913#endif
c4028958 7914 INIT_WORK(&bp->reset_task, bnx2_reset_task);
b6016b76
MC		 7915
7916 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
4edd473f 7917 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1);
b6016b76
MC		 7918 dev->mem_end = dev->mem_start + mem_len;
7919 dev->irq = pdev->irq;
7920
7921 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7922
7923 if (!bp->regview) {
3a9c6a49 7924 dev_err(&pdev->dev, "Cannot map register space, aborting\n");
b6016b76
MC		 7925 rc = -ENOMEM;
7926 goto err_out_release;
7927 }
7928
be7ff1af
MC		 7929 bnx2_set_power_state(bp, PCI_D0);
7930
b6016b76
MC		 7931 /* Configure byte swap and enable write to the reg_window registers.
7932 * Rely on CPU to do target byte swapping on big endian systems
7933 * The chip's target access swapping will not swap all accesses
7934 */
be7ff1af
MC		 7935 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG,
7936 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7937 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
b6016b76
MC		 7938
7939 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7940
883e5151
MC		 7941 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7942 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7943 dev_err(&pdev->dev,
3a9c6a49 7944 "Cannot find PCIE capability, aborting\n");
883e5151
MC		 7945 rc = -EIO;
7946 goto err_out_unmap;
7947 }
f86e82fb 7948 bp->flags |= BNX2_FLAG_PCIE;
2dd201d7 7949 if (CHIP_REV(bp) == CHIP_REV_Ax)
f86e82fb 7950 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
c239f279
MC		 7951
7952 /* AER (Advanced Error Reporting) hooks */
7953 err = pci_enable_pcie_error_reporting(pdev);
7954 if (err) {
7955 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting "
7956 "failed 0x%x\n", err);
7957 /* non-fatal, continue */
7958 }
7959
883e5151 7960 } else {
59b47d8a
MC		 7961 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7962 if (bp->pcix_cap == 0) {
7963 dev_err(&pdev->dev,
3a9c6a49 7964 "Cannot find PCIX capability, aborting\n");
59b47d8a
MC		 7965 rc = -EIO;
7966 goto err_out_unmap;
7967 }
61d9e3fa 7968 bp->flags |= BNX2_FLAG_BROKEN_STATS;
59b47d8a
MC		 7969 }
7970
b4b36042
MC		 7971 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7972 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
f86e82fb 7973 bp->flags |= BNX2_FLAG_MSIX_CAP;
b4b36042
MC		 7974 }
7975
8e6a72c4
MC		 7976 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7977 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
f86e82fb 7978 bp->flags |= BNX2_FLAG_MSI_CAP;
8e6a72c4
MC		 7979 }
7980
40453c83
MC		 7981 /* 5708 cannot support DMA addresses > 40-bit. */
7982 if (CHIP_NUM(bp) == CHIP_NUM_5708)
50cf156a 7983 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
40453c83 7984 else
6a35528a 7985 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
40453c83
MC		 7986
7987 /* Configure DMA attributes. */
7988 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7989 dev->features |= NETIF_F_HIGHDMA;
7990 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7991 if (rc) {
7992 dev_err(&pdev->dev,
3a9c6a49 7993 "pci_set_consistent_dma_mask failed, aborting\n");
40453c83
MC		 7994 goto err_out_unmap;
7995 }
284901a9 7996 } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
3a9c6a49 7997 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
40453c83
MC		 7998 goto err_out_unmap;
7999 }
8000
f86e82fb 8001 if (!(bp->flags & BNX2_FLAG_PCIE))
883e5151 8002 bnx2_get_pci_speed(bp);
b6016b76
MC		 8003
8004 /* 5706A0 may falsely detect SERR and PERR. */
8005 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8006 reg = REG_RD(bp, PCI_COMMAND);
8007 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
8008 REG_WR(bp, PCI_COMMAND, reg);
8009 }
8010 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
f86e82fb 8011 !(bp->flags & BNX2_FLAG_PCIX)) {
b6016b76 8012
9b91cf9d 8013 dev_err(&pdev->dev,
3a9c6a49 8014 "5706 A1 can only be used in a PCIX bus, aborting\n");
b6016b76
MC		 8015 goto err_out_unmap;
8016 }
8017
8018 bnx2_init_nvram(bp);
8019
2726d6e1 8020 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
e3648b3d
MC		 8021
8022 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
24cb230b
MC		 8023 BNX2_SHM_HDR_SIGNATURE_SIG) {
8024 u32 off = PCI_FUNC(pdev->devfn) << 2;
8025
2726d6e1 8026 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
24cb230b 8027 } else
e3648b3d
MC		 8028 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
8029
b6016b76
MC		 8030 /* Get the permanent MAC address. First we need to make sure the
8031 * firmware is actually running.
8032 */
2726d6e1 8033 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
b6016b76
MC		 8034
8035 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
8036 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
3a9c6a49 8037 dev_err(&pdev->dev, "Firmware not running, aborting\n");
b6016b76
MC		 8038 rc = -ENODEV;
8039 goto err_out_unmap;
8040 }
8041
76d99061
MC		 8042 bnx2_read_vpd_fw_ver(bp);
8043
8044 j = strlen(bp->fw_version);
2726d6e1 8045 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
76d99061 8046 for (i = 0; i < 3 && j < 24; i++) {
58fc2ea4
MC		 8047 u8 num, k, skip0;
8048
76d99061
MC		 8049 if (i == 0) {
8050 bp->fw_version[j++] = 'b';
8051 bp->fw_version[j++] = 'c';
8052 bp->fw_version[j++] = ' ';
8053 }
58fc2ea4
MC		 8054 num = (u8) (reg >> (24 - (i * 8)));
8055 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
8056 if (num >= k || !skip0 || k == 1) {
8057 bp->fw_version[j++] = (num / k) + '0';
8058 skip0 = 0;
8059 }
8060 }
8061 if (i != 2)
8062 bp->fw_version[j++] = '.';
8063 }
2726d6e1 8064 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
846f5c62
MC		 8065 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
8066 bp->wol = 1;
8067
8068 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
f86e82fb 8069 bp->flags |= BNX2_FLAG_ASF_ENABLE;
c2d3db8c
MC		 8070
8071 for (i = 0; i < 30; i++) {
2726d6e1 8072 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
c2d3db8c
MC		 8073 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
8074 break;
8075 msleep(10);
8076 }
8077 }
2726d6e1 8078 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
58fc2ea4
MC		 8079 reg &= BNX2_CONDITION_MFW_RUN_MASK;
8080 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
8081 reg != BNX2_CONDITION_MFW_RUN_NONE) {
2726d6e1 8082 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
58fc2ea4 8083
76d99061
MC		 8084 if (j < 32)
8085 bp->fw_version[j++] = ' ';
8086 for (i = 0; i < 3 && j < 28; i++) {
2726d6e1 8087 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
58fc2ea4
MC		 8088 reg = swab32(reg);
8089 memcpy(&bp->fw_version[j], &reg, 4);
8090 j += 4;
8091 }
8092 }
b6016b76 8093
2726d6e1 8094 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
b6016b76
MC		 8095 bp->mac_addr[0] = (u8) (reg >> 8);
8096 bp->mac_addr[1] = (u8) reg;
8097
2726d6e1 8098 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
b6016b76
MC		 8099 bp->mac_addr[2] = (u8) (reg >> 24);
8100 bp->mac_addr[3] = (u8) (reg >> 16);
8101 bp->mac_addr[4] = (u8) (reg >> 8);
8102 bp->mac_addr[5] = (u8) reg;
8103
8104 bp->tx_ring_size = MAX_TX_DESC_CNT;
932f3772 8105 bnx2_set_rx_ring_size(bp, 255);
b6016b76
MC		 8106
8107 bp->rx_csum = 1;
8108
cf7474a6 8109 bp->tx_quick_cons_trip_int = 2;
b6016b76 8110 bp->tx_quick_cons_trip = 20;
cf7474a6 8111 bp->tx_ticks_int = 18;
b6016b76 8112 bp->tx_ticks = 80;
6aa20a22 8113
cf7474a6
MC		 8114 bp->rx_quick_cons_trip_int = 2;
8115 bp->rx_quick_cons_trip = 12;
b6016b76
MC		 8116 bp->rx_ticks_int = 18;
8117 bp->rx_ticks = 18;
8118
7ea6920e 8119 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76 8120
ac392abc 8121 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 8122
5b0c76ad
MC		 8123 bp->phy_addr = 1;
8124
b6016b76 8125 /* Disable WOL support if we are running on a SERDES chip. */
253c8b75
MC		 8126 if (CHIP_NUM(bp) == CHIP_NUM_5709)
8127 bnx2_get_5709_media(bp);
8128 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
583c28e5 8129 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
bac0dff6 8130
0d8a6571 8131 bp->phy_port = PORT_TP;
583c28e5 8132 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 8133 bp->phy_port = PORT_FIBRE;
2726d6e1 8134 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
846f5c62 8135 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
f86e82fb 8136 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 8137 bp->wol = 0;
8138 }
38ea3686
MC		 8139 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
8140 /* Don't do parallel detect on this board because of
8141 * some board problems. The link will not go down
8142 * if we do parallel detect.
8143 */
8144 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
8145 pdev->subsystem_device == 0x310c)
8146 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
8147 } else {
5b0c76ad 8148 bp->phy_addr = 2;
5b0c76ad 8149 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
583c28e5 8150 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
5b0c76ad 8151 }
261dd5ca
MC		 8152 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
8153 CHIP_NUM(bp) == CHIP_NUM_5708)
583c28e5 8154 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
fb0c18bd
MC		 8155 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
8156 (CHIP_REV(bp) == CHIP_REV_Ax ||
8157 CHIP_REV(bp) == CHIP_REV_Bx))
583c28e5 8158 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
b6016b76 8159
7c62e83b
MC		 8160 bnx2_init_fw_cap(bp);
8161
16088272
MC		 8162 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
8163 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
5ec6d7bf
MC		 8164 (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
8165 !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
f86e82fb 8166 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 8167 bp->wol = 0;
8168 }
dda1e390 8169
b6016b76
MC		 8170 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8171 bp->tx_quick_cons_trip_int =
8172 bp->tx_quick_cons_trip;
8173 bp->tx_ticks_int = bp->tx_ticks;
8174 bp->rx_quick_cons_trip_int =
8175 bp->rx_quick_cons_trip;
8176 bp->rx_ticks_int = bp->rx_ticks;
8177 bp->comp_prod_trip_int = bp->comp_prod_trip;
8178 bp->com_ticks_int = bp->com_ticks;
8179 bp->cmd_ticks_int = bp->cmd_ticks;
8180 }
8181
f9317a40
MC		 8182 /* Disable MSI on 5706 if AMD 8132 bridge is found.
8183 *
8184 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
8185 * with byte enables disabled on the unused 32-bit word. This is legal
8186 * but causes problems on the AMD 8132 which will eventually stop
8187 * responding after a while.
8188 *
8189 * AMD believes this incompatibility is unique to the 5706, and
88187dfa 8190 * prefers to locally disable MSI rather than globally disabling it.
f9317a40
MC		 8191 */
8192 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
8193 struct pci_dev *amd_8132 = NULL;
8194
8195 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
8196 PCI_DEVICE_ID_AMD_8132_BRIDGE,
8197 amd_8132))) {
f9317a40 8198
44c10138
AK		 8199 if (amd_8132->revision >= 0x10 &&
8200 amd_8132->revision <= 0x13) {
f9317a40
MC		 8201 disable_msi = 1;
8202 pci_dev_put(amd_8132);
8203 break;
8204 }
8205 }
8206 }
8207
deaf391b 8208 bnx2_set_default_link(bp);
b6016b76
MC		 8209 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8210
cd339a0e 8211 init_timer(&bp->timer);
ac392abc 8212 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
cd339a0e
MC		 8213 bp->timer.data = (unsigned long) bp;
8214 bp->timer.function = bnx2_timer;
8215
c239f279
MC		 8216 pci_save_state(pdev);
8217
b6016b76
MC		 8218 return 0;
8219
8220err_out_unmap:
c239f279
MC		 8221 if (bp->flags & BNX2_FLAG_PCIE)
8222 pci_disable_pcie_error_reporting(pdev);
8223
b6016b76
MC		 8224 if (bp->regview) {
8225 iounmap(bp->regview);
73eef4cd 8226 bp->regview = NULL;
b6016b76
MC		 8227 }
8228
8229err_out_release:
8230 pci_release_regions(pdev);
8231
8232err_out_disable:
8233 pci_disable_device(pdev);
8234 pci_set_drvdata(pdev, NULL);
8235
8236err_out:
8237 return rc;
8238}
8239
883e5151
MC		 8240static char * __devinit
8241bnx2_bus_string(struct bnx2 *bp, char *str)
8242{
8243 char *s = str;
8244
f86e82fb 8245 if (bp->flags & BNX2_FLAG_PCIE) {
883e5151
MC		 8246 s += sprintf(s, "PCI Express");
8247 } else {
8248 s += sprintf(s, "PCI");
f86e82fb 8249 if (bp->flags & BNX2_FLAG_PCIX)
883e5151 8250 s += sprintf(s, "-X");
f86e82fb 8251 if (bp->flags & BNX2_FLAG_PCI_32BIT)
883e5151
MC		 8252 s += sprintf(s, " 32-bit");
8253 else
8254 s += sprintf(s, " 64-bit");
8255 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8256 }
8257 return str;
8258}
8259
f048fa9c
MC		 8260static void
8261bnx2_del_napi(struct bnx2 *bp)
8262{
8263 int i;
8264
8265 for (i = 0; i < bp->irq_nvecs; i++)
8266 netif_napi_del(&bp->bnx2_napi[i].napi);
8267}
8268
8269static void
35efa7c1
MC		 8270bnx2_init_napi(struct bnx2 *bp)
8271{
b4b36042 8272 int i;
35efa7c1 8273
4327ba43 8274 for (i = 0; i < bp->irq_nvecs; i++) {
35e9010b
MC		 8275 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8276 int (*poll)(struct napi_struct *, int);
8277
8278 if (i == 0)
8279 poll = bnx2_poll;
8280 else
f0ea2e63 8281 poll = bnx2_poll_msix;
35e9010b
MC		 8282
8283 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
b4b36042
MC		 8284 bnapi->bp = bp;
8285 }
35efa7c1
MC		 8286}
8287
0421eae6
SH		 8288static const struct net_device_ops bnx2_netdev_ops = {
8289 .ndo_open = bnx2_open,
8290 .ndo_start_xmit = bnx2_start_xmit,
8291 .ndo_stop = bnx2_close,
5d07bf26 8292 .ndo_get_stats64 = bnx2_get_stats64,
0421eae6
SH		 8293 .ndo_set_rx_mode = bnx2_set_rx_mode,
8294 .ndo_do_ioctl = bnx2_ioctl,
8295 .ndo_validate_addr = eth_validate_addr,
8296 .ndo_set_mac_address = bnx2_change_mac_addr,
8297 .ndo_change_mtu = bnx2_change_mtu,
8298 .ndo_tx_timeout = bnx2_tx_timeout,
257ddbda 8299#ifdef CONFIG_NET_POLL_CONTROLLER
0421eae6
SH		 8300 .ndo_poll_controller = poll_bnx2,
8301#endif
8302};
8303
72dccb01
ED		 8304static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
8305{
72dccb01 8306 dev->vlan_features |= flags;
72dccb01
ED		 8307}
8308
b6016b76
MC		 8309static int __devinit
8310bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8311{
8312 static int version_printed = 0;
8313 struct net_device *dev = NULL;
8314 struct bnx2 *bp;
0795af57 8315 int rc;
883e5151 8316 char str[40];
b6016b76
MC		 8317
8318 if (version_printed++ == 0)
3a9c6a49 8319 pr_info("%s", version);
b6016b76
MC		 8320
8321 /* dev zeroed in init_etherdev */
706bf240 8322 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
b6016b76
MC		 8323
8324 if (!dev)
8325 return -ENOMEM;
8326
8327 rc = bnx2_init_board(pdev, dev);
8328 if (rc < 0) {
8329 free_netdev(dev);
8330 return rc;
8331 }
8332
0421eae6 8333 dev->netdev_ops = &bnx2_netdev_ops;
b6016b76 8334 dev->watchdog_timeo = TX_TIMEOUT;
b6016b76 8335 dev->ethtool_ops = &bnx2_ethtool_ops;
b6016b76 8336
972ec0d4 8337 bp = netdev_priv(dev);
b6016b76 8338
1b2f922f
MC		 8339 pci_set_drvdata(pdev, dev);
8340
57579f76
MC		 8341 rc = bnx2_request_firmware(bp);
8342 if (rc)
8343 goto error;
8344
1b2f922f
MC		 8345 memcpy(dev->dev_addr, bp->mac_addr, 6);
8346 memcpy(dev->perm_addr, bp->mac_addr, 6);
1b2f922f 8347
fdc8541d
MC		 8348 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO |
8349 NETIF_F_RXHASH;
72dccb01
ED		 8350 vlan_features_add(dev, NETIF_F_IP_CSUM | NETIF_F_SG);
8351 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
d212f87b 8352 dev->features |= NETIF_F_IPV6_CSUM;
72dccb01
ED		 8353 vlan_features_add(dev, NETIF_F_IPV6_CSUM);
8354 }
1b2f922f 8355 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1b2f922f 8356 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
72dccb01
ED		 8357 vlan_features_add(dev, NETIF_F_TSO | NETIF_F_TSO_ECN);
8358 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4666f87a 8359 dev->features |= NETIF_F_TSO6;
72dccb01
ED		 8360 vlan_features_add(dev, NETIF_F_TSO6);
8361 }
b6016b76 8362 if ((rc = register_netdev(dev))) {
9b91cf9d 8363 dev_err(&pdev->dev, "Cannot register net device\n");
57579f76 8364 goto error;
b6016b76
MC		 8365 }
8366
3a9c6a49
JP		 8367 netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, node addr %pM\n",
8368 board_info[ent->driver_data].name,
8369 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8370 ((CHIP_ID(bp) & 0x0ff0) >> 4),
8371 bnx2_bus_string(bp, str),
8372 dev->base_addr,
8373 bp->pdev->irq, dev->dev_addr);
b6016b76 8374
b6016b76 8375 return 0;
57579f76
MC		 8376
8377error:
8378 if (bp->mips_firmware)
8379 release_firmware(bp->mips_firmware);
8380 if (bp->rv2p_firmware)
8381 release_firmware(bp->rv2p_firmware);
8382
8383 if (bp->regview)
8384 iounmap(bp->regview);
8385 pci_release_regions(pdev);
8386 pci_disable_device(pdev);
8387 pci_set_drvdata(pdev, NULL);
8388 free_netdev(dev);
8389 return rc;
b6016b76
MC		 8390}
8391
8392static void __devexit
8393bnx2_remove_one(struct pci_dev *pdev)
8394{
8395 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8396 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 8397
8398 unregister_netdev(dev);
8399
57579f76
MC		 8400 if (bp->mips_firmware)
8401 release_firmware(bp->mips_firmware);
8402 if (bp->rv2p_firmware)
8403 release_firmware(bp->rv2p_firmware);
8404
b6016b76
MC		 8405 if (bp->regview)
8406 iounmap(bp->regview);
8407
354fcd77
MC		 8408 kfree(bp->temp_stats_blk);
8409
c239f279
MC		 8410 if (bp->flags & BNX2_FLAG_PCIE)
8411 pci_disable_pcie_error_reporting(pdev);
cd709aa9 8412
c239f279 8413 free_netdev(dev);
cd709aa9 8414
b6016b76
MC		 8415 pci_release_regions(pdev);
8416 pci_disable_device(pdev);
8417 pci_set_drvdata(pdev, NULL);
8418}
8419
8420static int
829ca9a3 8421bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
b6016b76
MC		 8422{
8423 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8424 struct bnx2 *bp = netdev_priv(dev);
b6016b76 8425
6caebb02
MC		 8426 /* PCI register 4 needs to be saved whether netif_running() or not.
8427 * MSI address and data need to be saved if using MSI and
8428 * netif_running().
8429 */
8430 pci_save_state(pdev);
b6016b76
MC		 8431 if (!netif_running(dev))
8432 return 0;
8433
23f333a2 8434 cancel_work_sync(&bp->reset_task);
212f9934 8435 bnx2_netif_stop(bp, true);
b6016b76
MC		 8436 netif_device_detach(dev);
8437 del_timer_sync(&bp->timer);
74bf4ba3 8438 bnx2_shutdown_chip(bp);
b6016b76 8439 bnx2_free_skbs(bp);
829ca9a3 8440 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
b6016b76
MC		 8441 return 0;
8442}
8443
8444static int
8445bnx2_resume(struct pci_dev *pdev)
8446{
8447 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8448 struct bnx2 *bp = netdev_priv(dev);
b6016b76 8449
6caebb02 8450 pci_restore_state(pdev);
b6016b76
MC		 8451 if (!netif_running(dev))
8452 return 0;
8453
829ca9a3 8454 bnx2_set_power_state(bp, PCI_D0);
b6016b76 8455 netif_device_attach(dev);
9a120bc5 8456 bnx2_init_nic(bp, 1);
212f9934 8457 bnx2_netif_start(bp, true);
b6016b76
MC		 8458 return 0;
8459}
8460
6ff2da49
WX		 8461/**
8462 * bnx2_io_error_detected - called when PCI error is detected
8463 * @pdev: Pointer to PCI device
8464 * @state: The current pci connection state
8465 *
8466 * This function is called after a PCI bus error affecting
8467 * this device has been detected.
8468 */
8469static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8470 pci_channel_state_t state)
8471{
8472 struct net_device *dev = pci_get_drvdata(pdev);
8473 struct bnx2 *bp = netdev_priv(dev);
8474
8475 rtnl_lock();
8476 netif_device_detach(dev);
8477
2ec3de26
DN		 8478 if (state == pci_channel_io_perm_failure) {
8479 rtnl_unlock();
8480 return PCI_ERS_RESULT_DISCONNECT;
8481 }
8482
6ff2da49 8483 if (netif_running(dev)) {
212f9934 8484 bnx2_netif_stop(bp, true);
6ff2da49
WX		 8485 del_timer_sync(&bp->timer);
8486 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8487 }
8488
8489 pci_disable_device(pdev);
8490 rtnl_unlock();
8491
8492 /* Request a slot slot reset. */
8493 return PCI_ERS_RESULT_NEED_RESET;
8494}
8495
8496/**
8497 * bnx2_io_slot_reset - called after the pci bus has been reset.
8498 * @pdev: Pointer to PCI device
8499 *
8500 * Restart the card from scratch, as if from a cold-boot.
8501 */
8502static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8503{
8504 struct net_device *dev = pci_get_drvdata(pdev);
8505 struct bnx2 *bp = netdev_priv(dev);
cd709aa9
JF		 8506 pci_ers_result_t result;
8507 int err;
6ff2da49
WX		 8508
8509 rtnl_lock();
8510 if (pci_enable_device(pdev)) {
8511 dev_err(&pdev->dev,
3a9c6a49 8512 "Cannot re-enable PCI device after reset\n");
cd709aa9
JF		 8513 result = PCI_ERS_RESULT_DISCONNECT;
8514 } else {
8515 pci_set_master(pdev);
8516 pci_restore_state(pdev);
8517 pci_save_state(pdev);
8518
8519 if (netif_running(dev)) {
8520 bnx2_set_power_state(bp, PCI_D0);
8521 bnx2_init_nic(bp, 1);
8522 }
8523 result = PCI_ERS_RESULT_RECOVERED;
6ff2da49 8524 }
cd709aa9 8525 rtnl_unlock();
6ff2da49 8526
c239f279
MC		 8527 if (!(bp->flags & BNX2_FLAG_PCIE))
8528 return result;
8529
cd709aa9
JF		 8530 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8531 if (err) {
8532 dev_err(&pdev->dev,
8533 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8534 err); /* non-fatal, continue */
6ff2da49
WX		 8535 }
8536
cd709aa9 8537 return result;
6ff2da49
WX		 8538}
8539
8540/**
8541 * bnx2_io_resume - called when traffic can start flowing again.
8542 * @pdev: Pointer to PCI device
8543 *
8544 * This callback is called when the error recovery driver tells us that
8545 * its OK to resume normal operation.
8546 */
8547static void bnx2_io_resume(struct pci_dev *pdev)
8548{
8549 struct net_device *dev = pci_get_drvdata(pdev);
8550 struct bnx2 *bp = netdev_priv(dev);
8551
8552 rtnl_lock();
8553 if (netif_running(dev))
212f9934 8554 bnx2_netif_start(bp, true);
6ff2da49
WX		 8555
8556 netif_device_attach(dev);
8557 rtnl_unlock();
8558}
8559
8560static struct pci_error_handlers bnx2_err_handler = {
8561 .error_detected = bnx2_io_error_detected,
8562 .slot_reset = bnx2_io_slot_reset,
8563 .resume = bnx2_io_resume,
8564};
8565
b6016b76 8566static struct pci_driver bnx2_pci_driver = {
14ab9b86
PH		 8567 .name = DRV_MODULE_NAME,
8568 .id_table = bnx2_pci_tbl,
8569 .probe = bnx2_init_one,
8570 .remove = __devexit_p(bnx2_remove_one),
8571 .suspend = bnx2_suspend,
8572 .resume = bnx2_resume,
6ff2da49 8573 .err_handler = &bnx2_err_handler,
b6016b76
MC		 8574};
8575
8576static int __init bnx2_init(void)
8577{
29917620 8578 return pci_register_driver(&bnx2_pci_driver);
b6016b76
MC		 8579}
8580
8581static void __exit bnx2_cleanup(void)
8582{
8583 pci_unregister_driver(&bnx2_pci_driver);
8584}
8585
8586module_init(bnx2_init);
8587module_exit(bnx2_cleanup);
8588
8589
8590
Linux kernel - Deliverables
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