projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: Cleanup of neighbour code
[deliverable/linux.git] / drivers / net / bnx2.c
CommitLineData
b6016b76
MC		 1/* bnx2.c: Broadcom NX2 network driver.
2 *
feebb331 3 * Copyright (c) 2004-2008 Broadcom Corporation
b6016b76
MC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
f2a4f052
MC		 12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15
16#include <linux/kernel.h>
17#include <linux/timer.h>
18#include <linux/errno.h>
19#include <linux/ioport.h>
20#include <linux/slab.h>
21#include <linux/vmalloc.h>
22#include <linux/interrupt.h>
23#include <linux/pci.h>
24#include <linux/init.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/dma-mapping.h>
1977f032 29#include <linux/bitops.h>
f2a4f052
MC		 30#include <asm/io.h>
31#include <asm/irq.h>
32#include <linux/delay.h>
33#include <asm/byteorder.h>
c86a31f4 34#include <asm/page.h>
f2a4f052
MC		 35#include <linux/time.h>
36#include <linux/ethtool.h>
37#include <linux/mii.h>
f2a4f052 38#include <linux/if_vlan.h>
08013fa3 39#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
f2a4f052
MC		 40#define BCM_VLAN 1
41#endif
f2a4f052 42#include <net/ip.h>
de081fa5 43#include <net/tcp.h>
f2a4f052 44#include <net/checksum.h>
f2a4f052
MC		 45#include <linux/workqueue.h>
46#include <linux/crc32.h>
47#include <linux/prefetch.h>
29b12174 48#include <linux/cache.h>
fba9fe91 49#include <linux/zlib.h>
706bf240 50#include <linux/log2.h>
f2a4f052 51
b6016b76
MC		 52#include "bnx2.h"
53#include "bnx2_fw.h"
d43584c8 54#include "bnx2_fw2.h"
b6016b76 55
110d0ef9 56#define FW_BUF_SIZE 0x10000
b3448b0b 57
b6016b76
MC		 58#define DRV_MODULE_NAME "bnx2"
59#define PFX DRV_MODULE_NAME ": "
ec7e6fab
MC		 60#define DRV_MODULE_VERSION "1.8.1"
61#define DRV_MODULE_RELDATE "Oct 7, 2008"
b6016b76
MC		 62
63#define RUN_AT(x) (jiffies + (x))
64
65/* Time in jiffies before concluding the transmitter is hung. */
66#define TX_TIMEOUT (5*HZ)
67
fefa8645 68static char version[] __devinitdata =
b6016b76
MC		 69 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
70
71MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
453a9c6e 72MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
b6016b76
MC		 73MODULE_LICENSE("GPL");
74MODULE_VERSION(DRV_MODULE_VERSION);
75
76static int disable_msi = 0;
77
78module_param(disable_msi, int, 0);
79MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
80
81typedef enum {
82 BCM5706 = 0,
83 NC370T,
84 NC370I,
85 BCM5706S,
86 NC370F,
5b0c76ad
MC		 87 BCM5708,
88 BCM5708S,
bac0dff6 89 BCM5709,
27a005b8 90 BCM5709S,
7bb0a04f 91 BCM5716,
b6016b76
MC		 92} board_t;
93
94/* indexed by board_t, above */
fefa8645 95static struct {
b6016b76
MC		 96 char *name;
97} board_info[] __devinitdata = {
98 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
99 { "HP NC370T Multifunction Gigabit Server Adapter" },
100 { "HP NC370i Multifunction Gigabit Server Adapter" },
101 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
102 { "HP NC370F Multifunction Gigabit Server Adapter" },
5b0c76ad
MC		 103 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
104 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
bac0dff6 105 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
27a005b8 106 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
7bb0a04f 107 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
b6016b76
MC		 108 };
109
7bb0a04f 110static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
b6016b76
MC		 111 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
112 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
113 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
114 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
115 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
5b0c76ad
MC		 117 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
b6016b76
MC		 119 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
120 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
121 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
5b0c76ad
MC		 123 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
bac0dff6
MC		 125 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
27a005b8
MC		 127 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
7bb0a04f
MC		 129 { PCI_VENDOR_ID_BROADCOM, 0x163b,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
b6016b76
MC		 131 { 0, }
132};
133
134static struct flash_spec flash_table[] =
135{
e30372c9
MC		 136#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
137#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
b6016b76 138 /* Slow EEPROM */
37137709 139 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 140 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
b6016b76
MC		 141 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
142 "EEPROM - slow"},
37137709
MC		 143 /* Expansion entry 0001 */
144 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 145 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 146 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
147 "Entry 0001"},
b6016b76
MC		 148 /* Saifun SA25F010 (non-buffered flash) */
149 /* strap, cfg1, & write1 need updates */
37137709 150 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 151 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 152 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
153 "Non-buffered flash (128kB)"},
154 /* Saifun SA25F020 (non-buffered flash) */
155 /* strap, cfg1, & write1 need updates */
37137709 156 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 157 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 158 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
159 "Non-buffered flash (256kB)"},
37137709
MC		 160 /* Expansion entry 0100 */
161 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 162 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 163 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
164 "Entry 0100"},
165 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
6aa20a22 166 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 167 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 168 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
169 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
170 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
171 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 172 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 173 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
174 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
175 /* Saifun SA25F005 (non-buffered flash) */
176 /* strap, cfg1, & write1 need updates */
177 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 178 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 179 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
180 "Non-buffered flash (64kB)"},
181 /* Fast EEPROM */
182 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 183 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
37137709
MC		 184 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
185 "EEPROM - fast"},
186 /* Expansion entry 1001 */
187 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 189 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
190 "Entry 1001"},
191 /* Expansion entry 1010 */
192 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 194 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
195 "Entry 1010"},
196 /* ATMEL AT45DB011B (buffered flash) */
197 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 198 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 199 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
200 "Buffered flash (128kB)"},
201 /* Expansion entry 1100 */
202 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205 "Entry 1100"},
206 /* Expansion entry 1101 */
207 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 208 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 209 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
210 "Entry 1101"},
211 /* Ateml Expansion entry 1110 */
212 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 214 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
215 "Entry 1110 (Atmel)"},
216 /* ATMEL AT45DB021B (buffered flash) */
217 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 218 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 219 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
220 "Buffered flash (256kB)"},
b6016b76
MC		 221};
222
e30372c9
MC		 223static struct flash_spec flash_5709 = {
224 .flags = BNX2_NV_BUFFERED,
225 .page_bits = BCM5709_FLASH_PAGE_BITS,
226 .page_size = BCM5709_FLASH_PAGE_SIZE,
227 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
228 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
229 .name = "5709 Buffered flash (256kB)",
230};
231
b6016b76
MC		 232MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
233
35e9010b 234static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
e89bbf10 235{
2f8af120 236 u32 diff;
e89bbf10 237
2f8af120 238 smp_mb();
faac9c4b
MC		 239
240 /* The ring uses 256 indices for 255 entries, one of them
241 * needs to be skipped.
242 */
35e9010b 243 diff = txr->tx_prod - txr->tx_cons;
faac9c4b
MC		 244 if (unlikely(diff >= TX_DESC_CNT)) {
245 diff &= 0xffff;
246 if (diff == TX_DESC_CNT)
247 diff = MAX_TX_DESC_CNT;
248 }
e89bbf10
MC		 249 return (bp->tx_ring_size - diff);
250}
251
b6016b76
MC		 252static u32
253bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
254{
1b8227c4
MC		 255 u32 val;
256
257 spin_lock_bh(&bp->indirect_lock);
b6016b76 258 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
1b8227c4
MC		 259 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
260 spin_unlock_bh(&bp->indirect_lock);
261 return val;
b6016b76
MC		 262}
263
264static void
265bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
266{
1b8227c4 267 spin_lock_bh(&bp->indirect_lock);
b6016b76
MC		 268 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
269 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
1b8227c4 270 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 271}
272
2726d6e1
MC		 273static void
274bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
275{
276 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
277}
278
279static u32
280bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
281{
282 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
283}
284
b6016b76
MC		 285static void
286bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
287{
288 offset += cid_addr;
1b8227c4 289 spin_lock_bh(&bp->indirect_lock);
59b47d8a
MC		 290 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
291 int i;
292
293 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
294 REG_WR(bp, BNX2_CTX_CTX_CTRL,
295 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
296 for (i = 0; i < 5; i++) {
59b47d8a
MC		 297 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
298 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
299 break;
300 udelay(5);
301 }
302 } else {
303 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
304 REG_WR(bp, BNX2_CTX_DATA, val);
305 }
1b8227c4 306 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 307}
308
309static int
310bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
311{
312 u32 val1;
313 int i, ret;
314
583c28e5 315 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 316 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
317 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
318
319 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
320 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
321
322 udelay(40);
323 }
324
325 val1 = (bp->phy_addr << 21) | (reg << 16) |
326 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
327 BNX2_EMAC_MDIO_COMM_START_BUSY;
328 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
329
330 for (i = 0; i < 50; i++) {
331 udelay(10);
332
333 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
334 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
335 udelay(5);
336
337 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
338 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
339
340 break;
341 }
342 }
343
344 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
345 *val = 0x0;
346 ret = -EBUSY;
347 }
348 else {
349 *val = val1;
350 ret = 0;
351 }
352
583c28e5 353 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 354 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
355 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
356
357 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
358 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
359
360 udelay(40);
361 }
362
363 return ret;
364}
365
366static int
367bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
368{
369 u32 val1;
370 int i, ret;
371
583c28e5 372 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 373 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
374 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
375
376 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
377 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
378
379 udelay(40);
380 }
381
382 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
383 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
384 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
385 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
6aa20a22 386
b6016b76
MC		 387 for (i = 0; i < 50; i++) {
388 udelay(10);
389
390 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
391 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
392 udelay(5);
393 break;
394 }
395 }
396
397 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
398 ret = -EBUSY;
399 else
400 ret = 0;
401
583c28e5 402 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 403 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
404 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
405
406 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
407 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
408
409 udelay(40);
410 }
411
412 return ret;
413}
414
415static void
416bnx2_disable_int(struct bnx2 *bp)
417{
b4b36042
MC		 418 int i;
419 struct bnx2_napi *bnapi;
420
421 for (i = 0; i < bp->irq_nvecs; i++) {
422 bnapi = &bp->bnx2_napi[i];
423 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
424 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
425 }
b6016b76
MC		 426 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
427}
428
429static void
430bnx2_enable_int(struct bnx2 *bp)
431{
b4b36042
MC		 432 int i;
433 struct bnx2_napi *bnapi;
35efa7c1 434
b4b36042
MC		 435 for (i = 0; i < bp->irq_nvecs; i++) {
436 bnapi = &bp->bnx2_napi[i];
1269a8a6 437
b4b36042
MC		 438 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
439 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
440 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
441 bnapi->last_status_idx);
b6016b76 442
b4b36042
MC		 443 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
444 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
445 bnapi->last_status_idx);
446 }
bf5295bb 447 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 448}
449
450static void
451bnx2_disable_int_sync(struct bnx2 *bp)
452{
b4b36042
MC		 453 int i;
454
b6016b76
MC		 455 atomic_inc(&bp->intr_sem);
456 bnx2_disable_int(bp);
b4b36042
MC		 457 for (i = 0; i < bp->irq_nvecs; i++)
458 synchronize_irq(bp->irq_tbl[i].vector);
b6016b76
MC		 459}
460
35efa7c1
MC		 461static void
462bnx2_napi_disable(struct bnx2 *bp)
463{
b4b36042
MC		 464 int i;
465
466 for (i = 0; i < bp->irq_nvecs; i++)
467 napi_disable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 468}
469
470static void
471bnx2_napi_enable(struct bnx2 *bp)
472{
b4b36042
MC		 473 int i;
474
475 for (i = 0; i < bp->irq_nvecs; i++)
476 napi_enable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 477}
478
b6016b76
MC		 479static void
480bnx2_netif_stop(struct bnx2 *bp)
481{
482 bnx2_disable_int_sync(bp);
483 if (netif_running(bp->dev)) {
35efa7c1 484 bnx2_napi_disable(bp);
b6016b76
MC		 485 netif_tx_disable(bp->dev);
486 bp->dev->trans_start = jiffies; /* prevent tx timeout */
487 }
488}
489
490static void
491bnx2_netif_start(struct bnx2 *bp)
492{
493 if (atomic_dec_and_test(&bp->intr_sem)) {
494 if (netif_running(bp->dev)) {
706bf240 495 netif_tx_wake_all_queues(bp->dev);
35efa7c1 496 bnx2_napi_enable(bp);
b6016b76
MC		 497 bnx2_enable_int(bp);
498 }
499 }
500}
501
35e9010b
MC		 502static void
503bnx2_free_tx_mem(struct bnx2 *bp)
504{
505 int i;
506
507 for (i = 0; i < bp->num_tx_rings; i++) {
508 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
509 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
510
511 if (txr->tx_desc_ring) {
512 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
513 txr->tx_desc_ring,
514 txr->tx_desc_mapping);
515 txr->tx_desc_ring = NULL;
516 }
517 kfree(txr->tx_buf_ring);
518 txr->tx_buf_ring = NULL;
519 }
520}
521
bb4f98ab
MC		 522static void
523bnx2_free_rx_mem(struct bnx2 *bp)
524{
525 int i;
526
527 for (i = 0; i < bp->num_rx_rings; i++) {
528 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
529 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
530 int j;
531
532 for (j = 0; j < bp->rx_max_ring; j++) {
533 if (rxr->rx_desc_ring[j])
534 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
535 rxr->rx_desc_ring[j],
536 rxr->rx_desc_mapping[j]);
537 rxr->rx_desc_ring[j] = NULL;
538 }
539 if (rxr->rx_buf_ring)
540 vfree(rxr->rx_buf_ring);
541 rxr->rx_buf_ring = NULL;
542
543 for (j = 0; j < bp->rx_max_pg_ring; j++) {
544 if (rxr->rx_pg_desc_ring[j])
545 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
546 rxr->rx_pg_desc_ring[i],
547 rxr->rx_pg_desc_mapping[i]);
548 rxr->rx_pg_desc_ring[i] = NULL;
549 }
550 if (rxr->rx_pg_ring)
551 vfree(rxr->rx_pg_ring);
552 rxr->rx_pg_ring = NULL;
553 }
554}
555
35e9010b
MC		 556static int
557bnx2_alloc_tx_mem(struct bnx2 *bp)
558{
559 int i;
560
561 for (i = 0; i < bp->num_tx_rings; i++) {
562 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
563 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
564
565 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
566 if (txr->tx_buf_ring == NULL)
567 return -ENOMEM;
568
569 txr->tx_desc_ring =
570 pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
571 &txr->tx_desc_mapping);
572 if (txr->tx_desc_ring == NULL)
573 return -ENOMEM;
574 }
575 return 0;
576}
577
bb4f98ab
MC		 578static int
579bnx2_alloc_rx_mem(struct bnx2 *bp)
580{
581 int i;
582
583 for (i = 0; i < bp->num_rx_rings; i++) {
584 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
585 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
586 int j;
587
588 rxr->rx_buf_ring =
589 vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
590 if (rxr->rx_buf_ring == NULL)
591 return -ENOMEM;
592
593 memset(rxr->rx_buf_ring, 0,
594 SW_RXBD_RING_SIZE * bp->rx_max_ring);
595
596 for (j = 0; j < bp->rx_max_ring; j++) {
597 rxr->rx_desc_ring[j] =
598 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
599 &rxr->rx_desc_mapping[j]);
600 if (rxr->rx_desc_ring[j] == NULL)
601 return -ENOMEM;
602
603 }
604
605 if (bp->rx_pg_ring_size) {
606 rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
607 bp->rx_max_pg_ring);
608 if (rxr->rx_pg_ring == NULL)
609 return -ENOMEM;
610
611 memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
612 bp->rx_max_pg_ring);
613 }
614
615 for (j = 0; j < bp->rx_max_pg_ring; j++) {
616 rxr->rx_pg_desc_ring[j] =
617 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
618 &rxr->rx_pg_desc_mapping[j]);
619 if (rxr->rx_pg_desc_ring[j] == NULL)
620 return -ENOMEM;
621
622 }
623 }
624 return 0;
625}
626
b6016b76
MC		 627static void
628bnx2_free_mem(struct bnx2 *bp)
629{
13daffa2 630 int i;
43e80b89 631 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
13daffa2 632
35e9010b 633 bnx2_free_tx_mem(bp);
bb4f98ab 634 bnx2_free_rx_mem(bp);
35e9010b 635
59b47d8a
MC		 636 for (i = 0; i < bp->ctx_pages; i++) {
637 if (bp->ctx_blk[i]) {
638 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
639 bp->ctx_blk[i],
640 bp->ctx_blk_mapping[i]);
641 bp->ctx_blk[i] = NULL;
642 }
643 }
43e80b89 644 if (bnapi->status_blk.msi) {
0f31f994 645 pci_free_consistent(bp->pdev, bp->status_stats_size,
43e80b89
MC		 646 bnapi->status_blk.msi,
647 bp->status_blk_mapping);
648 bnapi->status_blk.msi = NULL;
0f31f994 649 bp->stats_blk = NULL;
b6016b76 650 }
b6016b76
MC		 651}
652
653static int
654bnx2_alloc_mem(struct bnx2 *bp)
655{
35e9010b 656 int i, status_blk_size, err;
43e80b89
MC		 657 struct bnx2_napi *bnapi;
658 void *status_blk;
b6016b76 659
0f31f994
MC		 660 /* Combine status and statistics blocks into one allocation. */
661 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
f86e82fb 662 if (bp->flags & BNX2_FLAG_MSIX_CAP)
b4b36042
MC		 663 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
664 BNX2_SBLK_MSIX_ALIGN_SIZE);
0f31f994
MC		 665 bp->status_stats_size = status_blk_size +
666 sizeof(struct statistics_block);
667
43e80b89
MC		 668 status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
669 &bp->status_blk_mapping);
670 if (status_blk == NULL)
b6016b76
MC		 671 goto alloc_mem_err;
672
43e80b89 673 memset(status_blk, 0, bp->status_stats_size);
b6016b76 674
43e80b89
MC		 675 bnapi = &bp->bnx2_napi[0];
676 bnapi->status_blk.msi = status_blk;
677 bnapi->hw_tx_cons_ptr =
678 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
679 bnapi->hw_rx_cons_ptr =
680 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
f86e82fb 681 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
b4b36042 682 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
43e80b89
MC		 683 struct status_block_msix *sblk;
684
685 bnapi = &bp->bnx2_napi[i];
b4b36042 686
43e80b89
MC		 687 sblk = (void *) (status_blk +
688 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
689 bnapi->status_blk.msix = sblk;
690 bnapi->hw_tx_cons_ptr =
691 &sblk->status_tx_quick_consumer_index;
692 bnapi->hw_rx_cons_ptr =
693 &sblk->status_rx_quick_consumer_index;
b4b36042
MC		 694 bnapi->int_num = i << 24;
695 }
696 }
35efa7c1 697
43e80b89 698 bp->stats_blk = status_blk + status_blk_size;
b6016b76 699
0f31f994 700 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
b6016b76 701
59b47d8a
MC		 702 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
703 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
704 if (bp->ctx_pages == 0)
705 bp->ctx_pages = 1;
706 for (i = 0; i < bp->ctx_pages; i++) {
707 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
708 BCM_PAGE_SIZE,
709 &bp->ctx_blk_mapping[i]);
710 if (bp->ctx_blk[i] == NULL)
711 goto alloc_mem_err;
712 }
713 }
35e9010b 714
bb4f98ab
MC		 715 err = bnx2_alloc_rx_mem(bp);
716 if (err)
717 goto alloc_mem_err;
718
35e9010b
MC		 719 err = bnx2_alloc_tx_mem(bp);
720 if (err)
721 goto alloc_mem_err;
722
b6016b76
MC		 723 return 0;
724
725alloc_mem_err:
726 bnx2_free_mem(bp);
727 return -ENOMEM;
728}
729
e3648b3d
MC		 730static void
731bnx2_report_fw_link(struct bnx2 *bp)
732{
733 u32 fw_link_status = 0;
734
583c28e5 735 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 736 return;
737
e3648b3d
MC		 738 if (bp->link_up) {
739 u32 bmsr;
740
741 switch (bp->line_speed) {
742 case SPEED_10:
743 if (bp->duplex == DUPLEX_HALF)
744 fw_link_status = BNX2_LINK_STATUS_10HALF;
745 else
746 fw_link_status = BNX2_LINK_STATUS_10FULL;
747 break;
748 case SPEED_100:
749 if (bp->duplex == DUPLEX_HALF)
750 fw_link_status = BNX2_LINK_STATUS_100HALF;
751 else
752 fw_link_status = BNX2_LINK_STATUS_100FULL;
753 break;
754 case SPEED_1000:
755 if (bp->duplex == DUPLEX_HALF)
756 fw_link_status = BNX2_LINK_STATUS_1000HALF;
757 else
758 fw_link_status = BNX2_LINK_STATUS_1000FULL;
759 break;
760 case SPEED_2500:
761 if (bp->duplex == DUPLEX_HALF)
762 fw_link_status = BNX2_LINK_STATUS_2500HALF;
763 else
764 fw_link_status = BNX2_LINK_STATUS_2500FULL;
765 break;
766 }
767
768 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
769
770 if (bp->autoneg) {
771 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
772
ca58c3af
MC		 773 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
774 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
e3648b3d
MC		 775
776 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
583c28e5 777 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
e3648b3d
MC		 778 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
779 else
780 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
781 }
782 }
783 else
784 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
785
2726d6e1 786 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
e3648b3d
MC		 787}
788
9b1084b8
MC		 789static char *
790bnx2_xceiver_str(struct bnx2 *bp)
791{
792 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
583c28e5 793 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
9b1084b8
MC		 794 "Copper"));
795}
796
b6016b76
MC		 797static void
798bnx2_report_link(struct bnx2 *bp)
799{
800 if (bp->link_up) {
801 netif_carrier_on(bp->dev);
9b1084b8
MC		 802 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
803 bnx2_xceiver_str(bp));
b6016b76
MC		 804
805 printk("%d Mbps ", bp->line_speed);
806
807 if (bp->duplex == DUPLEX_FULL)
808 printk("full duplex");
809 else
810 printk("half duplex");
811
812 if (bp->flow_ctrl) {
813 if (bp->flow_ctrl & FLOW_CTRL_RX) {
814 printk(", receive ");
815 if (bp->flow_ctrl & FLOW_CTRL_TX)
816 printk("& transmit ");
817 }
818 else {
819 printk(", transmit ");
820 }
821 printk("flow control ON");
822 }
823 printk("\n");
824 }
825 else {
826 netif_carrier_off(bp->dev);
9b1084b8
MC		 827 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
828 bnx2_xceiver_str(bp));
b6016b76 829 }
e3648b3d
MC		 830
831 bnx2_report_fw_link(bp);
b6016b76
MC		 832}
833
834static void
835bnx2_resolve_flow_ctrl(struct bnx2 *bp)
836{
837 u32 local_adv, remote_adv;
838
839 bp->flow_ctrl = 0;
6aa20a22 840 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
b6016b76
MC		 841 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
842
843 if (bp->duplex == DUPLEX_FULL) {
844 bp->flow_ctrl = bp->req_flow_ctrl;
845 }
846 return;
847 }
848
849 if (bp->duplex != DUPLEX_FULL) {
850 return;
851 }
852
583c28e5 853 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
5b0c76ad
MC		 854 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
855 u32 val;
856
857 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
858 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
859 bp->flow_ctrl |= FLOW_CTRL_TX;
860 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
861 bp->flow_ctrl |= FLOW_CTRL_RX;
862 return;
863 }
864
ca58c3af
MC		 865 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
866 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76 867
583c28e5 868 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 869 u32 new_local_adv = 0;
870 u32 new_remote_adv = 0;
871
872 if (local_adv & ADVERTISE_1000XPAUSE)
873 new_local_adv |= ADVERTISE_PAUSE_CAP;
874 if (local_adv & ADVERTISE_1000XPSE_ASYM)
875 new_local_adv |= ADVERTISE_PAUSE_ASYM;
876 if (remote_adv & ADVERTISE_1000XPAUSE)
877 new_remote_adv |= ADVERTISE_PAUSE_CAP;
878 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
879 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
880
881 local_adv = new_local_adv;
882 remote_adv = new_remote_adv;
883 }
884
885 /* See Table 28B-3 of 802.3ab-1999 spec. */
886 if (local_adv & ADVERTISE_PAUSE_CAP) {
887 if(local_adv & ADVERTISE_PAUSE_ASYM) {
888 if (remote_adv & ADVERTISE_PAUSE_CAP) {
889 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
890 }
891 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
892 bp->flow_ctrl = FLOW_CTRL_RX;
893 }
894 }
895 else {
896 if (remote_adv & ADVERTISE_PAUSE_CAP) {
897 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
898 }
899 }
900 }
901 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
902 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
903 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
904
905 bp->flow_ctrl = FLOW_CTRL_TX;
906 }
907 }
908}
909
27a005b8
MC		 910static int
911bnx2_5709s_linkup(struct bnx2 *bp)
912{
913 u32 val, speed;
914
915 bp->link_up = 1;
916
917 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
918 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
919 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
920
921 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
922 bp->line_speed = bp->req_line_speed;
923 bp->duplex = bp->req_duplex;
924 return 0;
925 }
926 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
927 switch (speed) {
928 case MII_BNX2_GP_TOP_AN_SPEED_10:
929 bp->line_speed = SPEED_10;
930 break;
931 case MII_BNX2_GP_TOP_AN_SPEED_100:
932 bp->line_speed = SPEED_100;
933 break;
934 case MII_BNX2_GP_TOP_AN_SPEED_1G:
935 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
936 bp->line_speed = SPEED_1000;
937 break;
938 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
939 bp->line_speed = SPEED_2500;
940 break;
941 }
942 if (val & MII_BNX2_GP_TOP_AN_FD)
943 bp->duplex = DUPLEX_FULL;
944 else
945 bp->duplex = DUPLEX_HALF;
946 return 0;
947}
948
b6016b76 949static int
5b0c76ad
MC		 950bnx2_5708s_linkup(struct bnx2 *bp)
951{
952 u32 val;
953
954 bp->link_up = 1;
955 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
956 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
957 case BCM5708S_1000X_STAT1_SPEED_10:
958 bp->line_speed = SPEED_10;
959 break;
960 case BCM5708S_1000X_STAT1_SPEED_100:
961 bp->line_speed = SPEED_100;
962 break;
963 case BCM5708S_1000X_STAT1_SPEED_1G:
964 bp->line_speed = SPEED_1000;
965 break;
966 case BCM5708S_1000X_STAT1_SPEED_2G5:
967 bp->line_speed = SPEED_2500;
968 break;
969 }
970 if (val & BCM5708S_1000X_STAT1_FD)
971 bp->duplex = DUPLEX_FULL;
972 else
973 bp->duplex = DUPLEX_HALF;
974
975 return 0;
976}
977
978static int
979bnx2_5706s_linkup(struct bnx2 *bp)
b6016b76
MC		 980{
981 u32 bmcr, local_adv, remote_adv, common;
982
983 bp->link_up = 1;
984 bp->line_speed = SPEED_1000;
985
ca58c3af 986 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 987 if (bmcr & BMCR_FULLDPLX) {
988 bp->duplex = DUPLEX_FULL;
989 }
990 else {
991 bp->duplex = DUPLEX_HALF;
992 }
993
994 if (!(bmcr & BMCR_ANENABLE)) {
995 return 0;
996 }
997
ca58c3af
MC		 998 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
999 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 1000
1001 common = local_adv & remote_adv;
1002 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1003
1004 if (common & ADVERTISE_1000XFULL) {
1005 bp->duplex = DUPLEX_FULL;
1006 }
1007 else {
1008 bp->duplex = DUPLEX_HALF;
1009 }
1010 }
1011
1012 return 0;
1013}
1014
1015static int
1016bnx2_copper_linkup(struct bnx2 *bp)
1017{
1018 u32 bmcr;
1019
ca58c3af 1020 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1021 if (bmcr & BMCR_ANENABLE) {
1022 u32 local_adv, remote_adv, common;
1023
1024 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1025 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1026
1027 common = local_adv & (remote_adv >> 2);
1028 if (common & ADVERTISE_1000FULL) {
1029 bp->line_speed = SPEED_1000;
1030 bp->duplex = DUPLEX_FULL;
1031 }
1032 else if (common & ADVERTISE_1000HALF) {
1033 bp->line_speed = SPEED_1000;
1034 bp->duplex = DUPLEX_HALF;
1035 }
1036 else {
ca58c3af
MC		 1037 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1038 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 1039
1040 common = local_adv & remote_adv;
1041 if (common & ADVERTISE_100FULL) {
1042 bp->line_speed = SPEED_100;
1043 bp->duplex = DUPLEX_FULL;
1044 }
1045 else if (common & ADVERTISE_100HALF) {
1046 bp->line_speed = SPEED_100;
1047 bp->duplex = DUPLEX_HALF;
1048 }
1049 else if (common & ADVERTISE_10FULL) {
1050 bp->line_speed = SPEED_10;
1051 bp->duplex = DUPLEX_FULL;
1052 }
1053 else if (common & ADVERTISE_10HALF) {
1054 bp->line_speed = SPEED_10;
1055 bp->duplex = DUPLEX_HALF;
1056 }
1057 else {
1058 bp->line_speed = 0;
1059 bp->link_up = 0;
1060 }
1061 }
1062 }
1063 else {
1064 if (bmcr & BMCR_SPEED100) {
1065 bp->line_speed = SPEED_100;
1066 }
1067 else {
1068 bp->line_speed = SPEED_10;
1069 }
1070 if (bmcr & BMCR_FULLDPLX) {
1071 bp->duplex = DUPLEX_FULL;
1072 }
1073 else {
1074 bp->duplex = DUPLEX_HALF;
1075 }
1076 }
1077
1078 return 0;
1079}
1080
83e3fc89 1081static void
bb4f98ab 1082bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
83e3fc89 1083{
bb4f98ab 1084 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
83e3fc89
MC		 1085
1086 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1087 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1088 val |= 0x02 << 8;
1089
1090 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1091 u32 lo_water, hi_water;
1092
1093 if (bp->flow_ctrl & FLOW_CTRL_TX)
1094 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1095 else
1096 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1097 if (lo_water >= bp->rx_ring_size)
1098 lo_water = 0;
1099
1100 hi_water = bp->rx_ring_size / 4;
1101
1102 if (hi_water <= lo_water)
1103 lo_water = 0;
1104
1105 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1106 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1107
1108 if (hi_water > 0xf)
1109 hi_water = 0xf;
1110 else if (hi_water == 0)
1111 lo_water = 0;
1112 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1113 }
1114 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1115}
1116
bb4f98ab
MC		 1117static void
1118bnx2_init_all_rx_contexts(struct bnx2 *bp)
1119{
1120 int i;
1121 u32 cid;
1122
1123 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1124 if (i == 1)
1125 cid = RX_RSS_CID;
1126 bnx2_init_rx_context(bp, cid);
1127 }
1128}
1129
344478db 1130static void
b6016b76
MC		 1131bnx2_set_mac_link(struct bnx2 *bp)
1132{
1133 u32 val;
1134
1135 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1136 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1137 (bp->duplex == DUPLEX_HALF)) {
1138 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1139 }
1140
1141 /* Configure the EMAC mode register. */
1142 val = REG_RD(bp, BNX2_EMAC_MODE);
1143
1144 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
5b0c76ad 1145 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 1146 BNX2_EMAC_MODE_25G_MODE);
b6016b76
MC		 1147
1148 if (bp->link_up) {
5b0c76ad
MC		 1149 switch (bp->line_speed) {
1150 case SPEED_10:
59b47d8a
MC		 1151 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1152 val |= BNX2_EMAC_MODE_PORT_MII_10M;
5b0c76ad
MC		 1153 break;
1154 }
1155 /* fall through */
1156 case SPEED_100:
1157 val |= BNX2_EMAC_MODE_PORT_MII;
1158 break;
1159 case SPEED_2500:
59b47d8a 1160 val |= BNX2_EMAC_MODE_25G_MODE;
5b0c76ad
MC		 1161 /* fall through */
1162 case SPEED_1000:
1163 val |= BNX2_EMAC_MODE_PORT_GMII;
1164 break;
1165 }
b6016b76
MC		 1166 }
1167 else {
1168 val |= BNX2_EMAC_MODE_PORT_GMII;
1169 }
1170
1171 /* Set the MAC to operate in the appropriate duplex mode. */
1172 if (bp->duplex == DUPLEX_HALF)
1173 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1174 REG_WR(bp, BNX2_EMAC_MODE, val);
1175
1176 /* Enable/disable rx PAUSE. */
1177 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1178
1179 if (bp->flow_ctrl & FLOW_CTRL_RX)
1180 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1181 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1182
1183 /* Enable/disable tx PAUSE. */
1184 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1185 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1186
1187 if (bp->flow_ctrl & FLOW_CTRL_TX)
1188 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1189 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1190
1191 /* Acknowledge the interrupt. */
1192 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1193
83e3fc89 1194 if (CHIP_NUM(bp) == CHIP_NUM_5709)
bb4f98ab 1195 bnx2_init_all_rx_contexts(bp);
b6016b76
MC		 1196}
1197
27a005b8
MC		 1198static void
1199bnx2_enable_bmsr1(struct bnx2 *bp)
1200{
583c28e5 1201 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1202 (CHIP_NUM(bp) == CHIP_NUM_5709))
1203 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1204 MII_BNX2_BLK_ADDR_GP_STATUS);
1205}
1206
1207static void
1208bnx2_disable_bmsr1(struct bnx2 *bp)
1209{
583c28e5 1210 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1211 (CHIP_NUM(bp) == CHIP_NUM_5709))
1212 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1213 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1214}
1215
605a9e20
MC		 1216static int
1217bnx2_test_and_enable_2g5(struct bnx2 *bp)
1218{
1219 u32 up1;
1220 int ret = 1;
1221
583c28e5 1222 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1223 return 0;
1224
1225 if (bp->autoneg & AUTONEG_SPEED)
1226 bp->advertising |= ADVERTISED_2500baseX_Full;
1227
27a005b8
MC		 1228 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1229 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1230
605a9e20
MC		 1231 bnx2_read_phy(bp, bp->mii_up1, &up1);
1232 if (!(up1 & BCM5708S_UP1_2G5)) {
1233 up1 |= BCM5708S_UP1_2G5;
1234 bnx2_write_phy(bp, bp->mii_up1, up1);
1235 ret = 0;
1236 }
1237
27a005b8
MC		 1238 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1239 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1240 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1241
605a9e20
MC		 1242 return ret;
1243}
1244
1245static int
1246bnx2_test_and_disable_2g5(struct bnx2 *bp)
1247{
1248 u32 up1;
1249 int ret = 0;
1250
583c28e5 1251 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1252 return 0;
1253
27a005b8
MC		 1254 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1255 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1256
605a9e20
MC		 1257 bnx2_read_phy(bp, bp->mii_up1, &up1);
1258 if (up1 & BCM5708S_UP1_2G5) {
1259 up1 &= ~BCM5708S_UP1_2G5;
1260 bnx2_write_phy(bp, bp->mii_up1, up1);
1261 ret = 1;
1262 }
1263
27a005b8
MC		 1264 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1265 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1266 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1267
605a9e20
MC		 1268 return ret;
1269}
1270
1271static void
1272bnx2_enable_forced_2g5(struct bnx2 *bp)
1273{
1274 u32 bmcr;
1275
583c28e5 1276 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1277 return;
1278
27a005b8
MC		 1279 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1280 u32 val;
1281
1282 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1283 MII_BNX2_BLK_ADDR_SERDES_DIG);
1284 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1285 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1286 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1287 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1288
1289 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1290 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1291 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1292
1293 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1294 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1295 bmcr |= BCM5708S_BMCR_FORCE_2500;
1296 }
1297
1298 if (bp->autoneg & AUTONEG_SPEED) {
1299 bmcr &= ~BMCR_ANENABLE;
1300 if (bp->req_duplex == DUPLEX_FULL)
1301 bmcr |= BMCR_FULLDPLX;
1302 }
1303 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1304}
1305
1306static void
1307bnx2_disable_forced_2g5(struct bnx2 *bp)
1308{
1309 u32 bmcr;
1310
583c28e5 1311 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1312 return;
1313
27a005b8
MC		 1314 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1315 u32 val;
1316
1317 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1318 MII_BNX2_BLK_ADDR_SERDES_DIG);
1319 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1320 val &= ~MII_BNX2_SD_MISC1_FORCE;
1321 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1322
1323 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1324 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1325 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1326
1327 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1328 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1329 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1330 }
1331
1332 if (bp->autoneg & AUTONEG_SPEED)
1333 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1334 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1335}
1336
b2fadeae
MC		 1337static void
1338bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1339{
1340 u32 val;
1341
1342 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1343 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1344 if (start)
1345 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1346 else
1347 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1348}
1349
b6016b76
MC		 1350static int
1351bnx2_set_link(struct bnx2 *bp)
1352{
1353 u32 bmsr;
1354 u8 link_up;
1355
80be4434 1356 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
b6016b76
MC		 1357 bp->link_up = 1;
1358 return 0;
1359 }
1360
583c28e5 1361 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1362 return 0;
1363
b6016b76
MC		 1364 link_up = bp->link_up;
1365
27a005b8
MC		 1366 bnx2_enable_bmsr1(bp);
1367 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1368 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1369 bnx2_disable_bmsr1(bp);
b6016b76 1370
583c28e5 1371 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
b6016b76 1372 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
a2724e25 1373 u32 val, an_dbg;
b6016b76 1374
583c28e5 1375 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
b2fadeae 1376 bnx2_5706s_force_link_dn(bp, 0);
583c28e5 1377 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
b2fadeae 1378 }
b6016b76 1379 val = REG_RD(bp, BNX2_EMAC_STATUS);
a2724e25
MC		 1380
1381 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1382 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1383 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1384
1385 if ((val & BNX2_EMAC_STATUS_LINK) &&
1386 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
b6016b76
MC		 1387 bmsr |= BMSR_LSTATUS;
1388 else
1389 bmsr &= ~BMSR_LSTATUS;
1390 }
1391
1392 if (bmsr & BMSR_LSTATUS) {
1393 bp->link_up = 1;
1394
583c28e5 1395 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad
MC		 1396 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1397 bnx2_5706s_linkup(bp);
1398 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1399 bnx2_5708s_linkup(bp);
27a005b8
MC		 1400 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1401 bnx2_5709s_linkup(bp);
b6016b76
MC		 1402 }
1403 else {
1404 bnx2_copper_linkup(bp);
1405 }
1406 bnx2_resolve_flow_ctrl(bp);
1407 }
1408 else {
583c28e5 1409 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
605a9e20
MC		 1410 (bp->autoneg & AUTONEG_SPEED))
1411 bnx2_disable_forced_2g5(bp);
b6016b76 1412
583c28e5 1413 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
b2fadeae
MC		 1414 u32 bmcr;
1415
1416 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1417 bmcr |= BMCR_ANENABLE;
1418 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1419
583c28e5 1420 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b2fadeae 1421 }
b6016b76
MC		 1422 bp->link_up = 0;
1423 }
1424
1425 if (bp->link_up != link_up) {
1426 bnx2_report_link(bp);
1427 }
1428
1429 bnx2_set_mac_link(bp);
1430
1431 return 0;
1432}
1433
1434static int
1435bnx2_reset_phy(struct bnx2 *bp)
1436{
1437 int i;
1438 u32 reg;
1439
ca58c3af 1440 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
b6016b76
MC		 1441
1442#define PHY_RESET_MAX_WAIT 100
1443 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1444 udelay(10);
1445
ca58c3af 1446 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
b6016b76
MC		 1447 if (!(reg & BMCR_RESET)) {
1448 udelay(20);
1449 break;
1450 }
1451 }
1452 if (i == PHY_RESET_MAX_WAIT) {
1453 return -EBUSY;
1454 }
1455 return 0;
1456}
1457
1458static u32
1459bnx2_phy_get_pause_adv(struct bnx2 *bp)
1460{
1461 u32 adv = 0;
1462
1463 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1464 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1465
583c28e5 1466 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1467 adv = ADVERTISE_1000XPAUSE;
1468 }
1469 else {
1470 adv = ADVERTISE_PAUSE_CAP;
1471 }
1472 }
1473 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
583c28e5 1474 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1475 adv = ADVERTISE_1000XPSE_ASYM;
1476 }
1477 else {
1478 adv = ADVERTISE_PAUSE_ASYM;
1479 }
1480 }
1481 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
583c28e5 1482 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1483 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1484 }
1485 else {
1486 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1487 }
1488 }
1489 return adv;
1490}
1491
a2f13890 1492static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
0d8a6571 1493
b6016b76 1494static int
0d8a6571
MC		 1495bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1496{
1497 u32 speed_arg = 0, pause_adv;
1498
1499 pause_adv = bnx2_phy_get_pause_adv(bp);
1500
1501 if (bp->autoneg & AUTONEG_SPEED) {
1502 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1503 if (bp->advertising & ADVERTISED_10baseT_Half)
1504 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1505 if (bp->advertising & ADVERTISED_10baseT_Full)
1506 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1507 if (bp->advertising & ADVERTISED_100baseT_Half)
1508 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1509 if (bp->advertising & ADVERTISED_100baseT_Full)
1510 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1511 if (bp->advertising & ADVERTISED_1000baseT_Full)
1512 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1513 if (bp->advertising & ADVERTISED_2500baseX_Full)
1514 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1515 } else {
1516 if (bp->req_line_speed == SPEED_2500)
1517 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1518 else if (bp->req_line_speed == SPEED_1000)
1519 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1520 else if (bp->req_line_speed == SPEED_100) {
1521 if (bp->req_duplex == DUPLEX_FULL)
1522 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1523 else
1524 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1525 } else if (bp->req_line_speed == SPEED_10) {
1526 if (bp->req_duplex == DUPLEX_FULL)
1527 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1528 else
1529 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1530 }
1531 }
1532
1533 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1534 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
c26736ec 1535 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
0d8a6571
MC		 1536 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1537
1538 if (port == PORT_TP)
1539 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1540 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1541
2726d6e1 1542 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
0d8a6571
MC		 1543
1544 spin_unlock_bh(&bp->phy_lock);
a2f13890 1545 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
0d8a6571
MC		 1546 spin_lock_bh(&bp->phy_lock);
1547
1548 return 0;
1549}
1550
1551static int
1552bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
b6016b76 1553{
605a9e20 1554 u32 adv, bmcr;
b6016b76
MC		 1555 u32 new_adv = 0;
1556
583c28e5 1557 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1558 return (bnx2_setup_remote_phy(bp, port));
1559
b6016b76
MC		 1560 if (!(bp->autoneg & AUTONEG_SPEED)) {
1561 u32 new_bmcr;
5b0c76ad
MC		 1562 int force_link_down = 0;
1563
605a9e20
MC		 1564 if (bp->req_line_speed == SPEED_2500) {
1565 if (!bnx2_test_and_enable_2g5(bp))
1566 force_link_down = 1;
1567 } else if (bp->req_line_speed == SPEED_1000) {
1568 if (bnx2_test_and_disable_2g5(bp))
1569 force_link_down = 1;
1570 }
ca58c3af 1571 bnx2_read_phy(bp, bp->mii_adv, &adv);
80be4434
MC		 1572 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1573
ca58c3af 1574 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
605a9e20 1575 new_bmcr = bmcr & ~BMCR_ANENABLE;
80be4434 1576 new_bmcr |= BMCR_SPEED1000;
605a9e20 1577
27a005b8
MC		 1578 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1579 if (bp->req_line_speed == SPEED_2500)
1580 bnx2_enable_forced_2g5(bp);
1581 else if (bp->req_line_speed == SPEED_1000) {
1582 bnx2_disable_forced_2g5(bp);
1583 new_bmcr &= ~0x2000;
1584 }
1585
1586 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1587 if (bp->req_line_speed == SPEED_2500)
1588 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1589 else
1590 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
5b0c76ad
MC		 1591 }
1592
b6016b76 1593 if (bp->req_duplex == DUPLEX_FULL) {
5b0c76ad 1594 adv |= ADVERTISE_1000XFULL;
b6016b76
MC		 1595 new_bmcr |= BMCR_FULLDPLX;
1596 }
1597 else {
5b0c76ad 1598 adv |= ADVERTISE_1000XHALF;
b6016b76
MC		 1599 new_bmcr &= ~BMCR_FULLDPLX;
1600 }
5b0c76ad 1601 if ((new_bmcr != bmcr) || (force_link_down)) {
b6016b76
MC		 1602 /* Force a link down visible on the other side */
1603 if (bp->link_up) {
ca58c3af 1604 bnx2_write_phy(bp, bp->mii_adv, adv &
5b0c76ad
MC		 1605 ~(ADVERTISE_1000XFULL |
1606 ADVERTISE_1000XHALF));
ca58c3af 1607 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
b6016b76
MC		 1608 BMCR_ANRESTART | BMCR_ANENABLE);
1609
1610 bp->link_up = 0;
1611 netif_carrier_off(bp->dev);
ca58c3af 1612 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
80be4434 1613 bnx2_report_link(bp);
b6016b76 1614 }
ca58c3af
MC		 1615 bnx2_write_phy(bp, bp->mii_adv, adv);
1616 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
605a9e20
MC		 1617 } else {
1618 bnx2_resolve_flow_ctrl(bp);
1619 bnx2_set_mac_link(bp);
b6016b76
MC		 1620 }
1621 return 0;
1622 }
1623
605a9e20 1624 bnx2_test_and_enable_2g5(bp);
5b0c76ad 1625
b6016b76
MC		 1626 if (bp->advertising & ADVERTISED_1000baseT_Full)
1627 new_adv |= ADVERTISE_1000XFULL;
1628
1629 new_adv |= bnx2_phy_get_pause_adv(bp);
1630
ca58c3af
MC		 1631 bnx2_read_phy(bp, bp->mii_adv, &adv);
1632 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1633
1634 bp->serdes_an_pending = 0;
1635 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1636 /* Force a link down visible on the other side */
1637 if (bp->link_up) {
ca58c3af 1638 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
80be4434
MC		 1639 spin_unlock_bh(&bp->phy_lock);
1640 msleep(20);
1641 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 1642 }
1643
ca58c3af
MC		 1644 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1645 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
b6016b76 1646 BMCR_ANENABLE);
f8dd064e
MC		 1647 /* Speed up link-up time when the link partner
1648 * does not autonegotiate which is very common
1649 * in blade servers. Some blade servers use
1650 * IPMI for kerboard input and it's important
1651 * to minimize link disruptions. Autoneg. involves
1652 * exchanging base pages plus 3 next pages and
1653 * normally completes in about 120 msec.
1654 */
1655 bp->current_interval = SERDES_AN_TIMEOUT;
1656 bp->serdes_an_pending = 1;
1657 mod_timer(&bp->timer, jiffies + bp->current_interval);
605a9e20
MC		 1658 } else {
1659 bnx2_resolve_flow_ctrl(bp);
1660 bnx2_set_mac_link(bp);
b6016b76
MC		 1661 }
1662
1663 return 0;
1664}
1665
1666#define ETHTOOL_ALL_FIBRE_SPEED \
583c28e5 1667 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
deaf391b
MC		 1668 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1669 (ADVERTISED_1000baseT_Full)
b6016b76
MC		 1670
1671#define ETHTOOL_ALL_COPPER_SPEED \
1672 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1673 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1674 ADVERTISED_1000baseT_Full)
1675
1676#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1677 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
6aa20a22 1678
b6016b76
MC		 1679#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1680
0d8a6571
MC		 1681static void
1682bnx2_set_default_remote_link(struct bnx2 *bp)
1683{
1684 u32 link;
1685
1686 if (bp->phy_port == PORT_TP)
2726d6e1 1687 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
0d8a6571 1688 else
2726d6e1 1689 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
0d8a6571
MC		 1690
1691 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1692 bp->req_line_speed = 0;
1693 bp->autoneg |= AUTONEG_SPEED;
1694 bp->advertising = ADVERTISED_Autoneg;
1695 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1696 bp->advertising |= ADVERTISED_10baseT_Half;
1697 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1698 bp->advertising |= ADVERTISED_10baseT_Full;
1699 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1700 bp->advertising |= ADVERTISED_100baseT_Half;
1701 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1702 bp->advertising |= ADVERTISED_100baseT_Full;
1703 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1704 bp->advertising |= ADVERTISED_1000baseT_Full;
1705 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1706 bp->advertising |= ADVERTISED_2500baseX_Full;
1707 } else {
1708 bp->autoneg = 0;
1709 bp->advertising = 0;
1710 bp->req_duplex = DUPLEX_FULL;
1711 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1712 bp->req_line_speed = SPEED_10;
1713 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1714 bp->req_duplex = DUPLEX_HALF;
1715 }
1716 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1717 bp->req_line_speed = SPEED_100;
1718 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1719 bp->req_duplex = DUPLEX_HALF;
1720 }
1721 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1722 bp->req_line_speed = SPEED_1000;
1723 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1724 bp->req_line_speed = SPEED_2500;
1725 }
1726}
1727
deaf391b
MC		 1728static void
1729bnx2_set_default_link(struct bnx2 *bp)
1730{
ab59859d
HH		 1731 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1732 bnx2_set_default_remote_link(bp);
1733 return;
1734 }
0d8a6571 1735
deaf391b
MC		 1736 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1737 bp->req_line_speed = 0;
583c28e5 1738 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
deaf391b
MC		 1739 u32 reg;
1740
1741 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1742
2726d6e1 1743 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
deaf391b
MC		 1744 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1745 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1746 bp->autoneg = 0;
1747 bp->req_line_speed = bp->line_speed = SPEED_1000;
1748 bp->req_duplex = DUPLEX_FULL;
1749 }
1750 } else
1751 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1752}
1753
df149d70
MC		 1754static void
1755bnx2_send_heart_beat(struct bnx2 *bp)
1756{
1757 u32 msg;
1758 u32 addr;
1759
1760 spin_lock(&bp->indirect_lock);
1761 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1762 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1763 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1764 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1765 spin_unlock(&bp->indirect_lock);
1766}
1767
0d8a6571
MC		 1768static void
1769bnx2_remote_phy_event(struct bnx2 *bp)
1770{
1771 u32 msg;
1772 u8 link_up = bp->link_up;
1773 u8 old_port;
1774
2726d6e1 1775 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
0d8a6571 1776
df149d70
MC		 1777 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1778 bnx2_send_heart_beat(bp);
1779
1780 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1781
0d8a6571
MC		 1782 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1783 bp->link_up = 0;
1784 else {
1785 u32 speed;
1786
1787 bp->link_up = 1;
1788 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1789 bp->duplex = DUPLEX_FULL;
1790 switch (speed) {
1791 case BNX2_LINK_STATUS_10HALF:
1792 bp->duplex = DUPLEX_HALF;
1793 case BNX2_LINK_STATUS_10FULL:
1794 bp->line_speed = SPEED_10;
1795 break;
1796 case BNX2_LINK_STATUS_100HALF:
1797 bp->duplex = DUPLEX_HALF;
1798 case BNX2_LINK_STATUS_100BASE_T4:
1799 case BNX2_LINK_STATUS_100FULL:
1800 bp->line_speed = SPEED_100;
1801 break;
1802 case BNX2_LINK_STATUS_1000HALF:
1803 bp->duplex = DUPLEX_HALF;
1804 case BNX2_LINK_STATUS_1000FULL:
1805 bp->line_speed = SPEED_1000;
1806 break;
1807 case BNX2_LINK_STATUS_2500HALF:
1808 bp->duplex = DUPLEX_HALF;
1809 case BNX2_LINK_STATUS_2500FULL:
1810 bp->line_speed = SPEED_2500;
1811 break;
1812 default:
1813 bp->line_speed = 0;
1814 break;
1815 }
1816
0d8a6571
MC		 1817 bp->flow_ctrl = 0;
1818 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1819 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1820 if (bp->duplex == DUPLEX_FULL)
1821 bp->flow_ctrl = bp->req_flow_ctrl;
1822 } else {
1823 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1824 bp->flow_ctrl |= FLOW_CTRL_TX;
1825 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1826 bp->flow_ctrl |= FLOW_CTRL_RX;
1827 }
1828
1829 old_port = bp->phy_port;
1830 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1831 bp->phy_port = PORT_FIBRE;
1832 else
1833 bp->phy_port = PORT_TP;
1834
1835 if (old_port != bp->phy_port)
1836 bnx2_set_default_link(bp);
1837
0d8a6571
MC		 1838 }
1839 if (bp->link_up != link_up)
1840 bnx2_report_link(bp);
1841
1842 bnx2_set_mac_link(bp);
1843}
1844
1845static int
1846bnx2_set_remote_link(struct bnx2 *bp)
1847{
1848 u32 evt_code;
1849
2726d6e1 1850 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
0d8a6571
MC		 1851 switch (evt_code) {
1852 case BNX2_FW_EVT_CODE_LINK_EVENT:
1853 bnx2_remote_phy_event(bp);
1854 break;
1855 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1856 default:
df149d70 1857 bnx2_send_heart_beat(bp);
0d8a6571
MC		 1858 break;
1859 }
1860 return 0;
1861}
1862
b6016b76
MC		 1863static int
1864bnx2_setup_copper_phy(struct bnx2 *bp)
1865{
1866 u32 bmcr;
1867 u32 new_bmcr;
1868
ca58c3af 1869 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1870
1871 if (bp->autoneg & AUTONEG_SPEED) {
1872 u32 adv_reg, adv1000_reg;
1873 u32 new_adv_reg = 0;
1874 u32 new_adv1000_reg = 0;
1875
ca58c3af 1876 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
b6016b76
MC		 1877 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1878 ADVERTISE_PAUSE_ASYM);
1879
1880 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1881 adv1000_reg &= PHY_ALL_1000_SPEED;
1882
1883 if (bp->advertising & ADVERTISED_10baseT_Half)
1884 new_adv_reg |= ADVERTISE_10HALF;
1885 if (bp->advertising & ADVERTISED_10baseT_Full)
1886 new_adv_reg |= ADVERTISE_10FULL;
1887 if (bp->advertising & ADVERTISED_100baseT_Half)
1888 new_adv_reg |= ADVERTISE_100HALF;
1889 if (bp->advertising & ADVERTISED_100baseT_Full)
1890 new_adv_reg |= ADVERTISE_100FULL;
1891 if (bp->advertising & ADVERTISED_1000baseT_Full)
1892 new_adv1000_reg |= ADVERTISE_1000FULL;
6aa20a22 1893
b6016b76
MC		 1894 new_adv_reg |= ADVERTISE_CSMA;
1895
1896 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1897
1898 if ((adv1000_reg != new_adv1000_reg) ||
1899 (adv_reg != new_adv_reg) ||
1900 ((bmcr & BMCR_ANENABLE) == 0)) {
1901
ca58c3af 1902 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
b6016b76 1903 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
ca58c3af 1904 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
b6016b76
MC		 1905 BMCR_ANENABLE);
1906 }
1907 else if (bp->link_up) {
1908 /* Flow ctrl may have changed from auto to forced */
1909 /* or vice-versa. */
1910
1911 bnx2_resolve_flow_ctrl(bp);
1912 bnx2_set_mac_link(bp);
1913 }
1914 return 0;
1915 }
1916
1917 new_bmcr = 0;
1918 if (bp->req_line_speed == SPEED_100) {
1919 new_bmcr |= BMCR_SPEED100;
1920 }
1921 if (bp->req_duplex == DUPLEX_FULL) {
1922 new_bmcr |= BMCR_FULLDPLX;
1923 }
1924 if (new_bmcr != bmcr) {
1925 u32 bmsr;
b6016b76 1926
ca58c3af
MC		 1927 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1928 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
6aa20a22 1929
b6016b76
MC		 1930 if (bmsr & BMSR_LSTATUS) {
1931 /* Force link down */
ca58c3af 1932 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
a16dda0e
MC		 1933 spin_unlock_bh(&bp->phy_lock);
1934 msleep(50);
1935 spin_lock_bh(&bp->phy_lock);
1936
ca58c3af
MC		 1937 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1938 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
b6016b76
MC		 1939 }
1940
ca58c3af 1941 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
b6016b76
MC		 1942
1943 /* Normally, the new speed is setup after the link has
1944 * gone down and up again. In some cases, link will not go
1945 * down so we need to set up the new speed here.
1946 */
1947 if (bmsr & BMSR_LSTATUS) {
1948 bp->line_speed = bp->req_line_speed;
1949 bp->duplex = bp->req_duplex;
1950 bnx2_resolve_flow_ctrl(bp);
1951 bnx2_set_mac_link(bp);
1952 }
27a005b8
MC		 1953 } else {
1954 bnx2_resolve_flow_ctrl(bp);
1955 bnx2_set_mac_link(bp);
b6016b76
MC		 1956 }
1957 return 0;
1958}
1959
1960static int
0d8a6571 1961bnx2_setup_phy(struct bnx2 *bp, u8 port)
b6016b76
MC		 1962{
1963 if (bp->loopback == MAC_LOOPBACK)
1964 return 0;
1965
583c28e5 1966 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 1967 return (bnx2_setup_serdes_phy(bp, port));
b6016b76
MC		 1968 }
1969 else {
1970 return (bnx2_setup_copper_phy(bp));
1971 }
1972}
1973
27a005b8 1974static int
9a120bc5 1975bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
27a005b8
MC		 1976{
1977 u32 val;
1978
1979 bp->mii_bmcr = MII_BMCR + 0x10;
1980 bp->mii_bmsr = MII_BMSR + 0x10;
1981 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1982 bp->mii_adv = MII_ADVERTISE + 0x10;
1983 bp->mii_lpa = MII_LPA + 0x10;
1984 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1985
1986 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1987 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1988
1989 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
9a120bc5
MC		 1990 if (reset_phy)
1991 bnx2_reset_phy(bp);
27a005b8
MC		 1992
1993 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1994
1995 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1996 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1997 val |= MII_BNX2_SD_1000XCTL1_FIBER;
1998 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1999
2000 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2001 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
583c28e5 2002 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
27a005b8
MC		 2003 val |= BCM5708S_UP1_2G5;
2004 else
2005 val &= ~BCM5708S_UP1_2G5;
2006 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2007
2008 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2009 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2010 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2011 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2012
2013 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2014
2015 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2016 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2017 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2018
2019 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2020
2021 return 0;
2022}
2023
b6016b76 2024static int
9a120bc5 2025bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
5b0c76ad
MC		 2026{
2027 u32 val;
2028
9a120bc5
MC		 2029 if (reset_phy)
2030 bnx2_reset_phy(bp);
27a005b8
MC		 2031
2032 bp->mii_up1 = BCM5708S_UP1;
2033
5b0c76ad
MC		 2034 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2035 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2036 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2037
2038 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2039 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2040 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2041
2042 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2043 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2044 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2045
583c28e5 2046 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
5b0c76ad
MC		 2047 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2048 val |= BCM5708S_UP1_2G5;
2049 bnx2_write_phy(bp, BCM5708S_UP1, val);
2050 }
2051
2052 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
dda1e390
MC		 2053 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2054 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
5b0c76ad
MC		 2055 /* increase tx signal amplitude */
2056 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2057 BCM5708S_BLK_ADDR_TX_MISC);
2058 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2059 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2060 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2061 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2062 }
2063
2726d6e1 2064 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
5b0c76ad
MC		 2065 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2066
2067 if (val) {
2068 u32 is_backplane;
2069
2726d6e1 2070 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
5b0c76ad
MC		 2071 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2072 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2073 BCM5708S_BLK_ADDR_TX_MISC);
2074 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2075 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2076 BCM5708S_BLK_ADDR_DIG);
2077 }
2078 }
2079 return 0;
2080}
2081
2082static int
9a120bc5 2083bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2084{
9a120bc5
MC		 2085 if (reset_phy)
2086 bnx2_reset_phy(bp);
27a005b8 2087
583c28e5 2088 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b6016b76 2089
59b47d8a
MC		 2090 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2091 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
b6016b76
MC		 2092
2093 if (bp->dev->mtu > 1500) {
2094 u32 val;
2095
2096 /* Set extended packet length bit */
2097 bnx2_write_phy(bp, 0x18, 0x7);
2098 bnx2_read_phy(bp, 0x18, &val);
2099 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2100
2101 bnx2_write_phy(bp, 0x1c, 0x6c00);
2102 bnx2_read_phy(bp, 0x1c, &val);
2103 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2104 }
2105 else {
2106 u32 val;
2107
2108 bnx2_write_phy(bp, 0x18, 0x7);
2109 bnx2_read_phy(bp, 0x18, &val);
2110 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2111
2112 bnx2_write_phy(bp, 0x1c, 0x6c00);
2113 bnx2_read_phy(bp, 0x1c, &val);
2114 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2115 }
2116
2117 return 0;
2118}
2119
2120static int
9a120bc5 2121bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2122{
5b0c76ad
MC		 2123 u32 val;
2124
9a120bc5
MC		 2125 if (reset_phy)
2126 bnx2_reset_phy(bp);
27a005b8 2127
583c28e5 2128 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
b6016b76
MC		 2129 bnx2_write_phy(bp, 0x18, 0x0c00);
2130 bnx2_write_phy(bp, 0x17, 0x000a);
2131 bnx2_write_phy(bp, 0x15, 0x310b);
2132 bnx2_write_phy(bp, 0x17, 0x201f);
2133 bnx2_write_phy(bp, 0x15, 0x9506);
2134 bnx2_write_phy(bp, 0x17, 0x401f);
2135 bnx2_write_phy(bp, 0x15, 0x14e2);
2136 bnx2_write_phy(bp, 0x18, 0x0400);
2137 }
2138
583c28e5 2139 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
b659f44e
MC		 2140 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2141 MII_BNX2_DSP_EXPAND_REG | 0x8);
2142 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2143 val &= ~(1 << 8);
2144 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2145 }
2146
b6016b76 2147 if (bp->dev->mtu > 1500) {
b6016b76
MC		 2148 /* Set extended packet length bit */
2149 bnx2_write_phy(bp, 0x18, 0x7);
2150 bnx2_read_phy(bp, 0x18, &val);
2151 bnx2_write_phy(bp, 0x18, val | 0x4000);
2152
2153 bnx2_read_phy(bp, 0x10, &val);
2154 bnx2_write_phy(bp, 0x10, val | 0x1);
2155 }
2156 else {
b6016b76
MC		 2157 bnx2_write_phy(bp, 0x18, 0x7);
2158 bnx2_read_phy(bp, 0x18, &val);
2159 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2160
2161 bnx2_read_phy(bp, 0x10, &val);
2162 bnx2_write_phy(bp, 0x10, val & ~0x1);
2163 }
2164
5b0c76ad
MC		 2165 /* ethernet@wirespeed */
2166 bnx2_write_phy(bp, 0x18, 0x7007);
2167 bnx2_read_phy(bp, 0x18, &val);
2168 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
b6016b76
MC		 2169 return 0;
2170}
2171
2172
2173static int
9a120bc5 2174bnx2_init_phy(struct bnx2 *bp, int reset_phy)
b6016b76
MC		 2175{
2176 u32 val;
2177 int rc = 0;
2178
583c28e5
MC		 2179 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2180 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
b6016b76 2181
ca58c3af
MC		 2182 bp->mii_bmcr = MII_BMCR;
2183 bp->mii_bmsr = MII_BMSR;
27a005b8 2184 bp->mii_bmsr1 = MII_BMSR;
ca58c3af
MC		 2185 bp->mii_adv = MII_ADVERTISE;
2186 bp->mii_lpa = MII_LPA;
2187
b6016b76
MC		 2188 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2189
583c28e5 2190 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 2191 goto setup_phy;
2192
b6016b76
MC		 2193 bnx2_read_phy(bp, MII_PHYSID1, &val);
2194 bp->phy_id = val << 16;
2195 bnx2_read_phy(bp, MII_PHYSID2, &val);
2196 bp->phy_id |= val & 0xffff;
2197
583c28e5 2198 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad 2199 if (CHIP_NUM(bp) == CHIP_NUM_5706)
9a120bc5 2200 rc = bnx2_init_5706s_phy(bp, reset_phy);
5b0c76ad 2201 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
9a120bc5 2202 rc = bnx2_init_5708s_phy(bp, reset_phy);
27a005b8 2203 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
9a120bc5 2204 rc = bnx2_init_5709s_phy(bp, reset_phy);
b6016b76
MC		 2205 }
2206 else {
9a120bc5 2207 rc = bnx2_init_copper_phy(bp, reset_phy);
b6016b76
MC		 2208 }
2209
0d8a6571
MC		 2210setup_phy:
2211 if (!rc)
2212 rc = bnx2_setup_phy(bp, bp->phy_port);
b6016b76
MC		 2213
2214 return rc;
2215}
2216
2217static int
2218bnx2_set_mac_loopback(struct bnx2 *bp)
2219{
2220 u32 mac_mode;
2221
2222 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2223 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2224 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2225 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2226 bp->link_up = 1;
2227 return 0;
2228}
2229
bc5a0690
MC		 2230static int bnx2_test_link(struct bnx2 *);
2231
2232static int
2233bnx2_set_phy_loopback(struct bnx2 *bp)
2234{
2235 u32 mac_mode;
2236 int rc, i;
2237
2238 spin_lock_bh(&bp->phy_lock);
ca58c3af 2239 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
bc5a0690
MC		 2240 BMCR_SPEED1000);
2241 spin_unlock_bh(&bp->phy_lock);
2242 if (rc)
2243 return rc;
2244
2245 for (i = 0; i < 10; i++) {
2246 if (bnx2_test_link(bp) == 0)
2247 break;
80be4434 2248 msleep(100);
bc5a0690
MC		 2249 }
2250
2251 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2252 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2253 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 2254 BNX2_EMAC_MODE_25G_MODE);
bc5a0690
MC		 2255
2256 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2257 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2258 bp->link_up = 1;
2259 return 0;
2260}
2261
b6016b76 2262static int
a2f13890 2263bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
b6016b76
MC		 2264{
2265 int i;
2266 u32 val;
2267
b6016b76
MC		 2268 bp->fw_wr_seq++;
2269 msg_data |= bp->fw_wr_seq;
2270
2726d6e1 2271 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76 2272
a2f13890
MC		 2273 if (!ack)
2274 return 0;
2275
b6016b76 2276 /* wait for an acknowledgement. */
b090ae2b
MC		 2277 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2278 msleep(10);
b6016b76 2279
2726d6e1 2280 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
b6016b76
MC		 2281
2282 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2283 break;
2284 }
b090ae2b
MC		 2285 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2286 return 0;
b6016b76
MC		 2287
2288 /* If we timed out, inform the firmware that this is the case. */
b090ae2b
MC		 2289 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2290 if (!silent)
2291 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2292 "%x\n", msg_data);
b6016b76
MC		 2293
2294 msg_data &= ~BNX2_DRV_MSG_CODE;
2295 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2296
2726d6e1 2297 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76 2298
b6016b76
MC		 2299 return -EBUSY;
2300 }
2301
b090ae2b
MC		 2302 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2303 return -EIO;
2304
b6016b76
MC		 2305 return 0;
2306}
2307
59b47d8a
MC		 2308static int
2309bnx2_init_5709_context(struct bnx2 *bp)
2310{
2311 int i, ret = 0;
2312 u32 val;
2313
2314 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2315 val |= (BCM_PAGE_BITS - 8) << 16;
2316 REG_WR(bp, BNX2_CTX_COMMAND, val);
641bdcd5
MC		 2317 for (i = 0; i < 10; i++) {
2318 val = REG_RD(bp, BNX2_CTX_COMMAND);
2319 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2320 break;
2321 udelay(2);
2322 }
2323 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2324 return -EBUSY;
2325
59b47d8a
MC		 2326 for (i = 0; i < bp->ctx_pages; i++) {
2327 int j;
2328
352f7687
MC		 2329 if (bp->ctx_blk[i])
2330 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2331 else
2332 return -ENOMEM;
2333
59b47d8a
MC		 2334 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2335 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2336 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2337 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2338 (u64) bp->ctx_blk_mapping[i] >> 32);
2339 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2340 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2341 for (j = 0; j < 10; j++) {
2342
2343 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2344 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2345 break;
2346 udelay(5);
2347 }
2348 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2349 ret = -EBUSY;
2350 break;
2351 }
2352 }
2353 return ret;
2354}
2355
b6016b76
MC		 2356static void
2357bnx2_init_context(struct bnx2 *bp)
2358{
2359 u32 vcid;
2360
2361 vcid = 96;
2362 while (vcid) {
2363 u32 vcid_addr, pcid_addr, offset;
7947b20e 2364 int i;
b6016b76
MC		 2365
2366 vcid--;
2367
2368 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2369 u32 new_vcid;
2370
2371 vcid_addr = GET_PCID_ADDR(vcid);
2372 if (vcid & 0x8) {
2373 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2374 }
2375 else {
2376 new_vcid = vcid;
2377 }
2378 pcid_addr = GET_PCID_ADDR(new_vcid);
2379 }
2380 else {
2381 vcid_addr = GET_CID_ADDR(vcid);
2382 pcid_addr = vcid_addr;
2383 }
2384
7947b20e
MC		 2385 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2386 vcid_addr += (i << PHY_CTX_SHIFT);
2387 pcid_addr += (i << PHY_CTX_SHIFT);
b6016b76 2388
5d5d0015 2389 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
7947b20e 2390 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
b6016b76 2391
7947b20e
MC		 2392 /* Zero out the context. */
2393 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
62a8313c 2394 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
7947b20e 2395 }
b6016b76
MC		 2396 }
2397}
2398
2399static int
2400bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2401{
2402 u16 *good_mbuf;
2403 u32 good_mbuf_cnt;
2404 u32 val;
2405
2406 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2407 if (good_mbuf == NULL) {
2408 printk(KERN_ERR PFX "Failed to allocate memory in "
2409 "bnx2_alloc_bad_rbuf\n");
2410 return -ENOMEM;
2411 }
2412
2413 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2414 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2415
2416 good_mbuf_cnt = 0;
2417
2418 /* Allocate a bunch of mbufs and save the good ones in an array. */
2726d6e1 2419 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76 2420 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2726d6e1
MC		 2421 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2422 BNX2_RBUF_COMMAND_ALLOC_REQ);
b6016b76 2423
2726d6e1 2424 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
b6016b76
MC		 2425
2426 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2427
2428 /* The addresses with Bit 9 set are bad memory blocks. */
2429 if (!(val & (1 << 9))) {
2430 good_mbuf[good_mbuf_cnt] = (u16) val;
2431 good_mbuf_cnt++;
2432 }
2433
2726d6e1 2434 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76
MC		 2435 }
2436
2437 /* Free the good ones back to the mbuf pool thus discarding
2438 * all the bad ones. */
2439 while (good_mbuf_cnt) {
2440 good_mbuf_cnt--;
2441
2442 val = good_mbuf[good_mbuf_cnt];
2443 val = (val << 9) | val | 1;
2444
2726d6e1 2445 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
b6016b76
MC		 2446 }
2447 kfree(good_mbuf);
2448 return 0;
2449}
2450
2451static void
5fcaed01 2452bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
b6016b76
MC		 2453{
2454 u32 val;
b6016b76
MC		 2455
2456 val = (mac_addr[0] << 8) | mac_addr[1];
2457
5fcaed01 2458 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
b6016b76 2459
6aa20a22 2460 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
b6016b76
MC		 2461 (mac_addr[4] << 8) | mac_addr[5];
2462
5fcaed01 2463 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
b6016b76
MC		 2464}
2465
47bf4246 2466static inline int
bb4f98ab 2467bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
47bf4246
MC		 2468{
2469 dma_addr_t mapping;
bb4f98ab 2470 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
47bf4246 2471 struct rx_bd *rxbd =
bb4f98ab 2472 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
47bf4246
MC		 2473 struct page *page = alloc_page(GFP_ATOMIC);
2474
2475 if (!page)
2476 return -ENOMEM;
2477 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2478 PCI_DMA_FROMDEVICE);
3d16af86
BL		 2479 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2480 __free_page(page);
2481 return -EIO;
2482 }
2483
47bf4246
MC		 2484 rx_pg->page = page;
2485 pci_unmap_addr_set(rx_pg, mapping, mapping);
2486 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2487 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2488 return 0;
2489}
2490
2491static void
bb4f98ab 2492bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
47bf4246 2493{
bb4f98ab 2494 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
47bf4246
MC		 2495 struct page *page = rx_pg->page;
2496
2497 if (!page)
2498 return;
2499
2500 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2501 PCI_DMA_FROMDEVICE);
2502
2503 __free_page(page);
2504 rx_pg->page = NULL;
2505}
2506
b6016b76 2507static inline int
bb4f98ab 2508bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
b6016b76
MC		 2509{
2510 struct sk_buff *skb;
bb4f98ab 2511 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
b6016b76 2512 dma_addr_t mapping;
bb4f98ab 2513 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
b6016b76
MC		 2514 unsigned long align;
2515
932f3772 2516 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
b6016b76
MC		 2517 if (skb == NULL) {
2518 return -ENOMEM;
2519 }
2520
59b47d8a
MC		 2521 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2522 skb_reserve(skb, BNX2_RX_ALIGN - align);
b6016b76 2523
b6016b76
MC		 2524 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2525 PCI_DMA_FROMDEVICE);
3d16af86
BL		 2526 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2527 dev_kfree_skb(skb);
2528 return -EIO;
2529 }
b6016b76
MC		 2530
2531 rx_buf->skb = skb;
2532 pci_unmap_addr_set(rx_buf, mapping, mapping);
2533
2534 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2535 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2536
bb4f98ab 2537 rxr->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76
MC		 2538
2539 return 0;
2540}
2541
da3e4fbe 2542static int
35efa7c1 2543bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
b6016b76 2544{
43e80b89 2545 struct status_block *sblk = bnapi->status_blk.msi;
b6016b76 2546 u32 new_link_state, old_link_state;
da3e4fbe 2547 int is_set = 1;
b6016b76 2548
da3e4fbe
MC		 2549 new_link_state = sblk->status_attn_bits & event;
2550 old_link_state = sblk->status_attn_bits_ack & event;
b6016b76 2551 if (new_link_state != old_link_state) {
da3e4fbe
MC		 2552 if (new_link_state)
2553 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2554 else
2555 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2556 } else
2557 is_set = 0;
2558
2559 return is_set;
2560}
2561
2562static void
35efa7c1 2563bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
da3e4fbe 2564{
74ecc62d
MC		 2565 spin_lock(&bp->phy_lock);
2566
2567 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
b6016b76 2568 bnx2_set_link(bp);
35efa7c1 2569 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
0d8a6571
MC		 2570 bnx2_set_remote_link(bp);
2571
74ecc62d
MC		 2572 spin_unlock(&bp->phy_lock);
2573
b6016b76
MC		 2574}
2575
ead7270b 2576static inline u16
35efa7c1 2577bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
ead7270b
MC		 2578{
2579 u16 cons;
2580
43e80b89
MC		 2581 /* Tell compiler that status block fields can change. */
2582 barrier();
2583 cons = *bnapi->hw_tx_cons_ptr;
ead7270b
MC		 2584 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2585 cons++;
2586 return cons;
2587}
2588
57851d84
MC		 2589static int
2590bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76 2591{
35e9010b 2592 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
b6016b76 2593 u16 hw_cons, sw_cons, sw_ring_cons;
706bf240
BL		 2594 int tx_pkt = 0, index;
2595 struct netdev_queue *txq;
2596
2597 index = (bnapi - bp->bnx2_napi);
2598 txq = netdev_get_tx_queue(bp->dev, index);
b6016b76 2599
35efa7c1 2600 hw_cons = bnx2_get_hw_tx_cons(bnapi);
35e9010b 2601 sw_cons = txr->tx_cons;
b6016b76
MC		 2602
2603 while (sw_cons != hw_cons) {
3d16af86 2604 struct sw_tx_bd *tx_buf;
b6016b76
MC		 2605 struct sk_buff *skb;
2606 int i, last;
2607
2608 sw_ring_cons = TX_RING_IDX(sw_cons);
2609
35e9010b 2610 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
b6016b76 2611 skb = tx_buf->skb;
1d39ed56 2612
b6016b76 2613 /* partial BD completions possible with TSO packets */
89114afd 2614 if (skb_is_gso(skb)) {
b6016b76
MC		 2615 u16 last_idx, last_ring_idx;
2616
2617 last_idx = sw_cons +
2618 skb_shinfo(skb)->nr_frags + 1;
2619 last_ring_idx = sw_ring_cons +
2620 skb_shinfo(skb)->nr_frags + 1;
2621 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2622 last_idx++;
2623 }
2624 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2625 break;
2626 }
2627 }
1d39ed56 2628
3d16af86 2629 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
b6016b76
MC		 2630
2631 tx_buf->skb = NULL;
2632 last = skb_shinfo(skb)->nr_frags;
2633
2634 for (i = 0; i < last; i++) {
2635 sw_cons = NEXT_TX_BD(sw_cons);
b6016b76
MC		 2636 }
2637
2638 sw_cons = NEXT_TX_BD(sw_cons);
2639
745720e5 2640 dev_kfree_skb(skb);
57851d84
MC		 2641 tx_pkt++;
2642 if (tx_pkt == budget)
2643 break;
b6016b76 2644
35efa7c1 2645 hw_cons = bnx2_get_hw_tx_cons(bnapi);
b6016b76
MC		 2646 }
2647
35e9010b
MC		 2648 txr->hw_tx_cons = hw_cons;
2649 txr->tx_cons = sw_cons;
706bf240 2650
2f8af120 2651 /* Need to make the tx_cons update visible to bnx2_start_xmit()
706bf240 2652 * before checking for netif_tx_queue_stopped(). Without the
2f8af120
MC		 2653 * memory barrier, there is a small possibility that bnx2_start_xmit()
2654 * will miss it and cause the queue to be stopped forever.
2655 */
2656 smp_mb();
b6016b76 2657
706bf240 2658 if (unlikely(netif_tx_queue_stopped(txq)) &&
35e9010b 2659 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
706bf240
BL		 2660 __netif_tx_lock(txq, smp_processor_id());
2661 if ((netif_tx_queue_stopped(txq)) &&
35e9010b 2662 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
706bf240
BL		 2663 netif_tx_wake_queue(txq);
2664 __netif_tx_unlock(txq);
b6016b76 2665 }
706bf240 2666
57851d84 2667 return tx_pkt;
b6016b76
MC		 2668}
2669
1db82f2a 2670static void
bb4f98ab 2671bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
a1f60190 2672 struct sk_buff *skb, int count)
1db82f2a
MC		 2673{
2674 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2675 struct rx_bd *cons_bd, *prod_bd;
1db82f2a 2676 int i;
3d16af86 2677 u16 hw_prod, prod;
bb4f98ab 2678 u16 cons = rxr->rx_pg_cons;
1db82f2a 2679
3d16af86
BL		 2680 cons_rx_pg = &rxr->rx_pg_ring[cons];
2681
2682 /* The caller was unable to allocate a new page to replace the
2683 * last one in the frags array, so we need to recycle that page
2684 * and then free the skb.
2685 */
2686 if (skb) {
2687 struct page *page;
2688 struct skb_shared_info *shinfo;
2689
2690 shinfo = skb_shinfo(skb);
2691 shinfo->nr_frags--;
2692 page = shinfo->frags[shinfo->nr_frags].page;
2693 shinfo->frags[shinfo->nr_frags].page = NULL;
2694
2695 cons_rx_pg->page = page;
2696 dev_kfree_skb(skb);
2697 }
2698
2699 hw_prod = rxr->rx_pg_prod;
2700
1db82f2a
MC		 2701 for (i = 0; i < count; i++) {
2702 prod = RX_PG_RING_IDX(hw_prod);
2703
bb4f98ab
MC		 2704 prod_rx_pg = &rxr->rx_pg_ring[prod];
2705 cons_rx_pg = &rxr->rx_pg_ring[cons];
2706 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2707 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1db82f2a 2708
1db82f2a
MC		 2709 if (prod != cons) {
2710 prod_rx_pg->page = cons_rx_pg->page;
2711 cons_rx_pg->page = NULL;
2712 pci_unmap_addr_set(prod_rx_pg, mapping,
2713 pci_unmap_addr(cons_rx_pg, mapping));
2714
2715 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2716 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2717
2718 }
2719 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2720 hw_prod = NEXT_RX_BD(hw_prod);
2721 }
bb4f98ab
MC		 2722 rxr->rx_pg_prod = hw_prod;
2723 rxr->rx_pg_cons = cons;
1db82f2a
MC		 2724}
2725
b6016b76 2726static inline void
bb4f98ab
MC		 2727bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2728 struct sk_buff *skb, u16 cons, u16 prod)
b6016b76 2729{
236b6394
MC		 2730 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2731 struct rx_bd *cons_bd, *prod_bd;
2732
bb4f98ab
MC		 2733 cons_rx_buf = &rxr->rx_buf_ring[cons];
2734 prod_rx_buf = &rxr->rx_buf_ring[prod];
b6016b76
MC		 2735
2736 pci_dma_sync_single_for_device(bp->pdev,
2737 pci_unmap_addr(cons_rx_buf, mapping),
601d3d18 2738 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
b6016b76 2739
bb4f98ab 2740 rxr->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76 2741
236b6394 2742 prod_rx_buf->skb = skb;
b6016b76 2743
236b6394
MC		 2744 if (cons == prod)
2745 return;
b6016b76 2746
236b6394
MC		 2747 pci_unmap_addr_set(prod_rx_buf, mapping,
2748 pci_unmap_addr(cons_rx_buf, mapping));
2749
bb4f98ab
MC		 2750 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2751 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
236b6394
MC		 2752 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2753 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
b6016b76
MC		 2754}
2755
85833c62 2756static int
bb4f98ab 2757bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
a1f60190
MC		 2758 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2759 u32 ring_idx)
85833c62
MC		 2760{
2761 int err;
2762 u16 prod = ring_idx & 0xffff;
2763
bb4f98ab 2764 err = bnx2_alloc_rx_skb(bp, rxr, prod);
85833c62 2765 if (unlikely(err)) {
bb4f98ab 2766 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
1db82f2a
MC		 2767 if (hdr_len) {
2768 unsigned int raw_len = len + 4;
2769 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2770
bb4f98ab 2771 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
1db82f2a 2772 }
85833c62
MC		 2773 return err;
2774 }
2775
d89cb6af 2776 skb_reserve(skb, BNX2_RX_OFFSET);
85833c62
MC		 2777 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2778 PCI_DMA_FROMDEVICE);
2779
1db82f2a
MC		 2780 if (hdr_len == 0) {
2781 skb_put(skb, len);
2782 return 0;
2783 } else {
2784 unsigned int i, frag_len, frag_size, pages;
2785 struct sw_pg *rx_pg;
bb4f98ab
MC		 2786 u16 pg_cons = rxr->rx_pg_cons;
2787 u16 pg_prod = rxr->rx_pg_prod;
1db82f2a
MC		 2788
2789 frag_size = len + 4 - hdr_len;
2790 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2791 skb_put(skb, hdr_len);
2792
2793 for (i = 0; i < pages; i++) {
3d16af86
BL		 2794 dma_addr_t mapping_old;
2795
1db82f2a
MC		 2796 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2797 if (unlikely(frag_len <= 4)) {
2798 unsigned int tail = 4 - frag_len;
2799
bb4f98ab
MC		 2800 rxr->rx_pg_cons = pg_cons;
2801 rxr->rx_pg_prod = pg_prod;
2802 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
a1f60190 2803 pages - i);
1db82f2a
MC		 2804 skb->len -= tail;
2805 if (i == 0) {
2806 skb->tail -= tail;
2807 } else {
2808 skb_frag_t *frag =
2809 &skb_shinfo(skb)->frags[i - 1];
2810 frag->size -= tail;
2811 skb->data_len -= tail;
2812 skb->truesize -= tail;
2813 }
2814 return 0;
2815 }
bb4f98ab 2816 rx_pg = &rxr->rx_pg_ring[pg_cons];
1db82f2a 2817
3d16af86
BL		 2818 /* Don't unmap yet. If we're unable to allocate a new
2819 * page, we need to recycle the page and the DMA addr.
2820 */
2821 mapping_old = pci_unmap_addr(rx_pg, mapping);
1db82f2a
MC		 2822 if (i == pages - 1)
2823 frag_len -= 4;
2824
2825 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2826 rx_pg->page = NULL;
2827
bb4f98ab
MC		 2828 err = bnx2_alloc_rx_page(bp, rxr,
2829 RX_PG_RING_IDX(pg_prod));
1db82f2a 2830 if (unlikely(err)) {
bb4f98ab
MC		 2831 rxr->rx_pg_cons = pg_cons;
2832 rxr->rx_pg_prod = pg_prod;
2833 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
a1f60190 2834 pages - i);
1db82f2a
MC		 2835 return err;
2836 }
2837
3d16af86
BL		 2838 pci_unmap_page(bp->pdev, mapping_old,
2839 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2840
1db82f2a
MC		 2841 frag_size -= frag_len;
2842 skb->data_len += frag_len;
2843 skb->truesize += frag_len;
2844 skb->len += frag_len;
2845
2846 pg_prod = NEXT_RX_BD(pg_prod);
2847 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2848 }
bb4f98ab
MC		 2849 rxr->rx_pg_prod = pg_prod;
2850 rxr->rx_pg_cons = pg_cons;
1db82f2a 2851 }
85833c62
MC		 2852 return 0;
2853}
2854
c09c2627 2855static inline u16
35efa7c1 2856bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
c09c2627 2857{
bb4f98ab
MC		 2858 u16 cons;
2859
43e80b89
MC		 2860 /* Tell compiler that status block fields can change. */
2861 barrier();
2862 cons = *bnapi->hw_rx_cons_ptr;
c09c2627
MC		 2863 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2864 cons++;
2865 return cons;
2866}
2867
b6016b76 2868static int
35efa7c1 2869bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76 2870{
bb4f98ab 2871 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
b6016b76
MC		 2872 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2873 struct l2_fhdr *rx_hdr;
1db82f2a 2874 int rx_pkt = 0, pg_ring_used = 0;
b6016b76 2875
35efa7c1 2876 hw_cons = bnx2_get_hw_rx_cons(bnapi);
bb4f98ab
MC		 2877 sw_cons = rxr->rx_cons;
2878 sw_prod = rxr->rx_prod;
b6016b76
MC		 2879
2880 /* Memory barrier necessary as speculative reads of the rx
2881 * buffer can be ahead of the index in the status block
2882 */
2883 rmb();
2884 while (sw_cons != hw_cons) {
1db82f2a 2885 unsigned int len, hdr_len;
ade2bfe7 2886 u32 status;
b6016b76
MC		 2887 struct sw_bd *rx_buf;
2888 struct sk_buff *skb;
236b6394 2889 dma_addr_t dma_addr;
f22828e8
MC		 2890 u16 vtag = 0;
2891 int hw_vlan __maybe_unused = 0;
b6016b76
MC		 2892
2893 sw_ring_cons = RX_RING_IDX(sw_cons);
2894 sw_ring_prod = RX_RING_IDX(sw_prod);
2895
bb4f98ab 2896 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
b6016b76 2897 skb = rx_buf->skb;
236b6394
MC		 2898
2899 rx_buf->skb = NULL;
2900
2901 dma_addr = pci_unmap_addr(rx_buf, mapping);
2902
2903 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
601d3d18
BL		 2904 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
2905 PCI_DMA_FROMDEVICE);
b6016b76
MC		 2906
2907 rx_hdr = (struct l2_fhdr *) skb->data;
1db82f2a 2908 len = rx_hdr->l2_fhdr_pkt_len;
b6016b76 2909
ade2bfe7 2910 if ((status = rx_hdr->l2_fhdr_status) &
b6016b76
MC		 2911 (L2_FHDR_ERRORS_BAD_CRC |
2912 L2_FHDR_ERRORS_PHY_DECODE |
2913 L2_FHDR_ERRORS_ALIGNMENT |
2914 L2_FHDR_ERRORS_TOO_SHORT |
2915 L2_FHDR_ERRORS_GIANT_FRAME)) {
2916
bb4f98ab 2917 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
a1f60190 2918 sw_ring_prod);
85833c62 2919 goto next_rx;
b6016b76 2920 }
1db82f2a
MC		 2921 hdr_len = 0;
2922 if (status & L2_FHDR_STATUS_SPLIT) {
2923 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2924 pg_ring_used = 1;
2925 } else if (len > bp->rx_jumbo_thresh) {
2926 hdr_len = bp->rx_jumbo_thresh;
2927 pg_ring_used = 1;
2928 }
2929
2930 len -= 4;
b6016b76 2931
5d5d0015 2932 if (len <= bp->rx_copy_thresh) {
b6016b76
MC		 2933 struct sk_buff *new_skb;
2934
f22828e8 2935 new_skb = netdev_alloc_skb(bp->dev, len + 6);
85833c62 2936 if (new_skb == NULL) {
bb4f98ab 2937 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
85833c62
MC		 2938 sw_ring_prod);
2939 goto next_rx;
2940 }
b6016b76
MC		 2941
2942 /* aligned copy */
d89cb6af 2943 skb_copy_from_linear_data_offset(skb,
f22828e8
MC		 2944 BNX2_RX_OFFSET - 6,
2945 new_skb->data, len + 6);
2946 skb_reserve(new_skb, 6);
b6016b76 2947 skb_put(new_skb, len);
b6016b76 2948
bb4f98ab 2949 bnx2_reuse_rx_skb(bp, rxr, skb,
b6016b76
MC		 2950 sw_ring_cons, sw_ring_prod);
2951
2952 skb = new_skb;
bb4f98ab 2953 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
a1f60190 2954 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
b6016b76 2955 goto next_rx;
b6016b76 2956
f22828e8
MC		 2957 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
2958 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
2959 vtag = rx_hdr->l2_fhdr_vlan_tag;
2960#ifdef BCM_VLAN
2961 if (bp->vlgrp)
2962 hw_vlan = 1;
2963 else
2964#endif
2965 {
2966 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
2967 __skb_push(skb, 4);
2968
2969 memmove(ve, skb->data + 4, ETH_ALEN * 2);
2970 ve->h_vlan_proto = htons(ETH_P_8021Q);
2971 ve->h_vlan_TCI = htons(vtag);
2972 len += 4;
2973 }
2974 }
2975
b6016b76
MC		 2976 skb->protocol = eth_type_trans(skb, bp->dev);
2977
2978 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
d1e100ba 2979 (ntohs(skb->protocol) != 0x8100)) {
b6016b76 2980
745720e5 2981 dev_kfree_skb(skb);
b6016b76
MC		 2982 goto next_rx;
2983
2984 }
2985
b6016b76
MC		 2986 skb->ip_summed = CHECKSUM_NONE;
2987 if (bp->rx_csum &&
2988 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2989 L2_FHDR_STATUS_UDP_DATAGRAM))) {
2990
ade2bfe7
MC		 2991 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2992 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
b6016b76
MC		 2993 skb->ip_summed = CHECKSUM_UNNECESSARY;
2994 }
2995
2996#ifdef BCM_VLAN
f22828e8
MC		 2997 if (hw_vlan)
2998 vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
b6016b76
MC		 2999 else
3000#endif
3001 netif_receive_skb(skb);
3002
b6016b76
MC		 3003 rx_pkt++;
3004
3005next_rx:
b6016b76
MC		 3006 sw_cons = NEXT_RX_BD(sw_cons);
3007 sw_prod = NEXT_RX_BD(sw_prod);
3008
3009 if ((rx_pkt == budget))
3010 break;
f4e418f7
MC		 3011
3012 /* Refresh hw_cons to see if there is new work */
3013 if (sw_cons == hw_cons) {
35efa7c1 3014 hw_cons = bnx2_get_hw_rx_cons(bnapi);
f4e418f7
MC		 3015 rmb();
3016 }
b6016b76 3017 }
bb4f98ab
MC		 3018 rxr->rx_cons = sw_cons;
3019 rxr->rx_prod = sw_prod;
b6016b76 3020
1db82f2a 3021 if (pg_ring_used)
bb4f98ab 3022 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
1db82f2a 3023
bb4f98ab 3024 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
b6016b76 3025
bb4f98ab 3026 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
b6016b76
MC		 3027
3028 mmiowb();
3029
3030 return rx_pkt;
3031
3032}
3033
3034/* MSI ISR - The only difference between this and the INTx ISR
3035 * is that the MSI interrupt is always serviced.
3036 */
3037static irqreturn_t
7d12e780 3038bnx2_msi(int irq, void *dev_instance)
b6016b76 3039{
f0ea2e63
MC		 3040 struct bnx2_napi *bnapi = dev_instance;
3041 struct bnx2 *bp = bnapi->bp;
3042 struct net_device *dev = bp->dev;
b6016b76 3043
43e80b89 3044 prefetch(bnapi->status_blk.msi);
b6016b76
MC		 3045 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3046 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3047 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3048
3049 /* Return here if interrupt is disabled. */
73eef4cd
MC		 3050 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3051 return IRQ_HANDLED;
b6016b76 3052
35efa7c1 3053 netif_rx_schedule(dev, &bnapi->napi);
b6016b76 3054
73eef4cd 3055 return IRQ_HANDLED;
b6016b76
MC		 3056}
3057
8e6a72c4
MC		 3058static irqreturn_t
3059bnx2_msi_1shot(int irq, void *dev_instance)
3060{
f0ea2e63
MC		 3061 struct bnx2_napi *bnapi = dev_instance;
3062 struct bnx2 *bp = bnapi->bp;
3063 struct net_device *dev = bp->dev;
8e6a72c4 3064
43e80b89 3065 prefetch(bnapi->status_blk.msi);
8e6a72c4
MC		 3066
3067 /* Return here if interrupt is disabled. */
3068 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3069 return IRQ_HANDLED;
3070
35efa7c1 3071 netif_rx_schedule(dev, &bnapi->napi);
8e6a72c4
MC		 3072
3073 return IRQ_HANDLED;
3074}
3075
b6016b76 3076static irqreturn_t
7d12e780 3077bnx2_interrupt(int irq, void *dev_instance)
b6016b76 3078{
f0ea2e63
MC		 3079 struct bnx2_napi *bnapi = dev_instance;
3080 struct bnx2 *bp = bnapi->bp;
3081 struct net_device *dev = bp->dev;
43e80b89 3082 struct status_block *sblk = bnapi->status_blk.msi;
b6016b76
MC		 3083
3084 /* When using INTx, it is possible for the interrupt to arrive
3085 * at the CPU before the status block posted prior to the
3086 * interrupt. Reading a register will flush the status block.
3087 * When using MSI, the MSI message will always complete after
3088 * the status block write.
3089 */
35efa7c1 3090 if ((sblk->status_idx == bnapi->last_status_idx) &&
b6016b76
MC		 3091 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3092 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
73eef4cd 3093 return IRQ_NONE;
b6016b76
MC		 3094
3095 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3096 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3097 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3098
b8a7ce7b
MC		 3099 /* Read back to deassert IRQ immediately to avoid too many
3100 * spurious interrupts.
3101 */
3102 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3103
b6016b76 3104 /* Return here if interrupt is shared and is disabled. */
73eef4cd
MC		 3105 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3106 return IRQ_HANDLED;
b6016b76 3107
35efa7c1
MC		 3108 if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
3109 bnapi->last_status_idx = sblk->status_idx;
3110 __netif_rx_schedule(dev, &bnapi->napi);
b8a7ce7b 3111 }
b6016b76 3112
73eef4cd 3113 return IRQ_HANDLED;
b6016b76
MC		 3114}
3115
f4e418f7 3116static inline int
43e80b89 3117bnx2_has_fast_work(struct bnx2_napi *bnapi)
f4e418f7 3118{
35e9010b 3119 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
bb4f98ab 3120 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
f4e418f7 3121
bb4f98ab 3122 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
35e9010b 3123 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
f4e418f7 3124 return 1;
43e80b89
MC		 3125 return 0;
3126}
3127
3128#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3129 STATUS_ATTN_BITS_TIMER_ABORT)
3130
3131static inline int
3132bnx2_has_work(struct bnx2_napi *bnapi)
3133{
3134 struct status_block *sblk = bnapi->status_blk.msi;
3135
3136 if (bnx2_has_fast_work(bnapi))
3137 return 1;
f4e418f7 3138
da3e4fbe
MC		 3139 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3140 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
f4e418f7
MC		 3141 return 1;
3142
3143 return 0;
3144}
3145
43e80b89 3146static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
b6016b76 3147{
43e80b89 3148 struct status_block *sblk = bnapi->status_blk.msi;
da3e4fbe
MC		 3149 u32 status_attn_bits = sblk->status_attn_bits;
3150 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
b6016b76 3151
da3e4fbe
MC		 3152 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3153 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
b6016b76 3154
35efa7c1 3155 bnx2_phy_int(bp, bnapi);
bf5295bb
MC		 3156
3157 /* This is needed to take care of transient status
3158 * during link changes.
3159 */
3160 REG_WR(bp, BNX2_HC_COMMAND,
3161 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3162 REG_RD(bp, BNX2_HC_COMMAND);
b6016b76 3163 }
43e80b89
MC		 3164}
3165
3166static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3167 int work_done, int budget)
3168{
3169 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3170 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
b6016b76 3171
35e9010b 3172 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
57851d84 3173 bnx2_tx_int(bp, bnapi, 0);
b6016b76 3174
bb4f98ab 3175 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
35efa7c1 3176 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
6aa20a22 3177
6f535763
DM		 3178 return work_done;
3179}
3180
f0ea2e63
MC		 3181static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3182{
3183 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3184 struct bnx2 *bp = bnapi->bp;
3185 int work_done = 0;
3186 struct status_block_msix *sblk = bnapi->status_blk.msix;
3187
3188 while (1) {
3189 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3190 if (unlikely(work_done >= budget))
3191 break;
3192
3193 bnapi->last_status_idx = sblk->status_idx;
3194 /* status idx must be read before checking for more work. */
3195 rmb();
3196 if (likely(!bnx2_has_fast_work(bnapi))) {
3197
3198 netif_rx_complete(bp->dev, napi);
3199 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3200 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3201 bnapi->last_status_idx);
3202 break;
3203 }
3204 }
3205 return work_done;
3206}
3207
6f535763
DM		 3208static int bnx2_poll(struct napi_struct *napi, int budget)
3209{
35efa7c1
MC		 3210 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3211 struct bnx2 *bp = bnapi->bp;
6f535763 3212 int work_done = 0;
43e80b89 3213 struct status_block *sblk = bnapi->status_blk.msi;
6f535763
DM		 3214
3215 while (1) {
43e80b89
MC		 3216 bnx2_poll_link(bp, bnapi);
3217
35efa7c1 3218 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
f4e418f7 3219
6f535763
DM		 3220 if (unlikely(work_done >= budget))
3221 break;
3222
35efa7c1 3223 /* bnapi->last_status_idx is used below to tell the hw how
6dee6421
MC		 3224 * much work has been processed, so we must read it before
3225 * checking for more work.
3226 */
35efa7c1 3227 bnapi->last_status_idx = sblk->status_idx;
6dee6421 3228 rmb();
35efa7c1 3229 if (likely(!bnx2_has_work(bnapi))) {
6f535763 3230 netif_rx_complete(bp->dev, napi);
f86e82fb 3231 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
6f535763
DM		 3232 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3233 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3234 bnapi->last_status_idx);
6dee6421 3235 break;
6f535763 3236 }
1269a8a6
MC		 3237 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3238 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
6f535763 3239 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
35efa7c1 3240 bnapi->last_status_idx);
1269a8a6 3241
6f535763
DM		 3242 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3243 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3244 bnapi->last_status_idx);
6f535763
DM		 3245 break;
3246 }
b6016b76
MC		 3247 }
3248
bea3348e 3249 return work_done;
b6016b76
MC		 3250}
3251
932ff279 3252/* Called with rtnl_lock from vlan functions and also netif_tx_lock
b6016b76
MC		 3253 * from set_multicast.
3254 */
3255static void
3256bnx2_set_rx_mode(struct net_device *dev)
3257{
972ec0d4 3258 struct bnx2 *bp = netdev_priv(dev);
b6016b76 3259 u32 rx_mode, sort_mode;
5fcaed01 3260 struct dev_addr_list *uc_ptr;
b6016b76 3261 int i;
b6016b76 3262
9f52b564
MC		 3263 if (!netif_running(dev))
3264 return;
3265
c770a65c 3266 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 3267
3268 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3269 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3270 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3271#ifdef BCM_VLAN
7c6337a1 3272 if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
b6016b76 3273 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76 3274#else
7c6337a1 3275 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
e29054f9 3276 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76
MC		 3277#endif
3278 if (dev->flags & IFF_PROMISC) {
3279 /* Promiscuous mode. */
3280 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
7510873d
MC		 3281 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3282 BNX2_RPM_SORT_USER0_PROM_VLAN;
b6016b76
MC		 3283 }
3284 else if (dev->flags & IFF_ALLMULTI) {
3285 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3286 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3287 0xffffffff);
3288 }
3289 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3290 }
3291 else {
3292 /* Accept one or more multicast(s). */
3293 struct dev_mc_list *mclist;
3294 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3295 u32 regidx;
3296 u32 bit;
3297 u32 crc;
3298
3299 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3300
3301 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3302 i++, mclist = mclist->next) {
3303
3304 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3305 bit = crc & 0xff;
3306 regidx = (bit & 0xe0) >> 5;
3307 bit &= 0x1f;
3308 mc_filter[regidx] |= (1 << bit);
3309 }
3310
3311 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3312 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3313 mc_filter[i]);
3314 }
3315
3316 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3317 }
3318
5fcaed01
BL		 3319 uc_ptr = NULL;
3320 if (dev->uc_count > BNX2_MAX_UNICAST_ADDRESSES) {
3321 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3322 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3323 BNX2_RPM_SORT_USER0_PROM_VLAN;
3324 } else if (!(dev->flags & IFF_PROMISC)) {
3325 uc_ptr = dev->uc_list;
3326
3327 /* Add all entries into to the match filter list */
3328 for (i = 0; i < dev->uc_count; i++) {
3329 bnx2_set_mac_addr(bp, uc_ptr->da_addr,
3330 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3331 sort_mode |= (1 <<
3332 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3333 uc_ptr = uc_ptr->next;
3334 }
3335
3336 }
3337
b6016b76
MC		 3338 if (rx_mode != bp->rx_mode) {
3339 bp->rx_mode = rx_mode;
3340 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3341 }
3342
3343 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3344 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3345 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3346
c770a65c 3347 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3348}
3349
3350static void
b491edd5 3351load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
b6016b76
MC		 3352 u32 rv2p_proc)
3353{
3354 int i;
3355 u32 val;
3356
d25be1d3
MC		 3357 if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {
3358 val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);
3359 val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;
3360 val |= XI_RV2P_PROC2_BD_PAGE_SIZE;
3361 rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);
3362 }
b6016b76
MC		 3363
3364 for (i = 0; i < rv2p_code_len; i += 8) {
b491edd5 3365 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
b6016b76 3366 rv2p_code++;
b491edd5 3367 REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
b6016b76
MC		 3368 rv2p_code++;
3369
3370 if (rv2p_proc == RV2P_PROC1) {
3371 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3372 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3373 }
3374 else {
3375 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3376 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3377 }
3378 }
3379
3380 /* Reset the processor, un-stall is done later. */
3381 if (rv2p_proc == RV2P_PROC1) {
3382 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3383 }
3384 else {
3385 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3386 }
3387}
3388
af3ee519 3389static int
10343cca 3390load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw)
b6016b76
MC		 3391{
3392 u32 offset;
3393 u32 val;
af3ee519 3394 int rc;
b6016b76
MC		 3395
3396 /* Halt the CPU. */
2726d6e1 3397 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3398 val |= cpu_reg->mode_value_halt;
2726d6e1
MC		 3399 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3400 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
b6016b76
MC		 3401
3402 /* Load the Text area. */
3403 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
af3ee519 3404 if (fw->gz_text) {
b6016b76
MC		 3405 int j;
3406
ea1f8d5c
MC		 3407 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3408 fw->gz_text_len);
3409 if (rc < 0)
b3448b0b 3410 return rc;
ea1f8d5c 3411
b6016b76 3412 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2726d6e1 3413 bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
b6016b76
MC		 3414 }
3415 }
3416
3417 /* Load the Data area. */
3418 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3419 if (fw->data) {
3420 int j;
3421
3422 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2726d6e1 3423 bnx2_reg_wr_ind(bp, offset, fw->data[j]);
b6016b76
MC		 3424 }
3425 }
3426
3427 /* Load the SBSS area. */
3428 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
ea1f8d5c 3429 if (fw->sbss_len) {
b6016b76
MC		 3430 int j;
3431
3432 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2726d6e1 3433 bnx2_reg_wr_ind(bp, offset, 0);
b6016b76
MC		 3434 }
3435 }
3436
3437 /* Load the BSS area. */
3438 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
ea1f8d5c 3439 if (fw->bss_len) {
b6016b76
MC		 3440 int j;
3441
3442 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2726d6e1 3443 bnx2_reg_wr_ind(bp, offset, 0);
b6016b76
MC		 3444 }
3445 }
3446
3447 /* Load the Read-Only area. */
3448 offset = cpu_reg->spad_base +
3449 (fw->rodata_addr - cpu_reg->mips_view_base);
3450 if (fw->rodata) {
3451 int j;
3452
3453 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2726d6e1 3454 bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
b6016b76
MC		 3455 }
3456 }
3457
3458 /* Clear the pre-fetch instruction. */
2726d6e1
MC		 3459 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3460 bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
b6016b76
MC		 3461
3462 /* Start the CPU. */
2726d6e1 3463 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3464 val &= ~cpu_reg->mode_value_halt;
2726d6e1
MC		 3465 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3466 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
af3ee519
MC		 3467
3468 return 0;
b6016b76
MC		 3469}
3470
fba9fe91 3471static int
b6016b76
MC		 3472bnx2_init_cpus(struct bnx2 *bp)
3473{
af3ee519 3474 struct fw_info *fw;
110d0ef9
MC		 3475 int rc, rv2p_len;
3476 void *text, *rv2p;
b6016b76
MC		 3477
3478 /* Initialize the RV2P processor. */
b3448b0b
DV		 3479 text = vmalloc(FW_BUF_SIZE);
3480 if (!text)
3481 return -ENOMEM;
110d0ef9
MC		 3482 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3483 rv2p = bnx2_xi_rv2p_proc1;
3484 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3485 } else {
3486 rv2p = bnx2_rv2p_proc1;
3487 rv2p_len = sizeof(bnx2_rv2p_proc1);
3488 }
3489 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
ea1f8d5c 3490 if (rc < 0)
fba9fe91 3491 goto init_cpu_err;
ea1f8d5c 3492
b3448b0b 3493 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
fba9fe91 3494
110d0ef9
MC		 3495 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3496 rv2p = bnx2_xi_rv2p_proc2;
3497 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3498 } else {
3499 rv2p = bnx2_rv2p_proc2;
3500 rv2p_len = sizeof(bnx2_rv2p_proc2);
3501 }
3502 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
ea1f8d5c 3503 if (rc < 0)
fba9fe91 3504 goto init_cpu_err;
ea1f8d5c 3505
b3448b0b 3506 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
b6016b76
MC		 3507
3508 /* Initialize the RX Processor. */
d43584c8
MC		 3509 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3510 fw = &bnx2_rxp_fw_09;
3511 else
3512 fw = &bnx2_rxp_fw_06;
fba9fe91 3513
ea1f8d5c 3514 fw->text = text;
10343cca 3515 rc = load_cpu_fw(bp, &cpu_reg_rxp, fw);
fba9fe91
MC		 3516 if (rc)
3517 goto init_cpu_err;
3518
b6016b76 3519 /* Initialize the TX Processor. */
d43584c8
MC		 3520 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3521 fw = &bnx2_txp_fw_09;
3522 else
3523 fw = &bnx2_txp_fw_06;
fba9fe91 3524
ea1f8d5c 3525 fw->text = text;
10343cca 3526 rc = load_cpu_fw(bp, &cpu_reg_txp, fw);
fba9fe91
MC		 3527 if (rc)
3528 goto init_cpu_err;
3529
b6016b76 3530 /* Initialize the TX Patch-up Processor. */
d43584c8
MC		 3531 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3532 fw = &bnx2_tpat_fw_09;
3533 else
3534 fw = &bnx2_tpat_fw_06;
fba9fe91 3535
ea1f8d5c 3536 fw->text = text;
10343cca 3537 rc = load_cpu_fw(bp, &cpu_reg_tpat, fw);
fba9fe91
MC		 3538 if (rc)
3539 goto init_cpu_err;
3540
b6016b76 3541 /* Initialize the Completion Processor. */
d43584c8
MC		 3542 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3543 fw = &bnx2_com_fw_09;
3544 else
3545 fw = &bnx2_com_fw_06;
fba9fe91 3546
ea1f8d5c 3547 fw->text = text;
10343cca 3548 rc = load_cpu_fw(bp, &cpu_reg_com, fw);
fba9fe91
MC		 3549 if (rc)
3550 goto init_cpu_err;
3551
d43584c8 3552 /* Initialize the Command Processor. */
110d0ef9 3553 if (CHIP_NUM(bp) == CHIP_NUM_5709)
d43584c8 3554 fw = &bnx2_cp_fw_09;
110d0ef9
MC		 3555 else
3556 fw = &bnx2_cp_fw_06;
3557
3558 fw->text = text;
10343cca 3559 rc = load_cpu_fw(bp, &cpu_reg_cp, fw);
b6016b76 3560
fba9fe91 3561init_cpu_err:
ea1f8d5c 3562 vfree(text);
fba9fe91 3563 return rc;
b6016b76
MC		 3564}
3565
3566static int
829ca9a3 3567bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
b6016b76
MC		 3568{
3569 u16 pmcsr;
3570
3571 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3572
3573 switch (state) {
829ca9a3 3574 case PCI_D0: {
b6016b76
MC		 3575 u32 val;
3576
3577 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3578 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3579 PCI_PM_CTRL_PME_STATUS);
3580
3581 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3582 /* delay required during transition out of D3hot */
3583 msleep(20);
3584
3585 val = REG_RD(bp, BNX2_EMAC_MODE);
3586 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3587 val &= ~BNX2_EMAC_MODE_MPKT;
3588 REG_WR(bp, BNX2_EMAC_MODE, val);
3589
3590 val = REG_RD(bp, BNX2_RPM_CONFIG);
3591 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3592 REG_WR(bp, BNX2_RPM_CONFIG, val);
3593 break;
3594 }
829ca9a3 3595 case PCI_D3hot: {
b6016b76
MC		 3596 int i;
3597 u32 val, wol_msg;
3598
3599 if (bp->wol) {
3600 u32 advertising;
3601 u8 autoneg;
3602
3603 autoneg = bp->autoneg;
3604 advertising = bp->advertising;
3605
239cd343
MC		 3606 if (bp->phy_port == PORT_TP) {
3607 bp->autoneg = AUTONEG_SPEED;
3608 bp->advertising = ADVERTISED_10baseT_Half |
3609 ADVERTISED_10baseT_Full |
3610 ADVERTISED_100baseT_Half |
3611 ADVERTISED_100baseT_Full |
3612 ADVERTISED_Autoneg;
3613 }
b6016b76 3614
239cd343
MC		 3615 spin_lock_bh(&bp->phy_lock);
3616 bnx2_setup_phy(bp, bp->phy_port);
3617 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3618
3619 bp->autoneg = autoneg;
3620 bp->advertising = advertising;
3621
5fcaed01 3622 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 3623
3624 val = REG_RD(bp, BNX2_EMAC_MODE);
3625
3626 /* Enable port mode. */
3627 val &= ~BNX2_EMAC_MODE_PORT;
239cd343 3628 val |= BNX2_EMAC_MODE_MPKT_RCVD |
b6016b76 3629 BNX2_EMAC_MODE_ACPI_RCVD |
b6016b76 3630 BNX2_EMAC_MODE_MPKT;
239cd343
MC		 3631 if (bp->phy_port == PORT_TP)
3632 val |= BNX2_EMAC_MODE_PORT_MII;
3633 else {
3634 val |= BNX2_EMAC_MODE_PORT_GMII;
3635 if (bp->line_speed == SPEED_2500)
3636 val |= BNX2_EMAC_MODE_25G_MODE;
3637 }
b6016b76
MC		 3638
3639 REG_WR(bp, BNX2_EMAC_MODE, val);
3640
3641 /* receive all multicast */
3642 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3643 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3644 0xffffffff);
3645 }
3646 REG_WR(bp, BNX2_EMAC_RX_MODE,
3647 BNX2_EMAC_RX_MODE_SORT_MODE);
3648
3649 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3650 BNX2_RPM_SORT_USER0_MC_EN;
3651 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3652 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3653 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3654 BNX2_RPM_SORT_USER0_ENA);
3655
3656 /* Need to enable EMAC and RPM for WOL. */
3657 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3658 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3659 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3660 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3661
3662 val = REG_RD(bp, BNX2_RPM_CONFIG);
3663 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3664 REG_WR(bp, BNX2_RPM_CONFIG, val);
3665
3666 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3667 }
3668 else {
3669 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3670 }
3671
f86e82fb 3672 if (!(bp->flags & BNX2_FLAG_NO_WOL))
a2f13890
MC		 3673 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3674 1, 0);
b6016b76
MC		 3675
3676 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3677 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3678 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3679
3680 if (bp->wol)
3681 pmcsr |= 3;
3682 }
3683 else {
3684 pmcsr |= 3;
3685 }
3686 if (bp->wol) {
3687 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3688 }
3689 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3690 pmcsr);
3691
3692 /* No more memory access after this point until
3693 * device is brought back to D0.
3694 */
3695 udelay(50);
3696 break;
3697 }
3698 default:
3699 return -EINVAL;
3700 }
3701 return 0;
3702}
3703
3704static int
3705bnx2_acquire_nvram_lock(struct bnx2 *bp)
3706{
3707 u32 val;
3708 int j;
3709
3710 /* Request access to the flash interface. */
3711 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3712 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3713 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3714 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3715 break;
3716
3717 udelay(5);
3718 }
3719
3720 if (j >= NVRAM_TIMEOUT_COUNT)
3721 return -EBUSY;
3722
3723 return 0;
3724}
3725
3726static int
3727bnx2_release_nvram_lock(struct bnx2 *bp)
3728{
3729 int j;
3730 u32 val;
3731
3732 /* Relinquish nvram interface. */
3733 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3734
3735 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3736 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3737 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3738 break;
3739
3740 udelay(5);
3741 }
3742
3743 if (j >= NVRAM_TIMEOUT_COUNT)
3744 return -EBUSY;
3745
3746 return 0;
3747}
3748
3749
3750static int
3751bnx2_enable_nvram_write(struct bnx2 *bp)
3752{
3753 u32 val;
3754
3755 val = REG_RD(bp, BNX2_MISC_CFG);
3756 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3757
e30372c9 3758 if (bp->flash_info->flags & BNX2_NV_WREN) {
b6016b76
MC		 3759 int j;
3760
3761 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3762 REG_WR(bp, BNX2_NVM_COMMAND,
3763 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3764
3765 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3766 udelay(5);
3767
3768 val = REG_RD(bp, BNX2_NVM_COMMAND);
3769 if (val & BNX2_NVM_COMMAND_DONE)
3770 break;
3771 }
3772
3773 if (j >= NVRAM_TIMEOUT_COUNT)
3774 return -EBUSY;
3775 }
3776 return 0;
3777}
3778
3779static void
3780bnx2_disable_nvram_write(struct bnx2 *bp)
3781{
3782 u32 val;
3783
3784 val = REG_RD(bp, BNX2_MISC_CFG);
3785 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3786}
3787
3788
3789static void
3790bnx2_enable_nvram_access(struct bnx2 *bp)
3791{
3792 u32 val;
3793
3794 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3795 /* Enable both bits, even on read. */
6aa20a22 3796 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 3797 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3798}
3799
3800static void
3801bnx2_disable_nvram_access(struct bnx2 *bp)
3802{
3803 u32 val;
3804
3805 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3806 /* Disable both bits, even after read. */
6aa20a22 3807 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 3808 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3809 BNX2_NVM_ACCESS_ENABLE_WR_EN));
3810}
3811
3812static int
3813bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3814{
3815 u32 cmd;
3816 int j;
3817
e30372c9 3818 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
b6016b76
MC		 3819 /* Buffered flash, no erase needed */
3820 return 0;
3821
3822 /* Build an erase command */
3823 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3824 BNX2_NVM_COMMAND_DOIT;
3825
3826 /* Need to clear DONE bit separately. */
3827 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3828
3829 /* Address of the NVRAM to read from. */
3830 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3831
3832 /* Issue an erase command. */
3833 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3834
3835 /* Wait for completion. */
3836 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3837 u32 val;
3838
3839 udelay(5);
3840
3841 val = REG_RD(bp, BNX2_NVM_COMMAND);
3842 if (val & BNX2_NVM_COMMAND_DONE)
3843 break;
3844 }
3845
3846 if (j >= NVRAM_TIMEOUT_COUNT)
3847 return -EBUSY;
3848
3849 return 0;
3850}
3851
3852static int
3853bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3854{
3855 u32 cmd;
3856 int j;
3857
3858 /* Build the command word. */
3859 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3860
e30372c9
MC		 3861 /* Calculate an offset of a buffered flash, not needed for 5709. */
3862 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 3863 offset = ((offset / bp->flash_info->page_size) <<
3864 bp->flash_info->page_bits) +
3865 (offset % bp->flash_info->page_size);
3866 }
3867
3868 /* Need to clear DONE bit separately. */
3869 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3870
3871 /* Address of the NVRAM to read from. */
3872 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3873
3874 /* Issue a read command. */
3875 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3876
3877 /* Wait for completion. */
3878 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3879 u32 val;
3880
3881 udelay(5);
3882
3883 val = REG_RD(bp, BNX2_NVM_COMMAND);
3884 if (val & BNX2_NVM_COMMAND_DONE) {
b491edd5
AV		 3885 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3886 memcpy(ret_val, &v, 4);
b6016b76
MC		 3887 break;
3888 }
3889 }
3890 if (j >= NVRAM_TIMEOUT_COUNT)
3891 return -EBUSY;
3892
3893 return 0;
3894}
3895
3896
3897static int
3898bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3899{
b491edd5
AV		 3900 u32 cmd;
3901 __be32 val32;
b6016b76
MC		 3902 int j;
3903
3904 /* Build the command word. */
3905 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3906
e30372c9
MC		 3907 /* Calculate an offset of a buffered flash, not needed for 5709. */
3908 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 3909 offset = ((offset / bp->flash_info->page_size) <<
3910 bp->flash_info->page_bits) +
3911 (offset % bp->flash_info->page_size);
3912 }
3913
3914 /* Need to clear DONE bit separately. */
3915 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3916
3917 memcpy(&val32, val, 4);
b6016b76
MC		 3918
3919 /* Write the data. */
b491edd5 3920 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
b6016b76
MC		 3921
3922 /* Address of the NVRAM to write to. */
3923 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3924
3925 /* Issue the write command. */
3926 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3927
3928 /* Wait for completion. */
3929 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3930 udelay(5);
3931
3932 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3933 break;
3934 }
3935 if (j >= NVRAM_TIMEOUT_COUNT)
3936 return -EBUSY;
3937
3938 return 0;
3939}
3940
3941static int
3942bnx2_init_nvram(struct bnx2 *bp)
3943{
3944 u32 val;
e30372c9 3945 int j, entry_count, rc = 0;
b6016b76
MC		 3946 struct flash_spec *flash;
3947
e30372c9
MC		 3948 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3949 bp->flash_info = &flash_5709;
3950 goto get_flash_size;
3951 }
3952
b6016b76
MC		 3953 /* Determine the selected interface. */
3954 val = REG_RD(bp, BNX2_NVM_CFG1);
3955
ff8ac609 3956 entry_count = ARRAY_SIZE(flash_table);
b6016b76 3957
b6016b76
MC		 3958 if (val & 0x40000000) {
3959
3960 /* Flash interface has been reconfigured */
3961 for (j = 0, flash = &flash_table[0]; j < entry_count;
37137709
MC		 3962 j++, flash++) {
3963 if ((val & FLASH_BACKUP_STRAP_MASK) ==
3964 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
b6016b76
MC		 3965 bp->flash_info = flash;
3966 break;
3967 }
3968 }
3969 }
3970 else {
37137709 3971 u32 mask;
b6016b76
MC		 3972 /* Not yet been reconfigured */
3973
37137709
MC		 3974 if (val & (1 << 23))
3975 mask = FLASH_BACKUP_STRAP_MASK;
3976 else
3977 mask = FLASH_STRAP_MASK;
3978
b6016b76
MC		 3979 for (j = 0, flash = &flash_table[0]; j < entry_count;
3980 j++, flash++) {
3981
37137709 3982 if ((val & mask) == (flash->strapping & mask)) {
b6016b76
MC		 3983 bp->flash_info = flash;
3984
3985 /* Request access to the flash interface. */
3986 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3987 return rc;
3988
3989 /* Enable access to flash interface */
3990 bnx2_enable_nvram_access(bp);
3991
3992 /* Reconfigure the flash interface */
3993 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3994 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3995 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3996 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3997
3998 /* Disable access to flash interface */
3999 bnx2_disable_nvram_access(bp);
4000 bnx2_release_nvram_lock(bp);
4001
4002 break;
4003 }
4004 }
4005 } /* if (val & 0x40000000) */
4006
4007 if (j == entry_count) {
4008 bp->flash_info = NULL;
2f23c523 4009 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
1122db71 4010 return -ENODEV;
b6016b76
MC		 4011 }
4012
e30372c9 4013get_flash_size:
2726d6e1 4014 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
1122db71
MC		 4015 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4016 if (val)
4017 bp->flash_size = val;
4018 else
4019 bp->flash_size = bp->flash_info->total_size;
4020
b6016b76
MC		 4021 return rc;
4022}
4023
4024static int
4025bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4026 int buf_size)
4027{
4028 int rc = 0;
4029 u32 cmd_flags, offset32, len32, extra;
4030
4031 if (buf_size == 0)
4032 return 0;
4033
4034 /* Request access to the flash interface. */
4035 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4036 return rc;
4037
4038 /* Enable access to flash interface */
4039 bnx2_enable_nvram_access(bp);
4040
4041 len32 = buf_size;
4042 offset32 = offset;
4043 extra = 0;
4044
4045 cmd_flags = 0;
4046
4047 if (offset32 & 3) {
4048 u8 buf[4];
4049 u32 pre_len;
4050
4051 offset32 &= ~3;
4052 pre_len = 4 - (offset & 3);
4053
4054 if (pre_len >= len32) {
4055 pre_len = len32;
4056 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4057 BNX2_NVM_COMMAND_LAST;
4058 }
4059 else {
4060 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4061 }
4062
4063 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4064
4065 if (rc)
4066 return rc;
4067
4068 memcpy(ret_buf, buf + (offset & 3), pre_len);
4069
4070 offset32 += 4;
4071 ret_buf += pre_len;
4072 len32 -= pre_len;
4073 }
4074 if (len32 & 3) {
4075 extra = 4 - (len32 & 3);
4076 len32 = (len32 + 4) & ~3;
4077 }
4078
4079 if (len32 == 4) {
4080 u8 buf[4];
4081
4082 if (cmd_flags)
4083 cmd_flags = BNX2_NVM_COMMAND_LAST;
4084 else
4085 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4086 BNX2_NVM_COMMAND_LAST;
4087
4088 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4089
4090 memcpy(ret_buf, buf, 4 - extra);
4091 }
4092 else if (len32 > 0) {
4093 u8 buf[4];
4094
4095 /* Read the first word. */
4096 if (cmd_flags)
4097 cmd_flags = 0;
4098 else
4099 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4100
4101 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4102
4103 /* Advance to the next dword. */
4104 offset32 += 4;
4105 ret_buf += 4;
4106 len32 -= 4;
4107
4108 while (len32 > 4 && rc == 0) {
4109 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4110
4111 /* Advance to the next dword. */
4112 offset32 += 4;
4113 ret_buf += 4;
4114 len32 -= 4;
4115 }
4116
4117 if (rc)
4118 return rc;
4119
4120 cmd_flags = BNX2_NVM_COMMAND_LAST;
4121 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4122
4123 memcpy(ret_buf, buf, 4 - extra);
4124 }
4125
4126 /* Disable access to flash interface */
4127 bnx2_disable_nvram_access(bp);
4128
4129 bnx2_release_nvram_lock(bp);
4130
4131 return rc;
4132}
4133
4134static int
4135bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4136 int buf_size)
4137{
4138 u32 written, offset32, len32;
e6be763f 4139 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
b6016b76
MC		 4140 int rc = 0;
4141 int align_start, align_end;
4142
4143 buf = data_buf;
4144 offset32 = offset;
4145 len32 = buf_size;
4146 align_start = align_end = 0;
4147
4148 if ((align_start = (offset32 & 3))) {
4149 offset32 &= ~3;
c873879c
MC		 4150 len32 += align_start;
4151 if (len32 < 4)
4152 len32 = 4;
b6016b76
MC		 4153 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4154 return rc;
4155 }
4156
4157 if (len32 & 3) {
c873879c
MC		 4158 align_end = 4 - (len32 & 3);
4159 len32 += align_end;
4160 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4161 return rc;
b6016b76
MC		 4162 }
4163
4164 if (align_start || align_end) {
e6be763f
MC		 4165 align_buf = kmalloc(len32, GFP_KERNEL);
4166 if (align_buf == NULL)
b6016b76
MC		 4167 return -ENOMEM;
4168 if (align_start) {
e6be763f 4169 memcpy(align_buf, start, 4);
b6016b76
MC		 4170 }
4171 if (align_end) {
e6be763f 4172 memcpy(align_buf + len32 - 4, end, 4);
b6016b76 4173 }
e6be763f
MC		 4174 memcpy(align_buf + align_start, data_buf, buf_size);
4175 buf = align_buf;
b6016b76
MC		 4176 }
4177
e30372c9 4178 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
ae181bc4
MC		 4179 flash_buffer = kmalloc(264, GFP_KERNEL);
4180 if (flash_buffer == NULL) {
4181 rc = -ENOMEM;
4182 goto nvram_write_end;
4183 }
4184 }
4185
b6016b76
MC		 4186 written = 0;
4187 while ((written < len32) && (rc == 0)) {
4188 u32 page_start, page_end, data_start, data_end;
4189 u32 addr, cmd_flags;
4190 int i;
b6016b76
MC		 4191
4192 /* Find the page_start addr */
4193 page_start = offset32 + written;
4194 page_start -= (page_start % bp->flash_info->page_size);
4195 /* Find the page_end addr */
4196 page_end = page_start + bp->flash_info->page_size;
4197 /* Find the data_start addr */
4198 data_start = (written == 0) ? offset32 : page_start;
4199 /* Find the data_end addr */
6aa20a22 4200 data_end = (page_end > offset32 + len32) ?
b6016b76
MC		 4201 (offset32 + len32) : page_end;
4202
4203 /* Request access to the flash interface. */
4204 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4205 goto nvram_write_end;
4206
4207 /* Enable access to flash interface */
4208 bnx2_enable_nvram_access(bp);
4209
4210 cmd_flags = BNX2_NVM_COMMAND_FIRST;
e30372c9 4211 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4212 int j;
4213
4214 /* Read the whole page into the buffer
4215 * (non-buffer flash only) */
4216 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4217 if (j == (bp->flash_info->page_size - 4)) {
4218 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4219 }
4220 rc = bnx2_nvram_read_dword(bp,
6aa20a22
JG		 4221 page_start + j,
4222 &flash_buffer[j],
b6016b76
MC		 4223 cmd_flags);
4224
4225 if (rc)
4226 goto nvram_write_end;
4227
4228 cmd_flags = 0;
4229 }
4230 }
4231
4232 /* Enable writes to flash interface (unlock write-protect) */
4233 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4234 goto nvram_write_end;
4235
b6016b76
MC		 4236 /* Loop to write back the buffer data from page_start to
4237 * data_start */
4238 i = 0;
e30372c9 4239 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
c873879c
MC		 4240 /* Erase the page */
4241 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4242 goto nvram_write_end;
4243
4244 /* Re-enable the write again for the actual write */
4245 bnx2_enable_nvram_write(bp);
4246
b6016b76
MC		 4247 for (addr = page_start; addr < data_start;
4248 addr += 4, i += 4) {
6aa20a22 4249
b6016b76
MC		 4250 rc = bnx2_nvram_write_dword(bp, addr,
4251 &flash_buffer[i], cmd_flags);
4252
4253 if (rc != 0)
4254 goto nvram_write_end;
4255
4256 cmd_flags = 0;
4257 }
4258 }
4259
4260 /* Loop to write the new data from data_start to data_end */
bae25761 4261 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
b6016b76 4262 if ((addr == page_end - 4) ||
e30372c9 4263 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
b6016b76
MC		 4264 (addr == data_end - 4))) {
4265
4266 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4267 }
4268 rc = bnx2_nvram_write_dword(bp, addr, buf,
4269 cmd_flags);
4270
4271 if (rc != 0)
4272 goto nvram_write_end;
4273
4274 cmd_flags = 0;
4275 buf += 4;
4276 }
4277
4278 /* Loop to write back the buffer data from data_end
4279 * to page_end */
e30372c9 4280 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4281 for (addr = data_end; addr < page_end;
4282 addr += 4, i += 4) {
6aa20a22 4283
b6016b76
MC		 4284 if (addr == page_end-4) {
4285 cmd_flags = BNX2_NVM_COMMAND_LAST;
4286 }
4287 rc = bnx2_nvram_write_dword(bp, addr,
4288 &flash_buffer[i], cmd_flags);
4289
4290 if (rc != 0)
4291 goto nvram_write_end;
4292
4293 cmd_flags = 0;
4294 }
4295 }
4296
4297 /* Disable writes to flash interface (lock write-protect) */
4298 bnx2_disable_nvram_write(bp);
4299
4300 /* Disable access to flash interface */
4301 bnx2_disable_nvram_access(bp);
4302 bnx2_release_nvram_lock(bp);
4303
4304 /* Increment written */
4305 written += data_end - data_start;
4306 }
4307
4308nvram_write_end:
e6be763f
MC		 4309 kfree(flash_buffer);
4310 kfree(align_buf);
b6016b76
MC		 4311 return rc;
4312}
4313
0d8a6571 4314static void
7c62e83b 4315bnx2_init_fw_cap(struct bnx2 *bp)
0d8a6571 4316{
7c62e83b 4317 u32 val, sig = 0;
0d8a6571 4318
583c28e5 4319 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
7c62e83b
MC		 4320 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4321
4322 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4323 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
0d8a6571 4324
2726d6e1 4325 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
0d8a6571
MC		 4326 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4327 return;
4328
7c62e83b
MC		 4329 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4330 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4331 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4332 }
4333
4334 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4335 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4336 u32 link;
4337
583c28e5 4338 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
0d8a6571 4339
7c62e83b
MC		 4340 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4341 if (link & BNX2_LINK_STATUS_SERDES_LINK)
0d8a6571
MC		 4342 bp->phy_port = PORT_FIBRE;
4343 else
4344 bp->phy_port = PORT_TP;
489310a4 4345
7c62e83b
MC		 4346 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4347 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
0d8a6571 4348 }
7c62e83b
MC		 4349
4350 if (netif_running(bp->dev) && sig)
4351 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
0d8a6571
MC		 4352}
4353
b4b36042
MC		 4354static void
4355bnx2_setup_msix_tbl(struct bnx2 *bp)
4356{
4357 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4358
4359 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4360 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4361}
4362
b6016b76
MC		 4363static int
4364bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4365{
4366 u32 val;
4367 int i, rc = 0;
489310a4 4368 u8 old_port;
b6016b76
MC		 4369
4370 /* Wait for the current PCI transaction to complete before
4371 * issuing a reset. */
4372 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4373 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4374 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4375 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4376 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4377 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4378 udelay(5);
4379
b090ae2b 4380 /* Wait for the firmware to tell us it is ok to issue a reset. */
a2f13890 4381 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
b090ae2b 4382
b6016b76
MC		 4383 /* Deposit a driver reset signature so the firmware knows that
4384 * this is a soft reset. */
2726d6e1
MC		 4385 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4386 BNX2_DRV_RESET_SIGNATURE_MAGIC);
b6016b76 4387
b6016b76
MC		 4388 /* Do a dummy read to force the chip to complete all current transaction
4389 * before we issue a reset. */
4390 val = REG_RD(bp, BNX2_MISC_ID);
4391
234754d5
MC		 4392 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4393 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4394 REG_RD(bp, BNX2_MISC_COMMAND);
4395 udelay(5);
b6016b76 4396
234754d5
MC		 4397 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4398 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
b6016b76 4399
234754d5 4400 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
b6016b76 4401
234754d5
MC		 4402 } else {
4403 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4404 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4405 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4406
4407 /* Chip reset. */
4408 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4409
594a9dfa
MC		 4410 /* Reading back any register after chip reset will hang the
4411 * bus on 5706 A0 and A1. The msleep below provides plenty
4412 * of margin for write posting.
4413 */
234754d5 4414 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
8e545881
AV		 4415 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4416 msleep(20);
b6016b76 4417
234754d5
MC		 4418 /* Reset takes approximate 30 usec */
4419 for (i = 0; i < 10; i++) {
4420 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4421 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4422 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4423 break;
4424 udelay(10);
4425 }
4426
4427 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4428 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4429 printk(KERN_ERR PFX "Chip reset did not complete\n");
4430 return -EBUSY;
4431 }
b6016b76
MC		 4432 }
4433
4434 /* Make sure byte swapping is properly configured. */
4435 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4436 if (val != 0x01020304) {
4437 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4438 return -ENODEV;
4439 }
4440
b6016b76 4441 /* Wait for the firmware to finish its initialization. */
a2f13890 4442 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
b090ae2b
MC		 4443 if (rc)
4444 return rc;
b6016b76 4445
0d8a6571 4446 spin_lock_bh(&bp->phy_lock);
489310a4 4447 old_port = bp->phy_port;
7c62e83b 4448 bnx2_init_fw_cap(bp);
583c28e5
MC		 4449 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4450 old_port != bp->phy_port)
0d8a6571
MC		 4451 bnx2_set_default_remote_link(bp);
4452 spin_unlock_bh(&bp->phy_lock);
4453
b6016b76
MC		 4454 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4455 /* Adjust the voltage regular to two steps lower. The default
4456 * of this register is 0x0000000e. */
4457 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4458
4459 /* Remove bad rbuf memory from the free pool. */
4460 rc = bnx2_alloc_bad_rbuf(bp);
4461 }
4462
f86e82fb 4463 if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 4464 bnx2_setup_msix_tbl(bp);
4465
b6016b76
MC		 4466 return rc;
4467}
4468
4469static int
4470bnx2_init_chip(struct bnx2 *bp)
4471{
4472 u32 val;
b4b36042 4473 int rc, i;
b6016b76
MC		 4474
4475 /* Make sure the interrupt is not active. */
4476 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4477
4478 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4479 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4480#ifdef __BIG_ENDIAN
6aa20a22 4481 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
b6016b76 4482#endif
6aa20a22 4483 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
b6016b76
MC		 4484 DMA_READ_CHANS << 12 |
4485 DMA_WRITE_CHANS << 16;
4486
4487 val |= (0x2 << 20) | (1 << 11);
4488
f86e82fb 4489 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
b6016b76
MC		 4490 val |= (1 << 23);
4491
4492 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
f86e82fb 4493 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
b6016b76
MC		 4494 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4495
4496 REG_WR(bp, BNX2_DMA_CONFIG, val);
4497
4498 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4499 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4500 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4501 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4502 }
4503
f86e82fb 4504 if (bp->flags & BNX2_FLAG_PCIX) {
b6016b76
MC		 4505 u16 val16;
4506
4507 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4508 &val16);
4509 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4510 val16 & ~PCI_X_CMD_ERO);
4511 }
4512
4513 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4514 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4515 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4516 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4517
4518 /* Initialize context mapping and zero out the quick contexts. The
4519 * context block must have already been enabled. */
641bdcd5
MC		 4520 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4521 rc = bnx2_init_5709_context(bp);
4522 if (rc)
4523 return rc;
4524 } else
59b47d8a 4525 bnx2_init_context(bp);
b6016b76 4526
fba9fe91
MC		 4527 if ((rc = bnx2_init_cpus(bp)) != 0)
4528 return rc;
4529
b6016b76
MC		 4530 bnx2_init_nvram(bp);
4531
5fcaed01 4532 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 4533
4534 val = REG_RD(bp, BNX2_MQ_CONFIG);
4535 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4536 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
68c9f75a
MC		 4537 if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4538 val |= BNX2_MQ_CONFIG_HALT_DIS;
4539
b6016b76
MC		 4540 REG_WR(bp, BNX2_MQ_CONFIG, val);
4541
4542 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4543 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4544 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4545
4546 val = (BCM_PAGE_BITS - 8) << 24;
4547 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4548
4549 /* Configure page size. */
4550 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4551 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4552 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4553 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4554
4555 val = bp->mac_addr[0] +
4556 (bp->mac_addr[1] << 8) +
4557 (bp->mac_addr[2] << 16) +
4558 bp->mac_addr[3] +
4559 (bp->mac_addr[4] << 8) +
4560 (bp->mac_addr[5] << 16);
4561 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4562
4563 /* Program the MTU. Also include 4 bytes for CRC32. */
4564 val = bp->dev->mtu + ETH_HLEN + 4;
4565 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4566 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4567 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4568
b4b36042
MC		 4569 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4570 bp->bnx2_napi[i].last_status_idx = 0;
4571
b6016b76
MC		 4572 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4573
4574 /* Set up how to generate a link change interrupt. */
4575 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4576
4577 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4578 (u64) bp->status_blk_mapping & 0xffffffff);
4579 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4580
4581 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4582 (u64) bp->stats_blk_mapping & 0xffffffff);
4583 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4584 (u64) bp->stats_blk_mapping >> 32);
4585
6aa20a22 4586 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
b6016b76
MC		 4587 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4588
4589 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4590 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4591
4592 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4593 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4594
4595 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4596
4597 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4598
4599 REG_WR(bp, BNX2_HC_COM_TICKS,
4600 (bp->com_ticks_int << 16) | bp->com_ticks);
4601
4602 REG_WR(bp, BNX2_HC_CMD_TICKS,
4603 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4604
02537b06
MC		 4605 if (CHIP_NUM(bp) == CHIP_NUM_5708)
4606 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4607 else
7ea6920e 4608 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
b6016b76
MC		 4609 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4610
4611 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
8e6a72c4 4612 val = BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76 4613 else {
8e6a72c4
MC		 4614 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4615 BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76
MC		 4616 }
4617
5e9ad9e1 4618 if (bp->irq_nvecs > 1) {
c76c0475
MC		 4619 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4620 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4621
5e9ad9e1
MC		 4622 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4623 }
4624
4625 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4626 val |= BNX2_HC_CONFIG_ONE_SHOT;
4627
4628 REG_WR(bp, BNX2_HC_CONFIG, val);
4629
4630 for (i = 1; i < bp->irq_nvecs; i++) {
4631 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4632 BNX2_HC_SB_CONFIG_1;
4633
6f743ca0 4634 REG_WR(bp, base,
c76c0475 4635 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
5e9ad9e1 4636 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
c76c0475
MC		 4637 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4638
6f743ca0 4639 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
c76c0475
MC		 4640 (bp->tx_quick_cons_trip_int << 16) |
4641 bp->tx_quick_cons_trip);
4642
6f743ca0 4643 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
c76c0475
MC		 4644 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4645
5e9ad9e1
MC		 4646 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4647 (bp->rx_quick_cons_trip_int << 16) |
4648 bp->rx_quick_cons_trip);
8e6a72c4 4649
5e9ad9e1
MC		 4650 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4651 (bp->rx_ticks_int << 16) | bp->rx_ticks);
4652 }
8e6a72c4 4653
b6016b76
MC		 4654 /* Clear internal stats counters. */
4655 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4656
da3e4fbe 4657 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
b6016b76
MC		 4658
4659 /* Initialize the receive filter. */
4660 bnx2_set_rx_mode(bp->dev);
4661
0aa38df7
MC		 4662 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4663 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4664 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4665 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4666 }
b090ae2b 4667 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
a2f13890 4668 1, 0);
b6016b76 4669
df149d70 4670 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
b6016b76
MC		 4671 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4672
4673 udelay(20);
4674
bf5295bb
MC		 4675 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4676
b090ae2b 4677 return rc;
b6016b76
MC		 4678}
4679
c76c0475
MC		 4680static void
4681bnx2_clear_ring_states(struct bnx2 *bp)
4682{
4683 struct bnx2_napi *bnapi;
35e9010b 4684 struct bnx2_tx_ring_info *txr;
bb4f98ab 4685 struct bnx2_rx_ring_info *rxr;
c76c0475
MC		 4686 int i;
4687
4688 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4689 bnapi = &bp->bnx2_napi[i];
35e9010b 4690 txr = &bnapi->tx_ring;
bb4f98ab 4691 rxr = &bnapi->rx_ring;
c76c0475 4692
35e9010b
MC		 4693 txr->tx_cons = 0;
4694 txr->hw_tx_cons = 0;
bb4f98ab
MC		 4695 rxr->rx_prod_bseq = 0;
4696 rxr->rx_prod = 0;
4697 rxr->rx_cons = 0;
4698 rxr->rx_pg_prod = 0;
4699 rxr->rx_pg_cons = 0;
c76c0475
MC		 4700 }
4701}
4702
59b47d8a 4703static void
35e9010b 4704bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
59b47d8a
MC		 4705{
4706 u32 val, offset0, offset1, offset2, offset3;
62a8313c 4707 u32 cid_addr = GET_CID_ADDR(cid);
59b47d8a
MC		 4708
4709 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4710 offset0 = BNX2_L2CTX_TYPE_XI;
4711 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4712 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4713 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4714 } else {
4715 offset0 = BNX2_L2CTX_TYPE;
4716 offset1 = BNX2_L2CTX_CMD_TYPE;
4717 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4718 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4719 }
4720 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
62a8313c 4721 bnx2_ctx_wr(bp, cid_addr, offset0, val);
59b47d8a
MC		 4722
4723 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
62a8313c 4724 bnx2_ctx_wr(bp, cid_addr, offset1, val);
59b47d8a 4725
35e9010b 4726 val = (u64) txr->tx_desc_mapping >> 32;
62a8313c 4727 bnx2_ctx_wr(bp, cid_addr, offset2, val);
59b47d8a 4728
35e9010b 4729 val = (u64) txr->tx_desc_mapping & 0xffffffff;
62a8313c 4730 bnx2_ctx_wr(bp, cid_addr, offset3, val);
59b47d8a 4731}
b6016b76
MC		 4732
4733static void
35e9010b 4734bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
b6016b76
MC		 4735{
4736 struct tx_bd *txbd;
c76c0475
MC		 4737 u32 cid = TX_CID;
4738 struct bnx2_napi *bnapi;
35e9010b 4739 struct bnx2_tx_ring_info *txr;
c76c0475 4740
35e9010b
MC		 4741 bnapi = &bp->bnx2_napi[ring_num];
4742 txr = &bnapi->tx_ring;
4743
4744 if (ring_num == 0)
4745 cid = TX_CID;
4746 else
4747 cid = TX_TSS_CID + ring_num - 1;
b6016b76 4748
2f8af120
MC		 4749 bp->tx_wake_thresh = bp->tx_ring_size / 2;
4750
35e9010b 4751 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
6aa20a22 4752
35e9010b
MC		 4753 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
4754 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
b6016b76 4755
35e9010b
MC		 4756 txr->tx_prod = 0;
4757 txr->tx_prod_bseq = 0;
6aa20a22 4758
35e9010b
MC		 4759 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4760 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
b6016b76 4761
35e9010b 4762 bnx2_init_tx_context(bp, cid, txr);
b6016b76
MC		 4763}
4764
4765static void
5d5d0015
MC		 4766bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4767 int num_rings)
b6016b76 4768{
b6016b76 4769 int i;
5d5d0015 4770 struct rx_bd *rxbd;
6aa20a22 4771
5d5d0015 4772 for (i = 0; i < num_rings; i++) {
13daffa2 4773 int j;
b6016b76 4774
5d5d0015 4775 rxbd = &rx_ring[i][0];
13daffa2 4776 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5d5d0015 4777 rxbd->rx_bd_len = buf_size;
13daffa2
MC		 4778 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4779 }
5d5d0015 4780 if (i == (num_rings - 1))
13daffa2
MC		 4781 j = 0;
4782 else
4783 j = i + 1;
5d5d0015
MC		 4784 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4785 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
13daffa2 4786 }
5d5d0015
MC		 4787}
4788
4789static void
bb4f98ab 4790bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5d5d0015
MC		 4791{
4792 int i;
4793 u16 prod, ring_prod;
bb4f98ab
MC		 4794 u32 cid, rx_cid_addr, val;
4795 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
4796 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
4797
4798 if (ring_num == 0)
4799 cid = RX_CID;
4800 else
4801 cid = RX_RSS_CID + ring_num - 1;
4802
4803 rx_cid_addr = GET_CID_ADDR(cid);
5d5d0015 4804
bb4f98ab 4805 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5d5d0015
MC		 4806 bp->rx_buf_use_size, bp->rx_max_ring);
4807
bb4f98ab 4808 bnx2_init_rx_context(bp, cid);
83e3fc89
MC		 4809
4810 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4811 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4812 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4813 }
4814
62a8313c 4815 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
47bf4246 4816 if (bp->rx_pg_ring_size) {
bb4f98ab
MC		 4817 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
4818 rxr->rx_pg_desc_mapping,
47bf4246
MC		 4819 PAGE_SIZE, bp->rx_max_pg_ring);
4820 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
62a8313c
MC		 4821 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4822 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5e9ad9e1 4823 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
47bf4246 4824
bb4f98ab 4825 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
62a8313c 4826 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
47bf4246 4827
bb4f98ab 4828 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
62a8313c 4829 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
47bf4246
MC		 4830
4831 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4832 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4833 }
b6016b76 4834
bb4f98ab 4835 val = (u64) rxr->rx_desc_mapping[0] >> 32;
62a8313c 4836 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
b6016b76 4837
bb4f98ab 4838 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
62a8313c 4839 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
b6016b76 4840
bb4f98ab 4841 ring_prod = prod = rxr->rx_pg_prod;
47bf4246 4842 for (i = 0; i < bp->rx_pg_ring_size; i++) {
bb4f98ab 4843 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
47bf4246
MC		 4844 break;
4845 prod = NEXT_RX_BD(prod);
4846 ring_prod = RX_PG_RING_IDX(prod);
4847 }
bb4f98ab 4848 rxr->rx_pg_prod = prod;
47bf4246 4849
bb4f98ab 4850 ring_prod = prod = rxr->rx_prod;
236b6394 4851 for (i = 0; i < bp->rx_ring_size; i++) {
bb4f98ab 4852 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
b6016b76 4853 break;
b6016b76
MC		 4854 prod = NEXT_RX_BD(prod);
4855 ring_prod = RX_RING_IDX(prod);
4856 }
bb4f98ab 4857 rxr->rx_prod = prod;
b6016b76 4858
bb4f98ab
MC		 4859 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
4860 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
4861 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
b6016b76 4862
bb4f98ab
MC		 4863 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
4864 REG_WR16(bp, rxr->rx_bidx_addr, prod);
4865
4866 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
b6016b76
MC		 4867}
4868
35e9010b
MC		 4869static void
4870bnx2_init_all_rings(struct bnx2 *bp)
4871{
4872 int i;
5e9ad9e1 4873 u32 val;
35e9010b
MC		 4874
4875 bnx2_clear_ring_states(bp);
4876
4877 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
4878 for (i = 0; i < bp->num_tx_rings; i++)
4879 bnx2_init_tx_ring(bp, i);
4880
4881 if (bp->num_tx_rings > 1)
4882 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
4883 (TX_TSS_CID << 7));
4884
5e9ad9e1
MC		 4885 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
4886 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
4887
bb4f98ab
MC		 4888 for (i = 0; i < bp->num_rx_rings; i++)
4889 bnx2_init_rx_ring(bp, i);
5e9ad9e1
MC		 4890
4891 if (bp->num_rx_rings > 1) {
4892 u32 tbl_32;
4893 u8 *tbl = (u8 *) &tbl_32;
4894
4895 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
4896 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
4897
4898 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
4899 tbl[i % 4] = i % (bp->num_rx_rings - 1);
4900 if ((i % 4) == 3)
4901 bnx2_reg_wr_ind(bp,
4902 BNX2_RXP_SCRATCH_RSS_TBL + i,
4903 cpu_to_be32(tbl_32));
4904 }
4905
4906 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
4907 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
4908
4909 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
4910
4911 }
35e9010b
MC		 4912}
4913
5d5d0015 4914static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
13daffa2 4915{
5d5d0015 4916 u32 max, num_rings = 1;
13daffa2 4917
5d5d0015
MC		 4918 while (ring_size > MAX_RX_DESC_CNT) {
4919 ring_size -= MAX_RX_DESC_CNT;
13daffa2
MC		 4920 num_rings++;
4921 }
4922 /* round to next power of 2 */
5d5d0015 4923 max = max_size;
13daffa2
MC		 4924 while ((max & num_rings) == 0)
4925 max >>= 1;
4926
4927 if (num_rings != max)
4928 max <<= 1;
4929
5d5d0015
MC		 4930 return max;
4931}
4932
4933static void
4934bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4935{
84eaa187 4936 u32 rx_size, rx_space, jumbo_size;
5d5d0015
MC		 4937
4938 /* 8 for CRC and VLAN */
d89cb6af 4939 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5d5d0015 4940
84eaa187
MC		 4941 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4942 sizeof(struct skb_shared_info);
4943
601d3d18 4944 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
47bf4246
MC		 4945 bp->rx_pg_ring_size = 0;
4946 bp->rx_max_pg_ring = 0;
4947 bp->rx_max_pg_ring_idx = 0;
f86e82fb 4948 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
84eaa187
MC		 4949 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4950
4951 jumbo_size = size * pages;
4952 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
4953 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
4954
4955 bp->rx_pg_ring_size = jumbo_size;
4956 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
4957 MAX_RX_PG_RINGS);
4958 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
601d3d18 4959 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
84eaa187
MC		 4960 bp->rx_copy_thresh = 0;
4961 }
5d5d0015
MC		 4962
4963 bp->rx_buf_use_size = rx_size;
4964 /* hw alignment */
4965 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
d89cb6af 4966 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5d5d0015
MC		 4967 bp->rx_ring_size = size;
4968 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
13daffa2
MC		 4969 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4970}
4971
b6016b76
MC		 4972static void
4973bnx2_free_tx_skbs(struct bnx2 *bp)
4974{
4975 int i;
4976
35e9010b
MC		 4977 for (i = 0; i < bp->num_tx_rings; i++) {
4978 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
4979 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
4980 int j;
b6016b76 4981
35e9010b 4982 if (txr->tx_buf_ring == NULL)
b6016b76 4983 continue;
b6016b76 4984
35e9010b 4985 for (j = 0; j < TX_DESC_CNT; ) {
3d16af86 4986 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
35e9010b 4987 struct sk_buff *skb = tx_buf->skb;
35e9010b
MC		 4988
4989 if (skb == NULL) {
4990 j++;
4991 continue;
4992 }
4993
3d16af86 4994 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
b6016b76 4995
35e9010b 4996 tx_buf->skb = NULL;
b6016b76 4997
3d16af86 4998 j += skb_shinfo(skb)->nr_frags + 1;
35e9010b 4999 dev_kfree_skb(skb);
b6016b76 5000 }
b6016b76 5001 }
b6016b76
MC		 5002}
5003
5004static void
5005bnx2_free_rx_skbs(struct bnx2 *bp)
5006{
5007 int i;
5008
bb4f98ab
MC		 5009 for (i = 0; i < bp->num_rx_rings; i++) {
5010 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5011 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5012 int j;
b6016b76 5013
bb4f98ab
MC		 5014 if (rxr->rx_buf_ring == NULL)
5015 return;
b6016b76 5016
bb4f98ab
MC		 5017 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5018 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5019 struct sk_buff *skb = rx_buf->skb;
b6016b76 5020
bb4f98ab
MC		 5021 if (skb == NULL)
5022 continue;
b6016b76 5023
bb4f98ab
MC		 5024 pci_unmap_single(bp->pdev,
5025 pci_unmap_addr(rx_buf, mapping),
5026 bp->rx_buf_use_size,
5027 PCI_DMA_FROMDEVICE);
b6016b76 5028
bb4f98ab
MC		 5029 rx_buf->skb = NULL;
5030
5031 dev_kfree_skb(skb);
5032 }
5033 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5034 bnx2_free_rx_page(bp, rxr, j);
b6016b76
MC		 5035 }
5036}
5037
5038static void
5039bnx2_free_skbs(struct bnx2 *bp)
5040{
5041 bnx2_free_tx_skbs(bp);
5042 bnx2_free_rx_skbs(bp);
5043}
5044
5045static int
5046bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5047{
5048 int rc;
5049
5050 rc = bnx2_reset_chip(bp, reset_code);
5051 bnx2_free_skbs(bp);
5052 if (rc)
5053 return rc;
5054
fba9fe91
MC		 5055 if ((rc = bnx2_init_chip(bp)) != 0)
5056 return rc;
5057
35e9010b 5058 bnx2_init_all_rings(bp);
b6016b76
MC		 5059 return 0;
5060}
5061
5062static int
9a120bc5 5063bnx2_init_nic(struct bnx2 *bp, int reset_phy)
b6016b76
MC		 5064{
5065 int rc;
5066
5067 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5068 return rc;
5069
80be4434 5070 spin_lock_bh(&bp->phy_lock);
9a120bc5 5071 bnx2_init_phy(bp, reset_phy);
b6016b76 5072 bnx2_set_link(bp);
543a827d
MC		 5073 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5074 bnx2_remote_phy_event(bp);
0d8a6571 5075 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 5076 return 0;
5077}
5078
74bf4ba3
MC		 5079static int
5080bnx2_shutdown_chip(struct bnx2 *bp)
5081{
5082 u32 reset_code;
5083
5084 if (bp->flags & BNX2_FLAG_NO_WOL)
5085 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5086 else if (bp->wol)
5087 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5088 else
5089 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5090
5091 return bnx2_reset_chip(bp, reset_code);
5092}
5093
b6016b76
MC		 5094static int
5095bnx2_test_registers(struct bnx2 *bp)
5096{
5097 int ret;
5bae30c9 5098 int i, is_5709;
f71e1309 5099 static const struct {
b6016b76
MC		 5100 u16 offset;
5101 u16 flags;
5bae30c9 5102#define BNX2_FL_NOT_5709 1
b6016b76
MC		 5103 u32 rw_mask;
5104 u32 ro_mask;
5105 } reg_tbl[] = {
5106 { 0x006c, 0, 0x00000000, 0x0000003f },
5107 { 0x0090, 0, 0xffffffff, 0x00000000 },
5108 { 0x0094, 0, 0x00000000, 0x00000000 },
5109
5bae30c9
MC		 5110 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5111 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5112 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5113 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5114 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5115 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5116 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5117 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5118 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5119
5120 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5121 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5122 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5123 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5124 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5125 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5126
5127 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5128 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5129 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
b6016b76
MC		 5130
5131 { 0x1000, 0, 0x00000000, 0x00000001 },
15b169cc 5132 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
b6016b76
MC		 5133
5134 { 0x1408, 0, 0x01c00800, 0x00000000 },
5135 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5136 { 0x14a8, 0, 0x00000000, 0x000001ff },
5b0c76ad 5137 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
b6016b76
MC		 5138 { 0x14b0, 0, 0x00000002, 0x00000001 },
5139 { 0x14b8, 0, 0x00000000, 0x00000000 },
5140 { 0x14c0, 0, 0x00000000, 0x00000009 },
5141 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5142 { 0x14cc, 0, 0x00000000, 0x00000001 },
5143 { 0x14d0, 0, 0xffffffff, 0x00000000 },
b6016b76
MC		 5144
5145 { 0x1800, 0, 0x00000000, 0x00000001 },
5146 { 0x1804, 0, 0x00000000, 0x00000003 },
b6016b76
MC		 5147
5148 { 0x2800, 0, 0x00000000, 0x00000001 },
5149 { 0x2804, 0, 0x00000000, 0x00003f01 },
5150 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5151 { 0x2810, 0, 0xffff0000, 0x00000000 },
5152 { 0x2814, 0, 0xffff0000, 0x00000000 },
5153 { 0x2818, 0, 0xffff0000, 0x00000000 },
5154 { 0x281c, 0, 0xffff0000, 0x00000000 },
5155 { 0x2834, 0, 0xffffffff, 0x00000000 },
5156 { 0x2840, 0, 0x00000000, 0xffffffff },
5157 { 0x2844, 0, 0x00000000, 0xffffffff },
5158 { 0x2848, 0, 0xffffffff, 0x00000000 },
5159 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5160
5161 { 0x2c00, 0, 0x00000000, 0x00000011 },
5162 { 0x2c04, 0, 0x00000000, 0x00030007 },
5163
b6016b76
MC		 5164 { 0x3c00, 0, 0x00000000, 0x00000001 },
5165 { 0x3c04, 0, 0x00000000, 0x00070000 },
5166 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5167 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5168 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5169 { 0x3c14, 0, 0x00000000, 0xffffffff },
5170 { 0x3c18, 0, 0x00000000, 0xffffffff },
5171 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5172 { 0x3c20, 0, 0xffffff00, 0x00000000 },
b6016b76
MC		 5173
5174 { 0x5004, 0, 0x00000000, 0x0000007f },
5175 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
b6016b76 5176
b6016b76
MC		 5177 { 0x5c00, 0, 0x00000000, 0x00000001 },
5178 { 0x5c04, 0, 0x00000000, 0x0003000f },
5179 { 0x5c08, 0, 0x00000003, 0x00000000 },
5180 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5181 { 0x5c10, 0, 0x00000000, 0xffffffff },
5182 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5183 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5184 { 0x5c88, 0, 0x00000000, 0x00077373 },
5185 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5186
5187 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5188 { 0x680c, 0, 0xffffffff, 0x00000000 },
5189 { 0x6810, 0, 0xffffffff, 0x00000000 },
5190 { 0x6814, 0, 0xffffffff, 0x00000000 },
5191 { 0x6818, 0, 0xffffffff, 0x00000000 },
5192 { 0x681c, 0, 0xffffffff, 0x00000000 },
5193 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5194 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5195 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5196 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5197 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5198 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5199 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5200 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5201 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5202 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5203 { 0x684c, 0, 0xffffffff, 0x00000000 },
5204 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5205 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5206 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5207 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5208 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5209 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5210
5211 { 0xffff, 0, 0x00000000, 0x00000000 },
5212 };
5213
5214 ret = 0;
5bae30c9
MC		 5215 is_5709 = 0;
5216 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5217 is_5709 = 1;
5218
b6016b76
MC		 5219 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5220 u32 offset, rw_mask, ro_mask, save_val, val;
5bae30c9
MC		 5221 u16 flags = reg_tbl[i].flags;
5222
5223 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5224 continue;
b6016b76
MC		 5225
5226 offset = (u32) reg_tbl[i].offset;
5227 rw_mask = reg_tbl[i].rw_mask;
5228 ro_mask = reg_tbl[i].ro_mask;
5229
14ab9b86 5230 save_val = readl(bp->regview + offset);
b6016b76 5231
14ab9b86 5232 writel(0, bp->regview + offset);
b6016b76 5233
14ab9b86 5234 val = readl(bp->regview + offset);
b6016b76
MC		 5235 if ((val & rw_mask) != 0) {
5236 goto reg_test_err;
5237 }
5238
5239 if ((val & ro_mask) != (save_val & ro_mask)) {
5240 goto reg_test_err;
5241 }
5242
14ab9b86 5243 writel(0xffffffff, bp->regview + offset);
b6016b76 5244
14ab9b86 5245 val = readl(bp->regview + offset);
b6016b76
MC		 5246 if ((val & rw_mask) != rw_mask) {
5247 goto reg_test_err;
5248 }
5249
5250 if ((val & ro_mask) != (save_val & ro_mask)) {
5251 goto reg_test_err;
5252 }
5253
14ab9b86 5254 writel(save_val, bp->regview + offset);
b6016b76
MC		 5255 continue;
5256
5257reg_test_err:
14ab9b86 5258 writel(save_val, bp->regview + offset);
b6016b76
MC		 5259 ret = -ENODEV;
5260 break;
5261 }
5262 return ret;
5263}
5264
5265static int
5266bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5267{
f71e1309 5268 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
b6016b76
MC		 5269 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5270 int i;
5271
5272 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5273 u32 offset;
5274
5275 for (offset = 0; offset < size; offset += 4) {
5276
2726d6e1 5277 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
b6016b76 5278
2726d6e1 5279 if (bnx2_reg_rd_ind(bp, start + offset) !=
b6016b76
MC		 5280 test_pattern[i]) {
5281 return -ENODEV;
5282 }
5283 }
5284 }
5285 return 0;
5286}
5287
5288static int
5289bnx2_test_memory(struct bnx2 *bp)
5290{
5291 int ret = 0;
5292 int i;
5bae30c9 5293 static struct mem_entry {
b6016b76
MC		 5294 u32 offset;
5295 u32 len;
5bae30c9 5296 } mem_tbl_5706[] = {
b6016b76 5297 { 0x60000, 0x4000 },
5b0c76ad 5298 { 0xa0000, 0x3000 },
b6016b76
MC		 5299 { 0xe0000, 0x4000 },
5300 { 0x120000, 0x4000 },
5301 { 0x1a0000, 0x4000 },
5302 { 0x160000, 0x4000 },
5303 { 0xffffffff, 0 },
5bae30c9
MC		 5304 },
5305 mem_tbl_5709[] = {
5306 { 0x60000, 0x4000 },
5307 { 0xa0000, 0x3000 },
5308 { 0xe0000, 0x4000 },
5309 { 0x120000, 0x4000 },
5310 { 0x1a0000, 0x4000 },
5311 { 0xffffffff, 0 },
b6016b76 5312 };
5bae30c9
MC		 5313 struct mem_entry *mem_tbl;
5314
5315 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5316 mem_tbl = mem_tbl_5709;
5317 else
5318 mem_tbl = mem_tbl_5706;
b6016b76
MC		 5319
5320 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5321 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5322 mem_tbl[i].len)) != 0) {
5323 return ret;
5324 }
5325 }
6aa20a22 5326
b6016b76
MC		 5327 return ret;
5328}
5329
bc5a0690
MC		 5330#define BNX2_MAC_LOOPBACK 0
5331#define BNX2_PHY_LOOPBACK 1
5332
b6016b76 5333static int
bc5a0690 5334bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
b6016b76
MC		 5335{
5336 unsigned int pkt_size, num_pkts, i;
5337 struct sk_buff *skb, *rx_skb;
5338 unsigned char *packet;
bc5a0690 5339 u16 rx_start_idx, rx_idx;
b6016b76
MC		 5340 dma_addr_t map;
5341 struct tx_bd *txbd;
5342 struct sw_bd *rx_buf;
5343 struct l2_fhdr *rx_hdr;
5344 int ret = -ENODEV;
c76c0475 5345 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
35e9010b 5346 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
bb4f98ab 5347 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
c76c0475
MC		 5348
5349 tx_napi = bnapi;
b6016b76 5350
35e9010b 5351 txr = &tx_napi->tx_ring;
bb4f98ab 5352 rxr = &bnapi->rx_ring;
bc5a0690
MC		 5353 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5354 bp->loopback = MAC_LOOPBACK;
5355 bnx2_set_mac_loopback(bp);
5356 }
5357 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
583c28e5 5358 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
489310a4
MC		 5359 return 0;
5360
80be4434 5361 bp->loopback = PHY_LOOPBACK;
bc5a0690
MC		 5362 bnx2_set_phy_loopback(bp);
5363 }
5364 else
5365 return -EINVAL;
b6016b76 5366
84eaa187 5367 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
932f3772 5368 skb = netdev_alloc_skb(bp->dev, pkt_size);
b6cbc3b6
JL		 5369 if (!skb)
5370 return -ENOMEM;
b6016b76 5371 packet = skb_put(skb, pkt_size);
6634292b 5372 memcpy(packet, bp->dev->dev_addr, 6);
b6016b76
MC		 5373 memset(packet + 6, 0x0, 8);
5374 for (i = 14; i < pkt_size; i++)
5375 packet[i] = (unsigned char) (i & 0xff);
5376
3d16af86
BL		 5377 if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
5378 dev_kfree_skb(skb);
5379 return -EIO;
5380 }
5381 map = skb_shinfo(skb)->dma_maps[0];
b6016b76 5382
bf5295bb
MC		 5383 REG_WR(bp, BNX2_HC_COMMAND,
5384 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5385
b6016b76
MC		 5386 REG_RD(bp, BNX2_HC_COMMAND);
5387
5388 udelay(5);
35efa7c1 5389 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76 5390
b6016b76
MC		 5391 num_pkts = 0;
5392
35e9010b 5393 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
b6016b76
MC		 5394
5395 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5396 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5397 txbd->tx_bd_mss_nbytes = pkt_size;
5398 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5399
5400 num_pkts++;
35e9010b
MC		 5401 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5402 txr->tx_prod_bseq += pkt_size;
b6016b76 5403
35e9010b
MC		 5404 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5405 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
b6016b76
MC		 5406
5407 udelay(100);
5408
bf5295bb
MC		 5409 REG_WR(bp, BNX2_HC_COMMAND,
5410 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5411
b6016b76
MC		 5412 REG_RD(bp, BNX2_HC_COMMAND);
5413
5414 udelay(5);
5415
3d16af86 5416 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
745720e5 5417 dev_kfree_skb(skb);
b6016b76 5418
35e9010b 5419 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
b6016b76 5420 goto loopback_test_done;
b6016b76 5421
35efa7c1 5422 rx_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76
MC		 5423 if (rx_idx != rx_start_idx + num_pkts) {
5424 goto loopback_test_done;
5425 }
5426
bb4f98ab 5427 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
b6016b76
MC		 5428 rx_skb = rx_buf->skb;
5429
5430 rx_hdr = (struct l2_fhdr *) rx_skb->data;
d89cb6af 5431 skb_reserve(rx_skb, BNX2_RX_OFFSET);
b6016b76
MC		 5432
5433 pci_dma_sync_single_for_cpu(bp->pdev,
5434 pci_unmap_addr(rx_buf, mapping),
5435 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5436
ade2bfe7 5437 if (rx_hdr->l2_fhdr_status &
b6016b76
MC		 5438 (L2_FHDR_ERRORS_BAD_CRC |
5439 L2_FHDR_ERRORS_PHY_DECODE |
5440 L2_FHDR_ERRORS_ALIGNMENT |
5441 L2_FHDR_ERRORS_TOO_SHORT |
5442 L2_FHDR_ERRORS_GIANT_FRAME)) {
5443
5444 goto loopback_test_done;
5445 }
5446
5447 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5448 goto loopback_test_done;
5449 }
5450
5451 for (i = 14; i < pkt_size; i++) {
5452 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5453 goto loopback_test_done;
5454 }
5455 }
5456
5457 ret = 0;
5458
5459loopback_test_done:
5460 bp->loopback = 0;
5461 return ret;
5462}
5463
bc5a0690
MC		 5464#define BNX2_MAC_LOOPBACK_FAILED 1
5465#define BNX2_PHY_LOOPBACK_FAILED 2
5466#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5467 BNX2_PHY_LOOPBACK_FAILED)
5468
5469static int
5470bnx2_test_loopback(struct bnx2 *bp)
5471{
5472 int rc = 0;
5473
5474 if (!netif_running(bp->dev))
5475 return BNX2_LOOPBACK_FAILED;
5476
5477 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5478 spin_lock_bh(&bp->phy_lock);
9a120bc5 5479 bnx2_init_phy(bp, 1);
bc5a0690
MC		 5480 spin_unlock_bh(&bp->phy_lock);
5481 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5482 rc |= BNX2_MAC_LOOPBACK_FAILED;
5483 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5484 rc |= BNX2_PHY_LOOPBACK_FAILED;
5485 return rc;
5486}
5487
b6016b76
MC		 5488#define NVRAM_SIZE 0x200
5489#define CRC32_RESIDUAL 0xdebb20e3
5490
5491static int
5492bnx2_test_nvram(struct bnx2 *bp)
5493{
b491edd5 5494 __be32 buf[NVRAM_SIZE / 4];
b6016b76
MC		 5495 u8 *data = (u8 *) buf;
5496 int rc = 0;
5497 u32 magic, csum;
5498
5499 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5500 goto test_nvram_done;
5501
5502 magic = be32_to_cpu(buf[0]);
5503 if (magic != 0x669955aa) {
5504 rc = -ENODEV;
5505 goto test_nvram_done;
5506 }
5507
5508 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5509 goto test_nvram_done;
5510
5511 csum = ether_crc_le(0x100, data);
5512 if (csum != CRC32_RESIDUAL) {
5513 rc = -ENODEV;
5514 goto test_nvram_done;
5515 }
5516
5517 csum = ether_crc_le(0x100, data + 0x100);
5518 if (csum != CRC32_RESIDUAL) {
5519 rc = -ENODEV;
5520 }
5521
5522test_nvram_done:
5523 return rc;
5524}
5525
5526static int
5527bnx2_test_link(struct bnx2 *bp)
5528{
5529 u32 bmsr;
5530
9f52b564
MC		 5531 if (!netif_running(bp->dev))
5532 return -ENODEV;
5533
583c28e5 5534 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
489310a4
MC		 5535 if (bp->link_up)
5536 return 0;
5537 return -ENODEV;
5538 }
c770a65c 5539 spin_lock_bh(&bp->phy_lock);
27a005b8
MC		 5540 bnx2_enable_bmsr1(bp);
5541 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5542 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5543 bnx2_disable_bmsr1(bp);
c770a65c 5544 spin_unlock_bh(&bp->phy_lock);
6aa20a22 5545
b6016b76
MC		 5546 if (bmsr & BMSR_LSTATUS) {
5547 return 0;
5548 }
5549 return -ENODEV;
5550}
5551
5552static int
5553bnx2_test_intr(struct bnx2 *bp)
5554{
5555 int i;
b6016b76
MC		 5556 u16 status_idx;
5557
5558 if (!netif_running(bp->dev))
5559 return -ENODEV;
5560
5561 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5562
5563 /* This register is not touched during run-time. */
bf5295bb 5564 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 5565 REG_RD(bp, BNX2_HC_COMMAND);
5566
5567 for (i = 0; i < 10; i++) {
5568 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5569 status_idx) {
5570
5571 break;
5572 }
5573
5574 msleep_interruptible(10);
5575 }
5576 if (i < 10)
5577 return 0;
5578
5579 return -ENODEV;
5580}
5581
38ea3686 5582/* Determining link for parallel detection. */
b2fadeae
MC		 5583static int
5584bnx2_5706_serdes_has_link(struct bnx2 *bp)
5585{
5586 u32 mode_ctl, an_dbg, exp;
5587
38ea3686
MC		 5588 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5589 return 0;
5590
b2fadeae
MC		 5591 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5592 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5593
5594 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5595 return 0;
5596
5597 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5598 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5599 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5600
f3014c0c 5601 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
b2fadeae
MC		 5602 return 0;
5603
5604 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5605 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5606 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5607
5608 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5609 return 0;
5610
5611 return 1;
5612}
5613
b6016b76 5614static void
48b01e2d 5615bnx2_5706_serdes_timer(struct bnx2 *bp)
b6016b76 5616{
b2fadeae
MC		 5617 int check_link = 1;
5618
48b01e2d 5619 spin_lock(&bp->phy_lock);
b2fadeae 5620 if (bp->serdes_an_pending) {
48b01e2d 5621 bp->serdes_an_pending--;
b2fadeae
MC		 5622 check_link = 0;
5623 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
48b01e2d 5624 u32 bmcr;
b6016b76 5625
ac392abc 5626 bp->current_interval = BNX2_TIMER_INTERVAL;
cd339a0e 5627
ca58c3af 5628 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 5629
48b01e2d 5630 if (bmcr & BMCR_ANENABLE) {
b2fadeae 5631 if (bnx2_5706_serdes_has_link(bp)) {
48b01e2d
MC		 5632 bmcr &= ~BMCR_ANENABLE;
5633 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
ca58c3af 5634 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
583c28e5 5635 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d 5636 }
b6016b76 5637 }
48b01e2d
MC		 5638 }
5639 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
583c28e5 5640 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
48b01e2d 5641 u32 phy2;
b6016b76 5642
48b01e2d
MC		 5643 bnx2_write_phy(bp, 0x17, 0x0f01);
5644 bnx2_read_phy(bp, 0x15, &phy2);
5645 if (phy2 & 0x20) {
5646 u32 bmcr;
cd339a0e 5647
ca58c3af 5648 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
48b01e2d 5649 bmcr |= BMCR_ANENABLE;
ca58c3af 5650 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
b6016b76 5651
583c28e5 5652 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d
MC		 5653 }
5654 } else
ac392abc 5655 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 5656
a2724e25 5657 if (check_link) {
b2fadeae
MC		 5658 u32 val;
5659
5660 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5661 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5662 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5663
a2724e25
MC		 5664 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5665 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5666 bnx2_5706s_force_link_dn(bp, 1);
5667 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5668 } else
5669 bnx2_set_link(bp);
5670 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5671 bnx2_set_link(bp);
b2fadeae 5672 }
48b01e2d
MC		 5673 spin_unlock(&bp->phy_lock);
5674}
b6016b76 5675
f8dd064e
MC		 5676static void
5677bnx2_5708_serdes_timer(struct bnx2 *bp)
5678{
583c28e5 5679 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 5680 return;
5681
583c28e5 5682 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
f8dd064e
MC		 5683 bp->serdes_an_pending = 0;
5684 return;
5685 }
b6016b76 5686
f8dd064e
MC		 5687 spin_lock(&bp->phy_lock);
5688 if (bp->serdes_an_pending)
5689 bp->serdes_an_pending--;
5690 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5691 u32 bmcr;
b6016b76 5692
ca58c3af 5693 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
f8dd064e 5694 if (bmcr & BMCR_ANENABLE) {
605a9e20 5695 bnx2_enable_forced_2g5(bp);
f8dd064e
MC		 5696 bp->current_interval = SERDES_FORCED_TIMEOUT;
5697 } else {
605a9e20 5698 bnx2_disable_forced_2g5(bp);
f8dd064e 5699 bp->serdes_an_pending = 2;
ac392abc 5700 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 5701 }
b6016b76 5702
f8dd064e 5703 } else
ac392abc 5704 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 5705
f8dd064e
MC		 5706 spin_unlock(&bp->phy_lock);
5707}
5708
48b01e2d
MC		 5709static void
5710bnx2_timer(unsigned long data)
5711{
5712 struct bnx2 *bp = (struct bnx2 *) data;
b6016b76 5713
48b01e2d
MC		 5714 if (!netif_running(bp->dev))
5715 return;
b6016b76 5716
48b01e2d
MC		 5717 if (atomic_read(&bp->intr_sem) != 0)
5718 goto bnx2_restart_timer;
b6016b76 5719
df149d70 5720 bnx2_send_heart_beat(bp);
b6016b76 5721
2726d6e1
MC		 5722 bp->stats_blk->stat_FwRxDrop =
5723 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
b6016b76 5724
02537b06
MC		 5725 /* workaround occasional corrupted counters */
5726 if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5727 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5728 BNX2_HC_COMMAND_STATS_NOW);
5729
583c28e5 5730 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
f8dd064e
MC		 5731 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5732 bnx2_5706_serdes_timer(bp);
27a005b8 5733 else
f8dd064e 5734 bnx2_5708_serdes_timer(bp);
b6016b76
MC		 5735 }
5736
5737bnx2_restart_timer:
cd339a0e 5738 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 5739}
5740
8e6a72c4
MC		 5741static int
5742bnx2_request_irq(struct bnx2 *bp)
5743{
6d866ffc 5744 unsigned long flags;
b4b36042
MC		 5745 struct bnx2_irq *irq;
5746 int rc = 0, i;
8e6a72c4 5747
f86e82fb 5748 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6d866ffc
MC		 5749 flags = 0;
5750 else
5751 flags = IRQF_SHARED;
b4b36042
MC		 5752
5753 for (i = 0; i < bp->irq_nvecs; i++) {
5754 irq = &bp->irq_tbl[i];
c76c0475 5755 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
f0ea2e63 5756 &bp->bnx2_napi[i]);
b4b36042
MC		 5757 if (rc)
5758 break;
5759 irq->requested = 1;
5760 }
8e6a72c4
MC		 5761 return rc;
5762}
5763
5764static void
5765bnx2_free_irq(struct bnx2 *bp)
5766{
b4b36042
MC		 5767 struct bnx2_irq *irq;
5768 int i;
8e6a72c4 5769
b4b36042
MC		 5770 for (i = 0; i < bp->irq_nvecs; i++) {
5771 irq = &bp->irq_tbl[i];
5772 if (irq->requested)
f0ea2e63 5773 free_irq(irq->vector, &bp->bnx2_napi[i]);
b4b36042 5774 irq->requested = 0;
6d866ffc 5775 }
f86e82fb 5776 if (bp->flags & BNX2_FLAG_USING_MSI)
b4b36042 5777 pci_disable_msi(bp->pdev);
f86e82fb 5778 else if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 5779 pci_disable_msix(bp->pdev);
5780
f86e82fb 5781 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
b4b36042
MC		 5782}
5783
5784static void
5e9ad9e1 5785bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
b4b36042 5786{
57851d84
MC		 5787 int i, rc;
5788 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5789
b4b36042
MC		 5790 bnx2_setup_msix_tbl(bp);
5791 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5792 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5793 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
57851d84
MC		 5794
5795 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5796 msix_ent[i].entry = i;
5797 msix_ent[i].vector = 0;
35e9010b
MC		 5798
5799 strcpy(bp->irq_tbl[i].name, bp->dev->name);
f0ea2e63 5800 bp->irq_tbl[i].handler = bnx2_msi_1shot;
57851d84
MC		 5801 }
5802
5803 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5804 if (rc != 0)
5805 return;
5806
5e9ad9e1 5807 bp->irq_nvecs = msix_vecs;
f86e82fb 5808 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
57851d84
MC		 5809 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5810 bp->irq_tbl[i].vector = msix_ent[i].vector;
6d866ffc
MC		 5811}
5812
5813static void
5814bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5815{
5e9ad9e1 5816 int cpus = num_online_cpus();
706bf240 5817 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
5e9ad9e1 5818
6d866ffc
MC		 5819 bp->irq_tbl[0].handler = bnx2_interrupt;
5820 strcpy(bp->irq_tbl[0].name, bp->dev->name);
b4b36042
MC		 5821 bp->irq_nvecs = 1;
5822 bp->irq_tbl[0].vector = bp->pdev->irq;
5823
5e9ad9e1
MC		 5824 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
5825 bnx2_enable_msix(bp, msix_vecs);
6d866ffc 5826
f86e82fb
DM		 5827 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5828 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6d866ffc 5829 if (pci_enable_msi(bp->pdev) == 0) {
f86e82fb 5830 bp->flags |= BNX2_FLAG_USING_MSI;
6d866ffc 5831 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
f86e82fb 5832 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6d866ffc
MC		 5833 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5834 } else
5835 bp->irq_tbl[0].handler = bnx2_msi;
b4b36042
MC		 5836
5837 bp->irq_tbl[0].vector = bp->pdev->irq;
6d866ffc
MC		 5838 }
5839 }
706bf240
BL		 5840
5841 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
5842 bp->dev->real_num_tx_queues = bp->num_tx_rings;
5843
5e9ad9e1 5844 bp->num_rx_rings = bp->irq_nvecs;
8e6a72c4
MC		 5845}
5846
b6016b76
MC		 5847/* Called with rtnl_lock */
5848static int
5849bnx2_open(struct net_device *dev)
5850{
972ec0d4 5851 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5852 int rc;
5853
1b2f922f
MC		 5854 netif_carrier_off(dev);
5855
829ca9a3 5856 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 5857 bnx2_disable_int(bp);
5858
35e9010b
MC		 5859 bnx2_setup_int_mode(bp, disable_msi);
5860 bnx2_napi_enable(bp);
b6016b76 5861 rc = bnx2_alloc_mem(bp);
2739a8bb
MC		 5862 if (rc)
5863 goto open_err;
b6016b76 5864
8e6a72c4 5865 rc = bnx2_request_irq(bp);
2739a8bb
MC		 5866 if (rc)
5867 goto open_err;
b6016b76 5868
9a120bc5 5869 rc = bnx2_init_nic(bp, 1);
2739a8bb
MC		 5870 if (rc)
5871 goto open_err;
6aa20a22 5872
cd339a0e 5873 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 5874
5875 atomic_set(&bp->intr_sem, 0);
5876
5877 bnx2_enable_int(bp);
5878
f86e82fb 5879 if (bp->flags & BNX2_FLAG_USING_MSI) {
b6016b76
MC		 5880 /* Test MSI to make sure it is working
5881 * If MSI test fails, go back to INTx mode
5882 */
5883 if (bnx2_test_intr(bp) != 0) {
5884 printk(KERN_WARNING PFX "%s: No interrupt was generated"
5885 " using MSI, switching to INTx mode. Please"
5886 " report this failure to the PCI maintainer"
5887 " and include system chipset information.\n",
5888 bp->dev->name);
5889
5890 bnx2_disable_int(bp);
8e6a72c4 5891 bnx2_free_irq(bp);
b6016b76 5892
6d866ffc
MC		 5893 bnx2_setup_int_mode(bp, 1);
5894
9a120bc5 5895 rc = bnx2_init_nic(bp, 0);
b6016b76 5896
8e6a72c4
MC		 5897 if (!rc)
5898 rc = bnx2_request_irq(bp);
5899
b6016b76 5900 if (rc) {
b6016b76 5901 del_timer_sync(&bp->timer);
2739a8bb 5902 goto open_err;
b6016b76
MC		 5903 }
5904 bnx2_enable_int(bp);
5905 }
5906 }
f86e82fb 5907 if (bp->flags & BNX2_FLAG_USING_MSI)
b6016b76 5908 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
f86e82fb 5909 else if (bp->flags & BNX2_FLAG_USING_MSIX)
57851d84 5910 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
b6016b76 5911
706bf240 5912 netif_tx_start_all_queues(dev);
b6016b76
MC		 5913
5914 return 0;
2739a8bb
MC		 5915
5916open_err:
5917 bnx2_napi_disable(bp);
5918 bnx2_free_skbs(bp);
5919 bnx2_free_irq(bp);
5920 bnx2_free_mem(bp);
5921 return rc;
b6016b76
MC		 5922}
5923
5924static void
c4028958 5925bnx2_reset_task(struct work_struct *work)
b6016b76 5926{
c4028958 5927 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
b6016b76 5928
afdc08b9
MC		 5929 if (!netif_running(bp->dev))
5930 return;
5931
b6016b76
MC		 5932 bnx2_netif_stop(bp);
5933
9a120bc5 5934 bnx2_init_nic(bp, 1);
b6016b76
MC		 5935
5936 atomic_set(&bp->intr_sem, 1);
5937 bnx2_netif_start(bp);
5938}
5939
5940static void
5941bnx2_tx_timeout(struct net_device *dev)
5942{
972ec0d4 5943 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5944
5945 /* This allows the netif to be shutdown gracefully before resetting */
5946 schedule_work(&bp->reset_task);
5947}
5948
5949#ifdef BCM_VLAN
5950/* Called with rtnl_lock */
5951static void
5952bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5953{
972ec0d4 5954 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5955
5956 bnx2_netif_stop(bp);
5957
5958 bp->vlgrp = vlgrp;
5959 bnx2_set_rx_mode(dev);
7c62e83b
MC		 5960 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
5961 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
b6016b76
MC		 5962
5963 bnx2_netif_start(bp);
5964}
b6016b76
MC		 5965#endif
5966
932ff279 5967/* Called with netif_tx_lock.
2f8af120
MC		 5968 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5969 * netif_wake_queue().
b6016b76
MC		 5970 */
5971static int
5972bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5973{
972ec0d4 5974 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5975 dma_addr_t mapping;
5976 struct tx_bd *txbd;
3d16af86 5977 struct sw_tx_bd *tx_buf;
b6016b76
MC		 5978 u32 len, vlan_tag_flags, last_frag, mss;
5979 u16 prod, ring_prod;
5980 int i;
706bf240
BL		 5981 struct bnx2_napi *bnapi;
5982 struct bnx2_tx_ring_info *txr;
5983 struct netdev_queue *txq;
3d16af86 5984 struct skb_shared_info *sp;
706bf240
BL		 5985
5986 /* Determine which tx ring we will be placed on */
5987 i = skb_get_queue_mapping(skb);
5988 bnapi = &bp->bnx2_napi[i];
5989 txr = &bnapi->tx_ring;
5990 txq = netdev_get_tx_queue(dev, i);
b6016b76 5991
35e9010b 5992 if (unlikely(bnx2_tx_avail(bp, txr) <
a550c99b 5993 (skb_shinfo(skb)->nr_frags + 1))) {
706bf240 5994 netif_tx_stop_queue(txq);
b6016b76
MC		 5995 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5996 dev->name);
5997
5998 return NETDEV_TX_BUSY;
5999 }
6000 len = skb_headlen(skb);
35e9010b 6001 prod = txr->tx_prod;
b6016b76
MC		 6002 ring_prod = TX_RING_IDX(prod);
6003
6004 vlan_tag_flags = 0;
84fa7933 6005 if (skb->ip_summed == CHECKSUM_PARTIAL) {
b6016b76
MC		 6006 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6007 }
6008
729b85cd 6009#ifdef BCM_VLAN
79ea13ce 6010 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
b6016b76
MC		 6011 vlan_tag_flags |=
6012 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6013 }
729b85cd 6014#endif
fde82055 6015 if ((mss = skb_shinfo(skb)->gso_size)) {
a1efb4b6 6016 u32 tcp_opt_len;
eddc9ec5 6017 struct iphdr *iph;
b6016b76 6018
b6016b76
MC		 6019 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6020
4666f87a
MC		 6021 tcp_opt_len = tcp_optlen(skb);
6022
6023 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6024 u32 tcp_off = skb_transport_offset(skb) -
6025 sizeof(struct ipv6hdr) - ETH_HLEN;
ab6a5bb6 6026
4666f87a
MC		 6027 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6028 TX_BD_FLAGS_SW_FLAGS;
6029 if (likely(tcp_off == 0))
6030 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6031 else {
6032 tcp_off >>= 3;
6033 vlan_tag_flags |= ((tcp_off & 0x3) <<
6034 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6035 ((tcp_off & 0x10) <<
6036 TX_BD_FLAGS_TCP6_OFF4_SHL);
6037 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6038 }
6039 } else {
4666f87a 6040 iph = ip_hdr(skb);
4666f87a
MC		 6041 if (tcp_opt_len || (iph->ihl > 5)) {
6042 vlan_tag_flags |= ((iph->ihl - 5) +
6043 (tcp_opt_len >> 2)) << 8;
6044 }
b6016b76 6045 }
4666f87a 6046 } else
b6016b76 6047 mss = 0;
b6016b76 6048
3d16af86
BL		 6049 if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
6050 dev_kfree_skb(skb);
6051 return NETDEV_TX_OK;
6052 }
6053
6054 sp = skb_shinfo(skb);
6055 mapping = sp->dma_maps[0];
6aa20a22 6056
35e9010b 6057 tx_buf = &txr->tx_buf_ring[ring_prod];
b6016b76 6058 tx_buf->skb = skb;
b6016b76 6059
35e9010b 6060 txbd = &txr->tx_desc_ring[ring_prod];
b6016b76
MC		 6061
6062 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6063 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6064 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6065 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6066
6067 last_frag = skb_shinfo(skb)->nr_frags;
6068
6069 for (i = 0; i < last_frag; i++) {
6070 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6071
6072 prod = NEXT_TX_BD(prod);
6073 ring_prod = TX_RING_IDX(prod);
35e9010b 6074 txbd = &txr->tx_desc_ring[ring_prod];
b6016b76
MC		 6075
6076 len = frag->size;
3d16af86 6077 mapping = sp->dma_maps[i + 1];
b6016b76
MC		 6078
6079 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6080 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6081 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6082 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6083
6084 }
6085 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6086
6087 prod = NEXT_TX_BD(prod);
35e9010b 6088 txr->tx_prod_bseq += skb->len;
b6016b76 6089
35e9010b
MC		 6090 REG_WR16(bp, txr->tx_bidx_addr, prod);
6091 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
b6016b76
MC		 6092
6093 mmiowb();
6094
35e9010b 6095 txr->tx_prod = prod;
b6016b76
MC		 6096 dev->trans_start = jiffies;
6097
35e9010b 6098 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
706bf240 6099 netif_tx_stop_queue(txq);
35e9010b 6100 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
706bf240 6101 netif_tx_wake_queue(txq);
b6016b76
MC		 6102 }
6103
6104 return NETDEV_TX_OK;
6105}
6106
6107/* Called with rtnl_lock */
6108static int
6109bnx2_close(struct net_device *dev)
6110{
972ec0d4 6111 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6112
4bb073c0 6113 cancel_work_sync(&bp->reset_task);
afdc08b9 6114
bea3348e 6115 bnx2_disable_int_sync(bp);
35efa7c1 6116 bnx2_napi_disable(bp);
b6016b76 6117 del_timer_sync(&bp->timer);
74bf4ba3 6118 bnx2_shutdown_chip(bp);
8e6a72c4 6119 bnx2_free_irq(bp);
b6016b76
MC		 6120 bnx2_free_skbs(bp);
6121 bnx2_free_mem(bp);
6122 bp->link_up = 0;
6123 netif_carrier_off(bp->dev);
829ca9a3 6124 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 6125 return 0;
6126}
6127
6128#define GET_NET_STATS64(ctr) \
6129 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
6130 (unsigned long) (ctr##_lo)
6131
6132#define GET_NET_STATS32(ctr) \
6133 (ctr##_lo)
6134
6135#if (BITS_PER_LONG == 64)
6136#define GET_NET_STATS GET_NET_STATS64
6137#else
6138#define GET_NET_STATS GET_NET_STATS32
6139#endif
6140
6141static struct net_device_stats *
6142bnx2_get_stats(struct net_device *dev)
6143{
972ec0d4 6144 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6145 struct statistics_block *stats_blk = bp->stats_blk;
6146 struct net_device_stats *net_stats = &bp->net_stats;
6147
6148 if (bp->stats_blk == NULL) {
6149 return net_stats;
6150 }
6151 net_stats->rx_packets =
6152 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
6153 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
6154 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
6155
6156 net_stats->tx_packets =
6157 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
6158 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
6159 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
6160
6161 net_stats->rx_bytes =
6162 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
6163
6164 net_stats->tx_bytes =
6165 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
6166
6aa20a22 6167 net_stats->multicast =
b6016b76
MC		 6168 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
6169
6aa20a22 6170 net_stats->collisions =
b6016b76
MC		 6171 (unsigned long) stats_blk->stat_EtherStatsCollisions;
6172
6aa20a22 6173 net_stats->rx_length_errors =
b6016b76
MC		 6174 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
6175 stats_blk->stat_EtherStatsOverrsizePkts);
6176
6aa20a22 6177 net_stats->rx_over_errors =
b6016b76
MC		 6178 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
6179
6aa20a22 6180 net_stats->rx_frame_errors =
b6016b76
MC		 6181 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
6182
6aa20a22 6183 net_stats->rx_crc_errors =
b6016b76
MC		 6184 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
6185
6186 net_stats->rx_errors = net_stats->rx_length_errors +
6187 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6188 net_stats->rx_crc_errors;
6189
6190 net_stats->tx_aborted_errors =
6191 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
6192 stats_blk->stat_Dot3StatsLateCollisions);
6193
5b0c76ad
MC		 6194 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6195 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76
MC		 6196 net_stats->tx_carrier_errors = 0;
6197 else {
6198 net_stats->tx_carrier_errors =
6199 (unsigned long)
6200 stats_blk->stat_Dot3StatsCarrierSenseErrors;
6201 }
6202
6203 net_stats->tx_errors =
6aa20a22 6204 (unsigned long)
b6016b76
MC		 6205 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6206 +
6207 net_stats->tx_aborted_errors +
6208 net_stats->tx_carrier_errors;
6209
cea94db9
MC		 6210 net_stats->rx_missed_errors =
6211 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
6212 stats_blk->stat_FwRxDrop);
6213
b6016b76
MC		 6214 return net_stats;
6215}
6216
6217/* All ethtool functions called with rtnl_lock */
6218
6219static int
6220bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6221{
972ec0d4 6222 struct bnx2 *bp = netdev_priv(dev);
7b6b8347 6223 int support_serdes = 0, support_copper = 0;
b6016b76
MC		 6224
6225 cmd->supported = SUPPORTED_Autoneg;
583c28e5 6226 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6227 support_serdes = 1;
6228 support_copper = 1;
6229 } else if (bp->phy_port == PORT_FIBRE)
6230 support_serdes = 1;
6231 else
6232 support_copper = 1;
6233
6234 if (support_serdes) {
b6016b76
MC		 6235 cmd->supported |= SUPPORTED_1000baseT_Full |
6236 SUPPORTED_FIBRE;
583c28e5 6237 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
605a9e20 6238 cmd->supported |= SUPPORTED_2500baseX_Full;
b6016b76 6239
b6016b76 6240 }
7b6b8347 6241 if (support_copper) {
b6016b76
MC		 6242 cmd->supported |= SUPPORTED_10baseT_Half |
6243 SUPPORTED_10baseT_Full |
6244 SUPPORTED_100baseT_Half |
6245 SUPPORTED_100baseT_Full |
6246 SUPPORTED_1000baseT_Full |
6247 SUPPORTED_TP;
6248
b6016b76
MC		 6249 }
6250
7b6b8347
MC		 6251 spin_lock_bh(&bp->phy_lock);
6252 cmd->port = bp->phy_port;
b6016b76
MC		 6253 cmd->advertising = bp->advertising;
6254
6255 if (bp->autoneg & AUTONEG_SPEED) {
6256 cmd->autoneg = AUTONEG_ENABLE;
6257 }
6258 else {
6259 cmd->autoneg = AUTONEG_DISABLE;
6260 }
6261
6262 if (netif_carrier_ok(dev)) {
6263 cmd->speed = bp->line_speed;
6264 cmd->duplex = bp->duplex;
6265 }
6266 else {
6267 cmd->speed = -1;
6268 cmd->duplex = -1;
6269 }
7b6b8347 6270 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6271
6272 cmd->transceiver = XCVR_INTERNAL;
6273 cmd->phy_address = bp->phy_addr;
6274
6275 return 0;
6276}
6aa20a22 6277
b6016b76
MC		 6278static int
6279bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6280{
972ec0d4 6281 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6282 u8 autoneg = bp->autoneg;
6283 u8 req_duplex = bp->req_duplex;
6284 u16 req_line_speed = bp->req_line_speed;
6285 u32 advertising = bp->advertising;
7b6b8347
MC		 6286 int err = -EINVAL;
6287
6288 spin_lock_bh(&bp->phy_lock);
6289
6290 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6291 goto err_out_unlock;
6292
583c28e5
MC		 6293 if (cmd->port != bp->phy_port &&
6294 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
7b6b8347 6295 goto err_out_unlock;
b6016b76 6296
d6b14486
MC		 6297 /* If device is down, we can store the settings only if the user
6298 * is setting the currently active port.
6299 */
6300 if (!netif_running(dev) && cmd->port != bp->phy_port)
6301 goto err_out_unlock;
6302
b6016b76
MC		 6303 if (cmd->autoneg == AUTONEG_ENABLE) {
6304 autoneg |= AUTONEG_SPEED;
6305
6aa20a22 6306 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
b6016b76
MC		 6307
6308 /* allow advertising 1 speed */
6309 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6310 (cmd->advertising == ADVERTISED_10baseT_Full) ||
6311 (cmd->advertising == ADVERTISED_100baseT_Half) ||
6312 (cmd->advertising == ADVERTISED_100baseT_Full)) {
6313
7b6b8347
MC		 6314 if (cmd->port == PORT_FIBRE)
6315 goto err_out_unlock;
b6016b76
MC		 6316
6317 advertising = cmd->advertising;
6318
27a005b8 6319 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
583c28e5 6320 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
7b6b8347
MC		 6321 (cmd->port == PORT_TP))
6322 goto err_out_unlock;
6323 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
b6016b76 6324 advertising = cmd->advertising;
7b6b8347
MC		 6325 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6326 goto err_out_unlock;
b6016b76 6327 else {
7b6b8347 6328 if (cmd->port == PORT_FIBRE)
b6016b76 6329 advertising = ETHTOOL_ALL_FIBRE_SPEED;
7b6b8347 6330 else
b6016b76 6331 advertising = ETHTOOL_ALL_COPPER_SPEED;
b6016b76
MC		 6332 }
6333 advertising |= ADVERTISED_Autoneg;
6334 }
6335 else {
7b6b8347 6336 if (cmd->port == PORT_FIBRE) {
80be4434
MC		 6337 if ((cmd->speed != SPEED_1000 &&
6338 cmd->speed != SPEED_2500) ||
6339 (cmd->duplex != DUPLEX_FULL))
7b6b8347 6340 goto err_out_unlock;
80be4434
MC		 6341
6342 if (cmd->speed == SPEED_2500 &&
583c28e5 6343 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
7b6b8347 6344 goto err_out_unlock;
b6016b76 6345 }
7b6b8347
MC		 6346 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6347 goto err_out_unlock;
6348
b6016b76
MC		 6349 autoneg &= ~AUTONEG_SPEED;
6350 req_line_speed = cmd->speed;
6351 req_duplex = cmd->duplex;
6352 advertising = 0;
6353 }
6354
6355 bp->autoneg = autoneg;
6356 bp->advertising = advertising;
6357 bp->req_line_speed = req_line_speed;
6358 bp->req_duplex = req_duplex;
6359
d6b14486
MC		 6360 err = 0;
6361 /* If device is down, the new settings will be picked up when it is
6362 * brought up.
6363 */
6364 if (netif_running(dev))
6365 err = bnx2_setup_phy(bp, cmd->port);
b6016b76 6366
7b6b8347 6367err_out_unlock:
c770a65c 6368 spin_unlock_bh(&bp->phy_lock);
b6016b76 6369
7b6b8347 6370 return err;
b6016b76
MC		 6371}
6372
6373static void
6374bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6375{
972ec0d4 6376 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6377
6378 strcpy(info->driver, DRV_MODULE_NAME);
6379 strcpy(info->version, DRV_MODULE_VERSION);
6380 strcpy(info->bus_info, pci_name(bp->pdev));
58fc2ea4 6381 strcpy(info->fw_version, bp->fw_version);
b6016b76
MC		 6382}
6383
244ac4f4
MC		 6384#define BNX2_REGDUMP_LEN (32 * 1024)
6385
6386static int
6387bnx2_get_regs_len(struct net_device *dev)
6388{
6389 return BNX2_REGDUMP_LEN;
6390}
6391
6392static void
6393bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6394{
6395 u32 *p = _p, i, offset;
6396 u8 *orig_p = _p;
6397 struct bnx2 *bp = netdev_priv(dev);
6398 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6399 0x0800, 0x0880, 0x0c00, 0x0c10,
6400 0x0c30, 0x0d08, 0x1000, 0x101c,
6401 0x1040, 0x1048, 0x1080, 0x10a4,
6402 0x1400, 0x1490, 0x1498, 0x14f0,
6403 0x1500, 0x155c, 0x1580, 0x15dc,
6404 0x1600, 0x1658, 0x1680, 0x16d8,
6405 0x1800, 0x1820, 0x1840, 0x1854,
6406 0x1880, 0x1894, 0x1900, 0x1984,
6407 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6408 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6409 0x2000, 0x2030, 0x23c0, 0x2400,
6410 0x2800, 0x2820, 0x2830, 0x2850,
6411 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6412 0x3c00, 0x3c94, 0x4000, 0x4010,
6413 0x4080, 0x4090, 0x43c0, 0x4458,
6414 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6415 0x4fc0, 0x5010, 0x53c0, 0x5444,
6416 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6417 0x5fc0, 0x6000, 0x6400, 0x6428,
6418 0x6800, 0x6848, 0x684c, 0x6860,
6419 0x6888, 0x6910, 0x8000 };
6420
6421 regs->version = 0;
6422
6423 memset(p, 0, BNX2_REGDUMP_LEN);
6424
6425 if (!netif_running(bp->dev))
6426 return;
6427
6428 i = 0;
6429 offset = reg_boundaries[0];
6430 p += offset;
6431 while (offset < BNX2_REGDUMP_LEN) {
6432 *p++ = REG_RD(bp, offset);
6433 offset += 4;
6434 if (offset == reg_boundaries[i + 1]) {
6435 offset = reg_boundaries[i + 2];
6436 p = (u32 *) (orig_p + offset);
6437 i += 2;
6438 }
6439 }
6440}
6441
b6016b76
MC		 6442static void
6443bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6444{
972ec0d4 6445 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6446
f86e82fb 6447 if (bp->flags & BNX2_FLAG_NO_WOL) {
b6016b76
MC		 6448 wol->supported = 0;
6449 wol->wolopts = 0;
6450 }
6451 else {
6452 wol->supported = WAKE_MAGIC;
6453 if (bp->wol)
6454 wol->wolopts = WAKE_MAGIC;
6455 else
6456 wol->wolopts = 0;
6457 }
6458 memset(&wol->sopass, 0, sizeof(wol->sopass));
6459}
6460
6461static int
6462bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6463{
972ec0d4 6464 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6465
6466 if (wol->wolopts & ~WAKE_MAGIC)
6467 return -EINVAL;
6468
6469 if (wol->wolopts & WAKE_MAGIC) {
f86e82fb 6470 if (bp->flags & BNX2_FLAG_NO_WOL)
b6016b76
MC		 6471 return -EINVAL;
6472
6473 bp->wol = 1;
6474 }
6475 else {
6476 bp->wol = 0;
6477 }
6478 return 0;
6479}
6480
6481static int
6482bnx2_nway_reset(struct net_device *dev)
6483{
972ec0d4 6484 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6485 u32 bmcr;
6486
9f52b564
MC		 6487 if (!netif_running(dev))
6488 return -EAGAIN;
6489
b6016b76
MC		 6490 if (!(bp->autoneg & AUTONEG_SPEED)) {
6491 return -EINVAL;
6492 }
6493
c770a65c 6494 spin_lock_bh(&bp->phy_lock);
b6016b76 6495
583c28e5 6496 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6497 int rc;
6498
6499 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6500 spin_unlock_bh(&bp->phy_lock);
6501 return rc;
6502 }
6503
b6016b76 6504 /* Force a link down visible on the other side */
583c28e5 6505 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
ca58c3af 6506 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
c770a65c 6507 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6508
6509 msleep(20);
6510
c770a65c 6511 spin_lock_bh(&bp->phy_lock);
f8dd064e
MC		 6512
6513 bp->current_interval = SERDES_AN_TIMEOUT;
6514 bp->serdes_an_pending = 1;
6515 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6516 }
6517
ca58c3af 6518 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 6519 bmcr &= ~BMCR_LOOPBACK;
ca58c3af 6520 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
b6016b76 6521
c770a65c 6522 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6523
6524 return 0;
6525}
6526
6527static int
6528bnx2_get_eeprom_len(struct net_device *dev)
6529{
972ec0d4 6530 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6531
1122db71 6532 if (bp->flash_info == NULL)
b6016b76
MC		 6533 return 0;
6534
1122db71 6535 return (int) bp->flash_size;
b6016b76
MC		 6536}
6537
6538static int
6539bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6540 u8 *eebuf)
6541{
972ec0d4 6542 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6543 int rc;
6544
9f52b564
MC		 6545 if (!netif_running(dev))
6546 return -EAGAIN;
6547
1064e944 6548 /* parameters already validated in ethtool_get_eeprom */
b6016b76
MC		 6549
6550 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6551
6552 return rc;
6553}
6554
6555static int
6556bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6557 u8 *eebuf)
6558{
972ec0d4 6559 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6560 int rc;
6561
9f52b564
MC		 6562 if (!netif_running(dev))
6563 return -EAGAIN;
6564
1064e944 6565 /* parameters already validated in ethtool_set_eeprom */
b6016b76
MC		 6566
6567 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6568
6569 return rc;
6570}
6571
6572static int
6573bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6574{
972ec0d4 6575 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6576
6577 memset(coal, 0, sizeof(struct ethtool_coalesce));
6578
6579 coal->rx_coalesce_usecs = bp->rx_ticks;
6580 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6581 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6582 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6583
6584 coal->tx_coalesce_usecs = bp->tx_ticks;
6585 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6586 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6587 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6588
6589 coal->stats_block_coalesce_usecs = bp->stats_ticks;
6590
6591 return 0;
6592}
6593
6594static int
6595bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6596{
972ec0d4 6597 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6598
6599 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6600 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6601
6aa20a22 6602 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
b6016b76
MC		 6603 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6604
6605 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6606 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6607
6608 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6609 if (bp->rx_quick_cons_trip_int > 0xff)
6610 bp->rx_quick_cons_trip_int = 0xff;
6611
6612 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6613 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6614
6615 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6616 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6617
6618 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6619 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6620
6621 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6622 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6623 0xff;
6624
6625 bp->stats_ticks = coal->stats_block_coalesce_usecs;
02537b06
MC		 6626 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6627 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6628 bp->stats_ticks = USEC_PER_SEC;
6629 }
7ea6920e
MC		 6630 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6631 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6632 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76
MC		 6633
6634 if (netif_running(bp->dev)) {
6635 bnx2_netif_stop(bp);
9a120bc5 6636 bnx2_init_nic(bp, 0);
b6016b76
MC		 6637 bnx2_netif_start(bp);
6638 }
6639
6640 return 0;
6641}
6642
6643static void
6644bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6645{
972ec0d4 6646 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6647
13daffa2 6648 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
b6016b76 6649 ering->rx_mini_max_pending = 0;
47bf4246 6650 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
b6016b76
MC		 6651
6652 ering->rx_pending = bp->rx_ring_size;
6653 ering->rx_mini_pending = 0;
47bf4246 6654 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
b6016b76
MC		 6655
6656 ering->tx_max_pending = MAX_TX_DESC_CNT;
6657 ering->tx_pending = bp->tx_ring_size;
6658}
6659
6660static int
5d5d0015 6661bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
b6016b76 6662{
13daffa2
MC		 6663 if (netif_running(bp->dev)) {
6664 bnx2_netif_stop(bp);
6665 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6666 bnx2_free_skbs(bp);
6667 bnx2_free_mem(bp);
6668 }
6669
5d5d0015
MC		 6670 bnx2_set_rx_ring_size(bp, rx);
6671 bp->tx_ring_size = tx;
b6016b76
MC		 6672
6673 if (netif_running(bp->dev)) {
13daffa2
MC		 6674 int rc;
6675
6676 rc = bnx2_alloc_mem(bp);
6677 if (rc)
6678 return rc;
9a120bc5 6679 bnx2_init_nic(bp, 0);
b6016b76
MC		 6680 bnx2_netif_start(bp);
6681 }
b6016b76
MC		 6682 return 0;
6683}
6684
5d5d0015
MC		 6685static int
6686bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6687{
6688 struct bnx2 *bp = netdev_priv(dev);
6689 int rc;
6690
6691 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6692 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6693 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6694
6695 return -EINVAL;
6696 }
6697 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6698 return rc;
6699}
6700
b6016b76
MC		 6701static void
6702bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6703{
972ec0d4 6704 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6705
6706 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6707 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6708 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6709}
6710
6711static int
6712bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6713{
972ec0d4 6714 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6715
6716 bp->req_flow_ctrl = 0;
6717 if (epause->rx_pause)
6718 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6719 if (epause->tx_pause)
6720 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6721
6722 if (epause->autoneg) {
6723 bp->autoneg |= AUTONEG_FLOW_CTRL;
6724 }
6725 else {
6726 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6727 }
6728
9f52b564
MC		 6729 if (netif_running(dev)) {
6730 spin_lock_bh(&bp->phy_lock);
6731 bnx2_setup_phy(bp, bp->phy_port);
6732 spin_unlock_bh(&bp->phy_lock);
6733 }
b6016b76
MC		 6734
6735 return 0;
6736}
6737
6738static u32
6739bnx2_get_rx_csum(struct net_device *dev)
6740{
972ec0d4 6741 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6742
6743 return bp->rx_csum;
6744}
6745
6746static int
6747bnx2_set_rx_csum(struct net_device *dev, u32 data)
6748{
972ec0d4 6749 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6750
6751 bp->rx_csum = data;
6752 return 0;
6753}
6754
b11d6213
MC		 6755static int
6756bnx2_set_tso(struct net_device *dev, u32 data)
6757{
4666f87a
MC		 6758 struct bnx2 *bp = netdev_priv(dev);
6759
6760 if (data) {
b11d6213 6761 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
4666f87a
MC		 6762 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6763 dev->features |= NETIF_F_TSO6;
6764 } else
6765 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6766 NETIF_F_TSO_ECN);
b11d6213
MC		 6767 return 0;
6768}
6769
cea94db9 6770#define BNX2_NUM_STATS 46
b6016b76 6771
14ab9b86 6772static struct {
b6016b76
MC		 6773 char string[ETH_GSTRING_LEN];
6774} bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6775 { "rx_bytes" },
6776 { "rx_error_bytes" },
6777 { "tx_bytes" },
6778 { "tx_error_bytes" },
6779 { "rx_ucast_packets" },
6780 { "rx_mcast_packets" },
6781 { "rx_bcast_packets" },
6782 { "tx_ucast_packets" },
6783 { "tx_mcast_packets" },
6784 { "tx_bcast_packets" },
6785 { "tx_mac_errors" },
6786 { "tx_carrier_errors" },
6787 { "rx_crc_errors" },
6788 { "rx_align_errors" },
6789 { "tx_single_collisions" },
6790 { "tx_multi_collisions" },
6791 { "tx_deferred" },
6792 { "tx_excess_collisions" },
6793 { "tx_late_collisions" },
6794 { "tx_total_collisions" },
6795 { "rx_fragments" },
6796 { "rx_jabbers" },
6797 { "rx_undersize_packets" },
6798 { "rx_oversize_packets" },
6799 { "rx_64_byte_packets" },
6800 { "rx_65_to_127_byte_packets" },
6801 { "rx_128_to_255_byte_packets" },
6802 { "rx_256_to_511_byte_packets" },
6803 { "rx_512_to_1023_byte_packets" },
6804 { "rx_1024_to_1522_byte_packets" },
6805 { "rx_1523_to_9022_byte_packets" },
6806 { "tx_64_byte_packets" },
6807 { "tx_65_to_127_byte_packets" },
6808 { "tx_128_to_255_byte_packets" },
6809 { "tx_256_to_511_byte_packets" },
6810 { "tx_512_to_1023_byte_packets" },
6811 { "tx_1024_to_1522_byte_packets" },
6812 { "tx_1523_to_9022_byte_packets" },
6813 { "rx_xon_frames" },
6814 { "rx_xoff_frames" },
6815 { "tx_xon_frames" },
6816 { "tx_xoff_frames" },
6817 { "rx_mac_ctrl_frames" },
6818 { "rx_filtered_packets" },
6819 { "rx_discards" },
cea94db9 6820 { "rx_fw_discards" },
b6016b76
MC		 6821};
6822
6823#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6824
f71e1309 6825static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 6826 STATS_OFFSET32(stat_IfHCInOctets_hi),
6827 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6828 STATS_OFFSET32(stat_IfHCOutOctets_hi),
6829 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6830 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6831 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6832 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6833 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6834 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6835 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6836 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6aa20a22
JG		 6837 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6838 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6839 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6840 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6841 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6842 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6843 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6844 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6845 STATS_OFFSET32(stat_EtherStatsCollisions),
6846 STATS_OFFSET32(stat_EtherStatsFragments),
6847 STATS_OFFSET32(stat_EtherStatsJabbers),
6848 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6849 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6850 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6851 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6852 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6853 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6854 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6855 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6856 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6857 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6858 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6859 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6860 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6861 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6862 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6863 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6864 STATS_OFFSET32(stat_XonPauseFramesReceived),
6865 STATS_OFFSET32(stat_XoffPauseFramesReceived),
6866 STATS_OFFSET32(stat_OutXonSent),
6867 STATS_OFFSET32(stat_OutXoffSent),
6868 STATS_OFFSET32(stat_MacControlFramesReceived),
6869 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6870 STATS_OFFSET32(stat_IfInMBUFDiscards),
cea94db9 6871 STATS_OFFSET32(stat_FwRxDrop),
b6016b76
MC		 6872};
6873
6874/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6875 * skipped because of errata.
6aa20a22 6876 */
14ab9b86 6877static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 6878 8,0,8,8,8,8,8,8,8,8,
6879 4,0,4,4,4,4,4,4,4,4,
6880 4,4,4,4,4,4,4,4,4,4,
6881 4,4,4,4,4,4,4,4,4,4,
cea94db9 6882 4,4,4,4,4,4,
b6016b76
MC		 6883};
6884
5b0c76ad
MC		 6885static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6886 8,0,8,8,8,8,8,8,8,8,
6887 4,4,4,4,4,4,4,4,4,4,
6888 4,4,4,4,4,4,4,4,4,4,
6889 4,4,4,4,4,4,4,4,4,4,
cea94db9 6890 4,4,4,4,4,4,
5b0c76ad
MC		 6891};
6892
b6016b76
MC		 6893#define BNX2_NUM_TESTS 6
6894
14ab9b86 6895static struct {
b6016b76
MC		 6896 char string[ETH_GSTRING_LEN];
6897} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6898 { "register_test (offline)" },
6899 { "memory_test (offline)" },
6900 { "loopback_test (offline)" },
6901 { "nvram_test (online)" },
6902 { "interrupt_test (online)" },
6903 { "link_test (online)" },
6904};
6905
6906static int
b9f2c044 6907bnx2_get_sset_count(struct net_device *dev, int sset)
b6016b76 6908{
b9f2c044
JG		 6909 switch (sset) {
6910 case ETH_SS_TEST:
6911 return BNX2_NUM_TESTS;
6912 case ETH_SS_STATS:
6913 return BNX2_NUM_STATS;
6914 default:
6915 return -EOPNOTSUPP;
6916 }
b6016b76
MC		 6917}
6918
6919static void
6920bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6921{
972ec0d4 6922 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6923
9f52b564
MC		 6924 bnx2_set_power_state(bp, PCI_D0);
6925
b6016b76
MC		 6926 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6927 if (etest->flags & ETH_TEST_FL_OFFLINE) {
80be4434
MC		 6928 int i;
6929
b6016b76
MC		 6930 bnx2_netif_stop(bp);
6931 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6932 bnx2_free_skbs(bp);
6933
6934 if (bnx2_test_registers(bp) != 0) {
6935 buf[0] = 1;
6936 etest->flags |= ETH_TEST_FL_FAILED;
6937 }
6938 if (bnx2_test_memory(bp) != 0) {
6939 buf[1] = 1;
6940 etest->flags |= ETH_TEST_FL_FAILED;
6941 }
bc5a0690 6942 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
b6016b76 6943 etest->flags |= ETH_TEST_FL_FAILED;
b6016b76 6944
9f52b564
MC		 6945 if (!netif_running(bp->dev))
6946 bnx2_shutdown_chip(bp);
b6016b76 6947 else {
9a120bc5 6948 bnx2_init_nic(bp, 1);
b6016b76
MC		 6949 bnx2_netif_start(bp);
6950 }
6951
6952 /* wait for link up */
80be4434
MC		 6953 for (i = 0; i < 7; i++) {
6954 if (bp->link_up)
6955 break;
6956 msleep_interruptible(1000);
6957 }
b6016b76
MC		 6958 }
6959
6960 if (bnx2_test_nvram(bp) != 0) {
6961 buf[3] = 1;
6962 etest->flags |= ETH_TEST_FL_FAILED;
6963 }
6964 if (bnx2_test_intr(bp) != 0) {
6965 buf[4] = 1;
6966 etest->flags |= ETH_TEST_FL_FAILED;
6967 }
6968
6969 if (bnx2_test_link(bp) != 0) {
6970 buf[5] = 1;
6971 etest->flags |= ETH_TEST_FL_FAILED;
6972
6973 }
9f52b564
MC		 6974 if (!netif_running(bp->dev))
6975 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 6976}
6977
6978static void
6979bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6980{
6981 switch (stringset) {
6982 case ETH_SS_STATS:
6983 memcpy(buf, bnx2_stats_str_arr,
6984 sizeof(bnx2_stats_str_arr));
6985 break;
6986 case ETH_SS_TEST:
6987 memcpy(buf, bnx2_tests_str_arr,
6988 sizeof(bnx2_tests_str_arr));
6989 break;
6990 }
6991}
6992
b6016b76
MC		 6993static void
6994bnx2_get_ethtool_stats(struct net_device *dev,
6995 struct ethtool_stats *stats, u64 *buf)
6996{
972ec0d4 6997 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6998 int i;
6999 u32 *hw_stats = (u32 *) bp->stats_blk;
14ab9b86 7000 u8 *stats_len_arr = NULL;
b6016b76
MC		 7001
7002 if (hw_stats == NULL) {
7003 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7004 return;
7005 }
7006
5b0c76ad
MC		 7007 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7008 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7009 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7010 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76 7011 stats_len_arr = bnx2_5706_stats_len_arr;
5b0c76ad
MC		 7012 else
7013 stats_len_arr = bnx2_5708_stats_len_arr;
b6016b76
MC		 7014
7015 for (i = 0; i < BNX2_NUM_STATS; i++) {
7016 if (stats_len_arr[i] == 0) {
7017 /* skip this counter */
7018 buf[i] = 0;
7019 continue;
7020 }
7021 if (stats_len_arr[i] == 4) {
7022 /* 4-byte counter */
7023 buf[i] = (u64)
7024 *(hw_stats + bnx2_stats_offset_arr[i]);
7025 continue;
7026 }
7027 /* 8-byte counter */
7028 buf[i] = (((u64) *(hw_stats +
7029 bnx2_stats_offset_arr[i])) << 32) +
7030 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
7031 }
7032}
7033
7034static int
7035bnx2_phys_id(struct net_device *dev, u32 data)
7036{
972ec0d4 7037 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7038 int i;
7039 u32 save;
7040
9f52b564
MC		 7041 bnx2_set_power_state(bp, PCI_D0);
7042
b6016b76
MC		 7043 if (data == 0)
7044 data = 2;
7045
7046 save = REG_RD(bp, BNX2_MISC_CFG);
7047 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7048
7049 for (i = 0; i < (data * 2); i++) {
7050 if ((i % 2) == 0) {
7051 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7052 }
7053 else {
7054 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7055 BNX2_EMAC_LED_1000MB_OVERRIDE |
7056 BNX2_EMAC_LED_100MB_OVERRIDE |
7057 BNX2_EMAC_LED_10MB_OVERRIDE |
7058 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7059 BNX2_EMAC_LED_TRAFFIC);
7060 }
7061 msleep_interruptible(500);
7062 if (signal_pending(current))
7063 break;
7064 }
7065 REG_WR(bp, BNX2_EMAC_LED, 0);
7066 REG_WR(bp, BNX2_MISC_CFG, save);
9f52b564
MC		 7067
7068 if (!netif_running(dev))
7069 bnx2_set_power_state(bp, PCI_D3hot);
7070
b6016b76
MC		 7071 return 0;
7072}
7073
4666f87a
MC		 7074static int
7075bnx2_set_tx_csum(struct net_device *dev, u32 data)
7076{
7077 struct bnx2 *bp = netdev_priv(dev);
7078
7079 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6460d948 7080 return (ethtool_op_set_tx_ipv6_csum(dev, data));
4666f87a
MC		 7081 else
7082 return (ethtool_op_set_tx_csum(dev, data));
7083}
7084
7282d491 7085static const struct ethtool_ops bnx2_ethtool_ops = {
b6016b76
MC		 7086 .get_settings = bnx2_get_settings,
7087 .set_settings = bnx2_set_settings,
7088 .get_drvinfo = bnx2_get_drvinfo,
244ac4f4
MC		 7089 .get_regs_len = bnx2_get_regs_len,
7090 .get_regs = bnx2_get_regs,
b6016b76
MC		 7091 .get_wol = bnx2_get_wol,
7092 .set_wol = bnx2_set_wol,
7093 .nway_reset = bnx2_nway_reset,
7094 .get_link = ethtool_op_get_link,
7095 .get_eeprom_len = bnx2_get_eeprom_len,
7096 .get_eeprom = bnx2_get_eeprom,
7097 .set_eeprom = bnx2_set_eeprom,
7098 .get_coalesce = bnx2_get_coalesce,
7099 .set_coalesce = bnx2_set_coalesce,
7100 .get_ringparam = bnx2_get_ringparam,
7101 .set_ringparam = bnx2_set_ringparam,
7102 .get_pauseparam = bnx2_get_pauseparam,
7103 .set_pauseparam = bnx2_set_pauseparam,
7104 .get_rx_csum = bnx2_get_rx_csum,
7105 .set_rx_csum = bnx2_set_rx_csum,
4666f87a 7106 .set_tx_csum = bnx2_set_tx_csum,
b6016b76 7107 .set_sg = ethtool_op_set_sg,
b11d6213 7108 .set_tso = bnx2_set_tso,
b6016b76
MC		 7109 .self_test = bnx2_self_test,
7110 .get_strings = bnx2_get_strings,
7111 .phys_id = bnx2_phys_id,
b6016b76 7112 .get_ethtool_stats = bnx2_get_ethtool_stats,
b9f2c044 7113 .get_sset_count = bnx2_get_sset_count,
b6016b76
MC		 7114};
7115
7116/* Called with rtnl_lock */
7117static int
7118bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7119{
14ab9b86 7120 struct mii_ioctl_data *data = if_mii(ifr);
972ec0d4 7121 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7122 int err;
7123
7124 switch(cmd) {
7125 case SIOCGMIIPHY:
7126 data->phy_id = bp->phy_addr;
7127
7128 /* fallthru */
7129 case SIOCGMIIREG: {
7130 u32 mii_regval;
7131
583c28e5 7132 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 7133 return -EOPNOTSUPP;
7134
dad3e452
MC		 7135 if (!netif_running(dev))
7136 return -EAGAIN;
7137
c770a65c 7138 spin_lock_bh(&bp->phy_lock);
b6016b76 7139 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
c770a65c 7140 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7141
7142 data->val_out = mii_regval;
7143
7144 return err;
7145 }
7146
7147 case SIOCSMIIREG:
7148 if (!capable(CAP_NET_ADMIN))
7149 return -EPERM;
7150
583c28e5 7151 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 7152 return -EOPNOTSUPP;
7153
dad3e452
MC		 7154 if (!netif_running(dev))
7155 return -EAGAIN;
7156
c770a65c 7157 spin_lock_bh(&bp->phy_lock);
b6016b76 7158 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
c770a65c 7159 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7160
7161 return err;
7162
7163 default:
7164 /* do nothing */
7165 break;
7166 }
7167 return -EOPNOTSUPP;
7168}
7169
7170/* Called with rtnl_lock */
7171static int
7172bnx2_change_mac_addr(struct net_device *dev, void *p)
7173{
7174 struct sockaddr *addr = p;
972ec0d4 7175 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7176
73eef4cd
MC		 7177 if (!is_valid_ether_addr(addr->sa_data))
7178 return -EINVAL;
7179
b6016b76
MC		 7180 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7181 if (netif_running(dev))
5fcaed01 7182 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 7183
7184 return 0;
7185}
7186
7187/* Called with rtnl_lock */
7188static int
7189bnx2_change_mtu(struct net_device *dev, int new_mtu)
7190{
972ec0d4 7191 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7192
7193 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7194 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7195 return -EINVAL;
7196
7197 dev->mtu = new_mtu;
5d5d0015 7198 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
b6016b76
MC		 7199}
7200
7201#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7202static void
7203poll_bnx2(struct net_device *dev)
7204{
972ec0d4 7205 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7206
7207 disable_irq(bp->pdev->irq);
7d12e780 7208 bnx2_interrupt(bp->pdev->irq, dev);
b6016b76
MC		 7209 enable_irq(bp->pdev->irq);
7210}
7211#endif
7212
253c8b75
MC		 7213static void __devinit
7214bnx2_get_5709_media(struct bnx2 *bp)
7215{
7216 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7217 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7218 u32 strap;
7219
7220 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7221 return;
7222 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
583c28e5 7223 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7224 return;
7225 }
7226
7227 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7228 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7229 else
7230 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7231
7232 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7233 switch (strap) {
7234 case 0x4:
7235 case 0x5:
7236 case 0x6:
583c28e5 7237 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7238 return;
7239 }
7240 } else {
7241 switch (strap) {
7242 case 0x1:
7243 case 0x2:
7244 case 0x4:
583c28e5 7245 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7246 return;
7247 }
7248 }
7249}
7250
883e5151
MC		 7251static void __devinit
7252bnx2_get_pci_speed(struct bnx2 *bp)
7253{
7254 u32 reg;
7255
7256 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7257 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7258 u32 clkreg;
7259
f86e82fb 7260 bp->flags |= BNX2_FLAG_PCIX;
883e5151
MC		 7261
7262 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7263
7264 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7265 switch (clkreg) {
7266 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7267 bp->bus_speed_mhz = 133;
7268 break;
7269
7270 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7271 bp->bus_speed_mhz = 100;
7272 break;
7273
7274 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7275 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7276 bp->bus_speed_mhz = 66;
7277 break;
7278
7279 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7280 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7281 bp->bus_speed_mhz = 50;
7282 break;
7283
7284 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7285 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7286 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7287 bp->bus_speed_mhz = 33;
7288 break;
7289 }
7290 }
7291 else {
7292 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7293 bp->bus_speed_mhz = 66;
7294 else
7295 bp->bus_speed_mhz = 33;
7296 }
7297
7298 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
f86e82fb 7299 bp->flags |= BNX2_FLAG_PCI_32BIT;
883e5151
MC		 7300
7301}
7302
b6016b76
MC		 7303static int __devinit
7304bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7305{
7306 struct bnx2 *bp;
7307 unsigned long mem_len;
58fc2ea4 7308 int rc, i, j;
b6016b76 7309 u32 reg;
40453c83 7310 u64 dma_mask, persist_dma_mask;
b6016b76 7311
b6016b76 7312 SET_NETDEV_DEV(dev, &pdev->dev);
972ec0d4 7313 bp = netdev_priv(dev);
b6016b76
MC		 7314
7315 bp->flags = 0;
7316 bp->phy_flags = 0;
7317
7318 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7319 rc = pci_enable_device(pdev);
7320 if (rc) {
898eb71c 7321 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
b6016b76
MC		 7322 goto err_out;
7323 }
7324
7325 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9b91cf9d 7326 dev_err(&pdev->dev,
2e8a538d 7327 "Cannot find PCI device base address, aborting.\n");
b6016b76
MC		 7328 rc = -ENODEV;
7329 goto err_out_disable;
7330 }
7331
7332 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7333 if (rc) {
9b91cf9d 7334 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
b6016b76
MC		 7335 goto err_out_disable;
7336 }
7337
7338 pci_set_master(pdev);
6ff2da49 7339 pci_save_state(pdev);
b6016b76
MC		 7340
7341 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7342 if (bp->pm_cap == 0) {
9b91cf9d 7343 dev_err(&pdev->dev,
2e8a538d 7344 "Cannot find power management capability, aborting.\n");
b6016b76
MC		 7345 rc = -EIO;
7346 goto err_out_release;
7347 }
7348
b6016b76
MC		 7349 bp->dev = dev;
7350 bp->pdev = pdev;
7351
7352 spin_lock_init(&bp->phy_lock);
1b8227c4 7353 spin_lock_init(&bp->indirect_lock);
c4028958 7354 INIT_WORK(&bp->reset_task, bnx2_reset_task);
b6016b76
MC		 7355
7356 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
706bf240 7357 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS);
b6016b76
MC		 7358 dev->mem_end = dev->mem_start + mem_len;
7359 dev->irq = pdev->irq;
7360
7361 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7362
7363 if (!bp->regview) {
9b91cf9d 7364 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
b6016b76
MC		 7365 rc = -ENOMEM;
7366 goto err_out_release;
7367 }
7368
7369 /* Configure byte swap and enable write to the reg_window registers.
7370 * Rely on CPU to do target byte swapping on big endian systems
7371 * The chip's target access swapping will not swap all accesses
7372 */
7373 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7374 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7375 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7376
829ca9a3 7377 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 7378
7379 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7380
883e5151
MC		 7381 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7382 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7383 dev_err(&pdev->dev,
7384 "Cannot find PCIE capability, aborting.\n");
7385 rc = -EIO;
7386 goto err_out_unmap;
7387 }
f86e82fb 7388 bp->flags |= BNX2_FLAG_PCIE;
2dd201d7 7389 if (CHIP_REV(bp) == CHIP_REV_Ax)
f86e82fb 7390 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
883e5151 7391 } else {
59b47d8a
MC		 7392 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7393 if (bp->pcix_cap == 0) {
7394 dev_err(&pdev->dev,
7395 "Cannot find PCIX capability, aborting.\n");
7396 rc = -EIO;
7397 goto err_out_unmap;
7398 }
7399 }
7400
b4b36042
MC		 7401 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7402 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
f86e82fb 7403 bp->flags |= BNX2_FLAG_MSIX_CAP;
b4b36042
MC		 7404 }
7405
8e6a72c4
MC		 7406 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7407 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
f86e82fb 7408 bp->flags |= BNX2_FLAG_MSI_CAP;
8e6a72c4
MC		 7409 }
7410
40453c83
MC		 7411 /* 5708 cannot support DMA addresses > 40-bit. */
7412 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7413 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
7414 else
7415 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
7416
7417 /* Configure DMA attributes. */
7418 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7419 dev->features |= NETIF_F_HIGHDMA;
7420 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7421 if (rc) {
7422 dev_err(&pdev->dev,
7423 "pci_set_consistent_dma_mask failed, aborting.\n");
7424 goto err_out_unmap;
7425 }
7426 } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7427 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7428 goto err_out_unmap;
7429 }
7430
f86e82fb 7431 if (!(bp->flags & BNX2_FLAG_PCIE))
883e5151 7432 bnx2_get_pci_speed(bp);
b6016b76
MC		 7433
7434 /* 5706A0 may falsely detect SERR and PERR. */
7435 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7436 reg = REG_RD(bp, PCI_COMMAND);
7437 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7438 REG_WR(bp, PCI_COMMAND, reg);
7439 }
7440 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
f86e82fb 7441 !(bp->flags & BNX2_FLAG_PCIX)) {
b6016b76 7442
9b91cf9d 7443 dev_err(&pdev->dev,
2e8a538d 7444 "5706 A1 can only be used in a PCIX bus, aborting.\n");
b6016b76
MC		 7445 goto err_out_unmap;
7446 }
7447
7448 bnx2_init_nvram(bp);
7449
2726d6e1 7450 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
e3648b3d
MC		 7451
7452 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
24cb230b
MC		 7453 BNX2_SHM_HDR_SIGNATURE_SIG) {
7454 u32 off = PCI_FUNC(pdev->devfn) << 2;
7455
2726d6e1 7456 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
24cb230b 7457 } else
e3648b3d
MC		 7458 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7459
b6016b76
MC		 7460 /* Get the permanent MAC address. First we need to make sure the
7461 * firmware is actually running.
7462 */
2726d6e1 7463 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
b6016b76
MC		 7464
7465 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7466 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
9b91cf9d 7467 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
b6016b76
MC		 7468 rc = -ENODEV;
7469 goto err_out_unmap;
7470 }
7471
2726d6e1 7472 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
58fc2ea4
MC		 7473 for (i = 0, j = 0; i < 3; i++) {
7474 u8 num, k, skip0;
7475
7476 num = (u8) (reg >> (24 - (i * 8)));
7477 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7478 if (num >= k || !skip0 || k == 1) {
7479 bp->fw_version[j++] = (num / k) + '0';
7480 skip0 = 0;
7481 }
7482 }
7483 if (i != 2)
7484 bp->fw_version[j++] = '.';
7485 }
2726d6e1 7486 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
846f5c62
MC		 7487 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7488 bp->wol = 1;
7489
7490 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
f86e82fb 7491 bp->flags |= BNX2_FLAG_ASF_ENABLE;
c2d3db8c
MC		 7492
7493 for (i = 0; i < 30; i++) {
2726d6e1 7494 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
c2d3db8c
MC		 7495 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7496 break;
7497 msleep(10);
7498 }
7499 }
2726d6e1 7500 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
58fc2ea4
MC		 7501 reg &= BNX2_CONDITION_MFW_RUN_MASK;
7502 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7503 reg != BNX2_CONDITION_MFW_RUN_NONE) {
2726d6e1 7504 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
58fc2ea4
MC		 7505
7506 bp->fw_version[j++] = ' ';
7507 for (i = 0; i < 3; i++) {
2726d6e1 7508 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
58fc2ea4
MC		 7509 reg = swab32(reg);
7510 memcpy(&bp->fw_version[j], &reg, 4);
7511 j += 4;
7512 }
7513 }
b6016b76 7514
2726d6e1 7515 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
b6016b76
MC		 7516 bp->mac_addr[0] = (u8) (reg >> 8);
7517 bp->mac_addr[1] = (u8) reg;
7518
2726d6e1 7519 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
b6016b76
MC		 7520 bp->mac_addr[2] = (u8) (reg >> 24);
7521 bp->mac_addr[3] = (u8) (reg >> 16);
7522 bp->mac_addr[4] = (u8) (reg >> 8);
7523 bp->mac_addr[5] = (u8) reg;
7524
7525 bp->tx_ring_size = MAX_TX_DESC_CNT;
932f3772 7526 bnx2_set_rx_ring_size(bp, 255);
b6016b76
MC		 7527
7528 bp->rx_csum = 1;
7529
b6016b76
MC		 7530 bp->tx_quick_cons_trip_int = 20;
7531 bp->tx_quick_cons_trip = 20;
7532 bp->tx_ticks_int = 80;
7533 bp->tx_ticks = 80;
6aa20a22 7534
b6016b76
MC		 7535 bp->rx_quick_cons_trip_int = 6;
7536 bp->rx_quick_cons_trip = 6;
7537 bp->rx_ticks_int = 18;
7538 bp->rx_ticks = 18;
7539
7ea6920e 7540 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76 7541
ac392abc 7542 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 7543
5b0c76ad
MC		 7544 bp->phy_addr = 1;
7545
b6016b76 7546 /* Disable WOL support if we are running on a SERDES chip. */
253c8b75
MC		 7547 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7548 bnx2_get_5709_media(bp);
7549 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
583c28e5 7550 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
bac0dff6 7551
0d8a6571 7552 bp->phy_port = PORT_TP;
583c28e5 7553 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 7554 bp->phy_port = PORT_FIBRE;
2726d6e1 7555 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
846f5c62 7556 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
f86e82fb 7557 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 7558 bp->wol = 0;
7559 }
38ea3686
MC		 7560 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7561 /* Don't do parallel detect on this board because of
7562 * some board problems. The link will not go down
7563 * if we do parallel detect.
7564 */
7565 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7566 pdev->subsystem_device == 0x310c)
7567 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7568 } else {
5b0c76ad 7569 bp->phy_addr = 2;
5b0c76ad 7570 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
583c28e5 7571 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
5b0c76ad 7572 }
261dd5ca
MC		 7573 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7574 CHIP_NUM(bp) == CHIP_NUM_5708)
583c28e5 7575 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
fb0c18bd
MC		 7576 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7577 (CHIP_REV(bp) == CHIP_REV_Ax ||
7578 CHIP_REV(bp) == CHIP_REV_Bx))
583c28e5 7579 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
b6016b76 7580
7c62e83b
MC		 7581 bnx2_init_fw_cap(bp);
7582
16088272
MC		 7583 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7584 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
846f5c62 7585 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
f86e82fb 7586 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 7587 bp->wol = 0;
7588 }
dda1e390 7589
b6016b76
MC		 7590 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7591 bp->tx_quick_cons_trip_int =
7592 bp->tx_quick_cons_trip;
7593 bp->tx_ticks_int = bp->tx_ticks;
7594 bp->rx_quick_cons_trip_int =
7595 bp->rx_quick_cons_trip;
7596 bp->rx_ticks_int = bp->rx_ticks;
7597 bp->comp_prod_trip_int = bp->comp_prod_trip;
7598 bp->com_ticks_int = bp->com_ticks;
7599 bp->cmd_ticks_int = bp->cmd_ticks;
7600 }
7601
f9317a40
MC		 7602 /* Disable MSI on 5706 if AMD 8132 bridge is found.
7603 *
7604 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
7605 * with byte enables disabled on the unused 32-bit word. This is legal
7606 * but causes problems on the AMD 8132 which will eventually stop
7607 * responding after a while.
7608 *
7609 * AMD believes this incompatibility is unique to the 5706, and
88187dfa 7610 * prefers to locally disable MSI rather than globally disabling it.
f9317a40
MC		 7611 */
7612 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7613 struct pci_dev *amd_8132 = NULL;
7614
7615 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7616 PCI_DEVICE_ID_AMD_8132_BRIDGE,
7617 amd_8132))) {
f9317a40 7618
44c10138
AK		 7619 if (amd_8132->revision >= 0x10 &&
7620 amd_8132->revision <= 0x13) {
f9317a40
MC		 7621 disable_msi = 1;
7622 pci_dev_put(amd_8132);
7623 break;
7624 }
7625 }
7626 }
7627
deaf391b 7628 bnx2_set_default_link(bp);
b6016b76
MC		 7629 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7630
cd339a0e 7631 init_timer(&bp->timer);
ac392abc 7632 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
cd339a0e
MC		 7633 bp->timer.data = (unsigned long) bp;
7634 bp->timer.function = bnx2_timer;
7635
b6016b76
MC		 7636 return 0;
7637
7638err_out_unmap:
7639 if (bp->regview) {
7640 iounmap(bp->regview);
73eef4cd 7641 bp->regview = NULL;
b6016b76
MC		 7642 }
7643
7644err_out_release:
7645 pci_release_regions(pdev);
7646
7647err_out_disable:
7648 pci_disable_device(pdev);
7649 pci_set_drvdata(pdev, NULL);
7650
7651err_out:
7652 return rc;
7653}
7654
883e5151
MC		 7655static char * __devinit
7656bnx2_bus_string(struct bnx2 *bp, char *str)
7657{
7658 char *s = str;
7659
f86e82fb 7660 if (bp->flags & BNX2_FLAG_PCIE) {
883e5151
MC		 7661 s += sprintf(s, "PCI Express");
7662 } else {
7663 s += sprintf(s, "PCI");
f86e82fb 7664 if (bp->flags & BNX2_FLAG_PCIX)
883e5151 7665 s += sprintf(s, "-X");
f86e82fb 7666 if (bp->flags & BNX2_FLAG_PCI_32BIT)
883e5151
MC		 7667 s += sprintf(s, " 32-bit");
7668 else
7669 s += sprintf(s, " 64-bit");
7670 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7671 }
7672 return str;
7673}
7674
2ba582b7 7675static void __devinit
35efa7c1
MC		 7676bnx2_init_napi(struct bnx2 *bp)
7677{
b4b36042 7678 int i;
35efa7c1 7679
b4b36042 7680 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
35e9010b
MC		 7681 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
7682 int (*poll)(struct napi_struct *, int);
7683
7684 if (i == 0)
7685 poll = bnx2_poll;
7686 else
f0ea2e63 7687 poll = bnx2_poll_msix;
35e9010b
MC		 7688
7689 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
b4b36042
MC		 7690 bnapi->bp = bp;
7691 }
35efa7c1
MC		 7692}
7693
b6016b76
MC		 7694static int __devinit
7695bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7696{
7697 static int version_printed = 0;
7698 struct net_device *dev = NULL;
7699 struct bnx2 *bp;
0795af57 7700 int rc;
883e5151 7701 char str[40];
b6016b76
MC		 7702
7703 if (version_printed++ == 0)
7704 printk(KERN_INFO "%s", version);
7705
7706 /* dev zeroed in init_etherdev */
706bf240 7707 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
b6016b76
MC		 7708
7709 if (!dev)
7710 return -ENOMEM;
7711
7712 rc = bnx2_init_board(pdev, dev);
7713 if (rc < 0) {
7714 free_netdev(dev);
7715 return rc;
7716 }
7717
7718 dev->open = bnx2_open;
7719 dev->hard_start_xmit = bnx2_start_xmit;
7720 dev->stop = bnx2_close;
7721 dev->get_stats = bnx2_get_stats;
5fcaed01 7722 dev->set_rx_mode = bnx2_set_rx_mode;
b6016b76
MC		 7723 dev->do_ioctl = bnx2_ioctl;
7724 dev->set_mac_address = bnx2_change_mac_addr;
7725 dev->change_mtu = bnx2_change_mtu;
7726 dev->tx_timeout = bnx2_tx_timeout;
7727 dev->watchdog_timeo = TX_TIMEOUT;
7728#ifdef BCM_VLAN
7729 dev->vlan_rx_register = bnx2_vlan_rx_register;
b6016b76 7730#endif
b6016b76 7731 dev->ethtool_ops = &bnx2_ethtool_ops;
b6016b76 7732
972ec0d4 7733 bp = netdev_priv(dev);
35efa7c1 7734 bnx2_init_napi(bp);
b6016b76
MC		 7735
7736#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7737 dev->poll_controller = poll_bnx2;
7738#endif
7739
1b2f922f
MC		 7740 pci_set_drvdata(pdev, dev);
7741
7742 memcpy(dev->dev_addr, bp->mac_addr, 6);
7743 memcpy(dev->perm_addr, bp->mac_addr, 6);
1b2f922f 7744
d212f87b 7745 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
4666f87a 7746 if (CHIP_NUM(bp) == CHIP_NUM_5709)
d212f87b
SH		 7747 dev->features |= NETIF_F_IPV6_CSUM;
7748
1b2f922f
MC		 7749#ifdef BCM_VLAN
7750 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7751#endif
7752 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
4666f87a
MC		 7753 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7754 dev->features |= NETIF_F_TSO6;
1b2f922f 7755
b6016b76 7756 if ((rc = register_netdev(dev))) {
9b91cf9d 7757 dev_err(&pdev->dev, "Cannot register net device\n");
b6016b76
MC		 7758 if (bp->regview)
7759 iounmap(bp->regview);
7760 pci_release_regions(pdev);
7761 pci_disable_device(pdev);
7762 pci_set_drvdata(pdev, NULL);
7763 free_netdev(dev);
7764 return rc;
7765 }
7766
883e5151 7767 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
e174961c 7768 "IRQ %d, node addr %pM\n",
b6016b76 7769 dev->name,
fbbf68b7 7770 board_info[ent->driver_data].name,
b6016b76
MC		 7771 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7772 ((CHIP_ID(bp) & 0x0ff0) >> 4),
883e5151 7773 bnx2_bus_string(bp, str),
b6016b76 7774 dev->base_addr,
e174961c 7775 bp->pdev->irq, dev->dev_addr);
b6016b76 7776
b6016b76
MC		 7777 return 0;
7778}
7779
7780static void __devexit
7781bnx2_remove_one(struct pci_dev *pdev)
7782{
7783 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 7784 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7785
afdc08b9
MC		 7786 flush_scheduled_work();
7787
b6016b76
MC		 7788 unregister_netdev(dev);
7789
7790 if (bp->regview)
7791 iounmap(bp->regview);
7792
7793 free_netdev(dev);
7794 pci_release_regions(pdev);
7795 pci_disable_device(pdev);
7796 pci_set_drvdata(pdev, NULL);
7797}
7798
7799static int
829ca9a3 7800bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
b6016b76
MC		 7801{
7802 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 7803 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7804
6caebb02
MC		 7805 /* PCI register 4 needs to be saved whether netif_running() or not.
7806 * MSI address and data need to be saved if using MSI and
7807 * netif_running().
7808 */
7809 pci_save_state(pdev);
b6016b76
MC		 7810 if (!netif_running(dev))
7811 return 0;
7812
1d60290f 7813 flush_scheduled_work();
b6016b76
MC		 7814 bnx2_netif_stop(bp);
7815 netif_device_detach(dev);
7816 del_timer_sync(&bp->timer);
74bf4ba3 7817 bnx2_shutdown_chip(bp);
b6016b76 7818 bnx2_free_skbs(bp);
829ca9a3 7819 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
b6016b76
MC		 7820 return 0;
7821}
7822
7823static int
7824bnx2_resume(struct pci_dev *pdev)
7825{
7826 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 7827 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7828
6caebb02 7829 pci_restore_state(pdev);
b6016b76
MC		 7830 if (!netif_running(dev))
7831 return 0;
7832
829ca9a3 7833 bnx2_set_power_state(bp, PCI_D0);
b6016b76 7834 netif_device_attach(dev);
9a120bc5 7835 bnx2_init_nic(bp, 1);
b6016b76
MC		 7836 bnx2_netif_start(bp);
7837 return 0;
7838}
7839
6ff2da49
WX		 7840/**
7841 * bnx2_io_error_detected - called when PCI error is detected
7842 * @pdev: Pointer to PCI device
7843 * @state: The current pci connection state
7844 *
7845 * This function is called after a PCI bus error affecting
7846 * this device has been detected.
7847 */
7848static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
7849 pci_channel_state_t state)
7850{
7851 struct net_device *dev = pci_get_drvdata(pdev);
7852 struct bnx2 *bp = netdev_priv(dev);
7853
7854 rtnl_lock();
7855 netif_device_detach(dev);
7856
7857 if (netif_running(dev)) {
7858 bnx2_netif_stop(bp);
7859 del_timer_sync(&bp->timer);
7860 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
7861 }
7862
7863 pci_disable_device(pdev);
7864 rtnl_unlock();
7865
7866 /* Request a slot slot reset. */
7867 return PCI_ERS_RESULT_NEED_RESET;
7868}
7869
7870/**
7871 * bnx2_io_slot_reset - called after the pci bus has been reset.
7872 * @pdev: Pointer to PCI device
7873 *
7874 * Restart the card from scratch, as if from a cold-boot.
7875 */
7876static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
7877{
7878 struct net_device *dev = pci_get_drvdata(pdev);
7879 struct bnx2 *bp = netdev_priv(dev);
7880
7881 rtnl_lock();
7882 if (pci_enable_device(pdev)) {
7883 dev_err(&pdev->dev,
7884 "Cannot re-enable PCI device after reset.\n");
7885 rtnl_unlock();
7886 return PCI_ERS_RESULT_DISCONNECT;
7887 }
7888 pci_set_master(pdev);
7889 pci_restore_state(pdev);
7890
7891 if (netif_running(dev)) {
7892 bnx2_set_power_state(bp, PCI_D0);
7893 bnx2_init_nic(bp, 1);
7894 }
7895
7896 rtnl_unlock();
7897 return PCI_ERS_RESULT_RECOVERED;
7898}
7899
7900/**
7901 * bnx2_io_resume - called when traffic can start flowing again.
7902 * @pdev: Pointer to PCI device
7903 *
7904 * This callback is called when the error recovery driver tells us that
7905 * its OK to resume normal operation.
7906 */
7907static void bnx2_io_resume(struct pci_dev *pdev)
7908{
7909 struct net_device *dev = pci_get_drvdata(pdev);
7910 struct bnx2 *bp = netdev_priv(dev);
7911
7912 rtnl_lock();
7913 if (netif_running(dev))
7914 bnx2_netif_start(bp);
7915
7916 netif_device_attach(dev);
7917 rtnl_unlock();
7918}
7919
7920static struct pci_error_handlers bnx2_err_handler = {
7921 .error_detected = bnx2_io_error_detected,
7922 .slot_reset = bnx2_io_slot_reset,
7923 .resume = bnx2_io_resume,
7924};
7925
b6016b76 7926static struct pci_driver bnx2_pci_driver = {
14ab9b86
PH		 7927 .name = DRV_MODULE_NAME,
7928 .id_table = bnx2_pci_tbl,
7929 .probe = bnx2_init_one,
7930 .remove = __devexit_p(bnx2_remove_one),
7931 .suspend = bnx2_suspend,
7932 .resume = bnx2_resume,
6ff2da49 7933 .err_handler = &bnx2_err_handler,
b6016b76
MC		 7934};
7935
7936static int __init bnx2_init(void)
7937{
29917620 7938 return pci_register_driver(&bnx2_pci_driver);
b6016b76
MC		 7939}
7940
7941static void __exit bnx2_cleanup(void)
7942{
7943 pci_unregister_driver(&bnx2_pci_driver);
7944}
7945
7946module_init(bnx2_init);
7947module_exit(bnx2_cleanup);
7948
7949
7950
Linux kernel - Deliverables
This page took 1.085776 seconds and 5 git commands to generate.