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a2fbb9ea ET |
1 | /* bnx2x_fw_defs.h: Broadcom Everest network driver. |
2 | * | |
f1410647 | 3 | * Copyright (c) 2007-2008 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | ||
11 | #define CSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\ | |
12 | (0x1922 + (port * 0x40) + (index * 0x4)) | |
13 | #define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\ | |
14 | (0x1900 + (port * 0x40)) | |
15 | #define CSTORM_HC_BTR_OFFSET(port)\ | |
16 | (0x1984 + (port * 0xc0)) | |
17 | #define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index)\ | |
18 | (0x141a + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4)) | |
19 | #define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index)\ | |
20 | (0x1418 + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4)) | |
21 | #define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id)\ | |
22 | (0x1400 + (port * 0x280) + (cpu_id * 0x28)) | |
23 | #define CSTORM_STATS_FLAGS_OFFSET(port) (0x5108 + (port * 0x8)) | |
24 | #define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id)\ | |
25 | (0x1510 + (port * 0x240) + (client_id * 0x20)) | |
26 | #define TSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\ | |
27 | (0x138a + (port * 0x28) + (index * 0x4)) | |
28 | #define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\ | |
29 | (0x1370 + (port * 0x28)) | |
30 | #define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port)\ | |
31 | (0x4b70 + (port * 0x8)) | |
32 | #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function)\ | |
33 | (0x1418 + (function * 0x30)) | |
34 | #define TSTORM_HC_BTR_OFFSET(port)\ | |
35 | (0x13c4 + (port * 0x18)) | |
36 | #define TSTORM_INDIRECTION_TABLE_OFFSET(port)\ | |
37 | (0x22c8 + (port * 0x80)) | |
38 | #define TSTORM_INDIRECTION_TABLE_SIZE 0x80 | |
39 | #define TSTORM_MAC_FILTER_CONFIG_OFFSET(port)\ | |
40 | (0x1420 + (port * 0x30)) | |
41 | #define TSTORM_RCQ_PROD_OFFSET(port, client_id)\ | |
42 | (0x1508 + (port * 0x240) + (client_id * 0x20)) | |
43 | #define TSTORM_STATS_FLAGS_OFFSET(port) (0x4b90 + (port * 0x8)) | |
44 | #define USTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\ | |
45 | (0x191a + (port * 0x28) + (index * 0x4)) | |
46 | #define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\ | |
47 | (0x1900 + (port * 0x28)) | |
48 | #define USTORM_HC_BTR_OFFSET(port)\ | |
49 | (0x1954 + (port * 0xb8)) | |
50 | #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(port)\ | |
51 | (0x5408 + (port * 0x8)) | |
52 | #define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index)\ | |
53 | (0x141a + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4)) | |
54 | #define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index)\ | |
55 | (0x1418 + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4)) | |
56 | #define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id)\ | |
57 | (0x1400 + (port * 0x280) + (cpu_id * 0x28)) | |
58 | #define XSTORM_ASSERT_LIST_INDEX_OFFSET 0x1000 | |
59 | #define XSTORM_ASSERT_LIST_OFFSET(idx) (0x1020 + (idx * 0x10)) | |
60 | #define XSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\ | |
61 | (0x141a + (port * 0x28) + (index * 0x4)) | |
62 | #define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\ | |
63 | (0x1400 + (port * 0x28)) | |
64 | #define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port)\ | |
65 | (0x5408 + (port * 0x8)) | |
66 | #define XSTORM_HC_BTR_OFFSET(port)\ | |
67 | (0x1454 + (port * 0x18)) | |
68 | #define XSTORM_SPQ_PAGE_BASE_OFFSET(port)\ | |
69 | (0x5328 + (port * 0x18)) | |
70 | #define XSTORM_SPQ_PROD_OFFSET(port)\ | |
71 | (0x5330 + (port * 0x18)) | |
72 | #define XSTORM_STATS_FLAGS_OFFSET(port) (0x53f8 + (port * 0x8)) | |
73 | #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0 | |
74 | ||
75 | /** | |
76 | * This file defines HSI constatnts for the ETH flow | |
77 | */ | |
78 | ||
79 | /* hash types */ | |
80 | #define DEFAULT_HASH_TYPE 0 | |
81 | #define IPV4_HASH_TYPE 1 | |
82 | #define TCP_IPV4_HASH_TYPE 2 | |
83 | #define IPV6_HASH_TYPE 3 | |
84 | #define TCP_IPV6_HASH_TYPE 4 | |
85 | ||
86 | /* values of command IDs in the ramrod message */ | |
87 | #define RAMROD_CMD_ID_ETH_PORT_SETUP (80) | |
88 | #define RAMROD_CMD_ID_ETH_CLIENT_SETUP (85) | |
89 | #define RAMROD_CMD_ID_ETH_STAT_QUERY (90) | |
90 | #define RAMROD_CMD_ID_ETH_UPDATE (100) | |
91 | #define RAMROD_CMD_ID_ETH_HALT (105) | |
92 | #define RAMROD_CMD_ID_ETH_SET_MAC (110) | |
93 | #define RAMROD_CMD_ID_ETH_CFC_DEL (115) | |
94 | #define RAMROD_CMD_ID_ETH_PORT_DEL (120) | |
95 | #define RAMROD_CMD_ID_ETH_FORWARD_SETUP (125) | |
96 | ||
97 | ||
98 | /* command values for set mac command */ | |
99 | #define T_ETH_MAC_COMMAND_SET 0 | |
100 | #define T_ETH_MAC_COMMAND_INVALIDATE 1 | |
101 | ||
102 | #define T_ETH_INDIRECTION_TABLE_SIZE 128 | |
103 | ||
104 | /* Maximal L2 clients supported */ | |
105 | #define ETH_MAX_RX_CLIENTS (18) | |
106 | ||
107 | /** | |
108 | * This file defines HSI constatnts common to all microcode flows | |
109 | */ | |
110 | ||
111 | /* Connection types */ | |
112 | #define ETH_CONNECTION_TYPE 0 | |
113 | ||
114 | #define PROTOCOL_STATE_BIT_OFFSET 6 | |
115 | ||
116 | #define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) | |
117 | ||
118 | /* microcode fixed page page size 4K (chains and ring segments) */ | |
119 | #define MC_PAGE_SIZE (4096) | |
120 | ||
121 | /* Host coalescing constants */ | |
122 | ||
123 | /* IGU constants */ | |
124 | #define IGU_PORT_BASE 0x0400 | |
125 | ||
126 | #define IGU_ADDR_MSIX 0x0000 | |
127 | #define IGU_ADDR_INT_ACK 0x0200 | |
128 | #define IGU_ADDR_PROD_UPD 0x0201 | |
129 | #define IGU_ADDR_ATTN_BITS_UPD 0x0202 | |
130 | #define IGU_ADDR_ATTN_BITS_SET 0x0203 | |
131 | #define IGU_ADDR_ATTN_BITS_CLR 0x0204 | |
132 | #define IGU_ADDR_COALESCE_NOW 0x0205 | |
133 | #define IGU_ADDR_SIMD_MASK 0x0206 | |
134 | #define IGU_ADDR_SIMD_NOMASK 0x0207 | |
135 | #define IGU_ADDR_MSI_CTL 0x0210 | |
136 | #define IGU_ADDR_MSI_ADDR_LO 0x0211 | |
137 | #define IGU_ADDR_MSI_ADDR_HI 0x0212 | |
138 | #define IGU_ADDR_MSI_DATA 0x0213 | |
139 | ||
140 | #define IGU_INT_ENABLE 0 | |
141 | #define IGU_INT_DISABLE 1 | |
142 | #define IGU_INT_NOP 2 | |
143 | #define IGU_INT_NOP2 3 | |
144 | ||
145 | /* index numbers */ | |
146 | #define HC_USTORM_DEF_SB_NUM_INDICES 4 | |
147 | #define HC_CSTORM_DEF_SB_NUM_INDICES 8 | |
148 | #define HC_XSTORM_DEF_SB_NUM_INDICES 4 | |
149 | #define HC_TSTORM_DEF_SB_NUM_INDICES 4 | |
150 | #define HC_USTORM_SB_NUM_INDICES 4 | |
151 | #define HC_CSTORM_SB_NUM_INDICES 4 | |
152 | ||
153 | /* index values - which counterto update */ | |
154 | ||
155 | #define HC_INDEX_U_ETH_RX_CQ_CONS 1 | |
156 | ||
157 | #define HC_INDEX_C_ETH_TX_CQ_CONS 1 | |
158 | ||
159 | #define HC_INDEX_DEF_X_SPQ_CONS 0 | |
160 | ||
161 | #define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2 | |
162 | #define HC_INDEX_DEF_C_ETH_SLOW_PATH 3 | |
163 | ||
164 | /* used by the driver to get the SB offset */ | |
165 | #define USTORM_ID 0 | |
166 | #define CSTORM_ID 1 | |
167 | #define XSTORM_ID 2 | |
168 | #define TSTORM_ID 3 | |
169 | #define ATTENTION_ID 4 | |
170 | ||
171 | /* max number of slow path commands per port */ | |
172 | #define MAX_RAMRODS_PER_PORT (8) | |
173 | ||
174 | /* values for RX ETH CQE type field */ | |
175 | #define RX_ETH_CQE_TYPE_ETH_FASTPATH (0) | |
176 | #define RX_ETH_CQE_TYPE_ETH_RAMROD (1) | |
177 | ||
178 | /* MAC address list size */ | |
179 | #define T_MAC_ADDRESS_LIST_SIZE (96) | |
180 | ||
181 | #define XSTORM_IP_ID_ROLL_HALF 0x8000 | |
182 | #define XSTORM_IP_ID_ROLL_ALL 0 | |
183 | ||
184 | #define FW_LOG_LIST_SIZE (50) | |
185 | ||
186 | #define NUM_OF_PROTOCOLS 4 | |
187 | #define MAX_COS_NUMBER 16 | |
188 | #define MAX_T_STAT_COUNTER_ID 18 | |
189 | ||
190 | #define T_FAIR 1 | |
191 | #define FAIR_MEM 2 | |
192 | #define RS_PERIODIC_TIMEOUT_IN_SDM_TICS 25 | |
193 | ||
194 | #define UNKNOWN_ADDRESS 0 | |
195 | #define UNICAST_ADDRESS 1 | |
196 | #define MULTICAST_ADDRESS 2 | |
197 | #define BROADCAST_ADDRESS 3 | |
198 |