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a2fbb9ea ET |
1 | /* bnx2x_fw_defs.h: Broadcom Everest network driver. |
2 | * | |
f1410647 | 3 | * Copyright (c) 2007-2008 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | ||
34f80b04 | 11 | #define CSTORM_ASSERT_LIST_INDEX_OFFSET \ |
6378c025 | 12 | (IS_E1H_OFFSET ? 0x7000 : 0x1000) |
34f80b04 | 13 | #define CSTORM_ASSERT_LIST_OFFSET(idx) \ |
6378c025 | 14 | (IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) |
34f80b04 | 15 | #define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ |
6378c025 EG |
16 | (IS_E1H_OFFSET ? (0x8522 + ((function>>1) * 0x40) + \ |
17 | ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \ | |
18 | 0x40) + (index * 0x4))) | |
34f80b04 | 19 | #define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ |
6378c025 EG |
20 | (IS_E1H_OFFSET ? (0x8500 + ((function>>1) * 0x40) + \ |
21 | ((function&1) * 0x100)) : (0x1900 + (function * 0x40))) | |
34f80b04 | 22 | #define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ |
6378c025 EG |
23 | (IS_E1H_OFFSET ? (0x8508 + ((function>>1) * 0x40) + \ |
24 | ((function&1) * 0x100)) : (0x1908 + (function * 0x40))) | |
34f80b04 | 25 | #define CSTORM_FUNCTION_MODE_OFFSET \ |
6378c025 | 26 | (IS_E1H_OFFSET ? 0x11e8 : 0xffffffff) |
34f80b04 | 27 | #define CSTORM_HC_BTR_OFFSET(port) \ |
6378c025 | 28 | (IS_E1H_OFFSET ? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0))) |
34f80b04 | 29 | #define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \ |
6378c025 | 30 | (IS_E1H_OFFSET ? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \ |
34f80b04 EG |
31 | (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \ |
32 | (index * 0x4))) | |
33 | #define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \ | |
6378c025 | 34 | (IS_E1H_OFFSET ? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \ |
34f80b04 EG |
35 | (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \ |
36 | (index * 0x4))) | |
37 | #define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \ | |
6378c025 | 38 | (IS_E1H_OFFSET ? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \ |
34f80b04 EG |
39 | (0x1400 + (port * 0x280) + (cpu_id * 0x28))) |
40 | #define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \ | |
6378c025 | 41 | (IS_E1H_OFFSET ? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \ |
34f80b04 EG |
42 | (0x1408 + (port * 0x280) + (cpu_id * 0x28))) |
43 | #define CSTORM_STATS_FLAGS_OFFSET(function) \ | |
6378c025 | 44 | (IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \ |
34f80b04 EG |
45 | (function * 0x8))) |
46 | #define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \ | |
6378c025 | 47 | (IS_E1H_OFFSET ? (0x31c0 + (function * 0x20)) : 0xffffffff) |
34f80b04 | 48 | #define TSTORM_ASSERT_LIST_INDEX_OFFSET \ |
6378c025 | 49 | (IS_E1H_OFFSET ? 0xa000 : 0x1000) |
34f80b04 | 50 | #define TSTORM_ASSERT_LIST_OFFSET(idx) \ |
6378c025 | 51 | (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) |
34f80b04 | 52 | #define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \ |
8d9c5f34 EG |
53 | (IS_E1H_OFFSET ? (0x3350 + (port * 0x190) + (client_id * 0x10)) \ |
54 | : (0x9c0 + (port * 0x130) + (client_id * 0x10))) | |
55 | #define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \ | |
56 | (IS_E1H_OFFSET ? 0x1ad8 : 0xffffffff) | |
34f80b04 | 57 | #define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ |
6378c025 EG |
58 | (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \ |
59 | ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \ | |
60 | 0x28) + (index * 0x4))) | |
34f80b04 | 61 | #define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ |
6378c025 EG |
62 | (IS_E1H_OFFSET ? (0xb000 + ((function>>1) * 0x28) + \ |
63 | ((function&1) * 0xa0)) : (0x1400 + (function * 0x28))) | |
34f80b04 | 64 | #define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ |
6378c025 EG |
65 | (IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \ |
66 | ((function&1) * 0xa0)) : (0x1408 + (function * 0x28))) | |
34f80b04 | 67 | #define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ |
6378c025 | 68 | (IS_E1H_OFFSET ? (0x2b80 + (function * 0x8)) : (0x4b68 + \ |
34f80b04 EG |
69 | (function * 0x8))) |
70 | #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \ | |
6378c025 | 71 | (IS_E1H_OFFSET ? (0x3000 + (function * 0x38)) : (0x1500 + \ |
34f80b04 EG |
72 | (function * 0x38))) |
73 | #define TSTORM_FUNCTION_MODE_OFFSET \ | |
6378c025 | 74 | (IS_E1H_OFFSET ? 0x1ad0 : 0xffffffff) |
34f80b04 | 75 | #define TSTORM_HC_BTR_OFFSET(port) \ |
6378c025 | 76 | (IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18))) |
34f80b04 | 77 | #define TSTORM_INDIRECTION_TABLE_OFFSET(function) \ |
6378c025 | 78 | (IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \ |
34f80b04 EG |
79 | (function * 0x80))) |
80 | #define TSTORM_INDIRECTION_TABLE_SIZE 0x80 | |
81 | #define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \ | |
6378c025 | 82 | (IS_E1H_OFFSET ? (0x3008 + (function * 0x38)) : (0x1508 + \ |
34f80b04 | 83 | (function * 0x38))) |
66e855f3 YG |
84 | #define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ |
85 | (IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \ | |
8d9c5f34 | 86 | 0x50)) : (0x4080 + (port * 0x5b0) + (stats_counter_id * 0x50))) |
34f80b04 | 87 | #define TSTORM_STATS_FLAGS_OFFSET(function) \ |
6378c025 | 88 | (IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \ |
34f80b04 | 89 | (function * 0x8))) |
8d9c5f34 | 90 | #define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3680 : 0x1c20) |
6378c025 EG |
91 | #define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa040 : 0x2c10) |
92 | #define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2440 : 0x1200) | |
34f80b04 | 93 | #define USTORM_ASSERT_LIST_INDEX_OFFSET \ |
8d9c5f34 | 94 | (IS_E1H_OFFSET ? 0x8960 : 0x1000) |
34f80b04 | 95 | #define USTORM_ASSERT_LIST_OFFSET(idx) \ |
8d9c5f34 | 96 | (IS_E1H_OFFSET ? (0x8980 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) |
34f80b04 | 97 | #define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \ |
8d9c5f34 EG |
98 | (IS_E1H_OFFSET ? (0x8018 + (port * 0x4b0) + (clientId * 0x30)) : \ |
99 | (0x5330 + (port * 0x260) + (clientId * 0x20))) | |
34f80b04 | 100 | #define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ |
8d9c5f34 EG |
101 | (IS_E1H_OFFSET ? (0x9522 + ((function>>1) * 0x40) + \ |
102 | ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \ | |
103 | 0x40) + (index * 0x4))) | |
34f80b04 | 104 | #define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ |
8d9c5f34 EG |
105 | (IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x40) + \ |
106 | ((function&1) * 0x100)) : (0x1900 + (function * 0x40))) | |
34f80b04 | 107 | #define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ |
8d9c5f34 EG |
108 | (IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x40) + \ |
109 | ((function&1) * 0x100)) : (0x1908 + (function * 0x40))) | |
34f80b04 | 110 | #define USTORM_FUNCTION_MODE_OFFSET \ |
6378c025 | 111 | (IS_E1H_OFFSET ? 0x2448 : 0xffffffff) |
34f80b04 | 112 | #define USTORM_HC_BTR_OFFSET(port) \ |
8d9c5f34 | 113 | (IS_E1H_OFFSET ? (0x9704 + (port * 0xf0)) : (0x1984 + (port * 0xc0))) |
34f80b04 | 114 | #define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \ |
8d9c5f34 EG |
115 | (IS_E1H_OFFSET ? (0x8010 + (port * 0x4b0) + (clientId * 0x30)) : \ |
116 | (0x5328 + (port * 0x260) + (clientId * 0x20))) | |
34f80b04 | 117 | #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \ |
8d9c5f34 | 118 | (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5308 + \ |
34f80b04 | 119 | (function * 0x8))) |
8d9c5f34 EG |
120 | #define USTORM_RX_PRODS_OFFSET(port, client_id) \ |
121 | (IS_E1H_OFFSET ? (0x8000 + (port * 0x4b0) + (client_id * 0x30)) \ | |
122 | : (0x5318 + (port * 0x260) + (client_id * 0x20))) | |
34f80b04 | 123 | #define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \ |
6378c025 | 124 | (IS_E1H_OFFSET ? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \ |
34f80b04 EG |
125 | (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \ |
126 | (index * 0x4))) | |
127 | #define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \ | |
6378c025 | 128 | (IS_E1H_OFFSET ? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \ |
34f80b04 EG |
129 | (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \ |
130 | (index * 0x4))) | |
131 | #define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \ | |
6378c025 | 132 | (IS_E1H_OFFSET ? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \ |
34f80b04 EG |
133 | (0x1400 + (port * 0x280) + (cpu_id * 0x28))) |
134 | #define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \ | |
6378c025 | 135 | (IS_E1H_OFFSET ? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \ |
34f80b04 EG |
136 | (0x1408 + (port * 0x280) + (cpu_id * 0x28))) |
137 | #define XSTORM_ASSERT_LIST_INDEX_OFFSET \ | |
6378c025 | 138 | (IS_E1H_OFFSET ? 0x9000 : 0x1000) |
34f80b04 | 139 | #define XSTORM_ASSERT_LIST_OFFSET(idx) \ |
6378c025 | 140 | (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) |
34f80b04 | 141 | #define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \ |
8d9c5f34 | 142 | (IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3ba0 + (port * 0x50))) |
34f80b04 | 143 | #define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ |
6378c025 EG |
144 | (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \ |
145 | ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \ | |
146 | 0x28) + (index * 0x4))) | |
34f80b04 | 147 | #define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ |
6378c025 EG |
148 | (IS_E1H_OFFSET ? (0xa000 + ((function>>1) * 0x28) + \ |
149 | ((function&1) * 0xa0)) : (0x1400 + (function * 0x28))) | |
34f80b04 | 150 | #define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ |
6378c025 EG |
151 | (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \ |
152 | ((function&1) * 0xa0)) : (0x1408 + (function * 0x28))) | |
34f80b04 | 153 | #define XSTORM_E1HOV_OFFSET(function) \ |
8d9c5f34 | 154 | (IS_E1H_OFFSET ? (0x2c10 + (function * 0x2)) : 0xffffffff) |
34f80b04 | 155 | #define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ |
6378c025 | 156 | (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3b70 + \ |
34f80b04 EG |
157 | (function * 0x8))) |
158 | #define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \ | |
8d9c5f34 EG |
159 | (IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3c80 + \ |
160 | (function * 0x90))) | |
34f80b04 | 161 | #define XSTORM_FUNCTION_MODE_OFFSET \ |
8d9c5f34 | 162 | (IS_E1H_OFFSET ? 0x2c20 : 0xffffffff) |
34f80b04 | 163 | #define XSTORM_HC_BTR_OFFSET(port) \ |
6378c025 | 164 | (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18))) |
66e855f3 YG |
165 | #define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ |
166 | (IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \ | |
167 | 0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38))) | |
34f80b04 | 168 | #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \ |
8d9c5f34 EG |
169 | (IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3c40 + \ |
170 | (function * 0x90))) | |
34f80b04 | 171 | #define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \ |
6378c025 | 172 | (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \ |
34f80b04 EG |
173 | (function * 0x10))) |
174 | #define XSTORM_SPQ_PROD_OFFSET(function) \ | |
6378c025 | 175 | (IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \ |
34f80b04 EG |
176 | (function * 0x10))) |
177 | #define XSTORM_STATS_FLAGS_OFFSET(function) \ | |
6378c025 | 178 | (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3b60 + \ |
34f80b04 | 179 | (function * 0x8))) |
a2fbb9ea ET |
180 | #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0 |
181 | ||
182 | /** | |
183 | * This file defines HSI constatnts for the ETH flow | |
184 | */ | |
34f80b04 EG |
185 | #ifdef _EVEREST_MICROCODE |
186 | #include "microcode_constants.h" | |
187 | #include "eth_rx_bd.h" | |
188 | #include "eth_tx_bd.h" | |
189 | #include "eth_rx_cqe.h" | |
190 | #include "eth_rx_sge.h" | |
191 | #include "eth_rx_cqe_next_page.h" | |
192 | #endif | |
193 | ||
194 | /* RSS hash types */ | |
195 | #define DEFAULT_HASH_TYPE 0 | |
196 | #define IPV4_HASH_TYPE 1 | |
197 | #define TCP_IPV4_HASH_TYPE 2 | |
198 | #define IPV6_HASH_TYPE 3 | |
199 | #define TCP_IPV6_HASH_TYPE 4 | |
200 | ||
201 | /* Ethernet Ring parmaters */ | |
202 | #define X_ETH_LOCAL_RING_SIZE 13 | |
203 | #define FIRST_BD_IN_PKT 0 | |
204 | #define PARSE_BD_INDEX 1 | |
205 | #define NUM_OF_ETH_BDS_IN_PAGE \ | |
206 | ((PAGE_SIZE) / (STRUCT_SIZE(eth_tx_bd)/8)) | |
207 | ||
208 | ||
209 | /* Rx ring params */ | |
210 | #define U_ETH_LOCAL_BD_RING_SIZE (16) | |
211 | #define U_ETH_LOCAL_SGE_RING_SIZE (12) | |
212 | #define U_ETH_SGL_SIZE (8) | |
213 | ||
214 | ||
215 | #define U_ETH_BDS_PER_PAGE_MASK \ | |
216 | ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))-1) | |
217 | #define U_ETH_CQE_PER_PAGE_MASK \ | |
218 | ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))-1) | |
219 | #define U_ETH_SGES_PER_PAGE_MASK \ | |
220 | ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))-1) | |
221 | ||
222 | #define U_ETH_SGES_PER_PAGE_INVERSE_MASK \ | |
223 | (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1)) | |
224 | ||
225 | ||
226 | #define TU_ETH_CQES_PER_PAGE \ | |
227 | (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe_next_page)/8)) | |
228 | #define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8)) | |
229 | #define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8)) | |
230 | ||
231 | #define U_ETH_UNDEFINED_Q 0xFF | |
a2fbb9ea ET |
232 | |
233 | /* values of command IDs in the ramrod message */ | |
34f80b04 EG |
234 | #define RAMROD_CMD_ID_ETH_PORT_SETUP (80) |
235 | #define RAMROD_CMD_ID_ETH_CLIENT_SETUP (85) | |
236 | #define RAMROD_CMD_ID_ETH_STAT_QUERY (90) | |
237 | #define RAMROD_CMD_ID_ETH_UPDATE (100) | |
238 | #define RAMROD_CMD_ID_ETH_HALT (105) | |
239 | #define RAMROD_CMD_ID_ETH_SET_MAC (110) | |
240 | #define RAMROD_CMD_ID_ETH_CFC_DEL (115) | |
241 | #define RAMROD_CMD_ID_ETH_PORT_DEL (120) | |
242 | #define RAMROD_CMD_ID_ETH_FORWARD_SETUP (125) | |
a2fbb9ea ET |
243 | |
244 | ||
245 | /* command values for set mac command */ | |
34f80b04 EG |
246 | #define T_ETH_MAC_COMMAND_SET 0 |
247 | #define T_ETH_MAC_COMMAND_INVALIDATE 1 | |
248 | ||
249 | #define T_ETH_INDIRECTION_TABLE_SIZE 128 | |
a2fbb9ea | 250 | |
34f80b04 EG |
251 | /*The CRC32 seed, that is used for the hash(reduction) multicast address */ |
252 | #define T_ETH_CRC32_HASH_SEED 0x00000000 | |
a2fbb9ea ET |
253 | |
254 | /* Maximal L2 clients supported */ | |
34f80b04 EG |
255 | #define ETH_MAX_RX_CLIENTS_E1 19 |
256 | #define ETH_MAX_RX_CLIENTS_E1H 25 | |
257 | ||
258 | /* Maximal aggregation queues supported */ | |
259 | #define ETH_MAX_AGGREGATION_QUEUES_E1 (32) | |
260 | #define ETH_MAX_AGGREGATION_QUEUES_E1H (64) | |
261 | ||
555f6c78 EG |
262 | /* ETH RSS modes */ |
263 | #define ETH_RSS_MODE_DISABLED 0 | |
264 | #define ETH_RSS_MODE_REGULAR 1 | |
265 | ||
a2fbb9ea ET |
266 | |
267 | /** | |
268 | * This file defines HSI constatnts common to all microcode flows | |
269 | */ | |
270 | ||
271 | /* Connection types */ | |
34f80b04 EG |
272 | #define ETH_CONNECTION_TYPE 0 |
273 | #define TOE_CONNECTION_TYPE 1 | |
274 | #define RDMA_CONNECTION_TYPE 2 | |
275 | #define ISCSI_CONNECTION_TYPE 3 | |
276 | #define FCOE_CONNECTION_TYPE 4 | |
277 | #define RESERVED_CONNECTION_TYPE_0 5 | |
278 | #define RESERVED_CONNECTION_TYPE_1 6 | |
279 | #define RESERVED_CONNECTION_TYPE_2 7 | |
280 | ||
a2fbb9ea | 281 | |
34f80b04 | 282 | #define PROTOCOL_STATE_BIT_OFFSET 6 |
a2fbb9ea | 283 | |
34f80b04 EG |
284 | #define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) |
285 | #define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) | |
286 | #define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) | |
a2fbb9ea ET |
287 | |
288 | /* microcode fixed page page size 4K (chains and ring segments) */ | |
34f80b04 | 289 | #define MC_PAGE_SIZE (4096) |
a2fbb9ea | 290 | |
a2fbb9ea | 291 | |
34f80b04 | 292 | /* Host coalescing constants */ |
a2fbb9ea ET |
293 | |
294 | /* index numbers */ | |
8d9c5f34 | 295 | #define HC_USTORM_DEF_SB_NUM_INDICES 8 |
34f80b04 EG |
296 | #define HC_CSTORM_DEF_SB_NUM_INDICES 8 |
297 | #define HC_XSTORM_DEF_SB_NUM_INDICES 4 | |
298 | #define HC_TSTORM_DEF_SB_NUM_INDICES 4 | |
299 | #define HC_USTORM_SB_NUM_INDICES 4 | |
300 | #define HC_CSTORM_SB_NUM_INDICES 4 | |
a2fbb9ea ET |
301 | |
302 | /* index values - which counterto update */ | |
303 | ||
34f80b04 EG |
304 | #define HC_INDEX_U_TOE_RX_CQ_CONS 0 |
305 | #define HC_INDEX_U_ETH_RX_CQ_CONS 1 | |
306 | #define HC_INDEX_U_ETH_RX_BD_CONS 2 | |
307 | #define HC_INDEX_U_FCOE_EQ_CONS 3 | |
308 | ||
309 | #define HC_INDEX_C_TOE_TX_CQ_CONS 0 | |
310 | #define HC_INDEX_C_ETH_TX_CQ_CONS 1 | |
311 | #define HC_INDEX_C_ISCSI_EQ_CONS 2 | |
312 | ||
313 | #define HC_INDEX_DEF_X_SPQ_CONS 0 | |
a2fbb9ea | 314 | |
34f80b04 EG |
315 | #define HC_INDEX_DEF_C_RDMA_EQ_CONS 0 |
316 | #define HC_INDEX_DEF_C_RDMA_NAL_PROD 1 | |
317 | #define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2 | |
318 | #define HC_INDEX_DEF_C_ETH_SLOW_PATH 3 | |
319 | #define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4 | |
320 | #define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5 | |
a2fbb9ea | 321 | |
34f80b04 EG |
322 | #define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0 |
323 | #define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1 | |
324 | #define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2 | |
325 | #define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3 | |
a2fbb9ea | 326 | |
a2fbb9ea ET |
327 | |
328 | /* used by the driver to get the SB offset */ | |
34f80b04 EG |
329 | #define USTORM_ID 0 |
330 | #define CSTORM_ID 1 | |
331 | #define XSTORM_ID 2 | |
332 | #define TSTORM_ID 3 | |
333 | #define ATTENTION_ID 4 | |
a2fbb9ea ET |
334 | |
335 | /* max number of slow path commands per port */ | |
34f80b04 | 336 | #define MAX_RAMRODS_PER_PORT (8) |
a2fbb9ea ET |
337 | |
338 | /* values for RX ETH CQE type field */ | |
34f80b04 EG |
339 | #define RX_ETH_CQE_TYPE_ETH_FASTPATH (0) |
340 | #define RX_ETH_CQE_TYPE_ETH_RAMROD (1) | |
341 | ||
342 | ||
343 | /**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ | |
344 | #define EMULATION_FREQUENCY_FACTOR (1600) | |
345 | #define FPGA_FREQUENCY_FACTOR (100) | |
346 | ||
347 | #define TIMERS_TICK_SIZE_CHIP (1e-3) | |
348 | #define TIMERS_TICK_SIZE_EMUL \ | |
349 | ((TIMERS_TICK_SIZE_CHIP)/((EMULATION_FREQUENCY_FACTOR))) | |
350 | #define TIMERS_TICK_SIZE_FPGA \ | |
351 | ((TIMERS_TICK_SIZE_CHIP)/((FPGA_FREQUENCY_FACTOR))) | |
352 | ||
353 | #define TSEMI_CLK1_RESUL_CHIP (1e-3) | |
354 | #define TSEMI_CLK1_RESUL_EMUL \ | |
355 | ((TSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR)) | |
356 | #define TSEMI_CLK1_RESUL_FPGA \ | |
357 | ((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR)) | |
358 | ||
359 | #define USEMI_CLK1_RESUL_CHIP \ | |
360 | (TIMERS_TICK_SIZE_CHIP) | |
361 | #define USEMI_CLK1_RESUL_EMUL \ | |
362 | (TIMERS_TICK_SIZE_EMUL) | |
363 | #define USEMI_CLK1_RESUL_FPGA \ | |
364 | (TIMERS_TICK_SIZE_FPGA) | |
365 | ||
366 | #define XSEMI_CLK1_RESUL_CHIP (1e-3) | |
367 | #define XSEMI_CLK1_RESUL_EMUL \ | |
368 | ((XSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR)) | |
369 | #define XSEMI_CLK1_RESUL_FPGA \ | |
370 | ((XSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR)) | |
371 | ||
372 | #define XSEMI_CLK2_RESUL_CHIP (1e-6) | |
373 | #define XSEMI_CLK2_RESUL_EMUL \ | |
374 | ((XSEMI_CLK2_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR)) | |
375 | #define XSEMI_CLK2_RESUL_FPGA \ | |
376 | ((XSEMI_CLK2_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR)) | |
377 | ||
378 | #define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6)) | |
379 | #define SDM_TIMER_TICK_RESUL_EMUL \ | |
380 | ((SDM_TIMER_TICK_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR)) | |
381 | #define SDM_TIMER_TICK_RESUL_FPGA \ | |
382 | ((SDM_TIMER_TICK_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR)) | |
383 | ||
384 | ||
385 | /**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ | |
a2fbb9ea ET |
386 | #define XSTORM_IP_ID_ROLL_HALF 0x8000 |
387 | #define XSTORM_IP_ID_ROLL_ALL 0 | |
388 | ||
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389 | #define FW_LOG_LIST_SIZE (50) |
390 | ||
391 | #define NUM_OF_PROTOCOLS 4 | |
8d9c5f34 EG |
392 | #define NUM_OF_SAFC_BITS 16 |
393 | #define MAX_COS_NUMBER 4 | |
34f80b04 EG |
394 | #define MAX_T_STAT_COUNTER_ID 18 |
395 | #define MAX_X_STAT_COUNTER_ID 18 | |
8d9c5f34 EG |
396 | #define MAX_U_STAT_COUNTER_ID 18 |
397 | ||
a2fbb9ea | 398 | |
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399 | #define UNKNOWN_ADDRESS 0 |
400 | #define UNICAST_ADDRESS 1 | |
401 | #define MULTICAST_ADDRESS 2 | |
402 | #define BROADCAST_ADDRESS 3 | |
a2fbb9ea | 403 | |
34f80b04 EG |
404 | #define SINGLE_FUNCTION 0 |
405 | #define MULTI_FUNCTION 1 | |
a2fbb9ea | 406 | |
34f80b04 EG |
407 | #define IP_V4 0 |
408 | #define IP_V6 1 | |
a2fbb9ea | 409 |