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a2fbb9ea ET |
1 | /* bnx2x_hsi.h: Broadcom Everest network driver. |
2 | * | |
f1410647 | 3 | * Copyright (c) 2007-2008 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | ||
f1410647 ET |
11 | #define PORT_0 0 |
12 | #define PORT_1 1 | |
13 | #define PORT_MAX 2 | |
a2fbb9ea ET |
14 | |
15 | /**************************************************************************** | |
16 | * Shared HW configuration * | |
17 | ****************************************************************************/ | |
18 | struct shared_hw_cfg { /* NVRAM Offset */ | |
19 | /* Up to 16 bytes of NULL-terminated string */ | |
20 | u8 part_num[16]; /* 0x104 */ | |
21 | ||
22 | u32 config; /* 0x114 */ | |
23 | #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 | |
24 | #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 | |
25 | #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 | |
26 | #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 | |
27 | #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002 | |
28 | ||
29 | #define SHARED_HW_CFG_PORT_SWAP 0x00000004 | |
30 | ||
31 | #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 | |
32 | ||
33 | #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 | |
34 | #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 | |
35 | /* Whatever MFW found in NVM | |
36 | (if multiple found, priority order is: NC-SI, UMP, IPMI) */ | |
37 | #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 | |
38 | #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 | |
39 | #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 | |
40 | #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 | |
41 | /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI | |
42 | (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ | |
43 | #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 | |
44 | /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI | |
45 | (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ | |
46 | #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 | |
47 | /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP | |
48 | (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ | |
49 | #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 | |
50 | ||
51 | #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000 | |
52 | #define SHARED_HW_CFG_LED_MODE_SHIFT 16 | |
53 | #define SHARED_HW_CFG_LED_MAC1 0x00000000 | |
54 | #define SHARED_HW_CFG_LED_PHY1 0x00010000 | |
55 | #define SHARED_HW_CFG_LED_PHY2 0x00020000 | |
56 | #define SHARED_HW_CFG_LED_PHY3 0x00030000 | |
57 | #define SHARED_HW_CFG_LED_MAC2 0x00040000 | |
58 | #define SHARED_HW_CFG_LED_PHY4 0x00050000 | |
59 | #define SHARED_HW_CFG_LED_PHY5 0x00060000 | |
60 | #define SHARED_HW_CFG_LED_PHY6 0x00070000 | |
61 | #define SHARED_HW_CFG_LED_MAC3 0x00080000 | |
62 | #define SHARED_HW_CFG_LED_PHY7 0x00090000 | |
63 | #define SHARED_HW_CFG_LED_PHY9 0x000a0000 | |
64 | #define SHARED_HW_CFG_LED_PHY11 0x000b0000 | |
65 | #define SHARED_HW_CFG_LED_MAC4 0x000c0000 | |
66 | #define SHARED_HW_CFG_LED_PHY8 0x000d0000 | |
67 | ||
68 | #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000 | |
69 | #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24 | |
70 | #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000 | |
71 | #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000 | |
72 | #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000 | |
73 | #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000 | |
74 | #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000 | |
75 | #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000 | |
76 | ||
77 | u32 config2; /* 0x118 */ | |
78 | /* one time auto detect grace period (in sec) */ | |
79 | #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff | |
80 | #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0 | |
81 | ||
82 | #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 | |
83 | ||
84 | /* The default value for the core clock is 250MHz and it is | |
85 | achieved by setting the clock change to 4 */ | |
86 | #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00 | |
87 | #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9 | |
88 | ||
89 | #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 | |
90 | #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 | |
91 | ||
f1410647 | 92 | #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 |
a2fbb9ea ET |
93 | |
94 | u32 power_dissipated; /* 0x11c */ | |
95 | #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000 | |
96 | #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24 | |
97 | ||
98 | #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000 | |
99 | #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16 | |
100 | #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000 | |
101 | #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000 | |
102 | #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000 | |
103 | #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000 | |
104 | ||
105 | u32 ump_nc_si_config; /* 0x120 */ | |
106 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 | |
107 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 | |
108 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 | |
109 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 | |
110 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 | |
111 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 | |
112 | ||
113 | #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00 | |
114 | #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8 | |
115 | ||
116 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000 | |
117 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16 | |
118 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000 | |
119 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000 | |
120 | ||
121 | u32 board; /* 0x124 */ | |
122 | #define SHARED_HW_CFG_BOARD_TYPE_MASK 0x0000ffff | |
123 | #define SHARED_HW_CFG_BOARD_TYPE_SHIFT 0 | |
124 | #define SHARED_HW_CFG_BOARD_TYPE_NONE 0x00000000 | |
125 | #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1000 0x00000001 | |
126 | #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1001 0x00000002 | |
127 | #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G 0x00000003 | |
128 | #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1004G 0x00000004 | |
129 | #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1007G 0x00000005 | |
130 | #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1015G 0x00000006 | |
131 | #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1020G 0x00000007 | |
132 | #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G 0x00000008 | |
f1410647 ET |
133 | #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G 0x00000009 |
134 | #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G 0x0000000a | |
a2fbb9ea ET |
135 | |
136 | #define SHARED_HW_CFG_BOARD_VER_MASK 0xffff0000 | |
137 | #define SHARED_HW_CFG_BOARD_VER_SHIFT 16 | |
138 | #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0xf0000000 | |
139 | #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 28 | |
140 | #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0x0f000000 | |
141 | #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 24 | |
142 | #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000 | |
143 | #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 | |
144 | ||
145 | u32 reserved; /* 0x128 */ | |
146 | ||
147 | }; | |
148 | ||
f1410647 | 149 | |
a2fbb9ea ET |
150 | /**************************************************************************** |
151 | * Port HW configuration * | |
152 | ****************************************************************************/ | |
f1410647 | 153 | struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ |
a2fbb9ea | 154 | |
a2fbb9ea ET |
155 | u32 pci_id; |
156 | #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000 | |
157 | #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff | |
158 | ||
159 | u32 pci_sub_id; | |
160 | #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000 | |
161 | #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff | |
162 | ||
163 | u32 power_dissipated; | |
164 | #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000 | |
165 | #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 | |
166 | #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000 | |
167 | #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 | |
168 | #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00 | |
169 | #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 | |
170 | #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff | |
171 | #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 | |
172 | ||
173 | u32 power_consumed; | |
174 | #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000 | |
175 | #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 | |
176 | #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000 | |
177 | #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 | |
178 | #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00 | |
179 | #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 | |
180 | #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff | |
181 | #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 | |
182 | ||
183 | u32 mac_upper; | |
184 | #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff | |
185 | #define PORT_HW_CFG_UPPERMAC_SHIFT 0 | |
186 | u32 mac_lower; | |
187 | ||
188 | u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */ | |
189 | u32 iscsi_mac_lower; | |
190 | ||
191 | u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */ | |
192 | u32 rdma_mac_lower; | |
193 | ||
194 | u32 serdes_config; | |
195 | /* for external PHY, or forced mode or during AN */ | |
196 | #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000 | |
197 | #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 16 | |
198 | ||
199 | #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0x0000ffff | |
200 | #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 0 | |
201 | ||
202 | u16 serdes_tx_driver_pre_emphasis[16]; | |
203 | u16 serdes_rx_driver_equalizer[16]; | |
204 | ||
205 | u32 xgxs_config_lane0; | |
206 | u32 xgxs_config_lane1; | |
207 | u32 xgxs_config_lane2; | |
208 | u32 xgxs_config_lane3; | |
209 | /* for external PHY, or forced mode or during AN */ | |
210 | #define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000 | |
211 | #define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_SHIFT 16 | |
212 | ||
213 | #define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_MASK 0x0000ffff | |
214 | #define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_SHIFT 0 | |
215 | ||
216 | u16 xgxs_tx_driver_pre_emphasis_lane0[16]; | |
217 | u16 xgxs_tx_driver_pre_emphasis_lane1[16]; | |
218 | u16 xgxs_tx_driver_pre_emphasis_lane2[16]; | |
219 | u16 xgxs_tx_driver_pre_emphasis_lane3[16]; | |
220 | ||
221 | u16 xgxs_rx_driver_equalizer_lane0[16]; | |
222 | u16 xgxs_rx_driver_equalizer_lane1[16]; | |
223 | u16 xgxs_rx_driver_equalizer_lane2[16]; | |
224 | u16 xgxs_rx_driver_equalizer_lane3[16]; | |
225 | ||
226 | u32 lane_config; | |
227 | #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff | |
228 | #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 | |
229 | #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff | |
230 | #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 | |
231 | #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00 | |
232 | #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 | |
233 | #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000 | |
234 | #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 | |
235 | /* AN and forced */ | |
236 | #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b | |
237 | /* forced only */ | |
238 | #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 | |
239 | /* forced only */ | |
240 | #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 | |
241 | /* forced only */ | |
242 | #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 | |
243 | ||
244 | u32 external_phy_config; | |
245 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000 | |
246 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 | |
247 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 | |
248 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 | |
249 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 | |
250 | ||
251 | #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000 | |
252 | #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 | |
253 | ||
254 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00 | |
255 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 | |
256 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 | |
257 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 | |
258 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 | |
259 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 | |
260 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 | |
261 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 | |
262 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8276 0x00000600 | |
263 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 | |
f1410647 ET |
264 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 |
265 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 | |
a2fbb9ea ET |
266 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 |
267 | ||
268 | #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff | |
269 | #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 | |
270 | ||
271 | u32 speed_capability_mask; | |
272 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000 | |
273 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 | |
274 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 | |
275 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 | |
276 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 | |
277 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 | |
278 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 | |
279 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 | |
280 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 | |
281 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G 0x00800000 | |
282 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G 0x01000000 | |
283 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G 0x02000000 | |
284 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G 0x04000000 | |
285 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G 0x08000000 | |
286 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 | |
287 | ||
288 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff | |
289 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 | |
290 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 | |
291 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 | |
292 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 | |
293 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 | |
294 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 | |
295 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 | |
296 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 | |
297 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G 0x00000080 | |
298 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G 0x00000100 | |
299 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G 0x00000200 | |
300 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G 0x00000400 | |
301 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G 0x00000800 | |
302 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 | |
303 | ||
304 | u32 reserved[2]; | |
305 | ||
306 | }; | |
307 | ||
f1410647 | 308 | |
a2fbb9ea ET |
309 | /**************************************************************************** |
310 | * Shared Feature configuration * | |
311 | ****************************************************************************/ | |
312 | struct shared_feat_cfg { /* NVRAM Offset */ | |
f1410647 ET |
313 | |
314 | u32 config; /* 0x450 */ | |
a2fbb9ea ET |
315 | #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 |
316 | ||
317 | }; | |
318 | ||
319 | ||
320 | /**************************************************************************** | |
321 | * Port Feature configuration * | |
322 | ****************************************************************************/ | |
f1410647 ET |
323 | struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ |
324 | ||
a2fbb9ea ET |
325 | u32 config; |
326 | #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f | |
327 | #define PORT_FEATURE_BAR1_SIZE_SHIFT 0 | |
328 | #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000 | |
329 | #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001 | |
330 | #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002 | |
331 | #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003 | |
332 | #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004 | |
333 | #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005 | |
334 | #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006 | |
335 | #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007 | |
336 | #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008 | |
337 | #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009 | |
338 | #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a | |
339 | #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b | |
340 | #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c | |
341 | #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d | |
342 | #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e | |
343 | #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f | |
344 | #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0 | |
345 | #define PORT_FEATURE_BAR2_SIZE_SHIFT 4 | |
346 | #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000 | |
347 | #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010 | |
348 | #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020 | |
349 | #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030 | |
350 | #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040 | |
351 | #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050 | |
352 | #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060 | |
353 | #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070 | |
354 | #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080 | |
355 | #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090 | |
356 | #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0 | |
357 | #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0 | |
358 | #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0 | |
359 | #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0 | |
360 | #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0 | |
361 | #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0 | |
362 | #define PORT_FEATURE_EN_SIZE_MASK 0x07000000 | |
363 | #define PORT_FEATURE_EN_SIZE_SHIFT 24 | |
364 | #define PORT_FEATURE_WOL_ENABLED 0x01000000 | |
365 | #define PORT_FEATURE_MBA_ENABLED 0x02000000 | |
366 | #define PORT_FEATURE_MFW_ENABLED 0x04000000 | |
367 | ||
368 | u32 wol_config; | |
369 | /* Default is used when driver sets to "auto" mode */ | |
370 | #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003 | |
371 | #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0 | |
372 | #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000 | |
373 | #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001 | |
374 | #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002 | |
375 | #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003 | |
376 | #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004 | |
377 | #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008 | |
378 | #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 | |
379 | ||
380 | u32 mba_config; | |
381 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000003 | |
382 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 | |
383 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 | |
384 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 | |
385 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 | |
386 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 | |
387 | #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100 | |
388 | #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200 | |
389 | #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 | |
390 | #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 | |
391 | #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 | |
392 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000 | |
393 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 | |
394 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 | |
395 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 | |
396 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 | |
397 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 | |
398 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 | |
399 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 | |
400 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 | |
401 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 | |
402 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 | |
403 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 | |
404 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 | |
405 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 | |
406 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 | |
407 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 | |
408 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 | |
409 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 | |
410 | #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000 | |
411 | #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 | |
412 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 | |
413 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 | |
414 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 | |
415 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 | |
416 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 | |
417 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 | |
418 | #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000 | |
419 | #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 | |
420 | #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 | |
421 | #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000 | |
422 | #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000 | |
423 | #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000 | |
424 | #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000 | |
425 | #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000 | |
426 | #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000 | |
427 | #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000 | |
428 | #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4 0x20000000 | |
429 | #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR 0x24000000 | |
430 | #define PORT_FEATURE_MBA_LINK_SPEED_12GBPS 0x28000000 | |
431 | #define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS 0x2c000000 | |
432 | #define PORT_FEATURE_MBA_LINK_SPEED_13GBPS 0x30000000 | |
433 | #define PORT_FEATURE_MBA_LINK_SPEED_15GBPS 0x34000000 | |
434 | #define PORT_FEATURE_MBA_LINK_SPEED_16GBPS 0x38000000 | |
435 | ||
436 | u32 bmc_config; | |
437 | #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000 | |
438 | #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001 | |
439 | ||
440 | u32 mba_vlan_cfg; | |
441 | #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff | |
442 | #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 | |
443 | #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 | |
444 | ||
445 | u32 resource_cfg; | |
446 | #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001 | |
447 | #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002 | |
448 | #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004 | |
449 | #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008 | |
450 | #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010 | |
451 | ||
452 | u32 smbus_config; | |
453 | /* Obsolete */ | |
454 | #define PORT_FEATURE_SMBUS_EN 0x00000001 | |
455 | #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe | |
456 | #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 | |
457 | ||
f1410647 | 458 | u32 reserved1; |
a2fbb9ea ET |
459 | |
460 | u32 link_config; /* Used as HW defaults for the driver */ | |
461 | #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 | |
462 | #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 | |
463 | /* (forced) low speed switch (< 10G) */ | |
464 | #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 | |
465 | /* (forced) high speed switch (>= 10G) */ | |
466 | #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 | |
467 | #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 | |
468 | #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 | |
469 | ||
470 | #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000 | |
471 | #define PORT_FEATURE_LINK_SPEED_SHIFT 16 | |
472 | #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 | |
473 | #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000 | |
474 | #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000 | |
475 | #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 | |
476 | #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 | |
477 | #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 | |
478 | #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 | |
479 | #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 | |
480 | #define PORT_FEATURE_LINK_SPEED_10G_KX4 0x00080000 | |
481 | #define PORT_FEATURE_LINK_SPEED_10G_KR 0x00090000 | |
482 | #define PORT_FEATURE_LINK_SPEED_12G 0x000a0000 | |
483 | #define PORT_FEATURE_LINK_SPEED_12_5G 0x000b0000 | |
484 | #define PORT_FEATURE_LINK_SPEED_13G 0x000c0000 | |
485 | #define PORT_FEATURE_LINK_SPEED_15G 0x000d0000 | |
486 | #define PORT_FEATURE_LINK_SPEED_16G 0x000e0000 | |
487 | ||
488 | #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 | |
489 | #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 | |
490 | #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 | |
491 | #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 | |
492 | #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 | |
493 | #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 | |
494 | #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 | |
495 | ||
496 | /* The default for MCP link configuration, | |
497 | uses the same defines as link_config */ | |
498 | u32 mfw_wol_link_cfg; | |
499 | ||
500 | u32 reserved[19]; | |
501 | ||
502 | }; | |
503 | ||
504 | ||
f1410647 ET |
505 | /***************************************************************************** |
506 | * Device Information * | |
507 | *****************************************************************************/ | |
508 | struct dev_info { /* size */ | |
509 | ||
510 | u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ | |
511 | ||
512 | struct shared_hw_cfg shared_hw_config; /* 40 */ | |
513 | ||
514 | struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ | |
515 | ||
516 | struct shared_feat_cfg shared_feature_config; /* 4 */ | |
517 | ||
518 | struct port_feat_cfg port_feature_config[PORT_MAX]; /* 116*2=232 */ | |
519 | ||
520 | }; | |
521 | ||
522 | ||
523 | #define FUNC_0 0 | |
524 | #define FUNC_1 1 | |
525 | #define E1_FUNC_MAX 2 | |
526 | #define FUNC_MAX E1_FUNC_MAX | |
527 | ||
528 | ||
529 | /* This value (in milliseconds) determines the frequency of the driver | |
530 | * issuing the PULSE message code. The firmware monitors this periodic | |
531 | * pulse to determine when to switch to an OS-absent mode. */ | |
532 | #define DRV_PULSE_PERIOD_MS 250 | |
533 | ||
534 | /* This value (in milliseconds) determines how long the driver should | |
535 | * wait for an acknowledgement from the firmware before timing out. Once | |
536 | * the firmware has timed out, the driver will assume there is no firmware | |
537 | * running and there won't be any firmware-driver synchronization during a | |
538 | * driver reset. */ | |
539 | #define FW_ACK_TIME_OUT_MS 5000 | |
540 | ||
541 | #define FW_ACK_POLL_TIME_MS 1 | |
542 | ||
543 | #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) | |
544 | ||
545 | /* LED Blink rate that will achieve ~15.9Hz */ | |
546 | #define LED_BLINK_RATE_VAL 480 | |
547 | ||
a2fbb9ea | 548 | /**************************************************************************** |
f1410647 | 549 | * Driver <-> FW Mailbox * |
a2fbb9ea | 550 | ****************************************************************************/ |
f1410647 | 551 | struct drv_port_mb { |
a2fbb9ea | 552 | |
f1410647 ET |
553 | u32 link_status; |
554 | /* Driver should update this field on any link change event */ | |
a2fbb9ea | 555 | |
f1410647 ET |
556 | #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 |
557 | #define LINK_STATUS_LINK_UP 0x00000001 | |
558 | #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E | |
559 | #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) | |
560 | #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) | |
561 | #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) | |
562 | #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) | |
563 | #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) | |
564 | #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) | |
565 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) | |
566 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) | |
567 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) | |
568 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) | |
569 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) | |
570 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) | |
571 | #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) | |
572 | #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) | |
573 | #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11<<1) | |
574 | #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11<<1) | |
575 | #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12<<1) | |
576 | #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12<<1) | |
577 | #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13<<1) | |
578 | #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13<<1) | |
579 | #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14<<1) | |
580 | #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14<<1) | |
581 | #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15<<1) | |
582 | #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15<<1) | |
a2fbb9ea | 583 | |
f1410647 ET |
584 | #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 |
585 | #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 | |
a2fbb9ea | 586 | |
f1410647 ET |
587 | #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 |
588 | #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 | |
589 | #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 | |
a2fbb9ea | 590 | |
f1410647 ET |
591 | #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 |
592 | #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 | |
593 | #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 | |
594 | #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 | |
595 | #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 | |
596 | #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 | |
597 | #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 | |
598 | ||
599 | #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 | |
600 | #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 | |
601 | ||
602 | #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 | |
603 | #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 | |
604 | ||
605 | #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 | |
606 | #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) | |
607 | #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) | |
608 | #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) | |
609 | #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) | |
610 | ||
611 | #define LINK_STATUS_SERDES_LINK 0x00100000 | |
612 | ||
613 | #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 | |
614 | #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 | |
615 | #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 | |
616 | #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000 | |
617 | #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000 | |
618 | #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000 | |
619 | #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000 | |
620 | #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000 | |
621 | ||
622 | u32 reserved[3]; | |
623 | ||
624 | }; | |
625 | ||
626 | ||
627 | struct drv_func_mb { | |
628 | ||
629 | u32 drv_mb_header; | |
630 | #define DRV_MSG_CODE_MASK 0xffff0000 | |
631 | #define DRV_MSG_CODE_LOAD_REQ 0x10000000 | |
632 | #define DRV_MSG_CODE_LOAD_DONE 0x11000000 | |
633 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 | |
634 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 | |
635 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 | |
636 | #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 | |
637 | #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 | |
638 | #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 | |
639 | #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 | |
640 | #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 | |
641 | #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 | |
642 | #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 | |
643 | #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 | |
644 | ||
645 | #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff | |
646 | ||
647 | u32 drv_mb_param; | |
648 | ||
649 | u32 fw_mb_header; | |
650 | #define FW_MSG_CODE_MASK 0xffff0000 | |
651 | #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 | |
652 | #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 | |
653 | #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 | |
654 | #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 | |
655 | #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 | |
656 | #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 | |
657 | #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 | |
658 | #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 | |
659 | #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 | |
660 | #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 | |
661 | #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 | |
662 | #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 | |
663 | #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 | |
664 | #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 | |
665 | #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 | |
666 | #define FW_MSG_CODE_NO_KEY 0x80f00000 | |
667 | #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 | |
668 | #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 | |
669 | #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 | |
670 | #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 | |
671 | #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 | |
672 | #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 | |
673 | ||
674 | #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff | |
675 | ||
676 | u32 fw_mb_param; | |
677 | ||
678 | u32 drv_pulse_mb; | |
679 | #define DRV_PULSE_SEQ_MASK 0x00007fff | |
680 | #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 | |
681 | /* The system time is in the format of | |
682 | * (year-2001)*12*32 + month*32 + day. */ | |
683 | #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 | |
684 | /* Indicate to the firmware not to go into the | |
685 | * OS-absent when it is not getting driver pulse. | |
686 | * This is used for debugging as well for PXE(MBA). */ | |
687 | ||
688 | u32 mcp_pulse_mb; | |
689 | #define MCP_PULSE_SEQ_MASK 0x00007fff | |
690 | #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 | |
691 | /* Indicates to the driver not to assert due to lack | |
692 | * of MCP response */ | |
693 | #define MCP_EVENT_MASK 0xffff0000 | |
694 | #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 | |
695 | ||
696 | u32 iscsi_boot_signature; | |
697 | u32 iscsi_boot_block_offset; | |
698 | ||
699 | u32 reserved[3]; | |
a2fbb9ea ET |
700 | |
701 | }; | |
702 | ||
703 | ||
704 | /**************************************************************************** | |
705 | * Management firmware state * | |
706 | ****************************************************************************/ | |
f1410647 ET |
707 | /* Allocate 440 bytes for management firmware */ |
708 | #define MGMTFW_STATE_WORD_SIZE 110 | |
a2fbb9ea ET |
709 | |
710 | struct mgmtfw_state { | |
711 | u32 opaque[MGMTFW_STATE_WORD_SIZE]; | |
712 | }; | |
713 | ||
714 | ||
715 | /**************************************************************************** | |
716 | * Shared Memory Region * | |
717 | ****************************************************************************/ | |
718 | struct shmem_region { /* SharedMem Offset (size) */ | |
f1410647 ET |
719 | |
720 | u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ | |
721 | #define SHR_MEM_FORMAT_REV_ID ('A'<<24) | |
722 | #define SHR_MEM_FORMAT_REV_MASK 0xff000000 | |
723 | /* validity bits */ | |
724 | #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 | |
725 | #define SHR_MEM_VALIDITY_MB 0x00200000 | |
726 | #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 | |
727 | #define SHR_MEM_VALIDITY_RESERVED 0x00000007 | |
a2fbb9ea ET |
728 | /* One licensing bit should be set */ |
729 | #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 | |
730 | #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 | |
731 | #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 | |
732 | #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 | |
f1410647 ET |
733 | /* Active MFW */ |
734 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 | |
735 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 | |
736 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 | |
737 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 | |
738 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 | |
739 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 | |
a2fbb9ea | 740 | |
f1410647 | 741 | struct dev_info dev_info; /* 0x8 (0x438) */ |
a2fbb9ea | 742 | |
f1410647 | 743 | u8 reserved[52*PORT_MAX]; |
a2fbb9ea ET |
744 | |
745 | /* FW information (for internal FW use) */ | |
f1410647 ET |
746 | u32 fw_info_fio_offset; /* 0x4a8 (0x4) */ |
747 | struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ | |
748 | ||
749 | struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ | |
750 | struct drv_func_mb func_mb[FUNC_MAX]; /* 0x684 (44*2=0x58) */ | |
a2fbb9ea | 751 | |
f1410647 | 752 | }; /* 0x6dc */ |
a2fbb9ea ET |
753 | |
754 | ||
755 | #define BCM_5710_FW_MAJOR_VERSION 4 | |
756 | #define BCM_5710_FW_MINOR_VERSION 0 | |
757 | #define BCM_5710_FW_REVISION_VERSION 14 | |
758 | #define BCM_5710_FW_COMPILE_FLAGS 1 | |
759 | ||
760 | ||
761 | /* | |
762 | * attention bits | |
763 | */ | |
764 | struct atten_def_status_block { | |
765 | u32 attn_bits; | |
766 | u32 attn_bits_ack; | |
767 | #if defined(__BIG_ENDIAN) | |
768 | u16 attn_bits_index; | |
769 | u8 reserved0; | |
770 | u8 status_block_id; | |
771 | #elif defined(__LITTLE_ENDIAN) | |
772 | u8 status_block_id; | |
773 | u8 reserved0; | |
774 | u16 attn_bits_index; | |
775 | #endif | |
776 | u32 reserved1; | |
777 | }; | |
778 | ||
779 | ||
780 | /* | |
781 | * common data for all protocols | |
782 | */ | |
783 | struct doorbell_hdr { | |
784 | u8 header; | |
785 | #define DOORBELL_HDR_RX (0x1<<0) | |
786 | #define DOORBELL_HDR_RX_SHIFT 0 | |
787 | #define DOORBELL_HDR_DB_TYPE (0x1<<1) | |
788 | #define DOORBELL_HDR_DB_TYPE_SHIFT 1 | |
789 | #define DOORBELL_HDR_DPM_SIZE (0x3<<2) | |
790 | #define DOORBELL_HDR_DPM_SIZE_SHIFT 2 | |
791 | #define DOORBELL_HDR_CONN_TYPE (0xF<<4) | |
792 | #define DOORBELL_HDR_CONN_TYPE_SHIFT 4 | |
793 | }; | |
794 | ||
795 | /* | |
796 | * doorbell message send to the chip | |
797 | */ | |
798 | struct doorbell { | |
799 | #if defined(__BIG_ENDIAN) | |
800 | u16 zero_fill2; | |
801 | u8 zero_fill1; | |
802 | struct doorbell_hdr header; | |
803 | #elif defined(__LITTLE_ENDIAN) | |
804 | struct doorbell_hdr header; | |
805 | u8 zero_fill1; | |
806 | u16 zero_fill2; | |
807 | #endif | |
808 | }; | |
809 | ||
810 | ||
811 | /* | |
812 | * IGU driver acknowlegement register | |
813 | */ | |
814 | struct igu_ack_register { | |
815 | #if defined(__BIG_ENDIAN) | |
816 | u16 sb_id_and_flags; | |
817 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) | |
818 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 | |
819 | #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) | |
820 | #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 | |
821 | #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) | |
822 | #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 | |
823 | #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) | |
824 | #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 | |
825 | #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) | |
826 | #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 | |
827 | u16 status_block_index; | |
828 | #elif defined(__LITTLE_ENDIAN) | |
829 | u16 status_block_index; | |
830 | u16 sb_id_and_flags; | |
831 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) | |
832 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 | |
833 | #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) | |
834 | #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 | |
835 | #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) | |
836 | #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 | |
837 | #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) | |
838 | #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 | |
839 | #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) | |
840 | #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 | |
841 | #endif | |
842 | }; | |
843 | ||
844 | ||
845 | /* | |
846 | * Parser parsing flags field | |
847 | */ | |
848 | struct parsing_flags { | |
849 | u16 flags; | |
850 | #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) | |
851 | #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 | |
852 | #define PARSING_FLAGS_NUMBER_OF_NESTED_VLANS (0x3<<1) | |
853 | #define PARSING_FLAGS_NUMBER_OF_NESTED_VLANS_SHIFT 1 | |
854 | #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) | |
855 | #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 | |
856 | #define PARSING_FLAGS_IP_OPTIONS (0x1<<5) | |
857 | #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 | |
858 | #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) | |
859 | #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 | |
860 | #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) | |
861 | #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 | |
862 | #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) | |
863 | #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 | |
864 | #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) | |
865 | #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 | |
866 | #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) | |
867 | #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 | |
868 | #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) | |
869 | #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 | |
870 | #define PARSING_FLAGS_LLC_SNAP (0x1<<13) | |
871 | #define PARSING_FLAGS_LLC_SNAP_SHIFT 13 | |
872 | #define PARSING_FLAGS_RESERVED0 (0x3<<14) | |
873 | #define PARSING_FLAGS_RESERVED0_SHIFT 14 | |
874 | }; | |
875 | ||
876 | ||
877 | /* | |
878 | * dmae command structure | |
879 | */ | |
880 | struct dmae_command { | |
881 | u32 opcode; | |
882 | #define DMAE_COMMAND_SRC (0x1<<0) | |
883 | #define DMAE_COMMAND_SRC_SHIFT 0 | |
884 | #define DMAE_COMMAND_DST (0x3<<1) | |
885 | #define DMAE_COMMAND_DST_SHIFT 1 | |
886 | #define DMAE_COMMAND_C_DST (0x1<<3) | |
887 | #define DMAE_COMMAND_C_DST_SHIFT 3 | |
888 | #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) | |
889 | #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 | |
890 | #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) | |
891 | #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 | |
892 | #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) | |
893 | #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 | |
894 | #define DMAE_COMMAND_ENDIANITY (0x3<<9) | |
895 | #define DMAE_COMMAND_ENDIANITY_SHIFT 9 | |
896 | #define DMAE_COMMAND_PORT (0x1<<11) | |
897 | #define DMAE_COMMAND_PORT_SHIFT 11 | |
898 | #define DMAE_COMMAND_CRC_RESET (0x1<<12) | |
899 | #define DMAE_COMMAND_CRC_RESET_SHIFT 12 | |
900 | #define DMAE_COMMAND_SRC_RESET (0x1<<13) | |
901 | #define DMAE_COMMAND_SRC_RESET_SHIFT 13 | |
902 | #define DMAE_COMMAND_DST_RESET (0x1<<14) | |
903 | #define DMAE_COMMAND_DST_RESET_SHIFT 14 | |
904 | #define DMAE_COMMAND_RESERVED0 (0x1FFFF<<15) | |
905 | #define DMAE_COMMAND_RESERVED0_SHIFT 15 | |
906 | u32 src_addr_lo; | |
907 | u32 src_addr_hi; | |
908 | u32 dst_addr_lo; | |
909 | u32 dst_addr_hi; | |
910 | #if defined(__BIG_ENDIAN) | |
911 | u16 reserved1; | |
912 | u16 len; | |
913 | #elif defined(__LITTLE_ENDIAN) | |
914 | u16 len; | |
915 | u16 reserved1; | |
916 | #endif | |
917 | u32 comp_addr_lo; | |
918 | u32 comp_addr_hi; | |
919 | u32 comp_val; | |
920 | u32 crc32; | |
921 | u32 crc32_c; | |
922 | #if defined(__BIG_ENDIAN) | |
923 | u16 crc16_c; | |
924 | u16 crc16; | |
925 | #elif defined(__LITTLE_ENDIAN) | |
926 | u16 crc16; | |
927 | u16 crc16_c; | |
928 | #endif | |
929 | #if defined(__BIG_ENDIAN) | |
930 | u16 reserved2; | |
931 | u16 crc_t10; | |
932 | #elif defined(__LITTLE_ENDIAN) | |
933 | u16 crc_t10; | |
934 | u16 reserved2; | |
935 | #endif | |
936 | #if defined(__BIG_ENDIAN) | |
937 | u16 xsum8; | |
938 | u16 xsum16; | |
939 | #elif defined(__LITTLE_ENDIAN) | |
940 | u16 xsum16; | |
941 | u16 xsum8; | |
942 | #endif | |
943 | }; | |
944 | ||
945 | ||
946 | struct double_regpair { | |
947 | u32 regpair0_lo; | |
948 | u32 regpair0_hi; | |
949 | u32 regpair1_lo; | |
950 | u32 regpair1_hi; | |
951 | }; | |
952 | ||
953 | ||
954 | /* | |
955 | * The eth Rx Buffer Descriptor | |
956 | */ | |
957 | struct eth_rx_bd { | |
958 | u32 addr_lo; | |
959 | u32 addr_hi; | |
960 | }; | |
961 | ||
962 | /* | |
963 | * The eth storm context of Ustorm | |
964 | */ | |
965 | struct ustorm_eth_st_context { | |
966 | #if defined(__BIG_ENDIAN) | |
967 | u8 sb_index_number; | |
968 | u8 status_block_id; | |
969 | u8 __local_rx_bd_cons; | |
970 | u8 __local_rx_bd_prod; | |
971 | #elif defined(__LITTLE_ENDIAN) | |
972 | u8 __local_rx_bd_prod; | |
973 | u8 __local_rx_bd_cons; | |
974 | u8 status_block_id; | |
975 | u8 sb_index_number; | |
976 | #endif | |
977 | #if defined(__BIG_ENDIAN) | |
978 | u16 rcq_cons; | |
979 | u16 rx_bd_cons; | |
980 | #elif defined(__LITTLE_ENDIAN) | |
981 | u16 rx_bd_cons; | |
982 | u16 rcq_cons; | |
983 | #endif | |
984 | u32 rx_bd_page_base_lo; | |
985 | u32 rx_bd_page_base_hi; | |
986 | u32 rcq_base_address_lo; | |
987 | u32 rcq_base_address_hi; | |
988 | #if defined(__BIG_ENDIAN) | |
989 | u16 __num_of_returned_cqes; | |
990 | u8 num_rss; | |
991 | u8 flags; | |
992 | #define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT (0x1<<0) | |
993 | #define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT_SHIFT 0 | |
994 | #define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC (0x1<<1) | |
995 | #define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC_SHIFT 1 | |
996 | #define USTORM_ETH_ST_CONTEXT_ENABLE_TPA (0x1<<2) | |
997 | #define USTORM_ETH_ST_CONTEXT_ENABLE_TPA_SHIFT 2 | |
998 | #define __USTORM_ETH_ST_CONTEXT_RESERVED0 (0x1F<<3) | |
999 | #define __USTORM_ETH_ST_CONTEXT_RESERVED0_SHIFT 3 | |
1000 | #elif defined(__LITTLE_ENDIAN) | |
1001 | u8 flags; | |
1002 | #define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT (0x1<<0) | |
1003 | #define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT_SHIFT 0 | |
1004 | #define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC (0x1<<1) | |
1005 | #define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC_SHIFT 1 | |
1006 | #define USTORM_ETH_ST_CONTEXT_ENABLE_TPA (0x1<<2) | |
1007 | #define USTORM_ETH_ST_CONTEXT_ENABLE_TPA_SHIFT 2 | |
1008 | #define __USTORM_ETH_ST_CONTEXT_RESERVED0 (0x1F<<3) | |
1009 | #define __USTORM_ETH_ST_CONTEXT_RESERVED0_SHIFT 3 | |
1010 | u8 num_rss; | |
1011 | u16 __num_of_returned_cqes; | |
1012 | #endif | |
1013 | #if defined(__BIG_ENDIAN) | |
1014 | u16 mc_alignment_size; | |
1015 | u16 agg_threshold; | |
1016 | #elif defined(__LITTLE_ENDIAN) | |
1017 | u16 agg_threshold; | |
1018 | u16 mc_alignment_size; | |
1019 | #endif | |
1020 | struct eth_rx_bd __local_bd_ring[16]; | |
1021 | }; | |
1022 | ||
1023 | /* | |
1024 | * The eth storm context of Tstorm | |
1025 | */ | |
1026 | struct tstorm_eth_st_context { | |
1027 | u32 __reserved0[28]; | |
1028 | }; | |
1029 | ||
1030 | /* | |
1031 | * The eth aggregative context section of Xstorm | |
1032 | */ | |
1033 | struct xstorm_eth_extra_ag_context_section { | |
1034 | #if defined(__BIG_ENDIAN) | |
1035 | u8 __tcp_agg_vars1; | |
1036 | u8 __reserved50; | |
1037 | u16 __mss; | |
1038 | #elif defined(__LITTLE_ENDIAN) | |
1039 | u16 __mss; | |
1040 | u8 __reserved50; | |
1041 | u8 __tcp_agg_vars1; | |
1042 | #endif | |
1043 | u32 __snd_nxt; | |
1044 | u32 __tx_wnd; | |
1045 | u32 __snd_una; | |
1046 | u32 __reserved53; | |
1047 | #if defined(__BIG_ENDIAN) | |
1048 | u8 __agg_val8_th; | |
1049 | u8 __agg_val8; | |
1050 | u16 __tcp_agg_vars2; | |
1051 | #elif defined(__LITTLE_ENDIAN) | |
1052 | u16 __tcp_agg_vars2; | |
1053 | u8 __agg_val8; | |
1054 | u8 __agg_val8_th; | |
1055 | #endif | |
1056 | u32 __reserved58; | |
1057 | u32 __reserved59; | |
1058 | u32 __reserved60; | |
1059 | u32 __reserved61; | |
1060 | #if defined(__BIG_ENDIAN) | |
1061 | u16 __agg_val7_th; | |
1062 | u16 __agg_val7; | |
1063 | #elif defined(__LITTLE_ENDIAN) | |
1064 | u16 __agg_val7; | |
1065 | u16 __agg_val7_th; | |
1066 | #endif | |
1067 | #if defined(__BIG_ENDIAN) | |
1068 | u8 __tcp_agg_vars5; | |
1069 | u8 __tcp_agg_vars4; | |
1070 | u8 __tcp_agg_vars3; | |
1071 | u8 __reserved62; | |
1072 | #elif defined(__LITTLE_ENDIAN) | |
1073 | u8 __reserved62; | |
1074 | u8 __tcp_agg_vars3; | |
1075 | u8 __tcp_agg_vars4; | |
1076 | u8 __tcp_agg_vars5; | |
1077 | #endif | |
1078 | u32 __tcp_agg_vars6; | |
1079 | #if defined(__BIG_ENDIAN) | |
1080 | u16 __agg_misc6; | |
1081 | u16 __tcp_agg_vars7; | |
1082 | #elif defined(__LITTLE_ENDIAN) | |
1083 | u16 __tcp_agg_vars7; | |
1084 | u16 __agg_misc6; | |
1085 | #endif | |
1086 | u32 __agg_val10; | |
1087 | u32 __agg_val10_th; | |
1088 | #if defined(__BIG_ENDIAN) | |
1089 | u16 __reserved3; | |
1090 | u8 __reserved2; | |
1091 | u8 __agg_misc7; | |
1092 | #elif defined(__LITTLE_ENDIAN) | |
1093 | u8 __agg_misc7; | |
1094 | u8 __reserved2; | |
1095 | u16 __reserved3; | |
1096 | #endif | |
1097 | }; | |
1098 | ||
1099 | /* | |
1100 | * The eth aggregative context of Xstorm | |
1101 | */ | |
1102 | struct xstorm_eth_ag_context { | |
1103 | #if defined(__BIG_ENDIAN) | |
1104 | u16 __bd_prod; | |
1105 | u8 __agg_vars1; | |
1106 | u8 __state; | |
1107 | #elif defined(__LITTLE_ENDIAN) | |
1108 | u8 __state; | |
1109 | u8 __agg_vars1; | |
1110 | u16 __bd_prod; | |
1111 | #endif | |
1112 | #if defined(__BIG_ENDIAN) | |
1113 | u8 cdu_reserved; | |
1114 | u8 __agg_vars4; | |
1115 | u8 __agg_vars3; | |
1116 | u8 __agg_vars2; | |
1117 | #elif defined(__LITTLE_ENDIAN) | |
1118 | u8 __agg_vars2; | |
1119 | u8 __agg_vars3; | |
1120 | u8 __agg_vars4; | |
1121 | u8 cdu_reserved; | |
1122 | #endif | |
1123 | u32 __more_packets_to_send; | |
1124 | #if defined(__BIG_ENDIAN) | |
1125 | u16 __agg_vars5; | |
1126 | u16 __agg_val4_th; | |
1127 | #elif defined(__LITTLE_ENDIAN) | |
1128 | u16 __agg_val4_th; | |
1129 | u16 __agg_vars5; | |
1130 | #endif | |
1131 | struct xstorm_eth_extra_ag_context_section __extra_section; | |
1132 | #if defined(__BIG_ENDIAN) | |
1133 | u16 __agg_vars7; | |
1134 | u8 __agg_val3_th; | |
1135 | u8 __agg_vars6; | |
1136 | #elif defined(__LITTLE_ENDIAN) | |
1137 | u8 __agg_vars6; | |
1138 | u8 __agg_val3_th; | |
1139 | u16 __agg_vars7; | |
1140 | #endif | |
1141 | #if defined(__BIG_ENDIAN) | |
1142 | u16 __agg_val11_th; | |
1143 | u16 __agg_val11; | |
1144 | #elif defined(__LITTLE_ENDIAN) | |
1145 | u16 __agg_val11; | |
1146 | u16 __agg_val11_th; | |
1147 | #endif | |
1148 | #if defined(__BIG_ENDIAN) | |
1149 | u8 __reserved1; | |
1150 | u8 __agg_val6_th; | |
1151 | u16 __agg_val9; | |
1152 | #elif defined(__LITTLE_ENDIAN) | |
1153 | u16 __agg_val9; | |
1154 | u8 __agg_val6_th; | |
1155 | u8 __reserved1; | |
1156 | #endif | |
1157 | #if defined(__BIG_ENDIAN) | |
1158 | u16 __agg_val2_th; | |
1159 | u16 __agg_val2; | |
1160 | #elif defined(__LITTLE_ENDIAN) | |
1161 | u16 __agg_val2; | |
1162 | u16 __agg_val2_th; | |
1163 | #endif | |
1164 | u32 __agg_vars8; | |
1165 | #if defined(__BIG_ENDIAN) | |
1166 | u16 __agg_misc0; | |
1167 | u16 __agg_val4; | |
1168 | #elif defined(__LITTLE_ENDIAN) | |
1169 | u16 __agg_val4; | |
1170 | u16 __agg_misc0; | |
1171 | #endif | |
1172 | #if defined(__BIG_ENDIAN) | |
1173 | u8 __agg_val3; | |
1174 | u8 __agg_val6; | |
1175 | u8 __agg_val5_th; | |
1176 | u8 __agg_val5; | |
1177 | #elif defined(__LITTLE_ENDIAN) | |
1178 | u8 __agg_val5; | |
1179 | u8 __agg_val5_th; | |
1180 | u8 __agg_val6; | |
1181 | u8 __agg_val3; | |
1182 | #endif | |
1183 | #if defined(__BIG_ENDIAN) | |
1184 | u16 __agg_misc1; | |
1185 | u16 __bd_ind_max_val; | |
1186 | #elif defined(__LITTLE_ENDIAN) | |
1187 | u16 __bd_ind_max_val; | |
1188 | u16 __agg_misc1; | |
1189 | #endif | |
1190 | u32 __reserved57; | |
1191 | u32 __agg_misc4; | |
1192 | u32 __agg_misc5; | |
1193 | }; | |
1194 | ||
1195 | /* | |
1196 | * The eth aggregative context section of Tstorm | |
1197 | */ | |
1198 | struct tstorm_eth_extra_ag_context_section { | |
1199 | u32 __agg_val1; | |
1200 | #if defined(__BIG_ENDIAN) | |
1201 | u8 __tcp_agg_vars2; | |
1202 | u8 __agg_val3; | |
1203 | u16 __agg_val2; | |
1204 | #elif defined(__LITTLE_ENDIAN) | |
1205 | u16 __agg_val2; | |
1206 | u8 __agg_val3; | |
1207 | u8 __tcp_agg_vars2; | |
1208 | #endif | |
1209 | #if defined(__BIG_ENDIAN) | |
1210 | u16 __agg_val5; | |
1211 | u8 __agg_val6; | |
1212 | u8 __tcp_agg_vars3; | |
1213 | #elif defined(__LITTLE_ENDIAN) | |
1214 | u8 __tcp_agg_vars3; | |
1215 | u8 __agg_val6; | |
1216 | u16 __agg_val5; | |
1217 | #endif | |
1218 | u32 __reserved63; | |
1219 | u32 __reserved64; | |
1220 | u32 __reserved65; | |
1221 | u32 __reserved66; | |
1222 | u32 __reserved67; | |
1223 | u32 __tcp_agg_vars1; | |
1224 | u32 __reserved61; | |
1225 | u32 __reserved62; | |
1226 | u32 __reserved2; | |
1227 | }; | |
1228 | ||
1229 | /* | |
1230 | * The eth aggregative context of Tstorm | |
1231 | */ | |
1232 | struct tstorm_eth_ag_context { | |
1233 | #if defined(__BIG_ENDIAN) | |
1234 | u16 __reserved54; | |
1235 | u8 __agg_vars1; | |
1236 | u8 __state; | |
1237 | #elif defined(__LITTLE_ENDIAN) | |
1238 | u8 __state; | |
1239 | u8 __agg_vars1; | |
1240 | u16 __reserved54; | |
1241 | #endif | |
1242 | #if defined(__BIG_ENDIAN) | |
1243 | u16 __agg_val4; | |
1244 | u16 __agg_vars2; | |
1245 | #elif defined(__LITTLE_ENDIAN) | |
1246 | u16 __agg_vars2; | |
1247 | u16 __agg_val4; | |
1248 | #endif | |
1249 | struct tstorm_eth_extra_ag_context_section __extra_section; | |
1250 | }; | |
1251 | ||
1252 | /* | |
1253 | * The eth aggregative context of Cstorm | |
1254 | */ | |
1255 | struct cstorm_eth_ag_context { | |
1256 | u32 __agg_vars1; | |
1257 | #if defined(__BIG_ENDIAN) | |
1258 | u8 __aux1_th; | |
1259 | u8 __aux1_val; | |
1260 | u16 __agg_vars2; | |
1261 | #elif defined(__LITTLE_ENDIAN) | |
1262 | u16 __agg_vars2; | |
1263 | u8 __aux1_val; | |
1264 | u8 __aux1_th; | |
1265 | #endif | |
1266 | u32 __num_of_treated_packet; | |
1267 | u32 __last_packet_treated; | |
1268 | #if defined(__BIG_ENDIAN) | |
1269 | u16 __reserved58; | |
1270 | u16 __reserved57; | |
1271 | #elif defined(__LITTLE_ENDIAN) | |
1272 | u16 __reserved57; | |
1273 | u16 __reserved58; | |
1274 | #endif | |
1275 | #if defined(__BIG_ENDIAN) | |
1276 | u8 __reserved62; | |
1277 | u8 __reserved61; | |
1278 | u8 __reserved60; | |
1279 | u8 __reserved59; | |
1280 | #elif defined(__LITTLE_ENDIAN) | |
1281 | u8 __reserved59; | |
1282 | u8 __reserved60; | |
1283 | u8 __reserved61; | |
1284 | u8 __reserved62; | |
1285 | #endif | |
1286 | #if defined(__BIG_ENDIAN) | |
1287 | u16 __reserved64; | |
1288 | u16 __reserved63; | |
1289 | #elif defined(__LITTLE_ENDIAN) | |
1290 | u16 __reserved63; | |
1291 | u16 __reserved64; | |
1292 | #endif | |
1293 | u32 __reserved65; | |
1294 | #if defined(__BIG_ENDIAN) | |
1295 | u16 __agg_vars3; | |
1296 | u16 __rq_inv_cnt; | |
1297 | #elif defined(__LITTLE_ENDIAN) | |
1298 | u16 __rq_inv_cnt; | |
1299 | u16 __agg_vars3; | |
1300 | #endif | |
1301 | #if defined(__BIG_ENDIAN) | |
1302 | u16 __packet_index_th; | |
1303 | u16 __packet_index; | |
1304 | #elif defined(__LITTLE_ENDIAN) | |
1305 | u16 __packet_index; | |
1306 | u16 __packet_index_th; | |
1307 | #endif | |
1308 | }; | |
1309 | ||
1310 | /* | |
1311 | * The eth aggregative context of Ustorm | |
1312 | */ | |
1313 | struct ustorm_eth_ag_context { | |
1314 | #if defined(__BIG_ENDIAN) | |
1315 | u8 __aux_counter_flags; | |
1316 | u8 __agg_vars2; | |
1317 | u8 __agg_vars1; | |
1318 | u8 __state; | |
1319 | #elif defined(__LITTLE_ENDIAN) | |
1320 | u8 __state; | |
1321 | u8 __agg_vars1; | |
1322 | u8 __agg_vars2; | |
1323 | u8 __aux_counter_flags; | |
1324 | #endif | |
1325 | #if defined(__BIG_ENDIAN) | |
1326 | u8 cdu_usage; | |
1327 | u8 __agg_misc2; | |
1328 | u16 __agg_misc1; | |
1329 | #elif defined(__LITTLE_ENDIAN) | |
1330 | u16 __agg_misc1; | |
1331 | u8 __agg_misc2; | |
1332 | u8 cdu_usage; | |
1333 | #endif | |
1334 | u32 __agg_misc4; | |
1335 | #if defined(__BIG_ENDIAN) | |
1336 | u8 __agg_val3_th; | |
1337 | u8 __agg_val3; | |
1338 | u16 __agg_misc3; | |
1339 | #elif defined(__LITTLE_ENDIAN) | |
1340 | u16 __agg_misc3; | |
1341 | u8 __agg_val3; | |
1342 | u8 __agg_val3_th; | |
1343 | #endif | |
1344 | u32 __agg_val1; | |
1345 | u32 __agg_misc4_th; | |
1346 | #if defined(__BIG_ENDIAN) | |
1347 | u16 __agg_val2_th; | |
1348 | u16 __agg_val2; | |
1349 | #elif defined(__LITTLE_ENDIAN) | |
1350 | u16 __agg_val2; | |
1351 | u16 __agg_val2_th; | |
1352 | #endif | |
1353 | #if defined(__BIG_ENDIAN) | |
1354 | u16 __reserved2; | |
1355 | u8 __decision_rules; | |
1356 | u8 __decision_rule_enable_bits; | |
1357 | #elif defined(__LITTLE_ENDIAN) | |
1358 | u8 __decision_rule_enable_bits; | |
1359 | u8 __decision_rules; | |
1360 | u16 __reserved2; | |
1361 | #endif | |
1362 | }; | |
1363 | ||
1364 | /* | |
1365 | * Timers connection context | |
1366 | */ | |
1367 | struct timers_block_context { | |
1368 | u32 __reserved_0; | |
1369 | u32 __reserved_1; | |
1370 | u32 __reserved_2; | |
1371 | u32 __reserved_flags; | |
1372 | }; | |
1373 | ||
1374 | /* | |
1375 | * structure for easy accessability to assembler | |
1376 | */ | |
1377 | struct eth_tx_bd_flags { | |
1378 | u8 as_bitfield; | |
1379 | #define ETH_TX_BD_FLAGS_VLAN_TAG (0x1<<0) | |
1380 | #define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0 | |
1381 | #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1) | |
1382 | #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1 | |
1383 | #define ETH_TX_BD_FLAGS_TCP_CSUM (0x1<<2) | |
1384 | #define ETH_TX_BD_FLAGS_TCP_CSUM_SHIFT 2 | |
1385 | #define ETH_TX_BD_FLAGS_END_BD (0x1<<3) | |
1386 | #define ETH_TX_BD_FLAGS_END_BD_SHIFT 3 | |
1387 | #define ETH_TX_BD_FLAGS_START_BD (0x1<<4) | |
1388 | #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 | |
1389 | #define ETH_TX_BD_FLAGS_HDR_POOL (0x1<<5) | |
1390 | #define ETH_TX_BD_FLAGS_HDR_POOL_SHIFT 5 | |
1391 | #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) | |
1392 | #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 | |
1393 | #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) | |
1394 | #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 | |
1395 | }; | |
1396 | ||
1397 | /* | |
1398 | * The eth Tx Buffer Descriptor | |
1399 | */ | |
1400 | struct eth_tx_bd { | |
1401 | u32 addr_lo; | |
1402 | u32 addr_hi; | |
1403 | u16 nbd; | |
1404 | u16 nbytes; | |
1405 | u16 vlan; | |
1406 | struct eth_tx_bd_flags bd_flags; | |
1407 | u8 general_data; | |
1408 | #define ETH_TX_BD_HDR_NBDS (0x3F<<0) | |
1409 | #define ETH_TX_BD_HDR_NBDS_SHIFT 0 | |
1410 | #define ETH_TX_BD_ETH_ADDR_TYPE (0x3<<6) | |
1411 | #define ETH_TX_BD_ETH_ADDR_TYPE_SHIFT 6 | |
1412 | }; | |
1413 | ||
1414 | /* | |
1415 | * Tx parsing BD structure for ETH,Relevant in START | |
1416 | */ | |
1417 | struct eth_tx_parse_bd { | |
1418 | u8 global_data; | |
1419 | #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0) | |
1420 | #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0 | |
1421 | #define ETH_TX_PARSE_BD_CS_ANY_FLG (0x1<<4) | |
1422 | #define ETH_TX_PARSE_BD_CS_ANY_FLG_SHIFT 4 | |
1423 | #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5) | |
1424 | #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5 | |
1425 | #define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6) | |
1426 | #define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6 | |
1427 | #define ETH_TX_PARSE_BD_NS_FLG (0x1<<7) | |
1428 | #define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7 | |
1429 | u8 tcp_flags; | |
1430 | #define ETH_TX_PARSE_BD_FIN_FLG (0x1<<0) | |
1431 | #define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0 | |
1432 | #define ETH_TX_PARSE_BD_SYN_FLG (0x1<<1) | |
1433 | #define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1 | |
1434 | #define ETH_TX_PARSE_BD_RST_FLG (0x1<<2) | |
1435 | #define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2 | |
1436 | #define ETH_TX_PARSE_BD_PSH_FLG (0x1<<3) | |
1437 | #define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3 | |
1438 | #define ETH_TX_PARSE_BD_ACK_FLG (0x1<<4) | |
1439 | #define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4 | |
1440 | #define ETH_TX_PARSE_BD_URG_FLG (0x1<<5) | |
1441 | #define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5 | |
1442 | #define ETH_TX_PARSE_BD_ECE_FLG (0x1<<6) | |
1443 | #define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6 | |
1444 | #define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7) | |
1445 | #define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7 | |
1446 | u8 ip_hlen; | |
1447 | s8 cs_offset; | |
1448 | u16 total_hlen; | |
1449 | u16 lso_mss; | |
1450 | u16 tcp_pseudo_csum; | |
1451 | u16 ip_id; | |
1452 | u32 tcp_send_seq; | |
1453 | }; | |
1454 | ||
1455 | /* | |
1456 | * The last BD in the BD memory will hold a pointer to the next BD memory | |
1457 | */ | |
1458 | struct eth_tx_next_bd { | |
1459 | u32 addr_lo; | |
1460 | u32 addr_hi; | |
1461 | u8 reserved[8]; | |
1462 | }; | |
1463 | ||
1464 | /* | |
1465 | * union for 3 Bd types | |
1466 | */ | |
1467 | union eth_tx_bd_types { | |
1468 | struct eth_tx_bd reg_bd; | |
1469 | struct eth_tx_parse_bd parse_bd; | |
1470 | struct eth_tx_next_bd next_bd; | |
1471 | }; | |
1472 | ||
1473 | /* | |
1474 | * The eth storm context of Xstorm | |
1475 | */ | |
1476 | struct xstorm_eth_st_context { | |
1477 | u32 tx_bd_page_base_lo; | |
1478 | u32 tx_bd_page_base_hi; | |
1479 | #if defined(__BIG_ENDIAN) | |
1480 | u16 tx_bd_cons; | |
1481 | u8 __reserved0; | |
1482 | u8 __local_tx_bd_prod; | |
1483 | #elif defined(__LITTLE_ENDIAN) | |
1484 | u8 __local_tx_bd_prod; | |
1485 | u8 __reserved0; | |
1486 | u16 tx_bd_cons; | |
1487 | #endif | |
1488 | u32 db_data_addr_lo; | |
1489 | u32 db_data_addr_hi; | |
1490 | u32 __pkt_cons; | |
1491 | u32 __gso_next; | |
1492 | u32 is_eth_conn_1b; | |
1493 | union eth_tx_bd_types __bds[13]; | |
1494 | }; | |
1495 | ||
1496 | /* | |
1497 | * The eth storm context of Cstorm | |
1498 | */ | |
1499 | struct cstorm_eth_st_context { | |
1500 | #if defined(__BIG_ENDIAN) | |
1501 | u16 __reserved0; | |
1502 | u8 sb_index_number; | |
1503 | u8 status_block_id; | |
1504 | #elif defined(__LITTLE_ENDIAN) | |
1505 | u8 status_block_id; | |
1506 | u8 sb_index_number; | |
1507 | u16 __reserved0; | |
1508 | #endif | |
1509 | u32 __reserved1[3]; | |
1510 | }; | |
1511 | ||
1512 | /* | |
1513 | * Ethernet connection context | |
1514 | */ | |
1515 | struct eth_context { | |
1516 | struct ustorm_eth_st_context ustorm_st_context; | |
1517 | struct tstorm_eth_st_context tstorm_st_context; | |
1518 | struct xstorm_eth_ag_context xstorm_ag_context; | |
1519 | struct tstorm_eth_ag_context tstorm_ag_context; | |
1520 | struct cstorm_eth_ag_context cstorm_ag_context; | |
1521 | struct ustorm_eth_ag_context ustorm_ag_context; | |
1522 | struct timers_block_context timers_context; | |
1523 | struct xstorm_eth_st_context xstorm_st_context; | |
1524 | struct cstorm_eth_st_context cstorm_st_context; | |
1525 | }; | |
1526 | ||
1527 | ||
1528 | /* | |
1529 | * ethernet doorbell | |
1530 | */ | |
1531 | struct eth_tx_doorbell { | |
1532 | #if defined(__BIG_ENDIAN) | |
1533 | u16 npackets; | |
1534 | u8 params; | |
1535 | #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) | |
1536 | #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 | |
1537 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) | |
1538 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 | |
1539 | #define ETH_TX_DOORBELL_SPARE (0x1<<7) | |
1540 | #define ETH_TX_DOORBELL_SPARE_SHIFT 7 | |
1541 | struct doorbell_hdr hdr; | |
1542 | #elif defined(__LITTLE_ENDIAN) | |
1543 | struct doorbell_hdr hdr; | |
1544 | u8 params; | |
1545 | #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) | |
1546 | #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 | |
1547 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) | |
1548 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 | |
1549 | #define ETH_TX_DOORBELL_SPARE (0x1<<7) | |
1550 | #define ETH_TX_DOORBELL_SPARE_SHIFT 7 | |
1551 | u16 npackets; | |
1552 | #endif | |
1553 | }; | |
1554 | ||
1555 | ||
1556 | /* | |
1557 | * ustorm status block | |
1558 | */ | |
1559 | struct ustorm_def_status_block { | |
1560 | u16 index_values[HC_USTORM_DEF_SB_NUM_INDICES]; | |
1561 | u16 status_block_index; | |
1562 | u8 reserved0; | |
1563 | u8 status_block_id; | |
1564 | u32 __flags; | |
1565 | }; | |
1566 | ||
1567 | /* | |
1568 | * cstorm status block | |
1569 | */ | |
1570 | struct cstorm_def_status_block { | |
1571 | u16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES]; | |
1572 | u16 status_block_index; | |
1573 | u8 reserved0; | |
1574 | u8 status_block_id; | |
1575 | u32 __flags; | |
1576 | }; | |
1577 | ||
1578 | /* | |
1579 | * xstorm status block | |
1580 | */ | |
1581 | struct xstorm_def_status_block { | |
1582 | u16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES]; | |
1583 | u16 status_block_index; | |
1584 | u8 reserved0; | |
1585 | u8 status_block_id; | |
1586 | u32 __flags; | |
1587 | }; | |
1588 | ||
1589 | /* | |
1590 | * tstorm status block | |
1591 | */ | |
1592 | struct tstorm_def_status_block { | |
1593 | u16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES]; | |
1594 | u16 status_block_index; | |
1595 | u8 reserved0; | |
1596 | u8 status_block_id; | |
1597 | u32 __flags; | |
1598 | }; | |
1599 | ||
1600 | /* | |
1601 | * host status block | |
1602 | */ | |
1603 | struct host_def_status_block { | |
1604 | struct atten_def_status_block atten_status_block; | |
1605 | struct ustorm_def_status_block u_def_status_block; | |
1606 | struct cstorm_def_status_block c_def_status_block; | |
1607 | struct xstorm_def_status_block x_def_status_block; | |
1608 | struct tstorm_def_status_block t_def_status_block; | |
1609 | }; | |
1610 | ||
1611 | ||
1612 | /* | |
1613 | * ustorm status block | |
1614 | */ | |
1615 | struct ustorm_status_block { | |
1616 | u16 index_values[HC_USTORM_SB_NUM_INDICES]; | |
1617 | u16 status_block_index; | |
1618 | u8 reserved0; | |
1619 | u8 status_block_id; | |
1620 | u32 __flags; | |
1621 | }; | |
1622 | ||
1623 | /* | |
1624 | * cstorm status block | |
1625 | */ | |
1626 | struct cstorm_status_block { | |
1627 | u16 index_values[HC_CSTORM_SB_NUM_INDICES]; | |
1628 | u16 status_block_index; | |
1629 | u8 reserved0; | |
1630 | u8 status_block_id; | |
1631 | u32 __flags; | |
1632 | }; | |
1633 | ||
1634 | /* | |
1635 | * host status block | |
1636 | */ | |
1637 | struct host_status_block { | |
1638 | struct ustorm_status_block u_status_block; | |
1639 | struct cstorm_status_block c_status_block; | |
1640 | }; | |
1641 | ||
1642 | ||
1643 | /* | |
1644 | * The data for RSS setup ramrod | |
1645 | */ | |
1646 | struct eth_client_setup_ramrod_data { | |
1647 | u32 client_id_5b; | |
1648 | u8 is_rdma_1b; | |
1649 | u8 reserved0; | |
1650 | u16 reserved1; | |
1651 | }; | |
1652 | ||
1653 | ||
1654 | /* | |
1655 | * L2 dynamic host coalescing init parameters | |
1656 | */ | |
1657 | struct eth_dynamic_hc_config { | |
1658 | u32 threshold[3]; | |
1659 | u8 hc_timeout[4]; | |
1660 | }; | |
1661 | ||
1662 | ||
1663 | /* | |
1664 | * regular eth FP CQE parameters struct | |
1665 | */ | |
1666 | struct eth_fast_path_rx_cqe { | |
1667 | u8 type; | |
1668 | u8 error_type_flags; | |
1669 | #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<0) | |
1670 | #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 0 | |
1671 | #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<1) | |
1672 | #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 1 | |
1673 | #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<2) | |
1674 | #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 2 | |
1675 | #define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<3) | |
1676 | #define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 3 | |
1677 | #define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<4) | |
1678 | #define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 4 | |
1679 | #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x7<<5) | |
1680 | #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 5 | |
1681 | u8 status_flags; | |
1682 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) | |
1683 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 | |
1684 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) | |
1685 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 | |
1686 | #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) | |
1687 | #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 | |
1688 | #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) | |
1689 | #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 | |
1690 | #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) | |
1691 | #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 | |
1692 | #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) | |
1693 | #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 | |
1694 | u8 placement_offset; | |
1695 | u32 rss_hash_result; | |
1696 | u16 vlan_tag; | |
1697 | u16 pkt_len; | |
1698 | u16 queue_index; | |
1699 | struct parsing_flags pars_flags; | |
1700 | }; | |
1701 | ||
1702 | ||
1703 | /* | |
1704 | * The data for RSS setup ramrod | |
1705 | */ | |
1706 | struct eth_halt_ramrod_data { | |
1707 | u32 client_id_5b; | |
1708 | u32 reserved0; | |
1709 | }; | |
1710 | ||
1711 | ||
1712 | /* | |
1713 | * Place holder for ramrods protocol specific data | |
1714 | */ | |
1715 | struct ramrod_data { | |
1716 | u32 data_lo; | |
1717 | u32 data_hi; | |
1718 | }; | |
1719 | ||
1720 | /* | |
1721 | * union for ramrod data for ethernet protocol (CQE) (force size of 16 bits) | |
1722 | */ | |
1723 | union eth_ramrod_data { | |
1724 | struct ramrod_data general; | |
1725 | }; | |
1726 | ||
1727 | ||
1728 | /* | |
1729 | * Rx Last BD in page (in ETH) | |
1730 | */ | |
1731 | struct eth_rx_bd_next_page { | |
1732 | u32 addr_lo; | |
1733 | u32 addr_hi; | |
1734 | u8 reserved[8]; | |
1735 | }; | |
1736 | ||
1737 | ||
1738 | /* | |
1739 | * Eth Rx Cqe structure- general structure for ramrods | |
1740 | */ | |
1741 | struct common_ramrod_eth_rx_cqe { | |
1742 | u8 type; | |
1743 | u8 conn_type_3b; | |
1744 | u16 reserved; | |
1745 | u32 conn_and_cmd_data; | |
1746 | #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) | |
1747 | #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 | |
1748 | #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) | |
1749 | #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 | |
1750 | struct ramrod_data protocol_data; | |
1751 | }; | |
1752 | ||
1753 | /* | |
1754 | * Rx Last CQE in page (in ETH) | |
1755 | */ | |
1756 | struct eth_rx_cqe_next_page { | |
1757 | u32 addr_lo; | |
1758 | u32 addr_hi; | |
1759 | u32 reserved0; | |
1760 | u32 reserved1; | |
1761 | }; | |
1762 | ||
1763 | /* | |
1764 | * union for all eth rx cqe types (fix their sizes) | |
1765 | */ | |
1766 | union eth_rx_cqe { | |
1767 | struct eth_fast_path_rx_cqe fast_path_cqe; | |
1768 | struct common_ramrod_eth_rx_cqe ramrod_cqe; | |
1769 | struct eth_rx_cqe_next_page next_page_cqe; | |
1770 | }; | |
1771 | ||
1772 | ||
1773 | /* | |
1774 | * common data for all protocols | |
1775 | */ | |
1776 | struct spe_hdr { | |
1777 | u32 conn_and_cmd_data; | |
1778 | #define SPE_HDR_CID (0xFFFFFF<<0) | |
1779 | #define SPE_HDR_CID_SHIFT 0 | |
1780 | #define SPE_HDR_CMD_ID (0xFF<<24) | |
1781 | #define SPE_HDR_CMD_ID_SHIFT 24 | |
1782 | u16 type; | |
1783 | #define SPE_HDR_CONN_TYPE (0xFF<<0) | |
1784 | #define SPE_HDR_CONN_TYPE_SHIFT 0 | |
1785 | #define SPE_HDR_COMMON_RAMROD (0xFF<<8) | |
1786 | #define SPE_HDR_COMMON_RAMROD_SHIFT 8 | |
1787 | u16 reserved; | |
1788 | }; | |
1789 | ||
1790 | struct regpair { | |
1791 | u32 lo; | |
1792 | u32 hi; | |
1793 | }; | |
1794 | ||
1795 | /* | |
1796 | * ethernet slow path element | |
1797 | */ | |
1798 | union eth_specific_data { | |
1799 | u8 protocol_data[8]; | |
1800 | struct regpair mac_config_addr; | |
1801 | struct eth_client_setup_ramrod_data client_setup_ramrod_data; | |
1802 | struct eth_halt_ramrod_data halt_ramrod_data; | |
1803 | struct regpair leading_cqe_addr; | |
1804 | struct regpair update_data_addr; | |
1805 | }; | |
1806 | ||
1807 | /* | |
1808 | * ethernet slow path element | |
1809 | */ | |
1810 | struct eth_spe { | |
1811 | struct spe_hdr hdr; | |
1812 | union eth_specific_data data; | |
1813 | }; | |
1814 | ||
1815 | ||
1816 | /* | |
1817 | * doorbell data in host memory | |
1818 | */ | |
1819 | struct eth_tx_db_data { | |
1820 | u32 packets_prod; | |
1821 | u16 bds_prod; | |
1822 | u16 reserved; | |
1823 | }; | |
1824 | ||
1825 | ||
1826 | /* | |
1827 | * Common configuration parameters per port in Tstorm | |
1828 | */ | |
1829 | struct tstorm_eth_function_common_config { | |
1830 | u32 config_flags; | |
1831 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) | |
1832 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 | |
1833 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) | |
1834 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 | |
1835 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) | |
1836 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 | |
1837 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) | |
1838 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 | |
1839 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE (0x1<<4) | |
1840 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4 | |
1841 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5) | |
1842 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5 | |
1843 | #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3FFFFFF<<6) | |
1844 | #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 6 | |
1845 | #if defined(__BIG_ENDIAN) | |
1846 | u16 __secondary_vlan_id; | |
1847 | u8 leading_client_id; | |
1848 | u8 rss_result_mask; | |
1849 | #elif defined(__LITTLE_ENDIAN) | |
1850 | u8 rss_result_mask; | |
1851 | u8 leading_client_id; | |
1852 | u16 __secondary_vlan_id; | |
1853 | #endif | |
1854 | }; | |
1855 | ||
1856 | /* | |
1857 | * parameters for eth update ramrod | |
1858 | */ | |
1859 | struct eth_update_ramrod_data { | |
1860 | struct tstorm_eth_function_common_config func_config; | |
1861 | u8 indirectionTable[128]; | |
1862 | }; | |
1863 | ||
1864 | ||
1865 | /* | |
1866 | * MAC filtering configuration command header | |
1867 | */ | |
1868 | struct mac_configuration_hdr { | |
1869 | u8 length_6b; | |
1870 | u8 offset; | |
1871 | u16 reserved0; | |
1872 | u32 reserved1; | |
1873 | }; | |
1874 | ||
1875 | /* | |
1876 | * MAC address in list for ramrod | |
1877 | */ | |
1878 | struct tstorm_cam_entry { | |
1879 | u16 lsb_mac_addr; | |
1880 | u16 middle_mac_addr; | |
1881 | u16 msb_mac_addr; | |
1882 | u16 flags; | |
1883 | #define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0) | |
1884 | #define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0 | |
1885 | #define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1) | |
1886 | #define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1 | |
1887 | #define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF<<4) | |
1888 | #define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4 | |
1889 | }; | |
1890 | ||
1891 | /* | |
1892 | * MAC filtering: CAM target table entry | |
1893 | */ | |
1894 | struct tstorm_cam_target_table_entry { | |
1895 | u8 flags; | |
1896 | #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1<<0) | |
1897 | #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0 | |
1898 | #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<1) | |
1899 | #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1 | |
1900 | #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1<<2) | |
1901 | #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2 | |
1902 | #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1<<3) | |
1903 | #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3 | |
1904 | #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4) | |
1905 | #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4 | |
1906 | u8 client_id; | |
1907 | u16 vlan_id; | |
1908 | }; | |
1909 | ||
1910 | /* | |
1911 | * MAC address in list for ramrod | |
1912 | */ | |
1913 | struct mac_configuration_entry { | |
1914 | struct tstorm_cam_entry cam_entry; | |
1915 | struct tstorm_cam_target_table_entry target_table_entry; | |
1916 | }; | |
1917 | ||
1918 | /* | |
1919 | * MAC filtering configuration command | |
1920 | */ | |
1921 | struct mac_configuration_cmd { | |
1922 | struct mac_configuration_hdr hdr; | |
1923 | struct mac_configuration_entry config_table[64]; | |
1924 | }; | |
1925 | ||
1926 | ||
1927 | /* | |
1928 | * Configuration parameters per client in Tstorm | |
1929 | */ | |
1930 | struct tstorm_eth_client_config { | |
1931 | #if defined(__BIG_ENDIAN) | |
1932 | u16 statistics_counter_id; | |
1933 | u16 mtu; | |
1934 | #elif defined(__LITTLE_ENDIAN) | |
1935 | u16 mtu; | |
1936 | u16 statistics_counter_id; | |
1937 | #endif | |
1938 | #if defined(__BIG_ENDIAN) | |
1939 | u16 drop_flags; | |
1940 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0) | |
1941 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0 | |
1942 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1) | |
1943 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1 | |
1944 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR (0x1<<2) | |
1945 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR_SHIFT 2 | |
1946 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<3) | |
1947 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 3 | |
1948 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<4) | |
1949 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 4 | |
1950 | #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x7FF<<5) | |
1951 | #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 5 | |
1952 | u16 config_flags; | |
1953 | #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0) | |
1954 | #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0 | |
1955 | #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1) | |
1956 | #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1 | |
1957 | #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x3FFF<<2) | |
1958 | #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 2 | |
1959 | #elif defined(__LITTLE_ENDIAN) | |
1960 | u16 config_flags; | |
1961 | #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0) | |
1962 | #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0 | |
1963 | #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1) | |
1964 | #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1 | |
1965 | #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x3FFF<<2) | |
1966 | #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 2 | |
1967 | u16 drop_flags; | |
1968 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0) | |
1969 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0 | |
1970 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1) | |
1971 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1 | |
1972 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR (0x1<<2) | |
1973 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR_SHIFT 2 | |
1974 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<3) | |
1975 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 3 | |
1976 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<4) | |
1977 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 4 | |
1978 | #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x7FF<<5) | |
1979 | #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 5 | |
1980 | #endif | |
1981 | }; | |
1982 | ||
1983 | ||
1984 | /* | |
1985 | * MAC filtering configuration parameters per port in Tstorm | |
1986 | */ | |
1987 | struct tstorm_eth_mac_filter_config { | |
1988 | u32 ucast_drop_all; | |
1989 | u32 ucast_accept_all; | |
1990 | u32 mcast_drop_all; | |
1991 | u32 mcast_accept_all; | |
1992 | u32 bcast_drop_all; | |
1993 | u32 bcast_accept_all; | |
1994 | u32 strict_vlan; | |
1995 | u32 __secondary_vlan_clients; | |
1996 | }; | |
1997 | ||
1998 | ||
1999 | struct rate_shaping_per_protocol { | |
2000 | #if defined(__BIG_ENDIAN) | |
2001 | u16 reserved0; | |
2002 | u16 protocol_rate; | |
2003 | #elif defined(__LITTLE_ENDIAN) | |
2004 | u16 protocol_rate; | |
2005 | u16 reserved0; | |
2006 | #endif | |
2007 | u32 protocol_quota; | |
2008 | s32 current_credit; | |
2009 | u32 reserved; | |
2010 | }; | |
2011 | ||
2012 | struct rate_shaping_vars { | |
2013 | struct rate_shaping_per_protocol protocol_vars[NUM_OF_PROTOCOLS]; | |
2014 | u32 pause_mask; | |
2015 | u32 periodic_stop; | |
2016 | u32 rs_periodic_timeout; | |
2017 | u32 rs_threshold; | |
2018 | u32 last_periodic_time; | |
2019 | u32 reserved; | |
2020 | }; | |
2021 | ||
2022 | struct fairness_per_protocol { | |
2023 | u32 credit_delta; | |
2024 | s32 fair_credit; | |
2025 | #if defined(__BIG_ENDIAN) | |
2026 | u16 reserved0; | |
2027 | u8 state; | |
2028 | u8 weight; | |
2029 | #elif defined(__LITTLE_ENDIAN) | |
2030 | u8 weight; | |
2031 | u8 state; | |
2032 | u16 reserved0; | |
2033 | #endif | |
2034 | u32 reserved1; | |
2035 | }; | |
2036 | ||
2037 | struct fairness_vars { | |
2038 | struct fairness_per_protocol protocol_vars[NUM_OF_PROTOCOLS]; | |
2039 | u32 upper_bound; | |
2040 | u32 port_rate; | |
2041 | u32 pause_mask; | |
2042 | u32 fair_threshold; | |
2043 | }; | |
2044 | ||
2045 | struct safc_struct { | |
2046 | u32 cur_pause_mask; | |
2047 | u32 expire_time; | |
2048 | #if defined(__BIG_ENDIAN) | |
2049 | u16 reserved0; | |
2050 | u8 cur_cos_types; | |
2051 | u8 safc_timeout_usec; | |
2052 | #elif defined(__LITTLE_ENDIAN) | |
2053 | u8 safc_timeout_usec; | |
2054 | u8 cur_cos_types; | |
2055 | u16 reserved0; | |
2056 | #endif | |
2057 | u32 reserved1; | |
2058 | }; | |
2059 | ||
2060 | struct demo_struct { | |
2061 | u8 con_number[NUM_OF_PROTOCOLS]; | |
2062 | #if defined(__BIG_ENDIAN) | |
2063 | u8 reserved1; | |
2064 | u8 fairness_enable; | |
2065 | u8 rate_shaping_enable; | |
2066 | u8 cmng_enable; | |
2067 | #elif defined(__LITTLE_ENDIAN) | |
2068 | u8 cmng_enable; | |
2069 | u8 rate_shaping_enable; | |
2070 | u8 fairness_enable; | |
2071 | u8 reserved1; | |
2072 | #endif | |
2073 | }; | |
2074 | ||
2075 | struct cmng_struct { | |
2076 | struct rate_shaping_vars rs_vars; | |
2077 | struct fairness_vars fair_vars; | |
2078 | struct safc_struct safc_vars; | |
2079 | struct demo_struct demo_vars; | |
2080 | }; | |
2081 | ||
2082 | ||
2083 | struct cos_to_protocol { | |
2084 | u8 mask[MAX_COS_NUMBER]; | |
2085 | }; | |
2086 | ||
2087 | ||
2088 | /* | |
2089 | * Common statistics collected by the Xstorm (per port) | |
2090 | */ | |
2091 | struct xstorm_common_stats { | |
2092 | struct regpair total_sent_bytes; | |
2093 | u32 total_sent_pkts; | |
2094 | u32 unicast_pkts_sent; | |
2095 | struct regpair unicast_bytes_sent; | |
2096 | struct regpair multicast_bytes_sent; | |
2097 | u32 multicast_pkts_sent; | |
2098 | u32 broadcast_pkts_sent; | |
2099 | struct regpair broadcast_bytes_sent; | |
2100 | struct regpair done; | |
2101 | }; | |
2102 | ||
2103 | /* | |
2104 | * Protocol-common statistics collected by the Tstorm (per client) | |
2105 | */ | |
2106 | struct tstorm_per_client_stats { | |
2107 | struct regpair total_rcv_bytes; | |
2108 | struct regpair rcv_unicast_bytes; | |
2109 | struct regpair rcv_broadcast_bytes; | |
2110 | struct regpair rcv_multicast_bytes; | |
2111 | struct regpair rcv_error_bytes; | |
2112 | u32 checksum_discard; | |
2113 | u32 packets_too_big_discard; | |
2114 | u32 total_rcv_pkts; | |
2115 | u32 rcv_unicast_pkts; | |
2116 | u32 rcv_broadcast_pkts; | |
2117 | u32 rcv_multicast_pkts; | |
2118 | u32 no_buff_discard; | |
2119 | u32 ttl0_discard; | |
2120 | u32 mac_discard; | |
2121 | u32 reserved; | |
2122 | }; | |
2123 | ||
2124 | /* | |
2125 | * Protocol-common statistics collected by the Tstorm (per port) | |
2126 | */ | |
2127 | struct tstorm_common_stats { | |
2128 | struct tstorm_per_client_stats client_statistics[MAX_T_STAT_COUNTER_ID]; | |
2129 | u32 mac_filter_discard; | |
2130 | u32 xxoverflow_discard; | |
2131 | u32 brb_truncate_discard; | |
2132 | u32 reserved; | |
2133 | struct regpair done; | |
2134 | }; | |
2135 | ||
2136 | /* | |
2137 | * Eth statistics query sturcture for the eth_stats_quesry ramrod | |
2138 | */ | |
2139 | struct eth_stats_query { | |
2140 | struct xstorm_common_stats xstorm_common; | |
2141 | struct tstorm_common_stats tstorm_common; | |
2142 | }; | |
2143 | ||
2144 | ||
2145 | /* | |
2146 | * FW version stored in the Xstorm RAM | |
2147 | */ | |
2148 | struct fw_version { | |
2149 | #if defined(__BIG_ENDIAN) | |
2150 | u16 patch; | |
2151 | u8 primary; | |
2152 | u8 client; | |
2153 | #elif defined(__LITTLE_ENDIAN) | |
2154 | u8 client; | |
2155 | u8 primary; | |
2156 | u16 patch; | |
2157 | #endif | |
2158 | u32 flags; | |
2159 | #define FW_VERSION_OPTIMIZED (0x1<<0) | |
2160 | #define FW_VERSION_OPTIMIZED_SHIFT 0 | |
2161 | #define FW_VERSION_BIG_ENDIEN (0x1<<1) | |
2162 | #define FW_VERSION_BIG_ENDIEN_SHIFT 1 | |
2163 | #define __FW_VERSION_RESERVED (0x3FFFFFFF<<2) | |
2164 | #define __FW_VERSION_RESERVED_SHIFT 2 | |
2165 | }; | |
2166 | ||
2167 | ||
2168 | /* | |
2169 | * FW version stored in first line of pram | |
2170 | */ | |
2171 | struct pram_fw_version { | |
2172 | #if defined(__BIG_ENDIAN) | |
2173 | u16 patch; | |
2174 | u8 primary; | |
2175 | u8 client; | |
2176 | #elif defined(__LITTLE_ENDIAN) | |
2177 | u8 client; | |
2178 | u8 primary; | |
2179 | u16 patch; | |
2180 | #endif | |
2181 | u8 flags; | |
2182 | #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) | |
2183 | #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 | |
2184 | #define PRAM_FW_VERSION_STORM_ID (0x3<<1) | |
2185 | #define PRAM_FW_VERSION_STORM_ID_SHIFT 1 | |
2186 | #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) | |
2187 | #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 | |
2188 | #define __PRAM_FW_VERSION_RESERVED0 (0xF<<4) | |
2189 | #define __PRAM_FW_VERSION_RESERVED0_SHIFT 4 | |
2190 | }; | |
2191 | ||
2192 | ||
2193 | /* | |
2194 | * The send queue element | |
2195 | */ | |
2196 | struct slow_path_element { | |
2197 | struct spe_hdr hdr; | |
2198 | u8 protocol_data[8]; | |
2199 | }; | |
2200 | ||
2201 | ||
2202 | /* | |
2203 | * eth/toe flags that indicate if to query | |
2204 | */ | |
2205 | struct stats_indication_flags { | |
2206 | u32 collect_eth; | |
2207 | u32 collect_toe; | |
2208 | }; | |
2209 | ||
2210 |