Commit | Line | Data |
---|---|---|
a2fbb9ea ET |
1 | /* bnx2x_reg.h: Broadcom Everest network driver. |
2 | * | |
d05c26ce | 3 | * Copyright (c) 2007-2009 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
33471629 | 9 | * The registers description starts with the register Access type followed |
a2fbb9ea ET |
10 | * by size in bits. For example [RW 32]. The access types are: |
11 | * R - Read only | |
12 | * RC - Clear on read | |
13 | * RW - Read/Write | |
14 | * ST - Statistics register (clear on read) | |
15 | * W - Write only | |
16 | * WB - Wide bus register - the size is over 32 bits and it should be | |
17 | * read/write in consecutive 32 bits accesses | |
18 | * WR - Write Clear (write 1 to clear the bit) | |
19 | * | |
20 | */ | |
21 | ||
22 | ||
23 | /* [R 19] Interrupt register #0 read */ | |
24 | #define BRB1_REG_BRB1_INT_STS 0x6011c | |
25 | /* [RW 4] Parity mask register #0 read/write */ | |
26 | #define BRB1_REG_BRB1_PRTY_MASK 0x60138 | |
f1410647 ET |
27 | /* [R 4] Parity register #0 read */ |
28 | #define BRB1_REG_BRB1_PRTY_STS 0x6012c | |
a2fbb9ea ET |
29 | /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At |
30 | address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address | |
31 | BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. */ | |
32 | #define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200 | |
1c06328c EG |
33 | /* [RW 10] The number of free blocks above which the High_llfc signal to |
34 | interface #n is de-asserted. */ | |
35 | #define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c | |
36 | /* [RW 10] The number of free blocks below which the High_llfc signal to | |
37 | interface #n is asserted. */ | |
38 | #define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c | |
a2fbb9ea ET |
39 | /* [RW 23] LL RAM data. */ |
40 | #define BRB1_REG_LL_RAM 0x61000 | |
1c06328c EG |
41 | /* [RW 10] The number of free blocks above which the Low_llfc signal to |
42 | interface #n is de-asserted. */ | |
43 | #define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c | |
44 | /* [RW 10] The number of free blocks below which the Low_llfc signal to | |
45 | interface #n is asserted. */ | |
46 | #define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c | |
a2fbb9ea ET |
47 | /* [R 24] The number of full blocks. */ |
48 | #define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090 | |
49 | /* [ST 32] The number of cycles that the write_full signal towards MAC #0 | |
50 | was asserted. */ | |
51 | #define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8 | |
52 | #define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc | |
a2fbb9ea ET |
53 | #define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8 |
54 | /* [ST 32] The number of cycles that the pause signal towards MAC #0 was | |
55 | asserted. */ | |
56 | #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8 | |
57 | #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc | |
a2fbb9ea ET |
58 | /* [RW 10] Write client 0: De-assert pause threshold. */ |
59 | #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078 | |
60 | #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c | |
61 | /* [RW 10] Write client 0: Assert pause threshold. */ | |
62 | #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068 | |
63 | #define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c | |
33471629 | 64 | /* [R 24] The number of full blocks occupied by port. */ |
34f80b04 | 65 | #define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094 |
a2fbb9ea ET |
66 | /* [RW 1] Reset the design by software. */ |
67 | #define BRB1_REG_SOFT_RESET 0x600dc | |
68 | /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */ | |
69 | #define CCM_REG_CAM_OCCUP 0xd0188 | |
70 | /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; | |
71 | acknowledge output is deasserted; all other signals are treated as usual; | |
72 | if 1 - normal activity. */ | |
73 | #define CCM_REG_CCM_CFC_IFEN 0xd003c | |
74 | /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is | |
75 | disregarded; valid is deasserted; all other signals are treated as usual; | |
76 | if 1 - normal activity. */ | |
77 | #define CCM_REG_CCM_CQM_IFEN 0xd000c | |
78 | /* [RW 1] If set the Q index; received from the QM is inserted to event ID. | |
79 | Otherwise 0 is inserted. */ | |
80 | #define CCM_REG_CCM_CQM_USE_Q 0xd00c0 | |
81 | /* [RW 11] Interrupt mask register #0 read/write */ | |
82 | #define CCM_REG_CCM_INT_MASK 0xd01e4 | |
83 | /* [R 11] Interrupt register #0 read */ | |
84 | #define CCM_REG_CCM_INT_STS 0xd01d8 | |
c18487ee YR |
85 | /* [R 27] Parity register #0 read */ |
86 | #define CCM_REG_CCM_PRTY_STS 0xd01e8 | |
a2fbb9ea ET |
87 | /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS |
88 | REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). | |
89 | Is used to determine the number of the AG context REG-pairs written back; | |
90 | when the input message Reg1WbFlg isn't set. */ | |
91 | #define CCM_REG_CCM_REG0_SZ 0xd00c4 | |
92 | /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is | |
93 | disregarded; valid is deasserted; all other signals are treated as usual; | |
94 | if 1 - normal activity. */ | |
95 | #define CCM_REG_CCM_STORM0_IFEN 0xd0004 | |
96 | /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is | |
97 | disregarded; valid is deasserted; all other signals are treated as usual; | |
98 | if 1 - normal activity. */ | |
99 | #define CCM_REG_CCM_STORM1_IFEN 0xd0008 | |
100 | /* [RW 1] CDU AG read Interface enable. If 0 - the request input is | |
101 | disregarded; valid output is deasserted; all other signals are treated as | |
102 | usual; if 1 - normal activity. */ | |
103 | #define CCM_REG_CDU_AG_RD_IFEN 0xd0030 | |
104 | /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input | |
105 | are disregarded; all other signals are treated as usual; if 1 - normal | |
106 | activity. */ | |
107 | #define CCM_REG_CDU_AG_WR_IFEN 0xd002c | |
108 | /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is | |
109 | disregarded; valid output is deasserted; all other signals are treated as | |
110 | usual; if 1 - normal activity. */ | |
111 | #define CCM_REG_CDU_SM_RD_IFEN 0xd0038 | |
112 | /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid | |
113 | input is disregarded; all other signals are treated as usual; if 1 - | |
114 | normal activity. */ | |
115 | #define CCM_REG_CDU_SM_WR_IFEN 0xd0034 | |
116 | /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes | |
117 | the initial credit value; read returns the current value of the credit | |
118 | counter. Must be initialized to 1 at start-up. */ | |
119 | #define CCM_REG_CFC_INIT_CRD 0xd0204 | |
120 | /* [RW 2] Auxillary counter flag Q number 1. */ | |
121 | #define CCM_REG_CNT_AUX1_Q 0xd00c8 | |
122 | /* [RW 2] Auxillary counter flag Q number 2. */ | |
123 | #define CCM_REG_CNT_AUX2_Q 0xd00cc | |
124 | /* [RW 28] The CM header value for QM request (primary). */ | |
125 | #define CCM_REG_CQM_CCM_HDR_P 0xd008c | |
126 | /* [RW 28] The CM header value for QM request (secondary). */ | |
127 | #define CCM_REG_CQM_CCM_HDR_S 0xd0090 | |
128 | /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; | |
129 | acknowledge output is deasserted; all other signals are treated as usual; | |
130 | if 1 - normal activity. */ | |
131 | #define CCM_REG_CQM_CCM_IFEN 0xd0014 | |
132 | /* [RW 6] QM output initial credit. Max credit available - 32. Write writes | |
133 | the initial credit value; read returns the current value of the credit | |
134 | counter. Must be initialized to 32 at start-up. */ | |
135 | #define CCM_REG_CQM_INIT_CRD 0xd020c | |
136 | /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 | |
137 | stands for weight 8 (the most prioritised); 1 stands for weight 1(least | |
138 | prioritised); 2 stands for weight 2; tc. */ | |
139 | #define CCM_REG_CQM_P_WEIGHT 0xd00b8 | |
8d9c5f34 EG |
140 | /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 |
141 | stands for weight 8 (the most prioritised); 1 stands for weight 1(least | |
142 | prioritised); 2 stands for weight 2; tc. */ | |
143 | #define CCM_REG_CQM_S_WEIGHT 0xd00bc | |
a2fbb9ea ET |
144 | /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; |
145 | acknowledge output is deasserted; all other signals are treated as usual; | |
146 | if 1 - normal activity. */ | |
147 | #define CCM_REG_CSDM_IFEN 0xd0018 | |
148 | /* [RC 1] Set when the message length mismatch (relative to last indication) | |
149 | at the SDM interface is detected. */ | |
150 | #define CCM_REG_CSDM_LENGTH_MIS 0xd0170 | |
8d9c5f34 EG |
151 | /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for |
152 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
153 | prioritised); 2 stands for weight 2; tc. */ | |
154 | #define CCM_REG_CSDM_WEIGHT 0xd00b4 | |
a2fbb9ea ET |
155 | /* [RW 28] The CM header for QM formatting in case of an error in the QM |
156 | inputs. */ | |
157 | #define CCM_REG_ERR_CCM_HDR 0xd0094 | |
158 | /* [RW 8] The Event ID in case the input message ErrorFlg is set. */ | |
159 | #define CCM_REG_ERR_EVNT_ID 0xd0098 | |
160 | /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write | |
161 | writes the initial credit value; read returns the current value of the | |
162 | credit counter. Must be initialized to 64 at start-up. */ | |
163 | #define CCM_REG_FIC0_INIT_CRD 0xd0210 | |
164 | /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write | |
165 | writes the initial credit value; read returns the current value of the | |
166 | credit counter. Must be initialized to 64 at start-up. */ | |
167 | #define CCM_REG_FIC1_INIT_CRD 0xd0214 | |
168 | /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 | |
169 | - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr; | |
170 | ~ccm_registers_gr_ld0_pr.gr_ld0_pr and | |
171 | ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and | |
172 | outputs to STORM: aggregation; load FIC0; load FIC1 and store. */ | |
173 | #define CCM_REG_GR_ARB_TYPE 0xd015c | |
174 | /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the | |
175 | highest priority is 3. It is supposed; that the Store channel priority is | |
176 | the compliment to 4 of the rest priorities - Aggregation channel; Load | |
177 | (FIC0) channel and Load (FIC1). */ | |
178 | #define CCM_REG_GR_LD0_PR 0xd0164 | |
179 | /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the | |
180 | highest priority is 3. It is supposed; that the Store channel priority is | |
181 | the compliment to 4 of the rest priorities - Aggregation channel; Load | |
182 | (FIC0) channel and Load (FIC1). */ | |
183 | #define CCM_REG_GR_LD1_PR 0xd0168 | |
184 | /* [RW 2] General flags index. */ | |
185 | #define CCM_REG_INV_DONE_Q 0xd0108 | |
186 | /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM | |
187 | context and sent to STORM; for a specific connection type. The double | |
188 | REG-pairs are used in order to align to STORM context row size of 128 | |
189 | bits. The offset of these data in the STORM context is always 0. Index | |
190 | _(0..15) stands for the connection type (one of 16). */ | |
191 | #define CCM_REG_N_SM_CTX_LD_0 0xd004c | |
192 | #define CCM_REG_N_SM_CTX_LD_1 0xd0050 | |
193 | #define CCM_REG_N_SM_CTX_LD_10 0xd0074 | |
194 | #define CCM_REG_N_SM_CTX_LD_11 0xd0078 | |
195 | #define CCM_REG_N_SM_CTX_LD_12 0xd007c | |
196 | #define CCM_REG_N_SM_CTX_LD_13 0xd0080 | |
197 | #define CCM_REG_N_SM_CTX_LD_14 0xd0084 | |
198 | #define CCM_REG_N_SM_CTX_LD_15 0xd0088 | |
199 | #define CCM_REG_N_SM_CTX_LD_2 0xd0054 | |
200 | #define CCM_REG_N_SM_CTX_LD_3 0xd0058 | |
201 | #define CCM_REG_N_SM_CTX_LD_4 0xd005c | |
202 | /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; | |
203 | acknowledge output is deasserted; all other signals are treated as usual; | |
204 | if 1 - normal activity. */ | |
205 | #define CCM_REG_PBF_IFEN 0xd0028 | |
206 | /* [RC 1] Set when the message length mismatch (relative to last indication) | |
207 | at the pbf interface is detected. */ | |
208 | #define CCM_REG_PBF_LENGTH_MIS 0xd0180 | |
209 | /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for | |
210 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
211 | prioritised); 2 stands for weight 2; tc. */ | |
212 | #define CCM_REG_PBF_WEIGHT 0xd00ac | |
a2fbb9ea ET |
213 | #define CCM_REG_PHYS_QNUM1_0 0xd0134 |
214 | #define CCM_REG_PHYS_QNUM1_1 0xd0138 | |
a2fbb9ea ET |
215 | #define CCM_REG_PHYS_QNUM2_0 0xd013c |
216 | #define CCM_REG_PHYS_QNUM2_1 0xd0140 | |
a2fbb9ea | 217 | #define CCM_REG_PHYS_QNUM3_0 0xd0144 |
c18487ee | 218 | #define CCM_REG_PHYS_QNUM3_1 0xd0148 |
a2fbb9ea ET |
219 | #define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114 |
220 | #define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118 | |
a2fbb9ea ET |
221 | #define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c |
222 | #define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120 | |
a2fbb9ea | 223 | #define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124 |
c18487ee YR |
224 | #define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128 |
225 | #define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c | |
226 | #define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130 | |
a2fbb9ea ET |
227 | /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is |
228 | disregarded; acknowledge output is deasserted; all other signals are | |
229 | treated as usual; if 1 - normal activity. */ | |
230 | #define CCM_REG_STORM_CCM_IFEN 0xd0010 | |
231 | /* [RC 1] Set when the message length mismatch (relative to last indication) | |
232 | at the STORM interface is detected. */ | |
233 | #define CCM_REG_STORM_LENGTH_MIS 0xd016c | |
8d9c5f34 EG |
234 | /* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin) |
235 | mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for | |
236 | weight 1(least prioritised); 2 stands for weight 2 (more prioritised); | |
237 | tc. */ | |
238 | #define CCM_REG_STORM_WEIGHT 0xd009c | |
a2fbb9ea ET |
239 | /* [RW 1] Input tsem Interface enable. If 0 - the valid input is |
240 | disregarded; acknowledge output is deasserted; all other signals are | |
241 | treated as usual; if 1 - normal activity. */ | |
242 | #define CCM_REG_TSEM_IFEN 0xd001c | |
243 | /* [RC 1] Set when the message length mismatch (relative to last indication) | |
244 | at the tsem interface is detected. */ | |
245 | #define CCM_REG_TSEM_LENGTH_MIS 0xd0174 | |
246 | /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for | |
247 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
248 | prioritised); 2 stands for weight 2; tc. */ | |
249 | #define CCM_REG_TSEM_WEIGHT 0xd00a0 | |
250 | /* [RW 1] Input usem Interface enable. If 0 - the valid input is | |
251 | disregarded; acknowledge output is deasserted; all other signals are | |
252 | treated as usual; if 1 - normal activity. */ | |
253 | #define CCM_REG_USEM_IFEN 0xd0024 | |
254 | /* [RC 1] Set when message length mismatch (relative to last indication) at | |
255 | the usem interface is detected. */ | |
256 | #define CCM_REG_USEM_LENGTH_MIS 0xd017c | |
257 | /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for | |
258 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
259 | prioritised); 2 stands for weight 2; tc. */ | |
260 | #define CCM_REG_USEM_WEIGHT 0xd00a8 | |
261 | /* [RW 1] Input xsem Interface enable. If 0 - the valid input is | |
262 | disregarded; acknowledge output is deasserted; all other signals are | |
263 | treated as usual; if 1 - normal activity. */ | |
264 | #define CCM_REG_XSEM_IFEN 0xd0020 | |
265 | /* [RC 1] Set when the message length mismatch (relative to last indication) | |
266 | at the xsem interface is detected. */ | |
267 | #define CCM_REG_XSEM_LENGTH_MIS 0xd0178 | |
268 | /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for | |
269 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
270 | prioritised); 2 stands for weight 2; tc. */ | |
271 | #define CCM_REG_XSEM_WEIGHT 0xd00a4 | |
272 | /* [RW 19] Indirect access to the descriptor table of the XX protection | |
273 | mechanism. The fields are: [5:0] - message length; [12:6] - message | |
274 | pointer; 18:13] - next pointer. */ | |
275 | #define CCM_REG_XX_DESCR_TABLE 0xd0300 | |
c18487ee | 276 | #define CCM_REG_XX_DESCR_TABLE_SIZE 36 |
a2fbb9ea ET |
277 | /* [R 7] Used to read the value of XX protection Free counter. */ |
278 | #define CCM_REG_XX_FREE 0xd0184 | |
279 | /* [RW 6] Initial value for the credit counter; responsible for fulfilling | |
280 | of the Input Stage XX protection buffer by the XX protection pending | |
281 | messages. Max credit available - 127. Write writes the initial credit | |
282 | value; read returns the current value of the credit counter. Must be | |
283 | initialized to maximum XX protected message size - 2 at start-up. */ | |
284 | #define CCM_REG_XX_INIT_CRD 0xd0220 | |
285 | /* [RW 7] The maximum number of pending messages; which may be stored in XX | |
286 | protection. At read the ~ccm_registers_xx_free.xx_free counter is read. | |
287 | At write comprises the start value of the ~ccm_registers_xx_free.xx_free | |
288 | counter. */ | |
289 | #define CCM_REG_XX_MSG_NUM 0xd0224 | |
290 | /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ | |
291 | #define CCM_REG_XX_OVFL_EVNT_ID 0xd0044 | |
292 | /* [RW 18] Indirect access to the XX table of the XX protection mechanism. | |
293 | The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] - | |
294 | header pointer. */ | |
295 | #define CCM_REG_XX_TABLE 0xd0280 | |
296 | #define CDU_REG_CDU_CHK_MASK0 0x101000 | |
297 | #define CDU_REG_CDU_CHK_MASK1 0x101004 | |
298 | #define CDU_REG_CDU_CONTROL0 0x101008 | |
299 | #define CDU_REG_CDU_DEBUG 0x101010 | |
300 | #define CDU_REG_CDU_GLOBAL_PARAMS 0x101020 | |
301 | /* [RW 7] Interrupt mask register #0 read/write */ | |
302 | #define CDU_REG_CDU_INT_MASK 0x10103c | |
303 | /* [R 7] Interrupt register #0 read */ | |
304 | #define CDU_REG_CDU_INT_STS 0x101030 | |
305 | /* [RW 5] Parity mask register #0 read/write */ | |
306 | #define CDU_REG_CDU_PRTY_MASK 0x10104c | |
f1410647 ET |
307 | /* [R 5] Parity register #0 read */ |
308 | #define CDU_REG_CDU_PRTY_STS 0x101040 | |
a2fbb9ea ET |
309 | /* [RC 32] logging of error data in case of a CDU load error: |
310 | {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error; | |
311 | ype_error; ctual_active; ctual_compressed_context}; */ | |
312 | #define CDU_REG_ERROR_DATA 0x101014 | |
313 | /* [WB 216] L1TT ram access. each entry has the following format : | |
314 | {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0]; | |
315 | ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */ | |
316 | #define CDU_REG_L1TT 0x101800 | |
317 | /* [WB 24] MATT ram access. each entry has the following | |
318 | format:{RegionLength[11:0]; egionOffset[11:0]} */ | |
319 | #define CDU_REG_MATT 0x101100 | |
c18487ee YR |
320 | /* [RW 1] when this bit is set the CDU operates in e1hmf mode */ |
321 | #define CDU_REG_MF_MODE 0x101050 | |
a2fbb9ea ET |
322 | /* [R 1] indication the initializing the activity counter by the hardware |
323 | was done. */ | |
324 | #define CFC_REG_AC_INIT_DONE 0x104078 | |
325 | /* [RW 13] activity counter ram access */ | |
326 | #define CFC_REG_ACTIVITY_COUNTER 0x104400 | |
327 | #define CFC_REG_ACTIVITY_COUNTER_SIZE 256 | |
328 | /* [R 1] indication the initializing the cams by the hardware was done. */ | |
329 | #define CFC_REG_CAM_INIT_DONE 0x10407c | |
330 | /* [RW 2] Interrupt mask register #0 read/write */ | |
331 | #define CFC_REG_CFC_INT_MASK 0x104108 | |
332 | /* [R 2] Interrupt register #0 read */ | |
333 | #define CFC_REG_CFC_INT_STS 0x1040fc | |
334 | /* [RC 2] Interrupt register #0 read clear */ | |
335 | #define CFC_REG_CFC_INT_STS_CLR 0x104100 | |
336 | /* [RW 4] Parity mask register #0 read/write */ | |
337 | #define CFC_REG_CFC_PRTY_MASK 0x104118 | |
f1410647 ET |
338 | /* [R 4] Parity register #0 read */ |
339 | #define CFC_REG_CFC_PRTY_STS 0x10410c | |
a2fbb9ea ET |
340 | /* [RW 21] CID cam access (21:1 - Data; alid - 0) */ |
341 | #define CFC_REG_CID_CAM 0x104800 | |
342 | #define CFC_REG_CONTROL0 0x104028 | |
343 | #define CFC_REG_DEBUG0 0x104050 | |
344 | /* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error | |
345 | vector) whether the cfc should be disabled upon it */ | |
346 | #define CFC_REG_DISABLE_ON_ERROR 0x104044 | |
347 | /* [RC 14] CFC error vector. when the CFC detects an internal error it will | |
348 | set one of these bits. the bit description can be found in CFC | |
349 | specifications */ | |
350 | #define CFC_REG_ERROR_VECTOR 0x10403c | |
8d9c5f34 EG |
351 | /* [WB 93] LCID info ram access */ |
352 | #define CFC_REG_INFO_RAM 0x105000 | |
353 | #define CFC_REG_INFO_RAM_SIZE 1024 | |
a2fbb9ea | 354 | #define CFC_REG_INIT_REG 0x10404c |
8d9c5f34 | 355 | #define CFC_REG_INTERFACES 0x104058 |
a2fbb9ea ET |
356 | /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this |
357 | field allows changing the priorities of the weighted-round-robin arbiter | |
358 | which selects which CFC load client should be served next */ | |
359 | #define CFC_REG_LCREQ_WEIGHTS 0x104084 | |
c18487ee YR |
360 | /* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */ |
361 | #define CFC_REG_LINK_LIST 0x104c00 | |
362 | #define CFC_REG_LINK_LIST_SIZE 256 | |
a2fbb9ea ET |
363 | /* [R 1] indication the initializing the link list by the hardware was done. */ |
364 | #define CFC_REG_LL_INIT_DONE 0x104074 | |
365 | /* [R 9] Number of allocated LCIDs which are at empty state */ | |
366 | #define CFC_REG_NUM_LCIDS_ALLOC 0x104020 | |
367 | /* [R 9] Number of Arriving LCIDs in Link List Block */ | |
368 | #define CFC_REG_NUM_LCIDS_ARRIVING 0x104004 | |
a2fbb9ea ET |
369 | /* [R 9] Number of Leaving LCIDs in Link List Block */ |
370 | #define CFC_REG_NUM_LCIDS_LEAVING 0x104018 | |
371 | /* [RW 8] The event id for aggregated interrupt 0 */ | |
372 | #define CSDM_REG_AGG_INT_EVENT_0 0xc2038 | |
c18487ee YR |
373 | #define CSDM_REG_AGG_INT_EVENT_1 0xc203c |
374 | #define CSDM_REG_AGG_INT_EVENT_10 0xc2060 | |
375 | #define CSDM_REG_AGG_INT_EVENT_11 0xc2064 | |
376 | #define CSDM_REG_AGG_INT_EVENT_12 0xc2068 | |
377 | #define CSDM_REG_AGG_INT_EVENT_13 0xc206c | |
378 | #define CSDM_REG_AGG_INT_EVENT_14 0xc2070 | |
379 | #define CSDM_REG_AGG_INT_EVENT_15 0xc2074 | |
380 | #define CSDM_REG_AGG_INT_EVENT_16 0xc2078 | |
381 | #define CSDM_REG_AGG_INT_EVENT_17 0xc207c | |
382 | #define CSDM_REG_AGG_INT_EVENT_18 0xc2080 | |
383 | #define CSDM_REG_AGG_INT_EVENT_19 0xc2084 | |
384 | #define CSDM_REG_AGG_INT_EVENT_2 0xc2040 | |
385 | #define CSDM_REG_AGG_INT_EVENT_20 0xc2088 | |
386 | #define CSDM_REG_AGG_INT_EVENT_21 0xc208c | |
387 | #define CSDM_REG_AGG_INT_EVENT_22 0xc2090 | |
388 | #define CSDM_REG_AGG_INT_EVENT_23 0xc2094 | |
389 | #define CSDM_REG_AGG_INT_EVENT_24 0xc2098 | |
390 | #define CSDM_REG_AGG_INT_EVENT_25 0xc209c | |
391 | #define CSDM_REG_AGG_INT_EVENT_26 0xc20a0 | |
392 | #define CSDM_REG_AGG_INT_EVENT_27 0xc20a4 | |
393 | #define CSDM_REG_AGG_INT_EVENT_28 0xc20a8 | |
394 | #define CSDM_REG_AGG_INT_EVENT_29 0xc20ac | |
395 | #define CSDM_REG_AGG_INT_EVENT_3 0xc2044 | |
396 | #define CSDM_REG_AGG_INT_EVENT_30 0xc20b0 | |
397 | #define CSDM_REG_AGG_INT_EVENT_31 0xc20b4 | |
398 | #define CSDM_REG_AGG_INT_EVENT_4 0xc2048 | |
399 | /* [RW 1] The T bit for aggregated interrupt 0 */ | |
400 | #define CSDM_REG_AGG_INT_T_0 0xc20b8 | |
401 | #define CSDM_REG_AGG_INT_T_1 0xc20bc | |
402 | #define CSDM_REG_AGG_INT_T_10 0xc20e0 | |
403 | #define CSDM_REG_AGG_INT_T_11 0xc20e4 | |
404 | #define CSDM_REG_AGG_INT_T_12 0xc20e8 | |
405 | #define CSDM_REG_AGG_INT_T_13 0xc20ec | |
406 | #define CSDM_REG_AGG_INT_T_14 0xc20f0 | |
407 | #define CSDM_REG_AGG_INT_T_15 0xc20f4 | |
408 | #define CSDM_REG_AGG_INT_T_16 0xc20f8 | |
409 | #define CSDM_REG_AGG_INT_T_17 0xc20fc | |
410 | #define CSDM_REG_AGG_INT_T_18 0xc2100 | |
411 | #define CSDM_REG_AGG_INT_T_19 0xc2104 | |
a2fbb9ea ET |
412 | /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ |
413 | #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008 | |
414 | /* [RW 16] The maximum value of the competion counter #0 */ | |
415 | #define CSDM_REG_CMP_COUNTER_MAX0 0xc201c | |
416 | /* [RW 16] The maximum value of the competion counter #1 */ | |
417 | #define CSDM_REG_CMP_COUNTER_MAX1 0xc2020 | |
418 | /* [RW 16] The maximum value of the competion counter #2 */ | |
419 | #define CSDM_REG_CMP_COUNTER_MAX2 0xc2024 | |
420 | /* [RW 16] The maximum value of the competion counter #3 */ | |
421 | #define CSDM_REG_CMP_COUNTER_MAX3 0xc2028 | |
422 | /* [RW 13] The start address in the internal RAM for the completion | |
423 | counters. */ | |
424 | #define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c | |
425 | /* [RW 32] Interrupt mask register #0 read/write */ | |
426 | #define CSDM_REG_CSDM_INT_MASK_0 0xc229c | |
427 | #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac | |
c18487ee YR |
428 | /* [R 32] Interrupt register #0 read */ |
429 | #define CSDM_REG_CSDM_INT_STS_0 0xc2290 | |
430 | #define CSDM_REG_CSDM_INT_STS_1 0xc22a0 | |
a2fbb9ea ET |
431 | /* [RW 11] Parity mask register #0 read/write */ |
432 | #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc | |
f1410647 ET |
433 | /* [R 11] Parity register #0 read */ |
434 | #define CSDM_REG_CSDM_PRTY_STS 0xc22b0 | |
a2fbb9ea ET |
435 | #define CSDM_REG_ENABLE_IN1 0xc2238 |
436 | #define CSDM_REG_ENABLE_IN2 0xc223c | |
437 | #define CSDM_REG_ENABLE_OUT1 0xc2240 | |
438 | #define CSDM_REG_ENABLE_OUT2 0xc2244 | |
439 | /* [RW 4] The initial number of messages that can be sent to the pxp control | |
440 | interface without receiving any ACK. */ | |
441 | #define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc | |
442 | /* [ST 32] The number of ACK after placement messages received */ | |
443 | #define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c | |
444 | /* [ST 32] The number of packet end messages received from the parser */ | |
445 | #define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274 | |
446 | /* [ST 32] The number of requests received from the pxp async if */ | |
447 | #define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278 | |
448 | /* [ST 32] The number of commands received in queue 0 */ | |
449 | #define CSDM_REG_NUM_OF_Q0_CMD 0xc2248 | |
450 | /* [ST 32] The number of commands received in queue 10 */ | |
451 | #define CSDM_REG_NUM_OF_Q10_CMD 0xc226c | |
452 | /* [ST 32] The number of commands received in queue 11 */ | |
453 | #define CSDM_REG_NUM_OF_Q11_CMD 0xc2270 | |
454 | /* [ST 32] The number of commands received in queue 1 */ | |
455 | #define CSDM_REG_NUM_OF_Q1_CMD 0xc224c | |
456 | /* [ST 32] The number of commands received in queue 3 */ | |
457 | #define CSDM_REG_NUM_OF_Q3_CMD 0xc2250 | |
458 | /* [ST 32] The number of commands received in queue 4 */ | |
459 | #define CSDM_REG_NUM_OF_Q4_CMD 0xc2254 | |
460 | /* [ST 32] The number of commands received in queue 5 */ | |
461 | #define CSDM_REG_NUM_OF_Q5_CMD 0xc2258 | |
462 | /* [ST 32] The number of commands received in queue 6 */ | |
463 | #define CSDM_REG_NUM_OF_Q6_CMD 0xc225c | |
464 | /* [ST 32] The number of commands received in queue 7 */ | |
465 | #define CSDM_REG_NUM_OF_Q7_CMD 0xc2260 | |
466 | /* [ST 32] The number of commands received in queue 8 */ | |
467 | #define CSDM_REG_NUM_OF_Q8_CMD 0xc2264 | |
468 | /* [ST 32] The number of commands received in queue 9 */ | |
469 | #define CSDM_REG_NUM_OF_Q9_CMD 0xc2268 | |
470 | /* [RW 13] The start address in the internal RAM for queue counters */ | |
471 | #define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010 | |
472 | /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ | |
473 | #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548 | |
474 | /* [R 1] parser fifo empty in sdm_sync block */ | |
475 | #define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550 | |
476 | /* [R 1] parser serial fifo empty in sdm_sync block */ | |
477 | #define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558 | |
478 | /* [RW 32] Tick for timer counter. Applicable only when | |
479 | ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */ | |
480 | #define CSDM_REG_TIMER_TICK 0xc2000 | |
481 | /* [RW 5] The number of time_slots in the arbitration cycle */ | |
482 | #define CSEM_REG_ARB_CYCLE_SIZE 0x200034 | |
483 | /* [RW 3] The source that is associated with arbitration element 0. Source | |
484 | decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- | |
485 | sleeping thread with priority 1; 4- sleeping thread with priority 2 */ | |
486 | #define CSEM_REG_ARB_ELEMENT0 0x200020 | |
487 | /* [RW 3] The source that is associated with arbitration element 1. Source | |
488 | decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- | |
489 | sleeping thread with priority 1; 4- sleeping thread with priority 2. | |
490 | Could not be equal to register ~csem_registers_arb_element0.arb_element0 */ | |
491 | #define CSEM_REG_ARB_ELEMENT1 0x200024 | |
492 | /* [RW 3] The source that is associated with arbitration element 2. Source | |
493 | decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- | |
494 | sleeping thread with priority 1; 4- sleeping thread with priority 2. | |
495 | Could not be equal to register ~csem_registers_arb_element0.arb_element0 | |
496 | and ~csem_registers_arb_element1.arb_element1 */ | |
497 | #define CSEM_REG_ARB_ELEMENT2 0x200028 | |
498 | /* [RW 3] The source that is associated with arbitration element 3. Source | |
499 | decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- | |
500 | sleeping thread with priority 1; 4- sleeping thread with priority 2.Could | |
501 | not be equal to register ~csem_registers_arb_element0.arb_element0 and | |
502 | ~csem_registers_arb_element1.arb_element1 and | |
503 | ~csem_registers_arb_element2.arb_element2 */ | |
504 | #define CSEM_REG_ARB_ELEMENT3 0x20002c | |
505 | /* [RW 3] The source that is associated with arbitration element 4. Source | |
506 | decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- | |
507 | sleeping thread with priority 1; 4- sleeping thread with priority 2. | |
508 | Could not be equal to register ~csem_registers_arb_element0.arb_element0 | |
509 | and ~csem_registers_arb_element1.arb_element1 and | |
510 | ~csem_registers_arb_element2.arb_element2 and | |
511 | ~csem_registers_arb_element3.arb_element3 */ | |
512 | #define CSEM_REG_ARB_ELEMENT4 0x200030 | |
513 | /* [RW 32] Interrupt mask register #0 read/write */ | |
514 | #define CSEM_REG_CSEM_INT_MASK_0 0x200110 | |
515 | #define CSEM_REG_CSEM_INT_MASK_1 0x200120 | |
c18487ee YR |
516 | /* [R 32] Interrupt register #0 read */ |
517 | #define CSEM_REG_CSEM_INT_STS_0 0x200104 | |
518 | #define CSEM_REG_CSEM_INT_STS_1 0x200114 | |
a2fbb9ea ET |
519 | /* [RW 32] Parity mask register #0 read/write */ |
520 | #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130 | |
521 | #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140 | |
f1410647 ET |
522 | /* [R 32] Parity register #0 read */ |
523 | #define CSEM_REG_CSEM_PRTY_STS_0 0x200124 | |
524 | #define CSEM_REG_CSEM_PRTY_STS_1 0x200134 | |
a2fbb9ea ET |
525 | #define CSEM_REG_ENABLE_IN 0x2000a4 |
526 | #define CSEM_REG_ENABLE_OUT 0x2000a8 | |
527 | /* [RW 32] This address space contains all registers and memories that are | |
528 | placed in SEM_FAST block. The SEM_FAST registers are described in | |
c18487ee YR |
529 | appendix B. In order to access the sem_fast registers the base address |
530 | ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ | |
a2fbb9ea ET |
531 | #define CSEM_REG_FAST_MEMORY 0x220000 |
532 | /* [RW 1] Disables input messages from FIC0 May be updated during run_time | |
533 | by the microcode */ | |
534 | #define CSEM_REG_FIC0_DISABLE 0x200224 | |
535 | /* [RW 1] Disables input messages from FIC1 May be updated during run_time | |
536 | by the microcode */ | |
537 | #define CSEM_REG_FIC1_DISABLE 0x200234 | |
538 | /* [RW 15] Interrupt table Read and write access to it is not possible in | |
539 | the middle of the work */ | |
540 | #define CSEM_REG_INT_TABLE 0x200400 | |
541 | /* [ST 24] Statistics register. The number of messages that entered through | |
542 | FIC0 */ | |
543 | #define CSEM_REG_MSG_NUM_FIC0 0x200000 | |
544 | /* [ST 24] Statistics register. The number of messages that entered through | |
545 | FIC1 */ | |
546 | #define CSEM_REG_MSG_NUM_FIC1 0x200004 | |
547 | /* [ST 24] Statistics register. The number of messages that were sent to | |
548 | FOC0 */ | |
549 | #define CSEM_REG_MSG_NUM_FOC0 0x200008 | |
550 | /* [ST 24] Statistics register. The number of messages that were sent to | |
551 | FOC1 */ | |
552 | #define CSEM_REG_MSG_NUM_FOC1 0x20000c | |
553 | /* [ST 24] Statistics register. The number of messages that were sent to | |
554 | FOC2 */ | |
555 | #define CSEM_REG_MSG_NUM_FOC2 0x200010 | |
556 | /* [ST 24] Statistics register. The number of messages that were sent to | |
557 | FOC3 */ | |
558 | #define CSEM_REG_MSG_NUM_FOC3 0x200014 | |
559 | /* [RW 1] Disables input messages from the passive buffer May be updated | |
560 | during run_time by the microcode */ | |
561 | #define CSEM_REG_PAS_DISABLE 0x20024c | |
562 | /* [WB 128] Debug only. Passive buffer memory */ | |
563 | #define CSEM_REG_PASSIVE_BUFFER 0x202000 | |
564 | /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ | |
565 | #define CSEM_REG_PRAM 0x240000 | |
566 | /* [R 16] Valid sleeping threads indication have bit per thread */ | |
567 | #define CSEM_REG_SLEEP_THREADS_VALID 0x20026c | |
568 | /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ | |
569 | #define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0 | |
570 | /* [RW 16] List of free threads . There is a bit per thread. */ | |
571 | #define CSEM_REG_THREADS_LIST 0x2002e4 | |
572 | /* [RW 3] The arbitration scheme of time_slot 0 */ | |
573 | #define CSEM_REG_TS_0_AS 0x200038 | |
574 | /* [RW 3] The arbitration scheme of time_slot 10 */ | |
575 | #define CSEM_REG_TS_10_AS 0x200060 | |
576 | /* [RW 3] The arbitration scheme of time_slot 11 */ | |
577 | #define CSEM_REG_TS_11_AS 0x200064 | |
578 | /* [RW 3] The arbitration scheme of time_slot 12 */ | |
579 | #define CSEM_REG_TS_12_AS 0x200068 | |
580 | /* [RW 3] The arbitration scheme of time_slot 13 */ | |
581 | #define CSEM_REG_TS_13_AS 0x20006c | |
582 | /* [RW 3] The arbitration scheme of time_slot 14 */ | |
583 | #define CSEM_REG_TS_14_AS 0x200070 | |
584 | /* [RW 3] The arbitration scheme of time_slot 15 */ | |
585 | #define CSEM_REG_TS_15_AS 0x200074 | |
586 | /* [RW 3] The arbitration scheme of time_slot 16 */ | |
587 | #define CSEM_REG_TS_16_AS 0x200078 | |
588 | /* [RW 3] The arbitration scheme of time_slot 17 */ | |
589 | #define CSEM_REG_TS_17_AS 0x20007c | |
590 | /* [RW 3] The arbitration scheme of time_slot 18 */ | |
591 | #define CSEM_REG_TS_18_AS 0x200080 | |
592 | /* [RW 3] The arbitration scheme of time_slot 1 */ | |
593 | #define CSEM_REG_TS_1_AS 0x20003c | |
594 | /* [RW 3] The arbitration scheme of time_slot 2 */ | |
595 | #define CSEM_REG_TS_2_AS 0x200040 | |
596 | /* [RW 3] The arbitration scheme of time_slot 3 */ | |
597 | #define CSEM_REG_TS_3_AS 0x200044 | |
598 | /* [RW 3] The arbitration scheme of time_slot 4 */ | |
599 | #define CSEM_REG_TS_4_AS 0x200048 | |
600 | /* [RW 3] The arbitration scheme of time_slot 5 */ | |
601 | #define CSEM_REG_TS_5_AS 0x20004c | |
602 | /* [RW 3] The arbitration scheme of time_slot 6 */ | |
603 | #define CSEM_REG_TS_6_AS 0x200050 | |
604 | /* [RW 3] The arbitration scheme of time_slot 7 */ | |
605 | #define CSEM_REG_TS_7_AS 0x200054 | |
606 | /* [RW 3] The arbitration scheme of time_slot 8 */ | |
607 | #define CSEM_REG_TS_8_AS 0x200058 | |
608 | /* [RW 3] The arbitration scheme of time_slot 9 */ | |
609 | #define CSEM_REG_TS_9_AS 0x20005c | |
610 | /* [RW 1] Parity mask register #0 read/write */ | |
611 | #define DBG_REG_DBG_PRTY_MASK 0xc0a8 | |
f1410647 ET |
612 | /* [R 1] Parity register #0 read */ |
613 | #define DBG_REG_DBG_PRTY_STS 0xc09c | |
a2fbb9ea ET |
614 | /* [RW 32] Commands memory. The address to command X; row Y is to calculated |
615 | as 14*X+Y. */ | |
616 | #define DMAE_REG_CMD_MEM 0x102400 | |
34f80b04 | 617 | #define DMAE_REG_CMD_MEM_SIZE 224 |
a2fbb9ea ET |
618 | /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c |
619 | initial value is all ones. */ | |
620 | #define DMAE_REG_CRC16C_INIT 0x10201c | |
621 | /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the | |
622 | CRC-16 T10 initial value is all ones. */ | |
623 | #define DMAE_REG_CRC16T10_INIT 0x102020 | |
624 | /* [RW 2] Interrupt mask register #0 read/write */ | |
625 | #define DMAE_REG_DMAE_INT_MASK 0x102054 | |
626 | /* [RW 4] Parity mask register #0 read/write */ | |
627 | #define DMAE_REG_DMAE_PRTY_MASK 0x102064 | |
f1410647 ET |
628 | /* [R 4] Parity register #0 read */ |
629 | #define DMAE_REG_DMAE_PRTY_STS 0x102058 | |
a2fbb9ea ET |
630 | /* [RW 1] Command 0 go. */ |
631 | #define DMAE_REG_GO_C0 0x102080 | |
632 | /* [RW 1] Command 1 go. */ | |
633 | #define DMAE_REG_GO_C1 0x102084 | |
634 | /* [RW 1] Command 10 go. */ | |
635 | #define DMAE_REG_GO_C10 0x102088 | |
636 | #define DMAE_REG_GO_C10_SIZE 1 | |
637 | /* [RW 1] Command 11 go. */ | |
638 | #define DMAE_REG_GO_C11 0x10208c | |
639 | #define DMAE_REG_GO_C11_SIZE 1 | |
640 | /* [RW 1] Command 12 go. */ | |
641 | #define DMAE_REG_GO_C12 0x102090 | |
642 | #define DMAE_REG_GO_C12_SIZE 1 | |
643 | /* [RW 1] Command 13 go. */ | |
644 | #define DMAE_REG_GO_C13 0x102094 | |
645 | #define DMAE_REG_GO_C13_SIZE 1 | |
646 | /* [RW 1] Command 14 go. */ | |
647 | #define DMAE_REG_GO_C14 0x102098 | |
648 | #define DMAE_REG_GO_C14_SIZE 1 | |
649 | /* [RW 1] Command 15 go. */ | |
650 | #define DMAE_REG_GO_C15 0x10209c | |
651 | #define DMAE_REG_GO_C15_SIZE 1 | |
652 | /* [RW 1] Command 10 go. */ | |
653 | #define DMAE_REG_GO_C10 0x102088 | |
654 | /* [RW 1] Command 11 go. */ | |
655 | #define DMAE_REG_GO_C11 0x10208c | |
656 | /* [RW 1] Command 12 go. */ | |
657 | #define DMAE_REG_GO_C12 0x102090 | |
658 | /* [RW 1] Command 13 go. */ | |
659 | #define DMAE_REG_GO_C13 0x102094 | |
660 | /* [RW 1] Command 14 go. */ | |
661 | #define DMAE_REG_GO_C14 0x102098 | |
662 | /* [RW 1] Command 15 go. */ | |
663 | #define DMAE_REG_GO_C15 0x10209c | |
664 | /* [RW 1] Command 2 go. */ | |
665 | #define DMAE_REG_GO_C2 0x1020a0 | |
666 | /* [RW 1] Command 3 go. */ | |
667 | #define DMAE_REG_GO_C3 0x1020a4 | |
668 | /* [RW 1] Command 4 go. */ | |
669 | #define DMAE_REG_GO_C4 0x1020a8 | |
670 | /* [RW 1] Command 5 go. */ | |
671 | #define DMAE_REG_GO_C5 0x1020ac | |
672 | /* [RW 1] Command 6 go. */ | |
673 | #define DMAE_REG_GO_C6 0x1020b0 | |
674 | /* [RW 1] Command 7 go. */ | |
675 | #define DMAE_REG_GO_C7 0x1020b4 | |
676 | /* [RW 1] Command 8 go. */ | |
677 | #define DMAE_REG_GO_C8 0x1020b8 | |
678 | /* [RW 1] Command 9 go. */ | |
679 | #define DMAE_REG_GO_C9 0x1020bc | |
680 | /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge | |
681 | input is disregarded; valid is deasserted; all other signals are treated | |
682 | as usual; if 1 - normal activity. */ | |
683 | #define DMAE_REG_GRC_IFEN 0x102008 | |
684 | /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the | |
685 | acknowledge input is disregarded; valid is deasserted; full is asserted; | |
686 | all other signals are treated as usual; if 1 - normal activity. */ | |
687 | #define DMAE_REG_PCI_IFEN 0x102004 | |
688 | /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the | |
689 | initial value to the credit counter; related to the address. Read returns | |
690 | the current value of the counter. */ | |
691 | #define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0 | |
692 | /* [RW 8] Aggregation command. */ | |
693 | #define DORQ_REG_AGG_CMD0 0x170060 | |
694 | /* [RW 8] Aggregation command. */ | |
695 | #define DORQ_REG_AGG_CMD1 0x170064 | |
696 | /* [RW 8] Aggregation command. */ | |
697 | #define DORQ_REG_AGG_CMD2 0x170068 | |
698 | /* [RW 8] Aggregation command. */ | |
699 | #define DORQ_REG_AGG_CMD3 0x17006c | |
700 | /* [RW 28] UCM Header. */ | |
701 | #define DORQ_REG_CMHEAD_RX 0x170050 | |
c18487ee YR |
702 | /* [RW 32] Doorbell address for RBC doorbells (function 0). */ |
703 | #define DORQ_REG_DB_ADDR0 0x17008c | |
a2fbb9ea ET |
704 | /* [RW 5] Interrupt mask register #0 read/write */ |
705 | #define DORQ_REG_DORQ_INT_MASK 0x170180 | |
706 | /* [R 5] Interrupt register #0 read */ | |
707 | #define DORQ_REG_DORQ_INT_STS 0x170174 | |
708 | /* [RC 5] Interrupt register #0 read clear */ | |
709 | #define DORQ_REG_DORQ_INT_STS_CLR 0x170178 | |
710 | /* [RW 2] Parity mask register #0 read/write */ | |
711 | #define DORQ_REG_DORQ_PRTY_MASK 0x170190 | |
f1410647 ET |
712 | /* [R 2] Parity register #0 read */ |
713 | #define DORQ_REG_DORQ_PRTY_STS 0x170184 | |
a2fbb9ea ET |
714 | /* [RW 8] The address to write the DPM CID to STORM. */ |
715 | #define DORQ_REG_DPM_CID_ADDR 0x170044 | |
716 | /* [RW 5] The DPM mode CID extraction offset. */ | |
717 | #define DORQ_REG_DPM_CID_OFST 0x170030 | |
718 | /* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */ | |
719 | #define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c | |
720 | /* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */ | |
721 | #define DORQ_REG_DQ_FIFO_FULL_TH 0x170078 | |
722 | /* [R 13] Current value of the DQ FIFO fill level according to following | |
723 | pointer. The range is 0 - 256 FIFO rows; where each row stands for the | |
724 | doorbell. */ | |
725 | #define DORQ_REG_DQ_FILL_LVLF 0x1700a4 | |
726 | /* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or | |
727 | equal to full threshold; reset on full clear. */ | |
728 | #define DORQ_REG_DQ_FULL_ST 0x1700c0 | |
729 | /* [RW 28] The value sent to CM header in the case of CFC load error. */ | |
730 | #define DORQ_REG_ERR_CMHEAD 0x170058 | |
731 | #define DORQ_REG_IF_EN 0x170004 | |
732 | #define DORQ_REG_MODE_ACT 0x170008 | |
733 | /* [RW 5] The normal mode CID extraction offset. */ | |
734 | #define DORQ_REG_NORM_CID_OFST 0x17002c | |
735 | /* [RW 28] TCM Header when only TCP context is loaded. */ | |
736 | #define DORQ_REG_NORM_CMHEAD_TX 0x17004c | |
737 | /* [RW 3] The number of simultaneous outstanding requests to Context Fetch | |
738 | Interface. */ | |
739 | #define DORQ_REG_OUTST_REQ 0x17003c | |
740 | #define DORQ_REG_REGN 0x170038 | |
741 | /* [R 4] Current value of response A counter credit. Initial credit is | |
742 | configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd | |
743 | register. */ | |
744 | #define DORQ_REG_RSPA_CRD_CNT 0x1700ac | |
745 | /* [R 4] Current value of response B counter credit. Initial credit is | |
746 | configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd | |
747 | register. */ | |
748 | #define DORQ_REG_RSPB_CRD_CNT 0x1700b0 | |
749 | /* [RW 4] The initial credit at the Doorbell Response Interface. The write | |
750 | writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The | |
751 | read reads this written value. */ | |
752 | #define DORQ_REG_RSP_INIT_CRD 0x170048 | |
753 | /* [RW 4] Initial activity counter value on the load request; when the | |
754 | shortcut is done. */ | |
755 | #define DORQ_REG_SHRT_ACT_CNT 0x170070 | |
756 | /* [RW 28] TCM Header when both ULP and TCP context is loaded. */ | |
757 | #define DORQ_REG_SHRT_CMHEAD 0x170054 | |
758 | #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4) | |
759 | #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3) | |
8badd27a | 760 | #define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7) |
a2fbb9ea ET |
761 | #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2) |
762 | #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1) | |
763 | #define HC_REG_AGG_INT_0 0x108050 | |
764 | #define HC_REG_AGG_INT_1 0x108054 | |
a2fbb9ea | 765 | #define HC_REG_ATTN_BIT 0x108120 |
a2fbb9ea | 766 | #define HC_REG_ATTN_IDX 0x108100 |
a2fbb9ea | 767 | #define HC_REG_ATTN_MSG0_ADDR_L 0x108018 |
a2fbb9ea | 768 | #define HC_REG_ATTN_MSG1_ADDR_L 0x108020 |
a2fbb9ea | 769 | #define HC_REG_ATTN_NUM_P0 0x108038 |
a2fbb9ea | 770 | #define HC_REG_ATTN_NUM_P1 0x10803c |
5c862848 | 771 | #define HC_REG_COMMAND_REG 0x108180 |
a2fbb9ea ET |
772 | #define HC_REG_CONFIG_0 0x108000 |
773 | #define HC_REG_CONFIG_1 0x108004 | |
c18487ee YR |
774 | #define HC_REG_FUNC_NUM_P0 0x1080ac |
775 | #define HC_REG_FUNC_NUM_P1 0x1080b0 | |
a2fbb9ea ET |
776 | /* [RW 3] Parity mask register #0 read/write */ |
777 | #define HC_REG_HC_PRTY_MASK 0x1080a0 | |
f1410647 ET |
778 | /* [R 3] Parity register #0 read */ |
779 | #define HC_REG_HC_PRTY_STS 0x108094 | |
a2fbb9ea | 780 | #define HC_REG_INT_MASK 0x108108 |
a2fbb9ea ET |
781 | #define HC_REG_LEADING_EDGE_0 0x108040 |
782 | #define HC_REG_LEADING_EDGE_1 0x108048 | |
a2fbb9ea | 783 | #define HC_REG_P0_PROD_CONS 0x108200 |
a2fbb9ea | 784 | #define HC_REG_P1_PROD_CONS 0x108400 |
a2fbb9ea ET |
785 | #define HC_REG_PBA_COMMAND 0x108140 |
786 | #define HC_REG_PCI_CONFIG_0 0x108010 | |
787 | #define HC_REG_PCI_CONFIG_1 0x108014 | |
a2fbb9ea | 788 | #define HC_REG_STATISTIC_COUNTERS 0x109000 |
a2fbb9ea ET |
789 | #define HC_REG_TRAILING_EDGE_0 0x108044 |
790 | #define HC_REG_TRAILING_EDGE_1 0x10804c | |
791 | #define HC_REG_UC_RAM_ADDR_0 0x108028 | |
792 | #define HC_REG_UC_RAM_ADDR_1 0x108030 | |
a2fbb9ea ET |
793 | #define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068 |
794 | #define HC_REG_VQID_0 0x108008 | |
795 | #define HC_REG_VQID_1 0x10800c | |
796 | #define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424 | |
797 | #define MCP_REG_MCPR_NVM_ADDR 0x8640c | |
798 | #define MCP_REG_MCPR_NVM_CFG4 0x8642c | |
799 | #define MCP_REG_MCPR_NVM_COMMAND 0x86400 | |
800 | #define MCP_REG_MCPR_NVM_READ 0x86410 | |
801 | #define MCP_REG_MCPR_NVM_SW_ARB 0x86420 | |
802 | #define MCP_REG_MCPR_NVM_WRITE 0x86408 | |
803 | #define MCP_REG_MCPR_NVM_WRITE1 0x86428 | |
804 | #define MCP_REG_MCPR_SCRATCH 0xa0000 | |
805 | /* [R 32] read first 32 bit after inversion of function 0. mapped as | |
806 | follows: [0] NIG attention for function0; [1] NIG attention for | |
807 | function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; | |
808 | [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] | |
809 | GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE | |
810 | glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; | |
811 | [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] | |
812 | MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB | |
813 | Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw | |
814 | interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity | |
815 | error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw | |
816 | interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF | |
817 | Parity error; [31] PBF Hw interrupt; */ | |
818 | #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c | |
819 | #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430 | |
820 | /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0] | |
821 | NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 | |
822 | mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; | |
823 | [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] | |
824 | PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event | |
825 | function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP | |
826 | Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for | |
827 | mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] | |
828 | BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC | |
829 | Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw | |
830 | interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI | |
831 | Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw | |
832 | interrupt; */ | |
833 | #define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434 | |
834 | /* [R 32] read second 32 bit after inversion of function 0. mapped as | |
835 | follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM | |
836 | Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw | |
837 | interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity | |
838 | error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw | |
839 | interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] | |
840 | NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; | |
841 | [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw | |
842 | interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM | |
843 | Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI | |
844 | Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM | |
845 | Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw | |
846 | interrupt; */ | |
847 | #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438 | |
848 | #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c | |
849 | /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0] | |
850 | PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error; | |
851 | [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; | |
852 | [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] | |
853 | XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] | |
854 | DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity | |
855 | error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux | |
856 | PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; | |
857 | [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; | |
858 | [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; | |
859 | [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; | |
860 | [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */ | |
861 | #define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440 | |
862 | /* [R 32] read third 32 bit after inversion of function 0. mapped as | |
863 | follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity | |
864 | error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] | |
865 | PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw | |
866 | interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity | |
867 | error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) | |
868 | Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] | |
869 | pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] | |
870 | MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] | |
871 | SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW | |
872 | timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 | |
873 | func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General | |
874 | attn1; */ | |
875 | #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444 | |
876 | #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448 | |
877 | /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0] | |
878 | CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP | |
879 | Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient | |
880 | Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity | |
881 | error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw | |
882 | interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] | |
883 | MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] | |
884 | Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW | |
885 | timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 | |
886 | func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 | |
887 | func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW | |
888 | timers attn_4 func1; [30] General attn0; [31] General attn1; */ | |
889 | #define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c | |
890 | /* [R 32] read fourth 32 bit after inversion of function 0. mapped as | |
891 | follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] | |
892 | General attn5; [4] General attn6; [5] General attn7; [6] General attn8; | |
893 | [7] General attn9; [8] General attn10; [9] General attn11; [10] General | |
894 | attn12; [11] General attn13; [12] General attn14; [13] General attn15; | |
895 | [14] General attn16; [15] General attn17; [16] General attn18; [17] | |
896 | General attn19; [18] General attn20; [19] General attn21; [20] Main power | |
897 | interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN | |
898 | Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC | |
899 | Latched timeout attention; [27] GRC Latched reserved access attention; | |
900 | [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP | |
901 | Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ | |
902 | #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450 | |
903 | #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454 | |
904 | /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0] | |
905 | General attn2; [1] General attn3; [2] General attn4; [3] General attn5; | |
906 | [4] General attn6; [5] General attn7; [6] General attn8; [7] General | |
907 | attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] | |
908 | General attn13; [12] General attn14; [13] General attn15; [14] General | |
909 | attn16; [15] General attn17; [16] General attn18; [17] General attn19; | |
910 | [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] | |
911 | RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] | |
912 | RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout | |
913 | attention; [27] GRC Latched reserved access attention; [28] MCP Latched | |
914 | rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched | |
915 | ump_tx_parity; [31] MCP Latched scpad_parity; */ | |
916 | #define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458 | |
c18487ee | 917 | /* [W 14] write to this register results with the clear of the latched |
a2fbb9ea ET |
918 | signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in |
919 | d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP | |
920 | latch; one in d5 clears GRC Latched timeout attention; one in d6 clears | |
921 | GRC Latched reserved access attention; one in d7 clears Latched | |
922 | rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears | |
c18487ee YR |
923 | Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both |
924 | ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears | |
925 | pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read | |
926 | from this register return zero */ | |
a2fbb9ea ET |
927 | #define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c |
928 | /* [RW 32] first 32b for enabling the output for function 0 output0. mapped | |
929 | as follows: [0] NIG attention for function0; [1] NIG attention for | |
930 | function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function | |
931 | 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] | |
932 | GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event | |
933 | function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP | |
934 | Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] | |
935 | SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X | |
936 | indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; | |
937 | [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] | |
938 | SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] | |
939 | TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] | |
940 | TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ | |
941 | #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c | |
942 | #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c | |
c18487ee | 943 | #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c |
a2fbb9ea | 944 | #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c |
c18487ee YR |
945 | #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc |
946 | #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc | |
947 | #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc | |
a2fbb9ea ET |
948 | /* [RW 32] first 32b for enabling the output for function 1 output0. mapped |
949 | as follows: [0] NIG attention for function0; [1] NIG attention for | |
950 | function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function | |
951 | 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] | |
952 | GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event | |
953 | function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP | |
954 | Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] | |
955 | SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X | |
956 | indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; | |
957 | [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] | |
958 | SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] | |
959 | TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] | |
960 | TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ | |
961 | #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c | |
962 | #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c | |
c18487ee | 963 | #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c |
a2fbb9ea | 964 | #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c |
c18487ee YR |
965 | #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c |
966 | #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c | |
967 | #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c | |
968 | /* [RW 32] first 32b for enabling the output for close the gate nig. mapped | |
969 | as follows: [0] NIG attention for function0; [1] NIG attention for | |
a2fbb9ea ET |
970 | function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function |
971 | 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] | |
972 | GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event | |
973 | function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP | |
974 | Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] | |
975 | SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X | |
976 | indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; | |
977 | [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] | |
978 | SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] | |
979 | TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] | |
980 | TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ | |
981 | #define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec | |
982 | #define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c | |
c18487ee YR |
983 | /* [RW 32] first 32b for enabling the output for close the gate pxp. mapped |
984 | as follows: [0] NIG attention for function0; [1] NIG attention for | |
a2fbb9ea ET |
985 | function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function |
986 | 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] | |
987 | GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event | |
988 | function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP | |
989 | Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] | |
990 | SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X | |
991 | indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; | |
992 | [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] | |
993 | SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] | |
994 | TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] | |
995 | TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ | |
996 | #define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc | |
997 | #define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c | |
998 | /* [RW 32] second 32b for enabling the output for function 0 output0. mapped | |
999 | as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM | |
1000 | Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw | |
1001 | interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity | |
1002 | error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw | |
1003 | interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] | |
1004 | NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; | |
1005 | [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw | |
1006 | interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM | |
1007 | Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI | |
1008 | Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM | |
1009 | Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw | |
1010 | interrupt; */ | |
1011 | #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070 | |
1012 | #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080 | |
1013 | /* [RW 32] second 32b for enabling the output for function 1 output0. mapped | |
1014 | as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM | |
1015 | Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw | |
1016 | interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity | |
1017 | error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw | |
1018 | interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] | |
1019 | NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; | |
1020 | [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw | |
1021 | interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM | |
1022 | Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI | |
1023 | Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM | |
1024 | Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw | |
1025 | interrupt; */ | |
1026 | #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110 | |
1027 | #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120 | |
c18487ee YR |
1028 | /* [RW 32] second 32b for enabling the output for close the gate nig. mapped |
1029 | as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM | |
1030 | Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw | |
1031 | interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity | |
1032 | error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw | |
1033 | interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] | |
1034 | NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; | |
1035 | [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw | |
1036 | interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM | |
1037 | Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI | |
1038 | Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM | |
1039 | Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw | |
1040 | interrupt; */ | |
a2fbb9ea ET |
1041 | #define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0 |
1042 | #define MISC_REG_AEU_ENABLE2_NIG_1 0xa190 | |
c18487ee YR |
1043 | /* [RW 32] second 32b for enabling the output for close the gate pxp. mapped |
1044 | as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM | |
1045 | Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw | |
1046 | interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity | |
1047 | error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw | |
1048 | interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] | |
1049 | NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; | |
1050 | [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw | |
1051 | interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM | |
1052 | Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI | |
1053 | Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM | |
1054 | Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw | |
1055 | interrupt; */ | |
a2fbb9ea ET |
1056 | #define MISC_REG_AEU_ENABLE2_PXP_0 0xa100 |
1057 | #define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0 | |
1058 | /* [RW 32] third 32b for enabling the output for function 0 output0. mapped | |
1059 | as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP | |
1060 | Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; | |
1061 | [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw | |
1062 | interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity | |
1063 | error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) | |
1064 | Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] | |
1065 | pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] | |
1066 | MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] | |
1067 | SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW | |
1068 | timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 | |
1069 | func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General | |
1070 | attn1; */ | |
1071 | #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074 | |
1072 | #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084 | |
1073 | /* [RW 32] third 32b for enabling the output for function 1 output0. mapped | |
1074 | as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP | |
1075 | Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; | |
1076 | [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw | |
1077 | interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity | |
1078 | error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) | |
1079 | Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] | |
1080 | pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] | |
1081 | MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] | |
1082 | SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW | |
1083 | timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 | |
1084 | func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General | |
1085 | attn1; */ | |
1086 | #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114 | |
1087 | #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124 | |
c18487ee YR |
1088 | /* [RW 32] third 32b for enabling the output for close the gate nig. mapped |
1089 | as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP | |
1090 | Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; | |
1091 | [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw | |
1092 | interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity | |
1093 | error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) | |
1094 | Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] | |
1095 | pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] | |
1096 | MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] | |
1097 | SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW | |
1098 | timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 | |
1099 | func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General | |
1100 | attn1; */ | |
a2fbb9ea ET |
1101 | #define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4 |
1102 | #define MISC_REG_AEU_ENABLE3_NIG_1 0xa194 | |
c18487ee YR |
1103 | /* [RW 32] third 32b for enabling the output for close the gate pxp. mapped |
1104 | as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP | |
1105 | Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; | |
1106 | [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw | |
1107 | interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity | |
1108 | error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) | |
1109 | Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] | |
1110 | pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] | |
1111 | MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] | |
1112 | SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW | |
1113 | timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 | |
1114 | func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General | |
1115 | attn1; */ | |
a2fbb9ea ET |
1116 | #define MISC_REG_AEU_ENABLE3_PXP_0 0xa104 |
1117 | #define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4 | |
1118 | /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped | |
1119 | as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] | |
1120 | General attn5; [4] General attn6; [5] General attn7; [6] General attn8; | |
1121 | [7] General attn9; [8] General attn10; [9] General attn11; [10] General | |
1122 | attn12; [11] General attn13; [12] General attn14; [13] General attn15; | |
1123 | [14] General attn16; [15] General attn17; [16] General attn18; [17] | |
1124 | General attn19; [18] General attn20; [19] General attn21; [20] Main power | |
1125 | interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN | |
1126 | Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC | |
1127 | Latched timeout attention; [27] GRC Latched reserved access attention; | |
1128 | [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP | |
1129 | Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ | |
1130 | #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078 | |
1131 | #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098 | |
c18487ee YR |
1132 | #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8 |
1133 | #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8 | |
1134 | #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8 | |
1135 | #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8 | |
a2fbb9ea ET |
1136 | /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped |
1137 | as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] | |
1138 | General attn5; [4] General attn6; [5] General attn7; [6] General attn8; | |
1139 | [7] General attn9; [8] General attn10; [9] General attn11; [10] General | |
1140 | attn12; [11] General attn13; [12] General attn14; [13] General attn15; | |
1141 | [14] General attn16; [15] General attn17; [16] General attn18; [17] | |
1142 | General attn19; [18] General attn20; [19] General attn21; [20] Main power | |
1143 | interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN | |
1144 | Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC | |
1145 | Latched timeout attention; [27] GRC Latched reserved access attention; | |
1146 | [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP | |
1147 | Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ | |
1148 | #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118 | |
1149 | #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138 | |
c18487ee YR |
1150 | #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158 |
1151 | #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168 | |
1152 | #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178 | |
1153 | #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188 | |
1154 | /* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped | |
1155 | as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] | |
1156 | General attn5; [4] General attn6; [5] General attn7; [6] General attn8; | |
1157 | [7] General attn9; [8] General attn10; [9] General attn11; [10] General | |
1158 | attn12; [11] General attn13; [12] General attn14; [13] General attn15; | |
1159 | [14] General attn16; [15] General attn17; [16] General attn18; [17] | |
1160 | General attn19; [18] General attn20; [19] General attn21; [20] Main power | |
1161 | interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN | |
1162 | Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC | |
1163 | Latched timeout attention; [27] GRC Latched reserved access attention; | |
1164 | [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP | |
1165 | Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ | |
a2fbb9ea ET |
1166 | #define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8 |
1167 | #define MISC_REG_AEU_ENABLE4_NIG_1 0xa198 | |
c18487ee YR |
1168 | /* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped |
1169 | as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] | |
1170 | General attn5; [4] General attn6; [5] General attn7; [6] General attn8; | |
1171 | [7] General attn9; [8] General attn10; [9] General attn11; [10] General | |
1172 | attn12; [11] General attn13; [12] General attn14; [13] General attn15; | |
1173 | [14] General attn16; [15] General attn17; [16] General attn18; [17] | |
1174 | General attn19; [18] General attn20; [19] General attn21; [20] Main power | |
1175 | interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN | |
1176 | Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC | |
1177 | Latched timeout attention; [27] GRC Latched reserved access attention; | |
1178 | [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP | |
1179 | Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ | |
a2fbb9ea ET |
1180 | #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108 |
1181 | #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8 | |
1182 | /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu | |
1183 | 128 bit vector */ | |
1184 | #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000 | |
1185 | #define MISC_REG_AEU_GENERAL_ATTN_1 0xa004 | |
1186 | #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028 | |
1187 | #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c | |
1188 | #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030 | |
1189 | #define MISC_REG_AEU_GENERAL_ATTN_13 0xa034 | |
1190 | #define MISC_REG_AEU_GENERAL_ATTN_14 0xa038 | |
1191 | #define MISC_REG_AEU_GENERAL_ATTN_15 0xa03c | |
1192 | #define MISC_REG_AEU_GENERAL_ATTN_16 0xa040 | |
1193 | #define MISC_REG_AEU_GENERAL_ATTN_17 0xa044 | |
1194 | #define MISC_REG_AEU_GENERAL_ATTN_18 0xa048 | |
1195 | #define MISC_REG_AEU_GENERAL_ATTN_19 0xa04c | |
f1410647 | 1196 | #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028 |
a2fbb9ea | 1197 | #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c |
c18487ee | 1198 | #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030 |
a2fbb9ea ET |
1199 | #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008 |
1200 | #define MISC_REG_AEU_GENERAL_ATTN_20 0xa050 | |
1201 | #define MISC_REG_AEU_GENERAL_ATTN_21 0xa054 | |
1202 | #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c | |
1203 | #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010 | |
1204 | #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014 | |
1205 | #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018 | |
f1410647 ET |
1206 | #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c |
1207 | #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020 | |
1208 | #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024 | |
c18487ee | 1209 | #define MISC_REG_AEU_GENERAL_MASK 0xa61c |
a2fbb9ea ET |
1210 | /* [RW 32] first 32b for inverting the input for function 0; for each bit: |
1211 | 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for | |
1212 | function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; | |
1213 | [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; | |
1214 | [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event | |
1215 | function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP | |
1216 | Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] | |
1217 | SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication | |
1218 | for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS | |
1219 | Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw | |
1220 | interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM | |
1221 | Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI | |
1222 | Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ | |
1223 | #define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c | |
1224 | #define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c | |
1225 | /* [RW 32] second 32b for inverting the input for function 0; for each bit: | |
1226 | 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity | |
1227 | error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw | |
1228 | interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM | |
1229 | Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw | |
1230 | interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] | |
1231 | DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity | |
1232 | error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux | |
1233 | PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; | |
1234 | [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; | |
1235 | [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; | |
1236 | [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; | |
1237 | [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */ | |
1238 | #define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230 | |
1239 | #define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240 | |
1240 | /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0; | |
c18487ee | 1241 | [9:8] = raserved. Zero = mask; one = unmask */ |
a2fbb9ea ET |
1242 | #define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060 |
1243 | #define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064 | |
c18487ee YR |
1244 | /* [RW 1] If set a system kill occurred */ |
1245 | #define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610 | |
1246 | /* [RW 32] Represent the status of the input vector to the AEU when a system | |
1247 | kill occurred. The register is reset in por reset. Mapped as follows: [0] | |
1248 | NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 | |
1249 | mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; | |
1250 | [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] | |
1251 | PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event | |
1252 | function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP | |
1253 | Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for | |
1254 | mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] | |
1255 | BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC | |
1256 | Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw | |
1257 | interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI | |
1258 | Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw | |
1259 | interrupt; */ | |
1260 | #define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600 | |
1261 | #define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604 | |
1262 | #define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608 | |
1263 | #define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c | |
a2fbb9ea ET |
1264 | /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1 |
1265 | Port. */ | |
1266 | #define MISC_REG_BOND_ID 0xa400 | |
1267 | /* [R 8] These bits indicate the metal revision of the chip. This value | |
1268 | starts at 0x00 for each all-layer tape-out and increments by one for each | |
1269 | tape-out. */ | |
1270 | #define MISC_REG_CHIP_METAL 0xa404 | |
1271 | /* [R 16] These bits indicate the part number for the chip. */ | |
1272 | #define MISC_REG_CHIP_NUM 0xa408 | |
1273 | /* [R 4] These bits indicate the base revision of the chip. This value | |
1274 | starts at 0x0 for the A0 tape-out and increments by one for each | |
1275 | all-layer tape-out. */ | |
1276 | #define MISC_REG_CHIP_REV 0xa40c | |
c18487ee YR |
1277 | /* [RW 32] The following driver registers(1...16) represent 16 drivers and |
1278 | 32 clients. Each client can be controlled by one driver only. One in each | |
1279 | bit represent that this driver control the appropriate client (Ex: bit 5 | |
1280 | is set means this driver control client number 5). addr1 = set; addr0 = | |
1281 | clear; read from both addresses will give the same result = status. write | |
1282 | to address 1 will set a request to control all the clients that their | |
1283 | appropriate bit (in the write command) is set. if the client is free (the | |
1284 | appropriate bit in all the other drivers is clear) one will be written to | |
1285 | that driver register; if the client isn't free the bit will remain zero. | |
1286 | if the appropriate bit is set (the driver request to gain control on a | |
1287 | client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW | |
1288 | interrupt will be asserted). write to address 0 will set a request to | |
1289 | free all the clients that their appropriate bit (in the write command) is | |
1290 | set. if the appropriate bit is clear (the driver request to free a client | |
1291 | it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will | |
1292 | be asserted). */ | |
1293 | #define MISC_REG_DRIVER_CONTROL_10 0xa3e0 | |
1294 | #define MISC_REG_DRIVER_CONTROL_10_SIZE 2 | |
1295 | /* [RW 32] The following driver registers(1...16) represent 16 drivers and | |
1296 | 32 clients. Each client can be controlled by one driver only. One in each | |
1297 | bit represent that this driver control the appropriate client (Ex: bit 5 | |
1298 | is set means this driver control client number 5). addr1 = set; addr0 = | |
1299 | clear; read from both addresses will give the same result = status. write | |
1300 | to address 1 will set a request to control all the clients that their | |
1301 | appropriate bit (in the write command) is set. if the client is free (the | |
1302 | appropriate bit in all the other drivers is clear) one will be written to | |
1303 | that driver register; if the client isn't free the bit will remain zero. | |
1304 | if the appropriate bit is set (the driver request to gain control on a | |
1305 | client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW | |
1306 | interrupt will be asserted). write to address 0 will set a request to | |
1307 | free all the clients that their appropriate bit (in the write command) is | |
1308 | set. if the appropriate bit is clear (the driver request to free a client | |
1309 | it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will | |
1310 | be asserted). */ | |
1311 | #define MISC_REG_DRIVER_CONTROL_11 0xa3e8 | |
1312 | #define MISC_REG_DRIVER_CONTROL_11_SIZE 2 | |
1313 | /* [RW 32] The following driver registers(1...16) represent 16 drivers and | |
1314 | 32 clients. Each client can be controlled by one driver only. One in each | |
1315 | bit represent that this driver control the appropriate client (Ex: bit 5 | |
1316 | is set means this driver control client number 5). addr1 = set; addr0 = | |
1317 | clear; read from both addresses will give the same result = status. write | |
1318 | to address 1 will set a request to control all the clients that their | |
1319 | appropriate bit (in the write command) is set. if the client is free (the | |
1320 | appropriate bit in all the other drivers is clear) one will be written to | |
1321 | that driver register; if the client isn't free the bit will remain zero. | |
1322 | if the appropriate bit is set (the driver request to gain control on a | |
1323 | client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW | |
1324 | interrupt will be asserted). write to address 0 will set a request to | |
1325 | free all the clients that their appropriate bit (in the write command) is | |
1326 | set. if the appropriate bit is clear (the driver request to free a client | |
1327 | it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will | |
1328 | be asserted). */ | |
1329 | #define MISC_REG_DRIVER_CONTROL_12 0xa3f0 | |
1330 | #define MISC_REG_DRIVER_CONTROL_12_SIZE 2 | |
1331 | /* [RW 32] The following driver registers(1...16) represent 16 drivers and | |
1332 | 32 clients. Each client can be controlled by one driver only. One in each | |
1333 | bit represent that this driver control the appropriate client (Ex: bit 5 | |
1334 | is set means this driver control client number 5). addr1 = set; addr0 = | |
1335 | clear; read from both addresses will give the same result = status. write | |
1336 | to address 1 will set a request to control all the clients that their | |
1337 | appropriate bit (in the write command) is set. if the client is free (the | |
1338 | appropriate bit in all the other drivers is clear) one will be written to | |
1339 | that driver register; if the client isn't free the bit will remain zero. | |
1340 | if the appropriate bit is set (the driver request to gain control on a | |
1341 | client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW | |
1342 | interrupt will be asserted). write to address 0 will set a request to | |
1343 | free all the clients that their appropriate bit (in the write command) is | |
1344 | set. if the appropriate bit is clear (the driver request to free a client | |
1345 | it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will | |
1346 | be asserted). */ | |
1347 | #define MISC_REG_DRIVER_CONTROL_13 0xa3f8 | |
1348 | #define MISC_REG_DRIVER_CONTROL_13_SIZE 2 | |
1349 | /* [RW 32] The following driver registers(1...16) represent 16 drivers and | |
1350 | 32 clients. Each client can be controlled by one driver only. One in each | |
f1410647 ET |
1351 | bit represent that this driver control the appropriate client (Ex: bit 5 |
1352 | is set means this driver control client number 5). addr1 = set; addr0 = | |
1353 | clear; read from both addresses will give the same result = status. write | |
1354 | to address 1 will set a request to control all the clients that their | |
1355 | appropriate bit (in the write command) is set. if the client is free (the | |
1356 | appropriate bit in all the other drivers is clear) one will be written to | |
1357 | that driver register; if the client isn't free the bit will remain zero. | |
1358 | if the appropriate bit is set (the driver request to gain control on a | |
1359 | client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW | |
1360 | interrupt will be asserted). write to address 0 will set a request to | |
1361 | free all the clients that their appropriate bit (in the write command) is | |
1362 | set. if the appropriate bit is clear (the driver request to free a client | |
1363 | it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will | |
1364 | be asserted). */ | |
1365 | #define MISC_REG_DRIVER_CONTROL_1 0xa510 | |
c18487ee YR |
1366 | #define MISC_REG_DRIVER_CONTROL_14 0xa5e0 |
1367 | #define MISC_REG_DRIVER_CONTROL_14_SIZE 2 | |
1368 | /* [RW 32] The following driver registers(1...16) represent 16 drivers and | |
1369 | 32 clients. Each client can be controlled by one driver only. One in each | |
1370 | bit represent that this driver control the appropriate client (Ex: bit 5 | |
1371 | is set means this driver control client number 5). addr1 = set; addr0 = | |
1372 | clear; read from both addresses will give the same result = status. write | |
1373 | to address 1 will set a request to control all the clients that their | |
1374 | appropriate bit (in the write command) is set. if the client is free (the | |
1375 | appropriate bit in all the other drivers is clear) one will be written to | |
1376 | that driver register; if the client isn't free the bit will remain zero. | |
1377 | if the appropriate bit is set (the driver request to gain control on a | |
1378 | client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW | |
1379 | interrupt will be asserted). write to address 0 will set a request to | |
1380 | free all the clients that their appropriate bit (in the write command) is | |
1381 | set. if the appropriate bit is clear (the driver request to free a client | |
1382 | it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will | |
1383 | be asserted). */ | |
1384 | #define MISC_REG_DRIVER_CONTROL_15 0xa5e8 | |
1385 | #define MISC_REG_DRIVER_CONTROL_15_SIZE 2 | |
1386 | /* [RW 32] The following driver registers(1...16) represent 16 drivers and | |
1387 | 32 clients. Each client can be controlled by one driver only. One in each | |
1388 | bit represent that this driver control the appropriate client (Ex: bit 5 | |
1389 | is set means this driver control client number 5). addr1 = set; addr0 = | |
1390 | clear; read from both addresses will give the same result = status. write | |
1391 | to address 1 will set a request to control all the clients that their | |
1392 | appropriate bit (in the write command) is set. if the client is free (the | |
1393 | appropriate bit in all the other drivers is clear) one will be written to | |
1394 | that driver register; if the client isn't free the bit will remain zero. | |
1395 | if the appropriate bit is set (the driver request to gain control on a | |
1396 | client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW | |
1397 | interrupt will be asserted). write to address 0 will set a request to | |
1398 | free all the clients that their appropriate bit (in the write command) is | |
1399 | set. if the appropriate bit is clear (the driver request to free a client | |
1400 | it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will | |
1401 | be asserted). */ | |
1402 | #define MISC_REG_DRIVER_CONTROL_16 0xa5f0 | |
1403 | #define MISC_REG_DRIVER_CONTROL_16_SIZE 2 | |
4a37fb66 YG |
1404 | /* [RW 32] The following driver registers(1...16) represent 16 drivers and |
1405 | 32 clients. Each client can be controlled by one driver only. One in each | |
1406 | bit represent that this driver control the appropriate client (Ex: bit 5 | |
1407 | is set means this driver control client number 5). addr1 = set; addr0 = | |
1408 | clear; read from both addresses will give the same result = status. write | |
1409 | to address 1 will set a request to control all the clients that their | |
1410 | appropriate bit (in the write command) is set. if the client is free (the | |
1411 | appropriate bit in all the other drivers is clear) one will be written to | |
1412 | that driver register; if the client isn't free the bit will remain zero. | |
1413 | if the appropriate bit is set (the driver request to gain control on a | |
1414 | client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW | |
1415 | interrupt will be asserted). write to address 0 will set a request to | |
1416 | free all the clients that their appropriate bit (in the write command) is | |
1417 | set. if the appropriate bit is clear (the driver request to free a client | |
1418 | it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will | |
1419 | be asserted). */ | |
1420 | #define MISC_REG_DRIVER_CONTROL_7 0xa3c8 | |
c18487ee YR |
1421 | /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0 |
1422 | only. */ | |
1423 | #define MISC_REG_E1HMF_MODE 0xa5f8 | |
f1410647 ET |
1424 | /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of |
1425 | these bits is written as a '1'; the corresponding SPIO bit will turn off | |
1426 | it's drivers and become an input. This is the reset state of all GPIO | |
1427 | pins. The read value of these bits will be a '1' if that last command | |
1428 | (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff). | |
1429 | [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written | |
1430 | as a '1'; the corresponding GPIO bit will drive low. The read value of | |
1431 | these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for | |
1432 | this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0; | |
1433 | SET When any of these bits is written as a '1'; the corresponding GPIO | |
1434 | bit will drive high (if it has that capability). The read value of these | |
1435 | bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this | |
1436 | bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0; | |
1437 | RO; These bits indicate the read value of each of the eight GPIO pins. | |
1438 | This is the result value of the pin; not the drive value. Writing these | |
1439 | bits will have not effect. */ | |
1440 | #define MISC_REG_GPIO 0xa490 | |
4acac6a5 EG |
1441 | /* [RW 8] These bits enable the GPIO_INTs to signals event to the |
1442 | IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2] | |
1443 | p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2; | |
1444 | [7] p1_gpio_3; */ | |
1445 | #define MISC_REG_GPIO_EVENT_EN 0xa2bc | |
1446 | /* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a | |
1447 | '1' to these bit clears the corresponding bit in the #OLD_VALUE register. | |
1448 | This will acknowledge an interrupt on the falling edge of corresponding | |
1449 | GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0; | |
1450 | Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE | |
1451 | register. This will acknowledge an interrupt on the rising edge of | |
1452 | corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1; | |
1453 | OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input | |
1454 | value. When the ~INT_STATE bit is set; this bit indicates the OLD value | |
1455 | of the pin such that if ~INT_STATE is set and this bit is '0'; then the | |
1456 | interrupt is due to a low to high edge. If ~INT_STATE is set and this bit | |
1457 | is '1'; then the interrupt is due to a high to low edge (reset value 0). | |
1458 | [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the | |
1459 | current GPIO interrupt state for each GPIO pin. This bit is cleared when | |
1460 | the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is | |
1461 | set when the GPIO input does not match the current value in #OLD_VALUE | |
1462 | (reset value 0). */ | |
1463 | #define MISC_REG_GPIO_INT 0xa494 | |
c18487ee YR |
1464 | /* [R 28] this field hold the last information that caused reserved |
1465 | attention. bits [19:0] - address; [22:20] function; [23] reserved; | |
33471629 | 1466 | [27:24] the master that caused the attention - according to the following |
c18487ee YR |
1467 | encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = |
1468 | dbu; 8 = dmae */ | |
1469 | #define MISC_REG_GRC_RSV_ATTN 0xa3c0 | |
1470 | /* [R 28] this field hold the last information that caused timeout | |
1471 | attention. bits [19:0] - address; [22:20] function; [23] reserved; | |
33471629 | 1472 | [27:24] the master that caused the attention - according to the following |
c18487ee YR |
1473 | encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = |
1474 | dbu; 8 = dmae */ | |
1475 | #define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4 | |
a2fbb9ea ET |
1476 | /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any |
1477 | access that does not finish within | |
1478 | ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is | |
1479 | cleared; this timeout is disabled. If this timeout occurs; the GRC shall | |
1480 | assert it attention output. */ | |
1481 | #define MISC_REG_GRC_TIMEOUT_EN 0xa280 | |
1482 | /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of | |
1483 | the bits is: [2:0] OAC reset value 001) CML output buffer bias control; | |
1484 | 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl | |
1485 | (reset value 001) Charge pump current control; 111 for 720u; 011 for | |
1486 | 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00) | |
1487 | Global bias control; When bit 7 is high bias current will be 10 0gh; When | |
1488 | bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8] | |
1489 | Pll_observe (reset value 010) Bits to control observability. bit 10 is | |
1490 | for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl | |
1491 | (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V | |
1492 | and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning | |
1493 | sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted | |
1494 | internally). [14] reserved (reset value 0) Reset for VCO sequencer is | |
1495 | connected to RESET input directly. [15] capRetry_en (reset value 0) | |
1496 | enable retry on cap search failure (inverted). [16] freqMonitor_e (reset | |
1497 | value 0) bit to continuously monitor vco freq (inverted). [17] | |
1498 | freqDetRestart_en (reset value 0) bit to enable restart when not freq | |
1499 | locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable | |
1500 | retry on freq det failure(inverted). [19] pllForceFdone_en (reset value | |
1501 | 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20] | |
1502 | pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass | |
1503 | (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value | |
1504 | 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0) | |
1505 | bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to | |
1506 | enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force | |
1507 | capPass. [26] capRestart (reset value 0) bit to force cap sequencer to | |
1508 | restart. [27] capSelectM_en (reset value 0) bit to enable cap select | |
1509 | register bits. */ | |
1510 | #define MISC_REG_LCPLL_CTRL_1 0xa2a4 | |
1511 | #define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8 | |
1512 | /* [RW 4] Interrupt mask register #0 read/write */ | |
1513 | #define MISC_REG_MISC_INT_MASK 0xa388 | |
1514 | /* [RW 1] Parity mask register #0 read/write */ | |
1515 | #define MISC_REG_MISC_PRTY_MASK 0xa398 | |
f1410647 ET |
1516 | /* [R 1] Parity register #0 read */ |
1517 | #define MISC_REG_MISC_PRTY_STS 0xa38c | |
c18487ee YR |
1518 | #define MISC_REG_NIG_WOL_P0 0xa270 |
1519 | #define MISC_REG_NIG_WOL_P1 0xa274 | |
1520 | /* [R 1] If set indicate that the pcie_rst_b was asserted without perst | |
1521 | assertion */ | |
1522 | #define MISC_REG_PCIE_HOT_RESET 0xa618 | |
a2fbb9ea ET |
1523 | /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911. |
1524 | inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1 | |
1525 | divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1 | |
1526 | divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2 | |
1527 | divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2 | |
1528 | divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9] | |
1529 | freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1] | |
1530 | (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value | |
1531 | 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16] | |
1532 | Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset | |
1533 | value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value | |
1534 | 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0); | |
1535 | [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25] | |
1536 | Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27] | |
1537 | testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29] | |
1538 | testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31] | |
1539 | testa_en (reset value 0); */ | |
1540 | #define MISC_REG_PLL_STORM_CTRL_1 0xa294 | |
1541 | #define MISC_REG_PLL_STORM_CTRL_2 0xa298 | |
1542 | #define MISC_REG_PLL_STORM_CTRL_3 0xa29c | |
1543 | #define MISC_REG_PLL_STORM_CTRL_4 0xa2a0 | |
c18487ee | 1544 | /* [RW 32] reset reg#2; rite/read one = the specific block is out of reset; |
a2fbb9ea ET |
1545 | write/read zero = the specific block is in reset; addr 0-wr- the write |
1546 | value will be written to the register; addr 1-set - one will be written | |
1547 | to all the bits that have the value of one in the data written (bits that | |
1548 | have the value of zero will not be change) ; addr 2-clear - zero will be | |
1549 | written to all the bits that have the value of one in the data written | |
1550 | (bits that have the value of zero will not be change); addr 3-ignore; | |
1551 | read ignore from all addr except addr 00; inside order of the bits is: | |
c18487ee YR |
1552 | [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc; |
1553 | [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7] | |
1554 | rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn; | |
1555 | [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13] | |
1556 | Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16] | |
1557 | rst_pxp_rq_rd_wr; 31:17] reserved */ | |
a2fbb9ea ET |
1558 | #define MISC_REG_RESET_REG_2 0xa590 |
1559 | /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is | |
1560 | shared with the driver resides */ | |
1561 | #define MISC_REG_SHARED_MEM_ADDR 0xa2b4 | |
f1410647 ET |
1562 | /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1'; |
1563 | the corresponding SPIO bit will turn off it's drivers and become an | |
1564 | input. This is the reset state of all SPIO pins. The read value of these | |
1565 | bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this | |
1566 | bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits | |
1567 | is written as a '1'; the corresponding SPIO bit will drive low. The read | |
1568 | value of these bits will be a '1' if that last command (#SET; #CLR; or | |
1569 | #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of | |
1570 | these bits is written as a '1'; the corresponding SPIO bit will drive | |
1571 | high (if it has that capability). The read value of these bits will be a | |
1572 | '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET. | |
1573 | (reset value 0). [7-0] VALUE RO; These bits indicate the read value of | |
1574 | each of the eight SPIO pins. This is the result value of the pin; not the | |
1575 | drive value. Writing these bits will have not effect. Each 8 bits field | |
1576 | is divided as follows: [0] VAUX Enable; when pulsed low; enables supply | |
1577 | from VAUX. (This is an output pin only; the FLOAT field is not applicable | |
1578 | for this pin); [1] VAUX Disable; when pulsed low; disables supply form | |
1579 | VAUX. (This is an output pin only; FLOAT field is not applicable for this | |
1580 | pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to | |
1581 | select VAUX supply. (This is an output pin only; it is not controlled by | |
1582 | the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT | |
1583 | field is not applicable for this pin; only the VALUE fields is relevant - | |
c18487ee | 1584 | it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6] |
f1410647 ET |
1585 | Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP |
1586 | device ID select; read by UMP firmware. */ | |
1587 | #define MISC_REG_SPIO 0xa4fc | |
1588 | /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC. | |
1589 | according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5; | |
1590 | [7:0] reserved */ | |
1591 | #define MISC_REG_SPIO_EVENT_EN 0xa2b8 | |
1592 | /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the | |
1593 | corresponding bit in the #OLD_VALUE register. This will acknowledge an | |
1594 | interrupt on the falling edge of corresponding SPIO input (reset value | |
1595 | 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit | |
1596 | in the #OLD_VALUE register. This will acknowledge an interrupt on the | |
1597 | rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE | |
1598 | RO; These bits indicate the old value of the SPIO input value. When the | |
1599 | ~INT_STATE bit is set; this bit indicates the OLD value of the pin such | |
1600 | that if ~INT_STATE is set and this bit is '0'; then the interrupt is due | |
1601 | to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the | |
1602 | interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE | |
1603 | RO; These bits indicate the current SPIO interrupt state for each SPIO | |
1604 | pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR | |
1605 | command bit is written. This bit is set when the SPIO input does not | |
1606 | match the current value in #OLD_VALUE (reset value 0). */ | |
1607 | #define MISC_REG_SPIO_INT 0xa500 | |
8d9c5f34 EG |
1608 | /* [RW 32] reload value for counter 4 if reload; the value will be reload if |
1609 | the counter reached zero and the reload bit | |
1610 | (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */ | |
1611 | #define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc | |
1612 | /* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses | |
1613 | in this register. addres 0 - timer 1; address - timer 2�address 7 - | |
1614 | timer 8 */ | |
1615 | #define MISC_REG_SW_TIMER_VAL 0xa5c0 | |
f1410647 ET |
1616 | /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are |
1617 | loaded; 0-prepare; -unprepare */ | |
1618 | #define MISC_REG_UNPREPARED 0xa424 | |
a2fbb9ea ET |
1619 | #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0) |
1620 | #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9) | |
1621 | #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15) | |
1622 | #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18) | |
1623 | /* [RW 1] Input enable for RX_BMAC0 IF */ | |
1624 | #define NIG_REG_BMAC0_IN_EN 0x100ac | |
1625 | /* [RW 1] output enable for TX_BMAC0 IF */ | |
1626 | #define NIG_REG_BMAC0_OUT_EN 0x100e0 | |
1627 | /* [RW 1] output enable for TX BMAC pause port 0 IF */ | |
1628 | #define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110 | |
1629 | /* [RW 1] output enable for RX_BMAC0_REGS IF */ | |
1630 | #define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8 | |
1631 | /* [RW 1] output enable for RX BRB1 port0 IF */ | |
1632 | #define NIG_REG_BRB0_OUT_EN 0x100f8 | |
1633 | /* [RW 1] Input enable for TX BRB1 pause port 0 IF */ | |
1634 | #define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4 | |
1635 | /* [RW 1] output enable for RX BRB1 port1 IF */ | |
1636 | #define NIG_REG_BRB1_OUT_EN 0x100fc | |
1637 | /* [RW 1] Input enable for TX BRB1 pause port 1 IF */ | |
1638 | #define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8 | |
1639 | /* [RW 1] output enable for RX BRB1 LP IF */ | |
1640 | #define NIG_REG_BRB_LB_OUT_EN 0x10100 | |
c18487ee YR |
1641 | /* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64] |
1642 | error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush; | |
1643 | 72:73]-vnic_num; 81:74]-sideband_info */ | |
a2fbb9ea ET |
1644 | #define NIG_REG_DEBUG_PACKET_LB 0x10800 |
1645 | /* [RW 1] Input enable for TX Debug packet */ | |
1646 | #define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc | |
1647 | /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all | |
1648 | packets from PBFare not forwarded to the MAC and just deleted from FIFO. | |
1649 | First packet may be deleted from the middle. And last packet will be | |
1650 | always deleted till the end. */ | |
1651 | #define NIG_REG_EGRESS_DRAIN0_MODE 0x10060 | |
1652 | /* [RW 1] Output enable to EMAC0 */ | |
1653 | #define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120 | |
1654 | /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs | |
1655 | to emac for port0; other way to bmac for port0 */ | |
1656 | #define NIG_REG_EGRESS_EMAC0_PORT 0x10058 | |
c18487ee YR |
1657 | /* [RW 32] TX_MNG_FIFO in NIG_TX_PORT0; data[31:0] written in FIFO order. */ |
1658 | #define NIG_REG_EGRESS_MNG0_FIFO 0x1045c | |
a2fbb9ea ET |
1659 | /* [RW 1] Input enable for TX PBF user packet port0 IF */ |
1660 | #define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc | |
1661 | /* [RW 1] Input enable for TX PBF user packet port1 IF */ | |
1662 | #define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0 | |
1663 | /* [RW 1] Input enable for RX_EMAC0 IF */ | |
1664 | #define NIG_REG_EMAC0_IN_EN 0x100a4 | |
1665 | /* [RW 1] output enable for TX EMAC pause port 0 IF */ | |
1666 | #define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118 | |
1667 | /* [R 1] status from emac0. This bit is set when MDINT from either the | |
1668 | EXT_MDINT pin or from the Copper PHY is driven low. This condition must | |
1669 | be cleared in the attached PHY device that is driving the MINT pin. */ | |
1670 | #define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494 | |
1671 | /* [WB 48] This address space contains BMAC0 registers. The BMAC registers | |
1672 | are described in appendix A. In order to access the BMAC0 registers; the | |
1673 | base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be | |
1674 | added to each BMAC register offset */ | |
1675 | #define NIG_REG_INGRESS_BMAC0_MEM 0x10c00 | |
1676 | /* [WB 48] This address space contains BMAC1 registers. The BMAC registers | |
1677 | are described in appendix A. In order to access the BMAC0 registers; the | |
1678 | base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be | |
1679 | added to each BMAC register offset */ | |
1680 | #define NIG_REG_INGRESS_BMAC1_MEM 0x11000 | |
1681 | /* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */ | |
1682 | #define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0 | |
1683 | /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data | |
1684 | packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */ | |
1685 | #define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4 | |
1686 | /* [RW 1] led 10g for port 0 */ | |
1687 | #define NIG_REG_LED_10G_P0 0x10320 | |
c18487ee YR |
1688 | /* [RW 1] led 10g for port 1 */ |
1689 | #define NIG_REG_LED_10G_P1 0x10324 | |
a2fbb9ea ET |
1690 | /* [RW 1] Port0: This bit is set to enable the use of the |
1691 | ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field | |
1692 | defined below. If this bit is cleared; then the blink rate will be about | |
1693 | 8Hz. */ | |
1694 | #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318 | |
1695 | /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for | |
1696 | Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field | |
1697 | is reset to 0x080; giving a default blink period of approximately 8Hz. */ | |
1698 | #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310 | |
1699 | /* [RW 1] Port0: If set along with the | |
34f80b04 | 1700 | ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0 |
a2fbb9ea ET |
1701 | bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED |
1702 | bit; the Traffic LED will blink with the blink rate specified in | |
1703 | ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and | |
1704 | ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0 | |
1705 | fields. */ | |
1706 | #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308 | |
1707 | /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The | |
1708 | Traffic LED will then be controlled via bit ~nig_registers_ | |
1709 | led_control_traffic_p0.led_control_traffic_p0 and bit | |
1710 | ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */ | |
1711 | #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8 | |
1712 | /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit; | |
1713 | turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also | |
1714 | set; the LED will blink with blink rate specified in | |
1715 | ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and | |
1716 | ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0 | |
1717 | fields. */ | |
1718 | #define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300 | |
1719 | /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3; | |
1720 | 9-11PHY7; 12 MAC4; 13-15 PHY10; */ | |
1721 | #define NIG_REG_LED_MODE_P0 0x102f0 | |
1c06328c EG |
1722 | /* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1- |
1723 | tsdm enable; b2- usdm enable */ | |
1724 | #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070 | |
1725 | /* [RW 1] SAFC enable for port0. This register may get 1 only when | |
1726 | ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same | |
1727 | port */ | |
1728 | #define NIG_REG_LLFC_ENABLE_0 0x16208 | |
1729 | /* [RW 16] classes are high-priority for port0 */ | |
1730 | #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058 | |
1731 | /* [RW 16] classes are low-priority for port0 */ | |
1732 | #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060 | |
1733 | /* [RW 1] Output enable of message to LLFC BMAC IF for port0 */ | |
1734 | #define NIG_REG_LLFC_OUT_EN_0 0x160c8 | |
c18487ee YR |
1735 | #define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c |
1736 | #define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154 | |
a2fbb9ea | 1737 | #define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244 |
c18487ee | 1738 | #define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048 |
a2fbb9ea ET |
1739 | /* [RW 1] send to BRB1 if no match on any of RMP rules. */ |
1740 | #define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c | |
c18487ee YR |
1741 | /* [RW 2] Determine the classification participants. 0: no classification.1: |
1742 | classification upon VLAN id. 2: classification upon MAC address. 3: | |
1743 | classification upon both VLAN id & MAC addr. */ | |
1744 | #define NIG_REG_LLH0_CLS_TYPE 0x16080 | |
a2fbb9ea ET |
1745 | /* [RW 32] cm header for llh0 */ |
1746 | #define NIG_REG_LLH0_CM_HEADER 0x1007c | |
c18487ee YR |
1747 | #define NIG_REG_LLH0_DEST_IP_0_1 0x101dc |
1748 | #define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0 | |
1749 | /* [RW 16] destination TCP address 1. The LLH will look for this address in | |
1750 | all incoming packets. */ | |
1751 | #define NIG_REG_LLH0_DEST_TCP_0 0x10220 | |
1752 | /* [RW 16] destination UDP address 1 The LLH will look for this address in | |
1753 | all incoming packets. */ | |
1754 | #define NIG_REG_LLH0_DEST_UDP_0 0x10214 | |
a2fbb9ea ET |
1755 | #define NIG_REG_LLH0_ERROR_MASK 0x1008c |
1756 | /* [RW 8] event id for llh0 */ | |
1757 | #define NIG_REG_LLH0_EVENT_ID 0x10084 | |
c18487ee YR |
1758 | #define NIG_REG_LLH0_FUNC_EN 0x160fc |
1759 | #define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100 | |
1760 | /* [RW 1] Determine the IP version to look for in | |
1761 | ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */ | |
1762 | #define NIG_REG_LLH0_IPV4_IPV6_0 0x10208 | |
1763 | /* [RW 1] t bit for llh0 */ | |
1764 | #define NIG_REG_LLH0_T_BIT 0x10074 | |
1765 | /* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */ | |
1766 | #define NIG_REG_LLH0_VLAN_ID_0 0x1022c | |
a2fbb9ea ET |
1767 | /* [RW 8] init credit counter for port0 in LLH */ |
1768 | #define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554 | |
1769 | #define NIG_REG_LLH0_XCM_MASK 0x10130 | |
da5a662a | 1770 | #define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248 |
a2fbb9ea ET |
1771 | /* [RW 1] send to BRB1 if no match on any of RMP rules. */ |
1772 | #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc | |
c18487ee YR |
1773 | /* [RW 2] Determine the classification participants. 0: no classification.1: |
1774 | classification upon VLAN id. 2: classification upon MAC address. 3: | |
1775 | classification upon both VLAN id & MAC addr. */ | |
1776 | #define NIG_REG_LLH1_CLS_TYPE 0x16084 | |
a2fbb9ea ET |
1777 | /* [RW 32] cm header for llh1 */ |
1778 | #define NIG_REG_LLH1_CM_HEADER 0x10080 | |
1779 | #define NIG_REG_LLH1_ERROR_MASK 0x10090 | |
1780 | /* [RW 8] event id for llh1 */ | |
1781 | #define NIG_REG_LLH1_EVENT_ID 0x10088 | |
1782 | /* [RW 8] init credit counter for port1 in LLH */ | |
1783 | #define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564 | |
1784 | #define NIG_REG_LLH1_XCM_MASK 0x10134 | |
c18487ee YR |
1785 | /* [RW 1] When this bit is set; the LLH will expect all packets to be with |
1786 | e1hov */ | |
1787 | #define NIG_REG_LLH_E1HOV_MODE 0x160d8 | |
1788 | /* [RW 1] When this bit is set; the LLH will classify the packet before | |
1789 | sending it to the BRB or calculating WoL on it. */ | |
1790 | #define NIG_REG_LLH_MF_MODE 0x16024 | |
a2fbb9ea ET |
1791 | #define NIG_REG_MASK_INTERRUPT_PORT0 0x10330 |
1792 | #define NIG_REG_MASK_INTERRUPT_PORT1 0x10334 | |
1793 | /* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */ | |
1794 | #define NIG_REG_NIG_EMAC0_EN 0x1003c | |
c18487ee YR |
1795 | /* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */ |
1796 | #define NIG_REG_NIG_EMAC1_EN 0x10040 | |
a2fbb9ea ET |
1797 | /* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the |
1798 | EMAC0 to strip the CRC from the ingress packets. */ | |
1799 | #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044 | |
c18487ee YR |
1800 | /* [R 32] Interrupt register #0 read */ |
1801 | #define NIG_REG_NIG_INT_STS_0 0x103b0 | |
1802 | #define NIG_REG_NIG_INT_STS_1 0x103c0 | |
1803 | /* [R 32] Parity register #0 read */ | |
1804 | #define NIG_REG_NIG_PRTY_STS 0x103d0 | |
1c06328c EG |
1805 | /* [RW 1] Pause enable for port0. This register may get 1 only when |
1806 | ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same | |
1807 | port */ | |
1808 | #define NIG_REG_PAUSE_ENABLE_0 0x160c0 | |
a2fbb9ea ET |
1809 | /* [RW 1] Input enable for RX PBF LP IF */ |
1810 | #define NIG_REG_PBF_LB_IN_EN 0x100b4 | |
f1410647 ET |
1811 | /* [RW 1] Value of this register will be transmitted to port swap when |
1812 | ~nig_registers_strap_override.strap_override =1 */ | |
1813 | #define NIG_REG_PORT_SWAP 0x10394 | |
a2fbb9ea ET |
1814 | /* [RW 1] output enable for RX parser descriptor IF */ |
1815 | #define NIG_REG_PRS_EOP_OUT_EN 0x10104 | |
1816 | /* [RW 1] Input enable for RX parser request IF */ | |
1817 | #define NIG_REG_PRS_REQ_IN_EN 0x100b8 | |
c1b73990 EG |
1818 | /* [RW 5] control to serdes - CL45 DEVAD */ |
1819 | #define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370 | |
1820 | /* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */ | |
1821 | #define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c | |
a2fbb9ea ET |
1822 | /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */ |
1823 | #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374 | |
1824 | /* [R 1] status from serdes0 that inputs to interrupt logic of link status */ | |
1825 | #define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578 | |
1826 | /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure | |
1827 | for port0 */ | |
1828 | #define NIG_REG_STAT0_BRB_DISCARD 0x105f0 | |
66e855f3 YG |
1829 | /* [R 32] Rx statistics : In user packets truncated due to BRB backpressure |
1830 | for port0 */ | |
1831 | #define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8 | |
34f80b04 EG |
1832 | /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that |
1833 | between 1024 and 1522 bytes for port0 */ | |
1834 | #define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750 | |
1835 | /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that | |
1836 | between 1523 bytes and above for port0 */ | |
1837 | #define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760 | |
a2fbb9ea ET |
1838 | /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure |
1839 | for port1 */ | |
1840 | #define NIG_REG_STAT1_BRB_DISCARD 0x10628 | |
34f80b04 EG |
1841 | /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that |
1842 | between 1024 and 1522 bytes for port1 */ | |
1843 | #define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0 | |
1844 | /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that | |
1845 | between 1523 bytes and above for port1 */ | |
1846 | #define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0 | |
a2fbb9ea ET |
1847 | /* [WB_R 64] Rx statistics : User octets received for LP */ |
1848 | #define NIG_REG_STAT2_BRB_OCTET 0x107e0 | |
1849 | #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328 | |
1850 | #define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c | |
f1410647 ET |
1851 | /* [RW 1] port swap mux selection. If this register equal to 0 then port |
1852 | swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then | |
1853 | ort swap is equal to ~nig_registers_port_swap.port_swap */ | |
1854 | #define NIG_REG_STRAP_OVERRIDE 0x10398 | |
a2fbb9ea ET |
1855 | /* [RW 1] output enable for RX_XCM0 IF */ |
1856 | #define NIG_REG_XCM0_OUT_EN 0x100f0 | |
1857 | /* [RW 1] output enable for RX_XCM1 IF */ | |
1858 | #define NIG_REG_XCM1_OUT_EN 0x100f4 | |
c18487ee YR |
1859 | /* [RW 1] control to xgxs - remote PHY in-band MDIO */ |
1860 | #define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348 | |
a2fbb9ea ET |
1861 | /* [RW 5] control to xgxs - CL45 DEVAD */ |
1862 | #define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c | |
c18487ee YR |
1863 | /* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */ |
1864 | #define NIG_REG_XGXS0_CTRL_MD_ST 0x10338 | |
a2fbb9ea ET |
1865 | /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */ |
1866 | #define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340 | |
1867 | /* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */ | |
1868 | #define NIG_REG_XGXS0_STATUS_LINK10G 0x10680 | |
1869 | /* [R 4] status from xgxs0 that inputs to interrupt logic of link status */ | |
1870 | #define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684 | |
1871 | /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */ | |
1872 | #define NIG_REG_XGXS_LANE_SEL_P0 0x102e8 | |
1873 | /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */ | |
1874 | #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0 | |
1875 | #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9) | |
1876 | #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15) | |
1877 | #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18) | |
1878 | #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18 | |
1879 | /* [RW 1] Disable processing further tasks from port 0 (after ending the | |
1880 | current task in process). */ | |
1881 | #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c | |
1882 | /* [RW 1] Disable processing further tasks from port 1 (after ending the | |
1883 | current task in process). */ | |
1884 | #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060 | |
1885 | /* [RW 1] Disable processing further tasks from port 4 (after ending the | |
1886 | current task in process). */ | |
1887 | #define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c | |
1888 | #define PBF_REG_IF_ENABLE_REG 0x140044 | |
1889 | /* [RW 1] Init bit. When set the initial credits are copied to the credit | |
1890 | registers (except the port credits). Should be set and then reset after | |
1891 | the configuration of the block has ended. */ | |
1892 | #define PBF_REG_INIT 0x140000 | |
1893 | /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is | |
1894 | copied to the credit register. Should be set and then reset after the | |
1895 | configuration of the port has ended. */ | |
1896 | #define PBF_REG_INIT_P0 0x140004 | |
1897 | /* [RW 1] Init bit for port 1. When set the initial credit of port 1 is | |
1898 | copied to the credit register. Should be set and then reset after the | |
1899 | configuration of the port has ended. */ | |
1900 | #define PBF_REG_INIT_P1 0x140008 | |
1901 | /* [RW 1] Init bit for port 4. When set the initial credit of port 4 is | |
1902 | copied to the credit register. Should be set and then reset after the | |
1903 | configuration of the port has ended. */ | |
1904 | #define PBF_REG_INIT_P4 0x14000c | |
1905 | /* [RW 1] Enable for mac interface 0. */ | |
1906 | #define PBF_REG_MAC_IF0_ENABLE 0x140030 | |
1907 | /* [RW 1] Enable for mac interface 1. */ | |
1908 | #define PBF_REG_MAC_IF1_ENABLE 0x140034 | |
1909 | /* [RW 1] Enable for the loopback interface. */ | |
1910 | #define PBF_REG_MAC_LB_ENABLE 0x140040 | |
1911 | /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause | |
1912 | not suppoterd. */ | |
1913 | #define PBF_REG_P0_ARB_THRSH 0x1400e4 | |
1914 | /* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */ | |
1915 | #define PBF_REG_P0_CREDIT 0x140200 | |
1916 | /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte | |
1917 | lines. */ | |
1918 | #define PBF_REG_P0_INIT_CRD 0x1400d0 | |
1919 | /* [RW 1] Indication that pause is enabled for port 0. */ | |
1920 | #define PBF_REG_P0_PAUSE_ENABLE 0x140014 | |
1921 | /* [R 8] Number of tasks in port 0 task queue. */ | |
1922 | #define PBF_REG_P0_TASK_CNT 0x140204 | |
1923 | /* [R 11] Current credit for port 1 in the tx port buffers in 16 byte lines. */ | |
1924 | #define PBF_REG_P1_CREDIT 0x140208 | |
1925 | /* [RW 11] Initial credit for port 1 in the tx port buffers in 16 byte | |
1926 | lines. */ | |
1927 | #define PBF_REG_P1_INIT_CRD 0x1400d4 | |
1928 | /* [R 8] Number of tasks in port 1 task queue. */ | |
1929 | #define PBF_REG_P1_TASK_CNT 0x14020c | |
1930 | /* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */ | |
1931 | #define PBF_REG_P4_CREDIT 0x140210 | |
1932 | /* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte | |
1933 | lines. */ | |
1934 | #define PBF_REG_P4_INIT_CRD 0x1400e0 | |
1935 | /* [R 8] Number of tasks in port 4 task queue. */ | |
1936 | #define PBF_REG_P4_TASK_CNT 0x140214 | |
1937 | /* [RW 5] Interrupt mask register #0 read/write */ | |
1938 | #define PBF_REG_PBF_INT_MASK 0x1401d4 | |
1939 | /* [R 5] Interrupt register #0 read */ | |
1940 | #define PBF_REG_PBF_INT_STS 0x1401c8 | |
1941 | #define PB_REG_CONTROL 0 | |
1942 | /* [RW 2] Interrupt mask register #0 read/write */ | |
1943 | #define PB_REG_PB_INT_MASK 0x28 | |
1944 | /* [R 2] Interrupt register #0 read */ | |
1945 | #define PB_REG_PB_INT_STS 0x1c | |
1946 | /* [RW 4] Parity mask register #0 read/write */ | |
1947 | #define PB_REG_PB_PRTY_MASK 0x38 | |
f1410647 ET |
1948 | /* [R 4] Parity register #0 read */ |
1949 | #define PB_REG_PB_PRTY_STS 0x2c | |
a2fbb9ea ET |
1950 | #define PRS_REG_A_PRSU_20 0x40134 |
1951 | /* [R 8] debug only: CFC load request current credit. Transaction based. */ | |
1952 | #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164 | |
1953 | /* [R 8] debug only: CFC search request current credit. Transaction based. */ | |
1954 | #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168 | |
1955 | /* [RW 6] The initial credit for the search message to the CFC interface. | |
1956 | Credit is transaction based. */ | |
1957 | #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c | |
1958 | /* [RW 24] CID for port 0 if no match */ | |
1959 | #define PRS_REG_CID_PORT_0 0x400fc | |
a2fbb9ea ET |
1960 | /* [RW 32] The CM header for flush message where 'load existed' bit in CFC |
1961 | load response is reset and packet type is 0. Used in packet start message | |
1962 | to TCM. */ | |
1963 | #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc | |
1964 | #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0 | |
1965 | #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4 | |
1966 | #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8 | |
1967 | #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec | |
8d9c5f34 | 1968 | #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0 |
a2fbb9ea ET |
1969 | /* [RW 32] The CM header for flush message where 'load existed' bit in CFC |
1970 | load response is set and packet type is 0. Used in packet start message | |
1971 | to TCM. */ | |
1972 | #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc | |
1973 | #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0 | |
1974 | #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4 | |
1975 | #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8 | |
1976 | #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc | |
8d9c5f34 | 1977 | #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0 |
a2fbb9ea ET |
1978 | /* [RW 32] The CM header for a match and packet type 1 for loopback port. |
1979 | Used in packet start message to TCM. */ | |
1980 | #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c | |
1981 | #define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0 | |
1982 | #define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4 | |
1983 | #define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8 | |
1984 | /* [RW 32] The CM header for a match and packet type 0. Used in packet start | |
1985 | message to TCM. */ | |
1986 | #define PRS_REG_CM_HDR_TYPE_0 0x40078 | |
1987 | #define PRS_REG_CM_HDR_TYPE_1 0x4007c | |
1988 | #define PRS_REG_CM_HDR_TYPE_2 0x40080 | |
1989 | #define PRS_REG_CM_HDR_TYPE_3 0x40084 | |
1990 | #define PRS_REG_CM_HDR_TYPE_4 0x40088 | |
1991 | /* [RW 32] The CM header in case there was not a match on the connection */ | |
1992 | #define PRS_REG_CM_NO_MATCH_HDR 0x400b8 | |
c18487ee YR |
1993 | /* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */ |
1994 | #define PRS_REG_E1HOV_MODE 0x401c8 | |
a2fbb9ea ET |
1995 | /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet |
1996 | start message to TCM. */ | |
1997 | #define PRS_REG_EVENT_ID_1 0x40054 | |
1998 | #define PRS_REG_EVENT_ID_2 0x40058 | |
1999 | #define PRS_REG_EVENT_ID_3 0x4005c | |
c18487ee YR |
2000 | /* [RW 16] The Ethernet type value for FCoE */ |
2001 | #define PRS_REG_FCOE_TYPE 0x401d0 | |
a2fbb9ea ET |
2002 | /* [RW 8] Context region for flush packet with packet type 0. Used in CFC |
2003 | load request message. */ | |
2004 | #define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004 | |
2005 | #define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008 | |
2006 | #define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c | |
2007 | #define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010 | |
2008 | #define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014 | |
2009 | #define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018 | |
2010 | #define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c | |
2011 | #define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020 | |
2012 | /* [RW 4] The increment value to send in the CFC load request message */ | |
2013 | #define PRS_REG_INC_VALUE 0x40048 | |
2014 | /* [RW 1] If set indicates not to send messages to CFC on received packets */ | |
2015 | #define PRS_REG_NIC_MODE 0x40138 | |
2016 | /* [RW 8] The 8-bit event ID for cases where there is no match on the | |
2017 | connection. Used in packet start message to TCM. */ | |
2018 | #define PRS_REG_NO_MATCH_EVENT_ID 0x40070 | |
2019 | /* [ST 24] The number of input CFC flush packets */ | |
2020 | #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128 | |
2021 | /* [ST 32] The number of cycles the Parser halted its operation since it | |
2022 | could not allocate the next serial number */ | |
2023 | #define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130 | |
2024 | /* [ST 24] The number of input packets */ | |
2025 | #define PRS_REG_NUM_OF_PACKETS 0x40124 | |
2026 | /* [ST 24] The number of input transparent flush packets */ | |
2027 | #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c | |
2028 | /* [RW 8] Context region for received Ethernet packet with a match and | |
2029 | packet type 0. Used in CFC load request message */ | |
2030 | #define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028 | |
2031 | #define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c | |
2032 | #define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030 | |
2033 | #define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034 | |
2034 | #define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038 | |
2035 | #define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c | |
2036 | #define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040 | |
2037 | #define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044 | |
2038 | /* [R 2] debug only: Number of pending requests for CAC on port 0. */ | |
2039 | #define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174 | |
2040 | /* [R 2] debug only: Number of pending requests for header parsing. */ | |
2041 | #define PRS_REG_PENDING_BRB_PRS_RQ 0x40170 | |
2042 | /* [R 1] Interrupt register #0 read */ | |
2043 | #define PRS_REG_PRS_INT_STS 0x40188 | |
2044 | /* [RW 8] Parity mask register #0 read/write */ | |
2045 | #define PRS_REG_PRS_PRTY_MASK 0x401a4 | |
f1410647 ET |
2046 | /* [R 8] Parity register #0 read */ |
2047 | #define PRS_REG_PRS_PRTY_STS 0x40198 | |
a2fbb9ea ET |
2048 | /* [RW 8] Context region for pure acknowledge packets. Used in CFC load |
2049 | request message */ | |
2050 | #define PRS_REG_PURE_REGIONS 0x40024 | |
2051 | /* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this | |
2052 | serail number was released by SDM but cannot be used because a previous | |
2053 | serial number was not released. */ | |
2054 | #define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154 | |
2055 | /* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this | |
2056 | serail number was released by SDM but cannot be used because a previous | |
2057 | serial number was not released. */ | |
2058 | #define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158 | |
2059 | /* [R 4] debug only: SRC current credit. Transaction based. */ | |
2060 | #define PRS_REG_SRC_CURRENT_CREDIT 0x4016c | |
2061 | /* [R 8] debug only: TCM current credit. Cycle based. */ | |
2062 | #define PRS_REG_TCM_CURRENT_CREDIT 0x40160 | |
2063 | /* [R 8] debug only: TSDM current credit. Transaction based. */ | |
2064 | #define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c | |
2065 | /* [R 6] Debug only: Number of used entries in the data FIFO */ | |
2066 | #define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c | |
2067 | /* [R 7] Debug only: Number of used entries in the header FIFO */ | |
2068 | #define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478 | |
34f80b04 EG |
2069 | #define PXP2_REG_PGL_ADDR_88_F0 0x120534 |
2070 | #define PXP2_REG_PGL_ADDR_8C_F0 0x120538 | |
2071 | #define PXP2_REG_PGL_ADDR_90_F0 0x12053c | |
2072 | #define PXP2_REG_PGL_ADDR_94_F0 0x120540 | |
a2fbb9ea ET |
2073 | #define PXP2_REG_PGL_CONTROL0 0x120490 |
2074 | #define PXP2_REG_PGL_CONTROL1 0x120514 | |
c18487ee YR |
2075 | /* [RW 32] third dword data of expansion rom request. this register is |
2076 | special. reading from it provides a vector outstanding read requests. if | |
2077 | a bit is zero it means that a read request on the corresponding tag did | |
2078 | not finish yet (not all completions have arrived for it) */ | |
2079 | #define PXP2_REG_PGL_EXP_ROM2 0x120808 | |
a2fbb9ea ET |
2080 | /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask; |
2081 | its[15:0]-address */ | |
2082 | #define PXP2_REG_PGL_INT_CSDM_0 0x1204f4 | |
2083 | #define PXP2_REG_PGL_INT_CSDM_1 0x1204f8 | |
2084 | #define PXP2_REG_PGL_INT_CSDM_2 0x1204fc | |
2085 | #define PXP2_REG_PGL_INT_CSDM_3 0x120500 | |
2086 | #define PXP2_REG_PGL_INT_CSDM_4 0x120504 | |
2087 | #define PXP2_REG_PGL_INT_CSDM_5 0x120508 | |
2088 | #define PXP2_REG_PGL_INT_CSDM_6 0x12050c | |
2089 | #define PXP2_REG_PGL_INT_CSDM_7 0x120510 | |
2090 | /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask; | |
2091 | its[15:0]-address */ | |
2092 | #define PXP2_REG_PGL_INT_TSDM_0 0x120494 | |
2093 | #define PXP2_REG_PGL_INT_TSDM_1 0x120498 | |
2094 | #define PXP2_REG_PGL_INT_TSDM_2 0x12049c | |
2095 | #define PXP2_REG_PGL_INT_TSDM_3 0x1204a0 | |
2096 | #define PXP2_REG_PGL_INT_TSDM_4 0x1204a4 | |
2097 | #define PXP2_REG_PGL_INT_TSDM_5 0x1204a8 | |
2098 | #define PXP2_REG_PGL_INT_TSDM_6 0x1204ac | |
2099 | #define PXP2_REG_PGL_INT_TSDM_7 0x1204b0 | |
2100 | /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask; | |
2101 | its[15:0]-address */ | |
2102 | #define PXP2_REG_PGL_INT_USDM_0 0x1204b4 | |
2103 | #define PXP2_REG_PGL_INT_USDM_1 0x1204b8 | |
2104 | #define PXP2_REG_PGL_INT_USDM_2 0x1204bc | |
2105 | #define PXP2_REG_PGL_INT_USDM_3 0x1204c0 | |
2106 | #define PXP2_REG_PGL_INT_USDM_4 0x1204c4 | |
2107 | #define PXP2_REG_PGL_INT_USDM_5 0x1204c8 | |
2108 | #define PXP2_REG_PGL_INT_USDM_6 0x1204cc | |
2109 | #define PXP2_REG_PGL_INT_USDM_7 0x1204d0 | |
2110 | /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask; | |
2111 | its[15:0]-address */ | |
2112 | #define PXP2_REG_PGL_INT_XSDM_0 0x1204d4 | |
2113 | #define PXP2_REG_PGL_INT_XSDM_1 0x1204d8 | |
2114 | #define PXP2_REG_PGL_INT_XSDM_2 0x1204dc | |
2115 | #define PXP2_REG_PGL_INT_XSDM_3 0x1204e0 | |
2116 | #define PXP2_REG_PGL_INT_XSDM_4 0x1204e4 | |
2117 | #define PXP2_REG_PGL_INT_XSDM_5 0x1204e8 | |
2118 | #define PXP2_REG_PGL_INT_XSDM_6 0x1204ec | |
2119 | #define PXP2_REG_PGL_INT_XSDM_7 0x1204f0 | |
f1ef27ef EG |
2120 | /* [RW 3] this field allows one function to pretend being another function |
2121 | when accessing any BAR mapped resource within the device. the value of | |
2122 | the field is the number of the function that will be accessed | |
2123 | effectively. after software write to this bit it must read it in order to | |
2124 | know that the new value is updated */ | |
2125 | #define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674 | |
2126 | #define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678 | |
2127 | #define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c | |
2128 | #define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680 | |
2129 | #define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684 | |
2130 | #define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688 | |
2131 | #define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c | |
2132 | #define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690 | |
a2fbb9ea ET |
2133 | /* [R 1] this bit indicates that a read request was blocked because of |
2134 | bus_master_en was deasserted */ | |
2135 | #define PXP2_REG_PGL_READ_BLOCKED 0x120568 | |
c18487ee | 2136 | #define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8 |
a2fbb9ea ET |
2137 | /* [R 18] debug only */ |
2138 | #define PXP2_REG_PGL_TXW_CDTS 0x12052c | |
2139 | /* [R 1] this bit indicates that a write request was blocked because of | |
2140 | bus_master_en was deasserted */ | |
2141 | #define PXP2_REG_PGL_WRITE_BLOCKED 0x120564 | |
2142 | #define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0 | |
2143 | #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4 | |
2144 | #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8 | |
2145 | #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4 | |
2146 | #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8 | |
2147 | #define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4 | |
2148 | #define PXP2_REG_PSWRQ_BW_ADD28 0x120228 | |
2149 | #define PXP2_REG_PSWRQ_BW_ADD28 0x120228 | |
2150 | #define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8 | |
2151 | #define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4 | |
2152 | #define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8 | |
2153 | #define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc | |
2154 | #define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0 | |
2155 | #define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c | |
2156 | #define PXP2_REG_PSWRQ_BW_L1 0x1202b0 | |
2157 | #define PXP2_REG_PSWRQ_BW_L10 0x1202d4 | |
2158 | #define PXP2_REG_PSWRQ_BW_L11 0x1202d8 | |
2159 | #define PXP2_REG_PSWRQ_BW_L10 0x1202d4 | |
2160 | #define PXP2_REG_PSWRQ_BW_L11 0x1202d8 | |
2161 | #define PXP2_REG_PSWRQ_BW_L2 0x1202b4 | |
2162 | #define PXP2_REG_PSWRQ_BW_L28 0x120318 | |
2163 | #define PXP2_REG_PSWRQ_BW_L28 0x120318 | |
2164 | #define PXP2_REG_PSWRQ_BW_L3 0x1202b8 | |
2165 | #define PXP2_REG_PSWRQ_BW_L6 0x1202c4 | |
2166 | #define PXP2_REG_PSWRQ_BW_L7 0x1202c8 | |
2167 | #define PXP2_REG_PSWRQ_BW_L8 0x1202cc | |
2168 | #define PXP2_REG_PSWRQ_BW_L9 0x1202d0 | |
2169 | #define PXP2_REG_PSWRQ_BW_RD 0x120324 | |
2170 | #define PXP2_REG_PSWRQ_BW_UB1 0x120238 | |
2171 | #define PXP2_REG_PSWRQ_BW_UB10 0x12025c | |
2172 | #define PXP2_REG_PSWRQ_BW_UB11 0x120260 | |
2173 | #define PXP2_REG_PSWRQ_BW_UB10 0x12025c | |
2174 | #define PXP2_REG_PSWRQ_BW_UB11 0x120260 | |
2175 | #define PXP2_REG_PSWRQ_BW_UB2 0x12023c | |
2176 | #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0 | |
2177 | #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0 | |
2178 | #define PXP2_REG_PSWRQ_BW_UB3 0x120240 | |
2179 | #define PXP2_REG_PSWRQ_BW_UB6 0x12024c | |
2180 | #define PXP2_REG_PSWRQ_BW_UB7 0x120250 | |
2181 | #define PXP2_REG_PSWRQ_BW_UB8 0x120254 | |
2182 | #define PXP2_REG_PSWRQ_BW_UB9 0x120258 | |
2183 | #define PXP2_REG_PSWRQ_BW_WR 0x120328 | |
2184 | #define PXP2_REG_PSWRQ_CDU0_L2P 0x120000 | |
2185 | #define PXP2_REG_PSWRQ_QM0_L2P 0x120038 | |
2186 | #define PXP2_REG_PSWRQ_SRC0_L2P 0x120054 | |
2187 | #define PXP2_REG_PSWRQ_TM0_L2P 0x12001c | |
c18487ee | 2188 | #define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0 |
34f80b04 EG |
2189 | /* [RW 32] Interrupt mask register #0 read/write */ |
2190 | #define PXP2_REG_PXP2_INT_MASK_0 0x120578 | |
2191 | /* [R 32] Interrupt register #0 read */ | |
2192 | #define PXP2_REG_PXP2_INT_STS_0 0x12056c | |
2193 | #define PXP2_REG_PXP2_INT_STS_1 0x120608 | |
2194 | /* [RC 32] Interrupt register #0 read clear */ | |
2195 | #define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570 | |
a2fbb9ea ET |
2196 | /* [RW 32] Parity mask register #0 read/write */ |
2197 | #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588 | |
2198 | #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598 | |
f1410647 ET |
2199 | /* [R 32] Parity register #0 read */ |
2200 | #define PXP2_REG_PXP2_PRTY_STS_0 0x12057c | |
2201 | #define PXP2_REG_PXP2_PRTY_STS_1 0x12058c | |
a2fbb9ea ET |
2202 | /* [R 1] Debug only: The 'almost full' indication from each fifo (gives |
2203 | indication about backpressure) */ | |
2204 | #define PXP2_REG_RD_ALMOST_FULL_0 0x120424 | |
2205 | /* [R 8] Debug only: The blocks counter - number of unused block ids */ | |
2206 | #define PXP2_REG_RD_BLK_CNT 0x120418 | |
2207 | /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer. | |
2208 | Must be bigger than 6. Normally should not be changed. */ | |
2209 | #define PXP2_REG_RD_BLK_NUM_CFG 0x12040c | |
2210 | /* [RW 2] CDU byte swapping mode configuration for master read requests */ | |
2211 | #define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404 | |
2212 | /* [RW 1] When '1'; inputs to the PSWRD block are ignored */ | |
2213 | #define PXP2_REG_RD_DISABLE_INPUTS 0x120374 | |
2214 | /* [R 1] PSWRD internal memories initialization is done */ | |
2215 | #define PXP2_REG_RD_INIT_DONE 0x120370 | |
2216 | /* [RW 8] The maximum number of blocks in Tetris Buffer that can be | |
2217 | allocated for vq10 */ | |
2218 | #define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0 | |
2219 | /* [RW 8] The maximum number of blocks in Tetris Buffer that can be | |
2220 | allocated for vq11 */ | |
2221 | #define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4 | |
2222 | /* [RW 8] The maximum number of blocks in Tetris Buffer that can be | |
2223 | allocated for vq17 */ | |
2224 | #define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc | |
2225 | /* [RW 8] The maximum number of blocks in Tetris Buffer that can be | |
2226 | allocated for vq18 */ | |
2227 | #define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0 | |
2228 | /* [RW 8] The maximum number of blocks in Tetris Buffer that can be | |
2229 | allocated for vq19 */ | |
2230 | #define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4 | |
2231 | /* [RW 8] The maximum number of blocks in Tetris Buffer that can be | |
2232 | allocated for vq22 */ | |
2233 | #define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0 | |
2234 | /* [RW 8] The maximum number of blocks in Tetris Buffer that can be | |
2235 | allocated for vq6 */ | |
2236 | #define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390 | |
2237 | /* [RW 8] The maximum number of blocks in Tetris Buffer that can be | |
2238 | allocated for vq9 */ | |
2239 | #define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c | |
2240 | /* [RW 2] PBF byte swapping mode configuration for master read requests */ | |
2241 | #define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4 | |
2242 | /* [R 1] Debug only: Indication if delivery ports are idle */ | |
2243 | #define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c | |
2244 | #define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420 | |
2245 | /* [RW 2] QM byte swapping mode configuration for master read requests */ | |
2246 | #define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8 | |
2247 | /* [R 7] Debug only: The SR counter - number of unused sub request ids */ | |
2248 | #define PXP2_REG_RD_SR_CNT 0x120414 | |
2249 | /* [RW 2] SRC byte swapping mode configuration for master read requests */ | |
2250 | #define PXP2_REG_RD_SRC_SWAP_MODE 0x120400 | |
2251 | /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must | |
2252 | be bigger than 1. Normally should not be changed. */ | |
2253 | #define PXP2_REG_RD_SR_NUM_CFG 0x120408 | |
2254 | /* [RW 1] Signals the PSWRD block to start initializing internal memories */ | |
2255 | #define PXP2_REG_RD_START_INIT 0x12036c | |
2256 | /* [RW 2] TM byte swapping mode configuration for master read requests */ | |
2257 | #define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc | |
2258 | /* [RW 10] Bandwidth addition to VQ0 write requests */ | |
2259 | #define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc | |
2260 | /* [RW 10] Bandwidth addition to VQ12 read requests */ | |
2261 | #define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec | |
2262 | /* [RW 10] Bandwidth addition to VQ13 read requests */ | |
2263 | #define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0 | |
2264 | /* [RW 10] Bandwidth addition to VQ14 read requests */ | |
2265 | #define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4 | |
2266 | /* [RW 10] Bandwidth addition to VQ15 read requests */ | |
2267 | #define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8 | |
2268 | /* [RW 10] Bandwidth addition to VQ16 read requests */ | |
2269 | #define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc | |
2270 | /* [RW 10] Bandwidth addition to VQ17 read requests */ | |
2271 | #define PXP2_REG_RQ_BW_RD_ADD17 0x120200 | |
2272 | /* [RW 10] Bandwidth addition to VQ18 read requests */ | |
2273 | #define PXP2_REG_RQ_BW_RD_ADD18 0x120204 | |
2274 | /* [RW 10] Bandwidth addition to VQ19 read requests */ | |
2275 | #define PXP2_REG_RQ_BW_RD_ADD19 0x120208 | |
2276 | /* [RW 10] Bandwidth addition to VQ20 read requests */ | |
2277 | #define PXP2_REG_RQ_BW_RD_ADD20 0x12020c | |
2278 | /* [RW 10] Bandwidth addition to VQ22 read requests */ | |
2279 | #define PXP2_REG_RQ_BW_RD_ADD22 0x120210 | |
2280 | /* [RW 10] Bandwidth addition to VQ23 read requests */ | |
2281 | #define PXP2_REG_RQ_BW_RD_ADD23 0x120214 | |
2282 | /* [RW 10] Bandwidth addition to VQ24 read requests */ | |
2283 | #define PXP2_REG_RQ_BW_RD_ADD24 0x120218 | |
2284 | /* [RW 10] Bandwidth addition to VQ25 read requests */ | |
2285 | #define PXP2_REG_RQ_BW_RD_ADD25 0x12021c | |
2286 | /* [RW 10] Bandwidth addition to VQ26 read requests */ | |
2287 | #define PXP2_REG_RQ_BW_RD_ADD26 0x120220 | |
2288 | /* [RW 10] Bandwidth addition to VQ27 read requests */ | |
2289 | #define PXP2_REG_RQ_BW_RD_ADD27 0x120224 | |
2290 | /* [RW 10] Bandwidth addition to VQ4 read requests */ | |
2291 | #define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc | |
2292 | /* [RW 10] Bandwidth addition to VQ5 read requests */ | |
2293 | #define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0 | |
2294 | /* [RW 10] Bandwidth Typical L for VQ0 Read requests */ | |
2295 | #define PXP2_REG_RQ_BW_RD_L0 0x1202ac | |
2296 | /* [RW 10] Bandwidth Typical L for VQ12 Read requests */ | |
2297 | #define PXP2_REG_RQ_BW_RD_L12 0x1202dc | |
2298 | /* [RW 10] Bandwidth Typical L for VQ13 Read requests */ | |
2299 | #define PXP2_REG_RQ_BW_RD_L13 0x1202e0 | |
2300 | /* [RW 10] Bandwidth Typical L for VQ14 Read requests */ | |
2301 | #define PXP2_REG_RQ_BW_RD_L14 0x1202e4 | |
2302 | /* [RW 10] Bandwidth Typical L for VQ15 Read requests */ | |
2303 | #define PXP2_REG_RQ_BW_RD_L15 0x1202e8 | |
2304 | /* [RW 10] Bandwidth Typical L for VQ16 Read requests */ | |
2305 | #define PXP2_REG_RQ_BW_RD_L16 0x1202ec | |
2306 | /* [RW 10] Bandwidth Typical L for VQ17 Read requests */ | |
2307 | #define PXP2_REG_RQ_BW_RD_L17 0x1202f0 | |
2308 | /* [RW 10] Bandwidth Typical L for VQ18 Read requests */ | |
2309 | #define PXP2_REG_RQ_BW_RD_L18 0x1202f4 | |
2310 | /* [RW 10] Bandwidth Typical L for VQ19 Read requests */ | |
2311 | #define PXP2_REG_RQ_BW_RD_L19 0x1202f8 | |
2312 | /* [RW 10] Bandwidth Typical L for VQ20 Read requests */ | |
2313 | #define PXP2_REG_RQ_BW_RD_L20 0x1202fc | |
2314 | /* [RW 10] Bandwidth Typical L for VQ22 Read requests */ | |
2315 | #define PXP2_REG_RQ_BW_RD_L22 0x120300 | |
2316 | /* [RW 10] Bandwidth Typical L for VQ23 Read requests */ | |
2317 | #define PXP2_REG_RQ_BW_RD_L23 0x120304 | |
2318 | /* [RW 10] Bandwidth Typical L for VQ24 Read requests */ | |
2319 | #define PXP2_REG_RQ_BW_RD_L24 0x120308 | |
2320 | /* [RW 10] Bandwidth Typical L for VQ25 Read requests */ | |
2321 | #define PXP2_REG_RQ_BW_RD_L25 0x12030c | |
2322 | /* [RW 10] Bandwidth Typical L for VQ26 Read requests */ | |
2323 | #define PXP2_REG_RQ_BW_RD_L26 0x120310 | |
2324 | /* [RW 10] Bandwidth Typical L for VQ27 Read requests */ | |
2325 | #define PXP2_REG_RQ_BW_RD_L27 0x120314 | |
2326 | /* [RW 10] Bandwidth Typical L for VQ4 Read requests */ | |
2327 | #define PXP2_REG_RQ_BW_RD_L4 0x1202bc | |
2328 | /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */ | |
2329 | #define PXP2_REG_RQ_BW_RD_L5 0x1202c0 | |
2330 | /* [RW 7] Bandwidth upper bound for VQ0 read requests */ | |
2331 | #define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234 | |
2332 | /* [RW 7] Bandwidth upper bound for VQ12 read requests */ | |
2333 | #define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264 | |
2334 | /* [RW 7] Bandwidth upper bound for VQ13 read requests */ | |
2335 | #define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268 | |
2336 | /* [RW 7] Bandwidth upper bound for VQ14 read requests */ | |
2337 | #define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c | |
2338 | /* [RW 7] Bandwidth upper bound for VQ15 read requests */ | |
2339 | #define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270 | |
2340 | /* [RW 7] Bandwidth upper bound for VQ16 read requests */ | |
2341 | #define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274 | |
2342 | /* [RW 7] Bandwidth upper bound for VQ17 read requests */ | |
2343 | #define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278 | |
2344 | /* [RW 7] Bandwidth upper bound for VQ18 read requests */ | |
2345 | #define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c | |
2346 | /* [RW 7] Bandwidth upper bound for VQ19 read requests */ | |
2347 | #define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280 | |
2348 | /* [RW 7] Bandwidth upper bound for VQ20 read requests */ | |
2349 | #define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284 | |
2350 | /* [RW 7] Bandwidth upper bound for VQ22 read requests */ | |
2351 | #define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288 | |
2352 | /* [RW 7] Bandwidth upper bound for VQ23 read requests */ | |
2353 | #define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c | |
2354 | /* [RW 7] Bandwidth upper bound for VQ24 read requests */ | |
2355 | #define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290 | |
2356 | /* [RW 7] Bandwidth upper bound for VQ25 read requests */ | |
2357 | #define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294 | |
2358 | /* [RW 7] Bandwidth upper bound for VQ26 read requests */ | |
2359 | #define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298 | |
2360 | /* [RW 7] Bandwidth upper bound for VQ27 read requests */ | |
2361 | #define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c | |
2362 | /* [RW 7] Bandwidth upper bound for VQ4 read requests */ | |
2363 | #define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244 | |
2364 | /* [RW 7] Bandwidth upper bound for VQ5 read requests */ | |
2365 | #define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248 | |
2366 | /* [RW 10] Bandwidth addition to VQ29 write requests */ | |
2367 | #define PXP2_REG_RQ_BW_WR_ADD29 0x12022c | |
2368 | /* [RW 10] Bandwidth addition to VQ30 write requests */ | |
2369 | #define PXP2_REG_RQ_BW_WR_ADD30 0x120230 | |
2370 | /* [RW 10] Bandwidth Typical L for VQ29 Write requests */ | |
2371 | #define PXP2_REG_RQ_BW_WR_L29 0x12031c | |
2372 | /* [RW 10] Bandwidth Typical L for VQ30 Write requests */ | |
2373 | #define PXP2_REG_RQ_BW_WR_L30 0x120320 | |
2374 | /* [RW 7] Bandwidth upper bound for VQ29 */ | |
2375 | #define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4 | |
2376 | /* [RW 7] Bandwidth upper bound for VQ30 */ | |
2377 | #define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8 | |
c18487ee YR |
2378 | /* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */ |
2379 | #define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008 | |
a2fbb9ea ET |
2380 | /* [RW 2] Endian mode for cdu */ |
2381 | #define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0 | |
c18487ee YR |
2382 | #define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c |
2383 | #define PXP2_REG_RQ_CDU_LAST_ILT 0x120620 | |
a2fbb9ea ET |
2384 | /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k; |
2385 | -128k */ | |
2386 | #define PXP2_REG_RQ_CDU_P_SIZE 0x120018 | |
2387 | /* [R 1] 1' indicates that the requester has finished its internal | |
2388 | configuration */ | |
2389 | #define PXP2_REG_RQ_CFG_DONE 0x1201b4 | |
2390 | /* [RW 2] Endian mode for debug */ | |
2391 | #define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4 | |
2392 | /* [RW 1] When '1'; requests will enter input buffers but wont get out | |
2393 | towards the glue */ | |
2394 | #define PXP2_REG_RQ_DISABLE_INPUTS 0x120330 | |
c18487ee YR |
2395 | /* [RW 1] 1 - SR will be aligned by 64B; 0 - SR will be aligned by 8B */ |
2396 | #define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0 | |
2397 | /* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will | |
2398 | be asserted */ | |
2399 | #define PXP2_REG_RQ_ELT_DISABLE 0x12066c | |
a2fbb9ea ET |
2400 | /* [RW 2] Endian mode for hc */ |
2401 | #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8 | |
c18487ee YR |
2402 | /* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back |
2403 | compatibility needs; Note that different registers are used per mode */ | |
2404 | #define PXP2_REG_RQ_ILT_MODE 0x1205b4 | |
a2fbb9ea ET |
2405 | /* [WB 53] Onchip address table */ |
2406 | #define PXP2_REG_RQ_ONCHIP_AT 0x122000 | |
c18487ee YR |
2407 | /* [WB 53] Onchip address table - B0 */ |
2408 | #define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000 | |
f1410647 ET |
2409 | /* [RW 13] Pending read limiter threshold; in Dwords */ |
2410 | #define PXP2_REG_RQ_PDR_LIMIT 0x12033c | |
a2fbb9ea ET |
2411 | /* [RW 2] Endian mode for qm */ |
2412 | #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194 | |
c18487ee YR |
2413 | #define PXP2_REG_RQ_QM_FIRST_ILT 0x120634 |
2414 | #define PXP2_REG_RQ_QM_LAST_ILT 0x120638 | |
a2fbb9ea ET |
2415 | /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k; |
2416 | -128k */ | |
2417 | #define PXP2_REG_RQ_QM_P_SIZE 0x120050 | |
33471629 | 2418 | /* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */ |
a2fbb9ea ET |
2419 | #define PXP2_REG_RQ_RBC_DONE 0x1201b0 |
2420 | /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B; | |
2421 | 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */ | |
2422 | #define PXP2_REG_RQ_RD_MBS0 0x120160 | |
f1410647 ET |
2423 | /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B; |
2424 | 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */ | |
2425 | #define PXP2_REG_RQ_RD_MBS1 0x120168 | |
a2fbb9ea ET |
2426 | /* [RW 2] Endian mode for src */ |
2427 | #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c | |
c18487ee YR |
2428 | #define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c |
2429 | #define PXP2_REG_RQ_SRC_LAST_ILT 0x120640 | |
a2fbb9ea ET |
2430 | /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k; |
2431 | -128k */ | |
2432 | #define PXP2_REG_RQ_SRC_P_SIZE 0x12006c | |
2433 | /* [RW 2] Endian mode for tm */ | |
2434 | #define PXP2_REG_RQ_TM_ENDIAN_M 0x120198 | |
c18487ee YR |
2435 | #define PXP2_REG_RQ_TM_FIRST_ILT 0x120644 |
2436 | #define PXP2_REG_RQ_TM_LAST_ILT 0x120648 | |
a2fbb9ea ET |
2437 | /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k; |
2438 | -128k */ | |
2439 | #define PXP2_REG_RQ_TM_P_SIZE 0x120034 | |
2440 | /* [R 5] Number of entries in the ufifo; his fifo has l2p completions */ | |
2441 | #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c | |
c18487ee YR |
2442 | /* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */ |
2443 | #define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094 | |
a2fbb9ea ET |
2444 | /* [R 8] Number of entries occupied by vq 0 in pswrq memory */ |
2445 | #define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810 | |
2446 | /* [R 8] Number of entries occupied by vq 10 in pswrq memory */ | |
2447 | #define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818 | |
2448 | /* [R 8] Number of entries occupied by vq 11 in pswrq memory */ | |
2449 | #define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820 | |
2450 | /* [R 8] Number of entries occupied by vq 12 in pswrq memory */ | |
2451 | #define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828 | |
2452 | /* [R 8] Number of entries occupied by vq 13 in pswrq memory */ | |
2453 | #define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830 | |
2454 | /* [R 8] Number of entries occupied by vq 14 in pswrq memory */ | |
2455 | #define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838 | |
2456 | /* [R 8] Number of entries occupied by vq 15 in pswrq memory */ | |
2457 | #define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840 | |
2458 | /* [R 8] Number of entries occupied by vq 16 in pswrq memory */ | |
2459 | #define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848 | |
2460 | /* [R 8] Number of entries occupied by vq 17 in pswrq memory */ | |
2461 | #define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850 | |
2462 | /* [R 8] Number of entries occupied by vq 18 in pswrq memory */ | |
2463 | #define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858 | |
2464 | /* [R 8] Number of entries occupied by vq 19 in pswrq memory */ | |
2465 | #define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860 | |
2466 | /* [R 8] Number of entries occupied by vq 1 in pswrq memory */ | |
2467 | #define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868 | |
2468 | /* [R 8] Number of entries occupied by vq 20 in pswrq memory */ | |
2469 | #define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870 | |
2470 | /* [R 8] Number of entries occupied by vq 21 in pswrq memory */ | |
2471 | #define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878 | |
2472 | /* [R 8] Number of entries occupied by vq 22 in pswrq memory */ | |
2473 | #define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880 | |
2474 | /* [R 8] Number of entries occupied by vq 23 in pswrq memory */ | |
2475 | #define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888 | |
2476 | /* [R 8] Number of entries occupied by vq 24 in pswrq memory */ | |
2477 | #define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890 | |
2478 | /* [R 8] Number of entries occupied by vq 25 in pswrq memory */ | |
2479 | #define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898 | |
2480 | /* [R 8] Number of entries occupied by vq 26 in pswrq memory */ | |
2481 | #define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0 | |
2482 | /* [R 8] Number of entries occupied by vq 27 in pswrq memory */ | |
2483 | #define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8 | |
2484 | /* [R 8] Number of entries occupied by vq 28 in pswrq memory */ | |
2485 | #define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0 | |
2486 | /* [R 8] Number of entries occupied by vq 29 in pswrq memory */ | |
2487 | #define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8 | |
2488 | /* [R 8] Number of entries occupied by vq 2 in pswrq memory */ | |
2489 | #define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0 | |
2490 | /* [R 8] Number of entries occupied by vq 30 in pswrq memory */ | |
2491 | #define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8 | |
2492 | /* [R 8] Number of entries occupied by vq 31 in pswrq memory */ | |
2493 | #define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0 | |
2494 | /* [R 8] Number of entries occupied by vq 3 in pswrq memory */ | |
2495 | #define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8 | |
2496 | /* [R 8] Number of entries occupied by vq 4 in pswrq memory */ | |
2497 | #define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0 | |
2498 | /* [R 8] Number of entries occupied by vq 5 in pswrq memory */ | |
2499 | #define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8 | |
2500 | /* [R 8] Number of entries occupied by vq 6 in pswrq memory */ | |
2501 | #define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0 | |
2502 | /* [R 8] Number of entries occupied by vq 7 in pswrq memory */ | |
2503 | #define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8 | |
2504 | /* [R 8] Number of entries occupied by vq 8 in pswrq memory */ | |
2505 | #define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900 | |
2506 | /* [R 8] Number of entries occupied by vq 9 in pswrq memory */ | |
2507 | #define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908 | |
2508 | /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B; | |
2509 | 001:256B; 010: 512B; */ | |
2510 | #define PXP2_REG_RQ_WR_MBS0 0x12015c | |
f1410647 ET |
2511 | /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B; |
2512 | 001:256B; 010: 512B; */ | |
2513 | #define PXP2_REG_RQ_WR_MBS1 0x120164 | |
c18487ee YR |
2514 | /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the |
2515 | buffer reaches this number has_payload will be asserted */ | |
2516 | #define PXP2_REG_WR_CDU_MPS 0x1205f0 | |
2517 | /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the | |
2518 | buffer reaches this number has_payload will be asserted */ | |
2519 | #define PXP2_REG_WR_CSDM_MPS 0x1205d0 | |
2520 | /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the | |
2521 | buffer reaches this number has_payload will be asserted */ | |
2522 | #define PXP2_REG_WR_DBG_MPS 0x1205e8 | |
2523 | /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the | |
2524 | buffer reaches this number has_payload will be asserted */ | |
2525 | #define PXP2_REG_WR_DMAE_MPS 0x1205ec | |
33471629 | 2526 | /* [RW 10] if Number of entries in dmae fifo will be higher than this |
a2fbb9ea ET |
2527 | threshold then has_payload indication will be asserted; the default value |
2528 | should be equal to > write MBS size! */ | |
2529 | #define PXP2_REG_WR_DMAE_TH 0x120368 | |
c18487ee YR |
2530 | /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the |
2531 | buffer reaches this number has_payload will be asserted */ | |
2532 | #define PXP2_REG_WR_HC_MPS 0x1205c8 | |
2533 | /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the | |
2534 | buffer reaches this number has_payload will be asserted */ | |
2535 | #define PXP2_REG_WR_QM_MPS 0x1205dc | |
2536 | /* [RW 1] 0 - working in A0 mode; - working in B0 mode */ | |
2537 | #define PXP2_REG_WR_REV_MODE 0x120670 | |
2538 | /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the | |
2539 | buffer reaches this number has_payload will be asserted */ | |
2540 | #define PXP2_REG_WR_SRC_MPS 0x1205e4 | |
2541 | /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the | |
2542 | buffer reaches this number has_payload will be asserted */ | |
2543 | #define PXP2_REG_WR_TM_MPS 0x1205e0 | |
2544 | /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the | |
2545 | buffer reaches this number has_payload will be asserted */ | |
2546 | #define PXP2_REG_WR_TSDM_MPS 0x1205d4 | |
33471629 | 2547 | /* [RW 10] if Number of entries in usdmdp fifo will be higher than this |
f1410647 ET |
2548 | threshold then has_payload indication will be asserted; the default value |
2549 | should be equal to > write MBS size! */ | |
2550 | #define PXP2_REG_WR_USDMDP_TH 0x120348 | |
c18487ee YR |
2551 | /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the |
2552 | buffer reaches this number has_payload will be asserted */ | |
2553 | #define PXP2_REG_WR_USDM_MPS 0x1205cc | |
2554 | /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the | |
2555 | buffer reaches this number has_payload will be asserted */ | |
2556 | #define PXP2_REG_WR_XSDM_MPS 0x1205d8 | |
a2fbb9ea ET |
2557 | /* [R 1] debug only: Indication if PSWHST arbiter is idle */ |
2558 | #define PXP_REG_HST_ARB_IS_IDLE 0x103004 | |
2559 | /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means | |
2560 | this client is waiting for the arbiter. */ | |
2561 | #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008 | |
c18487ee YR |
2562 | /* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit |
2563 | should update accoring to 'hst_discard_doorbells' register when the state | |
2564 | machine is idle */ | |
2565 | #define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0 | |
2566 | /* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1' | |
2567 | means this PSWHST is discarding inputs from this client. Each bit should | |
2568 | update accoring to 'hst_discard_internal_writes' register when the state | |
2569 | machine is idle. */ | |
2570 | #define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c | |
a2fbb9ea ET |
2571 | /* [WB 160] Used for initialization of the inbound interrupts memory */ |
2572 | #define PXP_REG_HST_INBOUND_INT 0x103800 | |
2573 | /* [RW 32] Interrupt mask register #0 read/write */ | |
2574 | #define PXP_REG_PXP_INT_MASK_0 0x103074 | |
2575 | #define PXP_REG_PXP_INT_MASK_1 0x103084 | |
2576 | /* [R 32] Interrupt register #0 read */ | |
2577 | #define PXP_REG_PXP_INT_STS_0 0x103068 | |
2578 | #define PXP_REG_PXP_INT_STS_1 0x103078 | |
2579 | /* [RC 32] Interrupt register #0 read clear */ | |
2580 | #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c | |
2581 | /* [RW 26] Parity mask register #0 read/write */ | |
2582 | #define PXP_REG_PXP_PRTY_MASK 0x103094 | |
f1410647 ET |
2583 | /* [R 26] Parity register #0 read */ |
2584 | #define PXP_REG_PXP_PRTY_STS 0x103088 | |
a2fbb9ea ET |
2585 | /* [RW 4] The activity counter initial increment value sent in the load |
2586 | request */ | |
2587 | #define QM_REG_ACTCTRINITVAL_0 0x168040 | |
2588 | #define QM_REG_ACTCTRINITVAL_1 0x168044 | |
2589 | #define QM_REG_ACTCTRINITVAL_2 0x168048 | |
2590 | #define QM_REG_ACTCTRINITVAL_3 0x16804c | |
2591 | /* [RW 32] The base logical address (in bytes) of each physical queue. The | |
2592 | index I represents the physical queue number. The 12 lsbs are ignore and | |
c18487ee YR |
2593 | considered zero so practically there are only 20 bits in this register; |
2594 | queues 63-0 */ | |
a2fbb9ea | 2595 | #define QM_REG_BASEADDR 0x168900 |
8d9c5f34 EG |
2596 | /* [RW 32] The base logical address (in bytes) of each physical queue. The |
2597 | index I represents the physical queue number. The 12 lsbs are ignore and | |
2598 | considered zero so practically there are only 20 bits in this register; | |
2599 | queues 127-64 */ | |
2600 | #define QM_REG_BASEADDR_EXT_A 0x16e100 | |
a2fbb9ea ET |
2601 | /* [RW 16] The byte credit cost for each task. This value is for both ports */ |
2602 | #define QM_REG_BYTECRDCOST 0x168234 | |
2603 | /* [RW 16] The initial byte credit value for both ports. */ | |
2604 | #define QM_REG_BYTECRDINITVAL 0x168238 | |
2605 | /* [RW 32] A bit per physical queue. If the bit is cleared then the physical | |
c18487ee | 2606 | queue uses port 0 else it uses port 1; queues 31-0 */ |
a2fbb9ea ET |
2607 | #define QM_REG_BYTECRDPORT_LSB 0x168228 |
2608 | /* [RW 32] A bit per physical queue. If the bit is cleared then the physical | |
c18487ee YR |
2609 | queue uses port 0 else it uses port 1; queues 95-64 */ |
2610 | #define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520 | |
2611 | /* [RW 32] A bit per physical queue. If the bit is cleared then the physical | |
2612 | queue uses port 0 else it uses port 1; queues 63-32 */ | |
a2fbb9ea | 2613 | #define QM_REG_BYTECRDPORT_MSB 0x168224 |
c18487ee YR |
2614 | /* [RW 32] A bit per physical queue. If the bit is cleared then the physical |
2615 | queue uses port 0 else it uses port 1; queues 127-96 */ | |
2616 | #define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c | |
a2fbb9ea ET |
2617 | /* [RW 16] The byte credit value that if above the QM is considered almost |
2618 | full */ | |
2619 | #define QM_REG_BYTECREDITAFULLTHR 0x168094 | |
2620 | /* [RW 4] The initial credit for interface */ | |
2621 | #define QM_REG_CMINITCRD_0 0x1680cc | |
2622 | #define QM_REG_CMINITCRD_1 0x1680d0 | |
2623 | #define QM_REG_CMINITCRD_2 0x1680d4 | |
2624 | #define QM_REG_CMINITCRD_3 0x1680d8 | |
2625 | #define QM_REG_CMINITCRD_4 0x1680dc | |
2626 | #define QM_REG_CMINITCRD_5 0x1680e0 | |
2627 | #define QM_REG_CMINITCRD_6 0x1680e4 | |
2628 | #define QM_REG_CMINITCRD_7 0x1680e8 | |
2629 | /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface | |
2630 | is masked */ | |
2631 | #define QM_REG_CMINTEN 0x1680ec | |
2632 | /* [RW 12] A bit vector which indicates which one of the queues are tied to | |
2633 | interface 0 */ | |
2634 | #define QM_REG_CMINTVOQMASK_0 0x1681f4 | |
2635 | #define QM_REG_CMINTVOQMASK_1 0x1681f8 | |
2636 | #define QM_REG_CMINTVOQMASK_2 0x1681fc | |
2637 | #define QM_REG_CMINTVOQMASK_3 0x168200 | |
2638 | #define QM_REG_CMINTVOQMASK_4 0x168204 | |
2639 | #define QM_REG_CMINTVOQMASK_5 0x168208 | |
2640 | #define QM_REG_CMINTVOQMASK_6 0x16820c | |
2641 | #define QM_REG_CMINTVOQMASK_7 0x168210 | |
2642 | /* [RW 20] The number of connections divided by 16 which dictates the size | |
c18487ee | 2643 | of each queue which belongs to even function number. */ |
a2fbb9ea ET |
2644 | #define QM_REG_CONNNUM_0 0x168020 |
2645 | /* [R 6] Keep the fill level of the fifo from write client 4 */ | |
2646 | #define QM_REG_CQM_WRC_FIFOLVL 0x168018 | |
2647 | /* [RW 8] The context regions sent in the CFC load request */ | |
2648 | #define QM_REG_CTXREG_0 0x168030 | |
2649 | #define QM_REG_CTXREG_1 0x168034 | |
2650 | #define QM_REG_CTXREG_2 0x168038 | |
2651 | #define QM_REG_CTXREG_3 0x16803c | |
2652 | /* [RW 12] The VOQ mask used to select the VOQs which needs to be full for | |
2653 | bypass enable */ | |
2654 | #define QM_REG_ENBYPVOQMASK 0x16823c | |
2655 | /* [RW 32] A bit mask per each physical queue. If a bit is set then the | |
c18487ee | 2656 | physical queue uses the byte credit; queues 31-0 */ |
a2fbb9ea ET |
2657 | #define QM_REG_ENBYTECRD_LSB 0x168220 |
2658 | /* [RW 32] A bit mask per each physical queue. If a bit is set then the | |
c18487ee YR |
2659 | physical queue uses the byte credit; queues 95-64 */ |
2660 | #define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518 | |
2661 | /* [RW 32] A bit mask per each physical queue. If a bit is set then the | |
2662 | physical queue uses the byte credit; queues 63-32 */ | |
a2fbb9ea | 2663 | #define QM_REG_ENBYTECRD_MSB 0x16821c |
c18487ee YR |
2664 | /* [RW 32] A bit mask per each physical queue. If a bit is set then the |
2665 | physical queue uses the byte credit; queues 127-96 */ | |
2666 | #define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514 | |
a2fbb9ea ET |
2667 | /* [RW 4] If cleared then the secondary interface will not be served by the |
2668 | RR arbiter */ | |
2669 | #define QM_REG_ENSEC 0x1680f0 | |
c18487ee | 2670 | /* [RW 32] NA */ |
a2fbb9ea | 2671 | #define QM_REG_FUNCNUMSEL_LSB 0x168230 |
c18487ee | 2672 | /* [RW 32] NA */ |
a2fbb9ea ET |
2673 | #define QM_REG_FUNCNUMSEL_MSB 0x16822c |
2674 | /* [RW 32] A mask register to mask the Almost empty signals which will not | |
c18487ee | 2675 | be use for the almost empty indication to the HW block; queues 31:0 */ |
a2fbb9ea ET |
2676 | #define QM_REG_HWAEMPTYMASK_LSB 0x168218 |
2677 | /* [RW 32] A mask register to mask the Almost empty signals which will not | |
c18487ee YR |
2678 | be use for the almost empty indication to the HW block; queues 95-64 */ |
2679 | #define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510 | |
2680 | /* [RW 32] A mask register to mask the Almost empty signals which will not | |
2681 | be use for the almost empty indication to the HW block; queues 63:32 */ | |
a2fbb9ea | 2682 | #define QM_REG_HWAEMPTYMASK_MSB 0x168214 |
c18487ee YR |
2683 | /* [RW 32] A mask register to mask the Almost empty signals which will not |
2684 | be use for the almost empty indication to the HW block; queues 127-96 */ | |
2685 | #define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c | |
a2fbb9ea ET |
2686 | /* [RW 4] The number of outstanding request to CFC */ |
2687 | #define QM_REG_OUTLDREQ 0x168804 | |
2688 | /* [RC 1] A flag to indicate that overflow error occurred in one of the | |
2689 | queues. */ | |
2690 | #define QM_REG_OVFERROR 0x16805c | |
c18487ee | 2691 | /* [RC 7] the Q were the qverflow occurs */ |
a2fbb9ea | 2692 | #define QM_REG_OVFQNUM 0x168058 |
c18487ee | 2693 | /* [R 16] Pause state for physical queues 15-0 */ |
a2fbb9ea | 2694 | #define QM_REG_PAUSESTATE0 0x168410 |
c18487ee | 2695 | /* [R 16] Pause state for physical queues 31-16 */ |
a2fbb9ea | 2696 | #define QM_REG_PAUSESTATE1 0x168414 |
c18487ee YR |
2697 | /* [R 16] Pause state for physical queues 47-32 */ |
2698 | #define QM_REG_PAUSESTATE2 0x16e684 | |
2699 | /* [R 16] Pause state for physical queues 63-48 */ | |
2700 | #define QM_REG_PAUSESTATE3 0x16e688 | |
2701 | /* [R 16] Pause state for physical queues 79-64 */ | |
2702 | #define QM_REG_PAUSESTATE4 0x16e68c | |
2703 | /* [R 16] Pause state for physical queues 95-80 */ | |
2704 | #define QM_REG_PAUSESTATE5 0x16e690 | |
2705 | /* [R 16] Pause state for physical queues 111-96 */ | |
2706 | #define QM_REG_PAUSESTATE6 0x16e694 | |
2707 | /* [R 16] Pause state for physical queues 127-112 */ | |
2708 | #define QM_REG_PAUSESTATE7 0x16e698 | |
a2fbb9ea ET |
2709 | /* [RW 2] The PCI attributes field used in the PCI request. */ |
2710 | #define QM_REG_PCIREQAT 0x168054 | |
2711 | /* [R 16] The byte credit of port 0 */ | |
2712 | #define QM_REG_PORT0BYTECRD 0x168300 | |
2713 | /* [R 16] The byte credit of port 1 */ | |
2714 | #define QM_REG_PORT1BYTECRD 0x168304 | |
c18487ee YR |
2715 | /* [RW 3] pci function number of queues 15-0 */ |
2716 | #define QM_REG_PQ2PCIFUNC_0 0x16e6bc | |
2717 | #define QM_REG_PQ2PCIFUNC_1 0x16e6c0 | |
2718 | #define QM_REG_PQ2PCIFUNC_2 0x16e6c4 | |
2719 | #define QM_REG_PQ2PCIFUNC_3 0x16e6c8 | |
2720 | #define QM_REG_PQ2PCIFUNC_4 0x16e6cc | |
2721 | #define QM_REG_PQ2PCIFUNC_5 0x16e6d0 | |
2722 | #define QM_REG_PQ2PCIFUNC_6 0x16e6d4 | |
2723 | #define QM_REG_PQ2PCIFUNC_7 0x16e6d8 | |
2724 | /* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow: | |
2725 | ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read | |
2726 | bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */ | |
a2fbb9ea | 2727 | #define QM_REG_PTRTBL 0x168a00 |
c18487ee YR |
2728 | /* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow: |
2729 | ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read | |
2730 | bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */ | |
2731 | #define QM_REG_PTRTBL_EXT_A 0x16e200 | |
a2fbb9ea ET |
2732 | /* [RW 2] Interrupt mask register #0 read/write */ |
2733 | #define QM_REG_QM_INT_MASK 0x168444 | |
2734 | /* [R 2] Interrupt register #0 read */ | |
2735 | #define QM_REG_QM_INT_STS 0x168438 | |
c18487ee | 2736 | /* [RW 12] Parity mask register #0 read/write */ |
a2fbb9ea | 2737 | #define QM_REG_QM_PRTY_MASK 0x168454 |
c18487ee | 2738 | /* [R 12] Parity register #0 read */ |
f1410647 | 2739 | #define QM_REG_QM_PRTY_STS 0x168448 |
a2fbb9ea ET |
2740 | /* [R 32] Current queues in pipeline: Queues from 32 to 63 */ |
2741 | #define QM_REG_QSTATUS_HIGH 0x16802c | |
c18487ee YR |
2742 | /* [R 32] Current queues in pipeline: Queues from 96 to 127 */ |
2743 | #define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408 | |
a2fbb9ea ET |
2744 | /* [R 32] Current queues in pipeline: Queues from 0 to 31 */ |
2745 | #define QM_REG_QSTATUS_LOW 0x168028 | |
c18487ee YR |
2746 | /* [R 32] Current queues in pipeline: Queues from 64 to 95 */ |
2747 | #define QM_REG_QSTATUS_LOW_EXT_A 0x16e404 | |
2748 | /* [R 24] The number of tasks queued for each queue; queues 63-0 */ | |
a2fbb9ea | 2749 | #define QM_REG_QTASKCTR_0 0x168308 |
c18487ee YR |
2750 | /* [R 24] The number of tasks queued for each queue; queues 127-64 */ |
2751 | #define QM_REG_QTASKCTR_EXT_A_0 0x16e584 | |
a2fbb9ea ET |
2752 | /* [RW 4] Queue tied to VOQ */ |
2753 | #define QM_REG_QVOQIDX_0 0x1680f4 | |
2754 | #define QM_REG_QVOQIDX_10 0x16811c | |
c18487ee YR |
2755 | #define QM_REG_QVOQIDX_100 0x16e49c |
2756 | #define QM_REG_QVOQIDX_101 0x16e4a0 | |
2757 | #define QM_REG_QVOQIDX_102 0x16e4a4 | |
2758 | #define QM_REG_QVOQIDX_103 0x16e4a8 | |
2759 | #define QM_REG_QVOQIDX_104 0x16e4ac | |
2760 | #define QM_REG_QVOQIDX_105 0x16e4b0 | |
2761 | #define QM_REG_QVOQIDX_106 0x16e4b4 | |
2762 | #define QM_REG_QVOQIDX_107 0x16e4b8 | |
2763 | #define QM_REG_QVOQIDX_108 0x16e4bc | |
2764 | #define QM_REG_QVOQIDX_109 0x16e4c0 | |
2765 | #define QM_REG_QVOQIDX_100 0x16e49c | |
2766 | #define QM_REG_QVOQIDX_101 0x16e4a0 | |
2767 | #define QM_REG_QVOQIDX_102 0x16e4a4 | |
2768 | #define QM_REG_QVOQIDX_103 0x16e4a8 | |
2769 | #define QM_REG_QVOQIDX_104 0x16e4ac | |
2770 | #define QM_REG_QVOQIDX_105 0x16e4b0 | |
2771 | #define QM_REG_QVOQIDX_106 0x16e4b4 | |
2772 | #define QM_REG_QVOQIDX_107 0x16e4b8 | |
2773 | #define QM_REG_QVOQIDX_108 0x16e4bc | |
2774 | #define QM_REG_QVOQIDX_109 0x16e4c0 | |
a2fbb9ea | 2775 | #define QM_REG_QVOQIDX_11 0x168120 |
c18487ee YR |
2776 | #define QM_REG_QVOQIDX_110 0x16e4c4 |
2777 | #define QM_REG_QVOQIDX_111 0x16e4c8 | |
2778 | #define QM_REG_QVOQIDX_112 0x16e4cc | |
2779 | #define QM_REG_QVOQIDX_113 0x16e4d0 | |
2780 | #define QM_REG_QVOQIDX_114 0x16e4d4 | |
2781 | #define QM_REG_QVOQIDX_115 0x16e4d8 | |
2782 | #define QM_REG_QVOQIDX_116 0x16e4dc | |
2783 | #define QM_REG_QVOQIDX_117 0x16e4e0 | |
2784 | #define QM_REG_QVOQIDX_118 0x16e4e4 | |
2785 | #define QM_REG_QVOQIDX_119 0x16e4e8 | |
2786 | #define QM_REG_QVOQIDX_110 0x16e4c4 | |
2787 | #define QM_REG_QVOQIDX_111 0x16e4c8 | |
2788 | #define QM_REG_QVOQIDX_112 0x16e4cc | |
2789 | #define QM_REG_QVOQIDX_113 0x16e4d0 | |
2790 | #define QM_REG_QVOQIDX_114 0x16e4d4 | |
2791 | #define QM_REG_QVOQIDX_115 0x16e4d8 | |
2792 | #define QM_REG_QVOQIDX_116 0x16e4dc | |
2793 | #define QM_REG_QVOQIDX_117 0x16e4e0 | |
2794 | #define QM_REG_QVOQIDX_118 0x16e4e4 | |
2795 | #define QM_REG_QVOQIDX_119 0x16e4e8 | |
a2fbb9ea | 2796 | #define QM_REG_QVOQIDX_12 0x168124 |
c18487ee YR |
2797 | #define QM_REG_QVOQIDX_120 0x16e4ec |
2798 | #define QM_REG_QVOQIDX_121 0x16e4f0 | |
2799 | #define QM_REG_QVOQIDX_122 0x16e4f4 | |
2800 | #define QM_REG_QVOQIDX_123 0x16e4f8 | |
2801 | #define QM_REG_QVOQIDX_124 0x16e4fc | |
2802 | #define QM_REG_QVOQIDX_125 0x16e500 | |
2803 | #define QM_REG_QVOQIDX_126 0x16e504 | |
2804 | #define QM_REG_QVOQIDX_127 0x16e508 | |
2805 | #define QM_REG_QVOQIDX_120 0x16e4ec | |
2806 | #define QM_REG_QVOQIDX_121 0x16e4f0 | |
2807 | #define QM_REG_QVOQIDX_122 0x16e4f4 | |
2808 | #define QM_REG_QVOQIDX_123 0x16e4f8 | |
2809 | #define QM_REG_QVOQIDX_124 0x16e4fc | |
2810 | #define QM_REG_QVOQIDX_125 0x16e500 | |
2811 | #define QM_REG_QVOQIDX_126 0x16e504 | |
2812 | #define QM_REG_QVOQIDX_127 0x16e508 | |
a2fbb9ea ET |
2813 | #define QM_REG_QVOQIDX_13 0x168128 |
2814 | #define QM_REG_QVOQIDX_14 0x16812c | |
2815 | #define QM_REG_QVOQIDX_15 0x168130 | |
2816 | #define QM_REG_QVOQIDX_16 0x168134 | |
2817 | #define QM_REG_QVOQIDX_17 0x168138 | |
2818 | #define QM_REG_QVOQIDX_21 0x168148 | |
c18487ee YR |
2819 | #define QM_REG_QVOQIDX_22 0x16814c |
2820 | #define QM_REG_QVOQIDX_23 0x168150 | |
2821 | #define QM_REG_QVOQIDX_24 0x168154 | |
a2fbb9ea | 2822 | #define QM_REG_QVOQIDX_25 0x168158 |
c18487ee YR |
2823 | #define QM_REG_QVOQIDX_26 0x16815c |
2824 | #define QM_REG_QVOQIDX_27 0x168160 | |
2825 | #define QM_REG_QVOQIDX_28 0x168164 | |
a2fbb9ea | 2826 | #define QM_REG_QVOQIDX_29 0x168168 |
c18487ee YR |
2827 | #define QM_REG_QVOQIDX_30 0x16816c |
2828 | #define QM_REG_QVOQIDX_31 0x168170 | |
a2fbb9ea ET |
2829 | #define QM_REG_QVOQIDX_32 0x168174 |
2830 | #define QM_REG_QVOQIDX_33 0x168178 | |
2831 | #define QM_REG_QVOQIDX_34 0x16817c | |
2832 | #define QM_REG_QVOQIDX_35 0x168180 | |
2833 | #define QM_REG_QVOQIDX_36 0x168184 | |
2834 | #define QM_REG_QVOQIDX_37 0x168188 | |
2835 | #define QM_REG_QVOQIDX_38 0x16818c | |
2836 | #define QM_REG_QVOQIDX_39 0x168190 | |
2837 | #define QM_REG_QVOQIDX_40 0x168194 | |
2838 | #define QM_REG_QVOQIDX_41 0x168198 | |
2839 | #define QM_REG_QVOQIDX_42 0x16819c | |
2840 | #define QM_REG_QVOQIDX_43 0x1681a0 | |
2841 | #define QM_REG_QVOQIDX_44 0x1681a4 | |
2842 | #define QM_REG_QVOQIDX_45 0x1681a8 | |
2843 | #define QM_REG_QVOQIDX_46 0x1681ac | |
2844 | #define QM_REG_QVOQIDX_47 0x1681b0 | |
2845 | #define QM_REG_QVOQIDX_48 0x1681b4 | |
2846 | #define QM_REG_QVOQIDX_49 0x1681b8 | |
2847 | #define QM_REG_QVOQIDX_5 0x168108 | |
2848 | #define QM_REG_QVOQIDX_50 0x1681bc | |
2849 | #define QM_REG_QVOQIDX_51 0x1681c0 | |
2850 | #define QM_REG_QVOQIDX_52 0x1681c4 | |
2851 | #define QM_REG_QVOQIDX_53 0x1681c8 | |
2852 | #define QM_REG_QVOQIDX_54 0x1681cc | |
2853 | #define QM_REG_QVOQIDX_55 0x1681d0 | |
2854 | #define QM_REG_QVOQIDX_56 0x1681d4 | |
2855 | #define QM_REG_QVOQIDX_57 0x1681d8 | |
2856 | #define QM_REG_QVOQIDX_58 0x1681dc | |
2857 | #define QM_REG_QVOQIDX_59 0x1681e0 | |
2858 | #define QM_REG_QVOQIDX_50 0x1681bc | |
2859 | #define QM_REG_QVOQIDX_51 0x1681c0 | |
2860 | #define QM_REG_QVOQIDX_52 0x1681c4 | |
2861 | #define QM_REG_QVOQIDX_53 0x1681c8 | |
2862 | #define QM_REG_QVOQIDX_54 0x1681cc | |
2863 | #define QM_REG_QVOQIDX_55 0x1681d0 | |
2864 | #define QM_REG_QVOQIDX_56 0x1681d4 | |
2865 | #define QM_REG_QVOQIDX_57 0x1681d8 | |
2866 | #define QM_REG_QVOQIDX_58 0x1681dc | |
2867 | #define QM_REG_QVOQIDX_59 0x1681e0 | |
2868 | #define QM_REG_QVOQIDX_6 0x16810c | |
2869 | #define QM_REG_QVOQIDX_60 0x1681e4 | |
2870 | #define QM_REG_QVOQIDX_61 0x1681e8 | |
2871 | #define QM_REG_QVOQIDX_62 0x1681ec | |
2872 | #define QM_REG_QVOQIDX_63 0x1681f0 | |
c18487ee YR |
2873 | #define QM_REG_QVOQIDX_64 0x16e40c |
2874 | #define QM_REG_QVOQIDX_65 0x16e410 | |
2875 | #define QM_REG_QVOQIDX_66 0x16e414 | |
2876 | #define QM_REG_QVOQIDX_67 0x16e418 | |
2877 | #define QM_REG_QVOQIDX_68 0x16e41c | |
2878 | #define QM_REG_QVOQIDX_69 0x16e420 | |
a2fbb9ea ET |
2879 | #define QM_REG_QVOQIDX_60 0x1681e4 |
2880 | #define QM_REG_QVOQIDX_61 0x1681e8 | |
2881 | #define QM_REG_QVOQIDX_62 0x1681ec | |
2882 | #define QM_REG_QVOQIDX_63 0x1681f0 | |
c18487ee YR |
2883 | #define QM_REG_QVOQIDX_64 0x16e40c |
2884 | #define QM_REG_QVOQIDX_65 0x16e410 | |
2885 | #define QM_REG_QVOQIDX_69 0x16e420 | |
a2fbb9ea | 2886 | #define QM_REG_QVOQIDX_7 0x168110 |
c18487ee YR |
2887 | #define QM_REG_QVOQIDX_70 0x16e424 |
2888 | #define QM_REG_QVOQIDX_71 0x16e428 | |
2889 | #define QM_REG_QVOQIDX_72 0x16e42c | |
2890 | #define QM_REG_QVOQIDX_73 0x16e430 | |
2891 | #define QM_REG_QVOQIDX_74 0x16e434 | |
2892 | #define QM_REG_QVOQIDX_75 0x16e438 | |
2893 | #define QM_REG_QVOQIDX_76 0x16e43c | |
2894 | #define QM_REG_QVOQIDX_77 0x16e440 | |
2895 | #define QM_REG_QVOQIDX_78 0x16e444 | |
2896 | #define QM_REG_QVOQIDX_79 0x16e448 | |
2897 | #define QM_REG_QVOQIDX_70 0x16e424 | |
2898 | #define QM_REG_QVOQIDX_71 0x16e428 | |
2899 | #define QM_REG_QVOQIDX_72 0x16e42c | |
2900 | #define QM_REG_QVOQIDX_73 0x16e430 | |
2901 | #define QM_REG_QVOQIDX_74 0x16e434 | |
2902 | #define QM_REG_QVOQIDX_75 0x16e438 | |
2903 | #define QM_REG_QVOQIDX_76 0x16e43c | |
2904 | #define QM_REG_QVOQIDX_77 0x16e440 | |
2905 | #define QM_REG_QVOQIDX_78 0x16e444 | |
2906 | #define QM_REG_QVOQIDX_79 0x16e448 | |
a2fbb9ea | 2907 | #define QM_REG_QVOQIDX_8 0x168114 |
c18487ee YR |
2908 | #define QM_REG_QVOQIDX_80 0x16e44c |
2909 | #define QM_REG_QVOQIDX_81 0x16e450 | |
2910 | #define QM_REG_QVOQIDX_82 0x16e454 | |
2911 | #define QM_REG_QVOQIDX_83 0x16e458 | |
2912 | #define QM_REG_QVOQIDX_84 0x16e45c | |
2913 | #define QM_REG_QVOQIDX_85 0x16e460 | |
2914 | #define QM_REG_QVOQIDX_86 0x16e464 | |
2915 | #define QM_REG_QVOQIDX_87 0x16e468 | |
2916 | #define QM_REG_QVOQIDX_88 0x16e46c | |
2917 | #define QM_REG_QVOQIDX_89 0x16e470 | |
2918 | #define QM_REG_QVOQIDX_80 0x16e44c | |
2919 | #define QM_REG_QVOQIDX_81 0x16e450 | |
2920 | #define QM_REG_QVOQIDX_85 0x16e460 | |
2921 | #define QM_REG_QVOQIDX_86 0x16e464 | |
2922 | #define QM_REG_QVOQIDX_87 0x16e468 | |
2923 | #define QM_REG_QVOQIDX_88 0x16e46c | |
2924 | #define QM_REG_QVOQIDX_89 0x16e470 | |
a2fbb9ea | 2925 | #define QM_REG_QVOQIDX_9 0x168118 |
c18487ee YR |
2926 | #define QM_REG_QVOQIDX_90 0x16e474 |
2927 | #define QM_REG_QVOQIDX_91 0x16e478 | |
2928 | #define QM_REG_QVOQIDX_92 0x16e47c | |
2929 | #define QM_REG_QVOQIDX_93 0x16e480 | |
2930 | #define QM_REG_QVOQIDX_94 0x16e484 | |
2931 | #define QM_REG_QVOQIDX_95 0x16e488 | |
2932 | #define QM_REG_QVOQIDX_96 0x16e48c | |
2933 | #define QM_REG_QVOQIDX_97 0x16e490 | |
2934 | #define QM_REG_QVOQIDX_98 0x16e494 | |
2935 | #define QM_REG_QVOQIDX_99 0x16e498 | |
2936 | #define QM_REG_QVOQIDX_90 0x16e474 | |
2937 | #define QM_REG_QVOQIDX_91 0x16e478 | |
2938 | #define QM_REG_QVOQIDX_92 0x16e47c | |
2939 | #define QM_REG_QVOQIDX_93 0x16e480 | |
2940 | #define QM_REG_QVOQIDX_94 0x16e484 | |
2941 | #define QM_REG_QVOQIDX_95 0x16e488 | |
2942 | #define QM_REG_QVOQIDX_96 0x16e48c | |
2943 | #define QM_REG_QVOQIDX_97 0x16e490 | |
2944 | #define QM_REG_QVOQIDX_98 0x16e494 | |
2945 | #define QM_REG_QVOQIDX_99 0x16e498 | |
a2fbb9ea ET |
2946 | /* [RW 1] Initialization bit command */ |
2947 | #define QM_REG_SOFT_RESET 0x168428 | |
2948 | /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */ | |
2949 | #define QM_REG_TASKCRDCOST_0 0x16809c | |
2950 | #define QM_REG_TASKCRDCOST_1 0x1680a0 | |
2951 | #define QM_REG_TASKCRDCOST_10 0x1680c4 | |
2952 | #define QM_REG_TASKCRDCOST_11 0x1680c8 | |
2953 | #define QM_REG_TASKCRDCOST_2 0x1680a4 | |
2954 | #define QM_REG_TASKCRDCOST_4 0x1680ac | |
2955 | #define QM_REG_TASKCRDCOST_5 0x1680b0 | |
2956 | /* [R 6] Keep the fill level of the fifo from write client 3 */ | |
2957 | #define QM_REG_TQM_WRC_FIFOLVL 0x168010 | |
2958 | /* [R 6] Keep the fill level of the fifo from write client 2 */ | |
2959 | #define QM_REG_UQM_WRC_FIFOLVL 0x168008 | |
2960 | /* [RC 32] Credit update error register */ | |
2961 | #define QM_REG_VOQCRDERRREG 0x168408 | |
2962 | /* [R 16] The credit value for each VOQ */ | |
2963 | #define QM_REG_VOQCREDIT_0 0x1682d0 | |
2964 | #define QM_REG_VOQCREDIT_1 0x1682d4 | |
2965 | #define QM_REG_VOQCREDIT_10 0x1682f8 | |
2966 | #define QM_REG_VOQCREDIT_11 0x1682fc | |
2967 | #define QM_REG_VOQCREDIT_4 0x1682e0 | |
2968 | /* [RW 16] The credit value that if above the QM is considered almost full */ | |
2969 | #define QM_REG_VOQCREDITAFULLTHR 0x168090 | |
2970 | /* [RW 16] The init and maximum credit for each VoQ */ | |
2971 | #define QM_REG_VOQINITCREDIT_0 0x168060 | |
2972 | #define QM_REG_VOQINITCREDIT_1 0x168064 | |
2973 | #define QM_REG_VOQINITCREDIT_10 0x168088 | |
2974 | #define QM_REG_VOQINITCREDIT_11 0x16808c | |
2975 | #define QM_REG_VOQINITCREDIT_2 0x168068 | |
2976 | #define QM_REG_VOQINITCREDIT_4 0x168070 | |
2977 | #define QM_REG_VOQINITCREDIT_5 0x168074 | |
2978 | /* [RW 1] The port of which VOQ belongs */ | |
c18487ee | 2979 | #define QM_REG_VOQPORT_0 0x1682a0 |
a2fbb9ea ET |
2980 | #define QM_REG_VOQPORT_1 0x1682a4 |
2981 | #define QM_REG_VOQPORT_10 0x1682c8 | |
2982 | #define QM_REG_VOQPORT_11 0x1682cc | |
2983 | #define QM_REG_VOQPORT_2 0x1682a8 | |
c18487ee | 2984 | /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ |
a2fbb9ea | 2985 | #define QM_REG_VOQQMASK_0_LSB 0x168240 |
c18487ee YR |
2986 | /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ |
2987 | #define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524 | |
2988 | /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ | |
a2fbb9ea | 2989 | #define QM_REG_VOQQMASK_0_MSB 0x168244 |
c18487ee YR |
2990 | /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ |
2991 | #define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528 | |
2992 | /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ | |
2993 | #define QM_REG_VOQQMASK_10_LSB 0x168290 | |
2994 | /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ | |
2995 | #define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574 | |
2996 | /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ | |
2997 | #define QM_REG_VOQQMASK_10_MSB 0x168294 | |
2998 | /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ | |
2999 | #define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578 | |
3000 | /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ | |
3001 | #define QM_REG_VOQQMASK_11_LSB 0x168298 | |
3002 | /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ | |
3003 | #define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c | |
3004 | /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ | |
3005 | #define QM_REG_VOQQMASK_11_MSB 0x16829c | |
3006 | /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ | |
3007 | #define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580 | |
3008 | /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ | |
3009 | #define QM_REG_VOQQMASK_1_LSB 0x168248 | |
3010 | /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ | |
3011 | #define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c | |
3012 | /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ | |
a2fbb9ea | 3013 | #define QM_REG_VOQQMASK_1_MSB 0x16824c |
c18487ee YR |
3014 | /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ |
3015 | #define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530 | |
3016 | /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ | |
a2fbb9ea | 3017 | #define QM_REG_VOQQMASK_2_LSB 0x168250 |
c18487ee YR |
3018 | /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ |
3019 | #define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534 | |
3020 | /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ | |
a2fbb9ea | 3021 | #define QM_REG_VOQQMASK_2_MSB 0x168254 |
c18487ee YR |
3022 | /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ |
3023 | #define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538 | |
3024 | /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ | |
a2fbb9ea | 3025 | #define QM_REG_VOQQMASK_3_LSB 0x168258 |
c18487ee YR |
3026 | /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ |
3027 | #define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c | |
3028 | /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ | |
3029 | #define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540 | |
3030 | /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ | |
a2fbb9ea | 3031 | #define QM_REG_VOQQMASK_4_LSB 0x168260 |
c18487ee YR |
3032 | /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ |
3033 | #define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544 | |
3034 | /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ | |
a2fbb9ea | 3035 | #define QM_REG_VOQQMASK_4_MSB 0x168264 |
c18487ee YR |
3036 | /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ |
3037 | #define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548 | |
3038 | /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ | |
a2fbb9ea | 3039 | #define QM_REG_VOQQMASK_5_LSB 0x168268 |
c18487ee YR |
3040 | /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ |
3041 | #define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c | |
3042 | /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ | |
a2fbb9ea | 3043 | #define QM_REG_VOQQMASK_5_MSB 0x16826c |
c18487ee YR |
3044 | /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ |
3045 | #define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550 | |
3046 | /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ | |
a2fbb9ea | 3047 | #define QM_REG_VOQQMASK_6_LSB 0x168270 |
c18487ee YR |
3048 | /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ |
3049 | #define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554 | |
3050 | /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ | |
a2fbb9ea | 3051 | #define QM_REG_VOQQMASK_6_MSB 0x168274 |
c18487ee YR |
3052 | /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ |
3053 | #define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558 | |
3054 | /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ | |
a2fbb9ea | 3055 | #define QM_REG_VOQQMASK_7_LSB 0x168278 |
c18487ee YR |
3056 | /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ |
3057 | #define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c | |
3058 | /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ | |
a2fbb9ea | 3059 | #define QM_REG_VOQQMASK_7_MSB 0x16827c |
c18487ee YR |
3060 | /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ |
3061 | #define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560 | |
3062 | /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ | |
a2fbb9ea | 3063 | #define QM_REG_VOQQMASK_8_LSB 0x168280 |
c18487ee YR |
3064 | /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ |
3065 | #define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564 | |
3066 | /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ | |
a2fbb9ea | 3067 | #define QM_REG_VOQQMASK_8_MSB 0x168284 |
c18487ee YR |
3068 | /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ |
3069 | #define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568 | |
3070 | /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ | |
a2fbb9ea | 3071 | #define QM_REG_VOQQMASK_9_LSB 0x168288 |
c18487ee YR |
3072 | /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ |
3073 | #define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c | |
3074 | /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ | |
3075 | #define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570 | |
a2fbb9ea ET |
3076 | /* [RW 32] Wrr weights */ |
3077 | #define QM_REG_WRRWEIGHTS_0 0x16880c | |
3078 | #define QM_REG_WRRWEIGHTS_1 0x168810 | |
3079 | #define QM_REG_WRRWEIGHTS_10 0x168814 | |
3080 | #define QM_REG_WRRWEIGHTS_10_SIZE 1 | |
3081 | /* [RW 32] Wrr weights */ | |
3082 | #define QM_REG_WRRWEIGHTS_11 0x168818 | |
3083 | #define QM_REG_WRRWEIGHTS_11_SIZE 1 | |
3084 | /* [RW 32] Wrr weights */ | |
3085 | #define QM_REG_WRRWEIGHTS_12 0x16881c | |
3086 | #define QM_REG_WRRWEIGHTS_12_SIZE 1 | |
3087 | /* [RW 32] Wrr weights */ | |
3088 | #define QM_REG_WRRWEIGHTS_13 0x168820 | |
3089 | #define QM_REG_WRRWEIGHTS_13_SIZE 1 | |
3090 | /* [RW 32] Wrr weights */ | |
3091 | #define QM_REG_WRRWEIGHTS_14 0x168824 | |
3092 | #define QM_REG_WRRWEIGHTS_14_SIZE 1 | |
3093 | /* [RW 32] Wrr weights */ | |
3094 | #define QM_REG_WRRWEIGHTS_15 0x168828 | |
3095 | #define QM_REG_WRRWEIGHTS_15_SIZE 1 | |
3096 | /* [RW 32] Wrr weights */ | |
c18487ee YR |
3097 | #define QM_REG_WRRWEIGHTS_16 0x16e000 |
3098 | #define QM_REG_WRRWEIGHTS_16_SIZE 1 | |
3099 | /* [RW 32] Wrr weights */ | |
3100 | #define QM_REG_WRRWEIGHTS_17 0x16e004 | |
3101 | #define QM_REG_WRRWEIGHTS_17_SIZE 1 | |
3102 | /* [RW 32] Wrr weights */ | |
3103 | #define QM_REG_WRRWEIGHTS_18 0x16e008 | |
3104 | #define QM_REG_WRRWEIGHTS_18_SIZE 1 | |
3105 | /* [RW 32] Wrr weights */ | |
3106 | #define QM_REG_WRRWEIGHTS_19 0x16e00c | |
3107 | #define QM_REG_WRRWEIGHTS_19_SIZE 1 | |
3108 | /* [RW 32] Wrr weights */ | |
a2fbb9ea ET |
3109 | #define QM_REG_WRRWEIGHTS_10 0x168814 |
3110 | #define QM_REG_WRRWEIGHTS_11 0x168818 | |
3111 | #define QM_REG_WRRWEIGHTS_12 0x16881c | |
3112 | #define QM_REG_WRRWEIGHTS_13 0x168820 | |
3113 | #define QM_REG_WRRWEIGHTS_14 0x168824 | |
3114 | #define QM_REG_WRRWEIGHTS_15 0x168828 | |
c18487ee YR |
3115 | #define QM_REG_WRRWEIGHTS_16 0x16e000 |
3116 | #define QM_REG_WRRWEIGHTS_17 0x16e004 | |
3117 | #define QM_REG_WRRWEIGHTS_18 0x16e008 | |
3118 | #define QM_REG_WRRWEIGHTS_19 0x16e00c | |
a2fbb9ea | 3119 | #define QM_REG_WRRWEIGHTS_2 0x16882c |
c18487ee YR |
3120 | #define QM_REG_WRRWEIGHTS_20 0x16e010 |
3121 | #define QM_REG_WRRWEIGHTS_20_SIZE 1 | |
3122 | /* [RW 32] Wrr weights */ | |
3123 | #define QM_REG_WRRWEIGHTS_21 0x16e014 | |
3124 | #define QM_REG_WRRWEIGHTS_21_SIZE 1 | |
3125 | /* [RW 32] Wrr weights */ | |
3126 | #define QM_REG_WRRWEIGHTS_22 0x16e018 | |
3127 | #define QM_REG_WRRWEIGHTS_22_SIZE 1 | |
3128 | /* [RW 32] Wrr weights */ | |
3129 | #define QM_REG_WRRWEIGHTS_23 0x16e01c | |
3130 | #define QM_REG_WRRWEIGHTS_23_SIZE 1 | |
3131 | /* [RW 32] Wrr weights */ | |
3132 | #define QM_REG_WRRWEIGHTS_24 0x16e020 | |
3133 | #define QM_REG_WRRWEIGHTS_24_SIZE 1 | |
3134 | /* [RW 32] Wrr weights */ | |
3135 | #define QM_REG_WRRWEIGHTS_25 0x16e024 | |
3136 | #define QM_REG_WRRWEIGHTS_25_SIZE 1 | |
3137 | /* [RW 32] Wrr weights */ | |
3138 | #define QM_REG_WRRWEIGHTS_26 0x16e028 | |
3139 | #define QM_REG_WRRWEIGHTS_26_SIZE 1 | |
3140 | /* [RW 32] Wrr weights */ | |
3141 | #define QM_REG_WRRWEIGHTS_27 0x16e02c | |
3142 | #define QM_REG_WRRWEIGHTS_27_SIZE 1 | |
3143 | /* [RW 32] Wrr weights */ | |
3144 | #define QM_REG_WRRWEIGHTS_28 0x16e030 | |
3145 | #define QM_REG_WRRWEIGHTS_28_SIZE 1 | |
3146 | /* [RW 32] Wrr weights */ | |
3147 | #define QM_REG_WRRWEIGHTS_29 0x16e034 | |
3148 | #define QM_REG_WRRWEIGHTS_29_SIZE 1 | |
3149 | /* [RW 32] Wrr weights */ | |
3150 | #define QM_REG_WRRWEIGHTS_20 0x16e010 | |
3151 | #define QM_REG_WRRWEIGHTS_21 0x16e014 | |
3152 | #define QM_REG_WRRWEIGHTS_22 0x16e018 | |
3153 | #define QM_REG_WRRWEIGHTS_23 0x16e01c | |
3154 | #define QM_REG_WRRWEIGHTS_24 0x16e020 | |
3155 | #define QM_REG_WRRWEIGHTS_25 0x16e024 | |
3156 | #define QM_REG_WRRWEIGHTS_26 0x16e028 | |
3157 | #define QM_REG_WRRWEIGHTS_27 0x16e02c | |
3158 | #define QM_REG_WRRWEIGHTS_28 0x16e030 | |
3159 | #define QM_REG_WRRWEIGHTS_29 0x16e034 | |
a2fbb9ea | 3160 | #define QM_REG_WRRWEIGHTS_3 0x168830 |
c18487ee YR |
3161 | #define QM_REG_WRRWEIGHTS_30 0x16e038 |
3162 | #define QM_REG_WRRWEIGHTS_30_SIZE 1 | |
3163 | /* [RW 32] Wrr weights */ | |
3164 | #define QM_REG_WRRWEIGHTS_31 0x16e03c | |
3165 | #define QM_REG_WRRWEIGHTS_31_SIZE 1 | |
3166 | /* [RW 32] Wrr weights */ | |
3167 | #define QM_REG_WRRWEIGHTS_30 0x16e038 | |
3168 | #define QM_REG_WRRWEIGHTS_31 0x16e03c | |
a2fbb9ea ET |
3169 | #define QM_REG_WRRWEIGHTS_4 0x168834 |
3170 | #define QM_REG_WRRWEIGHTS_5 0x168838 | |
3171 | #define QM_REG_WRRWEIGHTS_6 0x16883c | |
3172 | #define QM_REG_WRRWEIGHTS_7 0x168840 | |
3173 | #define QM_REG_WRRWEIGHTS_8 0x168844 | |
3174 | #define QM_REG_WRRWEIGHTS_9 0x168848 | |
3175 | /* [R 6] Keep the fill level of the fifo from write client 1 */ | |
3176 | #define QM_REG_XQM_WRC_FIFOLVL 0x168000 | |
c18487ee YR |
3177 | #define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR (0x1<<0) |
3178 | #define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR_SIZE 0 | |
3179 | #define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) | |
3180 | #define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 | |
3181 | #define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) | |
3182 | #define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 | |
3183 | #define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) | |
3184 | #define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 | |
3185 | #define CCM_CCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0) | |
3186 | #define CCM_CCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0 | |
3187 | #define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) | |
3188 | #define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 | |
3189 | #define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) | |
3190 | #define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 | |
3191 | #define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) | |
3192 | #define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 | |
3193 | #define CDU_CDU_INT_STS_REG_ADDRESS_ERROR (0x1<<0) | |
3194 | #define CDU_CDU_INT_STS_REG_ADDRESS_ERROR_SIZE 0 | |
3195 | #define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) | |
3196 | #define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 | |
3197 | #define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) | |
3198 | #define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 | |
3199 | #define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) | |
3200 | #define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 | |
3201 | #define CFC_CFC_INT_STS_REG_ADDRESS_ERROR (0x1<<0) | |
3202 | #define CFC_CFC_INT_STS_REG_ADDRESS_ERROR_SIZE 0 | |
3203 | #define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) | |
3204 | #define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 | |
3205 | #define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) | |
3206 | #define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 | |
3207 | #define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) | |
3208 | #define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 | |
3209 | #define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) | |
3210 | #define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 | |
3211 | #define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) | |
3212 | #define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 | |
3213 | #define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) | |
3214 | #define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 | |
3215 | #define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) | |
3216 | #define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 | |
3217 | #define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) | |
3218 | #define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 | |
3219 | #define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) | |
3220 | #define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 | |
3221 | #define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) | |
3222 | #define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 | |
3223 | #define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) | |
3224 | #define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 | |
3225 | #define DBG_DBG_INT_STS_REG_ADDRESS_ERROR (0x1<<0) | |
3226 | #define DBG_DBG_INT_STS_REG_ADDRESS_ERROR_SIZE 0 | |
3227 | #define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) | |
3228 | #define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 | |
3229 | #define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) | |
3230 | #define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 | |
3231 | #define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) | |
3232 | #define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 | |
3233 | #define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR (0x1<<0) | |
3234 | #define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR_SIZE 0 | |
3235 | #define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) | |
3236 | #define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 | |
3237 | #define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) | |
3238 | #define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 | |
3239 | #define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) | |
3240 | #define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 | |
a2fbb9ea ET |
3241 | #define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR (0x1<<0) |
3242 | #define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR_SIZE 0 | |
3243 | #define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) | |
3244 | #define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 | |
3245 | #define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) | |
3246 | #define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 | |
3247 | #define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) | |
3248 | #define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 | |
c18487ee YR |
3249 | #define HC_HC_INT_STS_REG_ADDRESS_ERROR (0x1<<0) |
3250 | #define HC_HC_INT_STS_REG_ADDRESS_ERROR_SIZE 0 | |
3251 | #define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) | |
3252 | #define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 | |
3253 | #define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) | |
3254 | #define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 | |
3255 | #define HC_HC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) | |
3256 | #define HC_HC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 | |
3257 | #define MISC_MISC_INT_STS_REG_ADDRESS_ERROR (0x1<<0) | |
3258 | #define MISC_MISC_INT_STS_REG_ADDRESS_ERROR_SIZE 0 | |
3259 | #define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) | |
3260 | #define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 | |
3261 | #define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) | |
3262 | #define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 | |
3263 | #define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) | |
3264 | #define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 | |
a2fbb9ea ET |
3265 | #define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) |
3266 | #define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 | |
3267 | #define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) | |
3268 | #define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 | |
3269 | #define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) | |
3270 | #define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 | |
3271 | #define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) | |
3272 | #define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 | |
c18487ee YR |
3273 | #define PBF_PBF_INT_STS_REG_ADDRESS_ERROR (0x1<<0) |
3274 | #define PBF_PBF_INT_STS_REG_ADDRESS_ERROR_SIZE 0 | |
3275 | #define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) | |
3276 | #define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 | |
3277 | #define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) | |
3278 | #define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 | |
3279 | #define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) | |
3280 | #define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 | |
3281 | #define PB_PB_INT_STS_REG_ADDRESS_ERROR (0x1<<0) | |
3282 | #define PB_PB_INT_STS_REG_ADDRESS_ERROR_SIZE 0 | |
3283 | #define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) | |
3284 | #define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 | |
3285 | #define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) | |
3286 | #define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 | |
3287 | #define PB_PB_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) | |
3288 | #define PB_PB_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 | |
3289 | #define PRS_PRS_INT_STS_REG_ADDRESS_ERROR (0x1<<0) | |
3290 | #define PRS_PRS_INT_STS_REG_ADDRESS_ERROR_SIZE 0 | |
3291 | #define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) | |
3292 | #define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 | |
3293 | #define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) | |
3294 | #define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 | |
3295 | #define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) | |
3296 | #define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 | |
3297 | #define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) | |
3298 | #define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 | |
3299 | #define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) | |
3300 | #define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 | |
3301 | #define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) | |
3302 | #define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 | |
3303 | #define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) | |
3304 | #define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 | |
3305 | #define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) | |
3306 | #define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 | |
3307 | #define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) | |
3308 | #define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 | |
3309 | #define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) | |
3310 | #define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 | |
3311 | #define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) | |
3312 | #define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 | |
3313 | #define QM_QM_INT_STS_REG_ADDRESS_ERROR (0x1<<0) | |
3314 | #define QM_QM_INT_STS_REG_ADDRESS_ERROR_SIZE 0 | |
3315 | #define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) | |
3316 | #define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 | |
3317 | #define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) | |
3318 | #define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 | |
3319 | #define QM_QM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) | |
3320 | #define QM_QM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 | |
3321 | #define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR (0x1<<0) | |
3322 | #define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR_SIZE 0 | |
3323 | #define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) | |
3324 | #define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 | |
3325 | #define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) | |
3326 | #define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 | |
3327 | #define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) | |
3328 | #define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 | |
3329 | #define SRC_SRC_INT_STS_REG_ADDRESS_ERROR (0x1<<0) | |
3330 | #define SRC_SRC_INT_STS_REG_ADDRESS_ERROR_SIZE 0 | |
3331 | #define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) | |
3332 | #define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 | |
3333 | #define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) | |
3334 | #define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 | |
3335 | #define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) | |
3336 | #define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 | |
a2fbb9ea ET |
3337 | #define TCM_TCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0) |
3338 | #define TCM_TCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0 | |
3339 | #define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) | |
3340 | #define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 | |
3341 | #define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) | |
3342 | #define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 | |
3343 | #define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) | |
3344 | #define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 | |
c18487ee YR |
3345 | #define TM_TM_INT_STS_REG_ADDRESS_ERROR (0x1<<0) |
3346 | #define TM_TM_INT_STS_REG_ADDRESS_ERROR_SIZE 0 | |
3347 | #define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) | |
3348 | #define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 | |
3349 | #define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) | |
3350 | #define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 | |
3351 | #define TM_TM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) | |
3352 | #define TM_TM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 | |
3353 | #define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) | |
3354 | #define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 | |
3355 | #define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) | |
3356 | #define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 | |
3357 | #define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) | |
3358 | #define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 | |
3359 | #define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) | |
3360 | #define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 | |
3361 | #define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) | |
3362 | #define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 | |
3363 | #define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) | |
3364 | #define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 | |
3365 | #define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) | |
3366 | #define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 | |
3367 | #define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) | |
3368 | #define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 | |
3369 | #define UCM_UCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0) | |
3370 | #define UCM_UCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0 | |
3371 | #define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) | |
3372 | #define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 | |
3373 | #define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) | |
3374 | #define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 | |
3375 | #define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) | |
3376 | #define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 | |
3377 | #define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) | |
3378 | #define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 | |
3379 | #define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) | |
3380 | #define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 | |
3381 | #define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) | |
3382 | #define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 | |
3383 | #define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) | |
3384 | #define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 | |
3385 | #define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) | |
3386 | #define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 | |
3387 | #define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) | |
3388 | #define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 | |
3389 | #define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) | |
3390 | #define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 | |
3391 | #define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) | |
3392 | #define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 | |
3393 | #define XCM_XCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0) | |
3394 | #define XCM_XCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0 | |
3395 | #define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) | |
3396 | #define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 | |
3397 | #define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) | |
3398 | #define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 | |
3399 | #define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) | |
3400 | #define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 | |
3401 | #define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) | |
3402 | #define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 | |
3403 | #define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) | |
3404 | #define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 | |
3405 | #define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) | |
3406 | #define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 | |
3407 | #define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) | |
3408 | #define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 | |
3409 | #define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) | |
3410 | #define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 | |
3411 | #define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) | |
3412 | #define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 | |
3413 | #define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) | |
3414 | #define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 | |
3415 | #define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) | |
3416 | #define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 | |
a2fbb9ea ET |
3417 | #define CFC_DEBUG1_REG_WRITE_AC (0x1<<4) |
3418 | #define CFC_DEBUG1_REG_WRITE_AC_SIZE 4 | |
33471629 | 3419 | /* [R 1] debug only: This bit indicates whether indicates that external |
a2fbb9ea ET |
3420 | buffer was wrapped (oldest data was thrown); Relevant only when |
3421 | ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=1 (wrap); */ | |
3422 | #define DBG_REG_WRAP_ON_EXT_BUFFER 0xc124 | |
3423 | #define DBG_REG_WRAP_ON_EXT_BUFFER_SIZE 1 | |
33471629 | 3424 | /* [R 1] debug only: This bit indicates whether the internal buffer was |
a2fbb9ea ET |
3425 | wrapped (oldest data was thrown) Relevant only when |
3426 | ~dbg_registers_debug_target=0 (internal buffer) */ | |
3427 | #define DBG_REG_WRAP_ON_INT_BUFFER 0xc128 | |
3428 | #define DBG_REG_WRAP_ON_INT_BUFFER_SIZE 1 | |
c18487ee YR |
3429 | #define QM_QM_PRTY_STS_REG_WRBUFF (0x1<<8) |
3430 | #define QM_QM_PRTY_STS_REG_WRBUFF_SIZE 8 | |
3431 | #define QM_QM_PRTY_STS_CLR_REG_WRBUFF (0x1<<8) | |
3432 | #define QM_QM_PRTY_STS_CLR_REG_WRBUFF_SIZE 8 | |
3433 | #define QM_QM_PRTY_STS_WR_REG_WRBUFF (0x1<<8) | |
3434 | #define QM_QM_PRTY_STS_WR_REG_WRBUFF_SIZE 8 | |
3435 | #define QM_QM_PRTY_MASK_REG_WRBUFF (0x1<<8) | |
3436 | #define QM_QM_PRTY_MASK_REG_WRBUFF_SIZE 8 | |
a2fbb9ea ET |
3437 | /* [RW 32] Wrr weights */ |
3438 | #define QM_REG_WRRWEIGHTS_0 0x16880c | |
3439 | #define QM_REG_WRRWEIGHTS_0_SIZE 1 | |
3440 | /* [RW 32] Wrr weights */ | |
3441 | #define QM_REG_WRRWEIGHTS_1 0x168810 | |
3442 | #define QM_REG_WRRWEIGHTS_1_SIZE 1 | |
3443 | /* [RW 32] Wrr weights */ | |
3444 | #define QM_REG_WRRWEIGHTS_10 0x168814 | |
3445 | #define QM_REG_WRRWEIGHTS_10_SIZE 1 | |
3446 | /* [RW 32] Wrr weights */ | |
3447 | #define QM_REG_WRRWEIGHTS_11 0x168818 | |
3448 | #define QM_REG_WRRWEIGHTS_11_SIZE 1 | |
3449 | /* [RW 32] Wrr weights */ | |
3450 | #define QM_REG_WRRWEIGHTS_12 0x16881c | |
3451 | #define QM_REG_WRRWEIGHTS_12_SIZE 1 | |
3452 | /* [RW 32] Wrr weights */ | |
3453 | #define QM_REG_WRRWEIGHTS_13 0x168820 | |
3454 | #define QM_REG_WRRWEIGHTS_13_SIZE 1 | |
3455 | /* [RW 32] Wrr weights */ | |
3456 | #define QM_REG_WRRWEIGHTS_14 0x168824 | |
3457 | #define QM_REG_WRRWEIGHTS_14_SIZE 1 | |
3458 | /* [RW 32] Wrr weights */ | |
3459 | #define QM_REG_WRRWEIGHTS_15 0x168828 | |
3460 | #define QM_REG_WRRWEIGHTS_15_SIZE 1 | |
3461 | /* [RW 32] Wrr weights */ | |
3462 | #define QM_REG_WRRWEIGHTS_2 0x16882c | |
3463 | #define QM_REG_WRRWEIGHTS_2_SIZE 1 | |
3464 | /* [RW 32] Wrr weights */ | |
3465 | #define QM_REG_WRRWEIGHTS_3 0x168830 | |
3466 | #define QM_REG_WRRWEIGHTS_3_SIZE 1 | |
3467 | /* [RW 32] Wrr weights */ | |
3468 | #define QM_REG_WRRWEIGHTS_4 0x168834 | |
3469 | #define QM_REG_WRRWEIGHTS_4_SIZE 1 | |
3470 | /* [RW 32] Wrr weights */ | |
3471 | #define QM_REG_WRRWEIGHTS_5 0x168838 | |
3472 | #define QM_REG_WRRWEIGHTS_5_SIZE 1 | |
3473 | /* [RW 32] Wrr weights */ | |
3474 | #define QM_REG_WRRWEIGHTS_6 0x16883c | |
3475 | #define QM_REG_WRRWEIGHTS_6_SIZE 1 | |
3476 | /* [RW 32] Wrr weights */ | |
3477 | #define QM_REG_WRRWEIGHTS_7 0x168840 | |
3478 | #define QM_REG_WRRWEIGHTS_7_SIZE 1 | |
3479 | /* [RW 32] Wrr weights */ | |
3480 | #define QM_REG_WRRWEIGHTS_8 0x168844 | |
3481 | #define QM_REG_WRRWEIGHTS_8_SIZE 1 | |
3482 | /* [RW 32] Wrr weights */ | |
3483 | #define QM_REG_WRRWEIGHTS_9 0x168848 | |
3484 | #define QM_REG_WRRWEIGHTS_9_SIZE 1 | |
c18487ee YR |
3485 | /* [RW 32] Wrr weights */ |
3486 | #define QM_REG_WRRWEIGHTS_16 0x16e000 | |
3487 | #define QM_REG_WRRWEIGHTS_16_SIZE 1 | |
3488 | /* [RW 32] Wrr weights */ | |
3489 | #define QM_REG_WRRWEIGHTS_17 0x16e004 | |
3490 | #define QM_REG_WRRWEIGHTS_17_SIZE 1 | |
3491 | /* [RW 32] Wrr weights */ | |
3492 | #define QM_REG_WRRWEIGHTS_18 0x16e008 | |
3493 | #define QM_REG_WRRWEIGHTS_18_SIZE 1 | |
3494 | /* [RW 32] Wrr weights */ | |
3495 | #define QM_REG_WRRWEIGHTS_19 0x16e00c | |
3496 | #define QM_REG_WRRWEIGHTS_19_SIZE 1 | |
3497 | /* [RW 32] Wrr weights */ | |
3498 | #define QM_REG_WRRWEIGHTS_20 0x16e010 | |
3499 | #define QM_REG_WRRWEIGHTS_20_SIZE 1 | |
3500 | /* [RW 32] Wrr weights */ | |
3501 | #define QM_REG_WRRWEIGHTS_21 0x16e014 | |
3502 | #define QM_REG_WRRWEIGHTS_21_SIZE 1 | |
3503 | /* [RW 32] Wrr weights */ | |
3504 | #define QM_REG_WRRWEIGHTS_22 0x16e018 | |
3505 | #define QM_REG_WRRWEIGHTS_22_SIZE 1 | |
3506 | /* [RW 32] Wrr weights */ | |
3507 | #define QM_REG_WRRWEIGHTS_23 0x16e01c | |
3508 | #define QM_REG_WRRWEIGHTS_23_SIZE 1 | |
3509 | /* [RW 32] Wrr weights */ | |
3510 | #define QM_REG_WRRWEIGHTS_24 0x16e020 | |
3511 | #define QM_REG_WRRWEIGHTS_24_SIZE 1 | |
3512 | /* [RW 32] Wrr weights */ | |
3513 | #define QM_REG_WRRWEIGHTS_25 0x16e024 | |
3514 | #define QM_REG_WRRWEIGHTS_25_SIZE 1 | |
3515 | /* [RW 32] Wrr weights */ | |
3516 | #define QM_REG_WRRWEIGHTS_26 0x16e028 | |
3517 | #define QM_REG_WRRWEIGHTS_26_SIZE 1 | |
3518 | /* [RW 32] Wrr weights */ | |
3519 | #define QM_REG_WRRWEIGHTS_27 0x16e02c | |
3520 | #define QM_REG_WRRWEIGHTS_27_SIZE 1 | |
3521 | /* [RW 32] Wrr weights */ | |
3522 | #define QM_REG_WRRWEIGHTS_28 0x16e030 | |
3523 | #define QM_REG_WRRWEIGHTS_28_SIZE 1 | |
3524 | /* [RW 32] Wrr weights */ | |
3525 | #define QM_REG_WRRWEIGHTS_29 0x16e034 | |
3526 | #define QM_REG_WRRWEIGHTS_29_SIZE 1 | |
3527 | /* [RW 32] Wrr weights */ | |
3528 | #define QM_REG_WRRWEIGHTS_30 0x16e038 | |
3529 | #define QM_REG_WRRWEIGHTS_30_SIZE 1 | |
3530 | /* [RW 32] Wrr weights */ | |
3531 | #define QM_REG_WRRWEIGHTS_31 0x16e03c | |
3532 | #define QM_REG_WRRWEIGHTS_31_SIZE 1 | |
a2fbb9ea | 3533 | #define SRC_REG_COUNTFREE0 0x40500 |
c18487ee YR |
3534 | /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two |
3535 | ports. If set the searcher support 8 functions. */ | |
3536 | #define SRC_REG_E1HMF_ENABLE 0x404cc | |
a2fbb9ea ET |
3537 | #define SRC_REG_FIRSTFREE0 0x40510 |
3538 | #define SRC_REG_KEYRSS0_0 0x40408 | |
c18487ee | 3539 | #define SRC_REG_KEYRSS0_7 0x40424 |
a2fbb9ea | 3540 | #define SRC_REG_KEYRSS1_9 0x40454 |
8d9c5f34 EG |
3541 | #define SRC_REG_KEYSEARCH_0 0x40458 |
3542 | #define SRC_REG_KEYSEARCH_1 0x4045c | |
3543 | #define SRC_REG_KEYSEARCH_2 0x40460 | |
3544 | #define SRC_REG_KEYSEARCH_3 0x40464 | |
3545 | #define SRC_REG_KEYSEARCH_4 0x40468 | |
3546 | #define SRC_REG_KEYSEARCH_5 0x4046c | |
3547 | #define SRC_REG_KEYSEARCH_6 0x40470 | |
3548 | #define SRC_REG_KEYSEARCH_7 0x40474 | |
3549 | #define SRC_REG_KEYSEARCH_8 0x40478 | |
3550 | #define SRC_REG_KEYSEARCH_9 0x4047c | |
a2fbb9ea | 3551 | #define SRC_REG_LASTFREE0 0x40530 |
a2fbb9ea ET |
3552 | #define SRC_REG_NUMBER_HASH_BITS0 0x40400 |
3553 | /* [RW 1] Reset internal state machines. */ | |
3554 | #define SRC_REG_SOFT_RST 0x4049c | |
c18487ee | 3555 | /* [R 3] Interrupt register #0 read */ |
a2fbb9ea ET |
3556 | #define SRC_REG_SRC_INT_STS 0x404ac |
3557 | /* [RW 3] Parity mask register #0 read/write */ | |
3558 | #define SRC_REG_SRC_PRTY_MASK 0x404c8 | |
f1410647 ET |
3559 | /* [R 3] Parity register #0 read */ |
3560 | #define SRC_REG_SRC_PRTY_STS 0x404bc | |
a2fbb9ea ET |
3561 | /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */ |
3562 | #define TCM_REG_CAM_OCCUP 0x5017c | |
3563 | /* [RW 1] CDU AG read Interface enable. If 0 - the request input is | |
3564 | disregarded; valid output is deasserted; all other signals are treated as | |
3565 | usual; if 1 - normal activity. */ | |
3566 | #define TCM_REG_CDU_AG_RD_IFEN 0x50034 | |
3567 | /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input | |
3568 | are disregarded; all other signals are treated as usual; if 1 - normal | |
3569 | activity. */ | |
3570 | #define TCM_REG_CDU_AG_WR_IFEN 0x50030 | |
3571 | /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is | |
3572 | disregarded; valid output is deasserted; all other signals are treated as | |
3573 | usual; if 1 - normal activity. */ | |
3574 | #define TCM_REG_CDU_SM_RD_IFEN 0x5003c | |
3575 | /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid | |
3576 | input is disregarded; all other signals are treated as usual; if 1 - | |
3577 | normal activity. */ | |
3578 | #define TCM_REG_CDU_SM_WR_IFEN 0x50038 | |
3579 | /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes | |
3580 | the initial credit value; read returns the current value of the credit | |
3581 | counter. Must be initialized to 1 at start-up. */ | |
3582 | #define TCM_REG_CFC_INIT_CRD 0x50204 | |
3583 | /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for | |
3584 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
3585 | prioritised); 2 stands for weight 2; tc. */ | |
3586 | #define TCM_REG_CP_WEIGHT 0x500c0 | |
3587 | /* [RW 1] Input csem Interface enable. If 0 - the valid input is | |
3588 | disregarded; acknowledge output is deasserted; all other signals are | |
3589 | treated as usual; if 1 - normal activity. */ | |
3590 | #define TCM_REG_CSEM_IFEN 0x5002c | |
3591 | /* [RC 1] Message length mismatch (relative to last indication) at the In#9 | |
3592 | interface. */ | |
3593 | #define TCM_REG_CSEM_LENGTH_MIS 0x50174 | |
8d9c5f34 EG |
3594 | /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for |
3595 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
3596 | prioritised); 2 stands for weight 2; tc. */ | |
3597 | #define TCM_REG_CSEM_WEIGHT 0x500bc | |
a2fbb9ea ET |
3598 | /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */ |
3599 | #define TCM_REG_ERR_EVNT_ID 0x500a0 | |
3600 | /* [RW 28] The CM erroneous header for QM and Timers formatting. */ | |
3601 | #define TCM_REG_ERR_TCM_HDR 0x5009c | |
3602 | /* [RW 8] The Event ID for Timers expiration. */ | |
3603 | #define TCM_REG_EXPR_EVNT_ID 0x500a4 | |
3604 | /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write | |
3605 | writes the initial credit value; read returns the current value of the | |
3606 | credit counter. Must be initialized to 64 at start-up. */ | |
3607 | #define TCM_REG_FIC0_INIT_CRD 0x5020c | |
3608 | /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write | |
3609 | writes the initial credit value; read returns the current value of the | |
3610 | credit counter. Must be initialized to 64 at start-up. */ | |
3611 | #define TCM_REG_FIC1_INIT_CRD 0x50210 | |
3612 | /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 | |
3613 | - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr; | |
3614 | ~tcm_registers_gr_ld0_pr.gr_ld0_pr and | |
3615 | ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */ | |
3616 | #define TCM_REG_GR_ARB_TYPE 0x50114 | |
3617 | /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the | |
3618 | highest priority is 3. It is supposed that the Store channel is the | |
3619 | compliment of the other 3 groups. */ | |
3620 | #define TCM_REG_GR_LD0_PR 0x5011c | |
3621 | /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the | |
3622 | highest priority is 3. It is supposed that the Store channel is the | |
3623 | compliment of the other 3 groups. */ | |
3624 | #define TCM_REG_GR_LD1_PR 0x50120 | |
3625 | /* [RW 4] The number of double REG-pairs; loaded from the STORM context and | |
3626 | sent to STORM; for a specific connection type. The double REG-pairs are | |
3627 | used to align to STORM context row size of 128 bits. The offset of these | |
3628 | data in the STORM context is always 0. Index _i stands for the connection | |
3629 | type (one of 16). */ | |
3630 | #define TCM_REG_N_SM_CTX_LD_0 0x50050 | |
3631 | #define TCM_REG_N_SM_CTX_LD_1 0x50054 | |
3632 | #define TCM_REG_N_SM_CTX_LD_10 0x50078 | |
3633 | #define TCM_REG_N_SM_CTX_LD_11 0x5007c | |
3634 | #define TCM_REG_N_SM_CTX_LD_12 0x50080 | |
3635 | #define TCM_REG_N_SM_CTX_LD_13 0x50084 | |
3636 | #define TCM_REG_N_SM_CTX_LD_14 0x50088 | |
3637 | #define TCM_REG_N_SM_CTX_LD_15 0x5008c | |
3638 | #define TCM_REG_N_SM_CTX_LD_2 0x50058 | |
3639 | #define TCM_REG_N_SM_CTX_LD_3 0x5005c | |
3640 | #define TCM_REG_N_SM_CTX_LD_4 0x50060 | |
8d9c5f34 | 3641 | #define TCM_REG_N_SM_CTX_LD_5 0x50064 |
a2fbb9ea ET |
3642 | /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; |
3643 | acknowledge output is deasserted; all other signals are treated as usual; | |
3644 | if 1 - normal activity. */ | |
3645 | #define TCM_REG_PBF_IFEN 0x50024 | |
3646 | /* [RC 1] Message length mismatch (relative to last indication) at the In#7 | |
3647 | interface. */ | |
3648 | #define TCM_REG_PBF_LENGTH_MIS 0x5016c | |
3649 | /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for | |
3650 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
3651 | prioritised); 2 stands for weight 2; tc. */ | |
3652 | #define TCM_REG_PBF_WEIGHT 0x500b4 | |
a2fbb9ea ET |
3653 | #define TCM_REG_PHYS_QNUM0_0 0x500e0 |
3654 | #define TCM_REG_PHYS_QNUM0_1 0x500e4 | |
a2fbb9ea | 3655 | #define TCM_REG_PHYS_QNUM1_0 0x500e8 |
c18487ee YR |
3656 | #define TCM_REG_PHYS_QNUM1_1 0x500ec |
3657 | #define TCM_REG_PHYS_QNUM2_0 0x500f0 | |
3658 | #define TCM_REG_PHYS_QNUM2_1 0x500f4 | |
3659 | #define TCM_REG_PHYS_QNUM3_0 0x500f8 | |
3660 | #define TCM_REG_PHYS_QNUM3_1 0x500fc | |
a2fbb9ea ET |
3661 | /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded; |
3662 | acknowledge output is deasserted; all other signals are treated as usual; | |
3663 | if 1 - normal activity. */ | |
3664 | #define TCM_REG_PRS_IFEN 0x50020 | |
3665 | /* [RC 1] Message length mismatch (relative to last indication) at the In#6 | |
3666 | interface. */ | |
3667 | #define TCM_REG_PRS_LENGTH_MIS 0x50168 | |
3668 | /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for | |
3669 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
3670 | prioritised); 2 stands for weight 2; tc. */ | |
3671 | #define TCM_REG_PRS_WEIGHT 0x500b0 | |
3672 | /* [RW 8] The Event ID for Timers formatting in case of stop done. */ | |
3673 | #define TCM_REG_STOP_EVNT_ID 0x500a8 | |
3674 | /* [RC 1] Message length mismatch (relative to last indication) at the STORM | |
3675 | interface. */ | |
3676 | #define TCM_REG_STORM_LENGTH_MIS 0x50160 | |
3677 | /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is | |
3678 | disregarded; acknowledge output is deasserted; all other signals are | |
3679 | treated as usual; if 1 - normal activity. */ | |
3680 | #define TCM_REG_STORM_TCM_IFEN 0x50010 | |
8d9c5f34 EG |
3681 | /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for |
3682 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
3683 | prioritised); 2 stands for weight 2; tc. */ | |
3684 | #define TCM_REG_STORM_WEIGHT 0x500ac | |
a2fbb9ea ET |
3685 | /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; |
3686 | acknowledge output is deasserted; all other signals are treated as usual; | |
3687 | if 1 - normal activity. */ | |
3688 | #define TCM_REG_TCM_CFC_IFEN 0x50040 | |
3689 | /* [RW 11] Interrupt mask register #0 read/write */ | |
3690 | #define TCM_REG_TCM_INT_MASK 0x501dc | |
3691 | /* [R 11] Interrupt register #0 read */ | |
3692 | #define TCM_REG_TCM_INT_STS 0x501d0 | |
c18487ee YR |
3693 | /* [R 27] Parity register #0 read */ |
3694 | #define TCM_REG_TCM_PRTY_STS 0x501e0 | |
a2fbb9ea ET |
3695 | /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS |
3696 | REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). | |
3697 | Is used to determine the number of the AG context REG-pairs written back; | |
3698 | when the input message Reg1WbFlg isn't set. */ | |
3699 | #define TCM_REG_TCM_REG0_SZ 0x500d8 | |
3700 | /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is | |
3701 | disregarded; valid is deasserted; all other signals are treated as usual; | |
3702 | if 1 - normal activity. */ | |
3703 | #define TCM_REG_TCM_STORM0_IFEN 0x50004 | |
3704 | /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is | |
3705 | disregarded; valid is deasserted; all other signals are treated as usual; | |
3706 | if 1 - normal activity. */ | |
3707 | #define TCM_REG_TCM_STORM1_IFEN 0x50008 | |
3708 | /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is | |
3709 | disregarded; valid is deasserted; all other signals are treated as usual; | |
3710 | if 1 - normal activity. */ | |
3711 | #define TCM_REG_TCM_TQM_IFEN 0x5000c | |
3712 | /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ | |
3713 | #define TCM_REG_TCM_TQM_USE_Q 0x500d4 | |
3714 | /* [RW 28] The CM header for Timers expiration command. */ | |
3715 | #define TCM_REG_TM_TCM_HDR 0x50098 | |
3716 | /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is | |
3717 | disregarded; acknowledge output is deasserted; all other signals are | |
3718 | treated as usual; if 1 - normal activity. */ | |
3719 | #define TCM_REG_TM_TCM_IFEN 0x5001c | |
8d9c5f34 EG |
3720 | /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for |
3721 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
3722 | prioritised); 2 stands for weight 2; tc. */ | |
3723 | #define TCM_REG_TM_WEIGHT 0x500d0 | |
a2fbb9ea ET |
3724 | /* [RW 6] QM output initial credit. Max credit available - 32.Write writes |
3725 | the initial credit value; read returns the current value of the credit | |
3726 | counter. Must be initialized to 32 at start-up. */ | |
3727 | #define TCM_REG_TQM_INIT_CRD 0x5021c | |
8d9c5f34 EG |
3728 | /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 |
3729 | stands for weight 8 (the most prioritised); 1 stands for weight 1(least | |
3730 | prioritised); 2 stands for weight 2; tc. */ | |
3731 | #define TCM_REG_TQM_P_WEIGHT 0x500c8 | |
3732 | /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 | |
3733 | stands for weight 8 (the most prioritised); 1 stands for weight 1(least | |
3734 | prioritised); 2 stands for weight 2; tc. */ | |
3735 | #define TCM_REG_TQM_S_WEIGHT 0x500cc | |
a2fbb9ea ET |
3736 | /* [RW 28] The CM header value for QM request (primary). */ |
3737 | #define TCM_REG_TQM_TCM_HDR_P 0x50090 | |
3738 | /* [RW 28] The CM header value for QM request (secondary). */ | |
3739 | #define TCM_REG_TQM_TCM_HDR_S 0x50094 | |
3740 | /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; | |
3741 | acknowledge output is deasserted; all other signals are treated as usual; | |
3742 | if 1 - normal activity. */ | |
3743 | #define TCM_REG_TQM_TCM_IFEN 0x50014 | |
3744 | /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; | |
3745 | acknowledge output is deasserted; all other signals are treated as usual; | |
3746 | if 1 - normal activity. */ | |
3747 | #define TCM_REG_TSDM_IFEN 0x50018 | |
3748 | /* [RC 1] Message length mismatch (relative to last indication) at the SDM | |
3749 | interface. */ | |
3750 | #define TCM_REG_TSDM_LENGTH_MIS 0x50164 | |
3751 | /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for | |
3752 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
3753 | prioritised); 2 stands for weight 2; tc. */ | |
3754 | #define TCM_REG_TSDM_WEIGHT 0x500c4 | |
3755 | /* [RW 1] Input usem Interface enable. If 0 - the valid input is | |
3756 | disregarded; acknowledge output is deasserted; all other signals are | |
3757 | treated as usual; if 1 - normal activity. */ | |
3758 | #define TCM_REG_USEM_IFEN 0x50028 | |
3759 | /* [RC 1] Message length mismatch (relative to last indication) at the In#8 | |
3760 | interface. */ | |
3761 | #define TCM_REG_USEM_LENGTH_MIS 0x50170 | |
8d9c5f34 EG |
3762 | /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for |
3763 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
3764 | prioritised); 2 stands for weight 2; tc. */ | |
3765 | #define TCM_REG_USEM_WEIGHT 0x500b8 | |
a2fbb9ea ET |
3766 | /* [RW 21] Indirect access to the descriptor table of the XX protection |
3767 | mechanism. The fields are: [5:0] - length of the message; 15:6] - message | |
3768 | pointer; 20:16] - next pointer. */ | |
3769 | #define TCM_REG_XX_DESCR_TABLE 0x50280 | |
c18487ee | 3770 | #define TCM_REG_XX_DESCR_TABLE_SIZE 32 |
a2fbb9ea ET |
3771 | /* [R 6] Use to read the value of XX protection Free counter. */ |
3772 | #define TCM_REG_XX_FREE 0x50178 | |
3773 | /* [RW 6] Initial value for the credit counter; responsible for fulfilling | |
3774 | of the Input Stage XX protection buffer by the XX protection pending | |
3775 | messages. Max credit available - 127.Write writes the initial credit | |
3776 | value; read returns the current value of the credit counter. Must be | |
3777 | initialized to 19 at start-up. */ | |
3778 | #define TCM_REG_XX_INIT_CRD 0x50220 | |
3779 | /* [RW 6] Maximum link list size (messages locked) per connection in the XX | |
3780 | protection. */ | |
3781 | #define TCM_REG_XX_MAX_LL_SZ 0x50044 | |
3782 | /* [RW 6] The maximum number of pending messages; which may be stored in XX | |
3783 | protection. ~tcm_registers_xx_free.xx_free is read on read. */ | |
3784 | #define TCM_REG_XX_MSG_NUM 0x50224 | |
3785 | /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ | |
3786 | #define TCM_REG_XX_OVFL_EVNT_ID 0x50048 | |
3787 | /* [RW 16] Indirect access to the XX table of the XX protection mechanism. | |
3788 | The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] - | |
3789 | header pointer. */ | |
3790 | #define TCM_REG_XX_TABLE 0x50240 | |
3791 | /* [RW 4] Load value for for cfc ac credit cnt. */ | |
3792 | #define TM_REG_CFC_AC_CRDCNT_VAL 0x164208 | |
3793 | /* [RW 4] Load value for cfc cld credit cnt. */ | |
3794 | #define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210 | |
3795 | /* [RW 8] Client0 context region. */ | |
3796 | #define TM_REG_CL0_CONT_REGION 0x164030 | |
3797 | /* [RW 8] Client1 context region. */ | |
3798 | #define TM_REG_CL1_CONT_REGION 0x164034 | |
3799 | /* [RW 8] Client2 context region. */ | |
3800 | #define TM_REG_CL2_CONT_REGION 0x164038 | |
3801 | /* [RW 2] Client in High priority client number. */ | |
3802 | #define TM_REG_CLIN_PRIOR0_CLIENT 0x164024 | |
3803 | /* [RW 4] Load value for clout0 cred cnt. */ | |
3804 | #define TM_REG_CLOUT_CRDCNT0_VAL 0x164220 | |
3805 | /* [RW 4] Load value for clout1 cred cnt. */ | |
3806 | #define TM_REG_CLOUT_CRDCNT1_VAL 0x164228 | |
3807 | /* [RW 4] Load value for clout2 cred cnt. */ | |
3808 | #define TM_REG_CLOUT_CRDCNT2_VAL 0x164230 | |
3809 | /* [RW 1] Enable client0 input. */ | |
3810 | #define TM_REG_EN_CL0_INPUT 0x164008 | |
3811 | /* [RW 1] Enable client1 input. */ | |
3812 | #define TM_REG_EN_CL1_INPUT 0x16400c | |
3813 | /* [RW 1] Enable client2 input. */ | |
3814 | #define TM_REG_EN_CL2_INPUT 0x164010 | |
8d9c5f34 | 3815 | #define TM_REG_EN_LINEAR0_TIMER 0x164014 |
a2fbb9ea ET |
3816 | /* [RW 1] Enable real time counter. */ |
3817 | #define TM_REG_EN_REAL_TIME_CNT 0x1640d8 | |
3818 | /* [RW 1] Enable for Timers state machines. */ | |
3819 | #define TM_REG_EN_TIMERS 0x164000 | |
3820 | /* [RW 4] Load value for expiration credit cnt. CFC max number of | |
3821 | outstanding load requests for timers (expiration) context loading. */ | |
3822 | #define TM_REG_EXP_CRDCNT_VAL 0x164238 | |
8d9c5f34 EG |
3823 | /* [RW 32] Linear0 logic address. */ |
3824 | #define TM_REG_LIN0_LOGIC_ADDR 0x164240 | |
c18487ee | 3825 | /* [RW 18] Linear0 Max active cid (in banks of 32 entries). */ |
a2fbb9ea ET |
3826 | #define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048 |
3827 | /* [WB 64] Linear0 phy address. */ | |
3828 | #define TM_REG_LIN0_PHY_ADDR 0x164270 | |
8d9c5f34 EG |
3829 | /* [RW 1] Linear0 physical address valid. */ |
3830 | #define TM_REG_LIN0_PHY_ADDR_VALID 0x164248 | |
a2fbb9ea ET |
3831 | /* [RW 24] Linear0 array scan timeout. */ |
3832 | #define TM_REG_LIN0_SCAN_TIME 0x16403c | |
8d9c5f34 EG |
3833 | /* [RW 32] Linear1 logic address. */ |
3834 | #define TM_REG_LIN1_LOGIC_ADDR 0x164250 | |
a2fbb9ea ET |
3835 | /* [WB 64] Linear1 phy address. */ |
3836 | #define TM_REG_LIN1_PHY_ADDR 0x164280 | |
8d9c5f34 EG |
3837 | /* [RW 1] Linear1 physical address valid. */ |
3838 | #define TM_REG_LIN1_PHY_ADDR_VALID 0x164258 | |
a2fbb9ea ET |
3839 | /* [RW 6] Linear timer set_clear fifo threshold. */ |
3840 | #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070 | |
3841 | /* [RW 2] Load value for pci arbiter credit cnt. */ | |
3842 | #define TM_REG_PCIARB_CRDCNT_VAL 0x164260 | |
3843 | /* [RW 1] Timer software reset - active high. */ | |
3844 | #define TM_REG_TIMER_SOFT_RST 0x164004 | |
3845 | /* [RW 20] The amount of hardware cycles for each timer tick. */ | |
3846 | #define TM_REG_TIMER_TICK_SIZE 0x16401c | |
3847 | /* [RW 8] Timers Context region. */ | |
3848 | #define TM_REG_TM_CONTEXT_REGION 0x164044 | |
3849 | /* [RW 1] Interrupt mask register #0 read/write */ | |
3850 | #define TM_REG_TM_INT_MASK 0x1640fc | |
3851 | /* [R 1] Interrupt register #0 read */ | |
3852 | #define TM_REG_TM_INT_STS 0x1640f0 | |
3853 | /* [RW 8] The event id for aggregated interrupt 0 */ | |
3854 | #define TSDM_REG_AGG_INT_EVENT_0 0x42038 | |
8d9c5f34 EG |
3855 | #define TSDM_REG_AGG_INT_EVENT_1 0x4203c |
3856 | #define TSDM_REG_AGG_INT_EVENT_10 0x42060 | |
3857 | #define TSDM_REG_AGG_INT_EVENT_11 0x42064 | |
3858 | #define TSDM_REG_AGG_INT_EVENT_12 0x42068 | |
3859 | #define TSDM_REG_AGG_INT_EVENT_13 0x4206c | |
3860 | #define TSDM_REG_AGG_INT_EVENT_14 0x42070 | |
3861 | #define TSDM_REG_AGG_INT_EVENT_15 0x42074 | |
3862 | #define TSDM_REG_AGG_INT_EVENT_16 0x42078 | |
3863 | #define TSDM_REG_AGG_INT_EVENT_17 0x4207c | |
3864 | #define TSDM_REG_AGG_INT_EVENT_18 0x42080 | |
3865 | #define TSDM_REG_AGG_INT_EVENT_19 0x42084 | |
c18487ee YR |
3866 | #define TSDM_REG_AGG_INT_EVENT_2 0x42040 |
3867 | #define TSDM_REG_AGG_INT_EVENT_20 0x42088 | |
3868 | #define TSDM_REG_AGG_INT_EVENT_21 0x4208c | |
3869 | #define TSDM_REG_AGG_INT_EVENT_22 0x42090 | |
3870 | #define TSDM_REG_AGG_INT_EVENT_23 0x42094 | |
3871 | #define TSDM_REG_AGG_INT_EVENT_24 0x42098 | |
3872 | #define TSDM_REG_AGG_INT_EVENT_25 0x4209c | |
3873 | #define TSDM_REG_AGG_INT_EVENT_26 0x420a0 | |
3874 | #define TSDM_REG_AGG_INT_EVENT_27 0x420a4 | |
3875 | #define TSDM_REG_AGG_INT_EVENT_28 0x420a8 | |
3876 | #define TSDM_REG_AGG_INT_EVENT_29 0x420ac | |
3877 | #define TSDM_REG_AGG_INT_EVENT_3 0x42044 | |
3878 | #define TSDM_REG_AGG_INT_EVENT_30 0x420b0 | |
3879 | #define TSDM_REG_AGG_INT_EVENT_31 0x420b4 | |
3880 | #define TSDM_REG_AGG_INT_EVENT_4 0x42048 | |
8d9c5f34 EG |
3881 | /* [RW 1] The T bit for aggregated interrupt 0 */ |
3882 | #define TSDM_REG_AGG_INT_T_0 0x420b8 | |
3883 | #define TSDM_REG_AGG_INT_T_1 0x420bc | |
3884 | #define TSDM_REG_AGG_INT_T_10 0x420e0 | |
3885 | #define TSDM_REG_AGG_INT_T_11 0x420e4 | |
3886 | #define TSDM_REG_AGG_INT_T_12 0x420e8 | |
3887 | #define TSDM_REG_AGG_INT_T_13 0x420ec | |
3888 | #define TSDM_REG_AGG_INT_T_14 0x420f0 | |
3889 | #define TSDM_REG_AGG_INT_T_15 0x420f4 | |
3890 | #define TSDM_REG_AGG_INT_T_16 0x420f8 | |
3891 | #define TSDM_REG_AGG_INT_T_17 0x420fc | |
3892 | #define TSDM_REG_AGG_INT_T_18 0x42100 | |
3893 | #define TSDM_REG_AGG_INT_T_19 0x42104 | |
a2fbb9ea ET |
3894 | /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ |
3895 | #define TSDM_REG_CFC_RSP_START_ADDR 0x42008 | |
3896 | /* [RW 16] The maximum value of the competion counter #0 */ | |
3897 | #define TSDM_REG_CMP_COUNTER_MAX0 0x4201c | |
3898 | /* [RW 16] The maximum value of the competion counter #1 */ | |
3899 | #define TSDM_REG_CMP_COUNTER_MAX1 0x42020 | |
3900 | /* [RW 16] The maximum value of the competion counter #2 */ | |
3901 | #define TSDM_REG_CMP_COUNTER_MAX2 0x42024 | |
3902 | /* [RW 16] The maximum value of the competion counter #3 */ | |
3903 | #define TSDM_REG_CMP_COUNTER_MAX3 0x42028 | |
3904 | /* [RW 13] The start address in the internal RAM for the completion | |
3905 | counters. */ | |
3906 | #define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c | |
3907 | #define TSDM_REG_ENABLE_IN1 0x42238 | |
3908 | #define TSDM_REG_ENABLE_IN2 0x4223c | |
3909 | #define TSDM_REG_ENABLE_OUT1 0x42240 | |
3910 | #define TSDM_REG_ENABLE_OUT2 0x42244 | |
3911 | /* [RW 4] The initial number of messages that can be sent to the pxp control | |
3912 | interface without receiving any ACK. */ | |
3913 | #define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc | |
3914 | /* [ST 32] The number of ACK after placement messages received */ | |
3915 | #define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c | |
3916 | /* [ST 32] The number of packet end messages received from the parser */ | |
3917 | #define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274 | |
3918 | /* [ST 32] The number of requests received from the pxp async if */ | |
3919 | #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278 | |
3920 | /* [ST 32] The number of commands received in queue 0 */ | |
3921 | #define TSDM_REG_NUM_OF_Q0_CMD 0x42248 | |
3922 | /* [ST 32] The number of commands received in queue 10 */ | |
3923 | #define TSDM_REG_NUM_OF_Q10_CMD 0x4226c | |
3924 | /* [ST 32] The number of commands received in queue 11 */ | |
3925 | #define TSDM_REG_NUM_OF_Q11_CMD 0x42270 | |
3926 | /* [ST 32] The number of commands received in queue 1 */ | |
3927 | #define TSDM_REG_NUM_OF_Q1_CMD 0x4224c | |
3928 | /* [ST 32] The number of commands received in queue 3 */ | |
3929 | #define TSDM_REG_NUM_OF_Q3_CMD 0x42250 | |
3930 | /* [ST 32] The number of commands received in queue 4 */ | |
3931 | #define TSDM_REG_NUM_OF_Q4_CMD 0x42254 | |
3932 | /* [ST 32] The number of commands received in queue 5 */ | |
3933 | #define TSDM_REG_NUM_OF_Q5_CMD 0x42258 | |
3934 | /* [ST 32] The number of commands received in queue 6 */ | |
3935 | #define TSDM_REG_NUM_OF_Q6_CMD 0x4225c | |
3936 | /* [ST 32] The number of commands received in queue 7 */ | |
3937 | #define TSDM_REG_NUM_OF_Q7_CMD 0x42260 | |
3938 | /* [ST 32] The number of commands received in queue 8 */ | |
3939 | #define TSDM_REG_NUM_OF_Q8_CMD 0x42264 | |
3940 | /* [ST 32] The number of commands received in queue 9 */ | |
3941 | #define TSDM_REG_NUM_OF_Q9_CMD 0x42268 | |
3942 | /* [RW 13] The start address in the internal RAM for the packet end message */ | |
3943 | #define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014 | |
3944 | /* [RW 13] The start address in the internal RAM for queue counters */ | |
3945 | #define TSDM_REG_Q_COUNTER_START_ADDR 0x42010 | |
3946 | /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ | |
3947 | #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548 | |
3948 | /* [R 1] parser fifo empty in sdm_sync block */ | |
3949 | #define TSDM_REG_SYNC_PARSER_EMPTY 0x42550 | |
3950 | /* [R 1] parser serial fifo empty in sdm_sync block */ | |
3951 | #define TSDM_REG_SYNC_SYNC_EMPTY 0x42558 | |
3952 | /* [RW 32] Tick for timer counter. Applicable only when | |
3953 | ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */ | |
3954 | #define TSDM_REG_TIMER_TICK 0x42000 | |
3955 | /* [RW 32] Interrupt mask register #0 read/write */ | |
3956 | #define TSDM_REG_TSDM_INT_MASK_0 0x4229c | |
3957 | #define TSDM_REG_TSDM_INT_MASK_1 0x422ac | |
c18487ee YR |
3958 | /* [R 32] Interrupt register #0 read */ |
3959 | #define TSDM_REG_TSDM_INT_STS_0 0x42290 | |
3960 | #define TSDM_REG_TSDM_INT_STS_1 0x422a0 | |
a2fbb9ea ET |
3961 | /* [RW 11] Parity mask register #0 read/write */ |
3962 | #define TSDM_REG_TSDM_PRTY_MASK 0x422bc | |
f1410647 ET |
3963 | /* [R 11] Parity register #0 read */ |
3964 | #define TSDM_REG_TSDM_PRTY_STS 0x422b0 | |
a2fbb9ea ET |
3965 | /* [RW 5] The number of time_slots in the arbitration cycle */ |
3966 | #define TSEM_REG_ARB_CYCLE_SIZE 0x180034 | |
3967 | /* [RW 3] The source that is associated with arbitration element 0. Source | |
3968 | decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- | |
3969 | sleeping thread with priority 1; 4- sleeping thread with priority 2 */ | |
3970 | #define TSEM_REG_ARB_ELEMENT0 0x180020 | |
3971 | /* [RW 3] The source that is associated with arbitration element 1. Source | |
3972 | decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- | |
3973 | sleeping thread with priority 1; 4- sleeping thread with priority 2. | |
3974 | Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */ | |
3975 | #define TSEM_REG_ARB_ELEMENT1 0x180024 | |
3976 | /* [RW 3] The source that is associated with arbitration element 2. Source | |
3977 | decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- | |
3978 | sleeping thread with priority 1; 4- sleeping thread with priority 2. | |
3979 | Could not be equal to register ~tsem_registers_arb_element0.arb_element0 | |
3980 | and ~tsem_registers_arb_element1.arb_element1 */ | |
3981 | #define TSEM_REG_ARB_ELEMENT2 0x180028 | |
3982 | /* [RW 3] The source that is associated with arbitration element 3. Source | |
3983 | decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- | |
3984 | sleeping thread with priority 1; 4- sleeping thread with priority 2.Could | |
3985 | not be equal to register ~tsem_registers_arb_element0.arb_element0 and | |
3986 | ~tsem_registers_arb_element1.arb_element1 and | |
3987 | ~tsem_registers_arb_element2.arb_element2 */ | |
3988 | #define TSEM_REG_ARB_ELEMENT3 0x18002c | |
3989 | /* [RW 3] The source that is associated with arbitration element 4. Source | |
3990 | decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- | |
3991 | sleeping thread with priority 1; 4- sleeping thread with priority 2. | |
3992 | Could not be equal to register ~tsem_registers_arb_element0.arb_element0 | |
3993 | and ~tsem_registers_arb_element1.arb_element1 and | |
3994 | ~tsem_registers_arb_element2.arb_element2 and | |
3995 | ~tsem_registers_arb_element3.arb_element3 */ | |
3996 | #define TSEM_REG_ARB_ELEMENT4 0x180030 | |
3997 | #define TSEM_REG_ENABLE_IN 0x1800a4 | |
3998 | #define TSEM_REG_ENABLE_OUT 0x1800a8 | |
3999 | /* [RW 32] This address space contains all registers and memories that are | |
4000 | placed in SEM_FAST block. The SEM_FAST registers are described in | |
c18487ee YR |
4001 | appendix B. In order to access the sem_fast registers the base address |
4002 | ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ | |
a2fbb9ea ET |
4003 | #define TSEM_REG_FAST_MEMORY 0x1a0000 |
4004 | /* [RW 1] Disables input messages from FIC0 May be updated during run_time | |
4005 | by the microcode */ | |
4006 | #define TSEM_REG_FIC0_DISABLE 0x180224 | |
4007 | /* [RW 1] Disables input messages from FIC1 May be updated during run_time | |
4008 | by the microcode */ | |
4009 | #define TSEM_REG_FIC1_DISABLE 0x180234 | |
4010 | /* [RW 15] Interrupt table Read and write access to it is not possible in | |
4011 | the middle of the work */ | |
4012 | #define TSEM_REG_INT_TABLE 0x180400 | |
4013 | /* [ST 24] Statistics register. The number of messages that entered through | |
4014 | FIC0 */ | |
4015 | #define TSEM_REG_MSG_NUM_FIC0 0x180000 | |
4016 | /* [ST 24] Statistics register. The number of messages that entered through | |
4017 | FIC1 */ | |
4018 | #define TSEM_REG_MSG_NUM_FIC1 0x180004 | |
4019 | /* [ST 24] Statistics register. The number of messages that were sent to | |
4020 | FOC0 */ | |
4021 | #define TSEM_REG_MSG_NUM_FOC0 0x180008 | |
4022 | /* [ST 24] Statistics register. The number of messages that were sent to | |
4023 | FOC1 */ | |
4024 | #define TSEM_REG_MSG_NUM_FOC1 0x18000c | |
4025 | /* [ST 24] Statistics register. The number of messages that were sent to | |
4026 | FOC2 */ | |
4027 | #define TSEM_REG_MSG_NUM_FOC2 0x180010 | |
4028 | /* [ST 24] Statistics register. The number of messages that were sent to | |
4029 | FOC3 */ | |
4030 | #define TSEM_REG_MSG_NUM_FOC3 0x180014 | |
4031 | /* [RW 1] Disables input messages from the passive buffer May be updated | |
4032 | during run_time by the microcode */ | |
4033 | #define TSEM_REG_PAS_DISABLE 0x18024c | |
4034 | /* [WB 128] Debug only. Passive buffer memory */ | |
4035 | #define TSEM_REG_PASSIVE_BUFFER 0x181000 | |
4036 | /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ | |
4037 | #define TSEM_REG_PRAM 0x1c0000 | |
4038 | /* [R 8] Valid sleeping threads indication have bit per thread */ | |
4039 | #define TSEM_REG_SLEEP_THREADS_VALID 0x18026c | |
4040 | /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ | |
4041 | #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0 | |
4042 | /* [RW 8] List of free threads . There is a bit per thread. */ | |
4043 | #define TSEM_REG_THREADS_LIST 0x1802e4 | |
4044 | /* [RW 3] The arbitration scheme of time_slot 0 */ | |
4045 | #define TSEM_REG_TS_0_AS 0x180038 | |
4046 | /* [RW 3] The arbitration scheme of time_slot 10 */ | |
4047 | #define TSEM_REG_TS_10_AS 0x180060 | |
4048 | /* [RW 3] The arbitration scheme of time_slot 11 */ | |
4049 | #define TSEM_REG_TS_11_AS 0x180064 | |
4050 | /* [RW 3] The arbitration scheme of time_slot 12 */ | |
4051 | #define TSEM_REG_TS_12_AS 0x180068 | |
4052 | /* [RW 3] The arbitration scheme of time_slot 13 */ | |
4053 | #define TSEM_REG_TS_13_AS 0x18006c | |
4054 | /* [RW 3] The arbitration scheme of time_slot 14 */ | |
4055 | #define TSEM_REG_TS_14_AS 0x180070 | |
4056 | /* [RW 3] The arbitration scheme of time_slot 15 */ | |
4057 | #define TSEM_REG_TS_15_AS 0x180074 | |
4058 | /* [RW 3] The arbitration scheme of time_slot 16 */ | |
4059 | #define TSEM_REG_TS_16_AS 0x180078 | |
4060 | /* [RW 3] The arbitration scheme of time_slot 17 */ | |
4061 | #define TSEM_REG_TS_17_AS 0x18007c | |
4062 | /* [RW 3] The arbitration scheme of time_slot 18 */ | |
4063 | #define TSEM_REG_TS_18_AS 0x180080 | |
4064 | /* [RW 3] The arbitration scheme of time_slot 1 */ | |
4065 | #define TSEM_REG_TS_1_AS 0x18003c | |
4066 | /* [RW 3] The arbitration scheme of time_slot 2 */ | |
4067 | #define TSEM_REG_TS_2_AS 0x180040 | |
4068 | /* [RW 3] The arbitration scheme of time_slot 3 */ | |
4069 | #define TSEM_REG_TS_3_AS 0x180044 | |
4070 | /* [RW 3] The arbitration scheme of time_slot 4 */ | |
4071 | #define TSEM_REG_TS_4_AS 0x180048 | |
4072 | /* [RW 3] The arbitration scheme of time_slot 5 */ | |
4073 | #define TSEM_REG_TS_5_AS 0x18004c | |
4074 | /* [RW 3] The arbitration scheme of time_slot 6 */ | |
4075 | #define TSEM_REG_TS_6_AS 0x180050 | |
4076 | /* [RW 3] The arbitration scheme of time_slot 7 */ | |
4077 | #define TSEM_REG_TS_7_AS 0x180054 | |
4078 | /* [RW 3] The arbitration scheme of time_slot 8 */ | |
4079 | #define TSEM_REG_TS_8_AS 0x180058 | |
4080 | /* [RW 3] The arbitration scheme of time_slot 9 */ | |
4081 | #define TSEM_REG_TS_9_AS 0x18005c | |
4082 | /* [RW 32] Interrupt mask register #0 read/write */ | |
4083 | #define TSEM_REG_TSEM_INT_MASK_0 0x180100 | |
4084 | #define TSEM_REG_TSEM_INT_MASK_1 0x180110 | |
c18487ee YR |
4085 | /* [R 32] Interrupt register #0 read */ |
4086 | #define TSEM_REG_TSEM_INT_STS_0 0x1800f4 | |
4087 | #define TSEM_REG_TSEM_INT_STS_1 0x180104 | |
a2fbb9ea ET |
4088 | /* [RW 32] Parity mask register #0 read/write */ |
4089 | #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120 | |
4090 | #define TSEM_REG_TSEM_PRTY_MASK_1 0x180130 | |
f1410647 ET |
4091 | /* [R 32] Parity register #0 read */ |
4092 | #define TSEM_REG_TSEM_PRTY_STS_0 0x180114 | |
4093 | #define TSEM_REG_TSEM_PRTY_STS_1 0x180124 | |
a2fbb9ea ET |
4094 | /* [R 5] Used to read the XX protection CAM occupancy counter. */ |
4095 | #define UCM_REG_CAM_OCCUP 0xe0170 | |
4096 | /* [RW 1] CDU AG read Interface enable. If 0 - the request input is | |
4097 | disregarded; valid output is deasserted; all other signals are treated as | |
4098 | usual; if 1 - normal activity. */ | |
4099 | #define UCM_REG_CDU_AG_RD_IFEN 0xe0038 | |
4100 | /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input | |
4101 | are disregarded; all other signals are treated as usual; if 1 - normal | |
4102 | activity. */ | |
4103 | #define UCM_REG_CDU_AG_WR_IFEN 0xe0034 | |
4104 | /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is | |
4105 | disregarded; valid output is deasserted; all other signals are treated as | |
4106 | usual; if 1 - normal activity. */ | |
4107 | #define UCM_REG_CDU_SM_RD_IFEN 0xe0040 | |
4108 | /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid | |
4109 | input is disregarded; all other signals are treated as usual; if 1 - | |
4110 | normal activity. */ | |
4111 | #define UCM_REG_CDU_SM_WR_IFEN 0xe003c | |
4112 | /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes | |
4113 | the initial credit value; read returns the current value of the credit | |
4114 | counter. Must be initialized to 1 at start-up. */ | |
4115 | #define UCM_REG_CFC_INIT_CRD 0xe0204 | |
4116 | /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for | |
4117 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
4118 | prioritised); 2 stands for weight 2; tc. */ | |
4119 | #define UCM_REG_CP_WEIGHT 0xe00c4 | |
4120 | /* [RW 1] Input csem Interface enable. If 0 - the valid input is | |
4121 | disregarded; acknowledge output is deasserted; all other signals are | |
4122 | treated as usual; if 1 - normal activity. */ | |
4123 | #define UCM_REG_CSEM_IFEN 0xe0028 | |
4124 | /* [RC 1] Set when the message length mismatch (relative to last indication) | |
4125 | at the csem interface is detected. */ | |
4126 | #define UCM_REG_CSEM_LENGTH_MIS 0xe0160 | |
4127 | /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for | |
4128 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
4129 | prioritised); 2 stands for weight 2; tc. */ | |
4130 | #define UCM_REG_CSEM_WEIGHT 0xe00b8 | |
4131 | /* [RW 1] Input dorq Interface enable. If 0 - the valid input is | |
4132 | disregarded; acknowledge output is deasserted; all other signals are | |
4133 | treated as usual; if 1 - normal activity. */ | |
4134 | #define UCM_REG_DORQ_IFEN 0xe0030 | |
4135 | /* [RC 1] Set when the message length mismatch (relative to last indication) | |
4136 | at the dorq interface is detected. */ | |
4137 | #define UCM_REG_DORQ_LENGTH_MIS 0xe0168 | |
8d9c5f34 EG |
4138 | /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for |
4139 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
4140 | prioritised); 2 stands for weight 2; tc. */ | |
4141 | #define UCM_REG_DORQ_WEIGHT 0xe00c0 | |
a2fbb9ea ET |
4142 | /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */ |
4143 | #define UCM_REG_ERR_EVNT_ID 0xe00a4 | |
4144 | /* [RW 28] The CM erroneous header for QM and Timers formatting. */ | |
4145 | #define UCM_REG_ERR_UCM_HDR 0xe00a0 | |
4146 | /* [RW 8] The Event ID for Timers expiration. */ | |
4147 | #define UCM_REG_EXPR_EVNT_ID 0xe00a8 | |
4148 | /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write | |
4149 | writes the initial credit value; read returns the current value of the | |
4150 | credit counter. Must be initialized to 64 at start-up. */ | |
4151 | #define UCM_REG_FIC0_INIT_CRD 0xe020c | |
4152 | /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write | |
4153 | writes the initial credit value; read returns the current value of the | |
4154 | credit counter. Must be initialized to 64 at start-up. */ | |
4155 | #define UCM_REG_FIC1_INIT_CRD 0xe0210 | |
4156 | /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 | |
4157 | - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr; | |
4158 | ~ucm_registers_gr_ld0_pr.gr_ld0_pr and | |
4159 | ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */ | |
4160 | #define UCM_REG_GR_ARB_TYPE 0xe0144 | |
4161 | /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the | |
4162 | highest priority is 3. It is supposed that the Store channel group is | |
4163 | compliment to the others. */ | |
4164 | #define UCM_REG_GR_LD0_PR 0xe014c | |
4165 | /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the | |
4166 | highest priority is 3. It is supposed that the Store channel group is | |
4167 | compliment to the others. */ | |
4168 | #define UCM_REG_GR_LD1_PR 0xe0150 | |
4169 | /* [RW 2] The queue index for invalidate counter flag decision. */ | |
4170 | #define UCM_REG_INV_CFLG_Q 0xe00e4 | |
4171 | /* [RW 5] The number of double REG-pairs; loaded from the STORM context and | |
4172 | sent to STORM; for a specific connection type. the double REG-pairs are | |
4173 | used in order to align to STORM context row size of 128 bits. The offset | |
4174 | of these data in the STORM context is always 0. Index _i stands for the | |
4175 | connection type (one of 16). */ | |
4176 | #define UCM_REG_N_SM_CTX_LD_0 0xe0054 | |
4177 | #define UCM_REG_N_SM_CTX_LD_1 0xe0058 | |
4178 | #define UCM_REG_N_SM_CTX_LD_10 0xe007c | |
4179 | #define UCM_REG_N_SM_CTX_LD_11 0xe0080 | |
4180 | #define UCM_REG_N_SM_CTX_LD_12 0xe0084 | |
4181 | #define UCM_REG_N_SM_CTX_LD_13 0xe0088 | |
4182 | #define UCM_REG_N_SM_CTX_LD_14 0xe008c | |
4183 | #define UCM_REG_N_SM_CTX_LD_15 0xe0090 | |
4184 | #define UCM_REG_N_SM_CTX_LD_2 0xe005c | |
4185 | #define UCM_REG_N_SM_CTX_LD_3 0xe0060 | |
4186 | #define UCM_REG_N_SM_CTX_LD_4 0xe0064 | |
c18487ee | 4187 | #define UCM_REG_N_SM_CTX_LD_5 0xe0068 |
a2fbb9ea ET |
4188 | #define UCM_REG_PHYS_QNUM0_0 0xe0110 |
4189 | #define UCM_REG_PHYS_QNUM0_1 0xe0114 | |
a2fbb9ea ET |
4190 | #define UCM_REG_PHYS_QNUM1_0 0xe0118 |
4191 | #define UCM_REG_PHYS_QNUM1_1 0xe011c | |
c18487ee YR |
4192 | #define UCM_REG_PHYS_QNUM2_0 0xe0120 |
4193 | #define UCM_REG_PHYS_QNUM2_1 0xe0124 | |
4194 | #define UCM_REG_PHYS_QNUM3_0 0xe0128 | |
4195 | #define UCM_REG_PHYS_QNUM3_1 0xe012c | |
a2fbb9ea ET |
4196 | /* [RW 8] The Event ID for Timers formatting in case of stop done. */ |
4197 | #define UCM_REG_STOP_EVNT_ID 0xe00ac | |
4198 | /* [RC 1] Set when the message length mismatch (relative to last indication) | |
4199 | at the STORM interface is detected. */ | |
4200 | #define UCM_REG_STORM_LENGTH_MIS 0xe0154 | |
4201 | /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is | |
4202 | disregarded; acknowledge output is deasserted; all other signals are | |
4203 | treated as usual; if 1 - normal activity. */ | |
4204 | #define UCM_REG_STORM_UCM_IFEN 0xe0010 | |
8d9c5f34 EG |
4205 | /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for |
4206 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
4207 | prioritised); 2 stands for weight 2; tc. */ | |
4208 | #define UCM_REG_STORM_WEIGHT 0xe00b0 | |
a2fbb9ea ET |
4209 | /* [RW 4] Timers output initial credit. Max credit available - 15.Write |
4210 | writes the initial credit value; read returns the current value of the | |
4211 | credit counter. Must be initialized to 4 at start-up. */ | |
4212 | #define UCM_REG_TM_INIT_CRD 0xe021c | |
4213 | /* [RW 28] The CM header for Timers expiration command. */ | |
4214 | #define UCM_REG_TM_UCM_HDR 0xe009c | |
4215 | /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is | |
4216 | disregarded; acknowledge output is deasserted; all other signals are | |
4217 | treated as usual; if 1 - normal activity. */ | |
4218 | #define UCM_REG_TM_UCM_IFEN 0xe001c | |
8d9c5f34 EG |
4219 | /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for |
4220 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
4221 | prioritised); 2 stands for weight 2; tc. */ | |
4222 | #define UCM_REG_TM_WEIGHT 0xe00d4 | |
a2fbb9ea ET |
4223 | /* [RW 1] Input tsem Interface enable. If 0 - the valid input is |
4224 | disregarded; acknowledge output is deasserted; all other signals are | |
4225 | treated as usual; if 1 - normal activity. */ | |
4226 | #define UCM_REG_TSEM_IFEN 0xe0024 | |
4227 | /* [RC 1] Set when the message length mismatch (relative to last indication) | |
4228 | at the tsem interface is detected. */ | |
4229 | #define UCM_REG_TSEM_LENGTH_MIS 0xe015c | |
4230 | /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for | |
4231 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
4232 | prioritised); 2 stands for weight 2; tc. */ | |
4233 | #define UCM_REG_TSEM_WEIGHT 0xe00b4 | |
4234 | /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; | |
4235 | acknowledge output is deasserted; all other signals are treated as usual; | |
4236 | if 1 - normal activity. */ | |
4237 | #define UCM_REG_UCM_CFC_IFEN 0xe0044 | |
4238 | /* [RW 11] Interrupt mask register #0 read/write */ | |
4239 | #define UCM_REG_UCM_INT_MASK 0xe01d4 | |
4240 | /* [R 11] Interrupt register #0 read */ | |
4241 | #define UCM_REG_UCM_INT_STS 0xe01c8 | |
c18487ee YR |
4242 | /* [R 27] Parity register #0 read */ |
4243 | #define UCM_REG_UCM_PRTY_STS 0xe01d8 | |
a2fbb9ea ET |
4244 | /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS |
4245 | REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). | |
4246 | Is used to determine the number of the AG context REG-pairs written back; | |
4247 | when the Reg1WbFlg isn't set. */ | |
4248 | #define UCM_REG_UCM_REG0_SZ 0xe00dc | |
4249 | /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is | |
4250 | disregarded; valid is deasserted; all other signals are treated as usual; | |
4251 | if 1 - normal activity. */ | |
4252 | #define UCM_REG_UCM_STORM0_IFEN 0xe0004 | |
4253 | /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is | |
4254 | disregarded; valid is deasserted; all other signals are treated as usual; | |
4255 | if 1 - normal activity. */ | |
4256 | #define UCM_REG_UCM_STORM1_IFEN 0xe0008 | |
4257 | /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is | |
4258 | disregarded; acknowledge output is deasserted; all other signals are | |
4259 | treated as usual; if 1 - normal activity. */ | |
4260 | #define UCM_REG_UCM_TM_IFEN 0xe0020 | |
4261 | /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is | |
4262 | disregarded; valid is deasserted; all other signals are treated as usual; | |
4263 | if 1 - normal activity. */ | |
4264 | #define UCM_REG_UCM_UQM_IFEN 0xe000c | |
4265 | /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ | |
4266 | #define UCM_REG_UCM_UQM_USE_Q 0xe00d8 | |
4267 | /* [RW 6] QM output initial credit. Max credit available - 32.Write writes | |
4268 | the initial credit value; read returns the current value of the credit | |
4269 | counter. Must be initialized to 32 at start-up. */ | |
4270 | #define UCM_REG_UQM_INIT_CRD 0xe0220 | |
4271 | /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 | |
4272 | stands for weight 8 (the most prioritised); 1 stands for weight 1(least | |
4273 | prioritised); 2 stands for weight 2; tc. */ | |
4274 | #define UCM_REG_UQM_P_WEIGHT 0xe00cc | |
8d9c5f34 EG |
4275 | /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 |
4276 | stands for weight 8 (the most prioritised); 1 stands for weight 1(least | |
4277 | prioritised); 2 stands for weight 2; tc. */ | |
4278 | #define UCM_REG_UQM_S_WEIGHT 0xe00d0 | |
a2fbb9ea ET |
4279 | /* [RW 28] The CM header value for QM request (primary). */ |
4280 | #define UCM_REG_UQM_UCM_HDR_P 0xe0094 | |
4281 | /* [RW 28] The CM header value for QM request (secondary). */ | |
4282 | #define UCM_REG_UQM_UCM_HDR_S 0xe0098 | |
4283 | /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; | |
4284 | acknowledge output is deasserted; all other signals are treated as usual; | |
4285 | if 1 - normal activity. */ | |
4286 | #define UCM_REG_UQM_UCM_IFEN 0xe0014 | |
4287 | /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; | |
4288 | acknowledge output is deasserted; all other signals are treated as usual; | |
4289 | if 1 - normal activity. */ | |
4290 | #define UCM_REG_USDM_IFEN 0xe0018 | |
4291 | /* [RC 1] Set when the message length mismatch (relative to last indication) | |
4292 | at the SDM interface is detected. */ | |
4293 | #define UCM_REG_USDM_LENGTH_MIS 0xe0158 | |
8d9c5f34 EG |
4294 | /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for |
4295 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
4296 | prioritised); 2 stands for weight 2; tc. */ | |
4297 | #define UCM_REG_USDM_WEIGHT 0xe00c8 | |
a2fbb9ea ET |
4298 | /* [RW 1] Input xsem Interface enable. If 0 - the valid input is |
4299 | disregarded; acknowledge output is deasserted; all other signals are | |
4300 | treated as usual; if 1 - normal activity. */ | |
4301 | #define UCM_REG_XSEM_IFEN 0xe002c | |
4302 | /* [RC 1] Set when the message length mismatch (relative to last indication) | |
4303 | at the xsem interface isdetected. */ | |
4304 | #define UCM_REG_XSEM_LENGTH_MIS 0xe0164 | |
8d9c5f34 EG |
4305 | /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for |
4306 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
4307 | prioritised); 2 stands for weight 2; tc. */ | |
4308 | #define UCM_REG_XSEM_WEIGHT 0xe00bc | |
a2fbb9ea ET |
4309 | /* [RW 20] Indirect access to the descriptor table of the XX protection |
4310 | mechanism. The fields are:[5:0] - message length; 14:6] - message | |
4311 | pointer; 19:15] - next pointer. */ | |
4312 | #define UCM_REG_XX_DESCR_TABLE 0xe0280 | |
c18487ee | 4313 | #define UCM_REG_XX_DESCR_TABLE_SIZE 32 |
a2fbb9ea ET |
4314 | /* [R 6] Use to read the XX protection Free counter. */ |
4315 | #define UCM_REG_XX_FREE 0xe016c | |
4316 | /* [RW 6] Initial value for the credit counter; responsible for fulfilling | |
4317 | of the Input Stage XX protection buffer by the XX protection pending | |
4318 | messages. Write writes the initial credit value; read returns the current | |
4319 | value of the credit counter. Must be initialized to 12 at start-up. */ | |
4320 | #define UCM_REG_XX_INIT_CRD 0xe0224 | |
4321 | /* [RW 6] The maximum number of pending messages; which may be stored in XX | |
4322 | protection. ~ucm_registers_xx_free.xx_free read on read. */ | |
4323 | #define UCM_REG_XX_MSG_NUM 0xe0228 | |
4324 | /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ | |
4325 | #define UCM_REG_XX_OVFL_EVNT_ID 0xe004c | |
4326 | /* [RW 16] Indirect access to the XX table of the XX protection mechanism. | |
4327 | The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] - | |
4328 | header pointer. */ | |
4329 | #define UCM_REG_XX_TABLE 0xe0300 | |
4330 | /* [RW 8] The event id for aggregated interrupt 0 */ | |
4331 | #define USDM_REG_AGG_INT_EVENT_0 0xc4038 | |
4332 | #define USDM_REG_AGG_INT_EVENT_1 0xc403c | |
4333 | #define USDM_REG_AGG_INT_EVENT_10 0xc4060 | |
4334 | #define USDM_REG_AGG_INT_EVENT_11 0xc4064 | |
4335 | #define USDM_REG_AGG_INT_EVENT_12 0xc4068 | |
4336 | #define USDM_REG_AGG_INT_EVENT_13 0xc406c | |
4337 | #define USDM_REG_AGG_INT_EVENT_14 0xc4070 | |
4338 | #define USDM_REG_AGG_INT_EVENT_15 0xc4074 | |
4339 | #define USDM_REG_AGG_INT_EVENT_16 0xc4078 | |
4340 | #define USDM_REG_AGG_INT_EVENT_17 0xc407c | |
4341 | #define USDM_REG_AGG_INT_EVENT_18 0xc4080 | |
4342 | #define USDM_REG_AGG_INT_EVENT_19 0xc4084 | |
c18487ee YR |
4343 | #define USDM_REG_AGG_INT_EVENT_2 0xc4040 |
4344 | #define USDM_REG_AGG_INT_EVENT_20 0xc4088 | |
4345 | #define USDM_REG_AGG_INT_EVENT_21 0xc408c | |
4346 | #define USDM_REG_AGG_INT_EVENT_22 0xc4090 | |
4347 | #define USDM_REG_AGG_INT_EVENT_23 0xc4094 | |
4348 | #define USDM_REG_AGG_INT_EVENT_24 0xc4098 | |
4349 | #define USDM_REG_AGG_INT_EVENT_25 0xc409c | |
4350 | #define USDM_REG_AGG_INT_EVENT_26 0xc40a0 | |
4351 | #define USDM_REG_AGG_INT_EVENT_27 0xc40a4 | |
4352 | #define USDM_REG_AGG_INT_EVENT_28 0xc40a8 | |
4353 | #define USDM_REG_AGG_INT_EVENT_29 0xc40ac | |
4354 | #define USDM_REG_AGG_INT_EVENT_3 0xc4044 | |
4355 | #define USDM_REG_AGG_INT_EVENT_30 0xc40b0 | |
4356 | #define USDM_REG_AGG_INT_EVENT_31 0xc40b4 | |
4357 | #define USDM_REG_AGG_INT_EVENT_4 0xc4048 | |
8d9c5f34 | 4358 | #define USDM_REG_AGG_INT_EVENT_5 0xc404c |
a2fbb9ea ET |
4359 | /* [RW 1] For each aggregated interrupt index whether the mode is normal (0) |
4360 | or auto-mask-mode (1) */ | |
4361 | #define USDM_REG_AGG_INT_MODE_0 0xc41b8 | |
4362 | #define USDM_REG_AGG_INT_MODE_1 0xc41bc | |
4363 | #define USDM_REG_AGG_INT_MODE_10 0xc41e0 | |
4364 | #define USDM_REG_AGG_INT_MODE_11 0xc41e4 | |
4365 | #define USDM_REG_AGG_INT_MODE_12 0xc41e8 | |
4366 | #define USDM_REG_AGG_INT_MODE_13 0xc41ec | |
4367 | #define USDM_REG_AGG_INT_MODE_14 0xc41f0 | |
4368 | #define USDM_REG_AGG_INT_MODE_15 0xc41f4 | |
4369 | #define USDM_REG_AGG_INT_MODE_16 0xc41f8 | |
4370 | #define USDM_REG_AGG_INT_MODE_17 0xc41fc | |
4371 | #define USDM_REG_AGG_INT_MODE_18 0xc4200 | |
4372 | #define USDM_REG_AGG_INT_MODE_19 0xc4204 | |
8d9c5f34 EG |
4373 | #define USDM_REG_AGG_INT_MODE_4 0xc41c8 |
4374 | #define USDM_REG_AGG_INT_MODE_5 0xc41cc | |
a2fbb9ea ET |
4375 | /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ |
4376 | #define USDM_REG_CFC_RSP_START_ADDR 0xc4008 | |
4377 | /* [RW 16] The maximum value of the competion counter #0 */ | |
4378 | #define USDM_REG_CMP_COUNTER_MAX0 0xc401c | |
4379 | /* [RW 16] The maximum value of the competion counter #1 */ | |
4380 | #define USDM_REG_CMP_COUNTER_MAX1 0xc4020 | |
4381 | /* [RW 16] The maximum value of the competion counter #2 */ | |
4382 | #define USDM_REG_CMP_COUNTER_MAX2 0xc4024 | |
4383 | /* [RW 16] The maximum value of the competion counter #3 */ | |
4384 | #define USDM_REG_CMP_COUNTER_MAX3 0xc4028 | |
4385 | /* [RW 13] The start address in the internal RAM for the completion | |
4386 | counters. */ | |
4387 | #define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c | |
4388 | #define USDM_REG_ENABLE_IN1 0xc4238 | |
4389 | #define USDM_REG_ENABLE_IN2 0xc423c | |
4390 | #define USDM_REG_ENABLE_OUT1 0xc4240 | |
4391 | #define USDM_REG_ENABLE_OUT2 0xc4244 | |
4392 | /* [RW 4] The initial number of messages that can be sent to the pxp control | |
4393 | interface without receiving any ACK. */ | |
4394 | #define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0 | |
4395 | /* [ST 32] The number of ACK after placement messages received */ | |
4396 | #define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280 | |
4397 | /* [ST 32] The number of packet end messages received from the parser */ | |
4398 | #define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278 | |
4399 | /* [ST 32] The number of requests received from the pxp async if */ | |
4400 | #define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c | |
4401 | /* [ST 32] The number of commands received in queue 0 */ | |
4402 | #define USDM_REG_NUM_OF_Q0_CMD 0xc4248 | |
4403 | /* [ST 32] The number of commands received in queue 10 */ | |
4404 | #define USDM_REG_NUM_OF_Q10_CMD 0xc4270 | |
4405 | /* [ST 32] The number of commands received in queue 11 */ | |
4406 | #define USDM_REG_NUM_OF_Q11_CMD 0xc4274 | |
4407 | /* [ST 32] The number of commands received in queue 1 */ | |
4408 | #define USDM_REG_NUM_OF_Q1_CMD 0xc424c | |
4409 | /* [ST 32] The number of commands received in queue 2 */ | |
4410 | #define USDM_REG_NUM_OF_Q2_CMD 0xc4250 | |
4411 | /* [ST 32] The number of commands received in queue 3 */ | |
4412 | #define USDM_REG_NUM_OF_Q3_CMD 0xc4254 | |
4413 | /* [ST 32] The number of commands received in queue 4 */ | |
4414 | #define USDM_REG_NUM_OF_Q4_CMD 0xc4258 | |
4415 | /* [ST 32] The number of commands received in queue 5 */ | |
4416 | #define USDM_REG_NUM_OF_Q5_CMD 0xc425c | |
4417 | /* [ST 32] The number of commands received in queue 6 */ | |
4418 | #define USDM_REG_NUM_OF_Q6_CMD 0xc4260 | |
4419 | /* [ST 32] The number of commands received in queue 7 */ | |
4420 | #define USDM_REG_NUM_OF_Q7_CMD 0xc4264 | |
4421 | /* [ST 32] The number of commands received in queue 8 */ | |
4422 | #define USDM_REG_NUM_OF_Q8_CMD 0xc4268 | |
4423 | /* [ST 32] The number of commands received in queue 9 */ | |
4424 | #define USDM_REG_NUM_OF_Q9_CMD 0xc426c | |
4425 | /* [RW 13] The start address in the internal RAM for the packet end message */ | |
4426 | #define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014 | |
4427 | /* [RW 13] The start address in the internal RAM for queue counters */ | |
4428 | #define USDM_REG_Q_COUNTER_START_ADDR 0xc4010 | |
4429 | /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ | |
4430 | #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550 | |
4431 | /* [R 1] parser fifo empty in sdm_sync block */ | |
4432 | #define USDM_REG_SYNC_PARSER_EMPTY 0xc4558 | |
4433 | /* [R 1] parser serial fifo empty in sdm_sync block */ | |
4434 | #define USDM_REG_SYNC_SYNC_EMPTY 0xc4560 | |
4435 | /* [RW 32] Tick for timer counter. Applicable only when | |
4436 | ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */ | |
4437 | #define USDM_REG_TIMER_TICK 0xc4000 | |
4438 | /* [RW 32] Interrupt mask register #0 read/write */ | |
4439 | #define USDM_REG_USDM_INT_MASK_0 0xc42a0 | |
4440 | #define USDM_REG_USDM_INT_MASK_1 0xc42b0 | |
c18487ee YR |
4441 | /* [R 32] Interrupt register #0 read */ |
4442 | #define USDM_REG_USDM_INT_STS_0 0xc4294 | |
4443 | #define USDM_REG_USDM_INT_STS_1 0xc42a4 | |
a2fbb9ea ET |
4444 | /* [RW 11] Parity mask register #0 read/write */ |
4445 | #define USDM_REG_USDM_PRTY_MASK 0xc42c0 | |
f1410647 ET |
4446 | /* [R 11] Parity register #0 read */ |
4447 | #define USDM_REG_USDM_PRTY_STS 0xc42b4 | |
a2fbb9ea ET |
4448 | /* [RW 5] The number of time_slots in the arbitration cycle */ |
4449 | #define USEM_REG_ARB_CYCLE_SIZE 0x300034 | |
4450 | /* [RW 3] The source that is associated with arbitration element 0. Source | |
4451 | decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- | |
4452 | sleeping thread with priority 1; 4- sleeping thread with priority 2 */ | |
4453 | #define USEM_REG_ARB_ELEMENT0 0x300020 | |
4454 | /* [RW 3] The source that is associated with arbitration element 1. Source | |
4455 | decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- | |
4456 | sleeping thread with priority 1; 4- sleeping thread with priority 2. | |
4457 | Could not be equal to register ~usem_registers_arb_element0.arb_element0 */ | |
4458 | #define USEM_REG_ARB_ELEMENT1 0x300024 | |
4459 | /* [RW 3] The source that is associated with arbitration element 2. Source | |
4460 | decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- | |
4461 | sleeping thread with priority 1; 4- sleeping thread with priority 2. | |
4462 | Could not be equal to register ~usem_registers_arb_element0.arb_element0 | |
4463 | and ~usem_registers_arb_element1.arb_element1 */ | |
4464 | #define USEM_REG_ARB_ELEMENT2 0x300028 | |
4465 | /* [RW 3] The source that is associated with arbitration element 3. Source | |
4466 | decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- | |
4467 | sleeping thread with priority 1; 4- sleeping thread with priority 2.Could | |
4468 | not be equal to register ~usem_registers_arb_element0.arb_element0 and | |
4469 | ~usem_registers_arb_element1.arb_element1 and | |
4470 | ~usem_registers_arb_element2.arb_element2 */ | |
4471 | #define USEM_REG_ARB_ELEMENT3 0x30002c | |
4472 | /* [RW 3] The source that is associated with arbitration element 4. Source | |
4473 | decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- | |
4474 | sleeping thread with priority 1; 4- sleeping thread with priority 2. | |
4475 | Could not be equal to register ~usem_registers_arb_element0.arb_element0 | |
4476 | and ~usem_registers_arb_element1.arb_element1 and | |
4477 | ~usem_registers_arb_element2.arb_element2 and | |
4478 | ~usem_registers_arb_element3.arb_element3 */ | |
4479 | #define USEM_REG_ARB_ELEMENT4 0x300030 | |
4480 | #define USEM_REG_ENABLE_IN 0x3000a4 | |
4481 | #define USEM_REG_ENABLE_OUT 0x3000a8 | |
4482 | /* [RW 32] This address space contains all registers and memories that are | |
4483 | placed in SEM_FAST block. The SEM_FAST registers are described in | |
c18487ee YR |
4484 | appendix B. In order to access the sem_fast registers the base address |
4485 | ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ | |
a2fbb9ea ET |
4486 | #define USEM_REG_FAST_MEMORY 0x320000 |
4487 | /* [RW 1] Disables input messages from FIC0 May be updated during run_time | |
4488 | by the microcode */ | |
4489 | #define USEM_REG_FIC0_DISABLE 0x300224 | |
4490 | /* [RW 1] Disables input messages from FIC1 May be updated during run_time | |
4491 | by the microcode */ | |
4492 | #define USEM_REG_FIC1_DISABLE 0x300234 | |
4493 | /* [RW 15] Interrupt table Read and write access to it is not possible in | |
4494 | the middle of the work */ | |
4495 | #define USEM_REG_INT_TABLE 0x300400 | |
4496 | /* [ST 24] Statistics register. The number of messages that entered through | |
4497 | FIC0 */ | |
4498 | #define USEM_REG_MSG_NUM_FIC0 0x300000 | |
4499 | /* [ST 24] Statistics register. The number of messages that entered through | |
4500 | FIC1 */ | |
4501 | #define USEM_REG_MSG_NUM_FIC1 0x300004 | |
4502 | /* [ST 24] Statistics register. The number of messages that were sent to | |
4503 | FOC0 */ | |
4504 | #define USEM_REG_MSG_NUM_FOC0 0x300008 | |
4505 | /* [ST 24] Statistics register. The number of messages that were sent to | |
4506 | FOC1 */ | |
4507 | #define USEM_REG_MSG_NUM_FOC1 0x30000c | |
4508 | /* [ST 24] Statistics register. The number of messages that were sent to | |
4509 | FOC2 */ | |
4510 | #define USEM_REG_MSG_NUM_FOC2 0x300010 | |
4511 | /* [ST 24] Statistics register. The number of messages that were sent to | |
4512 | FOC3 */ | |
4513 | #define USEM_REG_MSG_NUM_FOC3 0x300014 | |
4514 | /* [RW 1] Disables input messages from the passive buffer May be updated | |
4515 | during run_time by the microcode */ | |
4516 | #define USEM_REG_PAS_DISABLE 0x30024c | |
4517 | /* [WB 128] Debug only. Passive buffer memory */ | |
4518 | #define USEM_REG_PASSIVE_BUFFER 0x302000 | |
4519 | /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ | |
4520 | #define USEM_REG_PRAM 0x340000 | |
4521 | /* [R 16] Valid sleeping threads indication have bit per thread */ | |
4522 | #define USEM_REG_SLEEP_THREADS_VALID 0x30026c | |
4523 | /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ | |
4524 | #define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0 | |
4525 | /* [RW 16] List of free threads . There is a bit per thread. */ | |
4526 | #define USEM_REG_THREADS_LIST 0x3002e4 | |
4527 | /* [RW 3] The arbitration scheme of time_slot 0 */ | |
4528 | #define USEM_REG_TS_0_AS 0x300038 | |
4529 | /* [RW 3] The arbitration scheme of time_slot 10 */ | |
4530 | #define USEM_REG_TS_10_AS 0x300060 | |
4531 | /* [RW 3] The arbitration scheme of time_slot 11 */ | |
4532 | #define USEM_REG_TS_11_AS 0x300064 | |
4533 | /* [RW 3] The arbitration scheme of time_slot 12 */ | |
4534 | #define USEM_REG_TS_12_AS 0x300068 | |
4535 | /* [RW 3] The arbitration scheme of time_slot 13 */ | |
4536 | #define USEM_REG_TS_13_AS 0x30006c | |
4537 | /* [RW 3] The arbitration scheme of time_slot 14 */ | |
4538 | #define USEM_REG_TS_14_AS 0x300070 | |
4539 | /* [RW 3] The arbitration scheme of time_slot 15 */ | |
4540 | #define USEM_REG_TS_15_AS 0x300074 | |
4541 | /* [RW 3] The arbitration scheme of time_slot 16 */ | |
4542 | #define USEM_REG_TS_16_AS 0x300078 | |
4543 | /* [RW 3] The arbitration scheme of time_slot 17 */ | |
4544 | #define USEM_REG_TS_17_AS 0x30007c | |
4545 | /* [RW 3] The arbitration scheme of time_slot 18 */ | |
4546 | #define USEM_REG_TS_18_AS 0x300080 | |
4547 | /* [RW 3] The arbitration scheme of time_slot 1 */ | |
4548 | #define USEM_REG_TS_1_AS 0x30003c | |
4549 | /* [RW 3] The arbitration scheme of time_slot 2 */ | |
4550 | #define USEM_REG_TS_2_AS 0x300040 | |
4551 | /* [RW 3] The arbitration scheme of time_slot 3 */ | |
4552 | #define USEM_REG_TS_3_AS 0x300044 | |
4553 | /* [RW 3] The arbitration scheme of time_slot 4 */ | |
4554 | #define USEM_REG_TS_4_AS 0x300048 | |
4555 | /* [RW 3] The arbitration scheme of time_slot 5 */ | |
4556 | #define USEM_REG_TS_5_AS 0x30004c | |
4557 | /* [RW 3] The arbitration scheme of time_slot 6 */ | |
4558 | #define USEM_REG_TS_6_AS 0x300050 | |
4559 | /* [RW 3] The arbitration scheme of time_slot 7 */ | |
4560 | #define USEM_REG_TS_7_AS 0x300054 | |
4561 | /* [RW 3] The arbitration scheme of time_slot 8 */ | |
4562 | #define USEM_REG_TS_8_AS 0x300058 | |
4563 | /* [RW 3] The arbitration scheme of time_slot 9 */ | |
4564 | #define USEM_REG_TS_9_AS 0x30005c | |
4565 | /* [RW 32] Interrupt mask register #0 read/write */ | |
4566 | #define USEM_REG_USEM_INT_MASK_0 0x300110 | |
4567 | #define USEM_REG_USEM_INT_MASK_1 0x300120 | |
c18487ee YR |
4568 | /* [R 32] Interrupt register #0 read */ |
4569 | #define USEM_REG_USEM_INT_STS_0 0x300104 | |
4570 | #define USEM_REG_USEM_INT_STS_1 0x300114 | |
a2fbb9ea ET |
4571 | /* [RW 32] Parity mask register #0 read/write */ |
4572 | #define USEM_REG_USEM_PRTY_MASK_0 0x300130 | |
4573 | #define USEM_REG_USEM_PRTY_MASK_1 0x300140 | |
f1410647 ET |
4574 | /* [R 32] Parity register #0 read */ |
4575 | #define USEM_REG_USEM_PRTY_STS_0 0x300124 | |
4576 | #define USEM_REG_USEM_PRTY_STS_1 0x300134 | |
a2fbb9ea ET |
4577 | /* [RW 2] The queue index for registration on Aux1 counter flag. */ |
4578 | #define XCM_REG_AUX1_Q 0x20134 | |
4579 | /* [RW 2] Per each decision rule the queue index to register to. */ | |
4580 | #define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0 | |
4581 | /* [R 5] Used to read the XX protection CAM occupancy counter. */ | |
4582 | #define XCM_REG_CAM_OCCUP 0x20244 | |
4583 | /* [RW 1] CDU AG read Interface enable. If 0 - the request input is | |
4584 | disregarded; valid output is deasserted; all other signals are treated as | |
4585 | usual; if 1 - normal activity. */ | |
4586 | #define XCM_REG_CDU_AG_RD_IFEN 0x20044 | |
4587 | /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input | |
4588 | are disregarded; all other signals are treated as usual; if 1 - normal | |
4589 | activity. */ | |
4590 | #define XCM_REG_CDU_AG_WR_IFEN 0x20040 | |
4591 | /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is | |
4592 | disregarded; valid output is deasserted; all other signals are treated as | |
4593 | usual; if 1 - normal activity. */ | |
4594 | #define XCM_REG_CDU_SM_RD_IFEN 0x2004c | |
4595 | /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid | |
4596 | input is disregarded; all other signals are treated as usual; if 1 - | |
4597 | normal activity. */ | |
4598 | #define XCM_REG_CDU_SM_WR_IFEN 0x20048 | |
4599 | /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes | |
4600 | the initial credit value; read returns the current value of the credit | |
4601 | counter. Must be initialized to 1 at start-up. */ | |
4602 | #define XCM_REG_CFC_INIT_CRD 0x20404 | |
4603 | /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for | |
4604 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
4605 | prioritised); 2 stands for weight 2; tc. */ | |
4606 | #define XCM_REG_CP_WEIGHT 0x200dc | |
4607 | /* [RW 1] Input csem Interface enable. If 0 - the valid input is | |
4608 | disregarded; acknowledge output is deasserted; all other signals are | |
4609 | treated as usual; if 1 - normal activity. */ | |
4610 | #define XCM_REG_CSEM_IFEN 0x20028 | |
4611 | /* [RC 1] Set at message length mismatch (relative to last indication) at | |
4612 | the csem interface. */ | |
4613 | #define XCM_REG_CSEM_LENGTH_MIS 0x20228 | |
4614 | /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for | |
4615 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
4616 | prioritised); 2 stands for weight 2; tc. */ | |
4617 | #define XCM_REG_CSEM_WEIGHT 0x200c4 | |
4618 | /* [RW 1] Input dorq Interface enable. If 0 - the valid input is | |
4619 | disregarded; acknowledge output is deasserted; all other signals are | |
4620 | treated as usual; if 1 - normal activity. */ | |
4621 | #define XCM_REG_DORQ_IFEN 0x20030 | |
4622 | /* [RC 1] Set at message length mismatch (relative to last indication) at | |
4623 | the dorq interface. */ | |
4624 | #define XCM_REG_DORQ_LENGTH_MIS 0x20230 | |
8d9c5f34 EG |
4625 | /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for |
4626 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
4627 | prioritised); 2 stands for weight 2; tc. */ | |
4628 | #define XCM_REG_DORQ_WEIGHT 0x200cc | |
a2fbb9ea ET |
4629 | /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */ |
4630 | #define XCM_REG_ERR_EVNT_ID 0x200b0 | |
4631 | /* [RW 28] The CM erroneous header for QM and Timers formatting. */ | |
4632 | #define XCM_REG_ERR_XCM_HDR 0x200ac | |
4633 | /* [RW 8] The Event ID for Timers expiration. */ | |
4634 | #define XCM_REG_EXPR_EVNT_ID 0x200b4 | |
4635 | /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write | |
4636 | writes the initial credit value; read returns the current value of the | |
4637 | credit counter. Must be initialized to 64 at start-up. */ | |
4638 | #define XCM_REG_FIC0_INIT_CRD 0x2040c | |
4639 | /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write | |
4640 | writes the initial credit value; read returns the current value of the | |
4641 | credit counter. Must be initialized to 64 at start-up. */ | |
4642 | #define XCM_REG_FIC1_INIT_CRD 0x20410 | |
a2fbb9ea ET |
4643 | #define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118 |
4644 | #define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c | |
a2fbb9ea ET |
4645 | #define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108 |
4646 | #define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c | |
4647 | /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1 | |
4648 | - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr; | |
4649 | ~xcm_registers_gr_ld0_pr.gr_ld0_pr and | |
4650 | ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */ | |
4651 | #define XCM_REG_GR_ARB_TYPE 0x2020c | |
4652 | /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the | |
4653 | highest priority is 3. It is supposed that the Channel group is the | |
4654 | compliment of the other 3 groups. */ | |
4655 | #define XCM_REG_GR_LD0_PR 0x20214 | |
4656 | /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the | |
4657 | highest priority is 3. It is supposed that the Channel group is the | |
4658 | compliment of the other 3 groups. */ | |
4659 | #define XCM_REG_GR_LD1_PR 0x20218 | |
4660 | /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is | |
4661 | disregarded; acknowledge output is deasserted; all other signals are | |
4662 | treated as usual; if 1 - normal activity. */ | |
4663 | #define XCM_REG_NIG0_IFEN 0x20038 | |
4664 | /* [RC 1] Set at message length mismatch (relative to last indication) at | |
4665 | the nig0 interface. */ | |
4666 | #define XCM_REG_NIG0_LENGTH_MIS 0x20238 | |
8d9c5f34 EG |
4667 | /* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for |
4668 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
4669 | prioritised); 2 stands for weight 2; tc. */ | |
4670 | #define XCM_REG_NIG0_WEIGHT 0x200d4 | |
a2fbb9ea ET |
4671 | /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is |
4672 | disregarded; acknowledge output is deasserted; all other signals are | |
4673 | treated as usual; if 1 - normal activity. */ | |
4674 | #define XCM_REG_NIG1_IFEN 0x2003c | |
4675 | /* [RC 1] Set at message length mismatch (relative to last indication) at | |
4676 | the nig1 interface. */ | |
4677 | #define XCM_REG_NIG1_LENGTH_MIS 0x2023c | |
4678 | /* [RW 3] The weight of the input nig1 in the WRR mechanism. 0 stands for | |
4679 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
4680 | prioritised); 2 stands for weight 2; tc. */ | |
4681 | #define XCM_REG_NIG1_WEIGHT 0x200d8 | |
4682 | /* [RW 5] The number of double REG-pairs; loaded from the STORM context and | |
4683 | sent to STORM; for a specific connection type. The double REG-pairs are | |
4684 | used in order to align to STORM context row size of 128 bits. The offset | |
4685 | of these data in the STORM context is always 0. Index _i stands for the | |
4686 | connection type (one of 16). */ | |
4687 | #define XCM_REG_N_SM_CTX_LD_0 0x20060 | |
4688 | #define XCM_REG_N_SM_CTX_LD_1 0x20064 | |
4689 | #define XCM_REG_N_SM_CTX_LD_10 0x20088 | |
4690 | #define XCM_REG_N_SM_CTX_LD_11 0x2008c | |
4691 | #define XCM_REG_N_SM_CTX_LD_12 0x20090 | |
4692 | #define XCM_REG_N_SM_CTX_LD_13 0x20094 | |
4693 | #define XCM_REG_N_SM_CTX_LD_14 0x20098 | |
4694 | #define XCM_REG_N_SM_CTX_LD_15 0x2009c | |
4695 | #define XCM_REG_N_SM_CTX_LD_2 0x20068 | |
4696 | #define XCM_REG_N_SM_CTX_LD_3 0x2006c | |
4697 | #define XCM_REG_N_SM_CTX_LD_4 0x20070 | |
c18487ee | 4698 | #define XCM_REG_N_SM_CTX_LD_5 0x20074 |
a2fbb9ea ET |
4699 | /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; |
4700 | acknowledge output is deasserted; all other signals are treated as usual; | |
4701 | if 1 - normal activity. */ | |
4702 | #define XCM_REG_PBF_IFEN 0x20034 | |
4703 | /* [RC 1] Set at message length mismatch (relative to last indication) at | |
4704 | the pbf interface. */ | |
4705 | #define XCM_REG_PBF_LENGTH_MIS 0x20234 | |
4706 | /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for | |
4707 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
4708 | prioritised); 2 stands for weight 2; tc. */ | |
4709 | #define XCM_REG_PBF_WEIGHT 0x200d0 | |
c18487ee YR |
4710 | #define XCM_REG_PHYS_QNUM3_0 0x20100 |
4711 | #define XCM_REG_PHYS_QNUM3_1 0x20104 | |
a2fbb9ea ET |
4712 | /* [RW 8] The Event ID for Timers formatting in case of stop done. */ |
4713 | #define XCM_REG_STOP_EVNT_ID 0x200b8 | |
4714 | /* [RC 1] Set at message length mismatch (relative to last indication) at | |
4715 | the STORM interface. */ | |
4716 | #define XCM_REG_STORM_LENGTH_MIS 0x2021c | |
4717 | /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for | |
4718 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
4719 | prioritised); 2 stands for weight 2; tc. */ | |
4720 | #define XCM_REG_STORM_WEIGHT 0x200bc | |
4721 | /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is | |
4722 | disregarded; acknowledge output is deasserted; all other signals are | |
4723 | treated as usual; if 1 - normal activity. */ | |
4724 | #define XCM_REG_STORM_XCM_IFEN 0x20010 | |
4725 | /* [RW 4] Timers output initial credit. Max credit available - 15.Write | |
4726 | writes the initial credit value; read returns the current value of the | |
4727 | credit counter. Must be initialized to 4 at start-up. */ | |
4728 | #define XCM_REG_TM_INIT_CRD 0x2041c | |
8d9c5f34 EG |
4729 | /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for |
4730 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
4731 | prioritised); 2 stands for weight 2; tc. */ | |
4732 | #define XCM_REG_TM_WEIGHT 0x200ec | |
a2fbb9ea ET |
4733 | /* [RW 28] The CM header for Timers expiration command. */ |
4734 | #define XCM_REG_TM_XCM_HDR 0x200a8 | |
4735 | /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is | |
4736 | disregarded; acknowledge output is deasserted; all other signals are | |
4737 | treated as usual; if 1 - normal activity. */ | |
4738 | #define XCM_REG_TM_XCM_IFEN 0x2001c | |
4739 | /* [RW 1] Input tsem Interface enable. If 0 - the valid input is | |
4740 | disregarded; acknowledge output is deasserted; all other signals are | |
4741 | treated as usual; if 1 - normal activity. */ | |
4742 | #define XCM_REG_TSEM_IFEN 0x20024 | |
4743 | /* [RC 1] Set at message length mismatch (relative to last indication) at | |
4744 | the tsem interface. */ | |
4745 | #define XCM_REG_TSEM_LENGTH_MIS 0x20224 | |
4746 | /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for | |
4747 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
4748 | prioritised); 2 stands for weight 2; tc. */ | |
4749 | #define XCM_REG_TSEM_WEIGHT 0x200c0 | |
4750 | /* [RW 2] The queue index for registration on UNA greater NXT decision rule. */ | |
4751 | #define XCM_REG_UNA_GT_NXT_Q 0x20120 | |
4752 | /* [RW 1] Input usem Interface enable. If 0 - the valid input is | |
4753 | disregarded; acknowledge output is deasserted; all other signals are | |
4754 | treated as usual; if 1 - normal activity. */ | |
4755 | #define XCM_REG_USEM_IFEN 0x2002c | |
4756 | /* [RC 1] Message length mismatch (relative to last indication) at the usem | |
4757 | interface. */ | |
4758 | #define XCM_REG_USEM_LENGTH_MIS 0x2022c | |
4759 | /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for | |
4760 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
4761 | prioritised); 2 stands for weight 2; tc. */ | |
4762 | #define XCM_REG_USEM_WEIGHT 0x200c8 | |
a2fbb9ea | 4763 | #define XCM_REG_WU_DA_CNT_CMD00 0x201d4 |
a2fbb9ea | 4764 | #define XCM_REG_WU_DA_CNT_CMD01 0x201d8 |
a2fbb9ea | 4765 | #define XCM_REG_WU_DA_CNT_CMD10 0x201dc |
a2fbb9ea | 4766 | #define XCM_REG_WU_DA_CNT_CMD11 0x201e0 |
a2fbb9ea | 4767 | #define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4 |
a2fbb9ea | 4768 | #define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8 |
a2fbb9ea | 4769 | #define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec |
a2fbb9ea | 4770 | #define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0 |
a2fbb9ea | 4771 | #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4 |
a2fbb9ea | 4772 | #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8 |
a2fbb9ea | 4773 | #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc |
a2fbb9ea ET |
4774 | #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0 |
4775 | /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; | |
4776 | acknowledge output is deasserted; all other signals are treated as usual; | |
4777 | if 1 - normal activity. */ | |
4778 | #define XCM_REG_XCM_CFC_IFEN 0x20050 | |
4779 | /* [RW 14] Interrupt mask register #0 read/write */ | |
4780 | #define XCM_REG_XCM_INT_MASK 0x202b4 | |
4781 | /* [R 14] Interrupt register #0 read */ | |
4782 | #define XCM_REG_XCM_INT_STS 0x202a8 | |
c18487ee YR |
4783 | /* [R 30] Parity register #0 read */ |
4784 | #define XCM_REG_XCM_PRTY_STS 0x202b8 | |
a2fbb9ea ET |
4785 | /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS |
4786 | REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). | |
4787 | Is used to determine the number of the AG context REG-pairs written back; | |
4788 | when the Reg1WbFlg isn't set. */ | |
4789 | #define XCM_REG_XCM_REG0_SZ 0x200f4 | |
4790 | /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is | |
4791 | disregarded; valid is deasserted; all other signals are treated as usual; | |
4792 | if 1 - normal activity. */ | |
4793 | #define XCM_REG_XCM_STORM0_IFEN 0x20004 | |
4794 | /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is | |
4795 | disregarded; valid is deasserted; all other signals are treated as usual; | |
4796 | if 1 - normal activity. */ | |
4797 | #define XCM_REG_XCM_STORM1_IFEN 0x20008 | |
4798 | /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is | |
4799 | disregarded; acknowledge output is deasserted; all other signals are | |
4800 | treated as usual; if 1 - normal activity. */ | |
4801 | #define XCM_REG_XCM_TM_IFEN 0x20020 | |
4802 | /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is | |
4803 | disregarded; valid is deasserted; all other signals are treated as usual; | |
4804 | if 1 - normal activity. */ | |
4805 | #define XCM_REG_XCM_XQM_IFEN 0x2000c | |
4806 | /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ | |
4807 | #define XCM_REG_XCM_XQM_USE_Q 0x200f0 | |
4808 | /* [RW 4] The value by which CFC updates the activity counter at QM bypass. */ | |
4809 | #define XCM_REG_XQM_BYP_ACT_UPD 0x200fc | |
4810 | /* [RW 6] QM output initial credit. Max credit available - 32.Write writes | |
4811 | the initial credit value; read returns the current value of the credit | |
4812 | counter. Must be initialized to 32 at start-up. */ | |
4813 | #define XCM_REG_XQM_INIT_CRD 0x20420 | |
4814 | /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 | |
4815 | stands for weight 8 (the most prioritised); 1 stands for weight 1(least | |
4816 | prioritised); 2 stands for weight 2; tc. */ | |
4817 | #define XCM_REG_XQM_P_WEIGHT 0x200e4 | |
8d9c5f34 EG |
4818 | /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 |
4819 | stands for weight 8 (the most prioritised); 1 stands for weight 1(least | |
4820 | prioritised); 2 stands for weight 2; tc. */ | |
4821 | #define XCM_REG_XQM_S_WEIGHT 0x200e8 | |
a2fbb9ea ET |
4822 | /* [RW 28] The CM header value for QM request (primary). */ |
4823 | #define XCM_REG_XQM_XCM_HDR_P 0x200a0 | |
4824 | /* [RW 28] The CM header value for QM request (secondary). */ | |
4825 | #define XCM_REG_XQM_XCM_HDR_S 0x200a4 | |
4826 | /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; | |
4827 | acknowledge output is deasserted; all other signals are treated as usual; | |
4828 | if 1 - normal activity. */ | |
4829 | #define XCM_REG_XQM_XCM_IFEN 0x20014 | |
4830 | /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; | |
4831 | acknowledge output is deasserted; all other signals are treated as usual; | |
4832 | if 1 - normal activity. */ | |
4833 | #define XCM_REG_XSDM_IFEN 0x20018 | |
4834 | /* [RC 1] Set at message length mismatch (relative to last indication) at | |
4835 | the SDM interface. */ | |
4836 | #define XCM_REG_XSDM_LENGTH_MIS 0x20220 | |
4837 | /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for | |
4838 | weight 8 (the most prioritised); 1 stands for weight 1(least | |
4839 | prioritised); 2 stands for weight 2; tc. */ | |
4840 | #define XCM_REG_XSDM_WEIGHT 0x200e0 | |
4841 | /* [RW 17] Indirect access to the descriptor table of the XX protection | |
4842 | mechanism. The fields are: [5:0] - message length; 11:6] - message | |
4843 | pointer; 16:12] - next pointer. */ | |
4844 | #define XCM_REG_XX_DESCR_TABLE 0x20480 | |
c18487ee | 4845 | #define XCM_REG_XX_DESCR_TABLE_SIZE 32 |
a2fbb9ea ET |
4846 | /* [R 6] Used to read the XX protection Free counter. */ |
4847 | #define XCM_REG_XX_FREE 0x20240 | |
4848 | /* [RW 6] Initial value for the credit counter; responsible for fulfilling | |
4849 | of the Input Stage XX protection buffer by the XX protection pending | |
4850 | messages. Max credit available - 3.Write writes the initial credit value; | |
4851 | read returns the current value of the credit counter. Must be initialized | |
4852 | to 2 at start-up. */ | |
4853 | #define XCM_REG_XX_INIT_CRD 0x20424 | |
4854 | /* [RW 6] The maximum number of pending messages; which may be stored in XX | |
4855 | protection. ~xcm_registers_xx_free.xx_free read on read. */ | |
4856 | #define XCM_REG_XX_MSG_NUM 0x20428 | |
4857 | /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ | |
4858 | #define XCM_REG_XX_OVFL_EVNT_ID 0x20058 | |
c18487ee | 4859 | /* [RW 16] Indirect access to the XX table of the XX protection mechanism. |
a2fbb9ea ET |
4860 | The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] - |
4861 | header pointer. */ | |
4862 | #define XCM_REG_XX_TABLE 0x20500 | |
4863 | /* [RW 8] The event id for aggregated interrupt 0 */ | |
4864 | #define XSDM_REG_AGG_INT_EVENT_0 0x166038 | |
4865 | #define XSDM_REG_AGG_INT_EVENT_1 0x16603c | |
4866 | #define XSDM_REG_AGG_INT_EVENT_10 0x166060 | |
4867 | #define XSDM_REG_AGG_INT_EVENT_11 0x166064 | |
4868 | #define XSDM_REG_AGG_INT_EVENT_12 0x166068 | |
4869 | #define XSDM_REG_AGG_INT_EVENT_13 0x16606c | |
4870 | #define XSDM_REG_AGG_INT_EVENT_14 0x166070 | |
4871 | #define XSDM_REG_AGG_INT_EVENT_15 0x166074 | |
4872 | #define XSDM_REG_AGG_INT_EVENT_16 0x166078 | |
4873 | #define XSDM_REG_AGG_INT_EVENT_17 0x16607c | |
4874 | #define XSDM_REG_AGG_INT_EVENT_18 0x166080 | |
4875 | #define XSDM_REG_AGG_INT_EVENT_19 0x166084 | |
c18487ee YR |
4876 | #define XSDM_REG_AGG_INT_EVENT_10 0x166060 |
4877 | #define XSDM_REG_AGG_INT_EVENT_11 0x166064 | |
4878 | #define XSDM_REG_AGG_INT_EVENT_12 0x166068 | |
8d9c5f34 EG |
4879 | #define XSDM_REG_AGG_INT_EVENT_13 0x16606c |
4880 | #define XSDM_REG_AGG_INT_EVENT_14 0x166070 | |
a2fbb9ea ET |
4881 | #define XSDM_REG_AGG_INT_EVENT_2 0x166040 |
4882 | #define XSDM_REG_AGG_INT_EVENT_20 0x166088 | |
4883 | #define XSDM_REG_AGG_INT_EVENT_21 0x16608c | |
4884 | #define XSDM_REG_AGG_INT_EVENT_22 0x166090 | |
4885 | #define XSDM_REG_AGG_INT_EVENT_23 0x166094 | |
4886 | #define XSDM_REG_AGG_INT_EVENT_24 0x166098 | |
4887 | #define XSDM_REG_AGG_INT_EVENT_25 0x16609c | |
4888 | #define XSDM_REG_AGG_INT_EVENT_26 0x1660a0 | |
4889 | #define XSDM_REG_AGG_INT_EVENT_27 0x1660a4 | |
4890 | #define XSDM_REG_AGG_INT_EVENT_28 0x1660a8 | |
4891 | #define XSDM_REG_AGG_INT_EVENT_29 0x1660ac | |
c18487ee YR |
4892 | #define XSDM_REG_AGG_INT_EVENT_3 0x166044 |
4893 | #define XSDM_REG_AGG_INT_EVENT_30 0x1660b0 | |
4894 | #define XSDM_REG_AGG_INT_EVENT_31 0x1660b4 | |
4895 | #define XSDM_REG_AGG_INT_EVENT_4 0x166048 | |
4896 | #define XSDM_REG_AGG_INT_EVENT_5 0x16604c | |
4897 | #define XSDM_REG_AGG_INT_EVENT_6 0x166050 | |
4898 | #define XSDM_REG_AGG_INT_EVENT_7 0x166054 | |
4899 | #define XSDM_REG_AGG_INT_EVENT_8 0x166058 | |
4900 | #define XSDM_REG_AGG_INT_EVENT_9 0x16605c | |
a2fbb9ea ET |
4901 | /* [RW 1] For each aggregated interrupt index whether the mode is normal (0) |
4902 | or auto-mask-mode (1) */ | |
4903 | #define XSDM_REG_AGG_INT_MODE_0 0x1661b8 | |
4904 | #define XSDM_REG_AGG_INT_MODE_1 0x1661bc | |
4905 | #define XSDM_REG_AGG_INT_MODE_10 0x1661e0 | |
4906 | #define XSDM_REG_AGG_INT_MODE_11 0x1661e4 | |
4907 | #define XSDM_REG_AGG_INT_MODE_12 0x1661e8 | |
4908 | #define XSDM_REG_AGG_INT_MODE_13 0x1661ec | |
4909 | #define XSDM_REG_AGG_INT_MODE_14 0x1661f0 | |
4910 | #define XSDM_REG_AGG_INT_MODE_15 0x1661f4 | |
4911 | #define XSDM_REG_AGG_INT_MODE_16 0x1661f8 | |
4912 | #define XSDM_REG_AGG_INT_MODE_17 0x1661fc | |
4913 | #define XSDM_REG_AGG_INT_MODE_18 0x166200 | |
4914 | #define XSDM_REG_AGG_INT_MODE_19 0x166204 | |
4915 | /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ | |
4916 | #define XSDM_REG_CFC_RSP_START_ADDR 0x166008 | |
4917 | /* [RW 16] The maximum value of the competion counter #0 */ | |
4918 | #define XSDM_REG_CMP_COUNTER_MAX0 0x16601c | |
4919 | /* [RW 16] The maximum value of the competion counter #1 */ | |
4920 | #define XSDM_REG_CMP_COUNTER_MAX1 0x166020 | |
4921 | /* [RW 16] The maximum value of the competion counter #2 */ | |
4922 | #define XSDM_REG_CMP_COUNTER_MAX2 0x166024 | |
4923 | /* [RW 16] The maximum value of the competion counter #3 */ | |
4924 | #define XSDM_REG_CMP_COUNTER_MAX3 0x166028 | |
4925 | /* [RW 13] The start address in the internal RAM for the completion | |
4926 | counters. */ | |
4927 | #define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c | |
4928 | #define XSDM_REG_ENABLE_IN1 0x166238 | |
4929 | #define XSDM_REG_ENABLE_IN2 0x16623c | |
4930 | #define XSDM_REG_ENABLE_OUT1 0x166240 | |
4931 | #define XSDM_REG_ENABLE_OUT2 0x166244 | |
4932 | /* [RW 4] The initial number of messages that can be sent to the pxp control | |
4933 | interface without receiving any ACK. */ | |
4934 | #define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc | |
4935 | /* [ST 32] The number of ACK after placement messages received */ | |
4936 | #define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c | |
4937 | /* [ST 32] The number of packet end messages received from the parser */ | |
4938 | #define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274 | |
4939 | /* [ST 32] The number of requests received from the pxp async if */ | |
4940 | #define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278 | |
4941 | /* [ST 32] The number of commands received in queue 0 */ | |
4942 | #define XSDM_REG_NUM_OF_Q0_CMD 0x166248 | |
4943 | /* [ST 32] The number of commands received in queue 10 */ | |
4944 | #define XSDM_REG_NUM_OF_Q10_CMD 0x16626c | |
4945 | /* [ST 32] The number of commands received in queue 11 */ | |
4946 | #define XSDM_REG_NUM_OF_Q11_CMD 0x166270 | |
4947 | /* [ST 32] The number of commands received in queue 1 */ | |
4948 | #define XSDM_REG_NUM_OF_Q1_CMD 0x16624c | |
4949 | /* [ST 32] The number of commands received in queue 3 */ | |
4950 | #define XSDM_REG_NUM_OF_Q3_CMD 0x166250 | |
4951 | /* [ST 32] The number of commands received in queue 4 */ | |
4952 | #define XSDM_REG_NUM_OF_Q4_CMD 0x166254 | |
4953 | /* [ST 32] The number of commands received in queue 5 */ | |
4954 | #define XSDM_REG_NUM_OF_Q5_CMD 0x166258 | |
4955 | /* [ST 32] The number of commands received in queue 6 */ | |
4956 | #define XSDM_REG_NUM_OF_Q6_CMD 0x16625c | |
4957 | /* [ST 32] The number of commands received in queue 7 */ | |
4958 | #define XSDM_REG_NUM_OF_Q7_CMD 0x166260 | |
4959 | /* [ST 32] The number of commands received in queue 8 */ | |
4960 | #define XSDM_REG_NUM_OF_Q8_CMD 0x166264 | |
4961 | /* [ST 32] The number of commands received in queue 9 */ | |
4962 | #define XSDM_REG_NUM_OF_Q9_CMD 0x166268 | |
4963 | /* [RW 13] The start address in the internal RAM for queue counters */ | |
4964 | #define XSDM_REG_Q_COUNTER_START_ADDR 0x166010 | |
4965 | /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ | |
4966 | #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548 | |
4967 | /* [R 1] parser fifo empty in sdm_sync block */ | |
4968 | #define XSDM_REG_SYNC_PARSER_EMPTY 0x166550 | |
4969 | /* [R 1] parser serial fifo empty in sdm_sync block */ | |
4970 | #define XSDM_REG_SYNC_SYNC_EMPTY 0x166558 | |
4971 | /* [RW 32] Tick for timer counter. Applicable only when | |
4972 | ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */ | |
4973 | #define XSDM_REG_TIMER_TICK 0x166000 | |
4974 | /* [RW 32] Interrupt mask register #0 read/write */ | |
4975 | #define XSDM_REG_XSDM_INT_MASK_0 0x16629c | |
4976 | #define XSDM_REG_XSDM_INT_MASK_1 0x1662ac | |
c18487ee YR |
4977 | /* [R 32] Interrupt register #0 read */ |
4978 | #define XSDM_REG_XSDM_INT_STS_0 0x166290 | |
4979 | #define XSDM_REG_XSDM_INT_STS_1 0x1662a0 | |
a2fbb9ea ET |
4980 | /* [RW 11] Parity mask register #0 read/write */ |
4981 | #define XSDM_REG_XSDM_PRTY_MASK 0x1662bc | |
f1410647 ET |
4982 | /* [R 11] Parity register #0 read */ |
4983 | #define XSDM_REG_XSDM_PRTY_STS 0x1662b0 | |
a2fbb9ea ET |
4984 | /* [RW 5] The number of time_slots in the arbitration cycle */ |
4985 | #define XSEM_REG_ARB_CYCLE_SIZE 0x280034 | |
4986 | /* [RW 3] The source that is associated with arbitration element 0. Source | |
4987 | decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- | |
4988 | sleeping thread with priority 1; 4- sleeping thread with priority 2 */ | |
4989 | #define XSEM_REG_ARB_ELEMENT0 0x280020 | |
4990 | /* [RW 3] The source that is associated with arbitration element 1. Source | |
4991 | decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- | |
4992 | sleeping thread with priority 1; 4- sleeping thread with priority 2. | |
4993 | Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */ | |
4994 | #define XSEM_REG_ARB_ELEMENT1 0x280024 | |
4995 | /* [RW 3] The source that is associated with arbitration element 2. Source | |
4996 | decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- | |
4997 | sleeping thread with priority 1; 4- sleeping thread with priority 2. | |
4998 | Could not be equal to register ~xsem_registers_arb_element0.arb_element0 | |
4999 | and ~xsem_registers_arb_element1.arb_element1 */ | |
5000 | #define XSEM_REG_ARB_ELEMENT2 0x280028 | |
5001 | /* [RW 3] The source that is associated with arbitration element 3. Source | |
5002 | decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- | |
5003 | sleeping thread with priority 1; 4- sleeping thread with priority 2.Could | |
5004 | not be equal to register ~xsem_registers_arb_element0.arb_element0 and | |
5005 | ~xsem_registers_arb_element1.arb_element1 and | |
5006 | ~xsem_registers_arb_element2.arb_element2 */ | |
5007 | #define XSEM_REG_ARB_ELEMENT3 0x28002c | |
5008 | /* [RW 3] The source that is associated with arbitration element 4. Source | |
5009 | decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- | |
5010 | sleeping thread with priority 1; 4- sleeping thread with priority 2. | |
5011 | Could not be equal to register ~xsem_registers_arb_element0.arb_element0 | |
5012 | and ~xsem_registers_arb_element1.arb_element1 and | |
5013 | ~xsem_registers_arb_element2.arb_element2 and | |
5014 | ~xsem_registers_arb_element3.arb_element3 */ | |
5015 | #define XSEM_REG_ARB_ELEMENT4 0x280030 | |
5016 | #define XSEM_REG_ENABLE_IN 0x2800a4 | |
5017 | #define XSEM_REG_ENABLE_OUT 0x2800a8 | |
5018 | /* [RW 32] This address space contains all registers and memories that are | |
5019 | placed in SEM_FAST block. The SEM_FAST registers are described in | |
c18487ee YR |
5020 | appendix B. In order to access the sem_fast registers the base address |
5021 | ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ | |
a2fbb9ea ET |
5022 | #define XSEM_REG_FAST_MEMORY 0x2a0000 |
5023 | /* [RW 1] Disables input messages from FIC0 May be updated during run_time | |
5024 | by the microcode */ | |
5025 | #define XSEM_REG_FIC0_DISABLE 0x280224 | |
5026 | /* [RW 1] Disables input messages from FIC1 May be updated during run_time | |
5027 | by the microcode */ | |
5028 | #define XSEM_REG_FIC1_DISABLE 0x280234 | |
5029 | /* [RW 15] Interrupt table Read and write access to it is not possible in | |
5030 | the middle of the work */ | |
5031 | #define XSEM_REG_INT_TABLE 0x280400 | |
5032 | /* [ST 24] Statistics register. The number of messages that entered through | |
5033 | FIC0 */ | |
5034 | #define XSEM_REG_MSG_NUM_FIC0 0x280000 | |
5035 | /* [ST 24] Statistics register. The number of messages that entered through | |
5036 | FIC1 */ | |
5037 | #define XSEM_REG_MSG_NUM_FIC1 0x280004 | |
5038 | /* [ST 24] Statistics register. The number of messages that were sent to | |
5039 | FOC0 */ | |
5040 | #define XSEM_REG_MSG_NUM_FOC0 0x280008 | |
5041 | /* [ST 24] Statistics register. The number of messages that were sent to | |
5042 | FOC1 */ | |
5043 | #define XSEM_REG_MSG_NUM_FOC1 0x28000c | |
5044 | /* [ST 24] Statistics register. The number of messages that were sent to | |
5045 | FOC2 */ | |
5046 | #define XSEM_REG_MSG_NUM_FOC2 0x280010 | |
5047 | /* [ST 24] Statistics register. The number of messages that were sent to | |
5048 | FOC3 */ | |
5049 | #define XSEM_REG_MSG_NUM_FOC3 0x280014 | |
5050 | /* [RW 1] Disables input messages from the passive buffer May be updated | |
5051 | during run_time by the microcode */ | |
5052 | #define XSEM_REG_PAS_DISABLE 0x28024c | |
5053 | /* [WB 128] Debug only. Passive buffer memory */ | |
5054 | #define XSEM_REG_PASSIVE_BUFFER 0x282000 | |
5055 | /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ | |
5056 | #define XSEM_REG_PRAM 0x2c0000 | |
5057 | /* [R 16] Valid sleeping threads indication have bit per thread */ | |
5058 | #define XSEM_REG_SLEEP_THREADS_VALID 0x28026c | |
5059 | /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ | |
5060 | #define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0 | |
5061 | /* [RW 16] List of free threads . There is a bit per thread. */ | |
5062 | #define XSEM_REG_THREADS_LIST 0x2802e4 | |
5063 | /* [RW 3] The arbitration scheme of time_slot 0 */ | |
5064 | #define XSEM_REG_TS_0_AS 0x280038 | |
5065 | /* [RW 3] The arbitration scheme of time_slot 10 */ | |
5066 | #define XSEM_REG_TS_10_AS 0x280060 | |
5067 | /* [RW 3] The arbitration scheme of time_slot 11 */ | |
5068 | #define XSEM_REG_TS_11_AS 0x280064 | |
5069 | /* [RW 3] The arbitration scheme of time_slot 12 */ | |
5070 | #define XSEM_REG_TS_12_AS 0x280068 | |
5071 | /* [RW 3] The arbitration scheme of time_slot 13 */ | |
5072 | #define XSEM_REG_TS_13_AS 0x28006c | |
5073 | /* [RW 3] The arbitration scheme of time_slot 14 */ | |
5074 | #define XSEM_REG_TS_14_AS 0x280070 | |
5075 | /* [RW 3] The arbitration scheme of time_slot 15 */ | |
5076 | #define XSEM_REG_TS_15_AS 0x280074 | |
5077 | /* [RW 3] The arbitration scheme of time_slot 16 */ | |
5078 | #define XSEM_REG_TS_16_AS 0x280078 | |
5079 | /* [RW 3] The arbitration scheme of time_slot 17 */ | |
5080 | #define XSEM_REG_TS_17_AS 0x28007c | |
5081 | /* [RW 3] The arbitration scheme of time_slot 18 */ | |
5082 | #define XSEM_REG_TS_18_AS 0x280080 | |
5083 | /* [RW 3] The arbitration scheme of time_slot 1 */ | |
5084 | #define XSEM_REG_TS_1_AS 0x28003c | |
5085 | /* [RW 3] The arbitration scheme of time_slot 2 */ | |
5086 | #define XSEM_REG_TS_2_AS 0x280040 | |
5087 | /* [RW 3] The arbitration scheme of time_slot 3 */ | |
5088 | #define XSEM_REG_TS_3_AS 0x280044 | |
5089 | /* [RW 3] The arbitration scheme of time_slot 4 */ | |
5090 | #define XSEM_REG_TS_4_AS 0x280048 | |
5091 | /* [RW 3] The arbitration scheme of time_slot 5 */ | |
5092 | #define XSEM_REG_TS_5_AS 0x28004c | |
5093 | /* [RW 3] The arbitration scheme of time_slot 6 */ | |
5094 | #define XSEM_REG_TS_6_AS 0x280050 | |
5095 | /* [RW 3] The arbitration scheme of time_slot 7 */ | |
5096 | #define XSEM_REG_TS_7_AS 0x280054 | |
5097 | /* [RW 3] The arbitration scheme of time_slot 8 */ | |
5098 | #define XSEM_REG_TS_8_AS 0x280058 | |
5099 | /* [RW 3] The arbitration scheme of time_slot 9 */ | |
5100 | #define XSEM_REG_TS_9_AS 0x28005c | |
5101 | /* [RW 32] Interrupt mask register #0 read/write */ | |
5102 | #define XSEM_REG_XSEM_INT_MASK_0 0x280110 | |
5103 | #define XSEM_REG_XSEM_INT_MASK_1 0x280120 | |
c18487ee YR |
5104 | /* [R 32] Interrupt register #0 read */ |
5105 | #define XSEM_REG_XSEM_INT_STS_0 0x280104 | |
5106 | #define XSEM_REG_XSEM_INT_STS_1 0x280114 | |
a2fbb9ea ET |
5107 | /* [RW 32] Parity mask register #0 read/write */ |
5108 | #define XSEM_REG_XSEM_PRTY_MASK_0 0x280130 | |
5109 | #define XSEM_REG_XSEM_PRTY_MASK_1 0x280140 | |
f1410647 ET |
5110 | /* [R 32] Parity register #0 read */ |
5111 | #define XSEM_REG_XSEM_PRTY_STS_0 0x280124 | |
5112 | #define XSEM_REG_XSEM_PRTY_STS_1 0x280134 | |
a2fbb9ea ET |
5113 | #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0) |
5114 | #define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1) | |
5115 | #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) | |
5116 | #define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0) | |
5117 | #define MCPR_NVM_COMMAND_DOIT (1L<<4) | |
5118 | #define MCPR_NVM_COMMAND_DONE (1L<<3) | |
5119 | #define MCPR_NVM_COMMAND_FIRST (1L<<7) | |
5120 | #define MCPR_NVM_COMMAND_LAST (1L<<8) | |
5121 | #define MCPR_NVM_COMMAND_WR (1L<<5) | |
5122 | #define MCPR_NVM_COMMAND_WREN (1L<<16) | |
5123 | #define MCPR_NVM_COMMAND_WREN_BITSHIFT 16 | |
5124 | #define MCPR_NVM_COMMAND_WRDI (1L<<17) | |
5125 | #define MCPR_NVM_COMMAND_WRDI_BITSHIFT 17 | |
5126 | #define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9) | |
5127 | #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) | |
5128 | #define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) | |
5129 | #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3) | |
5130 | #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3) | |
5131 | #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3) | |
5132 | #define BIGMAC_REGISTER_RX_CONTROL (0x21<<3) | |
5133 | #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3) | |
5134 | #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3) | |
5135 | #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3) | |
5136 | #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3) | |
5137 | #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3) | |
5138 | #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3) | |
5139 | #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3) | |
5140 | #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3) | |
5141 | #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3) | |
5142 | #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3) | |
c18487ee YR |
5143 | #define EMAC_LED_1000MB_OVERRIDE (1L<<1) |
5144 | #define EMAC_LED_100MB_OVERRIDE (1L<<2) | |
5145 | #define EMAC_LED_10MB_OVERRIDE (1L<<3) | |
5146 | #define EMAC_LED_2500MB_OVERRIDE (1L<<12) | |
5147 | #define EMAC_LED_OVERRIDE (1L<<0) | |
5148 | #define EMAC_LED_TRAFFIC (1L<<6) | |
a2fbb9ea | 5149 | #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26) |
a2fbb9ea | 5150 | #define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26) |
a2fbb9ea ET |
5151 | #define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26) |
5152 | #define EMAC_MDIO_COMM_DATA (0xffffL<<0) | |
5153 | #define EMAC_MDIO_COMM_START_BUSY (1L<<29) | |
5154 | #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4) | |
5155 | #define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31) | |
f1410647 ET |
5156 | #define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16) |
5157 | #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16 | |
a2fbb9ea | 5158 | #define EMAC_MODE_25G_MODE (1L<<5) |
a2fbb9ea | 5159 | #define EMAC_MODE_HALF_DUPLEX (1L<<1) |
a2fbb9ea ET |
5160 | #define EMAC_MODE_PORT_GMII (2L<<2) |
5161 | #define EMAC_MODE_PORT_MII (1L<<2) | |
5162 | #define EMAC_MODE_PORT_MII_10M (3L<<2) | |
5163 | #define EMAC_MODE_RESET (1L<<0) | |
c18487ee | 5164 | #define EMAC_REG_EMAC_LED 0xc |
a2fbb9ea ET |
5165 | #define EMAC_REG_EMAC_MAC_MATCH 0x10 |
5166 | #define EMAC_REG_EMAC_MDIO_COMM 0xac | |
5167 | #define EMAC_REG_EMAC_MDIO_MODE 0xb4 | |
5168 | #define EMAC_REG_EMAC_MODE 0x0 | |
5169 | #define EMAC_REG_EMAC_RX_MODE 0xc8 | |
5170 | #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c | |
5171 | #define EMAC_REG_EMAC_RX_STAT_AC 0x180 | |
5172 | #define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4 | |
5173 | #define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23 | |
5174 | #define EMAC_REG_EMAC_TX_MODE 0xbc | |
5175 | #define EMAC_REG_EMAC_TX_STAT_AC 0x280 | |
5176 | #define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22 | |
5177 | #define EMAC_RX_MODE_FLOW_EN (1L<<2) | |
5178 | #define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) | |
5179 | #define EMAC_RX_MODE_PROMISCUOUS (1L<<8) | |
811a2f2d | 5180 | #define EMAC_RX_MODE_RESET (1L<<0) |
a2fbb9ea ET |
5181 | #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) |
5182 | #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) | |
8c99e7b0 | 5183 | #define EMAC_TX_MODE_FLOW_EN (1L<<4) |
811a2f2d | 5184 | #define EMAC_TX_MODE_RESET (1L<<0) |
c18487ee | 5185 | #define MISC_REGISTERS_GPIO_0 0 |
f1410647 ET |
5186 | #define MISC_REGISTERS_GPIO_1 1 |
5187 | #define MISC_REGISTERS_GPIO_2 2 | |
5188 | #define MISC_REGISTERS_GPIO_3 3 | |
5189 | #define MISC_REGISTERS_GPIO_CLR_POS 16 | |
5190 | #define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24) | |
5191 | #define MISC_REGISTERS_GPIO_FLOAT_POS 24 | |
c18487ee | 5192 | #define MISC_REGISTERS_GPIO_HIGH 1 |
f1410647 | 5193 | #define MISC_REGISTERS_GPIO_INPUT_HI_Z 2 |
4acac6a5 EG |
5194 | #define MISC_REGISTERS_GPIO_INT_CLR_POS 24 |
5195 | #define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0 | |
5196 | #define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1 | |
5197 | #define MISC_REGISTERS_GPIO_INT_SET_POS 16 | |
c18487ee | 5198 | #define MISC_REGISTERS_GPIO_LOW 0 |
f1410647 ET |
5199 | #define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1 |
5200 | #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0 | |
5201 | #define MISC_REGISTERS_GPIO_PORT_SHIFT 4 | |
5202 | #define MISC_REGISTERS_GPIO_SET_POS 8 | |
a2fbb9ea | 5203 | #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588 |
da5a662a | 5204 | #define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7) |
a2fbb9ea ET |
5205 | #define MISC_REGISTERS_RESET_REG_1_SET 0x584 |
5206 | #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598 | |
5207 | #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0) | |
5208 | #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14) | |
5209 | #define MISC_REGISTERS_RESET_REG_2_SET 0x594 | |
5210 | #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8 | |
5211 | #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1) | |
5212 | #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2) | |
5213 | #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3) | |
5214 | #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0) | |
5215 | #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5) | |
5216 | #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6) | |
5217 | #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7) | |
5218 | #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4) | |
5219 | #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8) | |
5220 | #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4 | |
f1410647 ET |
5221 | #define MISC_REGISTERS_SPIO_4 4 |
5222 | #define MISC_REGISTERS_SPIO_5 5 | |
5223 | #define MISC_REGISTERS_SPIO_7 7 | |
5224 | #define MISC_REGISTERS_SPIO_CLR_POS 16 | |
5225 | #define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24) | |
5226 | #define GRC_MISC_REGISTERS_SPIO_FLOAT7 0x80000000 | |
5227 | #define GRC_MISC_REGISTERS_SPIO_FLOAT6 0x40000000 | |
5228 | #define GRC_MISC_REGISTERS_SPIO_FLOAT5 0x20000000 | |
5229 | #define GRC_MISC_REGISTERS_SPIO_FLOAT4 0x10000000 | |
5230 | #define MISC_REGISTERS_SPIO_FLOAT_POS 24 | |
5231 | #define MISC_REGISTERS_SPIO_INPUT_HI_Z 2 | |
5232 | #define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16 | |
5233 | #define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1 | |
5234 | #define MISC_REGISTERS_SPIO_OUTPUT_LOW 0 | |
5235 | #define MISC_REGISTERS_SPIO_SET_POS 8 | |
5236 | #define HW_LOCK_MAX_RESOURCE_VALUE 31 | |
f1410647 | 5237 | #define HW_LOCK_RESOURCE_GPIO 1 |
46c6a674 | 5238 | #define HW_LOCK_RESOURCE_MDIO 0 |
3fcaf2e5 | 5239 | #define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3 |
f1410647 | 5240 | #define HW_LOCK_RESOURCE_SPIO 2 |
da5a662a | 5241 | #define HW_LOCK_RESOURCE_UNDI 5 |
052a38e0 | 5242 | #define PRS_FLAG_OVERETH_IPV4 1 |
a2fbb9ea ET |
5243 | #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18) |
5244 | #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31) | |
5245 | #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9) | |
5246 | #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (1<<8) | |
5247 | #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (1<<7) | |
5248 | #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (1<<6) | |
5249 | #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (1<<29) | |
5250 | #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (1<<28) | |
5251 | #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (1<<1) | |
5252 | #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (1<<0) | |
5253 | #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (1<<18) | |
5254 | #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1<<11) | |
5255 | #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13) | |
5256 | #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1<<12) | |
4acac6a5 EG |
5257 | #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (1<<5) |
5258 | #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (1<<9) | |
a2fbb9ea ET |
5259 | #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1<<12) |
5260 | #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (1<<15) | |
5261 | #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (1<<14) | |
5262 | #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (1<<20) | |
5263 | #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (1<<0) | |
5264 | #define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT (1<<31) | |
5265 | #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (1<<3) | |
5266 | #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (1<<2) | |
5267 | #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (1<<5) | |
5268 | #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (1<<4) | |
5269 | #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (1<<3) | |
5270 | #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (1<<2) | |
5271 | #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (1<<22) | |
f1410647 | 5272 | #define AEU_INPUTS_ATTN_BITS_SPIO5 (1<<15) |
a2fbb9ea ET |
5273 | #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (1<<27) |
5274 | #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (1<<5) | |
5275 | #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (1<<25) | |
5276 | #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (1<<24) | |
5277 | #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (1<<29) | |
5278 | #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (1<<28) | |
5279 | #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (1<<23) | |
5280 | #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (1<<27) | |
5281 | #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (1<<26) | |
5282 | #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (1<<21) | |
5283 | #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (1<<20) | |
5284 | #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (1<<25) | |
5285 | #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (1<<24) | |
5286 | #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (1<<16) | |
5287 | #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (1<<9) | |
5288 | #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (1<<7) | |
5289 | #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (1<<6) | |
5290 | #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (1<<11) | |
5291 | #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10) | |
5292 | #define RESERVED_GENERAL_ATTENTION_BIT_0 0 | |
5293 | ||
c18487ee | 5294 | #define EVEREST_GEN_ATTN_IN_USE_MASK 0x3ffe0 |
a2fbb9ea ET |
5295 | #define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000 |
5296 | ||
5297 | #define RESERVED_GENERAL_ATTENTION_BIT_6 6 | |
5298 | #define RESERVED_GENERAL_ATTENTION_BIT_7 7 | |
5299 | #define RESERVED_GENERAL_ATTENTION_BIT_8 8 | |
5300 | #define RESERVED_GENERAL_ATTENTION_BIT_9 9 | |
5301 | #define RESERVED_GENERAL_ATTENTION_BIT_10 10 | |
5302 | #define RESERVED_GENERAL_ATTENTION_BIT_11 11 | |
5303 | #define RESERVED_GENERAL_ATTENTION_BIT_12 12 | |
5304 | #define RESERVED_GENERAL_ATTENTION_BIT_13 13 | |
5305 | #define RESERVED_GENERAL_ATTENTION_BIT_14 14 | |
5306 | #define RESERVED_GENERAL_ATTENTION_BIT_15 15 | |
5307 | #define RESERVED_GENERAL_ATTENTION_BIT_16 16 | |
5308 | #define RESERVED_GENERAL_ATTENTION_BIT_17 17 | |
5309 | #define RESERVED_GENERAL_ATTENTION_BIT_18 18 | |
5310 | #define RESERVED_GENERAL_ATTENTION_BIT_19 19 | |
5311 | #define RESERVED_GENERAL_ATTENTION_BIT_20 20 | |
5312 | #define RESERVED_GENERAL_ATTENTION_BIT_21 21 | |
5313 | ||
5314 | /* storm asserts attention bits */ | |
5315 | #define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7 | |
5316 | #define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8 | |
5317 | #define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9 | |
5318 | #define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10 | |
5319 | ||
5320 | /* mcp error attention bit */ | |
5321 | #define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11 | |
5322 | ||
c18487ee YR |
5323 | /*E1H NIG status sync attention mapped to group 4-7*/ |
5324 | #define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12 | |
5325 | #define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13 | |
5326 | #define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14 | |
5327 | #define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15 | |
5328 | #define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16 | |
5329 | #define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17 | |
5330 | #define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18 | |
5331 | #define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19 | |
5332 | ||
5333 | ||
a2fbb9ea ET |
5334 | #define LATCHED_ATTN_RBCR 23 |
5335 | #define LATCHED_ATTN_RBCT 24 | |
5336 | #define LATCHED_ATTN_RBCN 25 | |
5337 | #define LATCHED_ATTN_RBCU 26 | |
5338 | #define LATCHED_ATTN_RBCP 27 | |
5339 | #define LATCHED_ATTN_TIMEOUT_GRC 28 | |
5340 | #define LATCHED_ATTN_RSVD_GRC 29 | |
5341 | #define LATCHED_ATTN_ROM_PARITY_MCP 30 | |
5342 | #define LATCHED_ATTN_UM_RX_PARITY_MCP 31 | |
5343 | #define LATCHED_ATTN_UM_TX_PARITY_MCP 32 | |
5344 | #define LATCHED_ATTN_SCPAD_PARITY_MCP 33 | |
5345 | ||
5346 | #define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32) | |
5347 | #define GENERAL_ATTEN_OFFSET(atten_name) (1 << ((94 + atten_name) % 32)) | |
5348 | /* | |
5349 | * This file defines GRC base address for every block. | |
5350 | * This file is included by chipsim, asm microcode and cpp microcode. | |
5351 | * These values are used in Design.xml on regBase attribute | |
5352 | * Use the base with the generated offsets of specific registers. | |
5353 | */ | |
5354 | ||
5355 | #define GRCBASE_PXPCS 0x000000 | |
5356 | #define GRCBASE_PCICONFIG 0x002000 | |
5357 | #define GRCBASE_PCIREG 0x002400 | |
5358 | #define GRCBASE_EMAC0 0x008000 | |
5359 | #define GRCBASE_EMAC1 0x008400 | |
5360 | #define GRCBASE_DBU 0x008800 | |
5361 | #define GRCBASE_MISC 0x00A000 | |
5362 | #define GRCBASE_DBG 0x00C000 | |
5363 | #define GRCBASE_NIG 0x010000 | |
5364 | #define GRCBASE_XCM 0x020000 | |
5365 | #define GRCBASE_PRS 0x040000 | |
5366 | #define GRCBASE_SRCH 0x040400 | |
5367 | #define GRCBASE_TSDM 0x042000 | |
5368 | #define GRCBASE_TCM 0x050000 | |
5369 | #define GRCBASE_BRB1 0x060000 | |
5370 | #define GRCBASE_MCP 0x080000 | |
5371 | #define GRCBASE_UPB 0x0C1000 | |
5372 | #define GRCBASE_CSDM 0x0C2000 | |
5373 | #define GRCBASE_USDM 0x0C4000 | |
5374 | #define GRCBASE_CCM 0x0D0000 | |
5375 | #define GRCBASE_UCM 0x0E0000 | |
5376 | #define GRCBASE_CDU 0x101000 | |
5377 | #define GRCBASE_DMAE 0x102000 | |
5378 | #define GRCBASE_PXP 0x103000 | |
5379 | #define GRCBASE_CFC 0x104000 | |
5380 | #define GRCBASE_HC 0x108000 | |
5381 | #define GRCBASE_PXP2 0x120000 | |
5382 | #define GRCBASE_PBF 0x140000 | |
5383 | #define GRCBASE_XPB 0x161000 | |
5384 | #define GRCBASE_TIMERS 0x164000 | |
5385 | #define GRCBASE_XSDM 0x166000 | |
5386 | #define GRCBASE_QM 0x168000 | |
5387 | #define GRCBASE_DQ 0x170000 | |
5388 | #define GRCBASE_TSEM 0x180000 | |
5389 | #define GRCBASE_CSEM 0x200000 | |
5390 | #define GRCBASE_XSEM 0x280000 | |
5391 | #define GRCBASE_USEM 0x300000 | |
5392 | #define GRCBASE_MISC_AEU GRCBASE_MISC | |
5393 | ||
5394 | ||
5c862848 | 5395 | /* offset of configuration space in the pci core register */ |
a2fbb9ea ET |
5396 | #define PCICFG_OFFSET 0x2000 |
5397 | #define PCICFG_VENDOR_ID_OFFSET 0x00 | |
5398 | #define PCICFG_DEVICE_ID_OFFSET 0x02 | |
c18487ee | 5399 | #define PCICFG_COMMAND_OFFSET 0x04 |
5c862848 EG |
5400 | #define PCICFG_COMMAND_IO_SPACE (1<<0) |
5401 | #define PCICFG_COMMAND_MEM_SPACE (1<<1) | |
5402 | #define PCICFG_COMMAND_BUS_MASTER (1<<2) | |
5403 | #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3) | |
5404 | #define PCICFG_COMMAND_MWI_CYCLES (1<<4) | |
5405 | #define PCICFG_COMMAND_VGA_SNOOP (1<<5) | |
5406 | #define PCICFG_COMMAND_PERR_ENA (1<<6) | |
5407 | #define PCICFG_COMMAND_STEPPING (1<<7) | |
5408 | #define PCICFG_COMMAND_SERR_ENA (1<<8) | |
5409 | #define PCICFG_COMMAND_FAST_B2B (1<<9) | |
5410 | #define PCICFG_COMMAND_INT_DISABLE (1<<10) | |
5411 | #define PCICFG_COMMAND_RESERVED (0x1f<<11) | |
c18487ee | 5412 | #define PCICFG_STATUS_OFFSET 0x06 |
0d1a8d2d | 5413 | #define PCICFG_REVESION_ID_OFFSET 0x08 |
a2fbb9ea ET |
5414 | #define PCICFG_CACHE_LINE_SIZE 0x0c |
5415 | #define PCICFG_LATENCY_TIMER 0x0d | |
5c862848 EG |
5416 | #define PCICFG_BAR_1_LOW 0x10 |
5417 | #define PCICFG_BAR_1_HIGH 0x14 | |
5418 | #define PCICFG_BAR_2_LOW 0x18 | |
5419 | #define PCICFG_BAR_2_HIGH 0x1c | |
5420 | #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c | |
c18487ee | 5421 | #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e |
5c862848 EG |
5422 | #define PCICFG_INT_LINE 0x3c |
5423 | #define PCICFG_INT_PIN 0x3d | |
5424 | #define PCICFG_PM_CAPABILITY 0x48 | |
5425 | #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16) | |
5426 | #define PCICFG_PM_CAPABILITY_CLOCK (1<<19) | |
5427 | #define PCICFG_PM_CAPABILITY_RESERVED (1<<20) | |
5428 | #define PCICFG_PM_CAPABILITY_DSI (1<<21) | |
5429 | #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22) | |
5430 | #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25) | |
5431 | #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26) | |
5432 | #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27) | |
5433 | #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28) | |
5434 | #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29) | |
5435 | #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30) | |
5436 | #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31) | |
5437 | #define PCICFG_PM_CSR_OFFSET 0x4c | |
5438 | #define PCICFG_PM_CSR_STATE (0x3<<0) | |
5439 | #define PCICFG_PM_CSR_PME_ENABLE (1<<8) | |
5440 | #define PCICFG_PM_CSR_PME_STATUS (1<<15) | |
0d1a8d2d | 5441 | #define PCICFG_MSI_CAP_ID_OFFSET 0x58 |
8badd27a EG |
5442 | #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16) |
5443 | #define PCICFG_MSI_CONTROL_MCAP (0x7<<17) | |
5444 | #define PCICFG_MSI_CONTROL_MENA (0x7<<20) | |
5445 | #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23) | |
5446 | #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24) | |
5c862848 EG |
5447 | #define PCICFG_GRC_ADDRESS 0x78 |
5448 | #define PCICFG_GRC_DATA 0x80 | |
0d1a8d2d | 5449 | #define PCICFG_MSIX_CAP_ID_OFFSET 0xa0 |
8badd27a EG |
5450 | #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16) |
5451 | #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27) | |
5452 | #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30) | |
5453 | #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31) | |
5454 | ||
a2fbb9ea | 5455 | #define PCICFG_DEVICE_CONTROL 0xb4 |
8badd27a EG |
5456 | #define PCICFG_DEVICE_STATUS 0xb6 |
5457 | #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0) | |
5458 | #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1) | |
5459 | #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2) | |
5460 | #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3) | |
5461 | #define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4) | |
5462 | #define PCICFG_DEVICE_STATUS_NO_PEND (1<<5) | |
a2fbb9ea ET |
5463 | #define PCICFG_LINK_CONTROL 0xbc |
5464 | ||
c18487ee | 5465 | |
a2fbb9ea ET |
5466 | #define BAR_USTRORM_INTMEM 0x400000 |
5467 | #define BAR_CSTRORM_INTMEM 0x410000 | |
5468 | #define BAR_XSTRORM_INTMEM 0x420000 | |
5469 | #define BAR_TSTRORM_INTMEM 0x430000 | |
5470 | ||
5c862848 | 5471 | /* for accessing the IGU in case of status block ACK */ |
a2fbb9ea ET |
5472 | #define BAR_IGU_INTMEM 0x440000 |
5473 | ||
5474 | #define BAR_DOORBELL_OFFSET 0x800000 | |
5475 | ||
5476 | #define BAR_ME_REGISTER 0x450000 | |
5477 | ||
5c862848 EG |
5478 | /* config_2 offset */ |
5479 | #define GRC_CONFIG_2_SIZE_REG 0x408 | |
5480 | #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) | |
a2fbb9ea ET |
5481 | #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) |
5482 | #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) | |
5483 | #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) | |
5484 | #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) | |
5485 | #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) | |
5486 | #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) | |
5487 | #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) | |
5488 | #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) | |
5489 | #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) | |
5490 | #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) | |
5491 | #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) | |
5492 | #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) | |
5493 | #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) | |
5494 | #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) | |
5495 | #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) | |
5496 | #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) | |
5c862848 EG |
5497 | #define PCI_CONFIG_2_BAR1_64ENA (1L<<4) |
5498 | #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) | |
5499 | #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) | |
5500 | #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) | |
5501 | #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) | |
a2fbb9ea ET |
5502 | #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) |
5503 | #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8) | |
5504 | #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8) | |
5505 | #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8) | |
5506 | #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8) | |
5507 | #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8) | |
5508 | #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8) | |
5509 | #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8) | |
5510 | #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8) | |
5511 | #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8) | |
5512 | #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8) | |
5513 | #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8) | |
5514 | #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8) | |
5515 | #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8) | |
5516 | #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8) | |
5517 | #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8) | |
5c862848 EG |
5518 | #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16) |
5519 | #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17) | |
a2fbb9ea ET |
5520 | |
5521 | /* config_3 offset */ | |
5c862848 EG |
5522 | #define GRC_CONFIG_3_SIZE_REG 0x40c |
5523 | #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) | |
5524 | #define PCI_CONFIG_3_FORCE_PME (1L<<24) | |
5525 | #define PCI_CONFIG_3_PME_STATUS (1L<<25) | |
5526 | #define PCI_CONFIG_3_PME_ENABLE (1L<<26) | |
5527 | #define PCI_CONFIG_3_PM_STATE (0x3L<<27) | |
5528 | #define PCI_CONFIG_3_VAUX_PRESET (1L<<30) | |
5529 | #define PCI_CONFIG_3_PCI_POWER (1L<<31) | |
a2fbb9ea ET |
5530 | |
5531 | #define GRC_BAR2_CONFIG 0x4e0 | |
5c862848 EG |
5532 | #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0) |
5533 | #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0) | |
5534 | #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0) | |
5535 | #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0) | |
5536 | #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0) | |
5537 | #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0) | |
5538 | #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0) | |
5539 | #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0) | |
5540 | #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0) | |
5541 | #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0) | |
5542 | #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0) | |
5543 | #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0) | |
5544 | #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0) | |
5545 | #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0) | |
5546 | #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0) | |
5547 | #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0) | |
5548 | #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0) | |
5549 | #define PCI_CONFIG_2_BAR2_64ENA (1L<<4) | |
5550 | ||
5551 | #define PCI_PM_DATA_A 0x410 | |
5552 | #define PCI_PM_DATA_B 0x414 | |
5553 | #define PCI_ID_VAL1 0x434 | |
5554 | #define PCI_ID_VAL2 0x438 | |
a2fbb9ea | 5555 | |
a2fbb9ea ET |
5556 | |
5557 | #define MDIO_REG_BANK_CL73_IEEEB0 0x0 | |
5558 | #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0 | |
5559 | #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200 | |
5560 | #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000 | |
5561 | #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000 | |
5562 | ||
5563 | #define MDIO_REG_BANK_CL73_IEEEB1 0x10 | |
c18487ee | 5564 | #define MDIO_CL73_IEEEB1_AN_ADV2 0x01 |
a2fbb9ea ET |
5565 | #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000 |
5566 | #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020 | |
5567 | #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040 | |
5568 | #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080 | |
5569 | ||
5570 | #define MDIO_REG_BANK_RX0 0x80b0 | |
5571 | #define MDIO_RX0_RX_EQ_BOOST 0x1c | |
5572 | #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 | |
5573 | #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10 | |
5574 | ||
5575 | #define MDIO_REG_BANK_RX1 0x80c0 | |
5576 | #define MDIO_RX1_RX_EQ_BOOST 0x1c | |
5577 | #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 | |
5578 | #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10 | |
5579 | ||
5580 | #define MDIO_REG_BANK_RX2 0x80d0 | |
5581 | #define MDIO_RX2_RX_EQ_BOOST 0x1c | |
5582 | #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 | |
5583 | #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10 | |
5584 | ||
5585 | #define MDIO_REG_BANK_RX3 0x80e0 | |
5586 | #define MDIO_RX3_RX_EQ_BOOST 0x1c | |
5587 | #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 | |
5588 | #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10 | |
5589 | ||
5590 | #define MDIO_REG_BANK_RX_ALL 0x80f0 | |
5591 | #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c | |
5592 | #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 | |
c18487ee | 5593 | #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10 |
a2fbb9ea ET |
5594 | |
5595 | #define MDIO_REG_BANK_TX0 0x8060 | |
5596 | #define MDIO_TX0_TX_DRIVER 0x17 | |
5597 | #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 | |
5598 | #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 | |
5599 | #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 | |
5600 | #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 | |
5601 | #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 | |
5602 | #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 | |
5603 | #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e | |
5604 | #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 | |
5605 | #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 | |
5606 | ||
c2c8b03e EG |
5607 | #define MDIO_REG_BANK_TX1 0x8070 |
5608 | #define MDIO_TX1_TX_DRIVER 0x17 | |
5609 | #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 | |
5610 | #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 | |
5611 | #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 | |
5612 | #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 | |
5613 | #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 | |
5614 | #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 | |
5615 | #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e | |
5616 | #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 | |
5617 | #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 | |
5618 | ||
5619 | #define MDIO_REG_BANK_TX2 0x8080 | |
5620 | #define MDIO_TX2_TX_DRIVER 0x17 | |
5621 | #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 | |
5622 | #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 | |
5623 | #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 | |
5624 | #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 | |
5625 | #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 | |
5626 | #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 | |
5627 | #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e | |
5628 | #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 | |
5629 | #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 | |
5630 | ||
5631 | #define MDIO_REG_BANK_TX3 0x8090 | |
5632 | #define MDIO_TX3_TX_DRIVER 0x17 | |
5633 | #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 | |
5634 | #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 | |
5635 | #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 | |
5636 | #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 | |
5637 | #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 | |
5638 | #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 | |
5639 | #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e | |
5640 | #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 | |
5641 | #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 | |
5642 | ||
a2fbb9ea ET |
5643 | #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000 |
5644 | #define MDIO_BLOCK0_XGXS_CONTROL 0x10 | |
5645 | ||
5646 | #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010 | |
5647 | #define MDIO_BLOCK1_LANE_CTRL0 0x15 | |
5648 | #define MDIO_BLOCK1_LANE_CTRL1 0x16 | |
5649 | #define MDIO_BLOCK1_LANE_CTRL2 0x17 | |
5650 | #define MDIO_BLOCK1_LANE_PRBS 0x19 | |
5651 | ||
5652 | #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100 | |
5653 | #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10 | |
5654 | #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000 | |
5655 | #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000 | |
c18487ee | 5656 | #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11 |
a2fbb9ea | 5657 | #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000 |
c18487ee | 5658 | #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14 |
f1410647 ET |
5659 | #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001 |
5660 | #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010 | |
c18487ee | 5661 | #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15 |
a2fbb9ea ET |
5662 | |
5663 | #define MDIO_REG_BANK_GP_STATUS 0x8120 | |
c18487ee YR |
5664 | #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B |
5665 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001 | |
5666 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002 | |
5667 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004 | |
5668 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008 | |
5669 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010 | |
5670 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020 | |
5671 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040 | |
5672 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080 | |
5673 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00 | |
5674 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000 | |
5675 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100 | |
5676 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200 | |
5677 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300 | |
5678 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400 | |
5679 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500 | |
5680 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600 | |
5681 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700 | |
5682 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800 | |
5683 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900 | |
5684 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00 | |
5685 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00 | |
5686 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00 | |
5687 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00 | |
5688 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00 | |
a2fbb9ea ET |
5689 | |
5690 | ||
5691 | #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130 | |
c18487ee YR |
5692 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11 |
5693 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1 | |
5694 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13 | |
5695 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1) | |
a2fbb9ea ET |
5696 | |
5697 | #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300 | |
c18487ee YR |
5698 | #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10 |
5699 | #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001 | |
5700 | #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002 | |
5701 | #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004 | |
5702 | #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008 | |
5703 | #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010 | |
5704 | #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020 | |
5705 | #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11 | |
5706 | #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001 | |
5707 | #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040 | |
5708 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14 | |
5709 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004 | |
5710 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018 | |
5711 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3 | |
5712 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018 | |
5713 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010 | |
5714 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008 | |
5715 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000 | |
5716 | #define MDIO_SERDES_DIGITAL_MISC1 0x18 | |
5717 | #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000 | |
5718 | #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000 | |
5719 | #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000 | |
5720 | #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000 | |
5721 | #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000 | |
5722 | #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000 | |
5723 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010 | |
5724 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f | |
5725 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000 | |
5726 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001 | |
5727 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002 | |
5728 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003 | |
5729 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004 | |
5730 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005 | |
5731 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006 | |
5732 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007 | |
5733 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008 | |
5734 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009 | |
a2fbb9ea ET |
5735 | |
5736 | #define MDIO_REG_BANK_OVER_1G 0x8320 | |
c18487ee YR |
5737 | #define MDIO_OVER_1G_DIGCTL_3_4 0x14 |
5738 | #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0 | |
5739 | #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5 | |
5740 | #define MDIO_OVER_1G_UP1 0x19 | |
5741 | #define MDIO_OVER_1G_UP1_2_5G 0x0001 | |
5742 | #define MDIO_OVER_1G_UP1_5G 0x0002 | |
5743 | #define MDIO_OVER_1G_UP1_6G 0x0004 | |
5744 | #define MDIO_OVER_1G_UP1_10G 0x0010 | |
5745 | #define MDIO_OVER_1G_UP1_10GH 0x0008 | |
5746 | #define MDIO_OVER_1G_UP1_12G 0x0020 | |
5747 | #define MDIO_OVER_1G_UP1_12_5G 0x0040 | |
5748 | #define MDIO_OVER_1G_UP1_13G 0x0080 | |
5749 | #define MDIO_OVER_1G_UP1_15G 0x0100 | |
5750 | #define MDIO_OVER_1G_UP1_16G 0x0200 | |
5751 | #define MDIO_OVER_1G_UP2 0x1A | |
5752 | #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007 | |
5753 | #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038 | |
5754 | #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0 | |
5755 | #define MDIO_OVER_1G_UP3 0x1B | |
5756 | #define MDIO_OVER_1G_UP3_HIGIG2 0x0001 | |
5757 | #define MDIO_OVER_1G_LP_UP1 0x1C | |
5758 | #define MDIO_OVER_1G_LP_UP2 0x1D | |
5759 | #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff | |
5760 | #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780 | |
5761 | #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7 | |
5762 | #define MDIO_OVER_1G_LP_UP3 0x1E | |
a2fbb9ea ET |
5763 | |
5764 | #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350 | |
c18487ee YR |
5765 | #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10 |
5766 | #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001 | |
5767 | #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002 | |
5768 | ||
5769 | #define MDIO_REG_BANK_CL73_USERB0 0x8370 | |
5770 | #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12 | |
5771 | #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000 | |
5772 | #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000 | |
5773 | #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000 | |
5774 | #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14 | |
5775 | #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001 | |
5776 | ||
5777 | #define MDIO_REG_BANK_AER_BLOCK 0xFFD0 | |
5778 | #define MDIO_AER_BLOCK_AER_REG 0x1E | |
5779 | ||
5780 | #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0 | |
5781 | #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10 | |
5782 | #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040 | |
5783 | #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000 | |
5784 | #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000 | |
5785 | #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040 | |
5786 | #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100 | |
5787 | #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200 | |
5788 | #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000 | |
5789 | #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000 | |
5790 | #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000 | |
5791 | #define MDIO_COMBO_IEEE0_MII_STATUS 0x11 | |
5792 | #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004 | |
5793 | #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020 | |
5794 | #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14 | |
5795 | #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020 | |
5796 | #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040 | |
5797 | #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180 | |
5798 | #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000 | |
5799 | #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080 | |
5800 | #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100 | |
5801 | #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180 | |
5802 | #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000 | |
5803 | #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15 | |
5804 | #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000 | |
5805 | #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000 | |
5806 | #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180 | |
5807 | #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000 | |
5808 | #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180 | |
5809 | #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040 | |
5810 | #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020 | |
5811 | /*WhenthelinkpartnerisinSGMIImode(bit0=1),then | |
5812 | bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge. | |
5813 | Theotherbitsarereservedandshouldbezero*/ | |
5814 | #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001 | |
5815 | ||
5816 | ||
5817 | #define MDIO_PMA_DEVAD 0x1 | |
5818 | /*ieee*/ | |
5819 | #define MDIO_PMA_REG_CTRL 0x0 | |
5820 | #define MDIO_PMA_REG_STATUS 0x1 | |
5821 | #define MDIO_PMA_REG_10G_CTRL2 0x7 | |
5822 | #define MDIO_PMA_REG_RX_SD 0xa | |
5823 | /*bcm*/ | |
5824 | #define MDIO_PMA_REG_BCM_CTRL 0x0096 | |
5825 | #define MDIO_PMA_REG_FEC_CTRL 0x00ab | |
5826 | #define MDIO_PMA_REG_RX_ALARM_CTRL 0x9000 | |
5827 | #define MDIO_PMA_REG_LASI_CTRL 0x9002 | |
5828 | #define MDIO_PMA_REG_RX_ALARM 0x9003 | |
5829 | #define MDIO_PMA_REG_TX_ALARM 0x9004 | |
5830 | #define MDIO_PMA_REG_LASI_STATUS 0x9005 | |
5831 | #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800 | |
5832 | #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808 | |
5833 | #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809 | |
5834 | #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02 | |
5835 | #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09 | |
5836 | #define MDIO_PMA_REG_MISC_CTRL 0xca0a | |
5837 | #define MDIO_PMA_REG_GEN_CTRL 0xca10 | |
5838 | #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188 | |
5839 | #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a | |
57963ed9 YR |
5840 | #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12 |
5841 | #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13 | |
c18487ee YR |
5842 | #define MDIO_PMA_REG_ROM_VER1 0xca19 |
5843 | #define MDIO_PMA_REG_ROM_VER2 0xca1a | |
5844 | #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b | |
5845 | #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d | |
cc1cb004 | 5846 | #define MDIO_PMA_REG_GEN_CTRL2 0xca1e |
589abe3a EG |
5847 | #define MDIO_PMA_REG_MISC_CTRL0 0xca23 |
5848 | #define MDIO_PMA_REG_LRM_MODE 0xca3f | |
c18487ee YR |
5849 | #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46 |
5850 | #define MDIO_PMA_REG_MISC_CTRL1 0xca85 | |
5851 | ||
589abe3a EG |
5852 | #define MDIO_PMA_REG_8726_TWO_WIRE_CTRL 0x8000 |
5853 | #define MDIO_PMA_REG_8726_TWO_WIRE_CTRL_STATUS_MASK 0x000c | |
5854 | #define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_IDLE 0x0000 | |
5855 | #define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_COMPLETE 0x0004 | |
5856 | #define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_IN_PROGRESS 0x0008 | |
5857 | #define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_FAILED 0x000c | |
5858 | #define MDIO_PMA_REG_8726_TWO_WIRE_BYTE_CNT 0x8002 | |
5859 | #define MDIO_PMA_REG_8726_TWO_WIRE_MEM_ADDR 0x8003 | |
5860 | #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820 | |
5861 | #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff | |
5862 | #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01 | |
5863 | #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05 | |
5864 | ||
5865 | ||
052a38e0 EG |
5866 | #define MDIO_PMA_REG_8073_CHIP_REV 0xc801 |
5867 | #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820 | |
5868 | #define MDIO_PMA_REG_8073_XAUI_WA 0xc841 | |
5869 | ||
c18487ee YR |
5870 | #define MDIO_PMA_REG_7101_RESET 0xc000 |
5871 | #define MDIO_PMA_REG_7107_LED_CNTL 0xc007 | |
5872 | #define MDIO_PMA_REG_7101_VER1 0xc026 | |
5873 | #define MDIO_PMA_REG_7101_VER2 0xc027 | |
5874 | ||
5875 | ||
5876 | #define MDIO_WIS_DEVAD 0x2 | |
5877 | /*bcm*/ | |
5878 | #define MDIO_WIS_REG_LASI_CNTL 0x9002 | |
5879 | #define MDIO_WIS_REG_LASI_STATUS 0x9005 | |
5880 | ||
5881 | #define MDIO_PCS_DEVAD 0x3 | |
5882 | #define MDIO_PCS_REG_STATUS 0x0020 | |
5883 | #define MDIO_PCS_REG_LASI_STATUS 0x9005 | |
5884 | #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000 | |
5885 | #define MDIO_PCS_REG_7101_SPI_MUX 0xD008 | |
5886 | #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A | |
5887 | #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5) | |
5888 | #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A | |
5889 | #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6) | |
5890 | #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7) | |
5891 | #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2) | |
5892 | #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028 | |
5893 | ||
a2fbb9ea | 5894 | |
c18487ee YR |
5895 | #define MDIO_XS_DEVAD 0x4 |
5896 | #define MDIO_XS_PLL_SEQUENCER 0x8000 | |
5897 | #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a | |
a2fbb9ea | 5898 | |
589abe3a EG |
5899 | #define MDIO_XS_8706_REG_BANK_RX0 0x80bc |
5900 | #define MDIO_XS_8706_REG_BANK_RX1 0x80cc | |
5901 | #define MDIO_XS_8706_REG_BANK_RX2 0x80dc | |
5902 | #define MDIO_XS_8706_REG_BANK_RX3 0x80ec | |
5903 | #define MDIO_XS_8706_REG_BANK_RXA 0x80fc | |
5904 | ||
c18487ee YR |
5905 | #define MDIO_AN_DEVAD 0x7 |
5906 | /*ieee*/ | |
5907 | #define MDIO_AN_REG_CTRL 0x0000 | |
5908 | #define MDIO_AN_REG_STATUS 0x0001 | |
5909 | #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020 | |
5910 | #define MDIO_AN_REG_ADV_PAUSE 0x0010 | |
5911 | #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400 | |
5912 | #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800 | |
5913 | #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00 | |
5914 | #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00 | |
5915 | #define MDIO_AN_REG_ADV 0x0011 | |
5916 | #define MDIO_AN_REG_ADV2 0x0012 | |
5917 | #define MDIO_AN_REG_LP_AUTO_NEG 0x0013 | |
5918 | #define MDIO_AN_REG_MASTER_STATUS 0x0021 | |
5919 | /*bcm*/ | |
5920 | #define MDIO_AN_REG_LINK_STATUS 0x8304 | |
5921 | #define MDIO_AN_REG_CL37_CL73 0x8370 | |
5922 | #define MDIO_AN_REG_CL37_AN 0xffe0 | |
8c99e7b0 YR |
5923 | #define MDIO_AN_REG_CL37_FC_LD 0xffe4 |
5924 | #define MDIO_AN_REG_CL37_FC_LP 0xffe5 | |
a2fbb9ea | 5925 | |
052a38e0 EG |
5926 | #define MDIO_AN_REG_8073_2_5G 0x8329 |
5927 | ||
a2fbb9ea | 5928 | |
c18487ee | 5929 | #define IGU_FUNC_BASE 0x0400 |
a2fbb9ea | 5930 | |
c18487ee YR |
5931 | #define IGU_ADDR_MSIX 0x0000 |
5932 | #define IGU_ADDR_INT_ACK 0x0200 | |
5933 | #define IGU_ADDR_PROD_UPD 0x0201 | |
5934 | #define IGU_ADDR_ATTN_BITS_UPD 0x0202 | |
5935 | #define IGU_ADDR_ATTN_BITS_SET 0x0203 | |
5936 | #define IGU_ADDR_ATTN_BITS_CLR 0x0204 | |
5937 | #define IGU_ADDR_COALESCE_NOW 0x0205 | |
5938 | #define IGU_ADDR_SIMD_MASK 0x0206 | |
5939 | #define IGU_ADDR_SIMD_NOMASK 0x0207 | |
5940 | #define IGU_ADDR_MSI_CTL 0x0210 | |
5941 | #define IGU_ADDR_MSI_ADDR_LO 0x0211 | |
5942 | #define IGU_ADDR_MSI_ADDR_HI 0x0212 | |
5943 | #define IGU_ADDR_MSI_DATA 0x0213 | |
a2fbb9ea | 5944 | |
c18487ee YR |
5945 | #define IGU_INT_ENABLE 0 |
5946 | #define IGU_INT_DISABLE 1 | |
5947 | #define IGU_INT_NOP 2 | |
5948 | #define IGU_INT_NOP2 3 | |
f1410647 | 5949 | |
5c862848 EG |
5950 | #define COMMAND_REG_INT_ACK 0x0 |
5951 | #define COMMAND_REG_PROD_UPD 0x4 | |
5952 | #define COMMAND_REG_ATTN_BITS_UPD 0x8 | |
5953 | #define COMMAND_REG_ATTN_BITS_SET 0xc | |
5954 | #define COMMAND_REG_ATTN_BITS_CLR 0x10 | |
5955 | #define COMMAND_REG_COALESCE_NOW 0x14 | |
5956 | #define COMMAND_REG_SIMD_MASK 0x18 | |
5957 | #define COMMAND_REG_SIMD_NOMASK 0x1c | |
5958 | ||
a2fbb9ea | 5959 |