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e0000163 CP |
1 | /* |
2 | * CAN bus driver for Microchip 251x CAN Controller with SPI Interface | |
3 | * | |
4 | * MCP2510 support and bug fixes by Christian Pellegrin | |
5 | * <chripell@evolware.org> | |
6 | * | |
7 | * Copyright 2009 Christian Pellegrin EVOL S.r.l. | |
8 | * | |
9 | * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved. | |
10 | * Written under contract by: | |
11 | * Chris Elston, Katalix Systems, Ltd. | |
12 | * | |
13 | * Based on Microchip MCP251x CAN controller driver written by | |
14 | * David Vrabel, Copyright 2006 Arcom Control Systems Ltd. | |
15 | * | |
16 | * Based on CAN bus driver for the CCAN controller written by | |
17 | * - Sascha Hauer, Marc Kleine-Budde, Pengutronix | |
18 | * - Simon Kallweit, intefo AG | |
19 | * Copyright 2007 | |
20 | * | |
21 | * This program is free software; you can redistribute it and/or modify | |
22 | * it under the terms of the version 2 of the GNU General Public License | |
23 | * as published by the Free Software Foundation | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License | |
31 | * along with this program; if not, write to the Free Software | |
32 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
33 | * | |
34 | * | |
35 | * | |
36 | * Your platform definition file should specify something like: | |
37 | * | |
38 | * static struct mcp251x_platform_data mcp251x_info = { | |
39 | * .oscillator_frequency = 8000000, | |
40 | * .board_specific_setup = &mcp251x_setup, | |
e0000163 CP |
41 | * .power_enable = mcp251x_power_enable, |
42 | * .transceiver_enable = NULL, | |
43 | * }; | |
44 | * | |
45 | * static struct spi_board_info spi_board_info[] = { | |
46 | * { | |
f1f8c6cb MKB |
47 | * .modalias = "mcp2510", |
48 | * // or "mcp2515" depending on your controller | |
e0000163 CP |
49 | * .platform_data = &mcp251x_info, |
50 | * .irq = IRQ_EINT13, | |
51 | * .max_speed_hz = 2*1000*1000, | |
52 | * .chip_select = 2, | |
53 | * }, | |
54 | * }; | |
55 | * | |
56 | * Please see mcp251x.h for a description of the fields in | |
57 | * struct mcp251x_platform_data. | |
58 | * | |
59 | */ | |
60 | ||
e0000163 CP |
61 | #include <linux/can/core.h> |
62 | #include <linux/can/dev.h> | |
63 | #include <linux/can/platform/mcp251x.h> | |
64 | #include <linux/completion.h> | |
65 | #include <linux/delay.h> | |
66 | #include <linux/device.h> | |
67 | #include <linux/dma-mapping.h> | |
68 | #include <linux/freezer.h> | |
69 | #include <linux/interrupt.h> | |
70 | #include <linux/io.h> | |
71 | #include <linux/kernel.h> | |
72 | #include <linux/module.h> | |
73 | #include <linux/netdevice.h> | |
74 | #include <linux/platform_device.h> | |
5a0e3ad6 | 75 | #include <linux/slab.h> |
e0000163 CP |
76 | #include <linux/spi/spi.h> |
77 | #include <linux/uaccess.h> | |
78 | ||
79 | /* SPI interface instruction set */ | |
80 | #define INSTRUCTION_WRITE 0x02 | |
81 | #define INSTRUCTION_READ 0x03 | |
82 | #define INSTRUCTION_BIT_MODIFY 0x05 | |
83 | #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n)) | |
84 | #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94) | |
85 | #define INSTRUCTION_RESET 0xC0 | |
86 | ||
87 | /* MPC251x registers */ | |
88 | #define CANSTAT 0x0e | |
89 | #define CANCTRL 0x0f | |
90 | # define CANCTRL_REQOP_MASK 0xe0 | |
91 | # define CANCTRL_REQOP_CONF 0x80 | |
92 | # define CANCTRL_REQOP_LISTEN_ONLY 0x60 | |
93 | # define CANCTRL_REQOP_LOOPBACK 0x40 | |
94 | # define CANCTRL_REQOP_SLEEP 0x20 | |
95 | # define CANCTRL_REQOP_NORMAL 0x00 | |
96 | # define CANCTRL_OSM 0x08 | |
97 | # define CANCTRL_ABAT 0x10 | |
98 | #define TEC 0x1c | |
99 | #define REC 0x1d | |
100 | #define CNF1 0x2a | |
101 | # define CNF1_SJW_SHIFT 6 | |
102 | #define CNF2 0x29 | |
103 | # define CNF2_BTLMODE 0x80 | |
104 | # define CNF2_SAM 0x40 | |
105 | # define CNF2_PS1_SHIFT 3 | |
106 | #define CNF3 0x28 | |
107 | # define CNF3_SOF 0x08 | |
108 | # define CNF3_WAKFIL 0x04 | |
109 | # define CNF3_PHSEG2_MASK 0x07 | |
110 | #define CANINTE 0x2b | |
111 | # define CANINTE_MERRE 0x80 | |
112 | # define CANINTE_WAKIE 0x40 | |
113 | # define CANINTE_ERRIE 0x20 | |
114 | # define CANINTE_TX2IE 0x10 | |
115 | # define CANINTE_TX1IE 0x08 | |
116 | # define CANINTE_TX0IE 0x04 | |
117 | # define CANINTE_RX1IE 0x02 | |
118 | # define CANINTE_RX0IE 0x01 | |
119 | #define CANINTF 0x2c | |
120 | # define CANINTF_MERRF 0x80 | |
121 | # define CANINTF_WAKIF 0x40 | |
122 | # define CANINTF_ERRIF 0x20 | |
123 | # define CANINTF_TX2IF 0x10 | |
124 | # define CANINTF_TX1IF 0x08 | |
125 | # define CANINTF_TX0IF 0x04 | |
126 | # define CANINTF_RX1IF 0x02 | |
127 | # define CANINTF_RX0IF 0x01 | |
5601b2df MKB |
128 | # define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF) |
129 | # define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF) | |
130 | # define CANINTF_ERR (CANINTF_ERRIF) | |
e0000163 CP |
131 | #define EFLG 0x2d |
132 | # define EFLG_EWARN 0x01 | |
133 | # define EFLG_RXWAR 0x02 | |
134 | # define EFLG_TXWAR 0x04 | |
135 | # define EFLG_RXEP 0x08 | |
136 | # define EFLG_TXEP 0x10 | |
137 | # define EFLG_TXBO 0x20 | |
138 | # define EFLG_RX0OVR 0x40 | |
139 | # define EFLG_RX1OVR 0x80 | |
140 | #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF) | |
141 | # define TXBCTRL_ABTF 0x40 | |
142 | # define TXBCTRL_MLOA 0x20 | |
143 | # define TXBCTRL_TXERR 0x10 | |
144 | # define TXBCTRL_TXREQ 0x08 | |
145 | #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF) | |
146 | # define SIDH_SHIFT 3 | |
147 | #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF) | |
148 | # define SIDL_SID_MASK 7 | |
149 | # define SIDL_SID_SHIFT 5 | |
150 | # define SIDL_EXIDE_SHIFT 3 | |
151 | # define SIDL_EID_SHIFT 16 | |
152 | # define SIDL_EID_MASK 3 | |
153 | #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF) | |
154 | #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF) | |
155 | #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF) | |
156 | # define DLC_RTR_SHIFT 6 | |
157 | #define TXBCTRL_OFF 0 | |
158 | #define TXBSIDH_OFF 1 | |
159 | #define TXBSIDL_OFF 2 | |
160 | #define TXBEID8_OFF 3 | |
161 | #define TXBEID0_OFF 4 | |
162 | #define TXBDLC_OFF 5 | |
163 | #define TXBDAT_OFF 6 | |
164 | #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF) | |
165 | # define RXBCTRL_BUKT 0x04 | |
166 | # define RXBCTRL_RXM0 0x20 | |
167 | # define RXBCTRL_RXM1 0x40 | |
168 | #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF) | |
169 | # define RXBSIDH_SHIFT 3 | |
170 | #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF) | |
171 | # define RXBSIDL_IDE 0x08 | |
b9958a95 | 172 | # define RXBSIDL_SRR 0x10 |
e0000163 CP |
173 | # define RXBSIDL_EID 3 |
174 | # define RXBSIDL_SHIFT 5 | |
175 | #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF) | |
176 | #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF) | |
177 | #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF) | |
178 | # define RXBDLC_LEN_MASK 0x0f | |
179 | # define RXBDLC_RTR 0x40 | |
180 | #define RXBCTRL_OFF 0 | |
181 | #define RXBSIDH_OFF 1 | |
182 | #define RXBSIDL_OFF 2 | |
183 | #define RXBEID8_OFF 3 | |
184 | #define RXBEID0_OFF 4 | |
185 | #define RXBDLC_OFF 5 | |
186 | #define RXBDAT_OFF 6 | |
bf66f373 CP |
187 | #define RXFSIDH(n) ((n) * 4) |
188 | #define RXFSIDL(n) ((n) * 4 + 1) | |
189 | #define RXFEID8(n) ((n) * 4 + 2) | |
190 | #define RXFEID0(n) ((n) * 4 + 3) | |
191 | #define RXMSIDH(n) ((n) * 4 + 0x20) | |
192 | #define RXMSIDL(n) ((n) * 4 + 0x21) | |
193 | #define RXMEID8(n) ((n) * 4 + 0x22) | |
194 | #define RXMEID0(n) ((n) * 4 + 0x23) | |
e0000163 CP |
195 | |
196 | #define GET_BYTE(val, byte) \ | |
197 | (((val) >> ((byte) * 8)) & 0xff) | |
198 | #define SET_BYTE(val, byte) \ | |
199 | (((val) & 0xff) << ((byte) * 8)) | |
200 | ||
201 | /* | |
202 | * Buffer size required for the largest SPI transfer (i.e., reading a | |
203 | * frame) | |
204 | */ | |
205 | #define CAN_FRAME_MAX_DATA_LEN 8 | |
206 | #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN) | |
207 | #define CAN_FRAME_MAX_BITS 128 | |
208 | ||
209 | #define TX_ECHO_SKB_MAX 1 | |
210 | ||
211 | #define DEVICE_NAME "mcp251x" | |
212 | ||
213 | static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */ | |
214 | module_param(mcp251x_enable_dma, int, S_IRUGO); | |
215 | MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)"); | |
216 | ||
217 | static struct can_bittiming_const mcp251x_bittiming_const = { | |
218 | .name = DEVICE_NAME, | |
219 | .tseg1_min = 3, | |
220 | .tseg1_max = 16, | |
221 | .tseg2_min = 2, | |
222 | .tseg2_max = 8, | |
223 | .sjw_max = 4, | |
224 | .brp_min = 1, | |
225 | .brp_max = 64, | |
226 | .brp_inc = 1, | |
227 | }; | |
228 | ||
f1f8c6cb MKB |
229 | enum mcp251x_model { |
230 | CAN_MCP251X_MCP2510 = 0x2510, | |
231 | CAN_MCP251X_MCP2515 = 0x2515, | |
232 | }; | |
233 | ||
e0000163 CP |
234 | struct mcp251x_priv { |
235 | struct can_priv can; | |
236 | struct net_device *net; | |
237 | struct spi_device *spi; | |
f1f8c6cb | 238 | enum mcp251x_model model; |
e0000163 | 239 | |
bf66f373 CP |
240 | struct mutex mcp_lock; /* SPI device lock */ |
241 | ||
e0000163 CP |
242 | u8 *spi_tx_buf; |
243 | u8 *spi_rx_buf; | |
244 | dma_addr_t spi_tx_dma; | |
245 | dma_addr_t spi_rx_dma; | |
246 | ||
247 | struct sk_buff *tx_skb; | |
248 | int tx_len; | |
bf66f373 | 249 | |
e0000163 CP |
250 | struct workqueue_struct *wq; |
251 | struct work_struct tx_work; | |
bf66f373 CP |
252 | struct work_struct restart_work; |
253 | ||
e0000163 CP |
254 | int force_quit; |
255 | int after_suspend; | |
256 | #define AFTER_SUSPEND_UP 1 | |
257 | #define AFTER_SUSPEND_DOWN 2 | |
258 | #define AFTER_SUSPEND_POWER 4 | |
259 | #define AFTER_SUSPEND_RESTART 8 | |
260 | int restart_tx; | |
261 | }; | |
262 | ||
beab675c MKB |
263 | #define MCP251X_IS(_model) \ |
264 | static inline int mcp251x_is_##_model(struct spi_device *spi) \ | |
265 | { \ | |
266 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); \ | |
267 | return priv->model == CAN_MCP251X_MCP##_model; \ | |
268 | } | |
269 | ||
270 | MCP251X_IS(2510); | |
271 | MCP251X_IS(2515); | |
272 | ||
e0000163 CP |
273 | static void mcp251x_clean(struct net_device *net) |
274 | { | |
275 | struct mcp251x_priv *priv = netdev_priv(net); | |
276 | ||
bf66f373 CP |
277 | if (priv->tx_skb || priv->tx_len) |
278 | net->stats.tx_errors++; | |
e0000163 CP |
279 | if (priv->tx_skb) |
280 | dev_kfree_skb(priv->tx_skb); | |
281 | if (priv->tx_len) | |
282 | can_free_echo_skb(priv->net, 0); | |
283 | priv->tx_skb = NULL; | |
284 | priv->tx_len = 0; | |
285 | } | |
286 | ||
287 | /* | |
288 | * Note about handling of error return of mcp251x_spi_trans: accessing | |
289 | * registers via SPI is not really different conceptually than using | |
290 | * normal I/O assembler instructions, although it's much more | |
291 | * complicated from a practical POV. So it's not advisable to always | |
292 | * check the return value of this function. Imagine that every | |
293 | * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0) | |
294 | * error();", it would be a great mess (well there are some situation | |
295 | * when exception handling C++ like could be useful after all). So we | |
296 | * just check that transfers are OK at the beginning of our | |
297 | * conversation with the chip and to avoid doing really nasty things | |
298 | * (like injecting bogus packets in the network stack). | |
299 | */ | |
300 | static int mcp251x_spi_trans(struct spi_device *spi, int len) | |
301 | { | |
302 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
303 | struct spi_transfer t = { | |
304 | .tx_buf = priv->spi_tx_buf, | |
305 | .rx_buf = priv->spi_rx_buf, | |
306 | .len = len, | |
307 | .cs_change = 0, | |
308 | }; | |
309 | struct spi_message m; | |
310 | int ret; | |
311 | ||
312 | spi_message_init(&m); | |
313 | ||
314 | if (mcp251x_enable_dma) { | |
315 | t.tx_dma = priv->spi_tx_dma; | |
316 | t.rx_dma = priv->spi_rx_dma; | |
317 | m.is_dma_mapped = 1; | |
318 | } | |
319 | ||
320 | spi_message_add_tail(&t, &m); | |
321 | ||
322 | ret = spi_sync(spi, &m); | |
323 | if (ret) | |
324 | dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret); | |
325 | return ret; | |
326 | } | |
327 | ||
328 | static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg) | |
329 | { | |
330 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
331 | u8 val = 0; | |
332 | ||
e0000163 CP |
333 | priv->spi_tx_buf[0] = INSTRUCTION_READ; |
334 | priv->spi_tx_buf[1] = reg; | |
335 | ||
336 | mcp251x_spi_trans(spi, 3); | |
337 | val = priv->spi_rx_buf[2]; | |
338 | ||
e0000163 CP |
339 | return val; |
340 | } | |
341 | ||
f3a3ed31 SH |
342 | static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg, |
343 | uint8_t *v1, uint8_t *v2) | |
344 | { | |
345 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
346 | ||
347 | priv->spi_tx_buf[0] = INSTRUCTION_READ; | |
348 | priv->spi_tx_buf[1] = reg; | |
349 | ||
350 | mcp251x_spi_trans(spi, 4); | |
351 | ||
352 | *v1 = priv->spi_rx_buf[2]; | |
353 | *v2 = priv->spi_rx_buf[3]; | |
354 | } | |
355 | ||
e0000163 CP |
356 | static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val) |
357 | { | |
358 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
359 | ||
e0000163 CP |
360 | priv->spi_tx_buf[0] = INSTRUCTION_WRITE; |
361 | priv->spi_tx_buf[1] = reg; | |
362 | priv->spi_tx_buf[2] = val; | |
363 | ||
364 | mcp251x_spi_trans(spi, 3); | |
e0000163 CP |
365 | } |
366 | ||
367 | static void mcp251x_write_bits(struct spi_device *spi, u8 reg, | |
368 | u8 mask, uint8_t val) | |
369 | { | |
370 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
371 | ||
e0000163 CP |
372 | priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY; |
373 | priv->spi_tx_buf[1] = reg; | |
374 | priv->spi_tx_buf[2] = mask; | |
375 | priv->spi_tx_buf[3] = val; | |
376 | ||
377 | mcp251x_spi_trans(spi, 4); | |
e0000163 CP |
378 | } |
379 | ||
380 | static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf, | |
381 | int len, int tx_buf_idx) | |
382 | { | |
e0000163 CP |
383 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); |
384 | ||
beab675c | 385 | if (mcp251x_is_2510(spi)) { |
e0000163 CP |
386 | int i; |
387 | ||
388 | for (i = 1; i < TXBDAT_OFF + len; i++) | |
389 | mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i, | |
390 | buf[i]); | |
391 | } else { | |
e0000163 CP |
392 | memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len); |
393 | mcp251x_spi_trans(spi, TXBDAT_OFF + len); | |
e0000163 CP |
394 | } |
395 | } | |
396 | ||
397 | static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame, | |
398 | int tx_buf_idx) | |
399 | { | |
400 | u32 sid, eid, exide, rtr; | |
401 | u8 buf[SPI_TRANSFER_BUF_LEN]; | |
402 | ||
403 | exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */ | |
404 | if (exide) | |
405 | sid = (frame->can_id & CAN_EFF_MASK) >> 18; | |
406 | else | |
407 | sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */ | |
408 | eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */ | |
409 | rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */ | |
410 | ||
411 | buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx); | |
412 | buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT; | |
413 | buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) | | |
414 | (exide << SIDL_EXIDE_SHIFT) | | |
415 | ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK); | |
416 | buf[TXBEID8_OFF] = GET_BYTE(eid, 1); | |
417 | buf[TXBEID0_OFF] = GET_BYTE(eid, 0); | |
418 | buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc; | |
419 | memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc); | |
420 | mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx); | |
421 | mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx), TXBCTRL_TXREQ); | |
422 | } | |
423 | ||
424 | static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf, | |
425 | int buf_idx) | |
426 | { | |
427 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
e0000163 | 428 | |
beab675c | 429 | if (mcp251x_is_2510(spi)) { |
e0000163 CP |
430 | int i, len; |
431 | ||
432 | for (i = 1; i < RXBDAT_OFF; i++) | |
433 | buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i); | |
c7cd606f OH |
434 | |
435 | len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK); | |
e0000163 CP |
436 | for (; i < (RXBDAT_OFF + len); i++) |
437 | buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i); | |
438 | } else { | |
e0000163 CP |
439 | priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx); |
440 | mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN); | |
441 | memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN); | |
e0000163 CP |
442 | } |
443 | } | |
444 | ||
445 | static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx) | |
446 | { | |
447 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
448 | struct sk_buff *skb; | |
449 | struct can_frame *frame; | |
450 | u8 buf[SPI_TRANSFER_BUF_LEN]; | |
451 | ||
452 | skb = alloc_can_skb(priv->net, &frame); | |
453 | if (!skb) { | |
454 | dev_err(&spi->dev, "cannot allocate RX skb\n"); | |
455 | priv->net->stats.rx_dropped++; | |
456 | return; | |
457 | } | |
458 | ||
459 | mcp251x_hw_rx_frame(spi, buf, buf_idx); | |
460 | if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) { | |
461 | /* Extended ID format */ | |
462 | frame->can_id = CAN_EFF_FLAG; | |
463 | frame->can_id |= | |
464 | /* Extended ID part */ | |
465 | SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) | | |
466 | SET_BYTE(buf[RXBEID8_OFF], 1) | | |
467 | SET_BYTE(buf[RXBEID0_OFF], 0) | | |
468 | /* Standard ID part */ | |
469 | (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) | | |
470 | (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18); | |
471 | /* Remote transmission request */ | |
472 | if (buf[RXBDLC_OFF] & RXBDLC_RTR) | |
473 | frame->can_id |= CAN_RTR_FLAG; | |
474 | } else { | |
475 | /* Standard ID format */ | |
476 | frame->can_id = | |
477 | (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) | | |
478 | (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT); | |
b9958a95 MKB |
479 | if (buf[RXBSIDL_OFF] & RXBSIDL_SRR) |
480 | frame->can_id |= CAN_RTR_FLAG; | |
e0000163 CP |
481 | } |
482 | /* Data length */ | |
c7cd606f | 483 | frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK); |
e0000163 CP |
484 | memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc); |
485 | ||
486 | priv->net->stats.rx_packets++; | |
487 | priv->net->stats.rx_bytes += frame->can_dlc; | |
57d3c7b0 | 488 | netif_rx_ni(skb); |
e0000163 CP |
489 | } |
490 | ||
491 | static void mcp251x_hw_sleep(struct spi_device *spi) | |
492 | { | |
493 | mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP); | |
494 | } | |
495 | ||
e0000163 CP |
496 | static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb, |
497 | struct net_device *net) | |
498 | { | |
499 | struct mcp251x_priv *priv = netdev_priv(net); | |
500 | struct spi_device *spi = priv->spi; | |
501 | ||
502 | if (priv->tx_skb || priv->tx_len) { | |
503 | dev_warn(&spi->dev, "hard_xmit called while tx busy\n"); | |
e0000163 CP |
504 | return NETDEV_TX_BUSY; |
505 | } | |
506 | ||
3ccd4c61 | 507 | if (can_dropped_invalid_skb(net, skb)) |
e0000163 | 508 | return NETDEV_TX_OK; |
e0000163 CP |
509 | |
510 | netif_stop_queue(net); | |
511 | priv->tx_skb = skb; | |
e0000163 CP |
512 | queue_work(priv->wq, &priv->tx_work); |
513 | ||
514 | return NETDEV_TX_OK; | |
515 | } | |
516 | ||
517 | static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode) | |
518 | { | |
519 | struct mcp251x_priv *priv = netdev_priv(net); | |
520 | ||
521 | switch (mode) { | |
522 | case CAN_MODE_START: | |
bf66f373 | 523 | mcp251x_clean(net); |
e0000163 CP |
524 | /* We have to delay work since SPI I/O may sleep */ |
525 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
526 | priv->restart_tx = 1; | |
527 | if (priv->can.restart_ms == 0) | |
528 | priv->after_suspend = AFTER_SUSPEND_RESTART; | |
bf66f373 | 529 | queue_work(priv->wq, &priv->restart_work); |
e0000163 CP |
530 | break; |
531 | default: | |
532 | return -EOPNOTSUPP; | |
533 | } | |
534 | ||
535 | return 0; | |
536 | } | |
537 | ||
bf66f373 | 538 | static int mcp251x_set_normal_mode(struct spi_device *spi) |
e0000163 CP |
539 | { |
540 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
541 | unsigned long timeout; | |
542 | ||
543 | /* Enable interrupts */ | |
544 | mcp251x_write_reg(spi, CANINTE, | |
545 | CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE | | |
bf66f373 | 546 | CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE); |
e0000163 CP |
547 | |
548 | if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { | |
549 | /* Put device into loopback mode */ | |
550 | mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK); | |
ad72c347 CP |
551 | } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { |
552 | /* Put device into listen-only mode */ | |
553 | mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY); | |
e0000163 CP |
554 | } else { |
555 | /* Put device into normal mode */ | |
bf66f373 | 556 | mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL); |
e0000163 CP |
557 | |
558 | /* Wait for the device to enter normal mode */ | |
559 | timeout = jiffies + HZ; | |
560 | while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) { | |
561 | schedule(); | |
562 | if (time_after(jiffies, timeout)) { | |
563 | dev_err(&spi->dev, "MCP251x didn't" | |
564 | " enter in normal mode\n"); | |
bf66f373 | 565 | return -EBUSY; |
e0000163 CP |
566 | } |
567 | } | |
568 | } | |
569 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
bf66f373 | 570 | return 0; |
e0000163 CP |
571 | } |
572 | ||
573 | static int mcp251x_do_set_bittiming(struct net_device *net) | |
574 | { | |
575 | struct mcp251x_priv *priv = netdev_priv(net); | |
576 | struct can_bittiming *bt = &priv->can.bittiming; | |
577 | struct spi_device *spi = priv->spi; | |
578 | ||
579 | mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) | | |
580 | (bt->brp - 1)); | |
581 | mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE | | |
582 | (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ? | |
583 | CNF2_SAM : 0) | | |
584 | ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) | | |
585 | (bt->prop_seg - 1)); | |
586 | mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK, | |
587 | (bt->phase_seg2 - 1)); | |
588 | dev_info(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n", | |
589 | mcp251x_read_reg(spi, CNF1), | |
590 | mcp251x_read_reg(spi, CNF2), | |
591 | mcp251x_read_reg(spi, CNF3)); | |
592 | ||
593 | return 0; | |
594 | } | |
595 | ||
596 | static int mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv, | |
597 | struct spi_device *spi) | |
598 | { | |
615534bc | 599 | mcp251x_do_set_bittiming(net); |
e0000163 | 600 | |
bf66f373 CP |
601 | mcp251x_write_reg(spi, RXBCTRL(0), |
602 | RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1); | |
603 | mcp251x_write_reg(spi, RXBCTRL(1), | |
604 | RXBCTRL_RXM0 | RXBCTRL_RXM1); | |
e0000163 CP |
605 | return 0; |
606 | } | |
607 | ||
bf66f373 | 608 | static int mcp251x_hw_reset(struct spi_device *spi) |
e0000163 CP |
609 | { |
610 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
611 | int ret; | |
bf66f373 | 612 | unsigned long timeout; |
e0000163 CP |
613 | |
614 | priv->spi_tx_buf[0] = INSTRUCTION_RESET; | |
e0000163 | 615 | ret = spi_write(spi, priv->spi_tx_buf, 1); |
bf66f373 | 616 | if (ret) { |
e0000163 | 617 | dev_err(&spi->dev, "reset failed: ret = %d\n", ret); |
bf66f373 CP |
618 | return -EIO; |
619 | } | |
620 | ||
e0000163 | 621 | /* Wait for reset to finish */ |
bf66f373 | 622 | timeout = jiffies + HZ; |
e0000163 | 623 | mdelay(10); |
bf66f373 CP |
624 | while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) |
625 | != CANCTRL_REQOP_CONF) { | |
626 | schedule(); | |
627 | if (time_after(jiffies, timeout)) { | |
628 | dev_err(&spi->dev, "MCP251x didn't" | |
629 | " enter in conf mode after reset\n"); | |
630 | return -EBUSY; | |
631 | } | |
632 | } | |
633 | return 0; | |
e0000163 CP |
634 | } |
635 | ||
636 | static int mcp251x_hw_probe(struct spi_device *spi) | |
637 | { | |
638 | int st1, st2; | |
639 | ||
640 | mcp251x_hw_reset(spi); | |
641 | ||
642 | /* | |
643 | * Please note that these are "magic values" based on after | |
644 | * reset defaults taken from data sheet which allows us to see | |
645 | * if we really have a chip on the bus (we avoid common all | |
646 | * zeroes or all ones situations) | |
647 | */ | |
648 | st1 = mcp251x_read_reg(spi, CANSTAT) & 0xEE; | |
649 | st2 = mcp251x_read_reg(spi, CANCTRL) & 0x17; | |
650 | ||
651 | dev_dbg(&spi->dev, "CANSTAT 0x%02x CANCTRL 0x%02x\n", st1, st2); | |
652 | ||
653 | /* Check for power up default values */ | |
654 | return (st1 == 0x80 && st2 == 0x07) ? 1 : 0; | |
655 | } | |
656 | ||
bf66f373 | 657 | static void mcp251x_open_clean(struct net_device *net) |
e0000163 CP |
658 | { |
659 | struct mcp251x_priv *priv = netdev_priv(net); | |
660 | struct spi_device *spi = priv->spi; | |
661 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
615534bc | 662 | |
bf66f373 CP |
663 | free_irq(spi->irq, priv); |
664 | mcp251x_hw_sleep(spi); | |
e0000163 | 665 | if (pdata->transceiver_enable) |
bf66f373 CP |
666 | pdata->transceiver_enable(0); |
667 | close_candev(net); | |
e0000163 CP |
668 | } |
669 | ||
670 | static int mcp251x_stop(struct net_device *net) | |
671 | { | |
672 | struct mcp251x_priv *priv = netdev_priv(net); | |
673 | struct spi_device *spi = priv->spi; | |
674 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
675 | ||
676 | close_candev(net); | |
677 | ||
bf66f373 CP |
678 | priv->force_quit = 1; |
679 | free_irq(spi->irq, priv); | |
680 | destroy_workqueue(priv->wq); | |
681 | priv->wq = NULL; | |
682 | ||
683 | mutex_lock(&priv->mcp_lock); | |
684 | ||
e0000163 CP |
685 | /* Disable and clear pending interrupts */ |
686 | mcp251x_write_reg(spi, CANINTE, 0x00); | |
687 | mcp251x_write_reg(spi, CANINTF, 0x00); | |
688 | ||
e0000163 | 689 | mcp251x_write_reg(spi, TXBCTRL(0), 0); |
bf66f373 | 690 | mcp251x_clean(net); |
e0000163 CP |
691 | |
692 | mcp251x_hw_sleep(spi); | |
693 | ||
694 | if (pdata->transceiver_enable) | |
695 | pdata->transceiver_enable(0); | |
696 | ||
697 | priv->can.state = CAN_STATE_STOPPED; | |
698 | ||
bf66f373 CP |
699 | mutex_unlock(&priv->mcp_lock); |
700 | ||
e0000163 CP |
701 | return 0; |
702 | } | |
703 | ||
bf66f373 CP |
704 | static void mcp251x_error_skb(struct net_device *net, int can_id, int data1) |
705 | { | |
706 | struct sk_buff *skb; | |
707 | struct can_frame *frame; | |
708 | ||
709 | skb = alloc_can_err_skb(net, &frame); | |
710 | if (skb) { | |
612eef4f | 711 | frame->can_id |= can_id; |
bf66f373 | 712 | frame->data[1] = data1; |
57d3c7b0 | 713 | netif_rx_ni(skb); |
bf66f373 CP |
714 | } else { |
715 | dev_err(&net->dev, | |
716 | "cannot allocate error skb\n"); | |
717 | } | |
718 | } | |
719 | ||
e0000163 CP |
720 | static void mcp251x_tx_work_handler(struct work_struct *ws) |
721 | { | |
722 | struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv, | |
723 | tx_work); | |
724 | struct spi_device *spi = priv->spi; | |
725 | struct net_device *net = priv->net; | |
726 | struct can_frame *frame; | |
727 | ||
bf66f373 | 728 | mutex_lock(&priv->mcp_lock); |
e0000163 | 729 | if (priv->tx_skb) { |
e0000163 CP |
730 | if (priv->can.state == CAN_STATE_BUS_OFF) { |
731 | mcp251x_clean(net); | |
bf66f373 CP |
732 | } else { |
733 | frame = (struct can_frame *)priv->tx_skb->data; | |
734 | ||
735 | if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN) | |
736 | frame->can_dlc = CAN_FRAME_MAX_DATA_LEN; | |
737 | mcp251x_hw_tx(spi, frame, 0); | |
738 | priv->tx_len = 1 + frame->can_dlc; | |
739 | can_put_echo_skb(priv->tx_skb, net, 0); | |
740 | priv->tx_skb = NULL; | |
e0000163 | 741 | } |
e0000163 | 742 | } |
bf66f373 | 743 | mutex_unlock(&priv->mcp_lock); |
e0000163 CP |
744 | } |
745 | ||
bf66f373 | 746 | static void mcp251x_restart_work_handler(struct work_struct *ws) |
e0000163 CP |
747 | { |
748 | struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv, | |
bf66f373 | 749 | restart_work); |
e0000163 CP |
750 | struct spi_device *spi = priv->spi; |
751 | struct net_device *net = priv->net; | |
e0000163 | 752 | |
bf66f373 | 753 | mutex_lock(&priv->mcp_lock); |
e0000163 CP |
754 | if (priv->after_suspend) { |
755 | mdelay(10); | |
756 | mcp251x_hw_reset(spi); | |
757 | mcp251x_setup(net, priv, spi); | |
758 | if (priv->after_suspend & AFTER_SUSPEND_RESTART) { | |
759 | mcp251x_set_normal_mode(spi); | |
760 | } else if (priv->after_suspend & AFTER_SUSPEND_UP) { | |
761 | netif_device_attach(net); | |
bf66f373 | 762 | mcp251x_clean(net); |
e0000163 | 763 | mcp251x_set_normal_mode(spi); |
bf66f373 | 764 | netif_wake_queue(net); |
e0000163 CP |
765 | } else { |
766 | mcp251x_hw_sleep(spi); | |
767 | } | |
768 | priv->after_suspend = 0; | |
bf66f373 | 769 | priv->force_quit = 0; |
e0000163 CP |
770 | } |
771 | ||
bf66f373 CP |
772 | if (priv->restart_tx) { |
773 | priv->restart_tx = 0; | |
774 | mcp251x_write_reg(spi, TXBCTRL(0), 0); | |
775 | mcp251x_clean(net); | |
776 | netif_wake_queue(net); | |
777 | mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0); | |
778 | } | |
779 | mutex_unlock(&priv->mcp_lock); | |
780 | } | |
e0000163 | 781 | |
bf66f373 CP |
782 | static irqreturn_t mcp251x_can_ist(int irq, void *dev_id) |
783 | { | |
784 | struct mcp251x_priv *priv = dev_id; | |
785 | struct spi_device *spi = priv->spi; | |
786 | struct net_device *net = priv->net; | |
e0000163 | 787 | |
bf66f373 CP |
788 | mutex_lock(&priv->mcp_lock); |
789 | while (!priv->force_quit) { | |
790 | enum can_state new_state; | |
f3a3ed31 | 791 | u8 intf, eflag; |
d3cd1565 | 792 | u8 clear_intf = 0; |
bf66f373 | 793 | int can_id = 0, data1 = 0; |
e0000163 | 794 | |
f3a3ed31 SH |
795 | mcp251x_read_2regs(spi, CANINTF, &intf, &eflag); |
796 | ||
5601b2df MKB |
797 | /* mask out flags we don't care about */ |
798 | intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR; | |
799 | ||
d3cd1565 | 800 | /* receive buffer 0 */ |
bf66f373 CP |
801 | if (intf & CANINTF_RX0IF) { |
802 | mcp251x_hw_rx(spi, 0); | |
9c473fc3 MKB |
803 | /* |
804 | * Free one buffer ASAP | |
805 | * (The MCP2515 does this automatically.) | |
806 | */ | |
807 | if (mcp251x_is_2510(spi)) | |
808 | mcp251x_write_bits(spi, CANINTF, CANINTF_RX0IF, 0x00); | |
e0000163 CP |
809 | } |
810 | ||
d3cd1565 MKB |
811 | /* receive buffer 1 */ |
812 | if (intf & CANINTF_RX1IF) { | |
bf66f373 | 813 | mcp251x_hw_rx(spi, 1); |
9c473fc3 MKB |
814 | /* the MCP2515 does this automatically */ |
815 | if (mcp251x_is_2510(spi)) | |
816 | clear_intf |= CANINTF_RX1IF; | |
d3cd1565 | 817 | } |
e0000163 | 818 | |
d3cd1565 | 819 | /* any error or tx interrupt we need to clear? */ |
5601b2df MKB |
820 | if (intf & (CANINTF_ERR | CANINTF_TX)) |
821 | clear_intf |= intf & (CANINTF_ERR | CANINTF_TX); | |
d3cd1565 MKB |
822 | if (clear_intf) |
823 | mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00); | |
e0000163 | 824 | |
7e15de3a SH |
825 | if (eflag) |
826 | mcp251x_write_bits(spi, EFLG, eflag, 0x00); | |
bf66f373 | 827 | |
e0000163 CP |
828 | /* Update can state */ |
829 | if (eflag & EFLG_TXBO) { | |
830 | new_state = CAN_STATE_BUS_OFF; | |
831 | can_id |= CAN_ERR_BUSOFF; | |
832 | } else if (eflag & EFLG_TXEP) { | |
833 | new_state = CAN_STATE_ERROR_PASSIVE; | |
834 | can_id |= CAN_ERR_CRTL; | |
835 | data1 |= CAN_ERR_CRTL_TX_PASSIVE; | |
836 | } else if (eflag & EFLG_RXEP) { | |
837 | new_state = CAN_STATE_ERROR_PASSIVE; | |
838 | can_id |= CAN_ERR_CRTL; | |
839 | data1 |= CAN_ERR_CRTL_RX_PASSIVE; | |
840 | } else if (eflag & EFLG_TXWAR) { | |
841 | new_state = CAN_STATE_ERROR_WARNING; | |
842 | can_id |= CAN_ERR_CRTL; | |
843 | data1 |= CAN_ERR_CRTL_TX_WARNING; | |
844 | } else if (eflag & EFLG_RXWAR) { | |
845 | new_state = CAN_STATE_ERROR_WARNING; | |
846 | can_id |= CAN_ERR_CRTL; | |
847 | data1 |= CAN_ERR_CRTL_RX_WARNING; | |
848 | } else { | |
849 | new_state = CAN_STATE_ERROR_ACTIVE; | |
850 | } | |
851 | ||
852 | /* Update can state statistics */ | |
853 | switch (priv->can.state) { | |
854 | case CAN_STATE_ERROR_ACTIVE: | |
855 | if (new_state >= CAN_STATE_ERROR_WARNING && | |
856 | new_state <= CAN_STATE_BUS_OFF) | |
857 | priv->can.can_stats.error_warning++; | |
858 | case CAN_STATE_ERROR_WARNING: /* fallthrough */ | |
859 | if (new_state >= CAN_STATE_ERROR_PASSIVE && | |
860 | new_state <= CAN_STATE_BUS_OFF) | |
861 | priv->can.can_stats.error_passive++; | |
862 | break; | |
863 | default: | |
864 | break; | |
865 | } | |
866 | priv->can.state = new_state; | |
867 | ||
bf66f373 CP |
868 | if (intf & CANINTF_ERRIF) { |
869 | /* Handle overflow counters */ | |
870 | if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) { | |
711e4d6e | 871 | if (eflag & EFLG_RX0OVR) { |
bf66f373 | 872 | net->stats.rx_over_errors++; |
711e4d6e SH |
873 | net->stats.rx_errors++; |
874 | } | |
875 | if (eflag & EFLG_RX1OVR) { | |
bf66f373 | 876 | net->stats.rx_over_errors++; |
711e4d6e SH |
877 | net->stats.rx_errors++; |
878 | } | |
bf66f373 CP |
879 | can_id |= CAN_ERR_CRTL; |
880 | data1 |= CAN_ERR_CRTL_RX_OVERFLOW; | |
e0000163 | 881 | } |
bf66f373 | 882 | mcp251x_error_skb(net, can_id, data1); |
e0000163 CP |
883 | } |
884 | ||
885 | if (priv->can.state == CAN_STATE_BUS_OFF) { | |
886 | if (priv->can.restart_ms == 0) { | |
bf66f373 | 887 | priv->force_quit = 1; |
e0000163 CP |
888 | can_bus_off(net); |
889 | mcp251x_hw_sleep(spi); | |
bf66f373 | 890 | break; |
e0000163 CP |
891 | } |
892 | } | |
893 | ||
894 | if (intf == 0) | |
895 | break; | |
896 | ||
5601b2df | 897 | if (intf & CANINTF_TX) { |
e0000163 CP |
898 | net->stats.tx_packets++; |
899 | net->stats.tx_bytes += priv->tx_len - 1; | |
900 | if (priv->tx_len) { | |
901 | can_get_echo_skb(net, 0); | |
902 | priv->tx_len = 0; | |
903 | } | |
904 | netif_wake_queue(net); | |
905 | } | |
906 | ||
bf66f373 CP |
907 | } |
908 | mutex_unlock(&priv->mcp_lock); | |
909 | return IRQ_HANDLED; | |
910 | } | |
e0000163 | 911 | |
bf66f373 CP |
912 | static int mcp251x_open(struct net_device *net) |
913 | { | |
914 | struct mcp251x_priv *priv = netdev_priv(net); | |
915 | struct spi_device *spi = priv->spi; | |
916 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
917 | int ret; | |
918 | ||
919 | ret = open_candev(net); | |
920 | if (ret) { | |
921 | dev_err(&spi->dev, "unable to set initial baudrate!\n"); | |
922 | return ret; | |
923 | } | |
924 | ||
925 | mutex_lock(&priv->mcp_lock); | |
926 | if (pdata->transceiver_enable) | |
927 | pdata->transceiver_enable(1); | |
928 | ||
929 | priv->force_quit = 0; | |
930 | priv->tx_skb = NULL; | |
931 | priv->tx_len = 0; | |
932 | ||
933 | ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist, | |
34206f26 EBS |
934 | pdata->irq_flags ? pdata->irq_flags : IRQF_TRIGGER_FALLING, |
935 | DEVICE_NAME, priv); | |
bf66f373 CP |
936 | if (ret) { |
937 | dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq); | |
938 | if (pdata->transceiver_enable) | |
939 | pdata->transceiver_enable(0); | |
940 | close_candev(net); | |
941 | goto open_unlock; | |
942 | } | |
943 | ||
58a69cb4 | 944 | priv->wq = create_freezable_workqueue("mcp251x_wq"); |
bf66f373 CP |
945 | INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler); |
946 | INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler); | |
947 | ||
948 | ret = mcp251x_hw_reset(spi); | |
949 | if (ret) { | |
950 | mcp251x_open_clean(net); | |
951 | goto open_unlock; | |
952 | } | |
953 | ret = mcp251x_setup(net, priv, spi); | |
954 | if (ret) { | |
955 | mcp251x_open_clean(net); | |
956 | goto open_unlock; | |
e0000163 | 957 | } |
bf66f373 CP |
958 | ret = mcp251x_set_normal_mode(spi); |
959 | if (ret) { | |
960 | mcp251x_open_clean(net); | |
961 | goto open_unlock; | |
962 | } | |
963 | netif_wake_queue(net); | |
964 | ||
965 | open_unlock: | |
966 | mutex_unlock(&priv->mcp_lock); | |
967 | return ret; | |
e0000163 CP |
968 | } |
969 | ||
970 | static const struct net_device_ops mcp251x_netdev_ops = { | |
971 | .ndo_open = mcp251x_open, | |
972 | .ndo_stop = mcp251x_stop, | |
973 | .ndo_start_xmit = mcp251x_hard_start_xmit, | |
974 | }; | |
975 | ||
976 | static int __devinit mcp251x_can_probe(struct spi_device *spi) | |
977 | { | |
978 | struct net_device *net; | |
979 | struct mcp251x_priv *priv; | |
980 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
981 | int ret = -ENODEV; | |
982 | ||
983 | if (!pdata) | |
984 | /* Platform data is required for osc freq */ | |
985 | goto error_out; | |
986 | ||
987 | /* Allocate can/net device */ | |
988 | net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX); | |
989 | if (!net) { | |
990 | ret = -ENOMEM; | |
991 | goto error_alloc; | |
992 | } | |
993 | ||
994 | net->netdev_ops = &mcp251x_netdev_ops; | |
995 | net->flags |= IFF_ECHO; | |
996 | ||
997 | priv = netdev_priv(net); | |
998 | priv->can.bittiming_const = &mcp251x_bittiming_const; | |
999 | priv->can.do_set_mode = mcp251x_do_set_mode; | |
1000 | priv->can.clock.freq = pdata->oscillator_frequency / 2; | |
ad72c347 CP |
1001 | priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES | |
1002 | CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY; | |
f1f8c6cb | 1003 | priv->model = spi_get_device_id(spi)->driver_data; |
e0000163 CP |
1004 | priv->net = net; |
1005 | dev_set_drvdata(&spi->dev, priv); | |
1006 | ||
1007 | priv->spi = spi; | |
bf66f373 | 1008 | mutex_init(&priv->mcp_lock); |
e0000163 CP |
1009 | |
1010 | /* If requested, allocate DMA buffers */ | |
1011 | if (mcp251x_enable_dma) { | |
1012 | spi->dev.coherent_dma_mask = ~0; | |
1013 | ||
1014 | /* | |
1015 | * Minimum coherent DMA allocation is PAGE_SIZE, so allocate | |
1016 | * that much and share it between Tx and Rx DMA buffers. | |
1017 | */ | |
1018 | priv->spi_tx_buf = dma_alloc_coherent(&spi->dev, | |
1019 | PAGE_SIZE, | |
1020 | &priv->spi_tx_dma, | |
1021 | GFP_DMA); | |
1022 | ||
1023 | if (priv->spi_tx_buf) { | |
1024 | priv->spi_rx_buf = (u8 *)(priv->spi_tx_buf + | |
1025 | (PAGE_SIZE / 2)); | |
1026 | priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma + | |
1027 | (PAGE_SIZE / 2)); | |
1028 | } else { | |
1029 | /* Fall back to non-DMA */ | |
1030 | mcp251x_enable_dma = 0; | |
1031 | } | |
1032 | } | |
1033 | ||
1034 | /* Allocate non-DMA buffers */ | |
1035 | if (!mcp251x_enable_dma) { | |
1036 | priv->spi_tx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL); | |
1037 | if (!priv->spi_tx_buf) { | |
1038 | ret = -ENOMEM; | |
1039 | goto error_tx_buf; | |
1040 | } | |
1041 | priv->spi_rx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL); | |
ce739b47 | 1042 | if (!priv->spi_rx_buf) { |
e0000163 CP |
1043 | ret = -ENOMEM; |
1044 | goto error_rx_buf; | |
1045 | } | |
1046 | } | |
1047 | ||
1048 | if (pdata->power_enable) | |
1049 | pdata->power_enable(1); | |
1050 | ||
1051 | /* Call out to platform specific setup */ | |
1052 | if (pdata->board_specific_setup) | |
1053 | pdata->board_specific_setup(spi); | |
1054 | ||
1055 | SET_NETDEV_DEV(net, &spi->dev); | |
1056 | ||
e0000163 CP |
1057 | /* Configure the SPI bus */ |
1058 | spi->mode = SPI_MODE_0; | |
1059 | spi->bits_per_word = 8; | |
1060 | spi_setup(spi); | |
1061 | ||
bf66f373 | 1062 | /* Here is OK to not lock the MCP, no one knows about it yet */ |
e0000163 CP |
1063 | if (!mcp251x_hw_probe(spi)) { |
1064 | dev_info(&spi->dev, "Probe failed\n"); | |
1065 | goto error_probe; | |
1066 | } | |
1067 | mcp251x_hw_sleep(spi); | |
1068 | ||
1069 | if (pdata->transceiver_enable) | |
1070 | pdata->transceiver_enable(0); | |
1071 | ||
1072 | ret = register_candev(net); | |
1073 | if (!ret) { | |
1074 | dev_info(&spi->dev, "probed\n"); | |
1075 | return ret; | |
1076 | } | |
1077 | error_probe: | |
1078 | if (!mcp251x_enable_dma) | |
1079 | kfree(priv->spi_rx_buf); | |
1080 | error_rx_buf: | |
1081 | if (!mcp251x_enable_dma) | |
1082 | kfree(priv->spi_tx_buf); | |
1083 | error_tx_buf: | |
1084 | free_candev(net); | |
1085 | if (mcp251x_enable_dma) | |
1086 | dma_free_coherent(&spi->dev, PAGE_SIZE, | |
1087 | priv->spi_tx_buf, priv->spi_tx_dma); | |
1088 | error_alloc: | |
1089 | if (pdata->power_enable) | |
1090 | pdata->power_enable(0); | |
1091 | dev_err(&spi->dev, "probe failed\n"); | |
1092 | error_out: | |
1093 | return ret; | |
1094 | } | |
1095 | ||
1096 | static int __devexit mcp251x_can_remove(struct spi_device *spi) | |
1097 | { | |
1098 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
1099 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
1100 | struct net_device *net = priv->net; | |
1101 | ||
1102 | unregister_candev(net); | |
1103 | free_candev(net); | |
1104 | ||
e0000163 CP |
1105 | if (mcp251x_enable_dma) { |
1106 | dma_free_coherent(&spi->dev, PAGE_SIZE, | |
1107 | priv->spi_tx_buf, priv->spi_tx_dma); | |
1108 | } else { | |
1109 | kfree(priv->spi_tx_buf); | |
1110 | kfree(priv->spi_rx_buf); | |
1111 | } | |
1112 | ||
1113 | if (pdata->power_enable) | |
1114 | pdata->power_enable(0); | |
1115 | ||
1116 | return 0; | |
1117 | } | |
1118 | ||
1119 | #ifdef CONFIG_PM | |
1120 | static int mcp251x_can_suspend(struct spi_device *spi, pm_message_t state) | |
1121 | { | |
1122 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
1123 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
1124 | struct net_device *net = priv->net; | |
1125 | ||
bf66f373 CP |
1126 | priv->force_quit = 1; |
1127 | disable_irq(spi->irq); | |
1128 | /* | |
1129 | * Note: at this point neither IST nor workqueues are running. | |
1130 | * open/stop cannot be called anyway so locking is not needed | |
1131 | */ | |
e0000163 CP |
1132 | if (netif_running(net)) { |
1133 | netif_device_detach(net); | |
1134 | ||
1135 | mcp251x_hw_sleep(spi); | |
1136 | if (pdata->transceiver_enable) | |
1137 | pdata->transceiver_enable(0); | |
1138 | priv->after_suspend = AFTER_SUSPEND_UP; | |
1139 | } else { | |
1140 | priv->after_suspend = AFTER_SUSPEND_DOWN; | |
1141 | } | |
1142 | ||
1143 | if (pdata->power_enable) { | |
1144 | pdata->power_enable(0); | |
1145 | priv->after_suspend |= AFTER_SUSPEND_POWER; | |
1146 | } | |
1147 | ||
1148 | return 0; | |
1149 | } | |
1150 | ||
1151 | static int mcp251x_can_resume(struct spi_device *spi) | |
1152 | { | |
1153 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
1154 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
1155 | ||
1156 | if (priv->after_suspend & AFTER_SUSPEND_POWER) { | |
1157 | pdata->power_enable(1); | |
bf66f373 | 1158 | queue_work(priv->wq, &priv->restart_work); |
e0000163 CP |
1159 | } else { |
1160 | if (priv->after_suspend & AFTER_SUSPEND_UP) { | |
1161 | if (pdata->transceiver_enable) | |
1162 | pdata->transceiver_enable(1); | |
bf66f373 | 1163 | queue_work(priv->wq, &priv->restart_work); |
e0000163 CP |
1164 | } else { |
1165 | priv->after_suspend = 0; | |
1166 | } | |
1167 | } | |
bf66f373 CP |
1168 | priv->force_quit = 0; |
1169 | enable_irq(spi->irq); | |
e0000163 CP |
1170 | return 0; |
1171 | } | |
1172 | #else | |
1173 | #define mcp251x_can_suspend NULL | |
1174 | #define mcp251x_can_resume NULL | |
1175 | #endif | |
1176 | ||
f1f8c6cb | 1177 | static const struct spi_device_id mcp251x_id_table[] = { |
e446630c MZ |
1178 | { "mcp2510", CAN_MCP251X_MCP2510 }, |
1179 | { "mcp2515", CAN_MCP251X_MCP2515 }, | |
1180 | { }, | |
1181 | }; | |
1182 | ||
1183 | MODULE_DEVICE_TABLE(spi, mcp251x_id_table); | |
1184 | ||
e0000163 CP |
1185 | static struct spi_driver mcp251x_can_driver = { |
1186 | .driver = { | |
1187 | .name = DEVICE_NAME, | |
1188 | .bus = &spi_bus_type, | |
1189 | .owner = THIS_MODULE, | |
1190 | }, | |
1191 | ||
e446630c | 1192 | .id_table = mcp251x_id_table, |
e0000163 CP |
1193 | .probe = mcp251x_can_probe, |
1194 | .remove = __devexit_p(mcp251x_can_remove), | |
1195 | .suspend = mcp251x_can_suspend, | |
1196 | .resume = mcp251x_can_resume, | |
1197 | }; | |
1198 | ||
1199 | static int __init mcp251x_can_init(void) | |
1200 | { | |
1201 | return spi_register_driver(&mcp251x_can_driver); | |
1202 | } | |
1203 | ||
1204 | static void __exit mcp251x_can_exit(void) | |
1205 | { | |
1206 | spi_unregister_driver(&mcp251x_can_driver); | |
1207 | } | |
1208 | ||
1209 | module_init(mcp251x_can_init); | |
1210 | module_exit(mcp251x_can_exit); | |
1211 | ||
1212 | MODULE_AUTHOR("Chris Elston <celston@katalix.com>, " | |
1213 | "Christian Pellegrin <chripell@evolware.org>"); | |
1214 | MODULE_DESCRIPTION("Microchip 251x CAN driver"); | |
1215 | MODULE_LICENSE("GPL v2"); |