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can: flexcan: fix use after free of priv
[deliverable/linux.git] / drivers / net / can / mcp251x.c
CommitLineData
e0000163
CP		 1/*
2 * CAN bus driver for Microchip 251x CAN Controller with SPI Interface
3 *
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
6 *
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
8 *
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
12 *
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
15 *
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
19 * Copyright 2007
20 *
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the version 2 of the GNU General Public License
23 * as published by the Free Software Foundation
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 *
34 *
35 *
36 * Your platform definition file should specify something like:
37 *
38 * static struct mcp251x_platform_data mcp251x_info = {
39 * .oscillator_frequency = 8000000,
40 * .board_specific_setup = &mcp251x_setup,
e0000163
CP		 41 * .power_enable = mcp251x_power_enable,
42 * .transceiver_enable = NULL,
43 * };
44 *
45 * static struct spi_board_info spi_board_info[] = {
46 * {
f1f8c6cb
MKB		 47 * .modalias = "mcp2510",
48 * // or "mcp2515" depending on your controller
e0000163
CP		 49 * .platform_data = &mcp251x_info,
50 * .irq = IRQ_EINT13,
51 * .max_speed_hz = 2*1000*1000,
52 * .chip_select = 2,
53 * },
54 * };
55 *
56 * Please see mcp251x.h for a description of the fields in
57 * struct mcp251x_platform_data.
58 *
59 */
60
e0000163
CP		 61#include <linux/can/core.h>
62#include <linux/can/dev.h>
63#include <linux/can/platform/mcp251x.h>
64#include <linux/completion.h>
65#include <linux/delay.h>
66#include <linux/device.h>
67#include <linux/dma-mapping.h>
68#include <linux/freezer.h>
69#include <linux/interrupt.h>
70#include <linux/io.h>
71#include <linux/kernel.h>
72#include <linux/module.h>
73#include <linux/netdevice.h>
74#include <linux/platform_device.h>
5a0e3ad6 75#include <linux/slab.h>
e0000163
CP		 76#include <linux/spi/spi.h>
77#include <linux/uaccess.h>
78
79/* SPI interface instruction set */
80#define INSTRUCTION_WRITE 0x02
81#define INSTRUCTION_READ 0x03
82#define INSTRUCTION_BIT_MODIFY 0x05
83#define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
84#define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
85#define INSTRUCTION_RESET 0xC0
86
87/* MPC251x registers */
88#define CANSTAT 0x0e
89#define CANCTRL 0x0f
90# define CANCTRL_REQOP_MASK 0xe0
91# define CANCTRL_REQOP_CONF 0x80
92# define CANCTRL_REQOP_LISTEN_ONLY 0x60
93# define CANCTRL_REQOP_LOOPBACK 0x40
94# define CANCTRL_REQOP_SLEEP 0x20
95# define CANCTRL_REQOP_NORMAL 0x00
96# define CANCTRL_OSM 0x08
97# define CANCTRL_ABAT 0x10
98#define TEC 0x1c
99#define REC 0x1d
100#define CNF1 0x2a
101# define CNF1_SJW_SHIFT 6
102#define CNF2 0x29
103# define CNF2_BTLMODE 0x80
104# define CNF2_SAM 0x40
105# define CNF2_PS1_SHIFT 3
106#define CNF3 0x28
107# define CNF3_SOF 0x08
108# define CNF3_WAKFIL 0x04
109# define CNF3_PHSEG2_MASK 0x07
110#define CANINTE 0x2b
111# define CANINTE_MERRE 0x80
112# define CANINTE_WAKIE 0x40
113# define CANINTE_ERRIE 0x20
114# define CANINTE_TX2IE 0x10
115# define CANINTE_TX1IE 0x08
116# define CANINTE_TX0IE 0x04
117# define CANINTE_RX1IE 0x02
118# define CANINTE_RX0IE 0x01
119#define CANINTF 0x2c
120# define CANINTF_MERRF 0x80
121# define CANINTF_WAKIF 0x40
122# define CANINTF_ERRIF 0x20
123# define CANINTF_TX2IF 0x10
124# define CANINTF_TX1IF 0x08
125# define CANINTF_TX0IF 0x04
126# define CANINTF_RX1IF 0x02
127# define CANINTF_RX0IF 0x01
5601b2df
MKB		 128# define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
129# define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
130# define CANINTF_ERR (CANINTF_ERRIF)
e0000163
CP		 131#define EFLG 0x2d
132# define EFLG_EWARN 0x01
133# define EFLG_RXWAR 0x02
134# define EFLG_TXWAR 0x04
135# define EFLG_RXEP 0x08
136# define EFLG_TXEP 0x10
137# define EFLG_TXBO 0x20
138# define EFLG_RX0OVR 0x40
139# define EFLG_RX1OVR 0x80
140#define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
141# define TXBCTRL_ABTF 0x40
142# define TXBCTRL_MLOA 0x20
143# define TXBCTRL_TXERR 0x10
144# define TXBCTRL_TXREQ 0x08
145#define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
146# define SIDH_SHIFT 3
147#define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
148# define SIDL_SID_MASK 7
149# define SIDL_SID_SHIFT 5
150# define SIDL_EXIDE_SHIFT 3
151# define SIDL_EID_SHIFT 16
152# define SIDL_EID_MASK 3
153#define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
154#define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
155#define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
156# define DLC_RTR_SHIFT 6
157#define TXBCTRL_OFF 0
158#define TXBSIDH_OFF 1
159#define TXBSIDL_OFF 2
160#define TXBEID8_OFF 3
161#define TXBEID0_OFF 4
162#define TXBDLC_OFF 5
163#define TXBDAT_OFF 6
164#define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
165# define RXBCTRL_BUKT 0x04
166# define RXBCTRL_RXM0 0x20
167# define RXBCTRL_RXM1 0x40
168#define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
169# define RXBSIDH_SHIFT 3
170#define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
171# define RXBSIDL_IDE 0x08
172# define RXBSIDL_EID 3
173# define RXBSIDL_SHIFT 5
174#define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
175#define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
176#define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
177# define RXBDLC_LEN_MASK 0x0f
178# define RXBDLC_RTR 0x40
179#define RXBCTRL_OFF 0
180#define RXBSIDH_OFF 1
181#define RXBSIDL_OFF 2
182#define RXBEID8_OFF 3
183#define RXBEID0_OFF 4
184#define RXBDLC_OFF 5
185#define RXBDAT_OFF 6
bf66f373
CP		 186#define RXFSIDH(n) ((n) * 4)
187#define RXFSIDL(n) ((n) * 4 + 1)
188#define RXFEID8(n) ((n) * 4 + 2)
189#define RXFEID0(n) ((n) * 4 + 3)
190#define RXMSIDH(n) ((n) * 4 + 0x20)
191#define RXMSIDL(n) ((n) * 4 + 0x21)
192#define RXMEID8(n) ((n) * 4 + 0x22)
193#define RXMEID0(n) ((n) * 4 + 0x23)
e0000163
CP		 194
195#define GET_BYTE(val, byte) \
196 (((val) >> ((byte) * 8)) & 0xff)
197#define SET_BYTE(val, byte) \
198 (((val) & 0xff) << ((byte) * 8))
199
200/*
201 * Buffer size required for the largest SPI transfer (i.e., reading a
202 * frame)
203 */
204#define CAN_FRAME_MAX_DATA_LEN 8
205#define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
206#define CAN_FRAME_MAX_BITS 128
207
208#define TX_ECHO_SKB_MAX 1
209
210#define DEVICE_NAME "mcp251x"
211
212static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */
213module_param(mcp251x_enable_dma, int, S_IRUGO);
214MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)");
215
216static struct can_bittiming_const mcp251x_bittiming_const = {
217 .name = DEVICE_NAME,
218 .tseg1_min = 3,
219 .tseg1_max = 16,
220 .tseg2_min = 2,
221 .tseg2_max = 8,
222 .sjw_max = 4,
223 .brp_min = 1,
224 .brp_max = 64,
225 .brp_inc = 1,
226};
227
f1f8c6cb
MKB		 228enum mcp251x_model {
229 CAN_MCP251X_MCP2510 = 0x2510,
230 CAN_MCP251X_MCP2515 = 0x2515,
231};
232
e0000163
CP		 233struct mcp251x_priv {
234 struct can_priv can;
235 struct net_device *net;
236 struct spi_device *spi;
f1f8c6cb 237 enum mcp251x_model model;
e0000163 238
bf66f373
CP		 239 struct mutex mcp_lock; /* SPI device lock */
240
e0000163
CP		 241 u8 *spi_tx_buf;
242 u8 *spi_rx_buf;
243 dma_addr_t spi_tx_dma;
244 dma_addr_t spi_rx_dma;
245
246 struct sk_buff *tx_skb;
247 int tx_len;
bf66f373 248
e0000163
CP		 249 struct workqueue_struct *wq;
250 struct work_struct tx_work;
bf66f373
CP		 251 struct work_struct restart_work;
252
e0000163
CP		 253 int force_quit;
254 int after_suspend;
255#define AFTER_SUSPEND_UP 1
256#define AFTER_SUSPEND_DOWN 2
257#define AFTER_SUSPEND_POWER 4
258#define AFTER_SUSPEND_RESTART 8
259 int restart_tx;
260};
261
beab675c
MKB		 262#define MCP251X_IS(_model) \
263static inline int mcp251x_is_##_model(struct spi_device *spi) \
264{ \
265 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); \
266 return priv->model == CAN_MCP251X_MCP##_model; \
267}
268
269MCP251X_IS(2510);
270MCP251X_IS(2515);
271
e0000163
CP		 272static void mcp251x_clean(struct net_device *net)
273{
274 struct mcp251x_priv *priv = netdev_priv(net);
275
bf66f373
CP		 276 if (priv->tx_skb || priv->tx_len)
277 net->stats.tx_errors++;
e0000163
CP		 278 if (priv->tx_skb)
279 dev_kfree_skb(priv->tx_skb);
280 if (priv->tx_len)
281 can_free_echo_skb(priv->net, 0);
282 priv->tx_skb = NULL;
283 priv->tx_len = 0;
284}
285
286/*
287 * Note about handling of error return of mcp251x_spi_trans: accessing
288 * registers via SPI is not really different conceptually than using
289 * normal I/O assembler instructions, although it's much more
290 * complicated from a practical POV. So it's not advisable to always
291 * check the return value of this function. Imagine that every
292 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
293 * error();", it would be a great mess (well there are some situation
294 * when exception handling C++ like could be useful after all). So we
295 * just check that transfers are OK at the beginning of our
296 * conversation with the chip and to avoid doing really nasty things
297 * (like injecting bogus packets in the network stack).
298 */
299static int mcp251x_spi_trans(struct spi_device *spi, int len)
300{
301 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
302 struct spi_transfer t = {
303 .tx_buf = priv->spi_tx_buf,
304 .rx_buf = priv->spi_rx_buf,
305 .len = len,
306 .cs_change = 0,
307 };
308 struct spi_message m;
309 int ret;
310
311 spi_message_init(&m);
312
313 if (mcp251x_enable_dma) {
314 t.tx_dma = priv->spi_tx_dma;
315 t.rx_dma = priv->spi_rx_dma;
316 m.is_dma_mapped = 1;
317 }
318
319 spi_message_add_tail(&t, &m);
320
321 ret = spi_sync(spi, &m);
322 if (ret)
323 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
324 return ret;
325}
326
327static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg)
328{
329 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
330 u8 val = 0;
331
e0000163
CP		 332 priv->spi_tx_buf[0] = INSTRUCTION_READ;
333 priv->spi_tx_buf[1] = reg;
334
335 mcp251x_spi_trans(spi, 3);
336 val = priv->spi_rx_buf[2];
337
e0000163
CP		 338 return val;
339}
340
f3a3ed31
SH		 341static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg,
342 uint8_t *v1, uint8_t *v2)
343{
344 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
345
346 priv->spi_tx_buf[0] = INSTRUCTION_READ;
347 priv->spi_tx_buf[1] = reg;
348
349 mcp251x_spi_trans(spi, 4);
350
351 *v1 = priv->spi_rx_buf[2];
352 *v2 = priv->spi_rx_buf[3];
353}
354
e0000163
CP		 355static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val)
356{
357 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
358
e0000163
CP		 359 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
360 priv->spi_tx_buf[1] = reg;
361 priv->spi_tx_buf[2] = val;
362
363 mcp251x_spi_trans(spi, 3);
e0000163
CP		 364}
365
366static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
367 u8 mask, uint8_t val)
368{
369 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
370
e0000163
CP		 371 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
372 priv->spi_tx_buf[1] = reg;
373 priv->spi_tx_buf[2] = mask;
374 priv->spi_tx_buf[3] = val;
375
376 mcp251x_spi_trans(spi, 4);
e0000163
CP		 377}
378
379static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
380 int len, int tx_buf_idx)
381{
e0000163
CP		 382 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
383
beab675c 384 if (mcp251x_is_2510(spi)) {
e0000163
CP		 385 int i;
386
387 for (i = 1; i < TXBDAT_OFF + len; i++)
388 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
389 buf[i]);
390 } else {
e0000163
CP		 391 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
392 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
e0000163
CP		 393 }
394}
395
396static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
397 int tx_buf_idx)
398{
399 u32 sid, eid, exide, rtr;
400 u8 buf[SPI_TRANSFER_BUF_LEN];
401
402 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
403 if (exide)
404 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
405 else
406 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
407 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
408 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
409
410 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
411 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
412 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
413 (exide << SIDL_EXIDE_SHIFT) |
414 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
415 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
416 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
417 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
418 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
419 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
420 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx), TXBCTRL_TXREQ);
421}
422
423static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
424 int buf_idx)
425{
426 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
e0000163 427
beab675c 428 if (mcp251x_is_2510(spi)) {
e0000163
CP		 429 int i, len;
430
431 for (i = 1; i < RXBDAT_OFF; i++)
432 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
c7cd606f
OH		 433
434 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
e0000163
CP		 435 for (; i < (RXBDAT_OFF + len); i++)
436 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
437 } else {
e0000163
CP		 438 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
439 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
440 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
e0000163
CP		 441 }
442}
443
444static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
445{
446 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
447 struct sk_buff *skb;
448 struct can_frame *frame;
449 u8 buf[SPI_TRANSFER_BUF_LEN];
450
451 skb = alloc_can_skb(priv->net, &frame);
452 if (!skb) {
453 dev_err(&spi->dev, "cannot allocate RX skb\n");
454 priv->net->stats.rx_dropped++;
455 return;
456 }
457
458 mcp251x_hw_rx_frame(spi, buf, buf_idx);
459 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
460 /* Extended ID format */
461 frame->can_id = CAN_EFF_FLAG;
462 frame->can_id |=
463 /* Extended ID part */
464 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
465 SET_BYTE(buf[RXBEID8_OFF], 1) |
466 SET_BYTE(buf[RXBEID0_OFF], 0) |
467 /* Standard ID part */
468 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
469 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
470 /* Remote transmission request */
471 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
472 frame->can_id |= CAN_RTR_FLAG;
473 } else {
474 /* Standard ID format */
475 frame->can_id =
476 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
477 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
478 }
479 /* Data length */
c7cd606f 480 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
e0000163
CP		 481 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
482
483 priv->net->stats.rx_packets++;
484 priv->net->stats.rx_bytes += frame->can_dlc;
57d3c7b0 485 netif_rx_ni(skb);
e0000163
CP		 486}
487
488static void mcp251x_hw_sleep(struct spi_device *spi)
489{
490 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
491}
492
e0000163
CP		 493static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
494 struct net_device *net)
495{
496 struct mcp251x_priv *priv = netdev_priv(net);
497 struct spi_device *spi = priv->spi;
498
499 if (priv->tx_skb || priv->tx_len) {
500 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
e0000163
CP		 501 return NETDEV_TX_BUSY;
502 }
503
3ccd4c61 504 if (can_dropped_invalid_skb(net, skb))
e0000163 505 return NETDEV_TX_OK;
e0000163
CP		 506
507 netif_stop_queue(net);
508 priv->tx_skb = skb;
e0000163
CP		 509 queue_work(priv->wq, &priv->tx_work);
510
511 return NETDEV_TX_OK;
512}
513
514static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
515{
516 struct mcp251x_priv *priv = netdev_priv(net);
517
518 switch (mode) {
519 case CAN_MODE_START:
bf66f373 520 mcp251x_clean(net);
e0000163
CP		 521 /* We have to delay work since SPI I/O may sleep */
522 priv->can.state = CAN_STATE_ERROR_ACTIVE;
523 priv->restart_tx = 1;
524 if (priv->can.restart_ms == 0)
525 priv->after_suspend = AFTER_SUSPEND_RESTART;
bf66f373 526 queue_work(priv->wq, &priv->restart_work);
e0000163
CP		 527 break;
528 default:
529 return -EOPNOTSUPP;
530 }
531
532 return 0;
533}
534
bf66f373 535static int mcp251x_set_normal_mode(struct spi_device *spi)
e0000163
CP		 536{
537 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
538 unsigned long timeout;
539
540 /* Enable interrupts */
541 mcp251x_write_reg(spi, CANINTE,
542 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
bf66f373 543 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
e0000163
CP		 544
545 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
546 /* Put device into loopback mode */
547 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
ad72c347
CP		 548 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
549 /* Put device into listen-only mode */
550 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
e0000163
CP		 551 } else {
552 /* Put device into normal mode */
bf66f373 553 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
e0000163
CP		 554
555 /* Wait for the device to enter normal mode */
556 timeout = jiffies + HZ;
557 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
558 schedule();
559 if (time_after(jiffies, timeout)) {
560 dev_err(&spi->dev, "MCP251x didn't"
561 " enter in normal mode\n");
bf66f373 562 return -EBUSY;
e0000163
CP		 563 }
564 }
565 }
566 priv->can.state = CAN_STATE_ERROR_ACTIVE;
bf66f373 567 return 0;
e0000163
CP		 568}
569
570static int mcp251x_do_set_bittiming(struct net_device *net)
571{
572 struct mcp251x_priv *priv = netdev_priv(net);
573 struct can_bittiming *bt = &priv->can.bittiming;
574 struct spi_device *spi = priv->spi;
575
576 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
577 (bt->brp - 1));
578 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
579 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
580 CNF2_SAM : 0) |
581 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
582 (bt->prop_seg - 1));
583 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
584 (bt->phase_seg2 - 1));
585 dev_info(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
586 mcp251x_read_reg(spi, CNF1),
587 mcp251x_read_reg(spi, CNF2),
588 mcp251x_read_reg(spi, CNF3));
589
590 return 0;
591}
592
593static int mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv,
594 struct spi_device *spi)
595{
615534bc 596 mcp251x_do_set_bittiming(net);
e0000163 597
bf66f373
CP		 598 mcp251x_write_reg(spi, RXBCTRL(0),
599 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
600 mcp251x_write_reg(spi, RXBCTRL(1),
601 RXBCTRL_RXM0 | RXBCTRL_RXM1);
e0000163
CP		 602 return 0;
603}
604
bf66f373 605static int mcp251x_hw_reset(struct spi_device *spi)
e0000163
CP		 606{
607 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
608 int ret;
bf66f373 609 unsigned long timeout;
e0000163
CP		 610
611 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
e0000163 612 ret = spi_write(spi, priv->spi_tx_buf, 1);
bf66f373 613 if (ret) {
e0000163 614 dev_err(&spi->dev, "reset failed: ret = %d\n", ret);
bf66f373
CP		 615 return -EIO;
616 }
617
e0000163 618 /* Wait for reset to finish */
bf66f373 619 timeout = jiffies + HZ;
e0000163 620 mdelay(10);
bf66f373
CP		 621 while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK)
622 != CANCTRL_REQOP_CONF) {
623 schedule();
624 if (time_after(jiffies, timeout)) {
625 dev_err(&spi->dev, "MCP251x didn't"
626 " enter in conf mode after reset\n");
627 return -EBUSY;
628 }
629 }
630 return 0;
e0000163
CP		 631}
632
633static int mcp251x_hw_probe(struct spi_device *spi)
634{
635 int st1, st2;
636
637 mcp251x_hw_reset(spi);
638
639 /*
640 * Please note that these are "magic values" based on after
641 * reset defaults taken from data sheet which allows us to see
642 * if we really have a chip on the bus (we avoid common all
643 * zeroes or all ones situations)
644 */
645 st1 = mcp251x_read_reg(spi, CANSTAT) & 0xEE;
646 st2 = mcp251x_read_reg(spi, CANCTRL) & 0x17;
647
648 dev_dbg(&spi->dev, "CANSTAT 0x%02x CANCTRL 0x%02x\n", st1, st2);
649
650 /* Check for power up default values */
651 return (st1 == 0x80 && st2 == 0x07) ? 1 : 0;
652}
653
bf66f373 654static void mcp251x_open_clean(struct net_device *net)
e0000163
CP		 655{
656 struct mcp251x_priv *priv = netdev_priv(net);
657 struct spi_device *spi = priv->spi;
658 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
615534bc 659
bf66f373
CP		 660 free_irq(spi->irq, priv);
661 mcp251x_hw_sleep(spi);
e0000163 662 if (pdata->transceiver_enable)
bf66f373
CP		 663 pdata->transceiver_enable(0);
664 close_candev(net);
e0000163
CP		 665}
666
667static int mcp251x_stop(struct net_device *net)
668{
669 struct mcp251x_priv *priv = netdev_priv(net);
670 struct spi_device *spi = priv->spi;
671 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
672
673 close_candev(net);
674
bf66f373
CP		 675 priv->force_quit = 1;
676 free_irq(spi->irq, priv);
677 destroy_workqueue(priv->wq);
678 priv->wq = NULL;
679
680 mutex_lock(&priv->mcp_lock);
681
e0000163
CP		 682 /* Disable and clear pending interrupts */
683 mcp251x_write_reg(spi, CANINTE, 0x00);
684 mcp251x_write_reg(spi, CANINTF, 0x00);
685
e0000163 686 mcp251x_write_reg(spi, TXBCTRL(0), 0);
bf66f373 687 mcp251x_clean(net);
e0000163
CP		 688
689 mcp251x_hw_sleep(spi);
690
691 if (pdata->transceiver_enable)
692 pdata->transceiver_enable(0);
693
694 priv->can.state = CAN_STATE_STOPPED;
695
bf66f373
CP		 696 mutex_unlock(&priv->mcp_lock);
697
e0000163
CP		 698 return 0;
699}
700
bf66f373
CP		 701static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
702{
703 struct sk_buff *skb;
704 struct can_frame *frame;
705
706 skb = alloc_can_err_skb(net, &frame);
707 if (skb) {
612eef4f 708 frame->can_id |= can_id;
bf66f373 709 frame->data[1] = data1;
57d3c7b0 710 netif_rx_ni(skb);
bf66f373
CP		 711 } else {
712 dev_err(&net->dev,
713 "cannot allocate error skb\n");
714 }
715}
716
e0000163
CP		 717static void mcp251x_tx_work_handler(struct work_struct *ws)
718{
719 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
720 tx_work);
721 struct spi_device *spi = priv->spi;
722 struct net_device *net = priv->net;
723 struct can_frame *frame;
724
bf66f373 725 mutex_lock(&priv->mcp_lock);
e0000163 726 if (priv->tx_skb) {
e0000163
CP		 727 if (priv->can.state == CAN_STATE_BUS_OFF) {
728 mcp251x_clean(net);
bf66f373
CP		 729 } else {
730 frame = (struct can_frame *)priv->tx_skb->data;
731
732 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
733 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
734 mcp251x_hw_tx(spi, frame, 0);
735 priv->tx_len = 1 + frame->can_dlc;
736 can_put_echo_skb(priv->tx_skb, net, 0);
737 priv->tx_skb = NULL;
e0000163 738 }
e0000163 739 }
bf66f373 740 mutex_unlock(&priv->mcp_lock);
e0000163
CP		 741}
742
bf66f373 743static void mcp251x_restart_work_handler(struct work_struct *ws)
e0000163
CP		 744{
745 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
bf66f373 746 restart_work);
e0000163
CP		 747 struct spi_device *spi = priv->spi;
748 struct net_device *net = priv->net;
e0000163 749
bf66f373 750 mutex_lock(&priv->mcp_lock);
e0000163
CP		 751 if (priv->after_suspend) {
752 mdelay(10);
753 mcp251x_hw_reset(spi);
754 mcp251x_setup(net, priv, spi);
755 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
756 mcp251x_set_normal_mode(spi);
757 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
758 netif_device_attach(net);
bf66f373 759 mcp251x_clean(net);
e0000163 760 mcp251x_set_normal_mode(spi);
bf66f373 761 netif_wake_queue(net);
e0000163
CP		 762 } else {
763 mcp251x_hw_sleep(spi);
764 }
765 priv->after_suspend = 0;
bf66f373 766 priv->force_quit = 0;
e0000163
CP		 767 }
768
bf66f373
CP		 769 if (priv->restart_tx) {
770 priv->restart_tx = 0;
771 mcp251x_write_reg(spi, TXBCTRL(0), 0);
772 mcp251x_clean(net);
773 netif_wake_queue(net);
774 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
775 }
776 mutex_unlock(&priv->mcp_lock);
777}
e0000163 778
bf66f373
CP		 779static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
780{
781 struct mcp251x_priv *priv = dev_id;
782 struct spi_device *spi = priv->spi;
783 struct net_device *net = priv->net;
e0000163 784
bf66f373
CP		 785 mutex_lock(&priv->mcp_lock);
786 while (!priv->force_quit) {
787 enum can_state new_state;
f3a3ed31 788 u8 intf, eflag;
d3cd1565 789 u8 clear_intf = 0;
bf66f373 790 int can_id = 0, data1 = 0;
e0000163 791
f3a3ed31
SH		 792 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
793
5601b2df
MKB		 794 /* mask out flags we don't care about */
795 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
796
d3cd1565 797 /* receive buffer 0 */
bf66f373
CP		 798 if (intf & CANINTF_RX0IF) {
799 mcp251x_hw_rx(spi, 0);
9c473fc3
MKB		 800 /*
801 * Free one buffer ASAP
802 * (The MCP2515 does this automatically.)
803 */
804 if (mcp251x_is_2510(spi))
805 mcp251x_write_bits(spi, CANINTF, CANINTF_RX0IF, 0x00);
e0000163
CP		 806 }
807
d3cd1565
MKB		 808 /* receive buffer 1 */
809 if (intf & CANINTF_RX1IF) {
bf66f373 810 mcp251x_hw_rx(spi, 1);
9c473fc3
MKB		 811 /* the MCP2515 does this automatically */
812 if (mcp251x_is_2510(spi))
813 clear_intf |= CANINTF_RX1IF;
d3cd1565 814 }
e0000163 815
d3cd1565 816 /* any error or tx interrupt we need to clear? */
5601b2df
MKB		 817 if (intf & (CANINTF_ERR | CANINTF_TX))
818 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
d3cd1565
MKB		 819 if (clear_intf)
820 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
e0000163 821
7e15de3a
SH		 822 if (eflag)
823 mcp251x_write_bits(spi, EFLG, eflag, 0x00);
bf66f373 824
e0000163
CP		 825 /* Update can state */
826 if (eflag & EFLG_TXBO) {
827 new_state = CAN_STATE_BUS_OFF;
828 can_id |= CAN_ERR_BUSOFF;
829 } else if (eflag & EFLG_TXEP) {
830 new_state = CAN_STATE_ERROR_PASSIVE;
831 can_id |= CAN_ERR_CRTL;
832 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
833 } else if (eflag & EFLG_RXEP) {
834 new_state = CAN_STATE_ERROR_PASSIVE;
835 can_id |= CAN_ERR_CRTL;
836 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
837 } else if (eflag & EFLG_TXWAR) {
838 new_state = CAN_STATE_ERROR_WARNING;
839 can_id |= CAN_ERR_CRTL;
840 data1 |= CAN_ERR_CRTL_TX_WARNING;
841 } else if (eflag & EFLG_RXWAR) {
842 new_state = CAN_STATE_ERROR_WARNING;
843 can_id |= CAN_ERR_CRTL;
844 data1 |= CAN_ERR_CRTL_RX_WARNING;
845 } else {
846 new_state = CAN_STATE_ERROR_ACTIVE;
847 }
848
849 /* Update can state statistics */
850 switch (priv->can.state) {
851 case CAN_STATE_ERROR_ACTIVE:
852 if (new_state >= CAN_STATE_ERROR_WARNING &&
853 new_state <= CAN_STATE_BUS_OFF)
854 priv->can.can_stats.error_warning++;
855 case CAN_STATE_ERROR_WARNING: /* fallthrough */
856 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
857 new_state <= CAN_STATE_BUS_OFF)
858 priv->can.can_stats.error_passive++;
859 break;
860 default:
861 break;
862 }
863 priv->can.state = new_state;
864
bf66f373
CP		 865 if (intf & CANINTF_ERRIF) {
866 /* Handle overflow counters */
867 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
711e4d6e 868 if (eflag & EFLG_RX0OVR) {
bf66f373 869 net->stats.rx_over_errors++;
711e4d6e
SH		 870 net->stats.rx_errors++;
871 }
872 if (eflag & EFLG_RX1OVR) {
bf66f373 873 net->stats.rx_over_errors++;
711e4d6e
SH		 874 net->stats.rx_errors++;
875 }
bf66f373
CP		 876 can_id |= CAN_ERR_CRTL;
877 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
e0000163 878 }
bf66f373 879 mcp251x_error_skb(net, can_id, data1);
e0000163
CP		 880 }
881
882 if (priv->can.state == CAN_STATE_BUS_OFF) {
883 if (priv->can.restart_ms == 0) {
bf66f373 884 priv->force_quit = 1;
e0000163
CP		 885 can_bus_off(net);
886 mcp251x_hw_sleep(spi);
bf66f373 887 break;
e0000163
CP		 888 }
889 }
890
891 if (intf == 0)
892 break;
893
5601b2df 894 if (intf & CANINTF_TX) {
e0000163
CP		 895 net->stats.tx_packets++;
896 net->stats.tx_bytes += priv->tx_len - 1;
897 if (priv->tx_len) {
898 can_get_echo_skb(net, 0);
899 priv->tx_len = 0;
900 }
901 netif_wake_queue(net);
902 }
903
bf66f373
CP		 904 }
905 mutex_unlock(&priv->mcp_lock);
906 return IRQ_HANDLED;
907}
e0000163 908
bf66f373
CP		 909static int mcp251x_open(struct net_device *net)
910{
911 struct mcp251x_priv *priv = netdev_priv(net);
912 struct spi_device *spi = priv->spi;
913 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
914 int ret;
915
916 ret = open_candev(net);
917 if (ret) {
918 dev_err(&spi->dev, "unable to set initial baudrate!\n");
919 return ret;
920 }
921
922 mutex_lock(&priv->mcp_lock);
923 if (pdata->transceiver_enable)
924 pdata->transceiver_enable(1);
925
926 priv->force_quit = 0;
927 priv->tx_skb = NULL;
928 priv->tx_len = 0;
929
930 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
931 IRQF_TRIGGER_FALLING, DEVICE_NAME, priv);
932 if (ret) {
933 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
934 if (pdata->transceiver_enable)
935 pdata->transceiver_enable(0);
936 close_candev(net);
937 goto open_unlock;
938 }
939
940 priv->wq = create_freezeable_workqueue("mcp251x_wq");
941 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
942 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
943
944 ret = mcp251x_hw_reset(spi);
945 if (ret) {
946 mcp251x_open_clean(net);
947 goto open_unlock;
948 }
949 ret = mcp251x_setup(net, priv, spi);
950 if (ret) {
951 mcp251x_open_clean(net);
952 goto open_unlock;
e0000163 953 }
bf66f373
CP		 954 ret = mcp251x_set_normal_mode(spi);
955 if (ret) {
956 mcp251x_open_clean(net);
957 goto open_unlock;
958 }
959 netif_wake_queue(net);
960
961open_unlock:
962 mutex_unlock(&priv->mcp_lock);
963 return ret;
e0000163
CP		 964}
965
966static const struct net_device_ops mcp251x_netdev_ops = {
967 .ndo_open = mcp251x_open,
968 .ndo_stop = mcp251x_stop,
969 .ndo_start_xmit = mcp251x_hard_start_xmit,
970};
971
972static int __devinit mcp251x_can_probe(struct spi_device *spi)
973{
974 struct net_device *net;
975 struct mcp251x_priv *priv;
976 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
977 int ret = -ENODEV;
978
979 if (!pdata)
980 /* Platform data is required for osc freq */
981 goto error_out;
982
983 /* Allocate can/net device */
984 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
985 if (!net) {
986 ret = -ENOMEM;
987 goto error_alloc;
988 }
989
990 net->netdev_ops = &mcp251x_netdev_ops;
991 net->flags |= IFF_ECHO;
992
993 priv = netdev_priv(net);
994 priv->can.bittiming_const = &mcp251x_bittiming_const;
995 priv->can.do_set_mode = mcp251x_do_set_mode;
996 priv->can.clock.freq = pdata->oscillator_frequency / 2;
ad72c347
CP		 997 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
998 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
f1f8c6cb 999 priv->model = spi_get_device_id(spi)->driver_data;
e0000163
CP		 1000 priv->net = net;
1001 dev_set_drvdata(&spi->dev, priv);
1002
1003 priv->spi = spi;
bf66f373 1004 mutex_init(&priv->mcp_lock);
e0000163
CP		 1005
1006 /* If requested, allocate DMA buffers */
1007 if (mcp251x_enable_dma) {
1008 spi->dev.coherent_dma_mask = ~0;
1009
1010 /*
1011 * Minimum coherent DMA allocation is PAGE_SIZE, so allocate
1012 * that much and share it between Tx and Rx DMA buffers.
1013 */
1014 priv->spi_tx_buf = dma_alloc_coherent(&spi->dev,
1015 PAGE_SIZE,
1016 &priv->spi_tx_dma,
1017 GFP_DMA);
1018
1019 if (priv->spi_tx_buf) {
1020 priv->spi_rx_buf = (u8 *)(priv->spi_tx_buf +
1021 (PAGE_SIZE / 2));
1022 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma +
1023 (PAGE_SIZE / 2));
1024 } else {
1025 /* Fall back to non-DMA */
1026 mcp251x_enable_dma = 0;
1027 }
1028 }
1029
1030 /* Allocate non-DMA buffers */
1031 if (!mcp251x_enable_dma) {
1032 priv->spi_tx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
1033 if (!priv->spi_tx_buf) {
1034 ret = -ENOMEM;
1035 goto error_tx_buf;
1036 }
1037 priv->spi_rx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
ce739b47 1038 if (!priv->spi_rx_buf) {
e0000163
CP		 1039 ret = -ENOMEM;
1040 goto error_rx_buf;
1041 }
1042 }
1043
1044 if (pdata->power_enable)
1045 pdata->power_enable(1);
1046
1047 /* Call out to platform specific setup */
1048 if (pdata->board_specific_setup)
1049 pdata->board_specific_setup(spi);
1050
1051 SET_NETDEV_DEV(net, &spi->dev);
1052
e0000163
CP		 1053 /* Configure the SPI bus */
1054 spi->mode = SPI_MODE_0;
1055 spi->bits_per_word = 8;
1056 spi_setup(spi);
1057
bf66f373 1058 /* Here is OK to not lock the MCP, no one knows about it yet */
e0000163
CP		 1059 if (!mcp251x_hw_probe(spi)) {
1060 dev_info(&spi->dev, "Probe failed\n");
1061 goto error_probe;
1062 }
1063 mcp251x_hw_sleep(spi);
1064
1065 if (pdata->transceiver_enable)
1066 pdata->transceiver_enable(0);
1067
1068 ret = register_candev(net);
1069 if (!ret) {
1070 dev_info(&spi->dev, "probed\n");
1071 return ret;
1072 }
1073error_probe:
1074 if (!mcp251x_enable_dma)
1075 kfree(priv->spi_rx_buf);
1076error_rx_buf:
1077 if (!mcp251x_enable_dma)
1078 kfree(priv->spi_tx_buf);
1079error_tx_buf:
1080 free_candev(net);
1081 if (mcp251x_enable_dma)
1082 dma_free_coherent(&spi->dev, PAGE_SIZE,
1083 priv->spi_tx_buf, priv->spi_tx_dma);
1084error_alloc:
1085 if (pdata->power_enable)
1086 pdata->power_enable(0);
1087 dev_err(&spi->dev, "probe failed\n");
1088error_out:
1089 return ret;
1090}
1091
1092static int __devexit mcp251x_can_remove(struct spi_device *spi)
1093{
1094 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1095 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1096 struct net_device *net = priv->net;
1097
1098 unregister_candev(net);
1099 free_candev(net);
1100
e0000163
CP		 1101 if (mcp251x_enable_dma) {
1102 dma_free_coherent(&spi->dev, PAGE_SIZE,
1103 priv->spi_tx_buf, priv->spi_tx_dma);
1104 } else {
1105 kfree(priv->spi_tx_buf);
1106 kfree(priv->spi_rx_buf);
1107 }
1108
1109 if (pdata->power_enable)
1110 pdata->power_enable(0);
1111
1112 return 0;
1113}
1114
1115#ifdef CONFIG_PM
1116static int mcp251x_can_suspend(struct spi_device *spi, pm_message_t state)
1117{
1118 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1119 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1120 struct net_device *net = priv->net;
1121
bf66f373
CP		 1122 priv->force_quit = 1;
1123 disable_irq(spi->irq);
1124 /*
1125 * Note: at this point neither IST nor workqueues are running.
1126 * open/stop cannot be called anyway so locking is not needed
1127 */
e0000163
CP		 1128 if (netif_running(net)) {
1129 netif_device_detach(net);
1130
1131 mcp251x_hw_sleep(spi);
1132 if (pdata->transceiver_enable)
1133 pdata->transceiver_enable(0);
1134 priv->after_suspend = AFTER_SUSPEND_UP;
1135 } else {
1136 priv->after_suspend = AFTER_SUSPEND_DOWN;
1137 }
1138
1139 if (pdata->power_enable) {
1140 pdata->power_enable(0);
1141 priv->after_suspend |= AFTER_SUSPEND_POWER;
1142 }
1143
1144 return 0;
1145}
1146
1147static int mcp251x_can_resume(struct spi_device *spi)
1148{
1149 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1150 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1151
1152 if (priv->after_suspend & AFTER_SUSPEND_POWER) {
1153 pdata->power_enable(1);
bf66f373 1154 queue_work(priv->wq, &priv->restart_work);
e0000163
CP		 1155 } else {
1156 if (priv->after_suspend & AFTER_SUSPEND_UP) {
1157 if (pdata->transceiver_enable)
1158 pdata->transceiver_enable(1);
bf66f373 1159 queue_work(priv->wq, &priv->restart_work);
e0000163
CP		 1160 } else {
1161 priv->after_suspend = 0;
1162 }
1163 }
bf66f373
CP		 1164 priv->force_quit = 0;
1165 enable_irq(spi->irq);
e0000163
CP		 1166 return 0;
1167}
1168#else
1169#define mcp251x_can_suspend NULL
1170#define mcp251x_can_resume NULL
1171#endif
1172
f1f8c6cb 1173static const struct spi_device_id mcp251x_id_table[] = {
e446630c
MZ		 1174 { "mcp2510", CAN_MCP251X_MCP2510 },
1175 { "mcp2515", CAN_MCP251X_MCP2515 },
1176 { },
1177};
1178
1179MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
1180
e0000163
CP		 1181static struct spi_driver mcp251x_can_driver = {
1182 .driver = {
1183 .name = DEVICE_NAME,
1184 .bus = &spi_bus_type,
1185 .owner = THIS_MODULE,
1186 },
1187
e446630c 1188 .id_table = mcp251x_id_table,
e0000163
CP		 1189 .probe = mcp251x_can_probe,
1190 .remove = __devexit_p(mcp251x_can_remove),
1191 .suspend = mcp251x_can_suspend,
1192 .resume = mcp251x_can_resume,
1193};
1194
1195static int __init mcp251x_can_init(void)
1196{
1197 return spi_register_driver(&mcp251x_can_driver);
1198}
1199
1200static void __exit mcp251x_can_exit(void)
1201{
1202 spi_unregister_driver(&mcp251x_can_driver);
1203}
1204
1205module_init(mcp251x_can_init);
1206module_exit(mcp251x_can_exit);
1207
1208MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1209 "Christian Pellegrin <chripell@evolware.org>");
1210MODULE_DESCRIPTION("Microchip 251x CAN driver");
1211MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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