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can: mcp251x: write intf only when needed
[deliverable/linux.git] / drivers / net / can / mcp251x.c
CommitLineData
e0000163
CP		 1/*
2 * CAN bus driver for Microchip 251x CAN Controller with SPI Interface
3 *
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
6 *
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
8 *
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
12 *
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
15 *
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
19 * Copyright 2007
20 *
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the version 2 of the GNU General Public License
23 * as published by the Free Software Foundation
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 *
34 *
35 *
36 * Your platform definition file should specify something like:
37 *
38 * static struct mcp251x_platform_data mcp251x_info = {
39 * .oscillator_frequency = 8000000,
40 * .board_specific_setup = &mcp251x_setup,
41 * .model = CAN_MCP251X_MCP2510,
42 * .power_enable = mcp251x_power_enable,
43 * .transceiver_enable = NULL,
44 * };
45 *
46 * static struct spi_board_info spi_board_info[] = {
47 * {
48 * .modalias = "mcp251x",
49 * .platform_data = &mcp251x_info,
50 * .irq = IRQ_EINT13,
51 * .max_speed_hz = 2*1000*1000,
52 * .chip_select = 2,
53 * },
54 * };
55 *
56 * Please see mcp251x.h for a description of the fields in
57 * struct mcp251x_platform_data.
58 *
59 */
60
e0000163
CP		 61#include <linux/can/core.h>
62#include <linux/can/dev.h>
63#include <linux/can/platform/mcp251x.h>
64#include <linux/completion.h>
65#include <linux/delay.h>
66#include <linux/device.h>
67#include <linux/dma-mapping.h>
68#include <linux/freezer.h>
69#include <linux/interrupt.h>
70#include <linux/io.h>
71#include <linux/kernel.h>
72#include <linux/module.h>
73#include <linux/netdevice.h>
74#include <linux/platform_device.h>
5a0e3ad6 75#include <linux/slab.h>
e0000163
CP		 76#include <linux/spi/spi.h>
77#include <linux/uaccess.h>
78
79/* SPI interface instruction set */
80#define INSTRUCTION_WRITE 0x02
81#define INSTRUCTION_READ 0x03
82#define INSTRUCTION_BIT_MODIFY 0x05
83#define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
84#define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
85#define INSTRUCTION_RESET 0xC0
86
87/* MPC251x registers */
88#define CANSTAT 0x0e
89#define CANCTRL 0x0f
90# define CANCTRL_REQOP_MASK 0xe0
91# define CANCTRL_REQOP_CONF 0x80
92# define CANCTRL_REQOP_LISTEN_ONLY 0x60
93# define CANCTRL_REQOP_LOOPBACK 0x40
94# define CANCTRL_REQOP_SLEEP 0x20
95# define CANCTRL_REQOP_NORMAL 0x00
96# define CANCTRL_OSM 0x08
97# define CANCTRL_ABAT 0x10
98#define TEC 0x1c
99#define REC 0x1d
100#define CNF1 0x2a
101# define CNF1_SJW_SHIFT 6
102#define CNF2 0x29
103# define CNF2_BTLMODE 0x80
104# define CNF2_SAM 0x40
105# define CNF2_PS1_SHIFT 3
106#define CNF3 0x28
107# define CNF3_SOF 0x08
108# define CNF3_WAKFIL 0x04
109# define CNF3_PHSEG2_MASK 0x07
110#define CANINTE 0x2b
111# define CANINTE_MERRE 0x80
112# define CANINTE_WAKIE 0x40
113# define CANINTE_ERRIE 0x20
114# define CANINTE_TX2IE 0x10
115# define CANINTE_TX1IE 0x08
116# define CANINTE_TX0IE 0x04
117# define CANINTE_RX1IE 0x02
118# define CANINTE_RX0IE 0x01
119#define CANINTF 0x2c
120# define CANINTF_MERRF 0x80
121# define CANINTF_WAKIF 0x40
122# define CANINTF_ERRIF 0x20
123# define CANINTF_TX2IF 0x10
124# define CANINTF_TX1IF 0x08
125# define CANINTF_TX0IF 0x04
126# define CANINTF_RX1IF 0x02
127# define CANINTF_RX0IF 0x01
d3cd1565
MKB		 128# define CANINTF_ERR_TX \
129 (CANINTF_ERRIF | CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
e0000163
CP		 130#define EFLG 0x2d
131# define EFLG_EWARN 0x01
132# define EFLG_RXWAR 0x02
133# define EFLG_TXWAR 0x04
134# define EFLG_RXEP 0x08
135# define EFLG_TXEP 0x10
136# define EFLG_TXBO 0x20
137# define EFLG_RX0OVR 0x40
138# define EFLG_RX1OVR 0x80
139#define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
140# define TXBCTRL_ABTF 0x40
141# define TXBCTRL_MLOA 0x20
142# define TXBCTRL_TXERR 0x10
143# define TXBCTRL_TXREQ 0x08
144#define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
145# define SIDH_SHIFT 3
146#define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
147# define SIDL_SID_MASK 7
148# define SIDL_SID_SHIFT 5
149# define SIDL_EXIDE_SHIFT 3
150# define SIDL_EID_SHIFT 16
151# define SIDL_EID_MASK 3
152#define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
153#define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
154#define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
155# define DLC_RTR_SHIFT 6
156#define TXBCTRL_OFF 0
157#define TXBSIDH_OFF 1
158#define TXBSIDL_OFF 2
159#define TXBEID8_OFF 3
160#define TXBEID0_OFF 4
161#define TXBDLC_OFF 5
162#define TXBDAT_OFF 6
163#define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
164# define RXBCTRL_BUKT 0x04
165# define RXBCTRL_RXM0 0x20
166# define RXBCTRL_RXM1 0x40
167#define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
168# define RXBSIDH_SHIFT 3
169#define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
170# define RXBSIDL_IDE 0x08
171# define RXBSIDL_EID 3
172# define RXBSIDL_SHIFT 5
173#define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
174#define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
175#define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
176# define RXBDLC_LEN_MASK 0x0f
177# define RXBDLC_RTR 0x40
178#define RXBCTRL_OFF 0
179#define RXBSIDH_OFF 1
180#define RXBSIDL_OFF 2
181#define RXBEID8_OFF 3
182#define RXBEID0_OFF 4
183#define RXBDLC_OFF 5
184#define RXBDAT_OFF 6
bf66f373
CP		 185#define RXFSIDH(n) ((n) * 4)
186#define RXFSIDL(n) ((n) * 4 + 1)
187#define RXFEID8(n) ((n) * 4 + 2)
188#define RXFEID0(n) ((n) * 4 + 3)
189#define RXMSIDH(n) ((n) * 4 + 0x20)
190#define RXMSIDL(n) ((n) * 4 + 0x21)
191#define RXMEID8(n) ((n) * 4 + 0x22)
192#define RXMEID0(n) ((n) * 4 + 0x23)
e0000163
CP		 193
194#define GET_BYTE(val, byte) \
195 (((val) >> ((byte) * 8)) & 0xff)
196#define SET_BYTE(val, byte) \
197 (((val) & 0xff) << ((byte) * 8))
198
199/*
200 * Buffer size required for the largest SPI transfer (i.e., reading a
201 * frame)
202 */
203#define CAN_FRAME_MAX_DATA_LEN 8
204#define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
205#define CAN_FRAME_MAX_BITS 128
206
207#define TX_ECHO_SKB_MAX 1
208
209#define DEVICE_NAME "mcp251x"
210
211static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */
212module_param(mcp251x_enable_dma, int, S_IRUGO);
213MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)");
214
215static struct can_bittiming_const mcp251x_bittiming_const = {
216 .name = DEVICE_NAME,
217 .tseg1_min = 3,
218 .tseg1_max = 16,
219 .tseg2_min = 2,
220 .tseg2_max = 8,
221 .sjw_max = 4,
222 .brp_min = 1,
223 .brp_max = 64,
224 .brp_inc = 1,
225};
226
227struct mcp251x_priv {
228 struct can_priv can;
229 struct net_device *net;
230 struct spi_device *spi;
231
bf66f373
CP		 232 struct mutex mcp_lock; /* SPI device lock */
233
e0000163
CP		 234 u8 *spi_tx_buf;
235 u8 *spi_rx_buf;
236 dma_addr_t spi_tx_dma;
237 dma_addr_t spi_rx_dma;
238
239 struct sk_buff *tx_skb;
240 int tx_len;
bf66f373 241
e0000163
CP		 242 struct workqueue_struct *wq;
243 struct work_struct tx_work;
bf66f373
CP		 244 struct work_struct restart_work;
245
e0000163
CP		 246 int force_quit;
247 int after_suspend;
248#define AFTER_SUSPEND_UP 1
249#define AFTER_SUSPEND_DOWN 2
250#define AFTER_SUSPEND_POWER 4
251#define AFTER_SUSPEND_RESTART 8
252 int restart_tx;
253};
254
255static void mcp251x_clean(struct net_device *net)
256{
257 struct mcp251x_priv *priv = netdev_priv(net);
258
bf66f373
CP		 259 if (priv->tx_skb || priv->tx_len)
260 net->stats.tx_errors++;
e0000163
CP		 261 if (priv->tx_skb)
262 dev_kfree_skb(priv->tx_skb);
263 if (priv->tx_len)
264 can_free_echo_skb(priv->net, 0);
265 priv->tx_skb = NULL;
266 priv->tx_len = 0;
267}
268
269/*
270 * Note about handling of error return of mcp251x_spi_trans: accessing
271 * registers via SPI is not really different conceptually than using
272 * normal I/O assembler instructions, although it's much more
273 * complicated from a practical POV. So it's not advisable to always
274 * check the return value of this function. Imagine that every
275 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
276 * error();", it would be a great mess (well there are some situation
277 * when exception handling C++ like could be useful after all). So we
278 * just check that transfers are OK at the beginning of our
279 * conversation with the chip and to avoid doing really nasty things
280 * (like injecting bogus packets in the network stack).
281 */
282static int mcp251x_spi_trans(struct spi_device *spi, int len)
283{
284 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
285 struct spi_transfer t = {
286 .tx_buf = priv->spi_tx_buf,
287 .rx_buf = priv->spi_rx_buf,
288 .len = len,
289 .cs_change = 0,
290 };
291 struct spi_message m;
292 int ret;
293
294 spi_message_init(&m);
295
296 if (mcp251x_enable_dma) {
297 t.tx_dma = priv->spi_tx_dma;
298 t.rx_dma = priv->spi_rx_dma;
299 m.is_dma_mapped = 1;
300 }
301
302 spi_message_add_tail(&t, &m);
303
304 ret = spi_sync(spi, &m);
305 if (ret)
306 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
307 return ret;
308}
309
310static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg)
311{
312 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
313 u8 val = 0;
314
e0000163
CP		 315 priv->spi_tx_buf[0] = INSTRUCTION_READ;
316 priv->spi_tx_buf[1] = reg;
317
318 mcp251x_spi_trans(spi, 3);
319 val = priv->spi_rx_buf[2];
320
e0000163
CP		 321 return val;
322}
323
f3a3ed31
SH		 324static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg,
325 uint8_t *v1, uint8_t *v2)
326{
327 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
328
329 priv->spi_tx_buf[0] = INSTRUCTION_READ;
330 priv->spi_tx_buf[1] = reg;
331
332 mcp251x_spi_trans(spi, 4);
333
334 *v1 = priv->spi_rx_buf[2];
335 *v2 = priv->spi_rx_buf[3];
336}
337
e0000163
CP		 338static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val)
339{
340 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
341
e0000163
CP		 342 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
343 priv->spi_tx_buf[1] = reg;
344 priv->spi_tx_buf[2] = val;
345
346 mcp251x_spi_trans(spi, 3);
e0000163
CP		 347}
348
349static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
350 u8 mask, uint8_t val)
351{
352 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
353
e0000163
CP		 354 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
355 priv->spi_tx_buf[1] = reg;
356 priv->spi_tx_buf[2] = mask;
357 priv->spi_tx_buf[3] = val;
358
359 mcp251x_spi_trans(spi, 4);
e0000163
CP		 360}
361
362static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
363 int len, int tx_buf_idx)
364{
365 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
366 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
367
368 if (pdata->model == CAN_MCP251X_MCP2510) {
369 int i;
370
371 for (i = 1; i < TXBDAT_OFF + len; i++)
372 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
373 buf[i]);
374 } else {
e0000163
CP		 375 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
376 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
e0000163
CP		 377 }
378}
379
380static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
381 int tx_buf_idx)
382{
383 u32 sid, eid, exide, rtr;
384 u8 buf[SPI_TRANSFER_BUF_LEN];
385
386 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
387 if (exide)
388 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
389 else
390 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
391 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
392 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
393
394 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
395 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
396 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
397 (exide << SIDL_EXIDE_SHIFT) |
398 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
399 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
400 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
401 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
402 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
403 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
404 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx), TXBCTRL_TXREQ);
405}
406
407static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
408 int buf_idx)
409{
410 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
411 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
412
413 if (pdata->model == CAN_MCP251X_MCP2510) {
414 int i, len;
415
416 for (i = 1; i < RXBDAT_OFF; i++)
417 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
c7cd606f
OH		 418
419 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
e0000163
CP		 420 for (; i < (RXBDAT_OFF + len); i++)
421 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
422 } else {
e0000163
CP		 423 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
424 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
425 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
e0000163
CP		 426 }
427}
428
429static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
430{
431 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
432 struct sk_buff *skb;
433 struct can_frame *frame;
434 u8 buf[SPI_TRANSFER_BUF_LEN];
435
436 skb = alloc_can_skb(priv->net, &frame);
437 if (!skb) {
438 dev_err(&spi->dev, "cannot allocate RX skb\n");
439 priv->net->stats.rx_dropped++;
440 return;
441 }
442
443 mcp251x_hw_rx_frame(spi, buf, buf_idx);
444 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
445 /* Extended ID format */
446 frame->can_id = CAN_EFF_FLAG;
447 frame->can_id |=
448 /* Extended ID part */
449 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
450 SET_BYTE(buf[RXBEID8_OFF], 1) |
451 SET_BYTE(buf[RXBEID0_OFF], 0) |
452 /* Standard ID part */
453 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
454 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
455 /* Remote transmission request */
456 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
457 frame->can_id |= CAN_RTR_FLAG;
458 } else {
459 /* Standard ID format */
460 frame->can_id =
461 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
462 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
463 }
464 /* Data length */
c7cd606f 465 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
e0000163
CP		 466 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
467
468 priv->net->stats.rx_packets++;
469 priv->net->stats.rx_bytes += frame->can_dlc;
57d3c7b0 470 netif_rx_ni(skb);
e0000163
CP		 471}
472
473static void mcp251x_hw_sleep(struct spi_device *spi)
474{
475 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
476}
477
e0000163
CP		 478static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
479 struct net_device *net)
480{
481 struct mcp251x_priv *priv = netdev_priv(net);
482 struct spi_device *spi = priv->spi;
483
484 if (priv->tx_skb || priv->tx_len) {
485 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
e0000163
CP		 486 return NETDEV_TX_BUSY;
487 }
488
3ccd4c61 489 if (can_dropped_invalid_skb(net, skb))
e0000163 490 return NETDEV_TX_OK;
e0000163
CP		 491
492 netif_stop_queue(net);
493 priv->tx_skb = skb;
e0000163
CP		 494 queue_work(priv->wq, &priv->tx_work);
495
496 return NETDEV_TX_OK;
497}
498
499static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
500{
501 struct mcp251x_priv *priv = netdev_priv(net);
502
503 switch (mode) {
504 case CAN_MODE_START:
bf66f373 505 mcp251x_clean(net);
e0000163
CP		 506 /* We have to delay work since SPI I/O may sleep */
507 priv->can.state = CAN_STATE_ERROR_ACTIVE;
508 priv->restart_tx = 1;
509 if (priv->can.restart_ms == 0)
510 priv->after_suspend = AFTER_SUSPEND_RESTART;
bf66f373 511 queue_work(priv->wq, &priv->restart_work);
e0000163
CP		 512 break;
513 default:
514 return -EOPNOTSUPP;
515 }
516
517 return 0;
518}
519
bf66f373 520static int mcp251x_set_normal_mode(struct spi_device *spi)
e0000163
CP		 521{
522 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
523 unsigned long timeout;
524
525 /* Enable interrupts */
526 mcp251x_write_reg(spi, CANINTE,
527 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
bf66f373 528 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
e0000163
CP		 529
530 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
531 /* Put device into loopback mode */
532 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
ad72c347
CP		 533 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
534 /* Put device into listen-only mode */
535 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
e0000163
CP		 536 } else {
537 /* Put device into normal mode */
bf66f373 538 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
e0000163
CP		 539
540 /* Wait for the device to enter normal mode */
541 timeout = jiffies + HZ;
542 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
543 schedule();
544 if (time_after(jiffies, timeout)) {
545 dev_err(&spi->dev, "MCP251x didn't"
546 " enter in normal mode\n");
bf66f373 547 return -EBUSY;
e0000163
CP		 548 }
549 }
550 }
551 priv->can.state = CAN_STATE_ERROR_ACTIVE;
bf66f373 552 return 0;
e0000163
CP		 553}
554
555static int mcp251x_do_set_bittiming(struct net_device *net)
556{
557 struct mcp251x_priv *priv = netdev_priv(net);
558 struct can_bittiming *bt = &priv->can.bittiming;
559 struct spi_device *spi = priv->spi;
560
561 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
562 (bt->brp - 1));
563 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
564 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
565 CNF2_SAM : 0) |
566 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
567 (bt->prop_seg - 1));
568 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
569 (bt->phase_seg2 - 1));
570 dev_info(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
571 mcp251x_read_reg(spi, CNF1),
572 mcp251x_read_reg(spi, CNF2),
573 mcp251x_read_reg(spi, CNF3));
574
575 return 0;
576}
577
578static int mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv,
579 struct spi_device *spi)
580{
615534bc 581 mcp251x_do_set_bittiming(net);
e0000163 582
bf66f373
CP		 583 mcp251x_write_reg(spi, RXBCTRL(0),
584 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
585 mcp251x_write_reg(spi, RXBCTRL(1),
586 RXBCTRL_RXM0 | RXBCTRL_RXM1);
e0000163
CP		 587 return 0;
588}
589
bf66f373 590static int mcp251x_hw_reset(struct spi_device *spi)
e0000163
CP		 591{
592 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
593 int ret;
bf66f373 594 unsigned long timeout;
e0000163
CP		 595
596 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
e0000163 597 ret = spi_write(spi, priv->spi_tx_buf, 1);
bf66f373 598 if (ret) {
e0000163 599 dev_err(&spi->dev, "reset failed: ret = %d\n", ret);
bf66f373
CP		 600 return -EIO;
601 }
602
e0000163 603 /* Wait for reset to finish */
bf66f373 604 timeout = jiffies + HZ;
e0000163 605 mdelay(10);
bf66f373
CP		 606 while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK)
607 != CANCTRL_REQOP_CONF) {
608 schedule();
609 if (time_after(jiffies, timeout)) {
610 dev_err(&spi->dev, "MCP251x didn't"
611 " enter in conf mode after reset\n");
612 return -EBUSY;
613 }
614 }
615 return 0;
e0000163
CP		 616}
617
618static int mcp251x_hw_probe(struct spi_device *spi)
619{
620 int st1, st2;
621
622 mcp251x_hw_reset(spi);
623
624 /*
625 * Please note that these are "magic values" based on after
626 * reset defaults taken from data sheet which allows us to see
627 * if we really have a chip on the bus (we avoid common all
628 * zeroes or all ones situations)
629 */
630 st1 = mcp251x_read_reg(spi, CANSTAT) & 0xEE;
631 st2 = mcp251x_read_reg(spi, CANCTRL) & 0x17;
632
633 dev_dbg(&spi->dev, "CANSTAT 0x%02x CANCTRL 0x%02x\n", st1, st2);
634
635 /* Check for power up default values */
636 return (st1 == 0x80 && st2 == 0x07) ? 1 : 0;
637}
638
bf66f373 639static void mcp251x_open_clean(struct net_device *net)
e0000163
CP		 640{
641 struct mcp251x_priv *priv = netdev_priv(net);
642 struct spi_device *spi = priv->spi;
643 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
615534bc 644
bf66f373
CP		 645 free_irq(spi->irq, priv);
646 mcp251x_hw_sleep(spi);
e0000163 647 if (pdata->transceiver_enable)
bf66f373
CP		 648 pdata->transceiver_enable(0);
649 close_candev(net);
e0000163
CP		 650}
651
652static int mcp251x_stop(struct net_device *net)
653{
654 struct mcp251x_priv *priv = netdev_priv(net);
655 struct spi_device *spi = priv->spi;
656 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
657
658 close_candev(net);
659
bf66f373
CP		 660 priv->force_quit = 1;
661 free_irq(spi->irq, priv);
662 destroy_workqueue(priv->wq);
663 priv->wq = NULL;
664
665 mutex_lock(&priv->mcp_lock);
666
e0000163
CP		 667 /* Disable and clear pending interrupts */
668 mcp251x_write_reg(spi, CANINTE, 0x00);
669 mcp251x_write_reg(spi, CANINTF, 0x00);
670
e0000163 671 mcp251x_write_reg(spi, TXBCTRL(0), 0);
bf66f373 672 mcp251x_clean(net);
e0000163
CP		 673
674 mcp251x_hw_sleep(spi);
675
676 if (pdata->transceiver_enable)
677 pdata->transceiver_enable(0);
678
679 priv->can.state = CAN_STATE_STOPPED;
680
bf66f373
CP		 681 mutex_unlock(&priv->mcp_lock);
682
e0000163
CP		 683 return 0;
684}
685
bf66f373
CP		 686static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
687{
688 struct sk_buff *skb;
689 struct can_frame *frame;
690
691 skb = alloc_can_err_skb(net, &frame);
692 if (skb) {
693 frame->can_id = can_id;
694 frame->data[1] = data1;
57d3c7b0 695 netif_rx_ni(skb);
bf66f373
CP		 696 } else {
697 dev_err(&net->dev,
698 "cannot allocate error skb\n");
699 }
700}
701
e0000163
CP		 702static void mcp251x_tx_work_handler(struct work_struct *ws)
703{
704 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
705 tx_work);
706 struct spi_device *spi = priv->spi;
707 struct net_device *net = priv->net;
708 struct can_frame *frame;
709
bf66f373 710 mutex_lock(&priv->mcp_lock);
e0000163 711 if (priv->tx_skb) {
e0000163
CP		 712 if (priv->can.state == CAN_STATE_BUS_OFF) {
713 mcp251x_clean(net);
bf66f373
CP		 714 } else {
715 frame = (struct can_frame *)priv->tx_skb->data;
716
717 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
718 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
719 mcp251x_hw_tx(spi, frame, 0);
720 priv->tx_len = 1 + frame->can_dlc;
721 can_put_echo_skb(priv->tx_skb, net, 0);
722 priv->tx_skb = NULL;
e0000163 723 }
e0000163 724 }
bf66f373 725 mutex_unlock(&priv->mcp_lock);
e0000163
CP		 726}
727
bf66f373 728static void mcp251x_restart_work_handler(struct work_struct *ws)
e0000163
CP		 729{
730 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
bf66f373 731 restart_work);
e0000163
CP		 732 struct spi_device *spi = priv->spi;
733 struct net_device *net = priv->net;
e0000163 734
bf66f373 735 mutex_lock(&priv->mcp_lock);
e0000163
CP		 736 if (priv->after_suspend) {
737 mdelay(10);
738 mcp251x_hw_reset(spi);
739 mcp251x_setup(net, priv, spi);
740 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
741 mcp251x_set_normal_mode(spi);
742 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
743 netif_device_attach(net);
bf66f373 744 mcp251x_clean(net);
e0000163 745 mcp251x_set_normal_mode(spi);
bf66f373 746 netif_wake_queue(net);
e0000163
CP		 747 } else {
748 mcp251x_hw_sleep(spi);
749 }
750 priv->after_suspend = 0;
bf66f373 751 priv->force_quit = 0;
e0000163
CP		 752 }
753
bf66f373
CP		 754 if (priv->restart_tx) {
755 priv->restart_tx = 0;
756 mcp251x_write_reg(spi, TXBCTRL(0), 0);
757 mcp251x_clean(net);
758 netif_wake_queue(net);
759 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
760 }
761 mutex_unlock(&priv->mcp_lock);
762}
e0000163 763
bf66f373
CP		 764static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
765{
766 struct mcp251x_priv *priv = dev_id;
767 struct spi_device *spi = priv->spi;
768 struct net_device *net = priv->net;
e0000163 769
bf66f373
CP		 770 mutex_lock(&priv->mcp_lock);
771 while (!priv->force_quit) {
772 enum can_state new_state;
f3a3ed31 773 u8 intf, eflag;
d3cd1565 774 u8 clear_intf = 0;
bf66f373 775 int can_id = 0, data1 = 0;
e0000163 776
f3a3ed31
SH		 777 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
778
d3cd1565 779 /* receive buffer 0 */
bf66f373
CP		 780 if (intf & CANINTF_RX0IF) {
781 mcp251x_hw_rx(spi, 0);
782 /* Free one buffer ASAP */
783 mcp251x_write_bits(spi, CANINTF, intf & CANINTF_RX0IF,
784 0x00);
e0000163
CP		 785 }
786
d3cd1565
MKB		 787 /* receive buffer 1 */
788 if (intf & CANINTF_RX1IF) {
bf66f373 789 mcp251x_hw_rx(spi, 1);
d3cd1565
MKB		 790 clear_intf |= CANINTF_RX1IF;
791 }
e0000163 792
d3cd1565
MKB		 793 /* any error or tx interrupt we need to clear? */
794 if (intf & CANINTF_ERR_TX)
795 clear_intf |= intf & CANINTF_ERR_TX;
796 if (clear_intf)
797 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
e0000163 798
7e15de3a
SH		 799 if (eflag)
800 mcp251x_write_bits(spi, EFLG, eflag, 0x00);
bf66f373 801
e0000163
CP		 802 /* Update can state */
803 if (eflag & EFLG_TXBO) {
804 new_state = CAN_STATE_BUS_OFF;
805 can_id |= CAN_ERR_BUSOFF;
806 } else if (eflag & EFLG_TXEP) {
807 new_state = CAN_STATE_ERROR_PASSIVE;
808 can_id |= CAN_ERR_CRTL;
809 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
810 } else if (eflag & EFLG_RXEP) {
811 new_state = CAN_STATE_ERROR_PASSIVE;
812 can_id |= CAN_ERR_CRTL;
813 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
814 } else if (eflag & EFLG_TXWAR) {
815 new_state = CAN_STATE_ERROR_WARNING;
816 can_id |= CAN_ERR_CRTL;
817 data1 |= CAN_ERR_CRTL_TX_WARNING;
818 } else if (eflag & EFLG_RXWAR) {
819 new_state = CAN_STATE_ERROR_WARNING;
820 can_id |= CAN_ERR_CRTL;
821 data1 |= CAN_ERR_CRTL_RX_WARNING;
822 } else {
823 new_state = CAN_STATE_ERROR_ACTIVE;
824 }
825
826 /* Update can state statistics */
827 switch (priv->can.state) {
828 case CAN_STATE_ERROR_ACTIVE:
829 if (new_state >= CAN_STATE_ERROR_WARNING &&
830 new_state <= CAN_STATE_BUS_OFF)
831 priv->can.can_stats.error_warning++;
832 case CAN_STATE_ERROR_WARNING: /* fallthrough */
833 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
834 new_state <= CAN_STATE_BUS_OFF)
835 priv->can.can_stats.error_passive++;
836 break;
837 default:
838 break;
839 }
840 priv->can.state = new_state;
841
bf66f373
CP		 842 if (intf & CANINTF_ERRIF) {
843 /* Handle overflow counters */
844 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
711e4d6e 845 if (eflag & EFLG_RX0OVR) {
bf66f373 846 net->stats.rx_over_errors++;
711e4d6e
SH		 847 net->stats.rx_errors++;
848 }
849 if (eflag & EFLG_RX1OVR) {
bf66f373 850 net->stats.rx_over_errors++;
711e4d6e
SH		 851 net->stats.rx_errors++;
852 }
bf66f373
CP		 853 can_id |= CAN_ERR_CRTL;
854 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
e0000163 855 }
bf66f373 856 mcp251x_error_skb(net, can_id, data1);
e0000163
CP		 857 }
858
859 if (priv->can.state == CAN_STATE_BUS_OFF) {
860 if (priv->can.restart_ms == 0) {
bf66f373 861 priv->force_quit = 1;
e0000163
CP		 862 can_bus_off(net);
863 mcp251x_hw_sleep(spi);
bf66f373 864 break;
e0000163
CP		 865 }
866 }
867
868 if (intf == 0)
869 break;
870
e0000163
CP		 871 if (intf & (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)) {
872 net->stats.tx_packets++;
873 net->stats.tx_bytes += priv->tx_len - 1;
874 if (priv->tx_len) {
875 can_get_echo_skb(net, 0);
876 priv->tx_len = 0;
877 }
878 netif_wake_queue(net);
879 }
880
bf66f373
CP		 881 }
882 mutex_unlock(&priv->mcp_lock);
883 return IRQ_HANDLED;
884}
e0000163 885
bf66f373
CP		 886static int mcp251x_open(struct net_device *net)
887{
888 struct mcp251x_priv *priv = netdev_priv(net);
889 struct spi_device *spi = priv->spi;
890 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
891 int ret;
892
893 ret = open_candev(net);
894 if (ret) {
895 dev_err(&spi->dev, "unable to set initial baudrate!\n");
896 return ret;
897 }
898
899 mutex_lock(&priv->mcp_lock);
900 if (pdata->transceiver_enable)
901 pdata->transceiver_enable(1);
902
903 priv->force_quit = 0;
904 priv->tx_skb = NULL;
905 priv->tx_len = 0;
906
907 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
908 IRQF_TRIGGER_FALLING, DEVICE_NAME, priv);
909 if (ret) {
910 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
911 if (pdata->transceiver_enable)
912 pdata->transceiver_enable(0);
913 close_candev(net);
914 goto open_unlock;
915 }
916
917 priv->wq = create_freezeable_workqueue("mcp251x_wq");
918 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
919 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
920
921 ret = mcp251x_hw_reset(spi);
922 if (ret) {
923 mcp251x_open_clean(net);
924 goto open_unlock;
925 }
926 ret = mcp251x_setup(net, priv, spi);
927 if (ret) {
928 mcp251x_open_clean(net);
929 goto open_unlock;
e0000163 930 }
bf66f373
CP		 931 ret = mcp251x_set_normal_mode(spi);
932 if (ret) {
933 mcp251x_open_clean(net);
934 goto open_unlock;
935 }
936 netif_wake_queue(net);
937
938open_unlock:
939 mutex_unlock(&priv->mcp_lock);
940 return ret;
e0000163
CP		 941}
942
943static const struct net_device_ops mcp251x_netdev_ops = {
944 .ndo_open = mcp251x_open,
945 .ndo_stop = mcp251x_stop,
946 .ndo_start_xmit = mcp251x_hard_start_xmit,
947};
948
949static int __devinit mcp251x_can_probe(struct spi_device *spi)
950{
951 struct net_device *net;
952 struct mcp251x_priv *priv;
953 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
e446630c 954 int model = spi_get_device_id(spi)->driver_data;
e0000163
CP		 955 int ret = -ENODEV;
956
957 if (!pdata)
958 /* Platform data is required for osc freq */
959 goto error_out;
960
e446630c
MZ		 961 if (model)
962 pdata->model = model;
963
e0000163
CP		 964 /* Allocate can/net device */
965 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
966 if (!net) {
967 ret = -ENOMEM;
968 goto error_alloc;
969 }
970
971 net->netdev_ops = &mcp251x_netdev_ops;
972 net->flags |= IFF_ECHO;
973
974 priv = netdev_priv(net);
975 priv->can.bittiming_const = &mcp251x_bittiming_const;
976 priv->can.do_set_mode = mcp251x_do_set_mode;
977 priv->can.clock.freq = pdata->oscillator_frequency / 2;
ad72c347
CP		 978 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
979 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
e0000163
CP		 980 priv->net = net;
981 dev_set_drvdata(&spi->dev, priv);
982
983 priv->spi = spi;
bf66f373 984 mutex_init(&priv->mcp_lock);
e0000163
CP		 985
986 /* If requested, allocate DMA buffers */
987 if (mcp251x_enable_dma) {
988 spi->dev.coherent_dma_mask = ~0;
989
990 /*
991 * Minimum coherent DMA allocation is PAGE_SIZE, so allocate
992 * that much and share it between Tx and Rx DMA buffers.
993 */
994 priv->spi_tx_buf = dma_alloc_coherent(&spi->dev,
995 PAGE_SIZE,
996 &priv->spi_tx_dma,
997 GFP_DMA);
998
999 if (priv->spi_tx_buf) {
1000 priv->spi_rx_buf = (u8 *)(priv->spi_tx_buf +
1001 (PAGE_SIZE / 2));
1002 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma +
1003 (PAGE_SIZE / 2));
1004 } else {
1005 /* Fall back to non-DMA */
1006 mcp251x_enable_dma = 0;
1007 }
1008 }
1009
1010 /* Allocate non-DMA buffers */
1011 if (!mcp251x_enable_dma) {
1012 priv->spi_tx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
1013 if (!priv->spi_tx_buf) {
1014 ret = -ENOMEM;
1015 goto error_tx_buf;
1016 }
1017 priv->spi_rx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
ce739b47 1018 if (!priv->spi_rx_buf) {
e0000163
CP		 1019 ret = -ENOMEM;
1020 goto error_rx_buf;
1021 }
1022 }
1023
1024 if (pdata->power_enable)
1025 pdata->power_enable(1);
1026
1027 /* Call out to platform specific setup */
1028 if (pdata->board_specific_setup)
1029 pdata->board_specific_setup(spi);
1030
1031 SET_NETDEV_DEV(net, &spi->dev);
1032
e0000163
CP		 1033 /* Configure the SPI bus */
1034 spi->mode = SPI_MODE_0;
1035 spi->bits_per_word = 8;
1036 spi_setup(spi);
1037
bf66f373 1038 /* Here is OK to not lock the MCP, no one knows about it yet */
e0000163
CP		 1039 if (!mcp251x_hw_probe(spi)) {
1040 dev_info(&spi->dev, "Probe failed\n");
1041 goto error_probe;
1042 }
1043 mcp251x_hw_sleep(spi);
1044
1045 if (pdata->transceiver_enable)
1046 pdata->transceiver_enable(0);
1047
1048 ret = register_candev(net);
1049 if (!ret) {
1050 dev_info(&spi->dev, "probed\n");
1051 return ret;
1052 }
1053error_probe:
1054 if (!mcp251x_enable_dma)
1055 kfree(priv->spi_rx_buf);
1056error_rx_buf:
1057 if (!mcp251x_enable_dma)
1058 kfree(priv->spi_tx_buf);
1059error_tx_buf:
1060 free_candev(net);
1061 if (mcp251x_enable_dma)
1062 dma_free_coherent(&spi->dev, PAGE_SIZE,
1063 priv->spi_tx_buf, priv->spi_tx_dma);
1064error_alloc:
1065 if (pdata->power_enable)
1066 pdata->power_enable(0);
1067 dev_err(&spi->dev, "probe failed\n");
1068error_out:
1069 return ret;
1070}
1071
1072static int __devexit mcp251x_can_remove(struct spi_device *spi)
1073{
1074 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1075 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1076 struct net_device *net = priv->net;
1077
1078 unregister_candev(net);
1079 free_candev(net);
1080
e0000163
CP		 1081 if (mcp251x_enable_dma) {
1082 dma_free_coherent(&spi->dev, PAGE_SIZE,
1083 priv->spi_tx_buf, priv->spi_tx_dma);
1084 } else {
1085 kfree(priv->spi_tx_buf);
1086 kfree(priv->spi_rx_buf);
1087 }
1088
1089 if (pdata->power_enable)
1090 pdata->power_enable(0);
1091
1092 return 0;
1093}
1094
1095#ifdef CONFIG_PM
1096static int mcp251x_can_suspend(struct spi_device *spi, pm_message_t state)
1097{
1098 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1099 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1100 struct net_device *net = priv->net;
1101
bf66f373
CP		 1102 priv->force_quit = 1;
1103 disable_irq(spi->irq);
1104 /*
1105 * Note: at this point neither IST nor workqueues are running.
1106 * open/stop cannot be called anyway so locking is not needed
1107 */
e0000163
CP		 1108 if (netif_running(net)) {
1109 netif_device_detach(net);
1110
1111 mcp251x_hw_sleep(spi);
1112 if (pdata->transceiver_enable)
1113 pdata->transceiver_enable(0);
1114 priv->after_suspend = AFTER_SUSPEND_UP;
1115 } else {
1116 priv->after_suspend = AFTER_SUSPEND_DOWN;
1117 }
1118
1119 if (pdata->power_enable) {
1120 pdata->power_enable(0);
1121 priv->after_suspend |= AFTER_SUSPEND_POWER;
1122 }
1123
1124 return 0;
1125}
1126
1127static int mcp251x_can_resume(struct spi_device *spi)
1128{
1129 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1130 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1131
1132 if (priv->after_suspend & AFTER_SUSPEND_POWER) {
1133 pdata->power_enable(1);
bf66f373 1134 queue_work(priv->wq, &priv->restart_work);
e0000163
CP		 1135 } else {
1136 if (priv->after_suspend & AFTER_SUSPEND_UP) {
1137 if (pdata->transceiver_enable)
1138 pdata->transceiver_enable(1);
bf66f373 1139 queue_work(priv->wq, &priv->restart_work);
e0000163
CP		 1140 } else {
1141 priv->after_suspend = 0;
1142 }
1143 }
bf66f373
CP		 1144 priv->force_quit = 0;
1145 enable_irq(spi->irq);
e0000163
CP		 1146 return 0;
1147}
1148#else
1149#define mcp251x_can_suspend NULL
1150#define mcp251x_can_resume NULL
1151#endif
1152
e446630c
MZ		 1153static struct spi_device_id mcp251x_id_table[] = {
1154 { "mcp251x", 0 /* Use pdata.model */ },
1155 { "mcp2510", CAN_MCP251X_MCP2510 },
1156 { "mcp2515", CAN_MCP251X_MCP2515 },
1157 { },
1158};
1159
1160MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
1161
e0000163
CP		 1162static struct spi_driver mcp251x_can_driver = {
1163 .driver = {
1164 .name = DEVICE_NAME,
1165 .bus = &spi_bus_type,
1166 .owner = THIS_MODULE,
1167 },
1168
e446630c 1169 .id_table = mcp251x_id_table,
e0000163
CP		 1170 .probe = mcp251x_can_probe,
1171 .remove = __devexit_p(mcp251x_can_remove),
1172 .suspend = mcp251x_can_suspend,
1173 .resume = mcp251x_can_resume,
1174};
1175
1176static int __init mcp251x_can_init(void)
1177{
1178 return spi_register_driver(&mcp251x_can_driver);
1179}
1180
1181static void __exit mcp251x_can_exit(void)
1182{
1183 spi_unregister_driver(&mcp251x_can_driver);
1184}
1185
1186module_init(mcp251x_can_init);
1187module_exit(mcp251x_can_exit);
1188
1189MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1190 "Christian Pellegrin <chripell@evolware.org>");
1191MODULE_DESCRIPTION("Microchip 251x CAN driver");
1192MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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