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8199d3a7 CL |
1 | /***************************************************************************** |
2 | * * | |
3 | * File: sge.c * | |
559fb51b SB |
4 | * $Revision: 1.26 $ * |
5 | * $Date: 2005/06/21 18:29:48 $ * | |
8199d3a7 CL |
6 | * Description: * |
7 | * DMA engine. * | |
8 | * part of the Chelsio 10Gb Ethernet Driver. * | |
9 | * * | |
10 | * This program is free software; you can redistribute it and/or modify * | |
11 | * it under the terms of the GNU General Public License, version 2, as * | |
12 | * published by the Free Software Foundation. * | |
13 | * * | |
14 | * You should have received a copy of the GNU General Public License along * | |
15 | * with this program; if not, write to the Free Software Foundation, Inc., * | |
16 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * | |
17 | * * | |
18 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * | |
19 | * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * | |
20 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * | |
21 | * * | |
22 | * http://www.chelsio.com * | |
23 | * * | |
24 | * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * | |
25 | * All rights reserved. * | |
26 | * * | |
27 | * Maintainers: maintainers@chelsio.com * | |
28 | * * | |
29 | * Authors: Dimitrios Michailidis <dm@chelsio.com> * | |
30 | * Tina Yang <tainay@chelsio.com> * | |
31 | * Felix Marti <felix@chelsio.com> * | |
32 | * Scott Bardone <sbardone@chelsio.com> * | |
33 | * Kurt Ottaway <kottaway@chelsio.com> * | |
34 | * Frank DiMambro <frank@chelsio.com> * | |
35 | * * | |
36 | * History: * | |
37 | * * | |
38 | ****************************************************************************/ | |
39 | ||
40 | #include "common.h" | |
41 | ||
8199d3a7 CL |
42 | #include <linux/types.h> |
43 | #include <linux/errno.h> | |
44 | #include <linux/pci.h> | |
f1d3d38a | 45 | #include <linux/ktime.h> |
8199d3a7 CL |
46 | #include <linux/netdevice.h> |
47 | #include <linux/etherdevice.h> | |
48 | #include <linux/if_vlan.h> | |
49 | #include <linux/skbuff.h> | |
50 | #include <linux/init.h> | |
51 | #include <linux/mm.h> | |
f1d3d38a | 52 | #include <linux/tcp.h> |
8199d3a7 CL |
53 | #include <linux/ip.h> |
54 | #include <linux/in.h> | |
55 | #include <linux/if_arp.h> | |
56 | ||
57 | #include "cpl5_cmd.h" | |
58 | #include "sge.h" | |
59 | #include "regs.h" | |
60 | #include "espi.h" | |
61 | ||
f1d3d38a SH |
62 | /* This belongs in if_ether.h */ |
63 | #define ETH_P_CPL5 0xf | |
8199d3a7 CL |
64 | |
65 | #define SGE_CMDQ_N 2 | |
66 | #define SGE_FREELQ_N 2 | |
559fb51b | 67 | #define SGE_CMDQ0_E_N 1024 |
8199d3a7 CL |
68 | #define SGE_CMDQ1_E_N 128 |
69 | #define SGE_FREEL_SIZE 4096 | |
70 | #define SGE_JUMBO_FREEL_SIZE 512 | |
71 | #define SGE_FREEL_REFILL_THRESH 16 | |
72 | #define SGE_RESPQ_E_N 1024 | |
559fb51b | 73 | #define SGE_INTRTIMER_NRES 1000 |
8199d3a7 | 74 | #define SGE_RX_SM_BUF_SIZE 1536 |
f1d3d38a | 75 | #define SGE_TX_DESC_MAX_PLEN 16384 |
8199d3a7 | 76 | |
559fb51b SB |
77 | #define SGE_RESPQ_REPLENISH_THRES (SGE_RESPQ_E_N / 4) |
78 | ||
79 | /* | |
80 | * Period of the TX buffer reclaim timer. This timer does not need to run | |
81 | * frequently as TX buffers are usually reclaimed by new TX packets. | |
82 | */ | |
83 | #define TX_RECLAIM_PERIOD (HZ / 4) | |
8199d3a7 | 84 | |
559fb51b SB |
85 | #define M_CMD_LEN 0x7fffffff |
86 | #define V_CMD_LEN(v) (v) | |
87 | #define G_CMD_LEN(v) ((v) & M_CMD_LEN) | |
88 | #define V_CMD_GEN1(v) ((v) << 31) | |
89 | #define V_CMD_GEN2(v) (v) | |
90 | #define F_CMD_DATAVALID (1 << 1) | |
91 | #define F_CMD_SOP (1 << 2) | |
92 | #define V_CMD_EOP(v) ((v) << 3) | |
93 | ||
8199d3a7 | 94 | /* |
559fb51b | 95 | * Command queue, receive buffer list, and response queue descriptors. |
8199d3a7 CL |
96 | */ |
97 | #if defined(__BIG_ENDIAN_BITFIELD) | |
98 | struct cmdQ_e { | |
559fb51b SB |
99 | u32 addr_lo; |
100 | u32 len_gen; | |
101 | u32 flags; | |
102 | u32 addr_hi; | |
8199d3a7 CL |
103 | }; |
104 | ||
105 | struct freelQ_e { | |
559fb51b SB |
106 | u32 addr_lo; |
107 | u32 len_gen; | |
108 | u32 gen2; | |
109 | u32 addr_hi; | |
8199d3a7 CL |
110 | }; |
111 | ||
112 | struct respQ_e { | |
113 | u32 Qsleeping : 4; | |
114 | u32 Cmdq1CreditReturn : 5; | |
115 | u32 Cmdq1DmaComplete : 5; | |
116 | u32 Cmdq0CreditReturn : 5; | |
117 | u32 Cmdq0DmaComplete : 5; | |
118 | u32 FreelistQid : 2; | |
119 | u32 CreditValid : 1; | |
120 | u32 DataValid : 1; | |
121 | u32 Offload : 1; | |
122 | u32 Eop : 1; | |
123 | u32 Sop : 1; | |
124 | u32 GenerationBit : 1; | |
125 | u32 BufferLength; | |
126 | }; | |
8199d3a7 CL |
127 | #elif defined(__LITTLE_ENDIAN_BITFIELD) |
128 | struct cmdQ_e { | |
559fb51b SB |
129 | u32 len_gen; |
130 | u32 addr_lo; | |
131 | u32 addr_hi; | |
132 | u32 flags; | |
8199d3a7 CL |
133 | }; |
134 | ||
135 | struct freelQ_e { | |
559fb51b SB |
136 | u32 len_gen; |
137 | u32 addr_lo; | |
138 | u32 addr_hi; | |
139 | u32 gen2; | |
8199d3a7 CL |
140 | }; |
141 | ||
142 | struct respQ_e { | |
143 | u32 BufferLength; | |
144 | u32 GenerationBit : 1; | |
145 | u32 Sop : 1; | |
146 | u32 Eop : 1; | |
147 | u32 Offload : 1; | |
148 | u32 DataValid : 1; | |
149 | u32 CreditValid : 1; | |
150 | u32 FreelistQid : 2; | |
151 | u32 Cmdq0DmaComplete : 5; | |
152 | u32 Cmdq0CreditReturn : 5; | |
153 | u32 Cmdq1DmaComplete : 5; | |
154 | u32 Cmdq1CreditReturn : 5; | |
155 | u32 Qsleeping : 4; | |
156 | } ; | |
157 | #endif | |
158 | ||
159 | /* | |
160 | * SW Context Command and Freelist Queue Descriptors | |
161 | */ | |
162 | struct cmdQ_ce { | |
163 | struct sk_buff *skb; | |
164 | DECLARE_PCI_UNMAP_ADDR(dma_addr); | |
165 | DECLARE_PCI_UNMAP_LEN(dma_len); | |
8199d3a7 CL |
166 | }; |
167 | ||
168 | struct freelQ_ce { | |
169 | struct sk_buff *skb; | |
170 | DECLARE_PCI_UNMAP_ADDR(dma_addr); | |
171 | DECLARE_PCI_UNMAP_LEN(dma_len); | |
172 | }; | |
173 | ||
174 | /* | |
559fb51b | 175 | * SW command, freelist and response rings |
8199d3a7 CL |
176 | */ |
177 | struct cmdQ { | |
559fb51b SB |
178 | unsigned long status; /* HW DMA fetch status */ |
179 | unsigned int in_use; /* # of in-use command descriptors */ | |
180 | unsigned int size; /* # of descriptors */ | |
f1d3d38a SH |
181 | unsigned int processed; /* total # of descs HW has processed */ |
182 | unsigned int cleaned; /* total # of descs SW has reclaimed */ | |
183 | unsigned int stop_thres; /* SW TX queue suspend threshold */ | |
559fb51b SB |
184 | u16 pidx; /* producer index (SW) */ |
185 | u16 cidx; /* consumer index (HW) */ | |
186 | u8 genbit; /* current generation (=valid) bit */ | |
f1d3d38a | 187 | u8 sop; /* is next entry start of packet? */ |
559fb51b SB |
188 | struct cmdQ_e *entries; /* HW command descriptor Q */ |
189 | struct cmdQ_ce *centries; /* SW command context descriptor Q */ | |
559fb51b | 190 | dma_addr_t dma_addr; /* DMA addr HW command descriptor Q */ |
356bd146 | 191 | spinlock_t lock; /* Lock to protect cmdQ enqueuing */ |
8199d3a7 CL |
192 | }; |
193 | ||
194 | struct freelQ { | |
559fb51b SB |
195 | unsigned int credits; /* # of available RX buffers */ |
196 | unsigned int size; /* free list capacity */ | |
197 | u16 pidx; /* producer index (SW) */ | |
198 | u16 cidx; /* consumer index (HW) */ | |
8199d3a7 | 199 | u16 rx_buffer_size; /* Buffer size on this free list */ |
f1d3d38a SH |
200 | u16 dma_offset; /* DMA offset to align IP headers */ |
201 | u16 recycleq_idx; /* skb recycle q to use */ | |
559fb51b SB |
202 | u8 genbit; /* current generation (=valid) bit */ |
203 | struct freelQ_e *entries; /* HW freelist descriptor Q */ | |
204 | struct freelQ_ce *centries; /* SW freelist context descriptor Q */ | |
205 | dma_addr_t dma_addr; /* DMA addr HW freelist descriptor Q */ | |
8199d3a7 CL |
206 | }; |
207 | ||
208 | struct respQ { | |
559fb51b SB |
209 | unsigned int credits; /* credits to be returned to SGE */ |
210 | unsigned int size; /* # of response Q descriptors */ | |
211 | u16 cidx; /* consumer index (SW) */ | |
212 | u8 genbit; /* current generation(=valid) bit */ | |
8199d3a7 | 213 | struct respQ_e *entries; /* HW response descriptor Q */ |
559fb51b SB |
214 | dma_addr_t dma_addr; /* DMA addr HW response descriptor Q */ |
215 | }; | |
216 | ||
217 | /* Bit flags for cmdQ.status */ | |
218 | enum { | |
219 | CMDQ_STAT_RUNNING = 1, /* fetch engine is running */ | |
220 | CMDQ_STAT_LAST_PKT_DB = 2 /* last packet rung the doorbell */ | |
8199d3a7 CL |
221 | }; |
222 | ||
f1d3d38a SH |
223 | /* T204 TX SW scheduler */ |
224 | ||
225 | /* Per T204 TX port */ | |
226 | struct sched_port { | |
227 | unsigned int avail; /* available bits - quota */ | |
228 | unsigned int drain_bits_per_1024ns; /* drain rate */ | |
229 | unsigned int speed; /* drain rate, mbps */ | |
230 | unsigned int mtu; /* mtu size */ | |
231 | struct sk_buff_head skbq; /* pending skbs */ | |
232 | }; | |
233 | ||
234 | /* Per T204 device */ | |
235 | struct sched { | |
236 | ktime_t last_updated; /* last time quotas were computed */ | |
356bd146 FR |
237 | unsigned int max_avail; /* max bits to be sent to any port */ |
238 | unsigned int port; /* port index (round robin ports) */ | |
239 | unsigned int num; /* num skbs in per port queues */ | |
f1d3d38a SH |
240 | struct sched_port p[MAX_NPORTS]; |
241 | struct tasklet_struct sched_tsk;/* tasklet used to run scheduler */ | |
242 | }; | |
243 | static void restart_sched(unsigned long); | |
244 | ||
245 | ||
8199d3a7 CL |
246 | /* |
247 | * Main SGE data structure | |
248 | * | |
249 | * Interrupts are handled by a single CPU and it is likely that on a MP system | |
250 | * the application is migrated to another CPU. In that scenario, we try to | |
251 | * seperate the RX(in irq context) and TX state in order to decrease memory | |
252 | * contention. | |
253 | */ | |
254 | struct sge { | |
356bd146 | 255 | struct adapter *adapter; /* adapter backpointer */ |
559fb51b | 256 | struct net_device *netdev; /* netdevice backpointer */ |
356bd146 FR |
257 | struct freelQ freelQ[SGE_FREELQ_N]; /* buffer free lists */ |
258 | struct respQ respQ; /* response Q */ | |
559fb51b | 259 | unsigned long stopped_tx_queues; /* bitmap of suspended Tx queues */ |
8199d3a7 CL |
260 | unsigned int rx_pkt_pad; /* RX padding for L2 packets */ |
261 | unsigned int jumbo_fl; /* jumbo freelist Q index */ | |
559fb51b | 262 | unsigned int intrtimer_nres; /* no-resource interrupt timer */ |
f1d3d38a | 263 | unsigned int fixed_intrtimer;/* non-adaptive interrupt timer */ |
559fb51b SB |
264 | struct timer_list tx_reclaim_timer; /* reclaims TX buffers */ |
265 | struct timer_list espibug_timer; | |
f1d3d38a SH |
266 | unsigned long espibug_timeout; |
267 | struct sk_buff *espibug_skb[MAX_NPORTS]; | |
559fb51b SB |
268 | u32 sge_control; /* shadow value of sge control reg */ |
269 | struct sge_intr_counts stats; | |
56f643c2 | 270 | struct sge_port_stats *port_stats[MAX_NPORTS]; |
f1d3d38a | 271 | struct sched *tx_sched; |
559fb51b | 272 | struct cmdQ cmdQ[SGE_CMDQ_N] ____cacheline_aligned_in_smp; |
8199d3a7 CL |
273 | }; |
274 | ||
f1d3d38a SH |
275 | /* |
276 | * stop tasklet and free all pending skb's | |
277 | */ | |
278 | static void tx_sched_stop(struct sge *sge) | |
279 | { | |
280 | struct sched *s = sge->tx_sched; | |
281 | int i; | |
282 | ||
283 | tasklet_kill(&s->sched_tsk); | |
284 | ||
285 | for (i = 0; i < MAX_NPORTS; i++) | |
286 | __skb_queue_purge(&s->p[s->port].skbq); | |
287 | } | |
288 | ||
289 | /* | |
290 | * t1_sched_update_parms() is called when the MTU or link speed changes. It | |
291 | * re-computes scheduler parameters to scope with the change. | |
292 | */ | |
293 | unsigned int t1_sched_update_parms(struct sge *sge, unsigned int port, | |
294 | unsigned int mtu, unsigned int speed) | |
295 | { | |
296 | struct sched *s = sge->tx_sched; | |
297 | struct sched_port *p = &s->p[port]; | |
298 | unsigned int max_avail_segs; | |
299 | ||
300 | pr_debug("t1_sched_update_params mtu=%d speed=%d\n", mtu, speed); | |
301 | if (speed) | |
302 | p->speed = speed; | |
303 | if (mtu) | |
304 | p->mtu = mtu; | |
305 | ||
306 | if (speed || mtu) { | |
307 | unsigned long long drain = 1024ULL * p->speed * (p->mtu - 40); | |
308 | do_div(drain, (p->mtu + 50) * 1000); | |
309 | p->drain_bits_per_1024ns = (unsigned int) drain; | |
310 | ||
311 | if (p->speed < 1000) | |
312 | p->drain_bits_per_1024ns = | |
313 | 90 * p->drain_bits_per_1024ns / 100; | |
314 | } | |
315 | ||
316 | if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204) { | |
317 | p->drain_bits_per_1024ns -= 16; | |
318 | s->max_avail = max(4096U, p->mtu + 16 + 14 + 4); | |
319 | max_avail_segs = max(1U, 4096 / (p->mtu - 40)); | |
320 | } else { | |
321 | s->max_avail = 16384; | |
322 | max_avail_segs = max(1U, 9000 / (p->mtu - 40)); | |
323 | } | |
324 | ||
325 | pr_debug("t1_sched_update_parms: mtu %u speed %u max_avail %u " | |
326 | "max_avail_segs %u drain_bits_per_1024ns %u\n", p->mtu, | |
327 | p->speed, s->max_avail, max_avail_segs, | |
328 | p->drain_bits_per_1024ns); | |
329 | ||
330 | return max_avail_segs * (p->mtu - 40); | |
331 | } | |
332 | ||
333 | /* | |
334 | * t1_sched_max_avail_bytes() tells the scheduler the maximum amount of | |
335 | * data that can be pushed per port. | |
336 | */ | |
337 | void t1_sched_set_max_avail_bytes(struct sge *sge, unsigned int val) | |
338 | { | |
339 | struct sched *s = sge->tx_sched; | |
340 | unsigned int i; | |
341 | ||
342 | s->max_avail = val; | |
343 | for (i = 0; i < MAX_NPORTS; i++) | |
344 | t1_sched_update_parms(sge, i, 0, 0); | |
345 | } | |
346 | ||
347 | /* | |
348 | * t1_sched_set_drain_bits_per_us() tells the scheduler at which rate a port | |
349 | * is draining. | |
350 | */ | |
351 | void t1_sched_set_drain_bits_per_us(struct sge *sge, unsigned int port, | |
352 | unsigned int val) | |
353 | { | |
354 | struct sched *s = sge->tx_sched; | |
355 | struct sched_port *p = &s->p[port]; | |
356 | p->drain_bits_per_1024ns = val * 1024 / 1000; | |
357 | t1_sched_update_parms(sge, port, 0, 0); | |
358 | } | |
359 | ||
360 | ||
361 | /* | |
362 | * get_clock() implements a ns clock (see ktime_get) | |
363 | */ | |
364 | static inline ktime_t get_clock(void) | |
365 | { | |
366 | struct timespec ts; | |
367 | ||
368 | ktime_get_ts(&ts); | |
369 | return timespec_to_ktime(ts); | |
370 | } | |
371 | ||
372 | /* | |
373 | * tx_sched_init() allocates resources and does basic initialization. | |
374 | */ | |
375 | static int tx_sched_init(struct sge *sge) | |
376 | { | |
377 | struct sched *s; | |
378 | int i; | |
379 | ||
380 | s = kzalloc(sizeof (struct sched), GFP_KERNEL); | |
381 | if (!s) | |
382 | return -ENOMEM; | |
383 | ||
384 | pr_debug("tx_sched_init\n"); | |
385 | tasklet_init(&s->sched_tsk, restart_sched, (unsigned long) sge); | |
386 | sge->tx_sched = s; | |
387 | ||
388 | for (i = 0; i < MAX_NPORTS; i++) { | |
389 | skb_queue_head_init(&s->p[i].skbq); | |
390 | t1_sched_update_parms(sge, i, 1500, 1000); | |
391 | } | |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
396 | /* | |
397 | * sched_update_avail() computes the delta since the last time it was called | |
398 | * and updates the per port quota (number of bits that can be sent to the any | |
399 | * port). | |
400 | */ | |
401 | static inline int sched_update_avail(struct sge *sge) | |
402 | { | |
403 | struct sched *s = sge->tx_sched; | |
404 | ktime_t now = get_clock(); | |
405 | unsigned int i; | |
406 | long long delta_time_ns; | |
407 | ||
408 | delta_time_ns = ktime_to_ns(ktime_sub(now, s->last_updated)); | |
409 | ||
410 | pr_debug("sched_update_avail delta=%lld\n", delta_time_ns); | |
411 | if (delta_time_ns < 15000) | |
412 | return 0; | |
413 | ||
414 | for (i = 0; i < MAX_NPORTS; i++) { | |
415 | struct sched_port *p = &s->p[i]; | |
416 | unsigned int delta_avail; | |
417 | ||
418 | delta_avail = (p->drain_bits_per_1024ns * delta_time_ns) >> 13; | |
419 | p->avail = min(p->avail + delta_avail, s->max_avail); | |
420 | } | |
421 | ||
422 | s->last_updated = now; | |
423 | ||
424 | return 1; | |
425 | } | |
426 | ||
427 | /* | |
428 | * sched_skb() is called from two different places. In the tx path, any | |
429 | * packet generating load on an output port will call sched_skb() | |
430 | * (skb != NULL). In addition, sched_skb() is called from the irq/soft irq | |
431 | * context (skb == NULL). | |
432 | * The scheduler only returns a skb (which will then be sent) if the | |
433 | * length of the skb is <= the current quota of the output port. | |
434 | */ | |
435 | static struct sk_buff *sched_skb(struct sge *sge, struct sk_buff *skb, | |
436 | unsigned int credits) | |
437 | { | |
438 | struct sched *s = sge->tx_sched; | |
439 | struct sk_buff_head *skbq; | |
440 | unsigned int i, len, update = 1; | |
441 | ||
442 | pr_debug("sched_skb %p\n", skb); | |
443 | if (!skb) { | |
444 | if (!s->num) | |
445 | return NULL; | |
446 | } else { | |
447 | skbq = &s->p[skb->dev->if_port].skbq; | |
448 | __skb_queue_tail(skbq, skb); | |
449 | s->num++; | |
450 | skb = NULL; | |
451 | } | |
452 | ||
453 | if (credits < MAX_SKB_FRAGS + 1) | |
454 | goto out; | |
455 | ||
356bd146 | 456 | again: |
f1d3d38a SH |
457 | for (i = 0; i < MAX_NPORTS; i++) { |
458 | s->port = ++s->port & (MAX_NPORTS - 1); | |
459 | skbq = &s->p[s->port].skbq; | |
460 | ||
461 | skb = skb_peek(skbq); | |
462 | ||
463 | if (!skb) | |
464 | continue; | |
465 | ||
466 | len = skb->len; | |
467 | if (len <= s->p[s->port].avail) { | |
468 | s->p[s->port].avail -= len; | |
469 | s->num--; | |
470 | __skb_unlink(skb, skbq); | |
471 | goto out; | |
472 | } | |
473 | skb = NULL; | |
474 | } | |
475 | ||
476 | if (update-- && sched_update_avail(sge)) | |
477 | goto again; | |
478 | ||
356bd146 FR |
479 | out: |
480 | /* If there are more pending skbs, we use the hardware to schedule us | |
f1d3d38a SH |
481 | * again. |
482 | */ | |
483 | if (s->num && !skb) { | |
484 | struct cmdQ *q = &sge->cmdQ[0]; | |
485 | clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
486 | if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) { | |
487 | set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
488 | writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL); | |
489 | } | |
490 | } | |
491 | pr_debug("sched_skb ret %p\n", skb); | |
492 | ||
493 | return skb; | |
494 | } | |
495 | ||
8199d3a7 CL |
496 | /* |
497 | * PIO to indicate that memory mapped Q contains valid descriptor(s). | |
498 | */ | |
559fb51b | 499 | static inline void doorbell_pio(struct adapter *adapter, u32 val) |
8199d3a7 CL |
500 | { |
501 | wmb(); | |
559fb51b | 502 | writel(val, adapter->regs + A_SG_DOORBELL); |
8199d3a7 CL |
503 | } |
504 | ||
505 | /* | |
506 | * Frees all RX buffers on the freelist Q. The caller must make sure that | |
507 | * the SGE is turned off before calling this function. | |
508 | */ | |
559fb51b | 509 | static void free_freelQ_buffers(struct pci_dev *pdev, struct freelQ *q) |
8199d3a7 | 510 | { |
559fb51b | 511 | unsigned int cidx = q->cidx; |
8199d3a7 | 512 | |
559fb51b SB |
513 | while (q->credits--) { |
514 | struct freelQ_ce *ce = &q->centries[cidx]; | |
8199d3a7 CL |
515 | |
516 | pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr), | |
517 | pci_unmap_len(ce, dma_len), | |
518 | PCI_DMA_FROMDEVICE); | |
519 | dev_kfree_skb(ce->skb); | |
520 | ce->skb = NULL; | |
559fb51b | 521 | if (++cidx == q->size) |
8199d3a7 CL |
522 | cidx = 0; |
523 | } | |
524 | } | |
525 | ||
526 | /* | |
527 | * Free RX free list and response queue resources. | |
528 | */ | |
529 | static void free_rx_resources(struct sge *sge) | |
530 | { | |
531 | struct pci_dev *pdev = sge->adapter->pdev; | |
532 | unsigned int size, i; | |
533 | ||
534 | if (sge->respQ.entries) { | |
559fb51b | 535 | size = sizeof(struct respQ_e) * sge->respQ.size; |
8199d3a7 CL |
536 | pci_free_consistent(pdev, size, sge->respQ.entries, |
537 | sge->respQ.dma_addr); | |
538 | } | |
539 | ||
540 | for (i = 0; i < SGE_FREELQ_N; i++) { | |
559fb51b | 541 | struct freelQ *q = &sge->freelQ[i]; |
8199d3a7 | 542 | |
559fb51b SB |
543 | if (q->centries) { |
544 | free_freelQ_buffers(pdev, q); | |
545 | kfree(q->centries); | |
8199d3a7 | 546 | } |
559fb51b SB |
547 | if (q->entries) { |
548 | size = sizeof(struct freelQ_e) * q->size; | |
549 | pci_free_consistent(pdev, size, q->entries, | |
550 | q->dma_addr); | |
8199d3a7 CL |
551 | } |
552 | } | |
553 | } | |
554 | ||
555 | /* | |
556 | * Allocates basic RX resources, consisting of memory mapped freelist Qs and a | |
559fb51b | 557 | * response queue. |
8199d3a7 CL |
558 | */ |
559 | static int alloc_rx_resources(struct sge *sge, struct sge_params *p) | |
560 | { | |
561 | struct pci_dev *pdev = sge->adapter->pdev; | |
562 | unsigned int size, i; | |
563 | ||
564 | for (i = 0; i < SGE_FREELQ_N; i++) { | |
559fb51b SB |
565 | struct freelQ *q = &sge->freelQ[i]; |
566 | ||
567 | q->genbit = 1; | |
568 | q->size = p->freelQ_size[i]; | |
569 | q->dma_offset = sge->rx_pkt_pad ? 0 : NET_IP_ALIGN; | |
570 | size = sizeof(struct freelQ_e) * q->size; | |
3e0f75be | 571 | q->entries = pci_alloc_consistent(pdev, size, &q->dma_addr); |
559fb51b | 572 | if (!q->entries) |
8199d3a7 | 573 | goto err_no_mem; |
3e0f75be | 574 | |
559fb51b | 575 | size = sizeof(struct freelQ_ce) * q->size; |
cbee9f91 | 576 | q->centries = kzalloc(size, GFP_KERNEL); |
559fb51b | 577 | if (!q->centries) |
8199d3a7 CL |
578 | goto err_no_mem; |
579 | } | |
580 | ||
581 | /* | |
582 | * Calculate the buffer sizes for the two free lists. FL0 accommodates | |
583 | * regular sized Ethernet frames, FL1 is sized not to exceed 16K, | |
584 | * including all the sk_buff overhead. | |
585 | * | |
586 | * Note: For T2 FL0 and FL1 are reversed. | |
587 | */ | |
588 | sge->freelQ[!sge->jumbo_fl].rx_buffer_size = SGE_RX_SM_BUF_SIZE + | |
589 | sizeof(struct cpl_rx_data) + | |
590 | sge->freelQ[!sge->jumbo_fl].dma_offset; | |
f1d3d38a SH |
591 | |
592 | size = (16 * 1024) - | |
593 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
594 | ||
595 | sge->freelQ[sge->jumbo_fl].rx_buffer_size = size; | |
8199d3a7 | 596 | |
559fb51b SB |
597 | /* |
598 | * Setup which skb recycle Q should be used when recycling buffers from | |
599 | * each free list. | |
600 | */ | |
601 | sge->freelQ[!sge->jumbo_fl].recycleq_idx = 0; | |
602 | sge->freelQ[sge->jumbo_fl].recycleq_idx = 1; | |
603 | ||
8199d3a7 | 604 | sge->respQ.genbit = 1; |
559fb51b SB |
605 | sge->respQ.size = SGE_RESPQ_E_N; |
606 | sge->respQ.credits = 0; | |
607 | size = sizeof(struct respQ_e) * sge->respQ.size; | |
3e0f75be | 608 | sge->respQ.entries = |
8199d3a7 CL |
609 | pci_alloc_consistent(pdev, size, &sge->respQ.dma_addr); |
610 | if (!sge->respQ.entries) | |
611 | goto err_no_mem; | |
8199d3a7 CL |
612 | return 0; |
613 | ||
614 | err_no_mem: | |
615 | free_rx_resources(sge); | |
616 | return -ENOMEM; | |
617 | } | |
618 | ||
619 | /* | |
559fb51b | 620 | * Reclaims n TX descriptors and frees the buffers associated with them. |
8199d3a7 | 621 | */ |
559fb51b | 622 | static void free_cmdQ_buffers(struct sge *sge, struct cmdQ *q, unsigned int n) |
8199d3a7 | 623 | { |
559fb51b | 624 | struct cmdQ_ce *ce; |
8199d3a7 | 625 | struct pci_dev *pdev = sge->adapter->pdev; |
559fb51b | 626 | unsigned int cidx = q->cidx; |
8199d3a7 | 627 | |
559fb51b SB |
628 | q->in_use -= n; |
629 | ce = &q->centries[cidx]; | |
630 | while (n--) { | |
3e0f75be FR |
631 | if (likely(pci_unmap_len(ce, dma_len))) { |
632 | pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr), | |
633 | pci_unmap_len(ce, dma_len), | |
634 | PCI_DMA_TODEVICE); | |
635 | if (q->sop) | |
f1d3d38a | 636 | q->sop = 0; |
f1d3d38a | 637 | } |
559fb51b | 638 | if (ce->skb) { |
f1d3d38a | 639 | dev_kfree_skb_any(ce->skb); |
559fb51b SB |
640 | q->sop = 1; |
641 | } | |
8199d3a7 | 642 | ce++; |
559fb51b | 643 | if (++cidx == q->size) { |
8199d3a7 | 644 | cidx = 0; |
559fb51b | 645 | ce = q->centries; |
8199d3a7 CL |
646 | } |
647 | } | |
559fb51b | 648 | q->cidx = cidx; |
8199d3a7 CL |
649 | } |
650 | ||
651 | /* | |
652 | * Free TX resources. | |
653 | * | |
654 | * Assumes that SGE is stopped and all interrupts are disabled. | |
655 | */ | |
656 | static void free_tx_resources(struct sge *sge) | |
657 | { | |
658 | struct pci_dev *pdev = sge->adapter->pdev; | |
659 | unsigned int size, i; | |
660 | ||
661 | for (i = 0; i < SGE_CMDQ_N; i++) { | |
559fb51b | 662 | struct cmdQ *q = &sge->cmdQ[i]; |
8199d3a7 | 663 | |
559fb51b SB |
664 | if (q->centries) { |
665 | if (q->in_use) | |
666 | free_cmdQ_buffers(sge, q, q->in_use); | |
667 | kfree(q->centries); | |
8199d3a7 | 668 | } |
559fb51b SB |
669 | if (q->entries) { |
670 | size = sizeof(struct cmdQ_e) * q->size; | |
671 | pci_free_consistent(pdev, size, q->entries, | |
672 | q->dma_addr); | |
8199d3a7 CL |
673 | } |
674 | } | |
675 | } | |
676 | ||
677 | /* | |
678 | * Allocates basic TX resources, consisting of memory mapped command Qs. | |
679 | */ | |
680 | static int alloc_tx_resources(struct sge *sge, struct sge_params *p) | |
681 | { | |
682 | struct pci_dev *pdev = sge->adapter->pdev; | |
683 | unsigned int size, i; | |
684 | ||
685 | for (i = 0; i < SGE_CMDQ_N; i++) { | |
559fb51b SB |
686 | struct cmdQ *q = &sge->cmdQ[i]; |
687 | ||
688 | q->genbit = 1; | |
689 | q->sop = 1; | |
690 | q->size = p->cmdQ_size[i]; | |
691 | q->in_use = 0; | |
692 | q->status = 0; | |
693 | q->processed = q->cleaned = 0; | |
694 | q->stop_thres = 0; | |
695 | spin_lock_init(&q->lock); | |
696 | size = sizeof(struct cmdQ_e) * q->size; | |
3e0f75be | 697 | q->entries = pci_alloc_consistent(pdev, size, &q->dma_addr); |
559fb51b | 698 | if (!q->entries) |
8199d3a7 | 699 | goto err_no_mem; |
3e0f75be | 700 | |
559fb51b | 701 | size = sizeof(struct cmdQ_ce) * q->size; |
cbee9f91 | 702 | q->centries = kzalloc(size, GFP_KERNEL); |
559fb51b | 703 | if (!q->centries) |
8199d3a7 CL |
704 | goto err_no_mem; |
705 | } | |
706 | ||
559fb51b SB |
707 | /* |
708 | * CommandQ 0 handles Ethernet and TOE packets, while queue 1 is TOE | |
709 | * only. For queue 0 set the stop threshold so we can handle one more | |
710 | * packet from each port, plus reserve an additional 24 entries for | |
711 | * Ethernet packets only. Queue 1 never suspends nor do we reserve | |
712 | * space for Ethernet packets. | |
713 | */ | |
714 | sge->cmdQ[0].stop_thres = sge->adapter->params.nports * | |
715 | (MAX_SKB_FRAGS + 1); | |
8199d3a7 CL |
716 | return 0; |
717 | ||
718 | err_no_mem: | |
719 | free_tx_resources(sge); | |
720 | return -ENOMEM; | |
721 | } | |
722 | ||
723 | static inline void setup_ring_params(struct adapter *adapter, u64 addr, | |
724 | u32 size, int base_reg_lo, | |
725 | int base_reg_hi, int size_reg) | |
726 | { | |
559fb51b SB |
727 | writel((u32)addr, adapter->regs + base_reg_lo); |
728 | writel(addr >> 32, adapter->regs + base_reg_hi); | |
729 | writel(size, adapter->regs + size_reg); | |
8199d3a7 CL |
730 | } |
731 | ||
732 | /* | |
733 | * Enable/disable VLAN acceleration. | |
734 | */ | |
735 | void t1_set_vlan_accel(struct adapter *adapter, int on_off) | |
736 | { | |
737 | struct sge *sge = adapter->sge; | |
738 | ||
739 | sge->sge_control &= ~F_VLAN_XTRACT; | |
740 | if (on_off) | |
741 | sge->sge_control |= F_VLAN_XTRACT; | |
742 | if (adapter->open_device_map) { | |
559fb51b | 743 | writel(sge->sge_control, adapter->regs + A_SG_CONTROL); |
f1d3d38a | 744 | readl(adapter->regs + A_SG_CONTROL); /* flush */ |
8199d3a7 CL |
745 | } |
746 | } | |
747 | ||
8199d3a7 CL |
748 | /* |
749 | * Programs the various SGE registers. However, the engine is not yet enabled, | |
750 | * but sge->sge_control is setup and ready to go. | |
751 | */ | |
752 | static void configure_sge(struct sge *sge, struct sge_params *p) | |
753 | { | |
754 | struct adapter *ap = sge->adapter; | |
356bd146 | 755 | |
559fb51b SB |
756 | writel(0, ap->regs + A_SG_CONTROL); |
757 | setup_ring_params(ap, sge->cmdQ[0].dma_addr, sge->cmdQ[0].size, | |
8199d3a7 | 758 | A_SG_CMD0BASELWR, A_SG_CMD0BASEUPR, A_SG_CMD0SIZE); |
559fb51b | 759 | setup_ring_params(ap, sge->cmdQ[1].dma_addr, sge->cmdQ[1].size, |
8199d3a7 CL |
760 | A_SG_CMD1BASELWR, A_SG_CMD1BASEUPR, A_SG_CMD1SIZE); |
761 | setup_ring_params(ap, sge->freelQ[0].dma_addr, | |
559fb51b | 762 | sge->freelQ[0].size, A_SG_FL0BASELWR, |
8199d3a7 CL |
763 | A_SG_FL0BASEUPR, A_SG_FL0SIZE); |
764 | setup_ring_params(ap, sge->freelQ[1].dma_addr, | |
559fb51b | 765 | sge->freelQ[1].size, A_SG_FL1BASELWR, |
8199d3a7 CL |
766 | A_SG_FL1BASEUPR, A_SG_FL1SIZE); |
767 | ||
768 | /* The threshold comparison uses <. */ | |
559fb51b | 769 | writel(SGE_RX_SM_BUF_SIZE + 1, ap->regs + A_SG_FLTHRESHOLD); |
8199d3a7 | 770 | |
559fb51b SB |
771 | setup_ring_params(ap, sge->respQ.dma_addr, sge->respQ.size, |
772 | A_SG_RSPBASELWR, A_SG_RSPBASEUPR, A_SG_RSPSIZE); | |
773 | writel((u32)sge->respQ.size - 1, ap->regs + A_SG_RSPQUEUECREDIT); | |
8199d3a7 CL |
774 | |
775 | sge->sge_control = F_CMDQ0_ENABLE | F_CMDQ1_ENABLE | F_FL0_ENABLE | | |
776 | F_FL1_ENABLE | F_CPL_ENABLE | F_RESPONSE_QUEUE_ENABLE | | |
777 | V_CMDQ_PRIORITY(2) | F_DISABLE_CMDQ1_GTS | F_ISCSI_COALESCE | | |
778 | V_RX_PKT_OFFSET(sge->rx_pkt_pad); | |
779 | ||
780 | #if defined(__BIG_ENDIAN_BITFIELD) | |
781 | sge->sge_control |= F_ENABLE_BIG_ENDIAN; | |
782 | #endif | |
783 | ||
559fb51b SB |
784 | /* Initialize no-resource timer */ |
785 | sge->intrtimer_nres = SGE_INTRTIMER_NRES * core_ticks_per_usec(ap); | |
786 | ||
787 | t1_sge_set_coalesce_params(sge, p); | |
8199d3a7 CL |
788 | } |
789 | ||
790 | /* | |
791 | * Return the payload capacity of the jumbo free-list buffers. | |
792 | */ | |
793 | static inline unsigned int jumbo_payload_capacity(const struct sge *sge) | |
794 | { | |
795 | return sge->freelQ[sge->jumbo_fl].rx_buffer_size - | |
559fb51b SB |
796 | sge->freelQ[sge->jumbo_fl].dma_offset - |
797 | sizeof(struct cpl_rx_data); | |
8199d3a7 CL |
798 | } |
799 | ||
800 | /* | |
801 | * Frees all SGE related resources and the sge structure itself | |
802 | */ | |
803 | void t1_sge_destroy(struct sge *sge) | |
804 | { | |
56f643c2 SH |
805 | int i; |
806 | ||
807 | for_each_port(sge->adapter, i) | |
808 | free_percpu(sge->port_stats[i]); | |
809 | ||
f1d3d38a | 810 | kfree(sge->tx_sched); |
8199d3a7 CL |
811 | free_tx_resources(sge); |
812 | free_rx_resources(sge); | |
813 | kfree(sge); | |
814 | } | |
815 | ||
816 | /* | |
817 | * Allocates new RX buffers on the freelist Q (and tracks them on the freelist | |
818 | * context Q) until the Q is full or alloc_skb fails. | |
819 | * | |
820 | * It is possible that the generation bits already match, indicating that the | |
821 | * buffer is already valid and nothing needs to be done. This happens when we | |
822 | * copied a received buffer into a new sk_buff during the interrupt processing. | |
823 | * | |
824 | * If the SGE doesn't automatically align packets properly (!sge->rx_pkt_pad), | |
825 | * we specify a RX_OFFSET in order to make sure that the IP header is 4B | |
826 | * aligned. | |
827 | */ | |
559fb51b | 828 | static void refill_free_list(struct sge *sge, struct freelQ *q) |
8199d3a7 CL |
829 | { |
830 | struct pci_dev *pdev = sge->adapter->pdev; | |
559fb51b SB |
831 | struct freelQ_ce *ce = &q->centries[q->pidx]; |
832 | struct freelQ_e *e = &q->entries[q->pidx]; | |
833 | unsigned int dma_len = q->rx_buffer_size - q->dma_offset; | |
8199d3a7 | 834 | |
559fb51b SB |
835 | while (q->credits < q->size) { |
836 | struct sk_buff *skb; | |
837 | dma_addr_t mapping; | |
8199d3a7 | 838 | |
559fb51b SB |
839 | skb = alloc_skb(q->rx_buffer_size, GFP_ATOMIC); |
840 | if (!skb) | |
841 | break; | |
842 | ||
843 | skb_reserve(skb, q->dma_offset); | |
844 | mapping = pci_map_single(pdev, skb->data, dma_len, | |
845 | PCI_DMA_FROMDEVICE); | |
24a427cf SH |
846 | skb_reserve(skb, sge->rx_pkt_pad); |
847 | ||
559fb51b SB |
848 | ce->skb = skb; |
849 | pci_unmap_addr_set(ce, dma_addr, mapping); | |
850 | pci_unmap_len_set(ce, dma_len, dma_len); | |
851 | e->addr_lo = (u32)mapping; | |
852 | e->addr_hi = (u64)mapping >> 32; | |
853 | e->len_gen = V_CMD_LEN(dma_len) | V_CMD_GEN1(q->genbit); | |
854 | wmb(); | |
855 | e->gen2 = V_CMD_GEN2(q->genbit); | |
8199d3a7 CL |
856 | |
857 | e++; | |
858 | ce++; | |
559fb51b SB |
859 | if (++q->pidx == q->size) { |
860 | q->pidx = 0; | |
861 | q->genbit ^= 1; | |
862 | ce = q->centries; | |
863 | e = q->entries; | |
8199d3a7 | 864 | } |
559fb51b | 865 | q->credits++; |
8199d3a7 | 866 | } |
8199d3a7 CL |
867 | } |
868 | ||
869 | /* | |
559fb51b SB |
870 | * Calls refill_free_list for both free lists. If we cannot fill at least 1/4 |
871 | * of both rings, we go into 'few interrupt mode' in order to give the system | |
872 | * time to free up resources. | |
8199d3a7 CL |
873 | */ |
874 | static void freelQs_empty(struct sge *sge) | |
875 | { | |
559fb51b SB |
876 | struct adapter *adapter = sge->adapter; |
877 | u32 irq_reg = readl(adapter->regs + A_SG_INT_ENABLE); | |
8199d3a7 CL |
878 | u32 irqholdoff_reg; |
879 | ||
880 | refill_free_list(sge, &sge->freelQ[0]); | |
881 | refill_free_list(sge, &sge->freelQ[1]); | |
882 | ||
559fb51b SB |
883 | if (sge->freelQ[0].credits > (sge->freelQ[0].size >> 2) && |
884 | sge->freelQ[1].credits > (sge->freelQ[1].size >> 2)) { | |
8199d3a7 | 885 | irq_reg |= F_FL_EXHAUSTED; |
559fb51b | 886 | irqholdoff_reg = sge->fixed_intrtimer; |
8199d3a7 CL |
887 | } else { |
888 | /* Clear the F_FL_EXHAUSTED interrupts for now */ | |
889 | irq_reg &= ~F_FL_EXHAUSTED; | |
890 | irqholdoff_reg = sge->intrtimer_nres; | |
891 | } | |
559fb51b SB |
892 | writel(irqholdoff_reg, adapter->regs + A_SG_INTRTIMER); |
893 | writel(irq_reg, adapter->regs + A_SG_INT_ENABLE); | |
8199d3a7 CL |
894 | |
895 | /* We reenable the Qs to force a freelist GTS interrupt later */ | |
559fb51b | 896 | doorbell_pio(adapter, F_FL0_ENABLE | F_FL1_ENABLE); |
8199d3a7 CL |
897 | } |
898 | ||
899 | #define SGE_PL_INTR_MASK (F_PL_INTR_SGE_ERR | F_PL_INTR_SGE_DATA) | |
900 | #define SGE_INT_FATAL (F_RESPQ_OVERFLOW | F_PACKET_TOO_BIG | F_PACKET_MISMATCH) | |
901 | #define SGE_INT_ENABLE (F_RESPQ_EXHAUSTED | F_RESPQ_OVERFLOW | \ | |
902 | F_FL_EXHAUSTED | F_PACKET_TOO_BIG | F_PACKET_MISMATCH) | |
903 | ||
904 | /* | |
905 | * Disable SGE Interrupts | |
906 | */ | |
907 | void t1_sge_intr_disable(struct sge *sge) | |
908 | { | |
559fb51b | 909 | u32 val = readl(sge->adapter->regs + A_PL_ENABLE); |
8199d3a7 | 910 | |
559fb51b SB |
911 | writel(val & ~SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE); |
912 | writel(0, sge->adapter->regs + A_SG_INT_ENABLE); | |
8199d3a7 CL |
913 | } |
914 | ||
915 | /* | |
916 | * Enable SGE interrupts. | |
917 | */ | |
918 | void t1_sge_intr_enable(struct sge *sge) | |
919 | { | |
920 | u32 en = SGE_INT_ENABLE; | |
559fb51b | 921 | u32 val = readl(sge->adapter->regs + A_PL_ENABLE); |
8199d3a7 CL |
922 | |
923 | if (sge->adapter->flags & TSO_CAPABLE) | |
924 | en &= ~F_PACKET_TOO_BIG; | |
559fb51b SB |
925 | writel(en, sge->adapter->regs + A_SG_INT_ENABLE); |
926 | writel(val | SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE); | |
8199d3a7 CL |
927 | } |
928 | ||
929 | /* | |
930 | * Clear SGE interrupts. | |
931 | */ | |
932 | void t1_sge_intr_clear(struct sge *sge) | |
933 | { | |
559fb51b SB |
934 | writel(SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_CAUSE); |
935 | writel(0xffffffff, sge->adapter->regs + A_SG_INT_CAUSE); | |
8199d3a7 CL |
936 | } |
937 | ||
938 | /* | |
939 | * SGE 'Error' interrupt handler | |
940 | */ | |
941 | int t1_sge_intr_error_handler(struct sge *sge) | |
942 | { | |
943 | struct adapter *adapter = sge->adapter; | |
559fb51b | 944 | u32 cause = readl(adapter->regs + A_SG_INT_CAUSE); |
8199d3a7 CL |
945 | |
946 | if (adapter->flags & TSO_CAPABLE) | |
947 | cause &= ~F_PACKET_TOO_BIG; | |
948 | if (cause & F_RESPQ_EXHAUSTED) | |
559fb51b | 949 | sge->stats.respQ_empty++; |
8199d3a7 | 950 | if (cause & F_RESPQ_OVERFLOW) { |
559fb51b | 951 | sge->stats.respQ_overflow++; |
8199d3a7 CL |
952 | CH_ALERT("%s: SGE response queue overflow\n", |
953 | adapter->name); | |
954 | } | |
955 | if (cause & F_FL_EXHAUSTED) { | |
559fb51b | 956 | sge->stats.freelistQ_empty++; |
8199d3a7 CL |
957 | freelQs_empty(sge); |
958 | } | |
959 | if (cause & F_PACKET_TOO_BIG) { | |
559fb51b | 960 | sge->stats.pkt_too_big++; |
8199d3a7 CL |
961 | CH_ALERT("%s: SGE max packet size exceeded\n", |
962 | adapter->name); | |
963 | } | |
964 | if (cause & F_PACKET_MISMATCH) { | |
559fb51b | 965 | sge->stats.pkt_mismatch++; |
8199d3a7 CL |
966 | CH_ALERT("%s: SGE packet mismatch\n", adapter->name); |
967 | } | |
968 | if (cause & SGE_INT_FATAL) | |
969 | t1_fatal_err(adapter); | |
970 | ||
559fb51b | 971 | writel(cause, adapter->regs + A_SG_INT_CAUSE); |
8199d3a7 CL |
972 | return 0; |
973 | } | |
974 | ||
56f643c2 | 975 | const struct sge_intr_counts *t1_sge_get_intr_counts(const struct sge *sge) |
559fb51b SB |
976 | { |
977 | return &sge->stats; | |
978 | } | |
979 | ||
56f643c2 SH |
980 | void t1_sge_get_port_stats(const struct sge *sge, int port, |
981 | struct sge_port_stats *ss) | |
559fb51b | 982 | { |
56f643c2 SH |
983 | int cpu; |
984 | ||
985 | memset(ss, 0, sizeof(*ss)); | |
986 | for_each_possible_cpu(cpu) { | |
987 | struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[port], cpu); | |
988 | ||
989 | ss->rx_packets += st->rx_packets; | |
990 | ss->rx_cso_good += st->rx_cso_good; | |
991 | ss->tx_packets += st->tx_packets; | |
992 | ss->tx_cso += st->tx_cso; | |
993 | ss->tx_tso += st->tx_tso; | |
994 | ss->vlan_xtract += st->vlan_xtract; | |
995 | ss->vlan_insert += st->vlan_insert; | |
996 | } | |
559fb51b SB |
997 | } |
998 | ||
999 | /** | |
1000 | * recycle_fl_buf - recycle a free list buffer | |
1001 | * @fl: the free list | |
1002 | * @idx: index of buffer to recycle | |
8199d3a7 | 1003 | * |
559fb51b SB |
1004 | * Recycles the specified buffer on the given free list by adding it at |
1005 | * the next available slot on the list. | |
8199d3a7 | 1006 | */ |
559fb51b | 1007 | static void recycle_fl_buf(struct freelQ *fl, int idx) |
8199d3a7 | 1008 | { |
559fb51b SB |
1009 | struct freelQ_e *from = &fl->entries[idx]; |
1010 | struct freelQ_e *to = &fl->entries[fl->pidx]; | |
8199d3a7 | 1011 | |
559fb51b SB |
1012 | fl->centries[fl->pidx] = fl->centries[idx]; |
1013 | to->addr_lo = from->addr_lo; | |
1014 | to->addr_hi = from->addr_hi; | |
1015 | to->len_gen = G_CMD_LEN(from->len_gen) | V_CMD_GEN1(fl->genbit); | |
1016 | wmb(); | |
1017 | to->gen2 = V_CMD_GEN2(fl->genbit); | |
1018 | fl->credits++; | |
8199d3a7 | 1019 | |
559fb51b SB |
1020 | if (++fl->pidx == fl->size) { |
1021 | fl->pidx = 0; | |
1022 | fl->genbit ^= 1; | |
8199d3a7 | 1023 | } |
559fb51b | 1024 | } |
8199d3a7 | 1025 | |
24a427cf SH |
1026 | static int copybreak __read_mostly = 256; |
1027 | module_param(copybreak, int, 0); | |
1028 | MODULE_PARM_DESC(copybreak, "Receive copy threshold"); | |
1029 | ||
559fb51b SB |
1030 | /** |
1031 | * get_packet - return the next ingress packet buffer | |
1032 | * @pdev: the PCI device that received the packet | |
1033 | * @fl: the SGE free list holding the packet | |
1034 | * @len: the actual packet length, excluding any SGE padding | |
1035 | * @dma_pad: padding at beginning of buffer left by SGE DMA | |
1036 | * @skb_pad: padding to be used if the packet is copied | |
1037 | * @copy_thres: length threshold under which a packet should be copied | |
1038 | * @drop_thres: # of remaining buffers before we start dropping packets | |
1039 | * | |
1040 | * Get the next packet from a free list and complete setup of the | |
1041 | * sk_buff. If the packet is small we make a copy and recycle the | |
1042 | * original buffer, otherwise we use the original buffer itself. If a | |
1043 | * positive drop threshold is supplied packets are dropped and their | |
1044 | * buffers recycled if (a) the number of remaining buffers is under the | |
1045 | * threshold and the packet is too big to copy, or (b) the packet should | |
1046 | * be copied but there is no memory for the copy. | |
1047 | */ | |
1048 | static inline struct sk_buff *get_packet(struct pci_dev *pdev, | |
24a427cf | 1049 | struct freelQ *fl, unsigned int len) |
559fb51b SB |
1050 | { |
1051 | struct sk_buff *skb; | |
24a427cf | 1052 | const struct freelQ_ce *ce = &fl->centries[fl->cidx]; |
559fb51b | 1053 | |
24a427cf SH |
1054 | if (len < copybreak) { |
1055 | skb = alloc_skb(len + 2, GFP_ATOMIC); | |
1056 | if (!skb) | |
1057 | goto use_orig_buf; | |
1058 | ||
1059 | skb_reserve(skb, 2); /* align IP header */ | |
1060 | skb_put(skb, len); | |
1061 | pci_dma_sync_single_for_cpu(pdev, | |
559fb51b | 1062 | pci_unmap_addr(ce, dma_addr), |
356bd146 | 1063 | pci_unmap_len(ce, dma_len), |
559fb51b | 1064 | PCI_DMA_FROMDEVICE); |
24a427cf SH |
1065 | memcpy(skb->data, ce->skb->data, len); |
1066 | pci_dma_sync_single_for_device(pdev, | |
1067 | pci_unmap_addr(ce, dma_addr), | |
1068 | pci_unmap_len(ce, dma_len), | |
1069 | PCI_DMA_FROMDEVICE); | |
559fb51b SB |
1070 | recycle_fl_buf(fl, fl->cidx); |
1071 | return skb; | |
8199d3a7 CL |
1072 | } |
1073 | ||
24a427cf SH |
1074 | use_orig_buf: |
1075 | if (fl->credits < 2) { | |
559fb51b SB |
1076 | recycle_fl_buf(fl, fl->cidx); |
1077 | return NULL; | |
1078 | } | |
8199d3a7 | 1079 | |
559fb51b SB |
1080 | pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr), |
1081 | pci_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE); | |
1082 | skb = ce->skb; | |
24a427cf SH |
1083 | prefetch(skb->data); |
1084 | ||
559fb51b SB |
1085 | skb_put(skb, len); |
1086 | return skb; | |
1087 | } | |
8199d3a7 | 1088 | |
559fb51b SB |
1089 | /** |
1090 | * unexpected_offload - handle an unexpected offload packet | |
1091 | * @adapter: the adapter | |
1092 | * @fl: the free list that received the packet | |
1093 | * | |
1094 | * Called when we receive an unexpected offload packet (e.g., the TOE | |
1095 | * function is disabled or the card is a NIC). Prints a message and | |
1096 | * recycles the buffer. | |
1097 | */ | |
1098 | static void unexpected_offload(struct adapter *adapter, struct freelQ *fl) | |
1099 | { | |
1100 | struct freelQ_ce *ce = &fl->centries[fl->cidx]; | |
1101 | struct sk_buff *skb = ce->skb; | |
1102 | ||
1103 | pci_dma_sync_single_for_cpu(adapter->pdev, pci_unmap_addr(ce, dma_addr), | |
1104 | pci_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE); | |
1105 | CH_ERR("%s: unexpected offload packet, cmd %u\n", | |
1106 | adapter->name, *skb->data); | |
1107 | recycle_fl_buf(fl, fl->cidx); | |
8199d3a7 CL |
1108 | } |
1109 | ||
f1d3d38a SH |
1110 | /* |
1111 | * T1/T2 SGE limits the maximum DMA size per TX descriptor to | |
1112 | * SGE_TX_DESC_MAX_PLEN (16KB). If the PAGE_SIZE is larger than 16KB, the | |
1113 | * stack might send more than SGE_TX_DESC_MAX_PLEN in a contiguous manner. | |
1114 | * Note that the *_large_page_tx_descs stuff will be optimized out when | |
1115 | * PAGE_SIZE <= SGE_TX_DESC_MAX_PLEN. | |
1116 | * | |
1117 | * compute_large_page_descs() computes how many additional descriptors are | |
1118 | * required to break down the stack's request. | |
1119 | */ | |
1120 | static inline unsigned int compute_large_page_tx_descs(struct sk_buff *skb) | |
1121 | { | |
1122 | unsigned int count = 0; | |
356bd146 | 1123 | |
f1d3d38a SH |
1124 | if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) { |
1125 | unsigned int nfrags = skb_shinfo(skb)->nr_frags; | |
1126 | unsigned int i, len = skb->len - skb->data_len; | |
1127 | while (len > SGE_TX_DESC_MAX_PLEN) { | |
1128 | count++; | |
1129 | len -= SGE_TX_DESC_MAX_PLEN; | |
1130 | } | |
1131 | for (i = 0; nfrags--; i++) { | |
1132 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
1133 | len = frag->size; | |
1134 | while (len > SGE_TX_DESC_MAX_PLEN) { | |
1135 | count++; | |
1136 | len -= SGE_TX_DESC_MAX_PLEN; | |
1137 | } | |
1138 | } | |
1139 | } | |
1140 | return count; | |
1141 | } | |
1142 | ||
1143 | /* | |
1144 | * Write a cmdQ entry. | |
1145 | * | |
1146 | * Since this function writes the 'flags' field, it must not be used to | |
1147 | * write the first cmdQ entry. | |
1148 | */ | |
1149 | static inline void write_tx_desc(struct cmdQ_e *e, dma_addr_t mapping, | |
1150 | unsigned int len, unsigned int gen, | |
1151 | unsigned int eop) | |
1152 | { | |
1153 | if (unlikely(len > SGE_TX_DESC_MAX_PLEN)) | |
1154 | BUG(); | |
1155 | e->addr_lo = (u32)mapping; | |
1156 | e->addr_hi = (u64)mapping >> 32; | |
1157 | e->len_gen = V_CMD_LEN(len) | V_CMD_GEN1(gen); | |
1158 | e->flags = F_CMD_DATAVALID | V_CMD_EOP(eop) | V_CMD_GEN2(gen); | |
1159 | } | |
1160 | ||
1161 | /* | |
1162 | * See comment for previous function. | |
1163 | * | |
1164 | * write_tx_descs_large_page() writes additional SGE tx descriptors if | |
1165 | * *desc_len exceeds HW's capability. | |
1166 | */ | |
1167 | static inline unsigned int write_large_page_tx_descs(unsigned int pidx, | |
1168 | struct cmdQ_e **e, | |
1169 | struct cmdQ_ce **ce, | |
1170 | unsigned int *gen, | |
1171 | dma_addr_t *desc_mapping, | |
1172 | unsigned int *desc_len, | |
1173 | unsigned int nfrags, | |
1174 | struct cmdQ *q) | |
1175 | { | |
1176 | if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) { | |
1177 | struct cmdQ_e *e1 = *e; | |
1178 | struct cmdQ_ce *ce1 = *ce; | |
1179 | ||
1180 | while (*desc_len > SGE_TX_DESC_MAX_PLEN) { | |
1181 | *desc_len -= SGE_TX_DESC_MAX_PLEN; | |
1182 | write_tx_desc(e1, *desc_mapping, SGE_TX_DESC_MAX_PLEN, | |
1183 | *gen, nfrags == 0 && *desc_len == 0); | |
1184 | ce1->skb = NULL; | |
1185 | pci_unmap_len_set(ce1, dma_len, 0); | |
1186 | *desc_mapping += SGE_TX_DESC_MAX_PLEN; | |
1187 | if (*desc_len) { | |
1188 | ce1++; | |
1189 | e1++; | |
1190 | if (++pidx == q->size) { | |
1191 | pidx = 0; | |
1192 | *gen ^= 1; | |
1193 | ce1 = q->centries; | |
1194 | e1 = q->entries; | |
1195 | } | |
1196 | } | |
1197 | } | |
1198 | *e = e1; | |
1199 | *ce = ce1; | |
1200 | } | |
1201 | return pidx; | |
1202 | } | |
1203 | ||
8199d3a7 | 1204 | /* |
559fb51b SB |
1205 | * Write the command descriptors to transmit the given skb starting at |
1206 | * descriptor pidx with the given generation. | |
8199d3a7 | 1207 | */ |
559fb51b SB |
1208 | static inline void write_tx_descs(struct adapter *adapter, struct sk_buff *skb, |
1209 | unsigned int pidx, unsigned int gen, | |
1210 | struct cmdQ *q) | |
8199d3a7 | 1211 | { |
f1d3d38a | 1212 | dma_addr_t mapping, desc_mapping; |
559fb51b SB |
1213 | struct cmdQ_e *e, *e1; |
1214 | struct cmdQ_ce *ce; | |
f1d3d38a SH |
1215 | unsigned int i, flags, first_desc_len, desc_len, |
1216 | nfrags = skb_shinfo(skb)->nr_frags; | |
559fb51b | 1217 | |
f1d3d38a | 1218 | e = e1 = &q->entries[pidx]; |
559fb51b | 1219 | ce = &q->centries[pidx]; |
f1d3d38a SH |
1220 | |
1221 | mapping = pci_map_single(adapter->pdev, skb->data, | |
1222 | skb->len - skb->data_len, PCI_DMA_TODEVICE); | |
1223 | ||
1224 | desc_mapping = mapping; | |
1225 | desc_len = skb->len - skb->data_len; | |
1226 | ||
1227 | flags = F_CMD_DATAVALID | F_CMD_SOP | | |
1228 | V_CMD_EOP(nfrags == 0 && desc_len <= SGE_TX_DESC_MAX_PLEN) | | |
1229 | V_CMD_GEN2(gen); | |
1230 | first_desc_len = (desc_len <= SGE_TX_DESC_MAX_PLEN) ? | |
1231 | desc_len : SGE_TX_DESC_MAX_PLEN; | |
1232 | e->addr_lo = (u32)desc_mapping; | |
1233 | e->addr_hi = (u64)desc_mapping >> 32; | |
1234 | e->len_gen = V_CMD_LEN(first_desc_len) | V_CMD_GEN1(gen); | |
1235 | ce->skb = NULL; | |
1236 | pci_unmap_len_set(ce, dma_len, 0); | |
1237 | ||
1238 | if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN && | |
1239 | desc_len > SGE_TX_DESC_MAX_PLEN) { | |
1240 | desc_mapping += first_desc_len; | |
1241 | desc_len -= first_desc_len; | |
1242 | e1++; | |
1243 | ce++; | |
1244 | if (++pidx == q->size) { | |
1245 | pidx = 0; | |
1246 | gen ^= 1; | |
1247 | e1 = q->entries; | |
1248 | ce = q->centries; | |
1249 | } | |
1250 | pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen, | |
1251 | &desc_mapping, &desc_len, | |
1252 | nfrags, q); | |
1253 | ||
1254 | if (likely(desc_len)) | |
1255 | write_tx_desc(e1, desc_mapping, desc_len, gen, | |
1256 | nfrags == 0); | |
1257 | } | |
1258 | ||
559fb51b SB |
1259 | ce->skb = NULL; |
1260 | pci_unmap_addr_set(ce, dma_addr, mapping); | |
1261 | pci_unmap_len_set(ce, dma_len, skb->len - skb->data_len); | |
8199d3a7 | 1262 | |
f1d3d38a | 1263 | for (i = 0; nfrags--; i++) { |
559fb51b | 1264 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
559fb51b | 1265 | e1++; |
f1d3d38a | 1266 | ce++; |
559fb51b SB |
1267 | if (++pidx == q->size) { |
1268 | pidx = 0; | |
1269 | gen ^= 1; | |
559fb51b | 1270 | e1 = q->entries; |
f1d3d38a | 1271 | ce = q->centries; |
8199d3a7 | 1272 | } |
8199d3a7 | 1273 | |
559fb51b SB |
1274 | mapping = pci_map_page(adapter->pdev, frag->page, |
1275 | frag->page_offset, frag->size, | |
1276 | PCI_DMA_TODEVICE); | |
f1d3d38a SH |
1277 | desc_mapping = mapping; |
1278 | desc_len = frag->size; | |
1279 | ||
1280 | pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen, | |
1281 | &desc_mapping, &desc_len, | |
1282 | nfrags, q); | |
1283 | if (likely(desc_len)) | |
1284 | write_tx_desc(e1, desc_mapping, desc_len, gen, | |
1285 | nfrags == 0); | |
559fb51b SB |
1286 | ce->skb = NULL; |
1287 | pci_unmap_addr_set(ce, dma_addr, mapping); | |
1288 | pci_unmap_len_set(ce, dma_len, frag->size); | |
8199d3a7 | 1289 | } |
559fb51b SB |
1290 | ce->skb = skb; |
1291 | wmb(); | |
1292 | e->flags = flags; | |
1293 | } | |
8199d3a7 | 1294 | |
559fb51b SB |
1295 | /* |
1296 | * Clean up completed Tx buffers. | |
1297 | */ | |
1298 | static inline void reclaim_completed_tx(struct sge *sge, struct cmdQ *q) | |
1299 | { | |
1300 | unsigned int reclaim = q->processed - q->cleaned; | |
8199d3a7 | 1301 | |
559fb51b | 1302 | if (reclaim) { |
f1d3d38a SH |
1303 | pr_debug("reclaim_completed_tx processed:%d cleaned:%d\n", |
1304 | q->processed, q->cleaned); | |
559fb51b SB |
1305 | free_cmdQ_buffers(sge, q, reclaim); |
1306 | q->cleaned += reclaim; | |
8199d3a7 | 1307 | } |
559fb51b | 1308 | } |
8199d3a7 | 1309 | |
f1d3d38a SH |
1310 | /* |
1311 | * Called from tasklet. Checks the scheduler for any | |
1312 | * pending skbs that can be sent. | |
1313 | */ | |
1314 | static void restart_sched(unsigned long arg) | |
1315 | { | |
1316 | struct sge *sge = (struct sge *) arg; | |
1317 | struct adapter *adapter = sge->adapter; | |
1318 | struct cmdQ *q = &sge->cmdQ[0]; | |
1319 | struct sk_buff *skb; | |
1320 | unsigned int credits, queued_skb = 0; | |
1321 | ||
1322 | spin_lock(&q->lock); | |
1323 | reclaim_completed_tx(sge, q); | |
1324 | ||
1325 | credits = q->size - q->in_use; | |
1326 | pr_debug("restart_sched credits=%d\n", credits); | |
1327 | while ((skb = sched_skb(sge, NULL, credits)) != NULL) { | |
1328 | unsigned int genbit, pidx, count; | |
1329 | count = 1 + skb_shinfo(skb)->nr_frags; | |
356bd146 | 1330 | count += compute_large_page_tx_descs(skb); |
f1d3d38a SH |
1331 | q->in_use += count; |
1332 | genbit = q->genbit; | |
1333 | pidx = q->pidx; | |
1334 | q->pidx += count; | |
1335 | if (q->pidx >= q->size) { | |
1336 | q->pidx -= q->size; | |
1337 | q->genbit ^= 1; | |
1338 | } | |
1339 | write_tx_descs(adapter, skb, pidx, genbit, q); | |
1340 | credits = q->size - q->in_use; | |
1341 | queued_skb = 1; | |
1342 | } | |
1343 | ||
1344 | if (queued_skb) { | |
1345 | clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
1346 | if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) { | |
1347 | set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
1348 | writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); | |
1349 | } | |
1350 | } | |
1351 | spin_unlock(&q->lock); | |
1352 | } | |
8199d3a7 | 1353 | |
559fb51b SB |
1354 | /** |
1355 | * sge_rx - process an ingress ethernet packet | |
1356 | * @sge: the sge structure | |
1357 | * @fl: the free list that contains the packet buffer | |
1358 | * @len: the packet length | |
8199d3a7 | 1359 | * |
559fb51b | 1360 | * Process an ingress ethernet pakcet and deliver it to the stack. |
8199d3a7 | 1361 | */ |
24a427cf | 1362 | static void sge_rx(struct sge *sge, struct freelQ *fl, unsigned int len) |
8199d3a7 | 1363 | { |
559fb51b | 1364 | struct sk_buff *skb; |
24a427cf | 1365 | const struct cpl_rx_pkt *p; |
559fb51b | 1366 | struct adapter *adapter = sge->adapter; |
56f643c2 | 1367 | struct sge_port_stats *st; |
8199d3a7 | 1368 | |
24a427cf | 1369 | skb = get_packet(adapter->pdev, fl, len - sge->rx_pkt_pad); |
56f643c2 SH |
1370 | if (unlikely(!skb)) { |
1371 | sge->stats.rx_drops++; | |
24a427cf | 1372 | return; |
8199d3a7 | 1373 | } |
559fb51b | 1374 | |
24a427cf | 1375 | p = (const struct cpl_rx_pkt *) skb->data; |
f1d3d38a SH |
1376 | if (p->iff >= adapter->params.nports) { |
1377 | kfree_skb(skb); | |
24a427cf | 1378 | return; |
f1d3d38a | 1379 | } |
24a427cf | 1380 | __skb_pull(skb, sizeof(*p)); |
f1d3d38a | 1381 | |
559fb51b | 1382 | skb->dev->last_rx = jiffies; |
56f643c2 SH |
1383 | st = per_cpu_ptr(sge->port_stats[p->iff], smp_processor_id()); |
1384 | st->rx_packets++; | |
1385 | ||
4c13eb66 | 1386 | skb->protocol = eth_type_trans(skb, adapter->port[p->iff].dev); |
559fb51b SB |
1387 | if ((adapter->flags & RX_CSUM_ENABLED) && p->csum == 0xffff && |
1388 | skb->protocol == htons(ETH_P_IP) && | |
1389 | (skb->data[9] == IPPROTO_TCP || skb->data[9] == IPPROTO_UDP)) { | |
56f643c2 | 1390 | ++st->rx_cso_good; |
559fb51b SB |
1391 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
1392 | } else | |
1393 | skb->ip_summed = CHECKSUM_NONE; | |
1394 | ||
1395 | if (unlikely(adapter->vlan_grp && p->vlan_valid)) { | |
56f643c2 | 1396 | st->vlan_xtract++; |
7fe26a60 | 1397 | #ifdef CONFIG_CHELSIO_T1_NAPI |
559fb51b SB |
1398 | vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, |
1399 | ntohs(p->vlan)); | |
7fe26a60 | 1400 | #else |
559fb51b SB |
1401 | vlan_hwaccel_rx(skb, adapter->vlan_grp, |
1402 | ntohs(p->vlan)); | |
7fe26a60 SH |
1403 | #endif |
1404 | } else { | |
1405 | #ifdef CONFIG_CHELSIO_T1_NAPI | |
559fb51b | 1406 | netif_receive_skb(skb); |
7fe26a60 | 1407 | #else |
559fb51b | 1408 | netif_rx(skb); |
7fe26a60 SH |
1409 | #endif |
1410 | } | |
8199d3a7 CL |
1411 | } |
1412 | ||
1413 | /* | |
559fb51b | 1414 | * Returns true if a command queue has enough available descriptors that |
8199d3a7 CL |
1415 | * we can resume Tx operation after temporarily disabling its packet queue. |
1416 | */ | |
559fb51b | 1417 | static inline int enough_free_Tx_descs(const struct cmdQ *q) |
8199d3a7 | 1418 | { |
559fb51b SB |
1419 | unsigned int r = q->processed - q->cleaned; |
1420 | ||
1421 | return q->in_use - r < (q->size >> 1); | |
8199d3a7 CL |
1422 | } |
1423 | ||
1424 | /* | |
559fb51b SB |
1425 | * Called when sufficient space has become available in the SGE command queues |
1426 | * after the Tx packet schedulers have been suspended to restart the Tx path. | |
8199d3a7 | 1427 | */ |
559fb51b | 1428 | static void restart_tx_queues(struct sge *sge) |
8199d3a7 | 1429 | { |
559fb51b | 1430 | struct adapter *adap = sge->adapter; |
3e0f75be | 1431 | int i; |
8199d3a7 | 1432 | |
3e0f75be FR |
1433 | if (!enough_free_Tx_descs(&sge->cmdQ[0])) |
1434 | return; | |
559fb51b | 1435 | |
3e0f75be FR |
1436 | for_each_port(adap, i) { |
1437 | struct net_device *nd = adap->port[i].dev; | |
559fb51b | 1438 | |
3e0f75be FR |
1439 | if (test_and_clear_bit(nd->if_port, &sge->stopped_tx_queues) && |
1440 | netif_running(nd)) { | |
1441 | sge->stats.cmdQ_restarted[2]++; | |
1442 | netif_wake_queue(nd); | |
559fb51b SB |
1443 | } |
1444 | } | |
1445 | } | |
1446 | ||
1447 | /* | |
356bd146 | 1448 | * update_tx_info is called from the interrupt handler/NAPI to return cmdQ0 |
559fb51b SB |
1449 | * information. |
1450 | */ | |
356bd146 FR |
1451 | static unsigned int update_tx_info(struct adapter *adapter, |
1452 | unsigned int flags, | |
559fb51b SB |
1453 | unsigned int pr0) |
1454 | { | |
1455 | struct sge *sge = adapter->sge; | |
1456 | struct cmdQ *cmdq = &sge->cmdQ[0]; | |
8199d3a7 | 1457 | |
559fb51b | 1458 | cmdq->processed += pr0; |
f1d3d38a SH |
1459 | if (flags & (F_FL0_ENABLE | F_FL1_ENABLE)) { |
1460 | freelQs_empty(sge); | |
1461 | flags &= ~(F_FL0_ENABLE | F_FL1_ENABLE); | |
1462 | } | |
559fb51b SB |
1463 | if (flags & F_CMDQ0_ENABLE) { |
1464 | clear_bit(CMDQ_STAT_RUNNING, &cmdq->status); | |
f1d3d38a | 1465 | |
559fb51b SB |
1466 | if (cmdq->cleaned + cmdq->in_use != cmdq->processed && |
1467 | !test_and_set_bit(CMDQ_STAT_LAST_PKT_DB, &cmdq->status)) { | |
1468 | set_bit(CMDQ_STAT_RUNNING, &cmdq->status); | |
1469 | writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); | |
1470 | } | |
f1d3d38a SH |
1471 | if (sge->tx_sched) |
1472 | tasklet_hi_schedule(&sge->tx_sched->sched_tsk); | |
1473 | ||
1474 | flags &= ~F_CMDQ0_ENABLE; | |
559fb51b | 1475 | } |
f1d3d38a | 1476 | |
559fb51b SB |
1477 | if (unlikely(sge->stopped_tx_queues != 0)) |
1478 | restart_tx_queues(sge); | |
8199d3a7 | 1479 | |
559fb51b SB |
1480 | return flags; |
1481 | } | |
8199d3a7 | 1482 | |
559fb51b SB |
1483 | /* |
1484 | * Process SGE responses, up to the supplied budget. Returns the number of | |
1485 | * responses processed. A negative budget is effectively unlimited. | |
1486 | */ | |
1487 | static int process_responses(struct adapter *adapter, int budget) | |
1488 | { | |
1489 | struct sge *sge = adapter->sge; | |
1490 | struct respQ *q = &sge->respQ; | |
1491 | struct respQ_e *e = &q->entries[q->cidx]; | |
24a427cf | 1492 | int done = 0; |
559fb51b SB |
1493 | unsigned int flags = 0; |
1494 | unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0}; | |
356bd146 | 1495 | |
24a427cf | 1496 | while (done < budget && e->GenerationBit == q->genbit) { |
559fb51b | 1497 | flags |= e->Qsleeping; |
356bd146 | 1498 | |
559fb51b SB |
1499 | cmdq_processed[0] += e->Cmdq0CreditReturn; |
1500 | cmdq_processed[1] += e->Cmdq1CreditReturn; | |
356bd146 | 1501 | |
559fb51b SB |
1502 | /* We batch updates to the TX side to avoid cacheline |
1503 | * ping-pong of TX state information on MP where the sender | |
1504 | * might run on a different CPU than this function... | |
1505 | */ | |
24a427cf | 1506 | if (unlikely((flags & F_CMDQ0_ENABLE) || cmdq_processed[0] > 64)) { |
559fb51b SB |
1507 | flags = update_tx_info(adapter, flags, cmdq_processed[0]); |
1508 | cmdq_processed[0] = 0; | |
1509 | } | |
24a427cf | 1510 | |
559fb51b SB |
1511 | if (unlikely(cmdq_processed[1] > 16)) { |
1512 | sge->cmdQ[1].processed += cmdq_processed[1]; | |
1513 | cmdq_processed[1] = 0; | |
8199d3a7 | 1514 | } |
24a427cf | 1515 | |
8199d3a7 | 1516 | if (likely(e->DataValid)) { |
559fb51b SB |
1517 | struct freelQ *fl = &sge->freelQ[e->FreelistQid]; |
1518 | ||
5d9428de | 1519 | BUG_ON(!e->Sop || !e->Eop); |
559fb51b SB |
1520 | if (unlikely(e->Offload)) |
1521 | unexpected_offload(adapter, fl); | |
1522 | else | |
1523 | sge_rx(sge, fl, e->BufferLength); | |
1524 | ||
24a427cf SH |
1525 | ++done; |
1526 | ||
559fb51b SB |
1527 | /* |
1528 | * Note: this depends on each packet consuming a | |
1529 | * single free-list buffer; cf. the BUG above. | |
1530 | */ | |
1531 | if (++fl->cidx == fl->size) | |
1532 | fl->cidx = 0; | |
24a427cf SH |
1533 | prefetch(fl->centries[fl->cidx].skb); |
1534 | ||
559fb51b SB |
1535 | if (unlikely(--fl->credits < |
1536 | fl->size - SGE_FREEL_REFILL_THRESH)) | |
1537 | refill_free_list(sge, fl); | |
1538 | } else | |
1539 | sge->stats.pure_rsps++; | |
8199d3a7 | 1540 | |
8199d3a7 | 1541 | e++; |
559fb51b SB |
1542 | if (unlikely(++q->cidx == q->size)) { |
1543 | q->cidx = 0; | |
1544 | q->genbit ^= 1; | |
1545 | e = q->entries; | |
1546 | } | |
1547 | prefetch(e); | |
1548 | ||
1549 | if (++q->credits > SGE_RESPQ_REPLENISH_THRES) { | |
1550 | writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT); | |
1551 | q->credits = 0; | |
8199d3a7 CL |
1552 | } |
1553 | } | |
1554 | ||
356bd146 | 1555 | flags = update_tx_info(adapter, flags, cmdq_processed[0]); |
559fb51b | 1556 | sge->cmdQ[1].processed += cmdq_processed[1]; |
8199d3a7 | 1557 | |
24a427cf | 1558 | return done; |
559fb51b | 1559 | } |
8199d3a7 | 1560 | |
3de00b89 SH |
1561 | static inline int responses_pending(const struct adapter *adapter) |
1562 | { | |
1563 | const struct respQ *Q = &adapter->sge->respQ; | |
1564 | const struct respQ_e *e = &Q->entries[Q->cidx]; | |
1565 | ||
1566 | return (e->GenerationBit == Q->genbit); | |
1567 | } | |
1568 | ||
7fe26a60 | 1569 | #ifdef CONFIG_CHELSIO_T1_NAPI |
559fb51b SB |
1570 | /* |
1571 | * A simpler version of process_responses() that handles only pure (i.e., | |
1572 | * non data-carrying) responses. Such respones are too light-weight to justify | |
1573 | * calling a softirq when using NAPI, so we handle them specially in hard | |
1574 | * interrupt context. The function is called with a pointer to a response, | |
1575 | * which the caller must ensure is a valid pure response. Returns 1 if it | |
1576 | * encounters a valid data-carrying response, 0 otherwise. | |
1577 | */ | |
3de00b89 | 1578 | static int process_pure_responses(struct adapter *adapter) |
559fb51b SB |
1579 | { |
1580 | struct sge *sge = adapter->sge; | |
1581 | struct respQ *q = &sge->respQ; | |
3de00b89 | 1582 | struct respQ_e *e = &q->entries[q->cidx]; |
24a427cf | 1583 | const struct freelQ *fl = &sge->freelQ[e->FreelistQid]; |
559fb51b SB |
1584 | unsigned int flags = 0; |
1585 | unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0}; | |
8199d3a7 | 1586 | |
24a427cf | 1587 | prefetch(fl->centries[fl->cidx].skb); |
3de00b89 SH |
1588 | if (e->DataValid) |
1589 | return 1; | |
24a427cf | 1590 | |
559fb51b SB |
1591 | do { |
1592 | flags |= e->Qsleeping; | |
8199d3a7 | 1593 | |
559fb51b SB |
1594 | cmdq_processed[0] += e->Cmdq0CreditReturn; |
1595 | cmdq_processed[1] += e->Cmdq1CreditReturn; | |
356bd146 | 1596 | |
559fb51b SB |
1597 | e++; |
1598 | if (unlikely(++q->cidx == q->size)) { | |
1599 | q->cidx = 0; | |
1600 | q->genbit ^= 1; | |
1601 | e = q->entries; | |
8199d3a7 | 1602 | } |
559fb51b | 1603 | prefetch(e); |
8199d3a7 | 1604 | |
559fb51b SB |
1605 | if (++q->credits > SGE_RESPQ_REPLENISH_THRES) { |
1606 | writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT); | |
1607 | q->credits = 0; | |
8199d3a7 | 1608 | } |
559fb51b SB |
1609 | sge->stats.pure_rsps++; |
1610 | } while (e->GenerationBit == q->genbit && !e->DataValid); | |
8199d3a7 | 1611 | |
356bd146 | 1612 | flags = update_tx_info(adapter, flags, cmdq_processed[0]); |
559fb51b | 1613 | sge->cmdQ[1].processed += cmdq_processed[1]; |
8199d3a7 | 1614 | |
559fb51b | 1615 | return e->GenerationBit == q->genbit; |
8199d3a7 CL |
1616 | } |
1617 | ||
1618 | /* | |
559fb51b SB |
1619 | * Handler for new data events when using NAPI. This does not need any locking |
1620 | * or protection from interrupts as data interrupts are off at this point and | |
1621 | * other adapter interrupts do not interfere. | |
8199d3a7 | 1622 | */ |
7fe26a60 | 1623 | int t1_poll(struct net_device *dev, int *budget) |
8199d3a7 | 1624 | { |
559fb51b | 1625 | struct adapter *adapter = dev->priv; |
3de00b89 | 1626 | int work_done; |
7fe26a60 | 1627 | |
3de00b89 | 1628 | work_done = process_responses(adapter, min(*budget, dev->quota)); |
559fb51b SB |
1629 | *budget -= work_done; |
1630 | dev->quota -= work_done; | |
8199d3a7 | 1631 | |
3de00b89 | 1632 | if (unlikely(responses_pending(adapter))) |
559fb51b SB |
1633 | return 1; |
1634 | ||
3de00b89 | 1635 | netif_rx_complete(dev); |
559fb51b | 1636 | writel(adapter->sge->respQ.cidx, adapter->regs + A_SG_SLEEPING); |
8199d3a7 | 1637 | |
7fe26a60 | 1638 | return 0; |
3de00b89 | 1639 | |
559fb51b | 1640 | } |
8199d3a7 | 1641 | |
559fb51b SB |
1642 | /* |
1643 | * NAPI version of the main interrupt handler. | |
1644 | */ | |
7fe26a60 | 1645 | irqreturn_t t1_interrupt(int irq, void *data) |
559fb51b | 1646 | { |
559fb51b SB |
1647 | struct adapter *adapter = data; |
1648 | struct sge *sge = adapter->sge; | |
3de00b89 | 1649 | int handled; |
559fb51b | 1650 | |
3de00b89 SH |
1651 | if (likely(responses_pending(adapter))) { |
1652 | struct net_device *dev = sge->netdev; | |
559fb51b | 1653 | |
356bd146 | 1654 | writel(F_PL_INTR_SGE_DATA, adapter->regs + A_PL_CAUSE); |
7fe26a60 | 1655 | |
3de00b89 SH |
1656 | if (__netif_rx_schedule_prep(dev)) { |
1657 | if (process_pure_responses(adapter)) | |
1658 | __netif_rx_schedule(dev); | |
1659 | else { | |
1660 | /* no data, no NAPI needed */ | |
1661 | writel(sge->respQ.cidx, adapter->regs + A_SG_SLEEPING); | |
1662 | netif_poll_enable(dev); /* undo schedule_prep */ | |
7fe26a60 | 1663 | } |
7fe26a60 | 1664 | } |
3de00b89 SH |
1665 | return IRQ_HANDLED; |
1666 | } | |
1667 | ||
1668 | spin_lock(&adapter->async_lock); | |
1669 | handled = t1_slow_intr_handler(adapter); | |
1670 | spin_unlock(&adapter->async_lock); | |
7fe26a60 | 1671 | |
559fb51b SB |
1672 | if (!handled) |
1673 | sge->stats.unhandled_irqs++; | |
3de00b89 | 1674 | |
559fb51b SB |
1675 | return IRQ_RETVAL(handled != 0); |
1676 | } | |
8199d3a7 | 1677 | |
7fe26a60 | 1678 | #else |
559fb51b SB |
1679 | /* |
1680 | * Main interrupt handler, optimized assuming that we took a 'DATA' | |
1681 | * interrupt. | |
1682 | * | |
1683 | * 1. Clear the interrupt | |
1684 | * 2. Loop while we find valid descriptors and process them; accumulate | |
1685 | * information that can be processed after the loop | |
1686 | * 3. Tell the SGE at which index we stopped processing descriptors | |
1687 | * 4. Bookkeeping; free TX buffers, ring doorbell if there are any | |
1688 | * outstanding TX buffers waiting, replenish RX buffers, potentially | |
1689 | * reenable upper layers if they were turned off due to lack of TX | |
1690 | * resources which are available again. | |
1691 | * 5. If we took an interrupt, but no valid respQ descriptors was found we | |
1692 | * let the slow_intr_handler run and do error handling. | |
1693 | */ | |
7fe26a60 | 1694 | irqreturn_t t1_interrupt(int irq, void *cookie) |
559fb51b SB |
1695 | { |
1696 | int work_done; | |
559fb51b | 1697 | struct adapter *adapter = cookie; |
54d3e568 | 1698 | struct respQ *Q = &adapter->sge->respQ; |
8199d3a7 | 1699 | |
559fb51b | 1700 | spin_lock(&adapter->async_lock); |
8199d3a7 | 1701 | |
559fb51b | 1702 | writel(F_PL_INTR_SGE_DATA, adapter->regs + A_PL_CAUSE); |
8199d3a7 | 1703 | |
b9662d0e | 1704 | if (likely(responses_pending(adapter))) |
559fb51b SB |
1705 | work_done = process_responses(adapter, -1); |
1706 | else | |
1707 | work_done = t1_slow_intr_handler(adapter); | |
8199d3a7 | 1708 | |
559fb51b SB |
1709 | /* |
1710 | * The unconditional clearing of the PL_CAUSE above may have raced | |
1711 | * with DMA completion and the corresponding generation of a response | |
1712 | * to cause us to miss the resulting data interrupt. The next write | |
1713 | * is also unconditional to recover the missed interrupt and render | |
1714 | * this race harmless. | |
1715 | */ | |
1716 | writel(Q->cidx, adapter->regs + A_SG_SLEEPING); | |
1717 | ||
1718 | if (!work_done) | |
1719 | adapter->sge->stats.unhandled_irqs++; | |
1720 | spin_unlock(&adapter->async_lock); | |
1721 | return IRQ_RETVAL(work_done != 0); | |
1722 | } | |
7fe26a60 | 1723 | #endif |
559fb51b SB |
1724 | |
1725 | /* | |
1726 | * Enqueues the sk_buff onto the cmdQ[qid] and has hardware fetch it. | |
1727 | * | |
1728 | * The code figures out how many entries the sk_buff will require in the | |
1729 | * cmdQ and updates the cmdQ data structure with the state once the enqueue | |
1730 | * has complete. Then, it doesn't access the global structure anymore, but | |
1731 | * uses the corresponding fields on the stack. In conjuction with a spinlock | |
1732 | * around that code, we can make the function reentrant without holding the | |
1733 | * lock when we actually enqueue (which might be expensive, especially on | |
1734 | * architectures with IO MMUs). | |
1735 | * | |
1736 | * This runs with softirqs disabled. | |
1737 | */ | |
aa84505f SH |
1738 | static int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter, |
1739 | unsigned int qid, struct net_device *dev) | |
559fb51b SB |
1740 | { |
1741 | struct sge *sge = adapter->sge; | |
1742 | struct cmdQ *q = &sge->cmdQ[qid]; | |
f1d3d38a | 1743 | unsigned int credits, pidx, genbit, count, use_sched_skb = 0; |
559fb51b | 1744 | |
cabdfb37 SH |
1745 | if (!spin_trylock(&q->lock)) |
1746 | return NETDEV_TX_LOCKED; | |
1747 | ||
559fb51b SB |
1748 | reclaim_completed_tx(sge, q); |
1749 | ||
1750 | pidx = q->pidx; | |
1751 | credits = q->size - q->in_use; | |
1752 | count = 1 + skb_shinfo(skb)->nr_frags; | |
f1d3d38a | 1753 | count += compute_large_page_tx_descs(skb); |
559fb51b | 1754 | |
f1d3d38a SH |
1755 | /* Ethernet packet */ |
1756 | if (unlikely(credits < count)) { | |
1757 | if (!netif_queue_stopped(dev)) { | |
559fb51b SB |
1758 | netif_stop_queue(dev); |
1759 | set_bit(dev->if_port, &sge->stopped_tx_queues); | |
232a347a | 1760 | sge->stats.cmdQ_full[2]++; |
f1d3d38a SH |
1761 | CH_ERR("%s: Tx ring full while queue awake!\n", |
1762 | adapter->name); | |
8199d3a7 | 1763 | } |
f1d3d38a SH |
1764 | spin_unlock(&q->lock); |
1765 | return NETDEV_TX_BUSY; | |
1766 | } | |
1767 | ||
1768 | if (unlikely(credits - count < q->stop_thres)) { | |
1769 | netif_stop_queue(dev); | |
1770 | set_bit(dev->if_port, &sge->stopped_tx_queues); | |
1771 | sge->stats.cmdQ_full[2]++; | |
1772 | } | |
1773 | ||
1774 | /* T204 cmdQ0 skbs that are destined for a certain port have to go | |
1775 | * through the scheduler. | |
1776 | */ | |
1777 | if (sge->tx_sched && !qid && skb->dev) { | |
356bd146 | 1778 | use_sched: |
f1d3d38a SH |
1779 | use_sched_skb = 1; |
1780 | /* Note that the scheduler might return a different skb than | |
1781 | * the one passed in. | |
1782 | */ | |
1783 | skb = sched_skb(sge, skb, credits); | |
1784 | if (!skb) { | |
1785 | spin_unlock(&q->lock); | |
1786 | return NETDEV_TX_OK; | |
559fb51b | 1787 | } |
f1d3d38a SH |
1788 | pidx = q->pidx; |
1789 | count = 1 + skb_shinfo(skb)->nr_frags; | |
1790 | count += compute_large_page_tx_descs(skb); | |
559fb51b | 1791 | } |
f1d3d38a | 1792 | |
559fb51b SB |
1793 | q->in_use += count; |
1794 | genbit = q->genbit; | |
f1d3d38a | 1795 | pidx = q->pidx; |
559fb51b SB |
1796 | q->pidx += count; |
1797 | if (q->pidx >= q->size) { | |
1798 | q->pidx -= q->size; | |
1799 | q->genbit ^= 1; | |
8199d3a7 | 1800 | } |
559fb51b | 1801 | spin_unlock(&q->lock); |
8199d3a7 | 1802 | |
559fb51b | 1803 | write_tx_descs(adapter, skb, pidx, genbit, q); |
8199d3a7 CL |
1804 | |
1805 | /* | |
1806 | * We always ring the doorbell for cmdQ1. For cmdQ0, we only ring | |
1807 | * the doorbell if the Q is asleep. There is a natural race, where | |
1808 | * the hardware is going to sleep just after we checked, however, | |
1809 | * then the interrupt handler will detect the outstanding TX packet | |
1810 | * and ring the doorbell for us. | |
1811 | */ | |
559fb51b SB |
1812 | if (qid) |
1813 | doorbell_pio(adapter, F_CMDQ1_ENABLE); | |
1814 | else { | |
1815 | clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
1816 | if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) { | |
1817 | set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status); | |
1818 | writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); | |
1819 | } | |
8199d3a7 | 1820 | } |
f1d3d38a SH |
1821 | |
1822 | if (use_sched_skb) { | |
1823 | if (spin_trylock(&q->lock)) { | |
1824 | credits = q->size - q->in_use; | |
1825 | skb = NULL; | |
1826 | goto use_sched; | |
1827 | } | |
1828 | } | |
aa84505f | 1829 | return NETDEV_TX_OK; |
8199d3a7 CL |
1830 | } |
1831 | ||
1832 | #define MK_ETH_TYPE_MSS(type, mss) (((mss) & 0x3FFF) | ((type) << 14)) | |
1833 | ||
559fb51b SB |
1834 | /* |
1835 | * eth_hdr_len - return the length of an Ethernet header | |
1836 | * @data: pointer to the start of the Ethernet header | |
1837 | * | |
1838 | * Returns the length of an Ethernet header, including optional VLAN tag. | |
1839 | */ | |
1840 | static inline int eth_hdr_len(const void *data) | |
1841 | { | |
1842 | const struct ethhdr *e = data; | |
1843 | ||
1844 | return e->h_proto == htons(ETH_P_8021Q) ? VLAN_ETH_HLEN : ETH_HLEN; | |
1845 | } | |
1846 | ||
8199d3a7 CL |
1847 | /* |
1848 | * Adds the CPL header to the sk_buff and passes it to t1_sge_tx. | |
1849 | */ | |
1850 | int t1_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1851 | { | |
1852 | struct adapter *adapter = dev->priv; | |
559fb51b | 1853 | struct sge *sge = adapter->sge; |
56f643c2 | 1854 | struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[dev->if_port], smp_processor_id()); |
8199d3a7 | 1855 | struct cpl_tx_pkt *cpl; |
cabdfb37 SH |
1856 | struct sk_buff *orig_skb = skb; |
1857 | int ret; | |
8199d3a7 | 1858 | |
f1d3d38a SH |
1859 | if (skb->protocol == htons(ETH_P_CPL5)) |
1860 | goto send; | |
1861 | ||
1862 | if (skb_shinfo(skb)->gso_size) { | |
8199d3a7 CL |
1863 | int eth_type; |
1864 | struct cpl_tx_pkt_lso *hdr; | |
1865 | ||
56f643c2 | 1866 | ++st->tx_tso; |
559fb51b | 1867 | |
bbe735e4 | 1868 | eth_type = skb_network_offset(skb) == ETH_HLEN ? |
8199d3a7 CL |
1869 | CPL_ETH_II : CPL_ETH_II_VLAN; |
1870 | ||
1871 | hdr = (struct cpl_tx_pkt_lso *)skb_push(skb, sizeof(*hdr)); | |
1872 | hdr->opcode = CPL_TX_PKT_LSO; | |
1873 | hdr->ip_csum_dis = hdr->l4_csum_dis = 0; | |
eddc9ec5 | 1874 | hdr->ip_hdr_words = ip_hdr(skb)->ihl; |
8199d3a7 CL |
1875 | hdr->tcp_hdr_words = skb->h.th->doff; |
1876 | hdr->eth_type_mss = htons(MK_ETH_TYPE_MSS(eth_type, | |
f1d3d38a | 1877 | skb_shinfo(skb)->gso_size)); |
8199d3a7 CL |
1878 | hdr->len = htonl(skb->len - sizeof(*hdr)); |
1879 | cpl = (struct cpl_tx_pkt *)hdr; | |
f1d3d38a | 1880 | } else { |
8199d3a7 | 1881 | /* |
356bd146 | 1882 | * Packets shorter than ETH_HLEN can break the MAC, drop them |
559fb51b SB |
1883 | * early. Also, we may get oversized packets because some |
1884 | * parts of the kernel don't handle our unusual hard_header_len | |
1885 | * right, drop those too. | |
8199d3a7 | 1886 | */ |
559fb51b SB |
1887 | if (unlikely(skb->len < ETH_HLEN || |
1888 | skb->len > dev->mtu + eth_hdr_len(skb->data))) { | |
f1d3d38a SH |
1889 | pr_debug("%s: packet size %d hdr %d mtu%d\n", dev->name, |
1890 | skb->len, eth_hdr_len(skb->data), dev->mtu); | |
559fb51b | 1891 | dev_kfree_skb_any(skb); |
aa84505f | 1892 | return NETDEV_TX_OK; |
559fb51b SB |
1893 | } |
1894 | ||
1895 | /* | |
1896 | * We are using a non-standard hard_header_len and some kernel | |
1897 | * components, such as pktgen, do not handle it right. | |
1898 | * Complain when this happens but try to fix things up. | |
1899 | */ | |
f1d3d38a | 1900 | if (unlikely(skb_headroom(skb) < dev->hard_header_len - ETH_HLEN)) { |
f1d3d38a SH |
1901 | pr_debug("%s: headroom %d header_len %d\n", dev->name, |
1902 | skb_headroom(skb), dev->hard_header_len); | |
1903 | ||
559fb51b SB |
1904 | if (net_ratelimit()) |
1905 | printk(KERN_ERR "%s: inadequate headroom in " | |
1906 | "Tx packet\n", dev->name); | |
1907 | skb = skb_realloc_headroom(skb, sizeof(*cpl)); | |
1908 | dev_kfree_skb_any(orig_skb); | |
1909 | if (!skb) | |
aa84505f | 1910 | return NETDEV_TX_OK; |
559fb51b | 1911 | } |
8199d3a7 CL |
1912 | |
1913 | if (!(adapter->flags & UDP_CSUM_CAPABLE) && | |
84fa7933 | 1914 | skb->ip_summed == CHECKSUM_PARTIAL && |
eddc9ec5 | 1915 | ip_hdr(skb)->protocol == IPPROTO_UDP) { |
84fa7933 | 1916 | if (unlikely(skb_checksum_help(skb))) { |
f1d3d38a | 1917 | pr_debug("%s: unable to do udp checksum\n", dev->name); |
559fb51b | 1918 | dev_kfree_skb_any(skb); |
aa84505f | 1919 | return NETDEV_TX_OK; |
559fb51b | 1920 | } |
f1d3d38a | 1921 | } |
8199d3a7 | 1922 | |
559fb51b SB |
1923 | /* Hmmm, assuming to catch the gratious arp... and we'll use |
1924 | * it to flush out stuck espi packets... | |
f1d3d38a SH |
1925 | */ |
1926 | if ((unlikely(!adapter->sge->espibug_skb[dev->if_port]))) { | |
8199d3a7 | 1927 | if (skb->protocol == htons(ETH_P_ARP) && |
559fb51b | 1928 | skb->nh.arph->ar_op == htons(ARPOP_REQUEST)) { |
f1d3d38a | 1929 | adapter->sge->espibug_skb[dev->if_port] = skb; |
559fb51b SB |
1930 | /* We want to re-use this skb later. We |
1931 | * simply bump the reference count and it | |
1932 | * will not be freed... | |
1933 | */ | |
1934 | skb = skb_get(skb); | |
1935 | } | |
8199d3a7 | 1936 | } |
559fb51b SB |
1937 | |
1938 | cpl = (struct cpl_tx_pkt *)__skb_push(skb, sizeof(*cpl)); | |
8199d3a7 CL |
1939 | cpl->opcode = CPL_TX_PKT; |
1940 | cpl->ip_csum_dis = 1; /* SW calculates IP csum */ | |
84fa7933 | 1941 | cpl->l4_csum_dis = skb->ip_summed == CHECKSUM_PARTIAL ? 0 : 1; |
8199d3a7 | 1942 | /* the length field isn't used so don't bother setting it */ |
559fb51b | 1943 | |
84fa7933 | 1944 | st->tx_cso += (skb->ip_summed == CHECKSUM_PARTIAL); |
8199d3a7 CL |
1945 | } |
1946 | cpl->iff = dev->if_port; | |
1947 | ||
1948 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) | |
1949 | if (adapter->vlan_grp && vlan_tx_tag_present(skb)) { | |
1950 | cpl->vlan_valid = 1; | |
1951 | cpl->vlan = htons(vlan_tx_tag_get(skb)); | |
559fb51b | 1952 | st->vlan_insert++; |
8199d3a7 CL |
1953 | } else |
1954 | #endif | |
1955 | cpl->vlan_valid = 0; | |
1956 | ||
f1d3d38a | 1957 | send: |
56f643c2 | 1958 | st->tx_packets++; |
8199d3a7 | 1959 | dev->trans_start = jiffies; |
cabdfb37 SH |
1960 | ret = t1_sge_tx(skb, adapter, 0, dev); |
1961 | ||
1962 | /* If transmit busy, and we reallocated skb's due to headroom limit, | |
1963 | * then silently discard to avoid leak. | |
1964 | */ | |
1965 | if (unlikely(ret != NETDEV_TX_OK && skb != orig_skb)) { | |
356bd146 | 1966 | dev_kfree_skb_any(skb); |
cabdfb37 | 1967 | ret = NETDEV_TX_OK; |
356bd146 | 1968 | } |
cabdfb37 | 1969 | return ret; |
559fb51b | 1970 | } |
8199d3a7 | 1971 | |
559fb51b SB |
1972 | /* |
1973 | * Callback for the Tx buffer reclaim timer. Runs with softirqs disabled. | |
1974 | */ | |
1975 | static void sge_tx_reclaim_cb(unsigned long data) | |
1976 | { | |
1977 | int i; | |
1978 | struct sge *sge = (struct sge *)data; | |
1979 | ||
1980 | for (i = 0; i < SGE_CMDQ_N; ++i) { | |
1981 | struct cmdQ *q = &sge->cmdQ[i]; | |
1982 | ||
1983 | if (!spin_trylock(&q->lock)) | |
1984 | continue; | |
8199d3a7 | 1985 | |
559fb51b | 1986 | reclaim_completed_tx(sge, q); |
f1d3d38a SH |
1987 | if (i == 0 && q->in_use) { /* flush pending credits */ |
1988 | writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL); | |
1989 | } | |
559fb51b SB |
1990 | spin_unlock(&q->lock); |
1991 | } | |
1992 | mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); | |
1993 | } | |
1994 | ||
1995 | /* | |
1996 | * Propagate changes of the SGE coalescing parameters to the HW. | |
1997 | */ | |
1998 | int t1_sge_set_coalesce_params(struct sge *sge, struct sge_params *p) | |
1999 | { | |
559fb51b SB |
2000 | sge->fixed_intrtimer = p->rx_coalesce_usecs * |
2001 | core_ticks_per_usec(sge->adapter); | |
2002 | writel(sge->fixed_intrtimer, sge->adapter->regs + A_SG_INTRTIMER); | |
8199d3a7 CL |
2003 | return 0; |
2004 | } | |
2005 | ||
559fb51b SB |
2006 | /* |
2007 | * Allocates both RX and TX resources and configures the SGE. However, | |
2008 | * the hardware is not enabled yet. | |
2009 | */ | |
2010 | int t1_sge_configure(struct sge *sge, struct sge_params *p) | |
8199d3a7 | 2011 | { |
559fb51b SB |
2012 | if (alloc_rx_resources(sge, p)) |
2013 | return -ENOMEM; | |
2014 | if (alloc_tx_resources(sge, p)) { | |
2015 | free_rx_resources(sge); | |
2016 | return -ENOMEM; | |
2017 | } | |
2018 | configure_sge(sge, p); | |
2019 | ||
2020 | /* | |
2021 | * Now that we have sized the free lists calculate the payload | |
2022 | * capacity of the large buffers. Other parts of the driver use | |
2023 | * this to set the max offload coalescing size so that RX packets | |
2024 | * do not overflow our large buffers. | |
2025 | */ | |
2026 | p->large_buf_capacity = jumbo_payload_capacity(sge); | |
2027 | return 0; | |
2028 | } | |
8199d3a7 | 2029 | |
559fb51b SB |
2030 | /* |
2031 | * Disables the DMA engine. | |
2032 | */ | |
2033 | void t1_sge_stop(struct sge *sge) | |
2034 | { | |
f1d3d38a | 2035 | int i; |
559fb51b | 2036 | writel(0, sge->adapter->regs + A_SG_CONTROL); |
f1d3d38a SH |
2037 | readl(sge->adapter->regs + A_SG_CONTROL); /* flush */ |
2038 | ||
559fb51b SB |
2039 | if (is_T2(sge->adapter)) |
2040 | del_timer_sync(&sge->espibug_timer); | |
f1d3d38a | 2041 | |
559fb51b | 2042 | del_timer_sync(&sge->tx_reclaim_timer); |
f1d3d38a SH |
2043 | if (sge->tx_sched) |
2044 | tx_sched_stop(sge); | |
2045 | ||
2046 | for (i = 0; i < MAX_NPORTS; i++) | |
2047 | if (sge->espibug_skb[i]) | |
2048 | kfree_skb(sge->espibug_skb[i]); | |
8199d3a7 CL |
2049 | } |
2050 | ||
559fb51b SB |
2051 | /* |
2052 | * Enables the DMA engine. | |
2053 | */ | |
2054 | void t1_sge_start(struct sge *sge) | |
8199d3a7 | 2055 | { |
559fb51b SB |
2056 | refill_free_list(sge, &sge->freelQ[0]); |
2057 | refill_free_list(sge, &sge->freelQ[1]); | |
2058 | ||
2059 | writel(sge->sge_control, sge->adapter->regs + A_SG_CONTROL); | |
2060 | doorbell_pio(sge->adapter, F_FL0_ENABLE | F_FL1_ENABLE); | |
f1d3d38a | 2061 | readl(sge->adapter->regs + A_SG_CONTROL); /* flush */ |
559fb51b SB |
2062 | |
2063 | mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); | |
2064 | ||
f1d3d38a | 2065 | if (is_T2(sge->adapter)) |
559fb51b SB |
2066 | mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); |
2067 | } | |
2068 | ||
2069 | /* | |
2070 | * Callback for the T2 ESPI 'stuck packet feature' workaorund | |
2071 | */ | |
f1d3d38a | 2072 | static void espibug_workaround_t204(unsigned long data) |
559fb51b SB |
2073 | { |
2074 | struct adapter *adapter = (struct adapter *)data; | |
8199d3a7 | 2075 | struct sge *sge = adapter->sge; |
f1d3d38a SH |
2076 | unsigned int nports = adapter->params.nports; |
2077 | u32 seop[MAX_NPORTS]; | |
8199d3a7 | 2078 | |
f1d3d38a SH |
2079 | if (adapter->open_device_map & PORT_MASK) { |
2080 | int i; | |
356bd146 FR |
2081 | |
2082 | if (t1_espi_get_mon_t204(adapter, &(seop[0]), 0) < 0) | |
f1d3d38a | 2083 | return; |
356bd146 | 2084 | |
f1d3d38a | 2085 | for (i = 0; i < nports; i++) { |
356bd146 FR |
2086 | struct sk_buff *skb = sge->espibug_skb[i]; |
2087 | ||
2088 | if (!netif_running(adapter->port[i].dev) || | |
2089 | netif_queue_stopped(adapter->port[i].dev) || | |
2090 | !seop[i] || ((seop[i] & 0xfff) != 0) || !skb) | |
2091 | continue; | |
2092 | ||
2093 | if (!skb->cb[0]) { | |
2094 | u8 ch_mac_addr[ETH_ALEN] = { | |
2095 | 0x0, 0x7, 0x43, 0x0, 0x0, 0x0 | |
2096 | }; | |
2097 | ||
2098 | memcpy(skb->data + sizeof(struct cpl_tx_pkt), | |
2099 | ch_mac_addr, ETH_ALEN); | |
2100 | memcpy(skb->data + skb->len - 10, | |
2101 | ch_mac_addr, ETH_ALEN); | |
2102 | skb->cb[0] = 0xff; | |
559fb51b | 2103 | } |
356bd146 FR |
2104 | |
2105 | /* bump the reference count to avoid freeing of | |
2106 | * the skb once the DMA has completed. | |
2107 | */ | |
2108 | skb = skb_get(skb); | |
2109 | t1_sge_tx(skb, adapter, 0, adapter->port[i].dev); | |
559fb51b SB |
2110 | } |
2111 | } | |
2112 | mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); | |
8199d3a7 CL |
2113 | } |
2114 | ||
f1d3d38a SH |
2115 | static void espibug_workaround(unsigned long data) |
2116 | { | |
2117 | struct adapter *adapter = (struct adapter *)data; | |
2118 | struct sge *sge = adapter->sge; | |
2119 | ||
2120 | if (netif_running(adapter->port[0].dev)) { | |
2121 | struct sk_buff *skb = sge->espibug_skb[0]; | |
2122 | u32 seop = t1_espi_get_mon(adapter, 0x930, 0); | |
2123 | ||
2124 | if ((seop & 0xfff0fff) == 0xfff && skb) { | |
2125 | if (!skb->cb[0]) { | |
2126 | u8 ch_mac_addr[ETH_ALEN] = | |
2127 | {0x0, 0x7, 0x43, 0x0, 0x0, 0x0}; | |
2128 | memcpy(skb->data + sizeof(struct cpl_tx_pkt), | |
2129 | ch_mac_addr, ETH_ALEN); | |
2130 | memcpy(skb->data + skb->len - 10, ch_mac_addr, | |
2131 | ETH_ALEN); | |
2132 | skb->cb[0] = 0xff; | |
2133 | } | |
2134 | ||
2135 | /* bump the reference count to avoid freeing of the | |
2136 | * skb once the DMA has completed. | |
2137 | */ | |
2138 | skb = skb_get(skb); | |
2139 | t1_sge_tx(skb, adapter, 0, adapter->port[0].dev); | |
2140 | } | |
2141 | } | |
2142 | mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); | |
2143 | } | |
2144 | ||
559fb51b SB |
2145 | /* |
2146 | * Creates a t1_sge structure and returns suggested resource parameters. | |
2147 | */ | |
2148 | struct sge * __devinit t1_sge_create(struct adapter *adapter, | |
2149 | struct sge_params *p) | |
2150 | { | |
cbee9f91 | 2151 | struct sge *sge = kzalloc(sizeof(*sge), GFP_KERNEL); |
56f643c2 | 2152 | int i; |
559fb51b SB |
2153 | |
2154 | if (!sge) | |
2155 | return NULL; | |
559fb51b SB |
2156 | |
2157 | sge->adapter = adapter; | |
2158 | sge->netdev = adapter->port[0].dev; | |
2159 | sge->rx_pkt_pad = t1_is_T1B(adapter) ? 0 : 2; | |
2160 | sge->jumbo_fl = t1_is_T1B(adapter) ? 1 : 0; | |
2161 | ||
56f643c2 SH |
2162 | for_each_port(adapter, i) { |
2163 | sge->port_stats[i] = alloc_percpu(struct sge_port_stats); | |
2164 | if (!sge->port_stats[i]) | |
2165 | goto nomem_port; | |
2166 | } | |
2167 | ||
559fb51b SB |
2168 | init_timer(&sge->tx_reclaim_timer); |
2169 | sge->tx_reclaim_timer.data = (unsigned long)sge; | |
2170 | sge->tx_reclaim_timer.function = sge_tx_reclaim_cb; | |
2171 | ||
2172 | if (is_T2(sge->adapter)) { | |
2173 | init_timer(&sge->espibug_timer); | |
f1d3d38a SH |
2174 | |
2175 | if (adapter->params.nports > 1) { | |
2176 | tx_sched_init(sge); | |
2177 | sge->espibug_timer.function = espibug_workaround_t204; | |
d7487421 | 2178 | } else |
f1d3d38a | 2179 | sge->espibug_timer.function = espibug_workaround; |
559fb51b | 2180 | sge->espibug_timer.data = (unsigned long)sge->adapter; |
f1d3d38a | 2181 | |
559fb51b | 2182 | sge->espibug_timeout = 1; |
f1d3d38a SH |
2183 | /* for T204, every 10ms */ |
2184 | if (adapter->params.nports > 1) | |
2185 | sge->espibug_timeout = HZ/100; | |
559fb51b | 2186 | } |
356bd146 | 2187 | |
559fb51b SB |
2188 | |
2189 | p->cmdQ_size[0] = SGE_CMDQ0_E_N; | |
2190 | p->cmdQ_size[1] = SGE_CMDQ1_E_N; | |
2191 | p->freelQ_size[!sge->jumbo_fl] = SGE_FREEL_SIZE; | |
2192 | p->freelQ_size[sge->jumbo_fl] = SGE_JUMBO_FREEL_SIZE; | |
f1d3d38a SH |
2193 | if (sge->tx_sched) { |
2194 | if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204) | |
2195 | p->rx_coalesce_usecs = 15; | |
2196 | else | |
2197 | p->rx_coalesce_usecs = 50; | |
2198 | } else | |
2199 | p->rx_coalesce_usecs = 50; | |
2200 | ||
559fb51b SB |
2201 | p->coalesce_enable = 0; |
2202 | p->sample_interval_usecs = 0; | |
559fb51b SB |
2203 | |
2204 | return sge; | |
56f643c2 SH |
2205 | nomem_port: |
2206 | while (i >= 0) { | |
2207 | free_percpu(sge->port_stats[i]); | |
2208 | --i; | |
2209 | } | |
2210 | kfree(sge); | |
2211 | return NULL; | |
2212 | ||
559fb51b | 2213 | } |